Morrow SuperRAM 24K
Contents
1. ORIENTATION When this manual refers to the bottom of the circuit board it means the edge with the gold 5 100 edge connectors Right and left assume a view from the component side of the board which has the silk screened parts legend embossed over the solder mask All IC sockets have their pins numbered have a 45 degree angle across the corner of pin one or have a notch at the end which indicates pin one On the 24K Memory Master all sockets and all ICs have pin 1 closest to the bottom left corner of the circuit board The 1 8 and 39 microfarad tantalum capacitors are polarized The 1 8 microfarad capacitor s positive end is identified by a circular tit where the lead enters the body of the housing A red band identifies the positive end of the 39 microfarad device The legend on the circuit board identifies the positive lead of these axial parts with a sign The by pass capacitors which are identified on the legend by an asterisk enclosed by an oval are not polarized The three DIP switch arrays to be positioned so that the letters and numbers stamped on them are right side up that is paddle 1 should be to the left and paddle 8 on the right Assembly Instructions The SIP resistor packs historically prone to being inserted backwards should have their orienting dot nearest the white dot on the legend of the board the 24K Memory Master board this turns out to be to the left for all three SIP packs2. 0
3. EXAMINE THE BOARD Visually examine the circuit board for any trace opens or shorts concentrated five minute scrutiny will uncover most trace defects Several hours of scattered unconcentrated work generally won t reveal anything Take special care that no short or opens exist on those areas of the circuit board that will be covered by IC sockets Ohm out any suspicious looking traces for either shorts or discontinuity as appropriate Return at once any bare board found to be flawed Such boards will be replaced under warranty SOLDERING AND SOLDER IRONS The most desirable soldering tool for a complex electronic kit is a constant temperature iron with an element regulated at 650 degrees F The tip should be fine so that it can be brought into close contact with the pads of the circuit board This type of soldering iron is available from Weller or Unger to name just two and should be a part of any electronics shop There are three important soldering rules that should be followed when building this kit 1 Do not use an iron that is too cold less than 600 degrees F or too hot more that 750 degrees F 2 Do not hold the iron against a pad for more than about six seconds at a time 3 Do not apply excessive amounts of solder The recommended procedure for components to the circuit board is as follows 1 Bring the iron in contact with BOTH the component lead AND the pad 2 Apply a SMALL amount of solder at
4. switch and paddle 4 is the OFF switch In this case ON means that the board will be active on Power On Clear hereafter called simply POC OFF means the board will come up inactive on For the ON option set paddle 3 to the on position and paddle 4 to the off position For the OFF option set paddle 3 to the off position and paddle 4 to the on position no case should paddles 3 and 4 of the DIP switch at position 8A be set to the same position The figure below depicts the ON and OFF switches of DIP switch 8A ON OFF OPTION SWITCH Paddle 3 in on on Paddle 4 in on pesition ON 3 4 position OFF beard active on POC off beard inactive on POC 8A PADDLE 3 MUST NOT BE IN THE SAME POSITION AS PADDLE 4 Operating Instructions BOARD SELECTION BY I O ADDRESS BANK SELECTION The purpose of Bank Selection is to allow more memory in a system than the CPU can normally address This is accomplished by assigning a board not only a memory address somewhere within the 64K range of addressable memory but also an I O port number between and 255 Thus two boards can share the same memory address yet a different I O address If system software Scheme takes care to disable one board by outputting an appropriate byte to the board s I O port number before enabling another board again by outputting the proper byte to its port number many memory boards can occupy the same me
5. 4 of DIP switch 8A off 3 Set the board to enable write operations by placing paddles 5 and 6 and 7 of DIP switch 8A to their on positions 4 Set the board to ignore PHANTOM by turning paddle 1 of switch 8A to the off position 5 Set the board to I O port 40H 1000 by setting paddle 2 of DIP switch 7A to on and the rest of the paddles of DIP switch 7A to off 6 Do not place the slid on jumper anywhere on the 16 pin jumper block TEST 1 Memory Addressing and Write Protection With the switch paddles set as indicated above and with the power off place the Memory Master in a system that has no memory eccupying the first 24K Power the system up With a front panel one that MUST generate the S 100 status signal SWO during memory deposits or a monitor examine location 0000 write H in this location and re examine it to be sure that it now contains 09 Now deposit 3770 in this same location and read it back Now set paddle 5 of DIP switch 8A to off and attempt to change the FF in location 0000H to another number you should not be able to alter this location now Set 15 System Check out paddle 5 of 8A back to on Verify that location 0909H can once again be altered Repeat the above procedure first at location 2000 using paddle 6 of 8A and then again at location 4000H with paddle 7 of 8A TEST 2 Bank Selection Place the slide on jumper across the two pins labled DATA9 on the 16
6. a slash in the Parts List DO NOT INSERT ANY INTEGRATED CIRCUITS AT THIS TIME Lr CE Da PA PPE PRE A PTO PS eA EM EP EA SOAS Before inserting in its socket the following check out procedure must be performed 1 Re check the back of the circuit board for solder shorts and bridged connections and for pins of IC sockets that have not been soldered These unsoldered pins can cause problems which are often intermittant and usually hard to find 2 Re check components for orientation Also make sure all components to be soldered have been soldered 3 With an Ohm Meter check for shorts between the 5 Volt lead of the 7805 regulators and ground The output pins of the regulators are on the right side of the part Check for shorts between 5 100 1 or 51 8V and ground On the 5 100 bus ground is on pins 50 and 100 4 Place the board WITHOUT ICs into a bus slot of an other wise empty system and power up the system In case of smoke power down immediately and investigate 5 With a VOM or scope check the regulators for 5V Next check for 5V and ground on all IC sockets If everything is OK power down and proceed to IC insertion IC INSERTION If an IC insertion tool is not available IC leads should be Straightened a ROW at a time not by the individual PIN edge of a stright sided table is an excellent device for this purpose Hold the IC by the plastic case place one row of legs agai
7. circuit board w silk screen legend 330 Ohm 1 4 watt resistors 3 3 k Ohm SIP resistor packs Disk by pass capacitors may vary in value from 01 to 1 microfarads depending on current supplies 1 8 microfarad tantalum capacitors 39 microfarad tantalum capacitors 8 position DIP switches Heat sinks 6 32 machine nuts amp screws 16 pin jumper block Slide on jumper 14 low profile sockets l6 pin low profile sockets 18 pin low profile sockets 7885 positive 5 volt regulators 741 500 quad 2 input NAND gate 74 502 quad 2 input NOR gate 74LS04 hex inverter 74LS32 quad 2 input OR gate 741574 dual d type flip flop 74115138 1 of 8 decoder 74LS266 quad Exclusive Nor gate 745288 6188 6331 826123 28 x 32 PROM 74LS367 hex Tri state buffer 5257 4K x 1 NMOS Static RAM 9K 7F 4K 5K 6K 9F 7K 9H 8F 7B 8B 9B 7D 9D 8D 7H 8H 8K 1B through 6J ASSEMBLY INSTRUCTIONS WARNING IMPROPER ASSEMBLY OF THIS KIT WILL VOID THE WARRANTY READ THESE INSTRUCTIONS CAREFULLY BEFORE ATTEMPTING TO CONSTRUCT THIS KIT INVENTORY Make sure that all the parts listed in the PARTS LIST have been included Notify Thinker Toys immediately if any parts are missing Also quickly return all extra parts USE SOCKETS Sockets are provided for every IC on the 24K Memory Master REPAIR WORK WILL BE PERFORMED RETURNED BOARD WITH ANY IC SOLDERED DIRECTLY TO THE CIRCUIT BOARD
8. F CURRENT BLOCK SAVE INITIAL ADDRESS GET TEST WORD STORE COMPLEMENT ADDRESS GET TEST WORD STORE COMPLEMENT amp DECREMENT ADDRESS RECOVER INITIAL ADDRESS GET TEST WORD COMPARE COMPLEMENT ADDRESS GET TEST WORD COMPARE COMPLEMENT amp DECREMENT ADDRESS ADVANCE THE BLOCK DECREMENT BLOCK COUNT CALCULATE NEW BASE FOR TEST WORD INCREMENT CYCLE COUNT GET LOWER BYTE OF ADDRESS ROTATE SHIFT ADD HIGHER BYTE OF ADDR ADD BASE SAVE TEST WORD YYY YYY YYY 123 124 126 127 130 132 133 134 137 140 141 _ 142 143 144 145 146 147 150 151 154 155 156 157 160 161 162 163 164 165 166 167 171 173 175 174 356 147 175 356 157 311 315 053 300 170 075 274 311 345 305 325 365 303 361 321 301 341 311 000 000 000 000 000 000 000 000 000 000 017 377 123 151 YYY 000 000 000 000 COMP INCR ERROR STALL TABLE STACK MOV XRI MOV MOV XRI MOV RET CALL DCX RNZ MOV DCR CMP RET PUSH PUSH PUSH PUSH JMP POP POP 170 H A A L 377Q COMP rz PSW STALL PSW COMPLEMENT THE UPPER BYTE ADDRESS WITH RESPECT TO MEM SIZE COMPLEMENT THE LOWER BYTE OF THE ADDRESS RESTORE ADDR TO NORMAL SIZE DECREMENT TEST IF LOWER BYTE ZERO TEST UPPER BYTE EQUAL TO BLOCK BOUNDARY SAVE ERROR ADDRESS SAVE CURRENT BLOCK SAVE TEST WORD SAVE E
9. RROR BITS DYNAMIC HALT RESTORE THE STATE OF THE CPU FLAGS ACC ONES ARE ERROR BITS E CURRENT RANDOM OFFSET D CURRENT TEST WORD C CURRENT BLOCK COUNT B CURRENT BLOCK PAGE HL ERROR ADDRESS RETURN ADDRESS CYCLE COUNT YY YY YY 7D 00 40 FF 53 4c 5 12 65 4C 65 24 OB 87 06 MEMORY TEST PROGRAM FOR 4 NMOS RAMS 00 07 YY YY YY YY YY YY YY YY YT YY Xx START LXI LXI NEWCYL PUSH MVI MVI LOOP LXI MOV ADD MOV PUSH CALL MOV CALL CALL MOV CALL JNZ POP WRITE READ XRA CNZ CALL CALL CNZ CALL JNZ MVI ADD MOV DCR JNZ MOV ADI MOV POP INX JMP TWORD MOV RLC ADD ADD ADD MOV RET 20 SP STACK B 0 B B PAGENO C BLKCNT H 7 377Q A B H TWORD M A COMP TWORD MA INCR WRITE H TWORD M ERROR COMP TWORD M ERROR INCR READ A 20Q B C LOOP A E 135 E A B B NEWCYL A L E YY YY YY OF FF 55 XY 69 YY COMP INCR ERROR STALL TABLE STACK MOV XRI MOV MOV XRI MOV RET CALL 21 170 3770 L A COMP H H H B D PSW STALL PSW D B H 0 FLAGS 0 ACC ONES ARE ERROR BITS 0 E CURRENT RANDOM OFFSET 0 D CURRENT TEST WORD 0 C BLOCKS LEFT TO TEST 0 CURRENT BLOCK PAGE 0 HL ERROR ADDRESS 0 RETURN ADDRESS 0 CYCLE COUNT
10. User s Manual SuperRam tm 24K MEMORY MASTER tm lntroducElolhssw s owe Operating Instr ctl nS 4 9 5 4 4 2 Memory 4 2 Memory Addressing 1 3 Write PLO CECE LO Mia Board Selection by I O Address 5 Board Selection by Data 6 Phantom 1 7 Summary of Switch 5 7 Parts 15 6 Assembly 5 9 Parts 1 lt 11 1 912 System 2 15 Memory DlagqnosStic cccccccccccescvessscsseceol 5 44 5 6646 4 5 54 466 22 Copyright 1979 Morrow 5221 CENTRAL AVENUE RICHMOND CA 94804 415 524 2101 MORROW DESIGNS User s Manual 24K MEMORY MASTER tm INTRODUCTION The Thinker Toys 24K Memory Master tm is our second entry into the field of bank select S 100 memory products Using the popular 5257 AK x 1 static RAM memory chip with an access time which allows us to guarantee operation with 4 2 Z 80 systems and 5MHz 8085 systems the 24K Memory Master is compatable with most popular S 100 bank select software This versatile board can be Switched to become selected or deselec
11. e toward the bottom of the circuit board when the part is installed Clip the excess leads from the parts Install and solder the three switch arrays Switch 1 is to be positioned to the left when the part is installed Install solder and clip the leads of the eighteen by pass capacitors whose positions are identified by an oval with an asterisk in the middle Install and solder the 16 pin jumper block just to the right of the RAM array Its position is marked by a rectangular outline with DATA at the top and DATA7 at the bottom Make sure that the shorter pins pass through the board Bend the leads of the four 7805 regulators and insert them in the circuit board Place a heat sink between the 7805 and the board Work a screw from the back of the board through the board heat sink and regulator in that order and hand tighten onto a nut at the top of the regulator Solder the leads and adjust the heat sinks so that they are square with the board Finally tighten the nut and screw 12 Parts Installation CLEAN AND EXAMINE THE BOARD Use flux cleaner to remove solder rosin residue Examine the circuit board carefully for shorts solder bridges or pins on Sockets that have not been soldered HOW TO FIND WHERE TO PLACE PARTS For parts placement please see the silk screened legend on the printed circuit board ICs may vary from those marked on the legend if they are listed as alternate ICs following
12. ignment scheme is illustrated in the figure below I O PORT ADDRESSING SWITCH 7 AD7 AD6 AD5 4 AD3 AD2 ADO 1 2 3 4 5 6 7 8 off A paddle in the off position is to be taken as a cleared bit while a paddle in the on position sets the bit Thus if all the paddles of the switch are turned to the off position would be the I O port number assigned to the Memory Master board When all the paddles of DIP switch 7A are in the on position 255 FF Hex or 377 Octal is the I O port number which is used to Operating Instructions select or deselect the board To set the board to say device 40H the following settings should be used 1 2 3 4 5 6 7 8 7 BOARD SELECTION BY DATA BANK SELECTION Once the I O port number of the Memory Master board has been determined there remains the selection of the data bit which will activate or deactivate the board during OUT instructions to the selected port There is a 16 pin jumber block consisting of two columns of 8 pins each located between columns 6 and 7 of the Memory Master circuit board Vertically it straddles rows and D This jumper block is used to assign a data bit to the bank selection logic on the board silk screened legend on the circuit board names the top pair of pins and the bottom pair 7 By jumpering one of the horizontal pairs of pins with the slide on jumper included with the Memory Ma
13. mory space without causing any conflict With the 24K Memory Master two assignments must be made for each board in order to operate under a bank select scheme First an I O port number must be decided upon and second a data bit within that port must be chosen to act as a switch to enable the board or disable it when a byte is written to the I O port which is assigned to the board If for example a board is assigned I O port number 40H and further assigned data bit within that port then the board will be activated when bit 0 of the CPU s register is on and an OUT 49H instruction is issued by the CPU Conversely the same board will be disabled when the CPU executes an OUT 48H instruction and bit of the A register is off The A register is the CPU s accumulater either case the board will remain selected or deselected until the CPU executes an OUT 40H instruction again and changes the board s selection state or a Power On Clear takes place will select or deselect the board according to the setting of paddles 3 and 4 of DIP switch 8A as described above DIP switch 7A the leftmost switch on the 24K Memory Master board controls the selection of the I O port number to which the board is assigned Paddles 1 through 8 on this switch may be thought of as representing the 8 address bits of the I O port with paddle 1 representing bit 7 paddle 2 representing bit 6 and so on through paddle 8 representing bit 0 This ass
14. ng return it as soon as possible for service 17 YYY YYY YYY 000 003 006 007 011 013 016 017 020 021 022 025 026 031 034 035 040 043 044 047 050 053 056 061 062 065 070 073 075 076 077 100 103 104 106 107 110 111 114 115 116 117 120 121 122 061 001 305 006 016 041 170 204 147 345 315 167 315 315 167 315 302 341 315 256 304 315 315 256 304 SIS 302 076 200 107 015 302 173 306 137 301 003 303 175 007 207 204 203 127 311 175 000 100 004 377 114 123 114 134 022 114 145 123 114 145 134 044 020 013 207 006 MEMORY TEST PROGRAM FOR 4K NMOS RAMS YYY 000 007 YYY YYY YYY YYY YYY YYY YYY YYY YYY START NEWCYL LOOP WRITE READ TWORD Octal LXI SP STACK LXI B 0 PUSH B MVI B PAGENO MVI C BLKCNT LXI H 7 377Q MOV A B ADD H MOV PUSH H CALL gt TWORD MOV M A CALL COMP CALL TWORD MOV M A CALL INCR JNZ WRITE POP H CALL TWORD XRA M CNZ ERROR CALL COMP CALL TWORD XRA M CNZ ERROR CALL INCR JNZ READ MVI A 20Q ADD MOV B A DCR C JNZ LOOP MOV A E ADI 135 MOV EA POP B INX B JMP NEWCYL MOV A L RLC ADD ADD H ADD E MOV DA RET INITIALIZE STACK POINTER INITIALIZE CYCLE COUNT UPDATE CYCLE COUNT STARTING ADDR OF TEST MEM OF 4K BLOCKS TO TEST HALF SIZE OF MEMORY 1 CALCULATE MIDDLE O
15. nst a flat surface and push very slightly Repeat with the opposite row Continue this procedure until the legs of the IC can be put into its socket with a minimum of effort 13 Parts Installation When the IC is inserted into its socket take care that one or more pins are NOT BENT UNDERNEATH ITS PLASTIC PACK This is a very common occurance and can escape even a fairly careful visual inspection BENT IC PINS ARE THE MOST COMMON BOARD FAULT IN KITS THAT ARE BUILT IN THE FIELD If IC pins are bent under the pack during insertion use a pair of long nose pliers to straighten them and try again When an IC must be removed from its socket use an IC remover a test clip another must for any electronics shop or a small enough Screw driver so that its blade can fit between the plastic case of the IC and the socket DO NOT ATTEMPT TO REMOVE AN IC WITH YOUR FINGERS Very often the pins will bend and cut a finger as the IC pops out of its socket Once the ICs have been inserted check once again for bent pins Then check twice that all the ICs have been inserted into their sockets with the proper orientation pin 1 must be pointed toward the lower left of the circuit board Upside down ICs are usually destroyed upon power up IF FOR ANY REASON IT BECOMES NECESSARY TO REMOVE A PART THAT HAS BEEN SOLDERED TO THE CIRCUIT BOARD CLIP ALL THE LEADS OF THE PART BEFORE REMOVING THIS WILL REDUCE THE CHANCE OF LIFTING PADS POWER UP If all pre
16. pin jumper block With a 0 the CPU s accumulator execute an OUT 40H command You should now have lost access to the Memory Master board Now execute an OUT 40H command with lin the CPU s accumulator The Memory Master should now be once again accessable TEST 3 ON OFF With a jumper still across DATA of the 16 pin jumper block make sure that you can still access the board Now turn off the power and back on again and again verify that the board can be accessed Next DIP switch 8A turn paddle 3 off and turn paddle 4 on Power down and power back up again The Memory Master should be disabled Execute an OUT 49H instruction with a l in the CPU s accumulator This should reactivate the Memory Master This completes the static system tests The following pages contain a full fleged memory diagnostic 16 MEMORY DIAGNOSTIC The memory test described below was designed by Phil Meads of William Brobeck Associates to exercise the most sensitive circuitry of the memory chips the address buffers The test starts from the middle and works its way outward alternately to the top and bottom of memory This type of test inverts the address lines more often than sequential ones This continual inversion process punishes and eventually breaks down weak or faulty address buffers in the device USING THE TEST The test itself must be placed in an area which is different than the location of the board s to be
17. re the address selection switches Each of these 9 paddles either grounds when set to on or pulls high when set to off one input of 74LS266 Exclusive Nor gate The other input is one of the three address lines A13 to 15 buffered and inverted by 74LS 4 s Sets of three of these 74LS266 equality gates will select their respective 8K memory block if and only if the S 100 address lines A13 to A15 exactly correspond to the setting of the appropriate paddles of the DIP switches Thus if the last three paddles of DIP switch 9A are all set to off or high then the inverted address lines 13 to 15 must also be high meaning that the actual address lines are low in order to select block C In this case selection will only occur when memory between H and lFFFH is being selected The diagram below depicts memory selection switches 8A and 9A and shows the correspondence between the paddles and the three 8K blocks of memory which they govern BLOCK AN BLOCK B NV BLOCK C N 15 14 A13 15 14 A13 15 14 A13 on I right most 8 1 2 3 4 5 6 7 8 switch of off top row position 8A 9A Operating Instructions MEMORY ADDRESSING TABLE The following table shows the relationship between switch settings of the three addressing paddles controlling an 8K memory block and the starting address of that 8K block The table applies equally to blocks A B or C Starting Address Al5 14 13 Corre
18. sponding hex binary Hex Octal digit digit god a 4000 10 900 off on off 4 0100 eee Gk d unc ce 12 222 ee 1 aeu p 8000 340 000 on on len E iHd As an example of addressing the 24K Memory Master board the following switch positions will set the unit to the 24K of memory starting at the second 8K boundary of memory 2000H 6 off on off on eff off n E 8A 9A In this example Block A occupies memory between 2000 and 3FFFH Block B occupies memory between 4000H and uU and Block eccupies memory between 6000 and Operating Instructions WRITE PROTECTION The fifth sixth and seventh paddles of DIP switch 8A are the Write Enable switches controlling the three blocks of memory on the 24K Memory Master board The CPU can write into an 8K block of memory when the paddle associated with that block is in the on position If the paddle is in the off position the entire block is protected and cannot be altered The association between paddle position and memory block is shown in the figure below WRITE ENABLE BLOCK A B C ee Ae eh 98 on write enable on 5 6 7 off write protect off SW 8D COMING UP ENABLED OR DISABLED ON POWER ON CLEAR Paddles three and four of DIP switch 8A control whether the Memory Master will come up active or inative on Power On Clear Paddle 3 is the ON
19. ster board the user can select the corresponding bit to activate or deactivate the board The 16 pin jumper block is shown below with all pairs numbered DATA BIT JUMPER SELECTION DATAQ jumper a horizontal pair to 16 pin jumper DATAL select activation data bit block located DATA2 columns DATA3 no pair jumpered and switch 6 and 7 and DATA4 8A paddle 3 on and paddle 4 straddling rows DATA5 off will cause the board to B C and D DATA6 always be activated DATA7 x As an example with the highest pair of pins jumpered and the board addressed as I O port 40H and OUT 49H instruction with data bit set in the accumulator will activate the board while any OUT 40H instruction with data bit 0 cleared will de activate the board other words an OUT 49H executing with say a71H in the accumulator will select while an OUT 40H with a 72H will deselect The fact that any bit can be used as the board select or de select criteria means that it is possible to assign up to 8 banks of memory using the same I O port number Thus it is possible ina single instruction to turn one bank of memory off and at the Operating Instructions same time turn another on Being able to select a bit within a port also means that it is possible to have as many as 2048 banks of memory within a single 5 100 system over a 100 MILLION bytes of memory This should be sufficient for most applications No
20. te that as indicated in the figure above the 24K Memory Master can be used as a conventional 24K memory board which pays no attention to any I O commands Simply do NOT jumper any pair of pins on the jumper block set paddle 3 of DIP switch 8A to the on position and set paddle 4 of the same switch to the off position This will cause the board to come up selected when power is applied It will also prevent any bit from deselecting the board regardless of the I O port addressing PHANTOM ENABLE Paddle 1 of DIP switch 8A is the Phantom Enable switch If this paddle is in the on position the Memory Master board will deactivate itself when PHANTOM line 67 of the S 100 bus is low asserted When paddle 1 is on the off position the Memory Master will not respond to the PHANTOM signal on the bus SUMMARY OF SWITCH SETTINGS AND FUNCTIONS I O PORT ADDRESSING AD7 AD6 AD5 AD4 AD3 AD2 AD on 4 1 2 3 4 5 6 7 8 7 off ENABLE WRITE MEMORY ADDRESSING on for ENABLEN BLOCK BLOCK B N BLOCK C N enable A B C 15 14 A13 15 A14 A13 A15 A14 A13 24 CR MEN SMS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 8A 9A i la N C OFF on deactivates board on POC ON on activates board 13 48 48 24K MEMORY MASTER PARTS LIST 5 x 10 printed
21. ted in response to any bit of any I O port to come up active or inactive on power up and to honor or ignore the PHANTOM bus signal Once selected the unit is configured as three independently addressable and write protectable 8K blocks with addressing allowed at the beginning of any 8K boundary Of course the 24K Memory Master also offers the reliability and economy that come with all Morrow Designs tm as well as service that is unmatched in the industry it s another Thinker Toys product you can bank on OPERATING INSTRUCTIONS C e em ap MED ARD GEO SUED MED ee GARD GNED GAP GU Wu D m IMPORTANT NOTE AVOID ELECTRICAL DAMAGE TO YOUR MEMORY MASTER BOARD TURN OFF THE POWER IN YOUR COMPUTER BEFORE INSTALLING OR REMOVING THE BOARD MEMORY ADDRESSING The 24K Memory Master is configured as three blocks of 8K bytes each Each block can be addressed on an 8K boundary Thus a block may begin at 0000H 2000H 4000 and so forth up to the last 8K boundary E H The addressing need not be consecutive and may even overlap DIP switch 9A at the top right hand side of the board and paddle 8 of DIP switch 8A a
22. tested test starts on a page boundary to make the task of relocating the binary code easier There are two parameters in the test to be set by the user 1 The number of 4K blocks to be tested keep in mind that there are four 4K blocks per board This constant is called _ BLKCNT and is located at the eleventh byte of the test 2 The starting page number of the lowest 4K block to be tested is called PAGENO and is located at the ninth byte of the test When testing more than one 4K block of memory be sure that they contiguous memory The page number of the position of the test itself must be entered wherever a YYY g or 16 occurs in the test listing This is necessary because JMP and CALL need both the page number and the location within the page to execute correctly The only other thing to remember when loading the test is that it must _be placed at the starting address of a page Start the test at the first instruction Once started the test will run continuously unless an error is detected the test encounters an error all the data pertinent to this error is stored in the last ten locations of the test After storing this data the test comes to a dynamic halt at the label STALL The test may be restarted by stopping the computer and restarting it at the POP PSW instruction following JMP STALL user may also restart the test from the beginning If errors indicate the board is malfunctioni
23. the point where the iron component lead and the pad ALL make contact 18 Assembly Instructions 3 After the initial application of solder and when it has flowed to the pad and component lead the heat of the iron will have transferred to BOTH the pad AND the lead Apply a small amount of additional solder to cover the joint between the pad and the lead NOT PILE SOLDER ON THE JOINT EXCESSIVE HEAT AND SOLDER CAUSE PADS AND LEADS TO LIFT FROM THE CIRCUIT BOARD ALSO EXCESSIVE SOLDER IS THE PRIMARY CAUSE FOR BOARD SHORTS AND BRIDGED CONNECTIONS 11 PARTS INSTALLATION PROTECT YOUR EYES WHEN YOU CLIP COMPONENT LEADS AFTER SOLDERING Install and solder the 4 330 Ohm 1 4 watt resistors Clip the excess leads from the parts 1 Install and solder the 18 pin sockets first then the 16 and 14 pin sockets in that order installing the sockets in this order a smaller sized socket will never be placed in a larger sized position Install and solder the three SIP resistor packs Be careful that the orienting dots are pointing to the left Install and solder the 4 axial lead 1 8 microfarad tantalum capacitors circular tit identifying the positive end is to face toward the bottom of the circuit board when the part is installed Clip the excess leads from the parts Install and solder the 4 axial lead 39 microfarad tantalum capacitors The red band identifying the positive end is to fac
24. vious checks have been performed you are ready to put power to your fully populated board an empty system with power off insert the Memory Master and power up If the board smokes power down immediately and investigate If not measure the regulated voltages once again If any of the voltages have been lost since powering up the bare board power down and check for upside down ICs Isolate the possible faulty chip or chips by powering down removing a section of ICs and powering up again Continue this sequence until the faulty IC or ICs are found BE SURE NEVER TO INSERT OR REMOVE BOARD WITH POWER ON THIS MAY DAMAGE THE BOARD This completes the initial check out of your Memory Master 14 SYSTEM CHECK OUT STATIC TEST Set up In order to check out the operation of the 24K Memory Master board first configure it to function as a simple 24K memory that is addressed as the first 24K of RAM that is from 0000H at the bottem to 5FFFH at the top This be accomplished by making the following switch settings 1 Set Memory Addressing switches as below FE N E N EE EEE OA NM on 8123 4 5 6 7 8 off 8 9 where off on This represents 0000H 5FFFH 2 Set the board to ON to appear active on As discussed above this is done by turning paddle 3 of DIP switch 8A on and turning paddle
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