2 - Homepages at WMU
Contents
1. void putcspil char cx char temp while SPI1SR amp SPTEF wait until write is permissible SPIIDR cx output the byte to the SPI The following function reads a character from the SPI1 interface char getcspil void while SPI1SR amp SPIF wait until a byte has been shifted in return SPIIDR return the character and clear SPIF flag Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 74 DAC AD7390 ANALOG 3 V Serial Input DEVICES Micropower 10 Bit and 12 Bit DACs AD7390 AD7391 FEATURES FUNCTIONAL BLOCK DIAGRAM Micropower 100 uA Single Supply 2 7 V to 5 5 V Operation Compact 1 75 mm Height SO 8 Package and 1 1 mm Height TSSOP 8 Package AD7390 12 Bit Resolution SPI and QSPI Serial Interface Compatible with Schmitt Trigger Inputs APPLICATIONS Automotive 0 5 V to 4 5 V Output Span Voltage Portable Communicati2. The following function outputs a carriage return and a linefeed int newline void putchar 0x0D putchar 0x0A return 0 j ECE 4510 ak e ake ak ak ak ak ak ak ak ak a ke ae akk ak ak ak ak ak 3k ak ake ake ake ake akk 2K K The following function copies a string backwards E fk sk ie e sk sk oe ie ak e sk ak oe ak ak ak ak oe ak a e ake ak ak ak ak ak ak 3k ak ake ake ake ake akk akk ak ak ak fe 2K 2K char strflip char dest const char src int copy_length char save dest int 1i dest dest copy_length dest 0 dest for ii 0 11 lt copy_length ii dest src dest srct return 0 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 63 Output to a new line ES Se E SE Se SE The following function outputs a carriage return and a linefeed to move the cursor to the first column of the next row ES Se int newline void 0 0 Carriage Return putch
3. Department of Electrical and Computer Engineering 4 AS College of Engineering and Applied Sciences qe WESTERN MICHIGAN UNIVERSITY gt 1903 2003 ECE 4510 Introduction to Microprocessors Software Review Dr Bradley J Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Modern Computers They are everywhere and in just about everything Ubiquitous computing Cloud computing Weare all users Some of us are knowledgeable users Fewer understand basic computer architecture Fewer yet are programmers Anda very few are designers architecting and building the next generation Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 The Computing Problem System or Application Requirements O ti Algorithm a ystem and Data Structures Hardware Architcture Programming Binding High Level Compile Application Languages Link Load Software Performance K Hwang Advanced Computer Architecture s Evaluation Parallelism Scalability Programmability McGraw Hill 1993 ISBM 0 07 03 1622 8 ECE 4510 5530 M
4. The CPU and Peripherals Tools Available for Software Background Debug Module BDM Breakpoint Module BKP Random Access Interupt Module Memory RAM 14K INT On Chip Memory Electrically Erasable Memory EETS 4K Flash Programmable Memory FTS 512K SFFFF high add Central Processing Unit CPU Serial Peripheral Interface SPI O 1 and 2 Clock and Reset Generator CRG Serial Communications Inter IC Bus ECE Interface IIC 4510 5530 UART SCI 0 and 1 Pod Connected to PC Analog to Digital Converter ATD 0 and 1 Parallel Port Integration Module PIM Pulse Width Modulation PWM Controller Area Network CAN 0 to 4 Enhanced Capture Timer ECT Other Automotive Standards ByteFlight BF and 6 J1850 BDLC Interfacing Thomson Delmar Learning 2006 Software Development Environment Create a project in the environment Load files containing code into the project For high level languages Compile into assembly language e For assembly language Assemble into object code module ink multiple object code modules into machine code module Load machine code module onto the target host Executing machine code For development Use a monitor program or debugger to run machine code For users Execute machine resident code ECE 2510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing T
5. 0x00 0x10 0x20 e Compose a register read write request by 0x30 oring the fields together 0x60 0x70 void adc setup norm void setupthe ADC 0x08 adc select 0x04 adcspi_transmit SETUP_REG WRITE_ REG CHO transmit GAINO 0x00 adc deselect 0x01 0 02 0x03 81 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 AD7705 h elements define adc_select PTX amp ADC_CSn define adc_deselect PTX ADC CSn define MD NORM 0x00 define MD SCAL 0x40 define MD ZCAL 0x80 e Compose a register read write request by define MD 0 0 oring the fields together define GAINI 0x00 define GAIN2 0x08 void adc setup selfcal void self cal ADC define GAIN4 0x10 define GAIN8 0x18 define GAIN16 0x20 age 8 define GAIN32 0x28 adespi transmit SETUP REG IWRITE REG CHO define GAIN64 0x30 adcspi transmit MD GAINO BUFFON define GAIN128 0x30 adc deselect define BIPOLAR 0x00 define UNIPOLAR 0x04 e You may want to wait for ready and then define BUFFON 0x02 define BUFFOFF 0x00 repeat for ECEdefine FSYNC 0x01 82 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 AD7705 h elements define adc_select PTX amp ADC_CSn define adc_deselect PTX ADC CSn defin
6. for ii 0 1 lt 10 1 initilize key input i j key input 1i 0 asm cli Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 31 5x7 Matrix with Source and Sink Cs E MIC5891 Source I I LTP 757G or similar Display Y ULN2803A Sink i 1 DOS 2 THES Sar note shown 74HCT595 shift reg LT Pte i rob e t t t i i gt ttt Future Sink TPIC6C596N i tob wei diui gE D gt te Yt el ele AA n 32 n 12 13 14 I5 l6 7 18 GND Hardware Operating the MIC5891YN A Minimum data active time before clock pulse data set up time 75ns B Minimum data active time after clock pulse data hold time 75ns C Minimum data pulse width 150ns D Minimum clock pulse width 150ns E Minimum time between clock activation and strobe 300ns F Minimum strobe pulse width 100ns G Typical time between strobe activation and output transition 1 0us SERIAL DATA M 8 BIT SERIAL PARALLEL SHIFT REGISTER Ds DATA OUI DATA I DATA IN T STROBE LATCHES STROBE OY L n GROUND OUTPUT 0 O ENABLE OUTPUT ENABLE s OUT OUT OUT OUT OUTs OUTg OUT OUT 1 2 3 4 5 6 7 8 Timing Conditions ECE 4510 5530 Material from or based on The HCS12 9S12 An Intr
7. PERS PERS4 enable pullup down on SPIO MISO pin PERS amp PERSS PERS6 PERS7 disable pullup down on SPIO pins PPSS amp PPSS4 pull ups on SCIO MISO WOMS WOMS4 open drain drive on SCIO MISO Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 27 ECE 4510 5530 PTX 7 PTX 6 PTX 5 PTX 4 PTX 3 PTX 2 PTX 1 PTX 0 Class Keypads 5V qe Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 28 A GetKey function define keypad PORTA ex define keypad dir DDRA exe char getkey void mxs L char key_array 4 4 0 7 4 1 15 8 5 2 14 9 6 3 13 12 11 10 char rmask cmask row col cmask init keypad scan exi for col 0 col lt 4 col P2 rmask 0 01 keypad cmask Test the Oth row mu for row 0 row lt 4 rowt if keypad amp rmask key switch detected pressed keypad OxFF standby keypad values return key array col row rmask rmask lt lt 1 cmask cmask lt lt 1 OxOF sequence of OxEF OxDF OxBF and Ox 7F keypad OxFF standby keypad values return OxFF ECE 29 4510 5530 Material from or based on The HCS1
8. PWM 01 and PWM 45 are left aligned PWMPOL PPOL I PWM 01 is positive polarity PWMPOL amp PPOL3 PPOL5 PWM 3 PWM 5 are negative polarity PWMPEROI 300 Left aligned 300 count period 10 kHz PWMPER23 150 Center aligned 2 x 150 count period 10 kHz PWMPERAS 300 Left aligned 300 count period 10 kHz PWMDTY01 100 Positive 100 300 duty cycle PWMDTY23 100 Centered Negative 150 100 150 duty cycle PWMDTY45 200 Negative 300 200 300 duty cycle PWME PWMEO PVMEI PWME2 PVME3 PWME4 PWMES Enable channel 01 23 and 45 j ECE 4510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 59 The HCS12 SCI Subsystem 3 of 3 Registers Outlined in red SCI data register Idle Interrupt RxD Receive shift register generation RDRF O i Receive and wake up control 8 IRQ s E Data format control to CP clock 50 Ltrensmitcontrot_ Interrupt Status Register 1 Transmit shift register generation Status Register 2 SCI data register Figure 9 8 HCS12 SCI block diagram ECE 4510 60 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 TxD char in_buffer 80 char out_buffer 80 char char_in char state 1 char count 0 char rev_ptr char tx_ptr int in_length vo
9. Status oduction to Software amp Hardware Interfacing 1 Deimar Learning 2006 Software Operating States gt Initialization B time in seconds data entry accept time idle until turned on D turn on and start counting down the time E undefined F emergency stop User proofing requires additional state transitions ECE 15 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Accept econds Sunseeker Driver Controller State Update Code 1 of 2 Update the DC Mode switch dcMODE case POWERUP if switches new amp SW IGN ON enable FALSE switches new amp SW IGN ON else dcMODE PRECHARGE break case PRECHARGE if switches new amp SW IGN ON enable FALSE switches new amp SW IGN ON switches out new OxFF00 if bps precharge done dcMODE DISABLE break case DISABLE if enable if reverse dd MODE REV_RDY else dd MODE FWD RDY switches new amp SW break case FWD RDY if enable dcMODE DISABLE else if reverse deMODE REV RDY enum MODE POWERUP PRECHARGE DISABLE FWD_RDY FWD_DRV REV_RDY REV_DRV REGENEN CRCNTRL dcMODE dcMode should be named dcState for the operating state the car is in else if adcvaluel gt ADC MIN moving dc MODE FWD DRV switc
10. asm cli TSCH1 20x90 enable TCNT and fast timer flag clear TSCR2 0x03 set prescaler to TCNT to 1 8 TIOS 5 enable OC5 TCTL1 0 04 select toggle for OC5 pin action delay use high frequency delay count first TC5 delay start an OC5 operation TIE BIT5 enable TC5 interrupt asm cli 53 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 C Program for Siren Generation 2 of 2 while 1 delayby100ms 5 wait for half a second delay LoFreq switch to low frequency tone delayby100ms 5 wait for half a second delay HiFreq switch to high frequency tone return 0 pragma interrupt_handler oc5_ISR void oc5_ISR void TC5 delay pragma abs_address vtimch5 Initialize the Interrupt Vector address void interrupt vectors void oc5 ISR A Assign the function pointer pragma end abs address to the ISR ECE 54 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 ECE 4510 PWM Block Diagram Channel 7 Period and duty Bus clock Clock select Channel 6 Period and duty Channel 5 Period and duty Channel 4 Period and duty olarity Period and duty Ali t Gui Period and duty Channel 1 Period and duty Cha
11. Interfacing Thomson Delmar Learning 2006 canO tx isr pragma interrupt handler canO tx isr void canO tx isr void Variables extern unsigned char transO extern unsigned char transObuft extern unsigned char 0 idx extern unsigned char state transObuff 0 0 5 transObuff 1 OxE7 trans0 loop 0x00 transO_pos 0x08 while trans0 loop 0x08 Send 8 characters at a time transObuff transO_loop 4 transO transO_idx Fill the transmit buffer une ened enar Wop if transO transO_idx 0x00 if final 8 char set is partially full unsigned char trans pos transO0 11 0 trans0 pos transO loop l trans0 loop 0x08 state 1 CANOTIER amp TXEIE0 j else transO_idx j trans0 loop transObuff 12 0 pos set the transmission length CANOTFLG clear the TXEO flag ECE 4510 99 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 0 rcv isr pragma interrupt handler canO rcv isr void canO rcv isr void Variables extern unsigned char recO extern unsigned char recObuflt extern unsigned char 0 idx extern unsigned char state extern unsigned char tx status unsigned char 0 loop for 0 0 0 loop recObuff 12 recO loop recO recO idx recObuff recO 10
12. The number of bytes that can be transmitted per transfer is unrestricted Each byte must be followed by an Acknowledge bit Data is transferred with the Most Significant Bit MSB first see Figure 6 If a slave cannot receive or transmit another complete byte of data until it has performed some other function it can hold the clock line SCL LOW to force the master into a wait state Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL c NXP I2C bus specification and user manual Rev 5 9 October 2012 ECE 5 4510 5530 HC Block Diagram data bus Address interrupt ADDR DECODE DATA MUX Start stop arbitration control address compare SCL SDA Figure 11 21 block diagram Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 I2C Initialization Compute an appropriate value and write it into the IBFD register Load a value into the IBAD register if the MCU may operate in slave mode Set the IBEN bit of the IBCR register to enable I2C module Modify the bits of the IBCR register to select master slave mode transmit receive mode and interrupt enable mode void openI2C char ibc char i2c ID 1 IBCR BEN enable I2C module slave receive IBFD OxIF set up I2C baud rate IBAD 12c ID set up slave address IBCR amp IBIE disable I2C
13. 2 CLKSEL amp PLLSEL PLLCTL PLLON AUTO REFDV XTALRATE PLLCOMPRATE 1 from 1 to 16 SYNR BUSRATE PLLCOMPRATE 1 from 1 to 64 asm nop Allow time for the PLL to start and settle asm nop asm nop asm nop while CRGFLG amp LOCK 0x00 asm nop j CLKSEL PLLSEL use the PLL as the system clock PEAR amp NECLK PortE pin 4 is E clk output MODE amp 0XEF Set to special single chip operation endif ifdef ACCESS PEAR amp NECLK PortE pin 4 is E clk output MODE amp 0XEF Set to special single chip operation endif Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 24 RTI Counter Chain WAITT RTIWAD STOP PSTP PRE RTI enable RTR E4 Note OSCCLK not SYSCLK and not E Clock 210 gating condition 2 15 A Clock Gate RT TIMEOUT 4 BIT MODULUS COUNTER RTR 3 0 ECE 4510 Figure 4 6 Clock Chain for RTI 25 reto Phe GNI odii e joies pon Inter acing Thomson alma Learning CRG RTI Initialization and ISR void crg_init void Port pin 7 is the Adapt Board LED DDRP DDRP7 PTP7 RTI Iniitalization RTICTL 0 27 8 x 2411 division OSCCLK 16 MHz gt 1 024 msec CRGINT RTIE enable the rti interrup pragma interrupt_handler rti_isr void
14. SOR ae TOR Oe a ak oe ee ea dee The following function creates a time delay which is equal to the multiple of 1 ms The value passed in Y specifies the number of one milliseconds to be delayed I EE HEE SOROR E OE IE SE ak SER SESIONES NC ak a ak ak e ak ak aS 3 ak ak SOR dee a ak a ea ee void delayby I ms int k See Textbook CD Utilities delay c int 1 The above is from the TSCRI TFFCA enable fast timer flag clear current textbook CD for 120 1 i MCCTL 0x07 enable modulus down counter with 1 16 as prescaler MCCNT 1500 let modulus down counter count down from 1500 while MCFLG amp MCZF MCCTL amp 0x04 disable modulus down counter 42 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Current Textbook Delay Code Delay c void delaybylOus intk prescale 1 MCCNT 240 void delayby50us int k prescale 1 MCCNT 1200 void delayby1ms int prescale 16 MCCNT 1500 void delaybylOms int prescale 16 MCCNT 15000 void delayby100ms int k prescale 16 loop 10 times with MCCNT 15000 These are blocking delay calls Interrupts may occur but nothing else is happening in the CPU ECE 2510 43 Ma
15. encoder1 cruise velocity CRUISE STEP j break case STATE 1 D 10 if encl new STATE 1 encoderl cruise velocity CRUISE STEP j else if encl new STATE 1 C 1 cruise velocity CRUISE STEP j break default break 40 uction to Sofiware os Hardware _new The HCS12 Timer Elements Bus clock gt Prescaler 16 bit Counter Modulus counter Interrupt 16 bit Modulus Counter Timer overflow interrupt Timer channel 0 interrupt Registers Timer channel 7 interrupt PA overflow 16 bit interrupt Pulse accumulator A PA input P OR 16 bit interrupt Pulse accumulator B Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare Channel 3 Input capture Output compare Channel 4 Input capture Output compare Channel 5 Input capture Output compare Channel 6 Input capture Output compare Channel 7 Input capture Output compare Figure 1 1 Timer Block Diagram Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 16 bit free running main timer Prescaler 16 bit modulus downcounter Prescaler Load Control Registers Interrupt Registers Capture Compare Registers 41 Delay Using ECT Down Counter void delayby I ms int k EE SORORE OE IE SE ak ak ak SE ak ak ake ak SEE ak ak A
16. interrupts send and receive data blocks 0 8 Bytes ECE 95 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 main unsigned char ii COPCTL 0x00 asm sei global interrupt disable pll init crg init init sci0 Initialize SCIO canO init Initialize CANO canl init Initialize CANO printf CANO Initialized n r printf CAN1 Initialized nv for 1 0 1 lt 641 0 1 0 1 1 0 asm cli global interrupt enable state 5 ECE 4510 CAN ECE2 while 1 if state 1 state 0 tx_status 0 printf Message 1 Sent n r j if state 2 state 0 printf Message 2 received n r printf amp recO 0 newline for 1 0 31 lt 64 1 0 1 0 if state 3 state 0 tx_status 0 printf Message 2 Sent n r if state 4 state 0 printf Message 1 received n r printf amp rec1 0 newline for 11 0 11 lt 64 1i 1 1 0 j j if state 5 state 0 tx_status 1 printf Start Sending n r canO tx start j if state 6 state 0 tx_status 2 printf Start Sending nr canl tx start if state 0 amp tx_status 0 delayby1ms 500 if last message 0 last_message 1 state 6 else last_message 0 state 5 return 0 end of mai
17. of the falling edge diff TCO edge if TCO lt edge1 overflow 1 pulse_width overflow 65536u diff asm swi j void INTERRUPT tovisr void TFLG2 TOF clear TOF flag overflow overflow 1 ECE 49 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example 8 4 Output Waveform include c egnu091 include hcs12 h define hi_time 900 define lo time 2100 void main void TSCH1 20x90 enable TCNT and fast timer flag clear TIOS enable function TSCR2 0 03 disable TCNT interrupt set prescaler to 8 TCTL2 20x03 set action to be pull high TCO TCNT time start an OCO operation while 1 while TFLG1 amp COF wait for PTO to go high TCTL2 0x02 set OCO pin action to pull low TCO hi time start a new OCO operation while TFLG1 amp COF wait for PTO pin to go low TCTL2 20x03 set OCO pin action to pull high TCO lo time start a new OCO operation j ECE 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example 8 6 Estimating an Input ECE 4510 5530 Waveforms Frequency include lt hcs12 h gt include lt vectors12 h gt include lt convert c gt include stdio c define
18. rti_isr void static unsigned int count 0x0000 CRGFLG RTIF Reset the interrupt flag count count 1 500 x 1 024 msec 0 512 sec if count 500 PTP7 count 0 ECE 4510 ifdef FLASH LOAD pragma abs address vrti Vector address void interrupt vectors void rti isr Assign the function pointer pragma end abs address to the ISR Initialize the Interrupt else pragma abs_address 0x3E70 Initialize the Interrupt void interrupt vectors void rti isr Assign the function pointer pragma end_abs_address to the ISR endif 26 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 ECE 4510 Parallel Pin Init SPI Port Init for SS Pin void init_spi0 void SPIO port pin name definitions not needed but nice define MISOO PT4 define MOSIO PTSS define SCKO PTS6 define SSOn PTS7 SPIO port interface macros define spi0_ select PTS amp PTS7 define spi0_deselect PTS PTS7 SPIOBR 0x20 set buad rate to 24 MHz 6 4 MHz SPIOCRI SPE MSTR CPHA Enable Master SCLK high active low even phases SPIOCR1 amp SSOE CPOL do not use the SSn output pin SPIOCR2 SPISWAI stop sclk in wait mode SPIOCR2 amp MODFEN SPC0 do not use the SSn output pin normal MISO MOSI pins DDRS PTS7 SSOn parallel output pin
19. the CANOTXDSR2 can data data u8 2 CANOTXDSR3 can data data u8 3 data and CANOTXDSRA can data data u8 4 sen d CANOTXDSRS can data data u8 5 CANOTXDSR6 can data data u8 6 CANOTXDSR7 can data data u8 7 CANOTFLG CANOTBSEL clear TXE flag to send j ECE 105 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Receive Procedure e When a valid message is received at the background receive buffer it will be transferred to the foreground receive buffer and the RXF flag will be set to 1 CANxRFLG amp RXF The user s program has to read the received message from the RxFG and then clear the RXF flag to acknowledge the interrupt and to release the foreground receive buffer When all receive buffers in the FIFO are filled with received messages an overrun condition may occur CANxRFLG amp OVRIF Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Using receive buffers 1 void can_receive void unsigned char flags Read out the interrupt flags register flags CANORFLG Check if CSCIF Check for errors _ o if flags amp CSCIF 0x00 error conditions Clear error flags CANORFLG amp CSCIF to high j ECE 107 4510 5530 Material from or based on The HCS12 9812 An Introduction to Softwar
20. to go low Place in Standby adc select transmit STANDBY Select comm register for write standby register pair 0 adc deselect Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 AD7705 c elements intadc convert 1 reset the ADC unsigned int temp0 templ ADC value Start ADC adc select transmit COMM Select comm register for write device enabled register pair 0 adc deselect while PORTC amp 0x10 wait for DRDY to go low Read Data adc select transmit READ REG Select data reg for read templ adcspi_exchange 0x00 temp0 adcspi_exchange 0x00 adc deselect ADC value temp1 lt lt 8 temp0 return ADC value Place in Standby adc select transmit STANDBY Select comm register for write standby register pair 0 adc deselect 80 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 define adc_select define adc_deselect define COMM REG define SETUP_REG define CLOCK REG define DATA REG Zdefine CAL REG Zdefine GAIN REG Zdefine READ REG Zdefine WRITE REG define STANDBY define CHO define define CHGNDREF define CHGNDS ECE 4510 5530 AD7705 h elements PTX amp ADC_CSn PTX ADC CSn
21. 2 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Main Code Periodic Keypad Test while 1 ECE 4510 5530 Do something here asm nop Key scanning designed for every while loop Looking for the key to be pressed and released if check_keypad_flag current_key getkey retrieve a key value if last_key lt gt OxFF else j j j key countt count the key press loops key status 0x01 status is 0x01 invalid press if key_count gt KEY_ THRESH accept if greater key_status 0x02 status is 0x02 valid press if current_key OxFF key status 0x03 status is 0x03 saved value key ptr last_key key_count 0 If key_status 0x03 do key status 0x00 FE something about the value last key current key written 30 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 ECE 4510 5530 Keypad Main Code Misc define keypad PORTA define keypad_dir DDRA define KEY THRESH 1000 void main void int ii char check keypad flag char X key _ status last_key current key char key input 10 char ptr int key count COPCTL 0x00 asm sei Initilize keypad and key variables keypad init set up port pins last key OxFF key count 0 key status 0x00 key_ptr amp key input 0
22. 4 if recO recO_idx 0x00 0 11 0 state 2 else 0 14 CANORFLG 0x01 clear the flag ECE 4510 100 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Procedure for Message Transmission Step 1 Identifying an available transmit buffer by checking the TXEx flag associated with the transmit buffer CANxTFLG Step 2 Setting a pointer to the empty transmit buffer by writing the CANxTELG register to the CANxTBSEL register This makes the transmit buffer accessible to the user Moves it to the foreground Step3 Storing the identifier the control bits and the data contents into one of the foreground transmit buffers Step 4 Flagging the buffer as ready by clearing the associated TXE flag Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Using multiple transmit buffers 1 void can_transmit void Check for static unsigned int buf_addr 3 OxFFFF OxFFFF OxFFFF Check if the incoming address has already been configured in a mailbox existin 2 if can address buf addr 0 Mailbox 0 setup matches our new message addre SS Write to TX Buffer 0 start at data registers and initiate transmission while CANOTFLG amp asm nop CANOTBSEL TX0 j else if can addre
23. 5 25 V operation Power dissipation 1 mW maximum 3 V Standby current 8 pA maximum 16 lead PDIP 16 lead SOIC and 16 lead TSSOP packages Figure 1 77 4510 5530 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 AD7705 c elements define adc_select PTX amp ADC_CSn define adc_deselect PTX ADC CSn void adc reset reset the ADC Software Reset adc select adcspi transmit OxFF adcspi transmit OxFF adcspi transmit OxFF adcspi transmit OxFF adc deselect j ECE 4510 5530 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 78 AD7705 c elements void adc init the ADC Initialize clock adc select transmit CLOCK REG Select clock register for write device enabled register pair 0 adcspi transmit FS25 CLKDIV 0 CLK is 1 MHz 0 25 Hz 40 msec adc deselect Initialize setup adc select adcspi transmit SETUP REG Select setup register adcspi transmit 0x00 Mode Normal Gain 1 000 Bipolar 0 FSYNC 0 adc deselect while PORTC amp 0x10 wait for DRDY to go low Run Self Cal adc select adcspi transmit SETUP REG Select setup register adcspi transmit 0x40 Mode Self Cal adc deselect while PORTC amp 0x10 wait for DRDY
24. G1 amp COF wait for the arrival of the first rising edge edge save the first captured edge and clear COF flag while TFLG1 amp COF wait for the arrival of the second rising edge period TCO edge asm swi ECE 47 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example 8 3 C Program for Pulse Width Measurement 1 of 2 include lt hcs12 h gt include lt vectors12 h gt unsigned diff edge1 overflow unsigned long pulse_width void INTERRUPT tovisr void void main void ECE 4510 5530 COPCTL 0x00 asm sei overflow 0 TSCR1 0x90 enable timer and fast flag clear TSCR2 0x05 set prescaler to 32 no timer overflow interrupt TIOS amp 1050 select input capture 0 TCTL4 0 01 prepare to capture the rising edge TFLG1 clear flag while TFLG1 amp COF wait for the arrival of the rising edge TFLG2 TOF clear TOF flag TSCHR2 0x80 enable TCNT overflow interrupt asm cli Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example 8 3 C Code Pulse Width 2 of 2 edge1 TCO save the first edge TCTL4 0x02 prepare to capture the falling edge while TFLG1 amp COF wait for the arrival
25. INTERRUPT attribute interrupt unsigned int frequency void INTERRUPT TCO isr void void main void char arr 7 char msg Signal frequency is int i oc cnt unsigned frequency UserTimerChO unsigned short amp TCO isr TSCR1 20x90 enable TCNT and fast flag clear TSCH2 0x02 set prescale factor to 4 TIOS 0x02 select OC1 and ICO oc cnt 100 prepare to perform 100 OC1 operations frequency 0 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example 8 6 C Code 2 of 2 TCTL4 0x01 prepare to capture PTO rising edge TFLG1 COF clear COF flag TIE ICO enable ICO interrupt asm cli TC1 TONT 60000 while oc_cnt while TFLG1 amp C1F TC1 TC1 60000 OC cnt oc cnt 1 asm sei int2alpha frequency arr puts msg puts amp arr 0 asm swi void INTERRUPT isr void TFLG1 COF clear COF flag frequency ECE 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 C Program for Siren Generation 1 of 2 ECE 4510 5530 include c egnu091 include hcs12 h include c egnu091 include delay c define HiFreq 1250 define LoFreq 5000 int delay delay count for OC5 operation int main void
26. SCIOSR1 amp RDRF return SCIODRL j ECE 4510 fk sk ie o sk sk oe oie leoi sk ak oe ak ak ak ak oe oie ake ae sk akk akk ak ak ak ak ak ake ae 2 ake akk The following function uses the polling method to outputa character to the SCIO port E fk sk ie int putchar char cx while SCIOSR1 amp TDRE continue SCIODRL cx return 0 EK fk sk ie The following function uses polling method to read a character from SCIO port si E fk sk ie char checkchar void if SCIOSR1 amp return SCIODRL else return 0 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 62 SCIO Functions FE Tk ri e oi sk ak ak ie ak ak ak oe ak ak oie sk oie oe oe oie ak a ae ake akk akk ak ak ak 3k eoe 2 k ae fe akk tete The following function reads a string from the SCIO port FE Tk a oi sk ak ak ie ak ak ak oe ak ak oi sk oie oe oe ak ak oie sk sie oe ak ak ak ak ak ak ak 2 ak 3K int getstr char ptr while 1 ptr getchar if ptr 0x0D ptr 0 return 0 else ptr j return 0 j
27. UE pragma abs_address vtimmdcu Initialize the Interrupt Vector address ECE void interrupt vectors void modcnt_isr Assign the function pointer 45 4510 5530 pragma on The HCS12 9812 An Introductio eo Bde amp Hardware Interfacing Thomson Delmar Learning 2006 Periodic Event Timing Usage Try it and I will fix it if necessary define FLAG TIME 500 0 5 sec interrupts unsigned char flag FALSE assign a global flag int main void asm cli modent init enable the modulus down counter asm cli start interrupts while 1 asm nop every loop code goes here if flag1 flag FALSE Reset the flag do something every 0 5 sec j j return 0 A different flag can be created for every periodic operation required i e keypad 5x7 matrix etc ECE 46 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example 8 2 C Program for Period Measurement include c egnu091 include hcs12 h void main void unsigned int edge1 period TSCR1 0x90 enable timer counter enable fast flag clear TIOS amp 1 50 enable input capture 0 TSCR2 0x06 disable TCNT overflow interrupt set prescaler to 64 TCTL4 0x01 capture the rising edge of the PTO pin TFLG1 COF clear the COF flag while TFL
28. You need one switch case statement to update the current state to the next state or not change A second switch case block may be needed to perform operations based on the state The two switch case blocks could be merged into one to minimize code but it may not be as clear to the person reading debugging the code as to what 1s going on two processes 1 what to do in a state and 2 what 1s the next state ECE 18 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Alternate State Method 1 asm sei disable interrupts sre Exist in a state until a condition state asm cli enable interrupts changes the state variable hile 1 locked in a state while state A primary while loop does not r regularl while state epeat 5 y must have a means to modify P state either in the state or by an while state interrupt with state as a global variable etc ECE 19 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Alternate State Method 2 asm sei disable interrupts initialize everything here Chained if eee else if eee else state asm cli enable interrupts __ primary while loop repeats hile 1 regular
29. ar 0x0A Line Feed return 0 j ECE 4510 5530 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Reading Into a Buffer ES Se ES SESS ee The following function reads a string from the SCIO port by calling the getchar function until the CR character is reached RES ie e le eoe ie ie le le ole ie ie ie le ak oe ak ie le ak oe oe ak ie ie le ak ak ak ie le e ak ak ak ak ak ak ak ak ak oe oe oe ak ak ak oe ak ak ak ak ak ak 2k ak ak k ak ak k K int getstr char ptr while 1 ptr getchar if ptr 0x0D ptr 0 return 0 j else ptr j return 0 j ECE 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 65 Using the stdio library Input output manipulation functions stdin makes a function call to getchar stdout makes a function call to putchar Name getc getchar gets printf sprintf putc putchar puts scanf sscanf ECE 4510 5530 Notes reads and returns a character from a given stream and advances the file position indicator it is allowed to be a macro with the same effects as fgetc except that it may evaluate the stream more than once has the same effects as getc stdi
30. aterial from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Software Development e System Engineering Define system architecture and architectural elements Partition system for engineering elements e g antenna RF digital programmable logic DSP general CPU real time software command amp control software with GUI e Software Development DSP and or CPU ECE 2510 Design Code Test SW SW Integration SW HW Integration System Integration Acceptance Testing Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Software Development Issues e Software development starts with problem definition Problem presented by the application must be fully understood before any program can be written Next step is to lay out an overall plan of how to solve the problem The plan is also called an algorithm Algorithm is a sequence of computational steps that transforms the input into the output An algorithm can be expressed in pseudo code that is very much like C or Pascal or the target language for the code An algorithm provides not only the overall plan for solving the problem but also documentation for the S W to be developed ECE 2510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006
31. construct ECE 2510 Figure 2 5 For looping construct 10 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Subroutine Hierarchy e Structure of a modular program can be visualized as shown Principles of program design involved in high level languages can be applied to assembly language programs Subroutine objects with calls and returns main program Subroutine 1 1 Subroutine 1 2 Subroutine 2 1 Subroutine 3 1 Subroutine 3 2 Subroutine 1 2 1 Subroutine 2 1 1 Subroutine 3 1 1 Subroutine 3 2 1 ECE 2510 11 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Interrupts For Embedded Processing Initialize the interrupting function and set the local interrupt enable bit clear pending interrupts if possible Make sure a valid interrupt service routine ISR exists Make sure the system can find the ISR code A ISR address table is often used for defined types of interrupts Also called an interrupt vector IV table address of address When ready set the global interrupt enable Pending interrupts will immediately be serviced Interrupt ISR will start where the IV says even if you forgot to define where in the ECE 2510 12 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar L
32. d while SPIOSR amp SPTEF wait until write is permissible SPIODR 0x00 trigger 8 SCK pulses to shift in data while SPIOSR amp SPIF wait until a byte has been shifted in return SPIODR return the character and clear SPIF flag j ECE 4510 71 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 SPI Test2 sp10 master spil slave void main void COPCTL 0x00 asm sei pll init crg init init sciO init spi0 init spil asm cli while state 1 printf Hello World n r delayby100ms 10 char in checkchar if char in 0 state 2 printf On to state 2 n r state 3 printf On to state 3 n r j j printf data bufferl ECE 4510 Designed to test SPIO Master to SPI1 Slave Note this only works for 8 bit transfers while state 3 1 0 ptr amp data bufferl 0 rcvO ptr amp in_buffer1 0 txl amp data buffer2 0 revl_ptr amp in buffer2 0 Transfer the data while tx0_ptr 0 putcspil tx1_ptr ixl pire Slave write spi0_ select rcev0_ptr exchespi0 tx0_ptr Master exchange 1 0 rcvO ptr spi0_ deselect rcvl_ptr getcspil Slave read revl_ptrt delaybylus 1 Print the master and slave input buffers rcvO ptr 0 revl_ptr 0 printf in_buffer2 newl
33. d char I2Creadc nack void int I2Creadstr char int uses special definitions for DC STOP IBCR DC TX ACK IBCR DC TX NACK IBCR 2 CHK x Material fro Real Time Clock Calendar rtic h and rtic c Function prototypes e int RTICinit void e int RTICwrite char char char RTICread char e int RTICpwm void global declaration externs based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 CAN Physical Layer Data Frames are transmitted on a two wire common bus as CAN high CAN_H and CAN low CAN L signals CAN_H Bus line CAN_L Analogue clrcultry Analogue clrcultry Termination A Termination B Analogue clrcultry Tx Rx Tx Digital circultry Digital circultry CAN node 1 CAN node 2 Rx Tx Digital circultry CAN node Figure 1 Suggested electrical interconnection ECE 4510 94 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 CAN may sound scary but The CAN controller will perform the majority of the tasks described t must be initialized t must be told which IDs to monitor and send t must watch for RTRs The CAN transceiver will take care of outputting and monitoring the correct voltage levels Our software will have to monitor status bits respond to
34. d to test loop back of SPIO while state 2 0 ptr amp data bufferl 0 rcvO ptr amp in bufferl 0 while tx0_ptr 0 spi0_ select SPI Exchange rcvO ptr exchespiO txO ptr 0 0_ spi0_ deselect delaybylus 1 j rcvO ptr 0 printf in_buffer1 newline 0 amp in_buffer1 0 for ii 0 11 lt 80 11 rcvO ptr 0 rcvO ptr delaybyl1us 5 j End of main 68 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 ECE 4510 void init spiO void ICICI ACI Similar to Example 10 3 1st ed initialization routine g EEEE EEEE EEEE E void init_spi0 void SPIO port pin name definitions not needed but nice define MISOO PT4 define MOSIO PTSS define SCK0 PTS6 define SSOn PTS7 Make a parallel pin Explicit sw operation SPIO port interface macros define 5 0 select PTS amp PTS7 define spi0_deselect PTS PTS7 SPIOBR 0x20 set buad rate to 24 MHz 6 4 MHz SPIOCRI SPE MSTR CPHA Enab
35. e amp Hardware Interfacing Thomson Delmar Learning 2006 Using receive buffers 2 No error check for received messages else if flags amp RXF 0x00 Read in the info address amp message data can address CANOIDARO can address can address lt lt 3 temp CANOIDARI gt gt 5 can address can address temp Fill out return structure check for Remote Frame requests and indicate the status correctly if amp 0x00 We ve received a standard data packet can status CAN OK Fill in the data can data data u8 0 CANORXDSRO can data data u8 1 CANORXDSRI can data data u8 2 CANORXDSRJ2 can data data u8 3 CANORXDSR3 can data data u8 4 CANORXDSRA can data data u8 5 CANORXDSRS can data data 08 6 CANORXDSR6 can data data u8 7 CANORXDSR7 can length CANORXDLR j else We ve received a remote frame request d X Data is irrelevant with an RTR Check F can status CAN RTR RTR or me S S ag Clear the IRQ flag ECE CANORFLG amp RXF 108 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Using receive buffers 3 else can status CAN ERROR can address 0x0001 can data data_u8 0 flags CANORFLG values returned Not CSCIF or Another error possibly an overrun error all receive buffers f
36. e CLKDISABLE 0x10 define CLKDIV 0x08 define CLK2 4MHZ 0 04 e Compose a register read write request by oring the fields together define FS20 0x00 define FS25 0x01 define FS100 0x02 void adc set clock void clock definition for ADC define FS200 0x03 define FS50 0x00 TS define FS60 0x01 define FS250 0x02 adcspi_transmit CLOCK_REG WRITE_ REG define FS500 0x03 adcspi transmit FS25 adc deselect 83 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Inter Integrated Circuit 12 nter Integrated Circuit I2C Interface Synchronous fast but with pull ups required More than 8 bits at a time Multiple devices can communicate using the same serial lines Bi directional data transfer Does not require a single master Vpp OUT Datal IN IN Devcel Dpeve2 ECE 2510 84 Material HON or Aoanecting standary 5 Oe Bs yuna eran brats he oftware amp Hardware Interfacing Thomson Delmar Learning 2006 Byte Level Transfer signal from receiver 1 2 3108 9 EH E STOP or byte complete clock line held LOW repeated START interrupt within slave while interrupts are serviced condition 002aac861 Fig6 Data transfer the PC bus e Every byte put on the SDA line must be eight bits long
37. earning 2006 General Real Time Code Flow e Interrupts that must be immediately processed External Interrupt Priority Interrupt 2 Int 2 Process y Set Int 2 Flag Y RTI Gea Start 2 e Sequential Code with Infinite Loop Process as time 1s available Initialization Y Enable Interrupts Sequential Code Priority Flag Based C ase Tn Default Oe Cad Interrupt 1 y Process 1 Process 2 y Set Int 1 Flag y y Heart Beat and Status C RTI J ECE 4510 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Interrupt M 2 Int 13 Modified for Sleep Low Power e Sequential Code with Infinite Loop Process followed by sleep mode Initialization Enable Interrupts Sleep mode exited by an interrupt Only awake when processing 15 needed Sequential Code Priority Flag Based If nothing External Interrupt Priority left to do Sleep until Int Interrupt M Interrupt 1 Interrupt 2 1 H Int 1 Int M Process Process Process Process 1 Process 2 Set Int 1 Set Int 2 Set Int M Flag Flag Flag f RTI RTI Updates amp
38. ffer 0 CANOIDAR3 OxE7 CANORIER RXFIE enable the receive interrupt CANOIDAR4 Ox5F receive 11 bit address is OxSFEO gt 0x02FF CANOTBSEL TX0 select the transmit buffer 0 CANOIDARS OxE7 CANOIDAR6 0 5 receive 11 bit address is OxSFEO gt 0 02 CANOIDAR7 OxE7 ECE 4510 97 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 void canO tx start void void canO tx start void transObuff 0 0 5 Nariables transObuff 1 OxE7 extern unsigned char transO extern unsigned char transObuff trans0_loop 0x00 extern unsigned char trans0_idx 0_ 0 08 extern unsigned char state while trans0 loop 0x08 Send 8 characters at a time unsigned char transO loop unsigned char 0 pos transObuff transO_loop 4 transO transO idx Fill the transmit buffer if transO transO_idx 0x00 Check if final 8 char set is partially full 1 while CANOTFLG amp TXE0 wait until buffer empty trans0_idx 0 fasm nop transO_pos trans0_loop 1 trans0 loop 0x08 state 0 j else 1 transO_idx j trans0 100 j transObuff 12 0 set the transmission length CANOTFLG clear the TXEO flag CANOTIER TXEIEO enable the transmit interrupt buffer 0 ECE 4510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware
39. he shift registers m X L L empty shift register loaded into storage register X L Z shift register clear parallel outputs in high impedance OFF state H Q6S NC logic HIGH level shifted into shift register stage 0 Contents of all shift register stages shifted through e g previous state of stage 6 internal Q6S appears on the serial output Q7S X T L H X NC QnS contents of shift register stages internal QnS are transferred to the storage register and parallel output stages T T L H X Q6S QnS contents of shift register shifted through previous contents of the shift register is transferred to the storage register and the parallel output stages I X T X x T X I STAGE 0 STAGES 1TO6 05 ars fmax 20 MHz max clock high 24 ns min set up 24 ns min hold 3 ns min STCP prop 63 ns max 4510 5530 Introduction to Software amp Hardware ar Learning 2006 Bit Banging column shift register e Using two cascaded 74HCT595 int jj PTP 0x10 Set the one into the shift register PTP 0x20 shift register clock rise amp 0 30 shift register clock fall for 05 lt 15 1 row_load rows_excited jjt offset load the row values PTP 0x20 shift register clock rise PTP amp 0x80 Output enable row and column amp 0x20 shift register clock fall delay how long is the LED
40. hes new amp SW break ECE 16 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 enum MODE ECE 4510 5530 Sunseeker Driver Controller State Update Code 2 of 2 case FWD DRV if lenable dcMODE DISABLE else if moving amp amp brake dcMODE FWD RDY j POWERUP else if cruise PRECHARGE dcMODE CRCNTRL DISABLE ie amp ud FWD RDY FWD DRV cruise ve Dey actual ve E cruise current avg set current REV RDY REV DRV ruise steps 0 REGENEN else if regen dcMODE REGENEN mnm REV RDY case dcMODE if enable dcMODE DISABLE else if reverse f deMODE FWD RDY else if adcvaluel gt ADC MIN moving dcMODE REV DRV j switches new amp SW REGEN break case REV DRV if enable dcMODE DISABLE else if moving amp amp brake dcMODE REV RDY switches new amp SW break case REGENEN if enable dcMODE DISABLE else if regen dcMODE FWD switches new amp SW REVERSE break case CRCNTRL if enable dcMODE DISABLE else if cruise brake dcoMODE FWD DRV switches new amp SW REVERSE SW REGEN break Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Learning 2006 17 Using the previous example
41. homson Delmar Learning 2006 High level Language Preferred e Syntax of a high level language is similar to English A translator is required to translate the program written in a high level language done by a compiler There are two types of compilers native compiler and cross compiler e High level languages allow the user to work on the program logic at higher level and achieve higher productivity e Source code A program written in assembly or high level language Object code The output of an assembler or compiler ECE 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Your 4510 5530 Development Environment Software Development Environment The Imagecraft Freescale CPU12 Development Tools ICCV7 for CPUI2 refereed to as ICC12 around WMU http www imagecraft com __ CPU Embedded Debugging Tool Freescale D Bug12 e NoICE with the background debugging module BDM ICE refers to an In Circuit Emulator ECE 2510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Code Flow Loop Diagrams false Figure 2 4 An infinite loop Figure 2 6 The While Do looping construct a For I i toi DOS b For I i downto i DOS Figure 2 7 The Repeat Until looping
42. id main void COPCTL 0x00 asm sei pll init crg init init 5 100 asm cli ECE 4510 SCI Test sw c while state 1 1 printf Hello World n r delayby100ms 2 char in checkchar if char in 0 state 2 printf On to state 2 n r j j while state 2 printf State2 n r delayby100ms 10 if count 4 state 3 printf On to state 3 n r j count while state 3 getstr in_buffer in_length strlen in_buffer printf in_ buffer newline strflip out_buffer in_buffer in_length printf out_buffer newline 61 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 SCIO Functions void init_sci0 void BR ECLK 16 x BR SCIOBD 156 24 MHz E clock 9600 bps desired 0 16 error SCISWAI wakeup to mark idle line after stop SCIOCRI SCISWAI WAKE ILT 8 bit data parity disabled even parity SCIOCRI amp M PE PT transmitter enable receiver enable no interrupts enabled not a break bit not wake up SCIOCR2 TE RE j FE Tk k oi sk sie oe ie ak ak ak oe ak ak a sk oi oe oe oie ak ae ke ake ake The following function uses polling method to read a character from SCIO port T FE Tk ri i oi sk sie ak ie e ak ak oe oie ak 2 sk sie oe oe ie ak ake ake ake ak ak ak tek int getchar void while
43. ine printf in_buffer1 newline Clear the master and slave input buffers rcvO ptr amp in bufferl 0 rcvl amp in buffer2 0 for ii 0 11 lt 80 11 rcvO ptr 0 rcvO ptr rcv ptr 0 revl_ptr j delaybylus 5 j end of main Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 72 ECE 4510 void init spil void void init spil void spil port pin name definitions not needed but nice define MISO1 PHO define MOSII define SCK1 PTH2 define SS1n PTH3 spil port initialization SPIIBR 0x20 set buad rate to 24 MHz 6 4 MHz SPIICRI SPE CPHA Enable Master SCLK high active low even phases SPIICRI amp SSOE MSTR CPOL do not use the SSn output pin SPIICR2 SPISWAI stop sclk in wait mode SPIICR2 amp MODFEN SPC0 do not use the SSn output pin normal MISO MOSI pins Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 73 ECE 4510 putcspil and getcspil The following function outputs a character to the SPII interface FE Tk si e oi sk se oe ie oie
44. interrupt IBCR IBSWAI disable I2C in wait mode j ECE 87 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 I2C Master Addressing e Check to insure the bus is not busy IBSR bit IBB e Send start condition as master IBCR bits MSSL and Transmit Send address and wait for the transmission to complete Modify the bits of the IBCR register to select master slave mode transmit receive mode and interrupt enable mode char sendSlaveID char cx char RdWrn 1 while IBSR amp IBB wait until I2C bus is idle IBCR TXRX MSSL generate a start condition IBDR Rd Wrn send out the slave address with R W bit while IBSR amp IBIF wait for address transmission to complete IBSR IBIF clear IBIF flag return IBSR amp RXAK return the status of the acknowledge j ECE 88 4510 5530 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 I2C Master Sending Byte Check to insure the address acknowledge was received e Send data and wait for the transmission to complete e Send Stop Condition if sendSlaveID address isc device 0x00 IBCR amp MSSL generate stop condition error condition else IBDR write data send out the value cx while IBSR amp IBIF wait until the byte i
45. l bb 102910500007 ZemetatiotucivauitSoftware amp Hardware Interfacing Thomson Delmar Learning 2006 Phase Lock Loops A Phase Lock Loop is capable of providing an integer change up or down in the clock rate input to the PLL A voltage controlled oscillator is used REFERENCE LOCK LOCK DETECTOR REFDV 3 0 FEEDBACK REFERENCE PROGRAMMABLE DIVIDER oE UP PHASE DOWN 4 DETECTOR CRYSTAL VODPLL MONITOR 5 supplied C VDDPLLVSSPLL VDDPLL VSSPLL XTAL CPUMP S LOOP PROGRAMMABLE DIVIDER Loop d FILTER PLLCLK VDDIVSS Figure 4 1 PLL Functional Diagram ECE 4510 23 Materiet este gt Dr RC RBS medie e ton Interfacing Thomson D lmar Leaning 5 CRG Clock and PLL Setting CRG sw h Public Function Prototypes void pll init void void crg_init void void rti isr void Defines for ECLK access and PLL setup ifndef ACCESS define ECLK ACCESS endif ifndef SET PLL define SET PLL endif PLL and ECLK Rate Setting define BUSRATE 24 define XTALRATE 16 16 MHz Xtal effective 16 MHz OSCCLK define PLLCOMPRATE 1 Note max XTAL PLLC 16 Module LED pin access define LED PORT PTP define LED PIN PTP7 Constant Definitions define TRUE 1 define FALSE 0 ECE 4510 void pll init void ifdef_ SET PLL PLLCLK 2 OSCCLK SYNR 1 REFDV 1 II ECLK PLLCLK
46. le Master SCLK high active low even phases SPIOCRI amp SSOE CPOL do not use the SSn output pin SPIOCR2 SPISWAIT stop sclk in wait mode SPIOCR2 amp MODFEN SPC0 do not use the SSn output pin normal MISO MOSI pins DDRS PTS7 SSOn parallel output pin PERS PERS4 enable pullup down on SCIO MISO pin PERS amp PERSS PERS6 PERS7 disable pullup down on SCIO pins PPSS amp PPSS4 pull ups on SCIO MISO WOMS WOMS4 open drain drive on SCIO MISO Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 69 ECE 4510 char exchcsp10 char The following function exchanges a character with the SPIO interface char exchcspi0 char cx char temp while SPIOSR amp SPTEF wait until write is permissible SPIODR cx output the byte to the SPI while SPIOSR amp SPIF wait until write operation is complete return SPIODR return the character and clear SPIF flag j Material from or based on The HCS12 9812 An Introduction to Soft
47. lock fall display count 0 break E c end display5x7_advance 38 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Optical Rotary Shaft Encoder OUTPUT WAVEFORM 0 12345618 x 0 1V max 1 3V min The code repeats from 1 to 4 Detect turn direction by which rising edge leads 16 32 position 11 25 degree or 22 5 degree for code change e Similar device used on Sunseeker to engage and control rcc cruise control 39 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Sunseeker Shaft Tracking Code Keep track of encoders encl new PIIN amp ENCI B ENCI switch encl old case STATE 1 A 00 if encl new STATE 1 1 cruise velocity CRUISE STEP j else if encl new STATE 1 D encoder1 cruise velocity CRUISE STEP break case STATE 1 B 01 if encl new STATE 1 encoder1 cruise velocity CRUISE STEP j else if encl new STATE 1 encoder1 cruise velocity CRUISE STEP j ECE break 4510 5530 Material from based on The HCS12 9S12 An LN Interfacing Thomson Delmar 1596 case STATE 1 C 11 if encl new STATE 1 D encoder1 cruise velocity CRUISE STEP j else if encl new STATE 1
48. ly if state A ia not locked in a state state update or modification can else if state be performed seperately else ete 20 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Clock and Reset Generation Block CRG CRG SW code setup ECE Power on Reset Voltage Regulator Low Voltage Reset Reset System Reset 7 Generator Clock Monito Oscil Bus Clock lator Core Clock Oscillator Clock 59 m VDDPLL Clock and Reset Real Time Interrupt VSSPLL Control PLL Lock Interrupt XI Self Clock Mode Interrupt 21 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Set Choice of Clock Sources PLLSEL or SCM wait CWALSYSWAI SYSCLK fi Core clock WAIT STOP i clock Bus phase clock E Clock SCM wait RTIWAD generator stop PSTP PRE i RTI enable 1 Time E Oscillato ess E VA as i Inte pt xtal 46 wait COPWAI i stop PSTP PCE i COP enable Clock COP Operating wait SYSWAI i ada A H oscillator i i 1 clock gating condition stop PSTD i n oscillator i clock gate 1 clock i pseudo stop mode ECE 4510 Materia
49. mable Open Drain Output Control CLKOUT with 4 selectable frequencies Alarm output 64 Bytes SRAM e Low Power CMOS Technology Dynamic Current 400 A max write e 100 kHz and 400 kHz Compatibility ESD Protection gt 4 000V e Packages include 8 Lead SOIC TSSOP 2x3 TDFN MSOP and PDIP e Temperature Ranges Industrial 1 40 C to 85 C Material from or based on The HCS12 9S12 An Introduction to Sof Interfacing Thomson Delmar Learning 2006 FIGURE 1 1 TYPICAL OPERATING CIRCUIT FIGURE 2 1 DEVICE PINOUTS TABLE 2 1 DESCRIPTIONS c vss Bidirectional Serial Data 1 Vcc bz ure MusFuncionPin 1 8Vi0 5 5V Power Supply Xi Xtall Input External Oscillator Input Typical Application Schematic FIGURE 1 2 SCHEMATIC SYETEM Wot 5 1 Valo L1 See ert 1K 25 22K xr FSS Lrgwia Sen Tet Hote 1 100nF Capacitor should be placed as close to the Voc pin fe device as possible Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Lalith s Example Code e 2C routines j2c h and i2c c Function prototypes int I2Cinit char baud divisor char dev id int I2Cstart char int I2Crestart char int I2Cwritec char data int I2Cwritestr char int char I2Creadc ack voi
50. n 96 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 void init void void can0_init void enable CAN and CANE 1 MSCAN clock source is the Oscillator clock 16MHz CANOCTLI CANE CANOCTLO INITRQ initialize the CAN while CANOCTL1 amp INITAK 0x00 asm nop Waiting for the acknowledge the init CANOIDMRO 0x00 11 bit address masks CANOBTRO 0x01 Baud Rate Prescaler for 8 MHz TQ clock 16 MHz 2 CANOIDMRI Ox1F CANOBTRO amp SJWI SJWO synchronizaiton jump width are one SJW 1Tq CANOIDMR2 0x00 CANOBTRI TSEG21 TSEGI1 TSEG1O CANOIDMR3 Ox1F one sample per bit TSEG2 3 Tq 4 Tq CANOIDMRA 0x00 8Tq 1 Sync seg 3 TSEG2 4 TSEG1 PROPSEG CANOIDMRS Ox1F supports 1 Mbps using a 16 MHz crystal and 8 MHz OSCCLOCK CANOIDMR6 0x00 CANOBTRO 0x43 Class default CANOIDMR7 0 1 CANOBTRI 0x23 Class default CANOCTLO amp INITRQ turn off the initialization state CANOIDAC IDAMO four 16 bit acceptance filters while CANOCTLO amp SYNCH 0x00 CANOIDARO 0 5 receive 11 bit address is OxSFEO gt 0x02FF asm nop waiting for the synchronization CANOIDARI OxE7 CANOIDAR2 0 5 receive 11 bit address is OxSFEO gt 0 02 CANOTIER TXEIEO enable the transmit interrupt bu
51. n reads characters from stdin until a newline is encountered and stores them in its only argument used to print to the standard output stream used to print to a char array C string writes and returns a character to a stream and advances the file position indicator for it equivalent to fputc except that a macro version may evaluate the stream more than once has the same effects as putc stdout outputs a character string to stdout used to input from the standard input stream used to input from a char array e g a C string Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 66 SS Multiple IC Interconnection 45V Slave 0 Slave 1 Slave k SPI Master Shift HCS12 register register Ue register MOSI SCK MISO SS MOSI SCK MISO SS Figure 10 9 Single master and multiple slave device connection method 1 ECE 4510 67 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 SPI Test MOSI to MISO loopback void main void COPCTL 0x00 asm sei pll init crg init init sci0 init spi0 DDRH 0x00 DDRS 0x80 asm cli while state 1 printf Hello World n r delayby100ms 10 char in checkchar if char in 0 state 2 printf On to state 2 n r j j printf data bufferl ECE 4510 Designe
52. nnel 0 Period and duty Material from or based on Te 2957 Figure 8 58 i Interfacing Thomson Delmar Learning SRI mare PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWMO PWM Test c 8 bit Reg Cnt void main void COPCTL 0x00 asm sei init pwm pll init printf PWM Initialized nv erg init printf On to state 4 n r init 5 100 state 4 asm cli while state 4 asm nop while state 1 printf Hello World n r delayby100ms 2 char_in checkchar if Y char in 0 state 2 printf On to state 2 n j j while state 2 1 printf State2 n r delayby100ms 10 if count 4 state 3 printf On to state 3 n r count j ECE 4510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 ECE 4510 void init pwm void void init pwm void PWMPRCLK 0x44 Presclae A and B by 16 1 5 MHz PWMCLK 0x00 Select A and B clocks PWMCTL PSWAI PFRZ All 8 bit registers stop clocks for W or F PWMCAE CAE2 PWM 2 is center aligned PWMCAE amp CAE4 CAE0 PWM 0 and PWM A are left aligned PWMPOL PPOLO PWM 0 is positive polarity PWMPOL amp PPOL2 PPOLA PWM 2 and PWMA are negative polarity PWMPERO 150 Left aligned 300 count period 10 kHz PWMPER2 75 Center aligned 2 x 150 count pe
53. oduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Bit Banging MIC row data Using software and individual bit level ports to create a more complex signaling stream PTP 0 data PTP 1 clock ECE 4510 5530 row load rows excited jj void row load char temp 1 int 11 for 11 0 11 lt 8 11 1 bit value temp amp 0x01 Determine value if bit value 0x01 0x01 WV Data output else PTP amp 0x01 setup gt 75ns 0x02 clock high pulse gt 150 ns amp 0 02 clock low 34 temp tempi bh or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Logic for Selecting Columns e 74 595 8 bit serial in serial or parallel out shift register with output latches 3 state STAGES 1 TO 6 8 STAGE SHIFT REGISTER SHCP op LL 8 BIT STORAGE REGISTER ooo 3 STATE OUTPUTS STCP Qo Q1 Q2 Q3 Q4 Q5 Q6 Q7 ECE 35 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Functional Table Table 3 Function tablel Control input output Function SHCP STCP OE MR DS Q7S x x x L NC aLOW evel on MR only affects t
54. on one row of LEDs is on PTP 0x80 Output disable row and column next row column ECE 37 4510 5530 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 5x7 Display Code Function if display5x7 advance flag 1 cycle load column bit 15 cycles load row data shift column bit and enable display5x7 advance flag FALSE PORTA 0x08 Output disable row source 1 cycle shift column bit to 16th empty column switch display count Operational rate approx 60 Hz 17 1020 Hz 7 Using rti 1 024 msec gt 976 Hz case 0 PORTA 0x10 Set one into the first shift register or 57 4 complete scans sec PORTA 0x20 shift register clock rise PORTA amp 0x30 shift register clock fall remove input data The next clock will cause the 1st column to be active display_count increment counter break case 1 case 2 case 3 case 4 case 5 case 6 case 7 case 8 case 9 case 10 case 11 case 12 case 13 case 14 case 15 row_location display_count offset 1 row index row_load row_data_array row_location load the row value PORTA 0x20 shift register clock rise PORTA amp 0x08 Output enable row source PORTA amp 0x20 shift register clock fall display countt increment counter break default PORTA 0x20 shift register clock rise PORTA amp 0x20 shift register c
55. ons Digitally Controlled Calibration ECE 75 4510 5530 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Example DAC AD7390 void dac_output unsigned int voltage output voltage char ms_byte char ls byte ms byte voltage gt gt 8 amp OxOF Shift 16 bit value to 8 Isbs and upper 4 bits ls byte voltage amp OxFF Convert 16 bit to 8 bit dac select spi0_transmit ms byte D11 D8 transmit the most sig byte spi0_transmit 15 byte D7 DBO transmit the least sig byte dac deselect j void dac clear void zero output voltage dac select LDn goes high dac clear select CLRn goes low clock cycle delay for clearing dac clear deselect CLRn returns high dac deselect LDn returns low j ECE 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 AD7705 ADC FEATURES FUNCTIONAL BLOCK DIAGRAM AD7705 2 fully differential input channel ADCs 16 bits no missing codes 0 003 nonlinearity AD7705 AD7706 Programmable gain front end gains from 1 to 128 CHARGE BALANCING AID CONVERTER 3 wire serial interface SPI amp QSPI MICROWIRE and DSP compatible Schmitt trigger input on SCLK Ability to buffer the analog input 2 7 V to 3 3 V or 4 75 V to
56. riod 10 kHz PWMPER4 150 Left aligned 300 count period 10 kHz PWMDTY0 50 Positive 100 300 duty cycle PWMDTY2 50 Centered Negative 150 100 150 duty cycle PWMDTY4 100 Negative 300 200 300 duty cycle PWME PWMEO PWME2 PWME4 Enable channel 0 2 and 4 Material from or based on The HCS12 9S12 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 57 PWM Test2 c 16 bit Reg Cnt void main void COPCTL 0x00 asm sei pll init while state 2 1 crg init printf State2 n r init_sci0 delayby 100ms 10 DDRS 0x80 if count 4 state 3 asm cli printf On to state 3 n r j while state 1 countt printf Hello World n r delayby 100ms 2 char_in checkchar init_pwm if 1 0 printf PWM Initialized n r state 2 printf On to state 4 n r printf On to state 2 n r state 4 j while state 4 asm nop j j ECE 4510 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 PWM Test2 c 16 bit Reg Cnt void init pwm void 1 PWMPRCLK 0x33 Presclae A and B by 8 3 MHz PWMCLK 0x00 Select A and B clocks PWMCTL 45 CON23 CONO1 PSWAI PFRZ 16 bit registers stop clocks for W or F PWMCAE CAE3 PWM 23 is center aligned PWMCAE amp CAES CAE1
57. s shifted out IBSR BIF clear the IBIF flag iffIBSR amp RXAK ERR 1 status of the acknowledge IBCR amp MSSL generate stop condition 89 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 I2C Master Reading Byte Check to insure the address acknowledge was received Place device in receive mode and perform dummy read Receive and provide NACK to end communications e Send Stop Condition if sendSlaveID address isc device 0x01 IBCR amp MSSL generate stop condition error_ condition else IBCR amp TXRX TXAK prepare to receive and acknowledge IBCR TXAK prepare to not acknowledge dummy IBDR a dummy read while IBSR amp IBIF wait for the byte to shift in IBSR IBIF clear the IBIF flag IBCR amp MSSL generate stop condition buf IBDR place the received byte in buf 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 I2C Real Time Clock Calendar MCP7940M Features e Real Time Clock Calendar RTCC A Hours Minutes Seconds Day of Week Day Month and Year Dual alarm with single output e On Chip Digital Trimming Calibration Range 127 to 127 ppm Resolution 1 ppm e Program
58. ss buf addr 1 Mailbox 1 setup matches our new message Write to TX Buffer 1 start at data registers and initiate transmission while CANOTFLG amp TXE1 asm nop CANOTBSEL TX1 j else if can address buf addr 2 Mailbox 2 setup matches our new message Write to TX Buffer 2 start at data registers and initiate transmission while CANOTFLG amp TXE2 asm nop CANOTBSEL TX2 j ECE else 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 102 Using multiple transmit buffers 2 else Check if we ve got any un setup mailboxes free and use them Che ck for Otherwise find a non busy mailbox and set it up with our new address if buf_addr 0 OxFFFF Mailbox 0 is free free Write to TX Buffer 0 start at address registers and initiate transmission CANOTBSEL TXO address buf_addr 0 can address j else if buf addr 1 OxFFFF Mailbox 1 is free Write to TX Buffer 1 start at address registers and initiate transmission CANOTBSEL TX1 buf_addr 1 can address j else if buf addr 2 OxFFFF Mailbox 2 is free Write to TX Buffer 2 start at address registers and initiate transmission while CANOTFLG amp TXE2 asm nop CANOTBSEL TX2 buf addr 2 can address j else ECE 103 4510 5530 Material from or based on The HCS12 9812 An Introduction to Sof
59. terial from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Delay Using ECT TCNT Counter time delay computation is based on 24 MHz crystal oscillator ui void delaybylms int 1 int 1x TSCRI 0x90 enable TCNT and fast timer flag clear TSCR2 0x06 disable timer interrupt set prescaler to 64 TIOS BITO enable OCO TCO TCNT 375 for ix 0 ix lt 1x while TFLG1 amp TCO 375 j TIOS amp BITO0 disable j ECE 4510 See Textbook CD Utilities delay c The above is from the old textbook CD 44 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Periodic Event Timing Possible Code void modent_init void Modulus Down Counter Iniitalization TSCRI TFFCA enable fast flag clear interrupt enable modulus mode prescale 16 MCCTL MCZI MODMC MCPRI MCPRO MCCNT 1500 msec interrupts MCCTL MCEN start counting pragma interrupt handler modent isr void modent isr void 1 static unsigned int flag count FLAG TIME extern unsigned char flag1 MCFLG MCZF Reset the interrupt flag FLAG TIME must be Trigger flag events indicators a flag count defined in a header file if flag count 0 1 flag count FLAG TIME flag TR
60. tware amp Hardware Interfacing Thomson Delmar Learning 2006 Using multiple transmit buffers 3 else Wait until No mailboxes free wait until at least one is not busy while CANOTFLG amp 0x07 0x00 asm nop mailbox Is it mailbox 0 if CANOTFLG amp TXEO 1 not Setup mailbox 0 and send the message CANOTBSEL TXO busy buf_addr 0 can address Is it mailbox 1 else if CANOTFLG amp TXEI Setup mailbox 1 and send the message CANOTBSEL TX1 buf_addr 1 can address Is it mailbox 2 else 1f CANOTFLG amp TXE2 TXE2 Setup mailbox 2 and send the message CANOTBSEL TX2 buf_addr 2 can address 104 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006 Using multiple transmit buffers 4 No matches in existing mailboxes No mailboxes already configured so we ll need to load an address set it up CANOTXIDRO unsigned char can address gt gt 3 CANOTXIDRI unsigned char can address lt lt 5 CANOTXIDR3 0x00 EID8 CANOTXIDR4 0x00 EIDO CANOTXDLR 0x08 DLC 8 bytes j Fill data into buffer it s used by any address Allow room at the start of the buffer for the address info if needed CANOTXDSRO can data data u8 0 CANOTXDSRI can data data 08 1 Load
61. ull ECE 109 4510 5530 Material from or based on The HCS12 9812 An Introduction to Software amp Hardware Interfacing Thomson Delmar Learning 2006
62. ware amp Hardware Interfacing Thomson Delmar Learning 2006 70 putcsp10 and getcsp10 E fk sk si ole sk sk oe sie leoi sk ak ak ak ak ak ak oe oe Ie oie sk oie oe ak ak ak ak oe oe Ie oie sk oe oe ie ak ak ak 3k oe Ie oi ok ae fe ie akk ak ak fe oe Ie oie sk oie oe e akk ok ak oe oe eoi obe ae fe akk akk ak ak ak 3 a ae ake akk The following function outputs a character to the SPIO interface E fk sk sie ak sk sk oe sie leoi sk ak ak ak ak ak ak oe oe Ie oie sk oie ak ak ak ak ak oe oe Ie oie sk ake oe ie ak ak ak oe oe Ie oi ok oe oe oie akk ak ak oe oe Ie oe ok oie oe akk akk ok ak oe oe eoi obe seco akk akk ak ak ak a a a ake akk tete void putcspi0 char cx char temp while SPIOSR amp SPTEF wait until write is permissible SPIODR cx output the byte to the SPI while SPIOSR amp SPIF wait until write operation is complete temp SPIODR clear SPIF flag j E fk sl sie oe ok sk oe sie le oie sk ak ak ak ak ak sk oie oe le ake ake ak ak oie ak ak ok oe oe le ake ake ake ak ak ak ak ak 3k ak ie ake ake ake akk oe ak ak ok 3 oe a oe 2 ok oe oe akk ak ok ae fe ie e ake ake akk akk ak ak ie a ake akk akk ak The following function reads a character from the SPIO interface E fk sk sie e char getcspi0 voi
Download Pdf Manuals
Related Search