Xilinx XAPP1001 Reference System : PLBv46 PCI Using the ML410
Contents
1. connected_periphs memory size uart16550 bus clock freq target directory foots type tamdisk size NFS info source NFS server NFS share sysace partition IP address Current Value Edit 0r04000000 700900000 Wears 2 ramdisk 8192 dhcp Default Value Vlsysace 8192 idhep w2 an Type array int int string enum string enum string string enum strina Description Peripherals IP used in Linux Main Memory size in bytes bus clock frequency HZ for uart baud rate Destination directory for Linux BSP Device for the root filesystem Ramdisk size in 1k blacks for ramdisk ro NFS root info given by dhep or kermel corr NFS server ip address or host name for NFS share name for NFS rootfs info on k Sysace partition for Sysace rootfs IP address IPVA address ar tan to nse S Ms Configuration for Libraries Figure 21 OK Cancel Help X1001_21_010708 Software Platform Setting Setup Verify that the target directory is the same as the directory containing the Linux source XAPP1001 v1 0 February 8 2008 www xilinx com 20 Linux Kernel XILINX 6 Click Connect_Periphs and add the peripherals using the instance names shown in Figure 22 7 Add Delete List of Parameter Values EE Parameter Name connected_periphs Parameter Description Peripherals IP used in Linux LEDs_8Bit PCI32_BRIDGE SysACE_CompactFlash 1tC_Bus TriM2. 10 11 12 Set the trigger in the Trigger Setup window The trigger used depends on the problem being debugged For example if debugging a configuration transaction from the ML410 PLBv46 PCI trigger on an PLBv46 address of C_LBASEADDR 0x10C If debugging a problem configuring from the PCI side trigger on the PCI_CBE for a configuration write on CBE Simpler triggers are PCI_FRAME_N PCI_Monitor_0 on the PCI side and PA_Valid or SI_AddrAck on the PLBv46 side Arm the trigger by selecting Trigger Setup Arm or clicking on the Arm icon Run XMD or GDB to trigger patterns which cause ChipScope to display waveform output For example set the trigger to PA_Valid arm the trigger and run xmd tcl xmd_commands 410 555 tcl at the command prompt This produces signal activity in the Analyzer waveform viewer 13 ChipScope results are analyzed in the waveform window as shown in Figure 20 This figure shows the bus signals generated in step 9 above To share the results with remote colleagues save the results in the waveform window as a Value Change Dump vcd file The vcd files can be translated and viewed in most simulators The vcd2wlf_ translator in ModeSim reads a vcd file and generates a waveform log file wif file for viewing in the ModelSim waveform viewer The vcd file can be opened in the Cadence Design System Inc Simvision design tool by selecting File Open Database ChipScope Pro Analyzer new projec
3. Figure 6 shows how to specify the values of the Base Address Register BAR generics in EDK To get this screen double click on PLBv46 PCI in the System Assembly View BS aplbv46 pci_0 plbv46_pci_vi_ 01a IPIF BARO Base Address IPIF BARO High Address Remote PCI device BAR to which IPIF BARO is translated when configured with FIFOs IPIF BARO Memory Designator IPIF BAR1 Base Address IPIF BAR1 High Address Remote PCI device BAR to which IPIF BAR1 is translated when configured with FIFOs IPIF BAR1 Memory Designator Remote PCI device BAR to which IPIF BAR2 is translated when configured with FIFOs a HDL Ee 2 Toggle Names Datasheet Restore x2o000000 pxorrrrrre fixecoooc0e Vv fxso000000 pxaverrrrE fxoooooooo px00000000 X1001_06_010708 Figure 6 Specifying the Values of Generics in EDK Implementation Results The resource utilization in the reference design is shown in Table 4 Table 4 Design Resource Utilization Resources Used Available Utilization Slice registers 8475 50560 16 Slice LUTs 11259 50560 22 DCM_ADV 1 12 8 Block RAM 57 232 24 Setting C_INCLUDE_PCI_CONFIG 1 configures the bridge as a host bridge When C_INCLUDE_BAR_OFFSET 0 the C_IPIFBAR2PCIBAR_ generic s are used in address translation instead of IPIFBAR2PCIBAR_ registers Setting C_IPIFBAR_NUM 2 specifies that there are two address ranges for PLB to PCI transactions
4. Modem 0x5457 USB 2 0x5237 PCI Bus Figure 3 shows PCI Bus Devices on the ML410 The TI2250 device is a PCI to PCI bridge to the two 5V PCI slots The ALi M1535D South Bridge interfaces to the legacy devices including the audio modem USB and IDE ports The Xilinx Virtex 5 ML555 Evaluation Board is inserted into PCI slot P3 X1001_03_010708 XAPP1001 v1 0 February 8 2008 www xilinx com Introduction gt XILINX Figure 4 shows the connections of the South Bridge to the legacy devices FPGA U37 inser PCIP_Ad24 ALi South Bridge a EEE U15 PCI_P_CLK3 32 768 MHz Device ID_ Vendor ID PCI_P_AD17 0x5451 0x10B9 PCI_P_AD18 S Bridge 0x1533 0x10B9 PCI _P_AD19 Modem 0x5457 0x10B9 14 3181 MHz PCI_P_AD26 USB 2 0x5237 0x10B9 PCI P AD27 IDE Bus 0x5229 0x10B9 PCI_P AD31 USB 1 0x5237 0x10B9 OSC 24 576 MHz PCI Bus Parallel PS 2 GPIO Port Keyboard P1 P2 J5 Figure 4 ALI Bus PCI to Legacy Devices Secondary IDE J16 J15 Primary IDE U4 J3 X1001_04_010708 The functions devices and buses in this reference design are addressed using the Configuration Address Port format shown in Figure 5 00 Doubleword Function No Bus No Reserved E i i i Dev No X964_05_010708 Figure 5 Configuration Address Port Format XAPP1001 v1 0 February 8 2008 www xilinx com 4 Reference System Spe
5. lt XILINX The following table shows the revision history for this document Date Version Revision 2 8 08 1 0 Initial Xilinx release Xilinx is disclosing this Application Note to you AS IS with no warranty of any kind This Application Note is one possible implementation of this feature application or standard and is subject to change without further notice from Xilinx You are responsible for obtaining any rights you may require in connection with your use or implementation of this Application Note XILINX MAKES NO REPRESENTATIONS OR WARRANTIES WHETHER EXPRESS OR IMPLIED STATUTORY OR OTHERWISE INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA LOST PROFITS OR FOR ANY SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE XAPP1001 v1 0 February 8 2008 www xilinx com 25
6. PCI Test Scan PCI Config Regs of ML410 Xilinx PCI Core AD24 Offset 00 030010EE Offset 04 02000546 Offset 08 0600001A Offset OC BB00FFOO Of fset 10 60000008 Offset 14 AGB00008 Offset 18 00000000 Offset 1C 00000000 Of fset 20 00000000 Offset 24 00000000 Offset 28 00000000 Offset 2C BEEFB DE Of fset 30 00000000 Offset 34 00000000 Offset 38 00000000 Offset 3C 543201FF Enable Master Transactions on Xilinx PCI Core Status Command Reg of Kilinx PCI pees 02000546 Set Max LAT Timer on Xilinx PCI Cor Status Reg xC in Xilinx PCI Cece 0000FFOO Set Bus Num and Subordinate bus Num on Xilinx PCI Core Bus Num Sub Bus Num Reg x114 in Xilinx PCI Core 01000000 Scan PCI Config Regs of South Bridge AD18 Of fset 00 153310B9 Offset 04 0210000F Offset 08 06019000 Offset 0C 90000000 Of fset 16 60000000 Offset 14 00000000 Offset 18 00000000 Offset 1C 00000000 Of fset 20 80000008 Offset 24 00000000 Offset 28 00000000 Offset 2C 153310B9 Of fset 30 60000000 Offset 34 000000A0 Offset 38 00000000 Offset 3C 00000000 Connected 0 01 04 Auto detect 9600 8 N 1 X1001_16_010708 Figure 16 Running hello_pci in GDB ChipScope is used to debug hardware problems Debugging can be done at either the system or PLBv46 PCI core level To analyze PLBv46 PCI internal signals insert the ChipScope cores into pci32_bridge_wrapper ngc To analyze signals involving multiple cores insert the ChipScope cores into system ngc The flow for usi
7. X1001_13_010708 XAPP1001 v1 0 February 8 2008 www xilinx com 13 Running the Applications XILINX Running the The selection of the hello_pci is shown in Figure 14 Make the hello_pci project active and the Applications remaining software projects inactive kd ilinx Platform Studio fhomefesters designs ml410_ppc_plbv46_pci system xmp System Assembly View2 x File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help a3 x JDP able rajaa y a GalanGo n n Lla An All ella lE jaa OD xl Project Applications 1P Catalog Software Projects We ppc405_virtex4 2 00 a fe Add Software Application Project ppc405_virtex4 2 00 a Default ppc405_0_bootloop plb_v46 1 00 a Default ppc405_1_bootloop m plb_v46 1 00 a Project TestApp_Peripheral ppc405_0_iplb1 plb_v46 1 00 a Processor ppc405_0 xps_bram_if_cntlr_1 xps_bram_if_cntir 1 00 a Executable home lesters design bram_block 1 00 a Compiler Options at xps_iic 1 00 a Sources util_reduced_logic 1 00 a Headers gt LEDs_sBit xps_gpio 1 00 a i aI Project pci_dma DDR_SDRAM mpmc 3 00 a Processor ppc405_0 1 xps_intc_O xps_intc 1 00 a Executable home lesters design MGT_wrapper mgt_protector 1 00 a Compiler Options PCI32_BRIDGE plbv46_pci 1 01 a Sources RS232_Uart_1 xps_uart16550 1 00 a Headers gt pci_arbiter_o0 pci_arbiter 1 00 a
8. XILINX XAPP1001 v1 0 February 8 2008 Summary Included Systems Required Hardware and Tools Introduction Application Note Embedded Processing Reference System PLBv46 PCI Using the ML410 Embedded Development Platform Author Lester Sanders This application note describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect PLBv46 PCI core using the IBM PowerPC 405 PPC405 Processor based embedded system in the ML410 Embedded Development Platform The reference system is Base System Builder BSB based and uses ten peripherals A set of files containing Xilinx Microprocessor Debugger KMD commands is provided for writing to the Configuration Space Headers and for verifying that the PLBv46 PCI core is operating correctly Several software projects illustrate how to configure the PLBv46 PCI core s set up interrupts scan configuration registers and set up and use DMA operations The procedure for using ChipScope Pro Analyzer to analyze PLBv46 PCI and system functionality is provided The steps used to build a Linux kernel using MontaVista Linux are listed This application note includes one reference system www xilinx com support documentation application_notes xapp1001 zip The project name in xapp1001 zip is ml410_ppc_plbv46_pci Users must have the following tools cables peripherals and licenses available and installed EDK provides an evaluation l
9. AD18 XAPP1001 v1 0 February 8 2008 www xilinx com Reference System Specifics ML410 XC4VFX60 Address Map The address map of the ML410 XC4VFX60 is listed in Table 3 Table 3 ML410 XC4VFX60 System Address Map XILINX Peripheral Instance Base Address High Address MPMC DDR_SDRAM 0x00000000 Ox03FFFFFF XPS UART16550 RS232_Uart_1 0x83E00000 Ox83EQOFFFF XPS INTC XPS_intc_O 0x81800000 0x8180FFFF PLBv46 PCI PCI32_Bridge 0x85E00000 Ox85E0FFFF XPS Central DMA xps_central_dma_0O 0x80200000 Ox8020FFFF XPS BRAM xps_bram_if_cntlr_O OxFFFF0000 OXFFFFFFFF XPS SYSACE SysACE_CompactFlash 0x83600000 0x8360FFFF XPS GPIO LEDs_8Bit 0x81400000 0x8140FFFF XPS IIC IIC_Bus 0x81600000 0x8160FFFF XPS_LL_TEMAC TriMode_MAC_MII 0x81C000000 0Ox81COFFFF The reference design contains the following settings for PLBv46 PCI generics Generics are parameters that are used in VHDL to configure the design C_FAMILY virtex4 C_INCLUDE_PCI_COMFIG 1 C_INCLUDE_BAROFFSET 0 C_IPIFBAR_NUM 2 C_PCIBAR_NUM 2 C_IPIFBAR_0 0x20000000 C_IPIFBAR2PCIBAR_0O 0x80000000 C_IPIFBAR_1 0xE8000000 C_IPIFBAR2PCIBAR_1 0x90000000 When C_FAMILY is defined as Virtex4 or Spartan3 the PLBv46 PCI uses the v3 0 PCI LogiCORE IP When C_FAMILY is defined as Virtex5 the PLBv46 PCI uses the v4 0 PCI LogiCORE IP XAPP1001 v1 0 February 8 2008 www xilinx com Reference System Specifics XILINX
10. Setting C_PCIBAR_NUM 2 specifies that two address ranges are used for PCI to PLB transactions XAPP1001 v1 0 February 8 2008 www xilinx com Reference System Specifics XILINX Figure 7 provides a functional diagram of the PLBv46 PCI core The functions in the PLBv46 PCI are the PLBv46 Master PLBv46 Slave v3 0 v4 0 PCI Core and the IPIF v3 0 v4 0 Bridge PLBv46 Master IPIF V3 Bridge V3 PCI Core PCI X1001_07_010708 PLBV46 PLBv46 I I I I I I I I I I I Slave I I I Figure 7 PLBv46 PCI Functional Diagram ML555 PCI PCI Express Evaluation Platform In the reference design the PLBv46 PCI in the XC4VFX60 on the ML410 board interfaces to the PLBv46 PCI in the Virtex 5 ML555 PCI PCI Express Embedded Development Platform This operates on a 32 bit PCI bus The ML555 board uses the Xilinx XC5VLX50T device in the 1136 pin package The address map for the XC5VLX50T is listed in Table 5 Table 5 ML555 Address Map Peripheral Instance Base Address High Address LMB BRAM IF CNTLR DLMB_CNTLR ILMB_CNTLR 0x0000000 Ox00001FFF XPS UARTLITE RS232_Uart_1 0x84000000 0x8400FFFF PLBv46 PCI plbv46_pci_O 0x42600000 0x4260FFFF MPMC DDR_SDRAM_64Mx32 0x90000000 Ox9OFFFFFFF XPS GPIO LEDs_8Bit 0x81400000 0x8140FFFF MDM debug_module 0x84400000 0Ox8440FFFF XPS INTC xps_intc_0O 0x80200000 Ox8020FFFF XPS CENTRAL DMA xps_central_dma_0O 0x81810000 O
11. The system uses the embedded PowerPC as the microprocessor and the PLBv46 PCI core On the ML410 board the Virtex 4 XC4VFX60 accesses two 33 MHz 32 bit PCI buses a primary 3 3V PCI bus and a secondary 5 0V PCI bus The FPGA is directly connected to the primary 3 3V bus The 5 0V PCI bus is connected to the Primary PCI bus with a PCI to PCl bridge the TI12250 The PCI devices and four PCI add in card slots on the ML410 are listed in Table 2 All PCI bus signals driven by the XC4VFX60 comply with the I O requirements in the PCI Local Bus Specification Revision 2 2 PCI configuration in this reference design uses the ML410 PLBv46 PCI Bridge as a host bridge Figure 2 shows the ML410 with the Vmetro VG PCI inserted into PCI slot P5 and the ML555 inserted into slot P3 J CF a bm i z X1001_02_010708 Figure 2 ML410 with ML555 Vmetro VG PCI in PCI Slots XAPP1001 v1 0 February 8 2008 www xilinx com 2 Introduction lt XILINX FPGA U37 IDSEL PCI Bus PCI_P_AD24 PCI_P_CLK5 PCI_P_CLK4 PCI_P_CLKO PCl to PCl Bridge U32 5 0V PCI Slot 6 PCI_S_AD18 inge fe 5 0V PCI Slot 4 PCI_S_AD19 ing L 3 3V PCI Slot 5 PCI_P_CLK1 PCI_P_CLK3 Figure 3 PCI Bus Devices on the ML410 PCI_P_AD17 PCI_P_AD18 PCI_P_AD19 PCI_P_AD26 PCI_P_AD27 IDE Bus 0x5229 PCI_P_AD31 USB 1 0x5237 IDSEL Dev ID Audio 0x5451 S Bridge 0x1533
12. f gt TriMode_MAC_MII xps_ll_temac 1 00 a Processor ppc405_0 jtagppc_cntlr_0 jtagppc_cntlr 2 00 a Executable home lesters design proc_sys_reset_O proc_sys_reset 2 00 a Compiler Options xps_central_dma_0 xps_central_dma 1 00 a Sources gt clock_generator_0 clock_generator 1 00 a Headers lt SysACE_CompactFlash xps_sysace 1 00 a l Block Diagram2 System Assembly View Output waming Error X1001_14_010708 Figure 14 Selecting the hello_pci Software Project With the hello_pci project selected right click to build the project Connect a null modem serial cable to the RS232C port on the ML410 board Start a HyperTerminal Set the baud rate to 9600 number of data bits to 8 no parity and no flow control as shown in Figure 15 COM1 Properties Port Setting Bits per second Data bits Parity Stop bits Flow control X1001_15_010708 Figure 15 HyperTerminal Parameters XAPP1001 v1 0 February 8 2008 www xilinx com 14 Using ChipScope with PLBv46 PCI XILINX Using ChipScope with PLBv46 PCI From XPS start XMD and enter connect ppc hw and rst at the XMD prompt Invoke GDB and select Run to start the application as shown in Figure 16 The hello_pci c code originally written for the OPB PCI used on a ML310 runs without modifications on this reference system t HyperTerminal PCI Test
13. xilinx com X1001_18_010708 17 Using ChipScope with PLBv46 PCI lt XILINX 6 Click Insert to insert the core into pci32_bridge_wrapper ngo In the ml1410 ppc plbv46 pci implementation directory copy pci32 bridge _wrapper ngo to pci32_b ridge wrapper ngc In XPS run Hardware gt Generate Bitstream and Device Configuration gt Download Bitstream Do not rerun Hardware Generate Netlist as this overwrites the implementation pci32 bridge wrapper ngc produced by the step above Verify that the file size of the pci32_bridge_wrapper larger than the original version 8 Invoke ChipScope Pro Analyzer by selecting ngc with the inserted core is significantly Start Programs gt ChipScope Pro ChipScope Pro Analyzer Click on the Chain icon located at the top left of the Chipscope Analyzer s GUI Verify that the message in the transcript window indicates that a n ICON is found 9 The ChipScope Analyzer waveform viewer displays signals named DATA To replace the DATA signal names with the familiar signal names specified in ChipScope Inserter select File Import and browse to plbv46_ pci_ccs cdc in the dialog box The Analyzer waveform viewer is more readable when buses rather than discrete signals are displayed Select the 32 PLB_ABus lt gt signals cl Bus New Bus With PLB_ABus lt 0 31 gt in the ick the right mouse button and select Add to waveform viewer select and d
14. 20 ChipScope Analyzer Results After running ChipScope it is sometimes necessary to revise the Trigger or Data nets or both used in a debug operation Saving Inserter and Analyzer projects simplifies this procedure The saved project can be re opened in Inserter and edits can be made The chipscope ml410 ppc _plbv46 pci_ccs cpj file can be used for the Analyzer project XAPP1001 v1 0 February 8 2008 www xilinx com 19 Linux Kernel lt XILINX Linux Kernel XAPP765 Getting Started with EDK and Monta Vista Linux introduces Monta Vista Linux to new users The steps to build and boot a Linux kernel are given below Steps 1 3 7 8 are run on a Linux machine with MontaVista Professional Edition installed 1 Add opt montavista pro host bin and opt montavista pro devkit ppc 405 bin to PATH Create and change to the m1410_ppc_plbv46_pci linux directory Run tar cf C opt3 montavista pro devkit 1lsp xilinx m140x ppc 405 linux 2 6 10 mvl401 tar xf To generate the Linux LSP in XPS enter Software gt Software Platform Settings Select Kernel and Operating Systems then select OS linux_2_6 and Version 1 00 b Under OS and Libraries set the entries as shown in Figure 21 Software Platform Settings Processar Information Processor Instance ppc405_0 x Software Platform jos and Libraries Drivers Configuration for OS linux_2_6 v1 00 b Name S linux_2_6 lt
15. Clock Signals PClmonitor lt 32 gt PClmonitor lt 33 gt PCImonitor lt 34 gt PCIlmonitor lt 35 gt PCImonitor lt 36 gt PCImonitor lt 37 gt PCLmonitor lt 38 gt PCILmonitor lt 39 gt PCLmonitor lt 40 gt gt v Pattern F Filter Source Instance Source Component PCI_monitor lt 41 gt PCI_monitor lt 42 gt PCIlmonitor lt 43 gt PCIlmonitor lt 44 gt PClmonitor lt 45 gt PCI32_BRIDGE pib2pci PClmonitor lt 46 gt PCI32_BRIDGE plb2pci PClmonitor lt 47 gt PCI32_BRIDGE plb2pci SlwrComp PCI32_BRIDGE plb2pci PLB_RNW PCI32_BRIDGE plb2pci SladdrAck PCI32_BRIDGE plb2pci SlrdBTerm PCI32_BRIDGE plb2pci SLrdDAck PCI32_BRIDGE plb2pci PLB_abort PCI32_BRIDGE plb2pci Slwait PCI32_BRIDGE plb2pci PLB_MRdDAck PCI32_BRIDGE plb2pci PCI32_BRIDGE plb2pci PCI32_BRIDGE plb2pci PCI32_BRIDGE pib2pci PCI32_BRIDGE pib2pci IPCIR2 RRINCE smih2nci PCI32_BRIDGE pib2pci Make Connections Move Ne Remove Connections Move Ne Figure 18 Making Net Connections in ChipScope Inserter www
16. L support Enable Enhanced IDE MFM RLL disk cdrom tape floppy support Enable Include IDE ATAPI CDROM support Enable Generic PCI IDE chipset support Enable Include IDE ATA 2 DISK support Enable ALI M15x3 chipset support Enable PROMISE PDC202 46162165168169170 support Enable SCSI support Enable SCSI disk support Enable SCSI CD ROM support Enable SCSI generic support Enable SCSI low level drivers Enable Adaptec AHA152X 2825 Adaptec AHA1542 and Adaptec AHA1740 support Select Network Device Support Ethernet 10 or 100 enable 3Com devices XAPP1001 v1 0 February 8 2008 www xilinx com 22 Linux Kernel XILINX Enable Vortex if using the 3Com PCI card Enable EISA VLB PCI and on board controllers Enable DECchip Tulip dc2Ix4x PCI support EtherExpressPro 100 support National Semiconductor DB8381x and SMC EtherPowerll Select Console Drivers Disable Frame Buffer Support Select Input Core Support Disable all Select Character Devices Disable Virtual Leave Serial enabled Disable Xilinx GPIO and Touchscreen Enable USB support Runmake zImage initrd Verify that the zImage initrd elf file is in the ml1410 ppc plbv46 pci linux arch ppc boot images directory 9 Use Impact to download implementation download bit to XC4VFX6O0 Either select Device Configuration Download Bitstream from XPS or run the following command from the command prompt impact batch etc download cmd 10 Invo
17. PCI bus signals Table 7 PCI Monitor Signals Bit Position PCI Signal FRAME_N DEVSEL_N TRDY_N IRDY_N AIO N STOP_N XAPP1001 v1 0 February 8 2008 www xilinx com 16 Using ChipScope with PLBv46 PCI XILINX Table 7 PCI Monitor Signals Bit Position PCI Signal 5 IDSEL_int 6 INTA 7 PERR_N 8 SERR_N 9 Reg_N_toArb 10 PAR 11 REQ_N 12 43 AD 44 47 CBE 5 The plbv46_pci_ccs cdc provides a good starting point for analyzing designs In some analyses additional nets are needed Figure 18 shows the GUI for making net connections Click Next four times to move to the Modify Connections window Select Modify Connections The Filter Pattern is used to find net s As an example of using the Filter Pattern enter ack in the dialog box to locate acknowledge signals such as Sl _AddrAck In the Net Selections area select either Clock Trigger or Data Signals Select the net and click Make Connections XAPP1001 v1 0 February 8 2008 The correct Clock Trigger and or Data signals displayed in red v select Net Structure Nets pci32_bridge_wrapper PCIZ2_BRIDGE pci2plb_bridge_generate _pci2plb_bridge l_plb_master_llin PCI32_BRIDGE pci2pib_bridge_generate _pci2plb_bridge l_plb_master_llin PCI32_BRIDGE pci_core l_pcim_ic_32bit_generate PCI_LC PCI_LC_I Net Selections Trigger Signals Data Signals
18. PCI32_BRIDGE PLB CH 23 JPCI32_BRIDGE PLB CH 24 JPCI32_BRIDGE PLB CH 25 JPCI32_BRIDGE PLB CH 26 PCI32_BRIDGE PLB S eee eee ameter Ta jal Trigger Setup DEV 1 MyDevice1 XC4VFX60 UNIT 0 MyiLAO ILA Match Unit CI Mo TriggerPorta Function Value Radix Counter AIK 90001 2000 _2000 3000 Bin lisabl Add Active g Trigger Condition Name TriggerConditiond Trigger Condition Equation Mo aimdeg4 Bul junews Storage Qualification E waveform DEV 1 MyDevice1 XC4VFX60 UNIT 0 MILADO ILA Type Window Iz Windows 1 Position Depth 1024 Iz All Data Bus Signal x gt PCL32_BRIDGE PCI_CBE 2CI32_BRIDGE PCI_AD PCI32_BRIDGE PCI_FRAME_N PCI32_BRIDGE PCI_DEVSEL_N PCI32_BRIDGE PCI_TRDY_N PCI32_BRIDGE PCI_IRDY_N PCI32_BRIDGE PCI_STOP_N PCI32_BRIDGE S1_RaDBus PCI32_BRIDGE PLB_RNW PCI32_BRIDGE PLB_ABus plb_PLB_PAValid plb_PLB_wrPendReq plb_PLB_rdBurst p1b_PLB_busLock plb_PLB_RNU m 0 0 E acx o 0 SE OPETI reroror INFO Successfully opened Xilinx Platform USB Cable INFO Cable Platform Cable USB Port USB21 Speed 3 MHz INFO Found 1 Core Unit in the JTAG device Chain Figure 19 Creating Buses X1001_19_010708 in ChipScope Analyzer XAPP1001 v1 0 February 8 2008 www xilinx com 18 Using ChipScope with PLBv46 PCI gt XILINX
19. cations Use the steps below to execute the system using files in the ml410_ppc_plbv46_pci ready_for_download directory 1 Change to the m1410 ppc plbv46 pci ready for download directory 2 Use iMPACT to download the bitstream impact batch xapp1001 cmd 3 Invoke XMD Connect to the PPC405 processor and reset xmd connect ppc hw rst 4 Download the executable dow ml410 ppc plbv46 pci ready for download pci dma elf Executing the Reference System from EDK Use the steps below to execute the system using XPS 1 Select File gt Open system xmp in XPS 2 Use Hardware Generate Bitstream to generate a bitstream 3 Use Device Configuration gt Update Bitstream to add bootloop to bitstream 4 Download the bitstream to the board using Device Configuration gt Download Bitstream 5 Right click the Software Project e g pci_dma and Build Project 6 Invoke XMD with Debug Launch gt XMD 7 Download the executable by the following command dow m1410 ppc plbv46 pci pci_ dma executable elf Verifying the Reference Design with the Xilinx Microprocessor Debugger After downloading the bitstream file and writing to the configuration header verify that the ML410 reference design is set up correctly 1 Configure the v3 0 Command Register Latency Timer and BAR s 2 Read the configuration header Configure the Command Register Latency Timer and BAR s of the other devices in the system 4 Read the config
20. cifics Reference System Specifics XILINX The Configuration Address Port and Configuration Data Port registers in the Virtex 4 PLBv46 PCI Bridge are used to configure multiple PCI functions when host bridge configuration is enabled The bit definitions of the Configuration Address Port in the big endian format used by the PLBv46 are given in Table 1 Table 1 Configuration Address Port Register Definitions Bit Definition 0 5 Target word address in configuration space 6 7 Hardwired to 0 8 12 Device 13 15 Function 16 23 Bus Number 24 Enable 25 31 Hardwired to 0 In addition to the PowerPC 405 processor and PLBv46 PCI this system includes DDR2 and BRAM memory UART interrupt controller SYSACE IIC and GPIO The modules are shown in Figure 1 The PCI Arbiter core is included in the FPGA The addresses of the IDSEL lines on the ML410 Board are listed in Table 2 Table 2 ML410 PCI Devices IDSEL Lines Device Dev ID Vend ID Bus Dev teen FPGA 0x0410 Ox10EE 0 8 AD24 Ali M1535D South Bridge 0x1533 0x10B9 0 AD18 ALi IDE 0x5529 0x10B9 0 11 AD27 ALi Audio 0x5451 0x10B9 0 11 AD17 ALi Modem 0x5457 0x10B9 0 3 AD19 ALi USB 1 0x5237 0x10B9 0 15 AD31 ALi USB 2 0x5237 0x10B9 0 10 AD26 TI Bridge T12250 0AC23 0x104C 0 9 AD25 3 3V PCI Slot 3 N A N A AD22 3 3V PCI Slot 5 N A N A 0 5 AD21 5 0V PCI Slot 4 N A N A 1 AD19 5 0V PCI Slot 6 N A N A 1 2
21. elete the 32 discrete PLB_ABus lt gt signals Repeat this for the PLBv46 data buses Make PCI Bus signals by creating a new bus for PCI_Monitor 44 47 then rename it to PCI_Monitor 44 47 PCI_CBE Create a new bus for PCI_Monitor 12 43 then re signals are displayed as buses in Figure 19 name it to PCI_Monitor 12 43 PCI_AD The Note The Reverse Bus Order operation is useful for analyzing buses in Analyzer ChipScope Pro Analyzer new project File View JTAGChain Device TriggerSetup Waveform Window Help Srat F Ta A New Project N al JTAG Chain DEV 0 MyDevice0 System_ACE_C g DEV MyDevicel XC4VFX60 UNIT 0 MyILAD ILA Trigger Setup Waveform Listing Bus Plot EPG memm Signals DEV 1 UNIT 0 9 Data Port l amp JPCI32_BRIDGE PCI_CBE JPCI32_BRIDGE PCI_AD J amp JPCI32_BRIDGE PCI_monito JPCI32_BRIDGE SI_RdDBus PCI32_BRIDGE PLB_ABus CH 0 fplb_PLB_PAvalid CH 1 fpib_PLB_wrPendReq CH 2 fpip_PLB_rdBurst CH 3 fplb_PLB_busLock CH 4 fplb_PLB_RNW CH 5 pib_PLB_SAValid CH 6 pib_PLB_rdPendReq CH 7 plb_PLB_wrBurst CH 8 PCI32_BRIDGE PLB_ CH 9 PCI32_BRIDGE PLB_ CH 10 PCI32_BRIDGE PLB CH 11 PCI32_BRIDGE PLB CH 12 PC132_BRIDGE PLB CH 13 PCI32_BRIDGEAP 21 CH 14 PCI32_BRIDGE PLB CH 15 PCI32_BRIDGE M_ CH 16 PCI32_BRIDGE PLB CH 17 PCI32_BRIDGE PLB CH 18 PCI32_BRIDGE PLB CH 19 PCI32_BRIDGE PLB CH 20 PCI32_BRIDGE PLB CH 21 JPCI32_BRIDGE PLB CH 22 J
22. icense for PLBv46 PCI e Xilinx EDK 9 2 02i e Xilinx ISE 9 2 04i e Xilinx Download Cable Platform Cable USB or Parallel Cable IV e Null modem serial cable e Monta Vista Linux v4 0 Development Kit e Model Technology ModelSim v6 1e e ChipScope Pro Analyzer 9 2 01 e PLBv46 PCI License PCI transactions are done between an initiator and a target This reference design is for the ML410 Embedded Development Platform To be useful a target board should be inserted into a PCI slot In the examples provided in this application note the ML555 Embedded Development Platform is inserted into PCI slot P3 of the Xilinx ML410 Evaluation Platform This allows both configuration and memory transactions to be done on the PCI bus between an initiator and a target The examples use the ML410 PLBv46 PCI as the initiator and the ML555 PLBv46 PCI as the target An Avnet Spartan 3 Evaluation board can be substituted for the ML555 Embedded Development Platform 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners XAPP1001 v1 0 February 8 2008 www xilinx com 1 Introduction gt XILINX Figure 1 is a block diagram of the reference system XPS_ SYSACE PPC405 XPS CENTRAL DMA PLBv46 PCI X1001_01_010708 Figure 1 ML410 PLBv46 PCI Reference System Block Diagram
23. igure 10 shows the parameters in pci_dma c which can be edited to run DMA transactions between different memory regions define MEM 0 BASEADDR 0x20000000 define MEM _1 BASEADDR 0x20002000 DMALength 1024 X1001_10_010708 Figure 10 Defining Source and Destination Addresses Length in pci_dma c DMA Transactions Many of the XMD scripts and C code examples generate Direct Memory Access DMA operations DMA transactions are initiated by writing to the Control Source Address Destination Address and Length registers of the DMA controller Table 6 provides these register locations of the XPS Central DMA controller Table 6 DMA Register Locations DMA Register Address Control Register C_BASEADDR 0x04 Source Address Register C_BASEADDR 0x08 Destination Address Register C_BASEADDR 0x0C Length Register C_BASEADDR 0x10 An example of XMD code which generates DMA transactions is given in Figure 11 Write DMA Control Register mwr 0x80200004 OxC0000004 Write DMA Source Address Register mwr 0x80200008 0x20000000 Write DMA Destination Address Register mwr O0x8020000C 0x20002000 Write DMA Length mwr 0x80200010 64 X1001_11_010708 Figure 11 Generating DMA Transactions XAPP1001 v1 0 February 8 2008 www xilinx com 12 Reference System Specifics lt XILINX The pci_dma c code consists of the four functions in the functional diagram in Figure 12 The Barberpole Regio
24. ke XMD From the m1410_ ppc plbv46 pci linux directory enter the following commands in the XMD window rst dow arch ppc boot images zImage initrd elf con 11 The HyperTerminal window displays the Linux boot process Login as root Enter ca and 1s 1 to view the contents of the mounted Linux partition 12 Enter lspci vv to view the PCI devices For each line of output the first 2 digits represent the PCI bus number followed by the device number and function number 13 An alternative to downloading the Linux kernel executable is to load it into CompactFlash The file used uses an ace file extension To generate an ace file run the command below from the m1410_ ppc _plbv46_ pci directory xmd tcl genace tcl jprog hw implementation system bit ace implementation ace system _hw ace board ML410 Copy the ace file to a 64 512 MB CompactFlash CF card in a CompactFlash reader writer Remove the CF card from the CF reader writer and insert it into the CompactFlash slot J22 on the ML410 board Power up the board and view Linux booting in the HyperTerminal window XAPP1001 v1 0 February 8 2008 www xilinx com 23 Reference Design Matrix Reference The reference design matrix is shown in Table 8 Design Matrix Table 8 Reference Design Matrix XILINX General Developer Name Xilinx Target devices stepping level ES production speed grades Virte
25. le Writing 0x08400080 to wL410 CAP OC Rev ID outfile mwr Ox4260010C 0x08400080 outfile Reading wWL410 Class Code Rev ID outfile mrd 0x42600110 1 outfile Writing ML410 0x0C400080 LT outfile mwr 0x4260010C 0x0C400080 outfile Writing ML410 OxO0FFOO00 to LT COP outfile mwr O0x42600110 OxO0FFO000 goutfile Reading M 410 COP at O0x42600110 Expecting LT Ox00FFO000 outfile mrd Ox42600110 1 outfile Writing O0x10400080 L410 BARO CAP outfile mwr Ox4260010C 0x10400080 outfile Writing ML410 BARO Ox60000000 outfile mwr O0x42600110 Ox00000060 outfile Reading L410 BARO goutfile mrd Ox42600110 1 outfile Writing 0x14400080 L410 BART CAP goutfile mwr Ox4260010C 0x14400080 outfile Writing ML410 BARI Ox40000000 outfile mwr 0x42600110 Ox00000040 outfile Reading L410 BARI X1001_09_010708 Figure 9 Excerpts from 410_555 tcl Software Projects The reference system contains the following software projects hello_pci This project enables master transactions sets the latency timer defines the bus number subordinate bus number and scans the PCI bus configuration space headers XAPP1001 v1 0 February 8 2008 www xilinx com 11 Reference System Specifics XILINX pci_dma This project runs DMA operations The user sets the source address destination address and DMA length This code is used for DMA operations between a variety of source and destination addresses F
26. n function provides a rotating data pattern on the memory located at the source address The Zero Region function sets the memory located at the destination address to all zeroes The DMA Region function performs a DMA transaction of data located at the source address to the memory at the destination address The Verify function verifies that data at the source address and destination address are equal Figure 13 show the Hyperterminal output when running the pci_dma executable elf The program is run twice initially with a length of 100 then with a length of 400 Barberpole Region X1001_12_010708 Figure 12 Functional diagram of pci_dma c t HyperTerminal File Edit View Call Transfer Help De g DB Entering BarberPoleRegion StartAddress 20000000 Length 00000100 Exiting BarberPoleRegion Entering ZeroRegion Entering main DHA example MEM_ StartAddress 20000000 MEM_1 StartAddress 20002000 Entering BarberPoleRegion StartAddress 20000000 Length 00000100 Exiting BarberPoleRegion Entering ZeroRegion Entering main DHA example MEM_ StartAddress 20000000 MEM_1 StartAddress 20002000 Entering BarberPoleRegion StartAddress 20000000 Length 90000400 Exiting BarberPoleRegion Entering ZeroRegion Connected 18 10 00 Auto detect 9600 8 N 1 Figure 13 pci_dma c Output
27. ng the two debugging methods differs Below an outline of the steps for debugging at the system level is provided This is followed by a detailed list of steps for debugging at the core level Inserting ChipScope at the System Level The following steps insert the ChipScope cores into the system 1 In XPS select Hardware gt Generate Netlist 2 From the command prompt in the implementation directory run ngcbuild i system ngc system2 ngc 3 Invoke ChipScope Inserter To specify the input in the Input Design Netlist window browse to the system2 ngc file created in step 2 Define the Clock Trigger and Data signals in Inserter and generate the ICON and ILA cores The chipscope m1410 ppc plbv46 pci_scs cdc file provides signals from the PLBv46 PCI and XPS Central DMA Controller as an example 4 From ml410_ppc_plbv46_pci implementation copy the file displayed in the Inserter Output Design Netlist window usually implementation system2 ngo to implementation system ngc XAPP1001 v1 0 February 8 2008 www xilinx com 15 Using ChipScope with PLBv46 PCI 5 In XPS run Hardware Generate Bitstream lt XILINX The m1410_ppc_plbv46_pci_scs cpj is provided in the chipscope directory for Analyzer projects Inserting ChipScope in the PLBv46 PCI Core The m1410 ppc plbv46 pci chipscope plbv46 pci _ccs cdc file is used to insert a ChipScope ILA core into the ML410 PLBv46 PCI Bridge wrapper pci32_bridge_wrapper core D
28. o the following steps to insert a core and analyze PLBv46 PCI problems with ChipScope 1 Invoke XPS Run Hardware Generate Netlist 2 Copy chipscope plbv46 pci _ccs cdc file to the project area one directory above the chipscope directory 3 Run Start gt Programs ChipScope Pro ChipScope Inserter 4 From ChipScope Inserter run File Open plbv46_pci_ccs cdc Figure 17 shows the ChipScope Inserter setup GUI after File Open plbv46_pci_ccs cdc bd ChipScope Pro Core Inserter File Edit Insert Help Cae o gt k ICON Design Files Core Utilization LUT Count 97 FF Count 28 BRAM Count o DEVICE Select Device Options Input Design Netlist signs ml410_ppc_plbv46_pci implementation pci32_bridge_wrapper ngc Browse Output Design Netlist signs ml410_ppc_plow46_pci implementation pci32_bridge_wrapper ngo Browse Messages Output Directory home lesters designs ml410_ppc_plbv46_pci implementation Browse Device Settings Device Family Virtex4 sl v Use SRL16s v Use RPMs Previous Next gt Figure 17 ChipScope Inserter Setup X1001_17_010708 The PCI_Monitor signals are the PCI bus signals AD CBE and the remaining PCI Bus signals Table 7 defines the functionality of the PCI_Monitor signals The Filter Pattern PCI_Monitor is used to locate the
29. ode_MAC_MII xps_intc_O To add an element to the parameter list click Add To delete an element select the row and click Delete Add Delete OK Cancel X1001_22_010708 Figure 22 Connected Peripherals Click OK 7 Select Software Generate Libraries and BSPs to generate the LSP in m1410_ ppc_plbv46_pci linux 8 The m1410_ppc_plbv46_ pci linux config is used to define the contents of the Linux kernel XAPP1001 v1 0 February 8 2008 www xilinx com 21 Linux Kernel XILINX As shown in Figure 23 enter make xconfig and generate anew config using the following options File Option Help o ld ll E Option Code maturity level options MPCI support General setup OLegacy proc pci interface Configure standard kernel features for s IPCI device name database Loadable module support Processor be IBM 4xx options Platform options PCCARD PCMCIA CardBus support Advanced setup Device Drivers i Generic Driver Options Memory Technology Devices MTD Bus options Parallel port support Plug and Play support Block devices 10 Schedulers TA ATAPI MFM RLL support SCSI device support Multi device support RAID and LVM Fusion MPT device support X1001_23 010408 Figure 23 Running make xconfig Run the following steps Select General Setup Enable PCI Disable PS 2 keyboard Change to dev ram for booting from ramdisk Select ATA IDE MFM RL
30. s Master Enable bit in the command register For memory transactions set the memory space bit For I O transactions set the I O space bit 2 Configure the Latency Timer to a non zero value usually OxFF 3 Configure at least one BAR Configure additional BARs as needed for other memory lO address ranges The v3 0 core configures itself only after the Bus Master Enable bit is set and the latency timer is set to avoid time outs If the v3 0 core latency timer remains at the default O value configuration writes to remote PCI devices do not complete and configuration reads of remote PCI devices terminate due to the latency timer expiration Configuration reads of remote PCI devices with the latency timer set to O return OXFFFFFFFF Configuration of PLBv46 PCI on the ML555 PCI PCI X Board When the ML555 is inserted into the ML410 PCI slot P3 AD22 the PLBv46 PCI Bridge in the XC4VFX60 FPGA interfaces to an PLBv46 PCI Bridge in the XC5VLX50T FPGA To configure the ML555 XC5VLXS50T connect the Xilinx Download USB or Parallel IV cable to the ML555 JTAG port and use Impact to download the download bit file After downloading the XC5VLX50T FPGA bit file the ML555 PLBv46 PCI is configured using Configuration write transactions from the ML410 PLBv46 PCI XAPP1001 v1 0 February 8 2008 www xilinx com 9 Reference System Specifics gt XILINX Executing the Reference System using the Pre Built Bitstream and the Compiled Software Appli
31. t Eile View JTAG Chain Device TriggerSetup Waveform Window Help Qanri Fle AHA 5 4 New Project K S Waveform DEV 1 MyDevice1 XC4VFX60 UNIT 0 MyILA0 ILA JTAG Chain DEV 0 MyDevice0 System_ACE_CF Bus Signal PTOI ee ee DEV MyDevice1 lt C4VFX60 z UNIT O MyILAD ILA PCI32 BRIDGE PCI_CBE x o Trigger Setup PCI32_BRIDGE PCI_FRAME_N Waveform Listing PCI32_BRIDGE PCI_DEVSEL_N Bus Plot im any PCI32_BRIDGE PCI_IRDY_N ol 1 1 PCI32_BRIDGE PCI_TRDY_N 1 l l ar Signals DEV 1 UNIT 0 g Data Port PCI32_BRIDGE PCI_STOP_N P IPCIS2_BRIDGEIPCI_CBE o pcI32_BRIDGE PCI_AD ooofoooooooo X 4o00 K 00000000 X onn IPCI32_BRIDGE PCI_AD JPCI32_BRIDGE PLB_WrDBu 2CI32 BRIDGE PLB WrDBus 2p 02062200 IPCI32_BRIDGE SI_RdDBus JPCI32_BRIDGE PLB_ABus CH 0 plb_PLB_PAValid PCI32 BRIDGE PLB_ABus 000 00000004 CH 1 plb_PLB_wrPendReq CH 2 Jplb_PLB_rdBurst 4 HH CH 3 plb_PLB_busLock 00 A X 0 0 D1 P CI32_BRIDGE S1_RdDBus ooo 00000000 COMMAND set_match_function 1 0 0 0 3 1 XXXXXXXXXXXIXXXXXXXXXXX COMMAND set_trigger_condition 10 3 15555 COMMAND set_storage_condition 1 0 FFFF COMMAND run 10 COMMAND upload 10 INFO Device 1 Unit 0 Waiting for core to be armed Upload X1001_20_010708 Figure
32. uration headers of the other devices in the system 5 Perform a memory read of one of the IPIF BARs 6 Perform a memory write of one of the IPIF BARs Verification is done using either Xilinx Microprocessor Debugger XMD or the software projects discussed later TCL scripts of the XMD commands are provided in ml410_ppc_plbv46_pci xmd_commands The 410_555 tcl script configures and verifies the ML410 and ML555 PCI cores To run this script enter xmd tcl xmd_commands 410 555 tcl at the command prompt XAPP1001 v1 0 February 8 2008 www xilinx com 10 Reference System Specifics XILINX The XMD commands in the 410_555 tc1 file partially listed in Figure 9 write to the Configuration Address Port and to the Configuration Data Port to program the Configuration Space Headers The Command Status Register Latency Timer and Base Address Registers of the ML410 and ML555 PLBv46 PCls are written and read v ECEE foutfile Configure the M 410 PLB PCI outfile Writing Ox00400080 to M410 CAP Device ID Vendor ID goutfile mwr Ox4260010C 0x00400080 outfile Reading CDP at O0x42600110 Device ID Vendor ID outfile mrd 0x42600110 1 outfile Writing 0x04400080 to M1410 CAP CSR outfile mwr Ox4260010C 0x04400080 outfile Writing 0x086002002 to ML410 CSR at 0x42600110 outfile mwr 0x42600110 0x86002002 outfile Reading ML410 COP at 0x42600110 CSR Expecting 0x46050002 outfile mrd 0x42600110 1 outfi
33. x 4 XC4VTFX60 Source code provided No Source code format VHDL Design uses code IP from an existing reference design application No note 3rd party or CORE Generator software Simulation Functional simulation performed No Timing simulation performed No Testbench used for functional simulations provided No Testbench format N A Simulator software used version i e ISE software Mentor N A Cadence other SPICE IBIS simulations No Implementation Synthesis software XST Implementation software tools used versions ISE9 2i SP3 Static timing analysis performed Yes Hardware Verification Hardware verified Yes Hardware platform used for verification ML410 ML555 References DS207 PCI 64 32 Interface v3 0 Data Sheet UG159 LogiCORE IP Initiator Target v3 1 for PCI UG262 LogiCORE IP Initiator Target v4 5 for PCI UG044 ChipScope ILA Tools Tutorial UG241 OPB PCI v1 02a User Manual XAPP765 Getting Started with EDK and MontaVista Linux ooN PF WON Platform UG085 ML410 Embedded Development Platform User Guide UG201 Virtex 5 ML555 Development Kit for PCI PCI Express Designs User Guide XAPP999 Reference System PLBv46 PCI Using the ML555 Embedded Development 10 XAPP1038 Reference System PLBv46 PCI Using the Avnet Spartan 3 Evaluation Board 11 XAPP998 PCI Bus Performance Measurements using the Vmetro Bus Analyzer XAPP1001 v1 0 February 8 2008 www xilinx com 24 Revision History Revision History Notice of Disclaimer
34. x8181FFFF XPS BRAM CNTLR xps_bram_if_cntlr_1 0x8A208000 Ox8A20FFFF The ML555 includes a 64 bit PCI edge connector 128 MB or 256 or 512 MB DDR2 SDRAM memory RS232C port LED displays XCF32P FSG48C Platform Flash configuration PROM and a JTAG port The MicroBlaze microprocessor is used The application note XAPP999 Reference System PLBv46 PCI in a ML555 Embedded Development Platform provides a link to the ML555 system XAPP1001 v1 0 February 8 2008 www xilinx com Reference System Specifics gt XILINX Figure 8 shows the principle interface blocks when transferring data between the PLBv46 PCI in the XC4VFX60 on the ML410 board and the PLBv46 PCI in the XC5VLX50T on the ML555 board ML555 Slot P3 PLBv46 PLBv46 PCI PCI X1001_08_010708 Figure 8 Interfacing ML410 PLBv46 PCI with ML555 PLBv46 PCI Configuration of PLBv46 PCI on the ML410 Board For the PLBv46 PCI bridge to perform transactions on the PCI bus the PCI LogiCORE IP v3 0 must be configured using configuration transactions from either the PCl side or from the PLB side In this reference design the ML410 PLBv46 PCI is the host bridge configured from the PLB side The v3 0 IDSEL input is connected to the address ports specified in Table 2 and the IDSEL port of the PLBv46 PCI is unused Use the following steps to write to the configuration space header CSH 1 Configure the Command and Status Register The minimum that must be set is the Bu
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