space 3d capacitance extraction user`s manual
Contents
1. Netherlands October 1991 N P van der Meijs Accurate and Efficient Layout Extraction Ph D Thesis Delft University of Technology Network Theory Section Delft the Netherlands 1992 The Nelsis IC Design System CONTENTS Introduction dy Tak 1 1 3D Capacitance Extraction 1 2 Space Characteristics 1 3 Documentation 1 4 On line Examples Program Usage 2 1 General 2 2 Batch Mode Pes oe 2 3 Interactive Extraction Technology Description 3 1 Introduction 3 2 Unit specification I 3 3 The vertical dimension list 3 4 The edge shape list 3 5 Dielectric Structure 3 6 Diffused conductors 3 7 Gate capacitances 3 8 Non 3D capacitances 3D Capacitance Computation 4 1 Introduction 4 2 Mesh Construction 4 3 Shape and Weight Faieadis 4 4 Accuracy of Elastance Matrix 4 5 Window Size 4 6 Discarding 3D Capas 4 7 Example Parameter File 4 8 Run time Versus Accuracy Examples 5 1 5 Parallel Consus 5 2 Cmos Static RAM Cell Solving Problems F 6 1 Long Computation Times 6 2 Numerical Problems 6 3 Negative Capacitances 6 4 Mesh Generation Problems Appendix A 3D Capacitance Model A 1 Introduction A 2 The Boundary Pismeni Method A 3 Approximate Matrix Inversion O O COoOAANANAA Q UUU NRF eee NNNNR FO NYVNNWNY WY Q L2 L2 L2 D QO O O References I 31 Figure 3 1 Figure A 1 Figure2. at steps in height above the substrate e g the transition of metal above polysilicon to metal not above polysilicon It must hold that cap3d default_step_slope gt 0 Z NOTE To prevent the overlap of different transition areas of one conductor which currently results in incorrect element meshes the value of cap3d default_step_slope may not be too small The Nelsis IC Design System Space 3D Capacitance Extraction 10 cap3d max_be_area area This parameter specifies in square microns the maximum area of boundary elements that are interior elements i e elements that are not along the edges corners of the conductors This parameter has no default and must therefore always be specified when performing 3D capacitance extraction cap3d edge_be_ratio float default 1 This parameter specifies the ratio between the maximum size of interior elements and the maximum size of edge elements edge elements are elements that are adjacent to the edges corners of the conductors interior elements are the other elements see also the parameter cap3d max_be_area To efficiently compute accurate 3D capacitances it is advantageous to use smaller elements near the edges corners of the conductors This is achieved by using for cap3d edge_be_ratio a value smaller than 1 Because the mesh refinement is done incrementally the size of the elements will gradually decrease towards the edges corners of the conductors This is also influenced
3. lambda is 0 25 mkpr exam2 available processes process id process name 3 scmos n 23 dimes01 select process id 1 23 3 enter lambda in microns gt 0 001 0 25 Next go to the project directory and copy the example source files from the directory cacd demo sram oe cd exam2 cp cacd demo sram oe The layout of the ram cell is put into the database as follows cgi sram gds A picture of the layout is shown below A t_vss E b_vss The following technology file sram s is used for extraction The Nelsis IC Design System Space 3D Capacitance Extraction 19 space element definition file for scmos_n example process with vertical dimensions for conductors for 3D capacitance extraction masks cpg polysilicon interconnect ccp contact metal to poly caa active area cva contact metal to metal2 cmf metal interconnect cwn n well cms metal2 interconnect csn n channel implant cca contact metal to diffusion cog contact to bondpads See also maskdata maxkeys 10 colors cpg red caa green cmf blue cms gold cca black ccp black cva black cwn glass csn glass cog glass cx glass unit resistance 1 Ohm unit c resistance le 12 Ohm meter 2 unit a_capacitance le 6 Farad per meter 2 unit e capacitance le 12 Farad per meter unit capacitance le 15 Farad unit vdimension le 6 meter unit shape
4. A brief description of this method is given in Section A 2 For the solution of the boundary element equations a large matrix needs to be inverted The approximate matrix inversion technique that is used for this is described in Section A 3 A 2 The Boundary Element Method Consider a domain V that contains M conductors Our purpose is to find the short circuit capacitance matrix C that gives the relation between the conductor charges QO Q Q2 Qu and the conductor potentials D ylas Q C A 1 The potential p at a point p in V can be expressed as 1 2 op Gp 2 p a dq A 2 V where p q is the charge distribution in V and G p q is the Green s function for V In order to solve A 2 the boundary element method subdivides the surfaces of the conductors in elements S1 S2 Sy the elements may partly be overlapping and approximates the charge distribution p q by X N p q p q gt a fil A 3 i l where O Oo Oy are unknown variables to be determined and f1 f2 fy are N independent shape functions also called basis functions The f s have the property that 1 ifi j Jay da 0 ifizj A4 Some examples of shape functions are given in Figure A 1 An approximation for the potential distribution is then obtained by insertion of A 3 into A 2 N DP E ce GP 2 fq dq A 5 i 1 Next N independent linear equations are obtained by introducing a set of N indepen
5. Value 1 means no enforcement Value 3 means triangular faces Value 4 means quadrilateral faces only valid with constant shape functions see below The Nelsis IC Design System Space 3D Capacitance Extraction 11 4 3 Shape and Weight Functions cap3d be_mode mode default Oc Specifies the type of shape functions and the type of weight functions that are used see Section A 2 mode shape function weight method Oc piecewise constant collocation Og piecewise constant Galerkin lg piecewise linear Galerkin An example of a piecewise constant shape functions is given in Figure A 1 b An example of a linear shape functions is given in Figure A 1 c Given a certain accuracy the Galerkin method as compared to the collocation method allows to use larger elements cap3d mp_min_dist distance_ratio default 2 0 When the charge and observation elements are not too close together the influence matrix element linking them can be calculated much faster 2 to 20 times using a multipole expansion than by numerical integration This parameter specifies a threshold value of the ratio between the charge observation distance and the convergence radius of the multipole expansion for larger distances the multipole expansion is used for smaller distances numerical integration Usually a ratio of 1 5 is satisfactory When setting the parameter to infinity all influence matrix elements are calculated by numerical integration cap3d m
6. by the parameter cap3d edge_be_split cap3d edge_be_split float default 0 5 If during mesh refinement a quadrilateral edge element is split into two elements see also the description of the parameter cap3d edge_be_ratio this parameter specifies the ratio between the size of the element that becomes an edge element and the size of the element that becomes an interior element cap3d edge_be_split_lw float default 4 During mesh refinement this parameter is used to determine the split direction of a quadrilateral element Interior elements are always split perpendicular to their longest side If the ratio between the longest side and the shortest side of an edge element does not becomes larger than cap3d edge_be_split_lw an edge element is split in a direction parallel to the edge direction Otherwise the edge element is split perpendicular to its longest side The minimum value for cap3d edge_be_split_lw is 2 cap3d max_coarse_be_area float default cap3d max_be_area For conductors that are sheet conductors thickness is zero this parameter specifies in square microns the maximum area of the boundary elements When this parameter is specified edge elements of sheet conductors are not further refined compared interior elements This parameter can for example be used to model large conductor planes with a much coarser element mesh cap3d be_shape number default 1 Enforces a particular shape of the boundary element faces
7. capacitance in the menu options click button DrawBEMesh DrawGreen and 3 dimensional in the menu display and click button extract in the menu Extract This will yield the following picture The Nelsis IC Design System Space 3D Capacitance Extraction 22 Extract The extraction result is retrieved using xspice 5 xspice a sram sram Generated by xspice 2 28 14 Apr 1999 Date 23 Jun 99 11 27 52 GMT Path users space sram m1 m2 m3 m4 m5 m6 gl c2 C3 c4 e5 c6 c7 c8 Language SPICE circuit sram pbulk nbulk word vdd b_vss t_vss cl c2 bit notbit vdd cl c2 pbulk penh 0 w 500n 1 500n vdd c2 cl pbulk penh 0 w 500n 1 500n b_vss cl c2 nbulk nenh 0 w 500n 1 500n t_vss c2 cl nbulk nenh_0 w 500n 1 500n notbit word c2 nbulk nenh_O w 500n 1 500n bit word cl nbulk nenh 0 w 500n 1 500n b vss word 114 8418e 18 b_ vss vdd 43 84559e 18 b vss c2 74 07894e 18 b vss cl 212 2093e 18 b_ vss notbit 610 2131e 18 b vss GND 1 80899f notbit bit 107 3521le 18 notbit word 115 7189e 18 The Nelsis IC Design System Space 3D Capacitance Extraction 23 c9 notbit vdd 6 609526e 18 notbit c2 360 5527e 18 notbit cl 66 39646e 18 notbit GND 2 597815f t_vss word 114 8457e 18 t_vss vdd 43 82953e 18 t_vss bit 610 33e 18 t_vss C2 212 2309e 18 t_vss cl 73 7881e 18 t_vss GND 1 808788f word bit 115 8338e 18 word c2 113 7943e 18 c21 word cl 111 6566e 18 c22 word GND 344 449e 18 c23 vdd bi
8. computation of a double surface integral but G becomes symmetrical which is advantageous for computing the inverse of the elastance matrix In the collocation boundary element method 4 the weight functions w are chosen equal to Dirac functions In this case the computation of G requires the evaluation of only single surface integrals G is artificially made symmetrical by using the average of the two entries that are at a symmetrical position A 3 Approximate Matrix Inversion Normally the inversion of the elastance matrix G in A 13 requires O N i time and O N 2 space To allow fast extraction times also for large circuits space is capable of computing an approximate inverse for G Therefore it utilizes a matrix inversion technique that takes as input a matrix that is specified on a stair case band around the main diagonal and produces as output a matrix in which only non zero entries occur for the positions that correspond to positions in the stair case band The basic idea is illustrated in Figure A 2 In Figure A 2 different approximations are computed for a simple boundary element mesh that consists of 4 elements and that is described by the following elastance matrix 1 0 0 4 0 2 0 1 0 4 1 0 0 4 0 2 0 2 0 4 1 0 0 4 A 14 0 1 0 2 0 4 1 0 For practical layouts the method proceeds as follows First the layout is subdivided into strips of width w see Figure A 3 All influences between elements that are within a distan
9. le 6 meter conductors name condition mask resistivity type cond m cmf emf 0 045 m first metal cond ms cms cms 0 030 m second metal cond pg cpg Cpg 40 m poly interconnect cond_pa caa cpg csn caa 70 p p active area cond na caa cpg csn caa 50 n n active area fets name condition gate d s nenh cpg caa csn cpg caa nenh MOS penh cpg caa csn cpg caa penh MOS contacts name condition layl lay2 resistivity cont_s cva cms cmf cms cmf 1 metal to metal2 cont _p ccp cmf cpg cmf cpg 100 metal to poly The Nelsis IC Design System Space 3D Capacitance Extraction 20 cont_a cca cmf caa cpg cmf caa 100 metal to active area capacitances active area capacitances name condition mask mask2 capacitivity acap_na caa cpg csn cwn gnd caa 100 n bottom ecap_na caa cpg csn cwn caa gnd caa 300 n sidewall acap _pa caa cpg csn cwn caa gnd 500 p bottom ecap _pa caa cpg csn cwn cwn caa caa gnd 600 p sidewall polysilicon capacitances acap_cpg_sub cpg caa cpg gnd 49 bot to sub ecap_cpg_ sub cpg cpg cmf cms caa cpg gnd 52 edge to sub first metal capacitances acap_cmf sub cmf cpg caa cmf gnd 25 ecap_cmf_sub omf cmf cms cpg caa cmf gnd 52 acap_cmf_caa emt caa cpg cca cca cmf caa 49 ecap_cmf_caa cmf cmf caa cms cpg cmf caa 59 acap_cmf_cpg cmf cpg ccp cmf cpg 49 ecap_cmf_cpg omf cmf cpg cms cmf cpg 59 second metal
10. main diagonal is computed complexity that is O Nw and a memory usage that is O w So when w is kept constant which is reasonable if one type of technology is used the computation complexity of the method is linear with the size of the circuit and the space complexity is constant The Nelsis IC Design System Space 3D Capacitance Extraction 30 Figure A 3 A layout subdivided into strips of width w The Nelsis IC Design System Space 3D Capacitance Extraction 31 References 1 E Weber Electromagnetic Fields Theory and Applications John Wiley amp Sons Inc New York 1957 P Dewilde and Z Q Ning Models For Large Integrated Circuits Kluwer Academic Publishers 1990 Z Q Ning P M Dewilde and F L Neerhoff Capacitance Coefficients for VLSI Multilevel Metallization Lines IEEE Trans on Electron Devices ED 34 3 pp 644 649 March 1987 Z Q Ning and P Dewilde SPIDER Capacitance Modelling for VLSI Interconnections IEEE Trans on Computer Aided Design 7 12 pp 1221 1228 December 1988 N P van der Meijs and A J van Genderen An Efficient Finite Element Method for Submicron IC Capacitance Extraction Proc 26th Design Automation Conference Las Vegas pp 678 681 June 1989 A J van Genderen Reduced Models for the Behavior of VLSI Circuits Ph D Thesis Delft University of Technology Network Theory Section Delft the
11. A 2 Figure A 3 LIST OF FIGURES Illustration of the heuristic approach to incorporate diffusion capacitances physical structure a and 3D capacitance model b Different types of shape or basis functions that can be used to model the surface charge density on the conductors a Dirac b constant f is described by the top of the wedge c linear fis described by the 4 slanting planes of the pyramid a Exact solution b only diagonals 1 3 are computed c only diagonals 1 2 are computed d only the main diagonal is computed A layout subdivided into strips of width w iii 27 29 30
12. S transistor source and drain regions are described in a somewhat different way than the poly silicon and the metal conductors The approach is illustrated in Figure 3 1 metal metal diff model TS locos diff field implant ground a b Figure 3 1 Illustration of the heuristic approach to incorporate diffusion capacitances physical structure a and 3D capacitance model b Figure 3 l a shows a cross sectional view of a diffused conductor The capacitance model employed by space for such a conductor is shown in Figure 3 1 b where the diffused interconnect is replaced by a thin sheet conductor Therefore the user must specify in the element definition file a zero thickness for the conductor The sheet conductor is positioned half the thickness of the field oxide above the ground plane which is flat and continuous and must be thought of as modeling the top side of the diffused conductors Initially the 3D capacitance extraction method will compute 3D capacitances between all conductors and ground The 3D capacitances between non diffused conductors mutually between non diffused conductors and ground and between non diffused The Nelsis IC Design System Space 3D Capacitance Extraction 8 conductors and diffused conductors are inserted in the extracted circuit However the 3D capacitances between diffused conductors and ground and between diffused conductors mutually are better repr
13. SPACE 3D CAPACITANCE EXTRACTION USER S MANUAL A J van Genderen N P van der Meijs Department of Electrical Engineering Delft University of Technology The Netherlands Report ET NT 94 37 Copyright 1994 1999 by the authors All rights reserved Last revision Aug 1999 Space 3D Capacitance Extraction 1 1 Introduction 1 1 3D Capacitance Extraction Parasitic capacitances of interconnects in integrated circuits become more important as the feature sizes on the circuits are decreased and the area of the circuit is unchanged or increased For submicron integrated circuits where the vertical dimensions of the wires are in the same order of magnitude as their minimum horizontal dimensions 3D numerical techniques are even required to accurately compute the values of the interconnect capacitances This document describes the layout to circuit extraction program space that is used to accurately and efficiently compute 3D interconnect capacitances of integrated circuits based upon their mask layout description The 3D capacitances are part of an output circuit together with other circuit components like transistors and resistances This circuit can directly be used as input for a circuit simulator like SPICE 1 2 Space Characteristics To compute 3D interconnect capacitances space uses a boundary element method In the boundary element method elements are placed on the boundaries of the interconnects This has as an advan
14. acted unit vdimension le 6 meter conductors metall in in 0 metal2 ins ins 0 vdimensions metall shape in in 1 6 1 0 metal2 shape ins ins 3 3 1 2 ins 1 2u 1 0u in 3 34 1 6u STILT IT AT At a transition area where a conductor goes from one bottom and thickness specification to another bottom and thickness specification the slope of the conductor is determined by the parameter default_step_slope see Section 4 2 NOTE To prevent the overlap of different transition areas of one conductor which currently results incorrect element meshes the differences in bottom and thickness specifications of one conductor may not be too large otherwise increase the parameter default_step_slope See Section 3 6 for a specification of diffused conductors The Nelsis IC Design System Space 3D Capacitance Extraction 6 3 4 The edge shape list Syntax eshapes name condition_list s mask dxb dxt The edge shape list specifies for different conductors the extension of each conductor in the x direction relative to the position of the original conductor edge in the layout The first value dxb specifies the extension of the bottom of the conductor and the second value dxt specifies the extension of the top of the conductor Either extension may be negative The edge shape list should be present in the element definition file after the vertical dimension list Example esh
15. apes metall_ eshape in in in 0 2 0 1 j PN in Tozu 97777777777 NOTE In some cases the use of eshapes may cause mesh generation problems because e g at corners the order of mesh nodes can get mixed up 3 5 Dielectric Structure Syntax dielectrics name permittivity bottom Specifies the dielectric structure of the chip This specification is included in the element The Nelsis IC Design System Space 3D Capacitance Extraction 7 definition file after the vertical dimension list and the edge shape list Up to 3 dielectric layers can be specified For each layer name is an arbitrary label that will be used for error messages etc permittivity is a real number giving the relative dielectric constant and bottom specifies in microns the bottom of the dielectric layer The value of bottom must be 20 The first dielectric in the list specifies the lowest dielectric the second dielectric the second lowest etc For the first dielectric layer bottom must be zero The top of a dielectric layer is at the bottom of the next dielectric The top of the last dielectric is at infinity No dielectric layers means vacuum If one or more dielectric layers are specified a ground plane at zero is present Example dielectrics Dielectric consists of 5 micron thick Si02 epsilon 3 9 on a conducting plane SiO2 3 9 0 0 air 1 0 5 0 3 6 Diffused conductors Diffused conductors which for example implement the MO
16. are specified in the unit specification of the element definition file A unit for the vertical dimension list is specified by means of the keywords unit and vdimension followed by the value of the unit A unit for the edge shape list is specified by means of the keywords unit and shape followed by the value of the unit Example The following specifies a unit of 1 micron for distances that are given in the vertical dimension list and for distances that are given in the edge shape list unit vdimension le 6 Micron unit shape le 6 Micron 3 3 The vertical dimension list Syntax vdimensions name condition_list s mask bottom thickness The vertical dimension list specifies for different conductors under different conditions e g metal2 above polysilicon or metal2 above metall 1 bottom the distance between the substrate and the bottom of the conductor 2 thickness the thickness of the conductor The vertical dimension list is included in the element definition file after the specification of the standard non 3D elements see the Space User s Manual The Nelsis IC Design System Space 3D Capacitance Extraction 5 Example An example of an almost minimal technology file with corresponding geometry is given below While minimal this file can actually be complete except for a specification of the dielectric structure for 3D extraction for a double metal process in which only metall and metal2 capacitances are extr
17. capacitances acap_cms_sub cms cmf cpg caa cms gnd 16 ecap_cms_sub cms cms cmf cpg caa cms gnd 51 acap_cms_ caa cms caa cmf cpg cms caa 25 ecap_cms caa cms cms caa cmf cpg cms caa 54 acap_cms cpg cms cpg cmf cms cpg 25 ecap_cms cpg cms cms cpg cmf cms cpg 54 acap_cms_cmf cms emf cva cms cmf 49 ecap_cms_cmf cms cms cmf cms cmf 61 lcap_cms cms cms cms cms cms 0 07 vdimensions ver _caa_on_all caa cpg caa 0 30 0 00 ver _cpg of caa cpg caa cpg 0 60 0 50 ver cpg on _caa cpg caa cpg 0 35 0 70 ver_cmf emf emf 1 70 0 70 ver _cms cms cms 2 80 0 70 eshapes cpg edge cpg cpg cpg 0 0 emf edge emf cmf emf 0 0 cms edge cms cms cms 0 0 The Nelsis IC Design System Space 3D Capacitance Extraction 21 dielectrics Dielectric consists of 5 micron thick SiO2 epsilon 3 9 on a conducting plane Si02 3 9 0 0 air 1 0 5 0 EOF Note that for the diffusion area a conductor of thickness 0 is used that is 0 30u above the substrate The contents of the parameter file sram p is as follows BEGIN cap3d be_mode Oc be_window max be_area 1 0 omit_gate_ds_cap on END cap3d After running tecc on the element definition file tecc sram s extraction in batch mode is done by using space3d space3d C3 E sram t P sram p sram For interactive extraction Xspace is used Xspace E sram t P sram p Click button sram in the menu database click button coupling cap and 3D
18. ce w will be taken into account and all influences between elements that are more than a distance 2w apart will not be taken into account Next a banded approximation according to Figure A 2 is computed whereby only influences are taken into account between elements that are in the y direction within a distance w for 1 each pair of adjacent strips and 2 each single strip except for the first and last strip The results that are obtained for the pairs of strips are added to the total result and the results that are obtained for the single strips are subtracted from the total result 5 6 7 By executing all steps of the extraction method as a scanline is swept over the layout from left to right the extraction method can be implemented to have a computation The Nelsis IC Design System Space 3D Capacitance Extraction 29 Ae 0 007 9 es X X X X Reh eae 1 2 3 d 4 X X X X _ 0454 0 434 0454 X X X X r 0 678 TT 0 424 T 0 424 T 0 678 a Fes a 0089 N oe He is alts S oe X X X X lL o4s5s 043 0455 ae 0 681 T 0 421 T 0 421 T 0 681 b X x e AO X X x 0476 046 047 x Xx p 0 714 T 0 429 T 0 429 T 0 714 c x J 7 x i IB aler x r 1 7 1 r 1 7 1 d Figure A 2 a Exact solution b only diagonals 1 3 are computed c only diagonals 1 2 are computed d only the
19. dent weight functions wi w2 wy that are defined on the sub areas Si S2 Sy and that are used to average out the error in 0 p The Nelsis IC Design System Space 3D Capacitance Extraction 27 Figure A 1 n fip _ f p a b o Different types of shape or basis functions that can be used to model the surface charge density on the conductors a Dirac b constant f is described by the top of the wedge c linear f is described by the 4 slanting planes of the pyramid wo p 0 dp 0 G 1 N A6 By insertion of A 5 the above set of equation may be rewritten as N E e Gir 2 fq wip da dp wi p 0D ap Si C 12 N A 7 Now let F be an NXM incidence matrix in which 1 if S is on conductor j as 0 otherwise A 8 Then Equation A 7 may be written as a set of NXN equations Ga WF A 9 where G is an NXN matrix that has entries G Go 2 fq wilp dq dp A 10 S S al O Oo Qy and W is an NXN matrix that has entries W 0 iA A 1la Wii w p dp A 11b The conductor charges are found from A 9 as The Nelsis IC Design System Space 3D Capacitance Extraction 28 O F a F G WF A 12 Thus the short circuit capacitance matrix C is obtained from A 12 as C F G W F A 13 In the Galerkin boundary element method 3 the weight functions w are chosen equal to the shape functions This way the evaluation of G requires the
20. esented by junction capacitances that are computed using an area perimeter method NOTE Therefore the 3D capacitances between diffused conductors and ground and between diffused conductors mutually are discarded by the program The junction capacitances that replace these capacitances have to be specified separatedly by the user in the element definition file See also Section 3 8 Although this approach is purely heuristic its results are satisfactory when the width of the diffusion paths is large enough compared to the height of the sheet conductors above the ground plane NOTE A conductor is defined as a diffused conductor within space if and only if in the element definition file of space the type of the conductor is specified as n or p 3 7 Gate capacitances When extracting 3D capacitances space assumes that the gate channel capacitances of field effect transistor are included in the simulation model that is used for the extracted transistor Therefore it discards the 3D capacitance to ground for conductor parts that are a gate of a field effect transistor and that are directly above the transistor area as defined in the element definition file Also the 3D coupling capacitances between gates and diffused conductors drain source areas see Section 3 6 can be discarded by the program depending whether they are present in the SPICE or other simulation model for the device This is achieved by turning on the parame
21. irst try an extraction with a parameter set that does not include many details Next a parameter set is used in which more details are included and the extraction results are evaluated to inspect the influence of the parameters See also Section 4 8 6 2 Numerical Problems If the elastance matrix see Section A 2 is badly conditioned space may be unable to invert this matrix and it may give error messages like domain error s in sqrt One reason for a badly conditioned elastance matrix is that there is too much difference in element sizes A solution in this case is to split the large elements either by decreasing the maximum size of the elements or by adding irregularities to the layout using a symbolic mask If very thin conductors are used the difference between the small vertical elements and the large horizontal elements may also become too large In this case it may for example be better to specify a zero thickness for the conductor in the element definition file In general the creation of small elements that are close to large elements and the creation of long and narrow elements should be avoided Also the use of the Galerkin method mode Og or 1g instead of the collocation method mode Oc might help in the above case Mode 1g will even be more robust than mode Og 6 3 Negative Capacitances Some element meshes may also give rise to negative capacitances Negative capacitances may for example occur when conductors are clo
22. n a height of 0 5 micron and their separation is also 0 5 micron The Nelsis IC Design System Space 3D Capacitance Extraction 15 An appropriate element definition file with name tech s is as follows cat tech s colors cpg red unit vdimension le 6 meter conductors resP cpg cpg 0 0 vdimensions dimP cpg cpg 0 5 0 5 dielectrics Dielectric consists of 5 micron thick Si02 epsilon 3 9 on a conducting plane SiO2 3 9 0 0 air 1 0 5 0 6 Furthermore we use the following parameter file param p cat param p BEGIN cap3d be_mode Oc max _be_ area 0 5 be_window 1 END cap3d 6 Then after having run tecc on the element definition file tecc tech s we extract a circuit description for the layout of the cell as follows space3d C3 E tech t P param p poly5 Alternatively Xspace can be used Xspace E tech t P param p Click button poly5 in the menu database click button coupling cap and 3D capacitance in the menu options click button DrawBEMesh DrawGreen and 3 dimensional in the menu display and click button extract in the menu Extract This will yield the following picture The Nelsis IC Design System Space 3D Capacitance Extraction 16 Extract atabase options The circuit that has been extracted can be inspected using the program xspice xspice a p
23. oly5 poly5 Generated by xspice 2 28 14 Apr 1999 Date 23 Jun 99 11 38 14 GMT Path users space poly5 Language SPICE circuit polyS e d c b a cl a b 253 3438e 18 c2 a GND 624 5254e 18 c3 b c 253 3438e 18 c4 b GND 458 1579e 18 c5 c d 253 3438e 18 c6 c GND 458 1579e 18 c7 e d 253 3438e 18 c8 e GND 624 5254e 18 c9 d GND 458 1579e 18 end poly5 Note that there are no capacitances between conductors that are more than a distance 2 be_window apart e g conductor a and conductor d or conductor a and conductor e In The Nelsis IC Design System Space 3D Capacitance Extraction the table below the capacitances of conductor a are given as a function of the window size In the column denoted by C the short circuit capacitance of node a is given which is the sum of all capacitances that are connected to a Note that the value of this capacitance is almost independent on the size of the window w capacitances 10 F u Ca gnd Ca b Ca c Ca d Ca e C a 1 624 5 253 3 877 8 2 5999 256 0 16 35 7 93 880 2 3 593 4 256 8 1664 7 14 4 0 878 5 4 591 0 257 3 17 11 7 22 473 877 4 5 590 5 257 4 17 18 7 27 4 79 877 1 The Nelsis IC Design System Space 3D Capacitance Extraction 18 5 2 Cmos Static RAM Cell The next example consists of a cmos static RAM cell in 0 5u technology To run the example first create a project e g with name exam2 for an scmos_n process and with
24. p_max_order 0 3 default 2 Specifies the highest multipole to be included in the multipole expansion For 0 only the monopole is included for 1 also the dipole and so forth The highest implemented value is 3 octopole because on the one hand this typically suffices for a precision of one per mil while on the other hand the required CPU time increases drastically with the number of multipoles 4 4 Accuracy of Elastance Matrix cap3d green_eps error default 0 001 Positive real value specifying the relative accuracy for evaluating the entries in the elastance matrix cap3d max_green_terms number default 500 For dielectrics consisting of more than one layer more than one term iteration will in The Nelsis IC Design System Space 3D Capacitance Extraction 12 general be necessary to find an approximation of the Green s function such that the error in the entries in the elastance matrix is within cap3d green_eps see above This parameter specifies the value for the maximum number of terms that may be used The upper bound of this parameter is 500 4 5 Window Size cap3d be_window w cap3d be_window wx wy Specifies the size in micron of the influence window All influences between elements that are within a distance w will be taken into account and all influences between elements that are more than a distance 2w apart will not be taken into account see Section A 3 If only one value is given this value specifie
25. s consisting of 2 or 3 dielectric layers may require much more computation time than the same computation for configurations consisting of 1 dielectric layer This is because the computation of the Green s functions requires much more time In this case the computation time can be decreased on the penalty of some loss in accuracy by increasing the value for the maximum error for the evaluation of the entries in the elastance matrix green_eps The Nelsis IC Design System Space 3D Capacitance Extraction 14 5 Examples 5 1 5 Parallel Conductors As a first example we show how space is used to compute 3D capacitances for a configuration consisting of 5 parallel conductors To run the example first create a project e g with name exam1 for an scmos_n process and with lambda is 0 05 mkpr examl available processes process id process name 3 scmos_n 23 dimes01 select process id 1 23 3 enter lambda in microns gt 0 001 0 05 mkpr project created Next go to the project directory and copy the example source files from the directory cacd demo polyS it is supposed that the demo directory has been installed under cacd oe cd examl cp cacd demo poly5 ol The layout description is put into the database using the program cgi cgi poly5 gds The layout of the configuration is shown below e g use Xdali to inspect the layout The conductors have a length of 5 micron a width of 0 5 micro
26. s the size of the window in the x direction and the y direction If two values are given the first value specifies the size of the window in the x direction and the second value specifies the size of the window in the y direction The extraction time is proportional to O Nw where N is the number of elements The memory usage of the program is O w A reasonable value for be_window is 1 3 times the maximum height of the circuit No default 4 6 Discarding 3D Capacitances cap3d omit_gate_ds_cap boolean default off Do not extract 3D capacitances between gates and diffused conductors drain source areas see Section 3 7 4 7 Example Parameter File An example of parameter settings for 3D capacitance extraction is as follows BEGIN cap3d max_be area 1 0 be_window 5 0 END cap3d 4 8 Run time Versus Accuracy The runtime of the program is largely dependent on the values of the parameters that are used For example if max_be_area is decreased smaller elements are used the accuracy will increase but also the number of elements will increase and the computation The Nelsis IC Design System Space 3D Capacitance Extraction 13 time will become larger The larger the size of the window the more accurate results are obtained but also longer extraction times will occur The Galerkin method is more accurate than the collocation method but it also requires more computation time Also 3D capacitance computation for configuration
27. se to each other and relatively large elements are used A typical example is the situation where the bottom of a transistor gate approaches its adjacent drain source regions More accurate results without negative capacitances are then obtained by 1 decreasing the maximum size of the elements and or 2 increasing the height of the bottom of the gate above the substrate If necessary the parameters min_coup_cap and or no_neg_cap can be set to The Nelsis IC Design System Space 3D Capacitance Extraction 25 remove the remaining small negative capacitances 6 4 Mesh Generation Problems If space gives error messages like mesh c 846 assertion failed or refine c 507 assertion failed there is something wrong with mesh generation This problem is often caused by the modeling of the steps in height above the substrate of the conductors If the slope of a conductor near such a transition area is too small different transition areas may overlap and the program will not be able to generate a correct mesh see Section 3 3 and Section 4 2 Mesh generation problems may also be caused by the use of eshapes see Section 3 4 and by the fact that because of the use of a window parameter cap3d be_window long and narrow mesh elements may be generated The Nelsis IC Design System Space 3D Capacitance Extraction 26 Appendix A 3D Capacitance Model A 1 Introduction Space uses a boundary element method to compute 3D capacitances
28. sented in this manual that are also available on line We will assume that the space software has been installed under the directory cacd The examples are then found in the directories cacd demo poly5 and cacd demo sram respectively The Nelsis IC Design System Space 3D Capacitance Extraction 3 2 Program Usage 2 1 General 3D capacitance extraction can be performed using one of the following versions of space space3d for batch mode extraction and Xspace for interactive extraction and mesh visualization Both these tools can also be used from within the graphical user interface helios Normally when performing a 3D capacitance extraction a flat extraction will be executed This implication can be disabled when turning on the parameter allow_hierarchical_cap3d 2 2 Batch Mode Extraction In order to use the 3D capacitance extraction mode of space3d use the option 3 Also use either the option c or the option C In both cases 3D ground and coupling capacitances are computed However only in the second case all these capacitances will be part of the output circuit In the first case all coupling capacitances will be reconnected to ground 2 3 Interactive Extraction For 3D capacitance extraction it may be helpful to use a special version of space that is called Xspace This version runs under X windows and uses a graphical window to among other things show the 3D mesh that is generated by the program Interacti
29. t 6 602351le 18 c24 vdd c2 56 77325e 18 c25 vdd c1 58 65705e 18 c26 vdd GND 9 5875f c27 bit c1 360 2216e 18 c28 bit c2 67 05357e 18 c29 bit GND 2 597536f c30 c2 c1 998 1218e 18 c31 c2 GND 5 426257f c32 cl GND 5 425884f end sram Fk f Fr O n a H Ww 4 n n H 00 Q O OA OA OTO A Q N F O wo model penh 0 pmos level 2 ld 0 tox 25n nsub 50e15 vto 1 10 uo 200 uexp 100m ucrit 10k delta 200m xj 500n vmax 50k neff 1 rsh 0 nfs 0 js 10u cj 500u cjsw 600p mj 500m mjsw 300m pb 800m cgdo 300p cgso 300p model nenh 0 nmos level 2 ld 0 tox 25n nsub 20e15 vto 700m uo 600 uexp 100m ucrit 10k delta 200m xj 500n vmax 50k neff 1 rsh 0 nfs 0 js 2u cj 100u cjsw 300p mj 500m mjsw 300m pb 800m cgdo 300p cgso 300p vpbulk pbulk 0 5 rpbulk pbulk 0 100meg vnbulk nbulk 0 0 rnbulk nbulk 0 100meg The Nelsis IC Design System Space 3D Capacitance Extraction 24 6 Solving Problems 6 1 Long Computation Times Although space has been implemented with emphasis on efficient 3D capacitance extraction methods sometimes long extraction times may occur This for example happens if too much time is spend on the computation of irrelevant details This is for example the case if the size of the elements is chosen too small if the window size is unnecessary large or if linear shape functions and the Galerkin method are used for too many elements A good strategy to circumvent this problem is to f
30. tage over the finite element and the finite difference method where the domain between the conductors is discretized that especially for 3D situations a lower number of discretization elements is used However a disadvantage of the boundary element method is that in order to compute the capacitance matrix it requires the inversion of a full matrix of size NXN where N is the total number of elements This takes O N 3 time and O N 2 memory To reduce the complexity of the above problem space employs a new matrix inversion technique that computes only an approximate inverse In practice this means that only coupling effects are computed between nearby elements and that no coupling capacitances are found between elements that are far apart For flat layout descriptions this method has a computation complexity that is O N and a space complexity that is O 1 As a result space is capable of quickly extracting relatively large circuits gt 100 transistors and memory limitations of the computer are seldom an insurmountable obstacle in using the program 1 3 Documentation Throughout this document it is assumed that the reader is familiar with the usage of space as a basic layout to circuit extractor i e extraction of transistors and connectivity This document only describes the additional information that is necessary to use space The Nelsis IC Design System Space 3D Capacitance Extraction 2 for 3D capacitance extrac
31. ter cap3d omit_gate_ds_cap in the parameter file 3 8 Non 3D capacitances When extracting 3D capacitances non 3D capacitances that are specified in the element definition file are not extracted except for capacitances between a diffused conductor and ground and capacitances between diffused conductors mutually see also Section 3 6 The Nelsis IC Design System Space 3D Capacitance Extraction 9 4 3D Capacitance Computation 4 1 Introduction Space uses a boundary element method to compute 3D capacitances see Appendix A Since there are several degrees of freedom with this method there are also several parameters that can be set with space during 3D capacitance extraction A brief description of these parameters is given below For more background information on the parameters the reader is referred to Appendix A The parameters are set in the space parameter file see also the Space User s Manual All lengths and distances are specified in micron and all areas are specified in square micron All parameters that have a name starting with cap3d may be used without this prefix if they are included between the lines BEGIN cap3d and END cap3d E g BEGIN cap3d max_be area 1 be_shape 3 END cap3d is equivalent to cap3d max_be_ area 1 cap3d be_ shape 3 4 2 Mesh Construction cap3d default_step_slope slope default 2 0 Specifies the tangent of the slope of conductors i e the tangent of in the figure below
32. tion The usage of space as a basic layout to circuit extractor is described in the following documents space user s manual This document describes all features of space except for the 3D capacitance extraction mode It is not an introduction to space for novice users those are referred to the space tutorial space tutorial The space tutorial provides a hands on introduction to using space and the auxiliary tools in the system that are used in conjunction with space It contains several examples space tutorial helios version The same tutorial as above but now described under the assumption that the graphical user interface helios is used to run the extraction tools manual pages For space as well as for other tools that are used in conjunction with space manual pages are available describing the usage of these programs The manual pages are on line available as well as in printed form The on line information can be obtained using the icdman program Xspace user s manual This short manual describes the usage of Xspace the interactive graphical X window version of space Xspace is also part of helios and can best be run from there Also available space substrate resistance extraction user s manual This manual describes how resistances between substrate terminals are computed in order to model substrate coupling effects in analog and mixed digital analog circuits 1 4 On line Examples Two examples are pre
33. vely the user can select the cell that is extracted the options that are used and the items that are displayed However for a complete graphical interface to all extraction tools it is better to use the graphical user interface helios that includes space3d as well as Xspace For 3D capacitance extraction using Xspace turn on 3D capacitance and either coupling cap or capacitance in the menu options To display also the 3D mesh click on DrawBEMesh and 3 dimensional and possibly DrawGreen in the menu display Then after selecting the name of the cell in the menu database the extraction can be started by clicking on extract in the menu Extract To preview the mesh for 3D capacitance computation use Xspace as described above and also turn on BE mesh only The Nelsis IC Design System Space 3D Capacitance Extraction 4 3 Technology Description 3 1 Introduction For 3D extraction the space element definition file is extended with a description of the vertical dimensions of the conductors optionally a description of the edge shapes of the conductors and a description of the dielectric structure of the circuit Information about these specifications is given below For basic information about the development of an element definition file see the Space User s Manual 3 2 Unit specification Optionally the unit for distances in the vertical dimension list and the unit for distances in the edge shape list
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