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User Manual - TTC Upgrade

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1. y s s i mE a LE do gt LN G 8 ES as NES li t W _ uw O ri Picture 2 2 1 b important points in the board EDA 1382 Block Signal Vref Value Light Green OCP Place socket Supported Not adjustable Truelight Place socket Not supported CT TC pero eee ae eee VIOLET UP RES 3 3 Volts supply Only one connected VIOLET DOWN RES 5 Volts supply Only one connected oe ee eee PINK RESISTORS Truelight signal selected when ORO res Are placed RED RESISTORS OCP signal selected when res Are placed back side CE TC res St BLUE RESISTORS Resistor unbalancing the when ORO res Thevenin Network manually BLUE INDUCTANCE FPGA Control Thevenin when placed 1uH Table 2 2 1 Block description PH ESS Document No 7 of 30 PH ESE 30 07 08 02 2 2 1 1 PHOTODIODE SELECTION DEPENDING OF THE SIGNAL TO TRANSMIT To the table below summarizes a review coming from the Laser and Photodiodes Evaluation that shows the bandwidth and signal types that each Photodiode can receive For more information and characteristics check the evaluation document or datasheets Photodiode Bandwidth Signal Supported Threshold Thevenin adjustable OCP SRX 03 Time of bit Tb lt 10us to 2ns 10MHz square YES NO Freq 100 KHz to 250 MHz OCP SRX 03 Tb gt 10us 10KHz square NO NO Freq gt 300Mhz ons width 11Khz pulse
2. 30 07 08 02 2 3 3 3 FREQUENCY COUNTERS CH1 Offset Size Access CH2 Name Offset Size Access CH3 Offset Size Access The full 32 bits frequency register must be read in a special order which is from LSW to MSW If not the 32 bits register won t be updated the right way These registers are generated by internal counters that count the number of rising clocks between rising edges in the received signals In order to measure higher frequencies than the clock frequency a frequency divider has been installed on the board 4 hardware Flips Flops gt 1 16 and inside the FPGA software divider 1 22 Every counter has a size of 32 bits that is divided in two registers of 16bits that must be read separately due to the fact that the board has only A24 D16 access In order to calculate the frequency the equation is 380 e168 22 Freq FreqLow FreqHighe 65536 This multiplication must be done in LONG UNSIGNED INT or FLOAT PH ESS Document No 20 of 30 PH ESE 30 07 08 02 Examples Frequency ValueReg1 Value Reg2 Frequency Original MHz Measured MHz 00000 ox0800 40 078 0x0000 OxO2BF 40 0568 0x0000 OxO2BE 40 113 400 78 0x0000 0x0047 396 619 0x0000 0x0046 402 285 Pulse 1MHz 0x0000 0x6e00 Pulse 11 245KHz 0x0026 0x361A 11 245027KHz OxFFFF OxFFFF 6Hz Table 2 3 3 4 Typical examples of values of the frequency co
3. Example OCP SRX 24 Tb lt 10us to 115 10MHz square YES NO Freq 100 KHz to 500 MHz 400MHz square om OCP SRX 24 Tb gt 10us 10KHz square NO NO pulse LL Truelight 50KHz to 400Mhz 10MHz square YES YES 400MHz square Truelight Tb high 16us Positive pulses YES YES maximum 16us width Table 2 2 1 1 Signals supported by each photodiode 2 2 1 2 PHOTODIODE CONFIGURATION THRESHOLD AND SELECTION The table below shows a brief summary of the necessary adjusts that need to be done in each channel to select the photodiode that is going to be used PH ESS Document No 8 of 30 PH ESE 30 07 08 02 Photodiode Mode Components to replace Manual HW FPGA SW OCP NOT THRESHOLD OCP CONNECTED GREEN LIGHT DARK BLUE DB don t care LIGHT BLUE LB don t care PINK RESISTORS PR disconnected RED RESISTORS RR connected VIOLET RES VR just ORO in bottom 5V Truelight MANUAL THRESHOLD TRUELIGHT CONN GREEN DARK DARK BLUE DB 100hms resistor LIGHT BLUE LB disconnected PINK RESISTORS PR connected RED RESISTORS RR disconnected VIOLET RES VR just ORO in bottom 5V Truelight THRESHOLD ADJUSTABLE DARK BLUE DB Oohms resistor LIGHT BLUE LB connected 1uH PINK RESISTORS connected RED RESISTORS RR disconnected VIOLET RES VR just ORO in bottom 5V Table 2 2 1 2 photodiode selection table PH ESS Document No 9 of 30 PH ESE 30 07 08 02
4. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk In case that another photodiode is going to be used it has to be connected on OCP place if the Output format is pure PECL for all the bandwidth TRUELIGHT place if the Output is differential NO PECL with AGC in the last stage of the preamplifier or with and internal AC coupled in the output In both cases the voltage must be selected between 3 3V and 5V with the Violet Resistors kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk In FPGA mode VME FPGA who unbalances the Thevenin network For this it is necessary write in the Vref Register a value different from 0 This makes it possible to unbalance the network from 0 to 750mv 2 2 1 3 SIGNAL DETECTION CIRCUIT The signal Detection circuit works ONLY with the OCP SRX photodiode This circuit will translate the signal detection state from the OCP to the Front panel A LED on the FP indicates the presence of optical power in each channel through a GREEN light or the absence with a RED light In a future Firmware version signal detection for Truelight Photodiodes based on the frequency of the received signal will be added Meanwhile the Frequency detectors registers can be used to know the signal presence 2 2 2 PHOTODIODES MODULES POST PROCESSING LOGIC The post processing logic is based on a few ECL gates that will increase the sig
5. has been written by Markus Joos 2 4 1 MANUAL CALIBRATION FIX VREF VALUES This configuration will be applied when a VME controller is not present or block the references to avoid third part modifications or intromission The manual modification is done by modifying the Resistors R and disconnecting de soldering the inductance more information about full Truelight Set UP in section 2 2 1 PH ESS Document No 23 of 30 PH ESE 30 07 08 02 Inductance Picture 2 4 1a Manual Calibration set UP In order to calculate the R convenient the user must follow the equation Vdiff V 120 e d 602 602 _ 202 Vdiff Vece 0 594 Vdiff Or the next Graphs PH ESS Document No 24 of 30 PH ESE 30 07 08 02 O 20 40 60 80 100 Vdiff mV Pictures 2 4 1b Calibration Graphs PH ESS Document No 25 of 30 PH ESE 30 07 08 02 2 4 2 THROUGH VME KNOWING THE SIGNALS AND PHOTODIODES USED The calibration can be done with monitor software like rfrxscope By Markus Joos or with readRXD monitor Tcl application that run over Markus Joos Vme_Drivers If the user is close to the board and knows the type of receivers that are mounted and which signal type they are receiving Then apply these rules Photodiode Signal Vref Value OCP SRX 03 1Mhz to 100Mhz clocks No adjustment required OCP SRX 03 400Mhz or Pulses clocks Don t care Not supp
6. see below the module is measuring the frequency of the noise And it is possible that the measured frequency of the picked up noise recognised as a good one So never put less than 0x5 on the VREF registers Here are some details about these registers CHX REF are a group of register that control the previously mentioned Thevenin Network in the 3 channels The values of these registers will be sent to the DAC to modify the network The modification is linear and follows the equation PH ESS Document No 16 of 30 PH ESE 30 07 08 02 Voff 02 R gt VcceR 602 3 02 R Voff mV DACvalue 4 7mV Vdiff V 120 Where Vdiff is the differential voltage between the differential lines Voff is the DAC voltage value R is the Manual Thevenin modifier Supposing a R20 we can obtain this graph where is possible to select graphically the value for the register the value is in Decimal do not forget to change to hexadecimal 00 00 600 00 900 00 400 00 Vdiff mV 300 00 Optimal Value for Si 100 150 Registe e DEC a Default value for everything TRR Optimal value for pulse TRR 0x15 Picture 2 3 3 3a Vdiff variation with Vref register PH ESS Document No 17 of 30 PH ESE 30 07 08 02 Positive Reference for BOTH LINES Negative pulse Noise when low level is keep more than 10us Picture 2 3 3 3b Positive pulse in balanced Thevenin network Posi
7. the Signals and Photodiodes a 25 2 5 Board configuration Jumpers and switch 28 2 6 Fibre 7 cable GCONMC CHONG uuu u uu uuu u ANNA KA CAN u uuu E ose u u u NAG u 2 VORNE EGENTES 28 2 7 Fron panel LEDS 29 2 8 References or more information 29 EIC COMMON SOM 30 3 3 Ne Ce ir u ne a AA AA PAA 30 oom POV e Pt AA mE 30 cR Mauer 30 3 4 TO Cee RET ET E 30 3 5 WO AIS OF TAN u u PAA 30 PH ESS Document No 3 of 30 PH ESE 30 07 08 02 1 INTRODUCTION The RF_RX_D Optical to RF VMEbus card is an interface VME card developed as receiver of RF TX D VMEbus Interface card This document contains a hardware description of the board and all the accessible registers of the D card as well as a description of the generic S W that has been developed for this card At the end of this document some basic examples of configuration procedures are proposed PH ESS Document No 4 of 30 PH ESE 30 07 08 02 2 RF_RX_D HARDWARE POWER DESCRIPTION This board requ
8. 2 Module MODO ADDRESS SPACE Manual address Module address 0x50 0000 Geographical address Module address Depends on the slot which the is plugged 0x3 4 Manual address ee ee ee Table2 3 1 b Examples of Module Addr PH ESS Document No 13 of 30 PH ESE 30 07 08 02 2 3 2 SOFTWARE VME ADDRES MAP 2 Unused pg OxNOO010 BEEN HeceiverModID Read Onl 2 OxN00012 2 CH1 OUTPUT REF SIGNAL Read Write OxAO OxN00014 2 CH2 OUTPUT REF SIGNAL Read Write OxAO TRR module only Def Val OxN00016 2 _OUTPUT REF SIGNAL 55 OxN00018 CH1 FREQ Head Freq Chi 0 31 Note 2 OxN0001C 4 CH2 FREQ Read Onl Freq Ch2 0 31 Note 2 OxN00020 CH3 FREQ Read Freq Ch3 0 31 Note 2 0xN00024 CARD ID Read Onl 0x1382 OXN00026 oi unused 0xN0003A BOARD ID Read Only 0x016C OxNOO08C 180 Unused sed O O O oxnoooF4 Unused PH ESS Document No 14 of 30 PH ESE 30 07 08 02 2 3 3 REGISTERS DESCRIPTION 2 3 3 1 RECEIVERMODID Bits 0 5 of the Receiver Module Ident code word are used to identify the installed Receiver modules between OCP SRX03 or SRX24 and TRR ReceiverModID OxN00006 bit Function Remarks The two bit code has the following meaning 00 No module installed 01 OCP SRX03 10 OCP SRX24 11 TRR Truelight Module 2 3 1 1 STATUS Offset Size Acce
9. MEBUS INTERFACE The VMEbus interface of the RF_RX_D cards is implemented in its FPGA and based on a VHDL Module developed by the AB RF group This Module has been developed especially for VME64 but adapted for using some functionality of VME64X like automatic addressing The firmware installed has been configured to work in the addressing mode of A24 D16 and works as a memory decoder where all the memory space is available The access modes dictated by address modifier are only available for 0x39 and Ox3D where the there is no distinction between privilege user and normal user Picture 2 3 Module address selector Two switches are used for address definition SW1 only the smallest bit is used If bitO is set to O SW 17 0x2 0x4 Ox6 the SW2 defines the address if bit O is set to 1 SW1 Ox1 Ox3 Ox5 the address is set by the geographical position of the module in the crate PH ESS Document No 12 of 30 PH ESE 30 07 08 02 2 3 1 ADDR MODULE SELLECTION Rotary Rotary Module address MA Switch 1 Switch 2 Automatic GEO Address A23 A20 lt GEOGA 3 0 OxM Manual Address A23 A20 lt M Requires VME64X crate Table 2 3 1 Address and ADDR Mode selection In others words the bottom rotary switch sw1 controls the addressing mode with the lower two bits which switches to automatic mode if the bit 0 or bit 1 Examples Rotary Switch 1 Rotary Switch
10. USER MANUAL Function Optical to RF ur 11 10 2006 Page 1 of 30 3 PH ESE 27 10 09 3 Modified 27 10 09 Default reg values updated RF RX D v2 0 Optical to RF Digital VMEbus Interface Card Hardware user manual Summary This document describes the functionality of the RF Rx Digital card the hardware is detailed and the VME mapping is described Prepared by Checked by Approved by Angel MONERA PH ESE Sophie BARON PH ESE Jose NOIRJEAN AB RF for information you can contact you can contact Jose NOIRJEAN 41 22 7679405 aN Jose NOIRJEAN Sophie BARON 41 22 7677339 mE Sophie BARON 1 2 3 PH ESS Document No 2 of 30 PH ESE 30 07 08 02 Table of Contents OI 1121 MEME 3 Hi HX u 4 PoWerdosc pi S m 4 AA E TEES 4 cel MOdUlES uama 5 2 2 1 1 Photodiode selection Depending of the signal to transmit 7 2 2 1 2 Photodiode configuration Threshold and 7 2215 Sna 9 2 2 2 Photodiodes Modules Post processing Logic a 9 222d Fro
11. V reference value for Pulse transmision 200 era DU a Ou AIN v C PE JU era a Ou A C v Vref Value por input output pulse 5 7V Tx Configuration Ch3 with Vref 0x70 560mv 5 6ns width pulse 15 10 5 dBm received in TRR gt N LO A 3 e p 3 e a 3 o 3 e o 5 Tx Configuration Ch3 with Vref 0x70 560mv 5 6ns width pulse 150 250 uW received in TRR PH ESS Document No 28 of 30 PH ESE 30 07 08 02 2 5 BOARD CONFIGURATION JUMPERS AND SWITCH Element Description LSB rotary switch See 2 3 1 section MSB _ switch 2 3 1 section mem qaa Panel IRL EIL a Soft reset of the FPGA when is pressed o x 7 U M B TP25 Frequency selector0 for the JTAG TP26 Frequency selector1 for the JTAG F C CCT SEES See eee eee ST3 If ST3 is ON gt the FPGA will be reprogrammed when the VME crate reset will be activated triggered by a VMEbus SYSRESET pM Table 2 5 Jumpers and Switch descriptions 2 6 FIBRE CABLE CONNECTIONS Connector To be connected to Format CH3 IN Optical Link RF Digital TX Optical Digital or Analog CH3 RF Out 50ohms LOAD LVPECL 50ohms AC DC coupled UL JTAG BIT BLASTER MODE EEPROM Table 2 6 Connectors and Descriptions PH ESS Document No 29 of 30 PH ESE 30 07 08 02 2 7 FRONT PANEL LEDS Description VME COMM Indicates if the last VME cycl
12. e was successful or wrong ERROR LED Indicates an VME bus error wrong register access CH1 LED SD CH1 Indicates Optical signal when is receiving 30dbm CH2 LED SD CH2 Indicates Optical signal when is receiving 30dbm CH3 LED SD CH3 Indicates Optical signal when is receiving 30dbm Table 2 7 Front Panel LEDS 2 8 REFERENCES OR MORE INFORMATION Lasers and Photodiodes evaluation by Angel Monera EDA documents https edms cern ch nav eda 01382 HF RX D TCL console Manual HF TX D User Manual PH ESS Document No PH ESE 30 07 08 02 TTC COMMON SOFTWARE 3 3 INTRODUCTION 3 3 1 H W ENVIRONMENT 3 3 2 S W ENVIRONMENT 3 4 TEST PROGRAMS 3 5 THE USER LIBRARY
13. guency MERO _ _ _______________ 10 2222 Output UU ul 10 2 3 VMEDUS IMENICE ous E nus 11 2k KONO 0 AA 12 2 3 2 Software VME addres map a a sas nisse sa sans rsen ans 13 2323 Registers Descerniplieh uu LLULLA 14 Ano o EE 5 uuu uuu u u uuu AA AAO 14 Sako CO TAI PA 14 2 3 3 2 VRef Registers Only for TRR or equivalent photodiodes 15 2339 Freguency Counters m E E 19 2934 1011 oculo u uu u uu kanaa a 20 Pl KONO 20 2 Ko CO 2 AA AA ee ee 20 2 3 1 4 uu 20 2 3 1 5 Firmware uuu uu OE 21 2 4 Calibration procedures Trr or Similar photodiode esses 22 2 4 1 Manual Calibration Fix Vref Values nennen nnne nnne nnn anne nnne narrans 22 2 4 2 Through VME Knowing the Signals and Photodiodes used 25 2 4 3 Through VME Unknowing
14. ires a VME crate with the standard VME64 power supply with 12 12 and 5 Volts available The nominal consumption for these power lines is the following Voltage Current A Fuse Current Table 2 1 Power consumption In order to check the power supplied to the board three LEDs have been installed to indicate the presence of 12V 12V and 3 3V generated from 5V indicating with this light both voltages If this LED is not lighting proceed checking the 5V fuse state OPTICAL INTERFACE The optical interface is composed of three equal channels based on two parallel circuits using two different photodiodes one being mounted at a time Both photodiodes have differential output and are connected to a group of ECL gates that will clean and prepare the signal to be amplified by a coaxial driver and processed with a FPGA COAX DRIVER ONNECTOR MODULE PHOTODIODE PCLto LVPCL _ B SPLITTER SS Picture 2 2 Optical Interface Diagram FPGA PH ESS Document No PH ESE 30 07 08 02 2 2 1 PHOTODIODES MODULES TUMPER OO TUMPER Power selector Resistor Picture 2 2 1 a Photodiodes Module in 1382 PH ESS Document No 6 of 30 PH ESE 30 07 08 02 Truelight TRR selector TRR Disconnect OCP selector Ee LLL Power inductan supply selector LJ 7 L8 V 0000000000 OCP OCP selector Disconnect T D p
15. nal power in order to drive the signal through long cables The user will be able to choose the output format between AC coupled 50 O or DC coupled LVPCL Another function of the Post Processing circuit is to split the signal and apply a frequency divider with the objective to be able to monitor the frequency with the FPGA through the VME interface PH ESS Document No 10 of 30 PH ESE 30 07 08 02 THE BOARD TO REMOUE Se Lu os ee a WA LUPECL COAX DRIVER Bo a FECL TO LUFECL TRANSLATOR MC1BEPEID y da s C PSU I PSU F A a 8 Tin sfc F 5 rece i HSE VO JUMPER N i 5 ri 8S5MASOD1 4 I s j 1 a ZEE Bec a Ep CH r G errs GND 5 Ep29 5o Er ex 2p s TUMPER TUMPER GN s Output FREQ DIV AC DC coupling selector FREQ OVER FIN Du elo Picture 2 2 2 Photodiodes Post Processing Logic 2 2 2 1 FREQUENCY DIVIDER The Frequency Divider is composed of 5 Flip Flops FF that divide the frequency by 16 2 2 2 2 OUTPUT FORMAT SELECTION In order to select the format of the output 500 AC coupled 800Vpp or DC coupled L VPECL you must place in the output of the system a capacitor of 100 nf AC or a 00 RESISTOR for DC coupling PH ESS Document No 11 of 30 PH ESE 30 07 08 02 2 3 V
16. orted ee TE Se SSS ES SEES EE OCP SRX 24 1Mhz to 500Mhz clocks No adjustment required OCP SRX 24 Pulses Don t care Not supported re Y aa Gr p Truelight 0 5Mhz to 400Mhz clocks Required 0x09 Truelight Any not optimal Required Oxa0 Table 2 4 2 Manual Calibration Values 2 4 3 THRoUGH VME UNKNOWING THE SIGNALS AND PHOTODIODES This will be the procedure algorithm to apply when the user doesn t know what types or receivers are installed in the board and which types of signals are received Like in the same procedure VME access software will be required in order to read and modify the desired registers PH ESS Document No 26 of 30 PH ESE 30 07 08 02 Start o ce Write 0 0 This valu 10Hz OXFFFF Write Picture 2 4 3 Remote Calibration Procedure This value is the minimum value to accept the pulse in good conditions and correspond to the worst scenario possible signal reception at 27dBm More values can be found in the next tables and graphs PH ESS Document No 27 of 30 PH ESE 30 07 08 02 Power Received in Value Hex for obtain a dBm 5 6ns width output Pulse widh of 5 6ns Value Dec 5 316 OxB5 181 7 199 160 9 125 0X88 136 11 79 0X78 120 13 50 0X70 112 15 31 0X70 112 17 19 0X70 112 19 12 0X65 101 21 7 0 58 88 23 5 0X4C 76 25 3 0X44 68 27 1 58 TRR
17. ss Default Values Bits Function Remarks NBN The channel is declared as being present if the measured frequency see CHX_FREQ registers matches with the following table PH ESS Document No 15 of 30 PH ESE 30 07 08 02 8 99 MHz up to 402 28 MHz 1 6 kHz up to 50 01 MHz OCP SRX03 amp OCP SRX24 TRR Truelight Module 2 3 3 2 VREF REGISTERS ONLY FOR TRR OR EQUIVALENT PHOTODIODES These registers only work with the photodiodes plugged in the Truelight socket They set up the value of the comparator threshold installed at the input of each channel For a balanced signal typically a clock the value must be as low as possible but has to be above the noise threshold Name Offset Size Access Default Values CH1 OUTPUT REF SIGNAL 0x0012 R W CH2 OUTPUT REF SIGNAL 0x0014 R W CH3 OUTPUT REF SIGNAL 0x0016 R W For a balanced signal typically a clock the value must be as low as possible but has to be above the noise threshold That is why the appropriated value for clock signals is between 0x05 and 0x09 at 12 For a unbalanced signal typically a pulse Revolution Frequency injection pulse the value must be more than the amplitude of the pulse at the output of the optical receiver but not too high That is why the appropriated value for pulse signals is between 0x70 and 0xAO at 12 Note be careful if the VREF value is 0x0
18. tive New reference for Negative y Pulse Line Controlled by VME a een Theoretical reference for BOTH LINES New reference for Positive Line Controlled by hardware Resistor Pulse width reduced Out Picture 2 3 3 3c Positive pulse in an Unbalanced Thevenin network V New reference for Negative Line Controlled bv VME ILLI Negative _ Theoretical reference for both LINES V New reference for Positive Line Controlled by hardware Resistor ut O Cross signa Picture 2 3 3 3d Negative pulse in an Unbalanced Thevenin network PH ESS Document No PH ESE 30 07 08 02 Review When the network is balanced the user must avoid keeping a level for more than 10us When the network is UNBALANCED the network will force zero detection when there is no signal negative or zero signal When a positive level is received the output will change to positive following the received signal for a maximum of 10us will received Examples of Outputs with unbalanced network Input Output notes Low 50s high 5us low 50s Low 50s high 5us low 50s ot AGC actuation Low 50s high 10us low 505 40us Low 50s high 50us low 50s T Pi has 2 J uut TEL ALLE p64 c lt Ki O G Picture 2 3 3 3e Truelight Selection Vref controlled by FPGA VME PH ESS Document No 19 of 30 PH ESE
19. unter 2 3 3 4 BOARD IDENTIFICATION 2 3 1 2 IDENT CODE Ident Code OxN0008 nmm _____ default dent Code oA 2 3 1 3 CARDID CARD ID OxN00024 CARD ID 0x1382 Ro This register contains the EDA number of the board EDA 001382 2 3 1 4 BOARD ID BOARD ID OxN0003A ptf Function ams __ BOARD id 0x016C This register contains the VME64x board ID of the RF RX CERN centrally defined and is set to the value 364 0x16C See http ess web cern ch ESS boardIDistribution PHP for details PH ESS Document No 21 of 30 PH ESE 30 07 08 02 2 3 1 5 FIRMWARE VERSION Firmware OxN0003A Version Bi Function aem __ _______ 31 Firmwareversion lp 2 4 PH ESS Document No 22 of 30 PH ESE 30 07 08 02 CALIBRATION PROCEDURES TRR OR SIMILAR PHOTODIODE The calibration procedure will apply only to the channels where a TRUELIGHT or equivalent photodiode is installed The OCP photodiodes DO NOT REQUIRE ANY CALIBRATION Only be selected see section 2 2 1 1 The calibration procedure can be done manually or trough VME dividing this last option in two different scenarios Knowing the frequency and type of the signal received Unknowing the frequency and type of the signal received In order to read and modify the board s registers the program rfrxscope has been developed It helps the user accessing the board registers in an interactive way rfrxscope

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