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IP-EX20x User`s Manual

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1. 2 Y al poy lt o ilo a ilo la H H FRONT VIEW 078 19 8 69 9 lt 10 51 261 9 gt TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC NOTE DIMENSIONS ARE IN INCHES MILLIMETERS 450 1 465 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
2. 7 and fitness for a particular purpose Further Acromag assumes no responsibility for 2 0 PREPARATION FOR USE any errors that may appear in iis manual and Makes 20 UNPACKING AND 8 commitment to update or CARD CAGE 8 1 1 8 KOAP ere Menlo nation BOARD 6 8 contained in this manual No Default Hardware Configuration 8 par dis anal IP Field VO 9 copied or oduced Logic Interface Connector 10 form without the prior written Non Isolation Considerations 11 consent of Acromag Inc 3 0 PROGRAMMING INFORMATION CONFIGURATION 12 Configuration Address Map 12 Configuration 13 Configuration Methodologies amp Procedures 13 IP Identification Space 15 USER MODBDE iecit cocina 16 Example Design Address Map 16 Control Register aces 18 Input Output Registers 18 Direction Control Registers 19 Interrupt E
3. Based FPGA IP Module 4 0 THEORY OF This section contains information regarding the design of the board A OPERATION description of the basic functionality of the circuitry used on the board is also provided Refer to the IP EP2 Series Block Diagram drawing at the end of this manual as you review this material IP BUS INTERFACE LOGIC The logic interface to the carrier board is made through connector 1 refer to Table 2 4 P1 also provides 5V power the module 12V is not used Note that the ERROR signal 40 and two Reserved signals 36 and 49 have been reserved for factory programming These signals will not interfere in the operation of the IP interface The IP Specification defines all IP control signals with 5V signaling levels Since the Altera Cyclone II Field Programmable Gate Array FPGA is not 5V tolerant all signals are buffered using a Complex Programmable Logic Device CPLD The worst case buffer propagation delay is 10nS This delay is significant if running the IP EP2 Series module at 32 2 Therefore it is recommended that 1 wait state be implemented for all IP read write cycles Furthermore the direction control signals are required to control the IP Data bus These signals are controlled from the FPGA For more information on implementation of this requirement refer to the documentation provided in the EDK The Altera FPGA installed on the IP Module controls the interface to the carrier board per IP Mo
4. Not Used Interrupt Enable Registers Read Write Base The Interrupt Enable Registers provide a mask bit for the first 8 channels on any IP EP2 model A 0 bit will prevent the corresponding input channel from generating an external interrupt A 1 bit will allow the corresponding input channel to generate an interrupt Only those channels enabled for interrupts will generate interrupts Interrupts are only available on the first eight channels Interrupt Enable Register MSB LSB Ch 06 Ch 05 Ch 03 Ch 00 The Interrupt Enable register at the carrier s base address offset OBH is used to control channels 00 through 07 For example channel 00 is controlled data bit 0 as seen in the prior table Channel read operations use 8 bit or 16 bit data transfers The upper 8 bits of this register are Not Used and will always read logic O All input channel interrupts are disabled set to 07 following a power on or software reset Interrupt Type Configuration Registers Read Write Base The Interrupt Type Configuration Registers determine the type of input channel transition that will generate an interrupt for each of the 8 possible interrupting channels 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means Acromag
5. a must buy for first time IP EP2 module purchasers The design kit model IP EP2 EDK provides the user with the basic information required to develop a custom FPGA program for download to the Altera FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files The IP EP2 modules are intended for users fluent in the use of Altera FPGA design tools Acromag provides a software product sold separately to facilitate the IP MODULE DLL CONTROL development of Windows 2000 XP Vista 7 applications accessing SOFTWARE Acromag Industry Pack models installed on Acromag PCI Carrier Cards and Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE VxWORKS Acromag provides a software product sold separately consisting of SOFTWARE board VxWorks software This software Model IPSW API VXW is composed of VxWorks real time operating system libraries for all Acromag IP modules and Carriers PCI I O Cards and CompactPCI I O Cards The software is implemented as a library
6. Digital Input Output Logic Digital TTL field I O are provided on the IP EP201 and IP EP202 models through the Field I O Connector refer to Table 2 2 Digital input output signals to the FPGA are buffered using an octal bus transceiver Signals received are converted from 5V TTL to LVTTL as required by the FPGA The digital receivers output TTL signals The direction control of the digital channels is controlled in groups of eight Each field line has a 10K pull down resistor to GND Output operation is considered Fail safe That is the Digital Input Output signals are always configured as inputs following a power up or software reset This is done for safety reasons to ensure reliable control under all conditions Differential I O are provided on the IP EP202 and IP EP203 models EIA RS485 RS422 through the Field I O Connector refer to Table 2 1 and 2 2 Differential Input Output Logic channels to the FPGA are buffered using EIA RS485 RS422 line transceivers The transceivers are considered failsafe as a open or short circuit on the I O will not damage the board Field input lines are not terminated External 120 Ohm resistors are recommended on all receivers Signals received are converted from the required EIA RS485 RS422 voltages to the LVTTL levels required by the FPGA Likewise LVTTL signals are converted to the EIA RS485 RS422 voltages for data output transmission The direction control of the differential channels is controlled
7. Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes See Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packaged TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 8610 or APC8620 Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U APC8610 or APC8620 1 non intelligent carrier boards field connectors only via a flat ribbon cable Model 5025 551 x The A D connectors on the carrier board connect the field signals to the P2 connector on each of the Industrial I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial Pack IP Each Industrial Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AV
8. Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 2 1 the interrupt will occur when a Change Of State COS occurs at the corresponding input channel i e any state transition low to high or high to USER MODE low The Interrupt Type Configuration register at the carrier s base address offset ODH is used to control channels 00 through 07 For example channel 00 is controlled via data bit O as seen in the table below Interrupt Type COS or H L Configuration Register MSB LSB Data Data Data Data Data Data Data Data Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 Ch 06 Ch 05 Ch 03 Ch 00 Channel read or write operations use 8 bit or 16 bit data transfers The upper 8 bits of this register are Not Used and will always read logic 0 Note that interrupts will not occur unless they are enabled via the Interrupt Enable Register at base address offset OBH All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specified by the digital input channel Interrupt Polarity Register Interrupt Status Registers Read Write Base OFH The Interrupt Status Register reflects the status of each of the interrupting channels A 1 bit indicates that an interrupt is pending for the corresponding channel A channel that does not have i
9. The Vector Register can be written with an 8 bit interrupt vector This vector is provided to the carrier and system bus upon an active INTSEL cycle Reading or writing to this register is possible via 16 bit or 8 bit data transfers Interrupts are released on register access to the Interrupt Status register Issue of a software or hardware reset will clear the contents of this register to 0 Memory Data Register Read Write 15H The Memory Data register is used to provide read or write access to SRAM memory Reading or writing to this register is possible via 16 bit data transfers only In order to properly access the memory which constitutes 64K words an address pointer to a single word in memory must first be specified The address is specified via the Memory Address register The value written into the Memory Address register is used to point to one of the 64K words All read or write accesses to the Memory Data register will in turn implement an access to memory at the address specified by the Memory Address register The address specified in the Memory Address register will be automatically incremented after the read or write cycle is completed Thus when consecutive locations within the memory are accessed the Memory Address register need not be manually updated by software Read or write accesses to this register require four wait states A software or hardware reset has no affect on this register Acromag Inc Tel 248
10. keyed to avoid incorrect assembly P2 pin assignments are unique to each IP model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board When reading Table 2 1 notice that Differential input output channels as well as digital TTL input output channels are listed with their corresponding connector pin number Furthermore each Differential point could be either RS485 or LVDS defined by the IP EP2 model Table 2 2 lists the channels dedicated to each of the IP EP2 models Pin Description mom Pin Description Table 2 1 2 Series DIFF TTL DIFF TTL Field I O Pin Connections 012 O25 yeh 013 1026 TN 013 1027 S485 or LVDS channels VO14 028 Refer to Table 2 2 for VO 014 029 assignments per module 015 1030 1 015 1 031 2 The External Clock Input is 1 016 1 032 routed directly to an global 1 016 1 033 input on the Cyclone FPGA 017 1034 05 1 010 11 1 017 1 035 WARNING THE 1 018 1 036 EXTERNAL CLOCK 1 018 1 037 INPUT PIN IS NOT 5V 1 006 1 013 14 019 1 038 TOLERANT IT 1 019 1 039 REQUIRES LVTTL 3 3V 1 007 1 015 16 20 1 040 SIGNALING APPLYING 008 016 17 1 020 1 041 5V TO FIELD I O PIN 49 VO21 1042 MAY DAMAGE THE 1 009 1 018 19 1 021 1 043 BOARD 1 009 1 019 20 22 1 044 022 045 010 1 021 22 23 1 046 11 1 022 23 1 023 1 047 1 011 1 023 24 E
11. 46 48 50 1 3 5 7 9 1113 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 205 H 58 5 FRONT VIEW ERMINATION PANEL ACROMAG PART RAIL DIN MOUNTING SHOWN DIN EN 50035 32mm RAIL DIN MOUNTING SHOWN HERE DIN EN 50022 35mm NUMBER 4001 040 Al SCREWDRIVER SLOT FOR REMOVAL FROM RAIL SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 0 02 0 5 MODEL 5025 552 TERMINATION PANEL 4501 464A Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual MODEL 5 MODULE SCHEMATIC A B 123 48 49 50 123 48 49 50 123 48 49 50 123 48 49 50 Cyclone Based FPGA Module 453 D 125 48 49 50 123 48 49 50 123 48 49 50 lt 123 48 49 50 CONNECTORS ON PC BOARD CONNECTORS ON FRONT PANEL A B VIEW lt 9 19 253 4 gt a 80 0 TE m li 5 m I Pr 85 1 it 3 pn d i
12. Cyclone Based FPGA IP Module 25 1 Start the BitCalc2K1 Version 2 program enter the desired x frequency and select the IP clock speed Desired Frequency in MHz 4 Clock Speed Calculate 2 Hit the Calculate Button Expected Frequency in 2000000 5 i 2 3 Write to the Clock Control Register 1 at base address Expected Frequency Error PPM 0 000000 plus an offset of 19H using the data provided by the Register Data INSTRUCTIONS Enter the desired program proper IP lock speed MHzis L 4 Write to the Clock Control Register 2 at base address EA ae Aessoge Bon wl opea ene lo introl Register 3 calculation is complete plus an offset of 1BH using the data provided by the program 5 Write to the Clock Control Register 3 at base address plus an offset of 1DH using the data provided by the program 6 Write 1H to the Clock Trigger Register at base address plus an offset of 1FH After approximately 1 2ms programming is complete and the clock is available for use by the FPGA A software or hardware reset during programming will cause errors If a reset occurs repeat the above procedure Programming Interrupts Digital input channels can be programmed to generate interrupts for the following conditions e Change of State COS at selected input channels e Input level polarity match at selected input channels Interrupts generated by the I
13. O Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Register Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Change of State Interrupts may now be generated by the input channels programmed above for any Change Of State transition Programming Example for Level Polarity Match Interrupts 1 Program the Interrupt Vector Register with the user specified interrupt vector This vector forms a pointer to a location in memory that contains the address of the interrupt handling routine Select channel polarity match interrupts by writing a 0 to each channel s respective bit in the Interrupt Type Registers Note that Change Of State interrupts specified with 1 may be mixed with polarity match interrupts specified with O Select the desired polarity High Low level for interrupts by writing a 0 Low or 1 High level to each channel s respective bit in the Interrupt Polarity Registers Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Registers Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Interrupts can now be generated by matching the input level with the selected polarity for programmed interrupt
14. The status of the Altera FPGA during configuration can be monitored via the Status register at base address 01H Bit 1 monitors the Altera nStatus signal which must remain high during configuration Bit 2 of the Status register reflects the Altera FPGA CONF DONE signal The CONF DONE signal must remain at a logic low until configuration has completed 7 Write program data one byte at a time to the Configuration Data register at base address 03H 8 Upon successful configuration control of the IP bus will automatically be switched to user mode and the Altera FPGA will have control of the IP bus interface It is good practice to issue a software reset prior to operating the board Refer to the documentation provided with the IP EP2 EDK for further information on programming methodologies IP EP2 Direct JTAG The IP EP2 module can also implement configuration using a standard Configuration Procedure JTAG interface The JTAG interface can either program the directly or program the FLASH configuration memory When programming the FPGA directly the programming jumper may be in either position Note that the FPGA will require reprogramming after power down The following is the general procedure for direct programming of the Altera FPGA using the JTAG interface 1 Connect the 10 pin Altera JTAG cable not included to the board 2 Power up the carrier board 3 Download the Configuration sof file to the FPGA via JTAG using Al
15. Wiring 100 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 551 X Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 0 to 70 C Storage Temperature 25 C to 85 C Shipping Weight 1 25 pounds 0 6Kg packaged Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com TRANSCEIVER INTERFACE amp LVDS TRANSCEIVERS 1 000 U 1 TIL 0 TRANSCEIVERS 1 000 098 10K 0 U 3 J p 047 Sa u 1 047 1 40 2 Series User s Manual 2 5 NOTE TERMINATION RESISTOR 87 100 Ohms provided for LVDS 1 0 NOT provided for RS485 R422 1 0 RS485 R422 may require external resistors 5 485 5 42
16. channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 2 7 General Sequence of Events for Processing an Interrupt USER MODE 1 2 The IP EP2 Series module asserts the Interrupt Request 0 Line INTREQO in response to an interrupt condition at one or more inputs The AVME9630 9660 carrier board acts as an interrupter in making the VMEbus interrupt request asserts corresponding to the IP interrupt request The VMEbus host interrupt handler asserts IACK and the level of the interrupt it is seeking on 01 03 When the asserted VMEbus IACKIN signal daisy chained is passed to the AVME9630 9660 the carrier board will check if the level requested matches that specified by the host If it matches the carrier board will assert the INTSEL line to the appropriate IP together with carrier board generated address bit A1 to select which interrupt request is being processed A1 low corresponds to IntReq0 A1 high corresponds to INTREQ1 The IP EP2 Series module puts the appropriate interrupt vector on the local data bus 000 007 for the 008 O interrupter and asserts ACK to the carrier board The carrier board passes this along to the VMEbus DO8 O and asserts DTACK The host uses the vector to form a pointer to an interrupt service routine for the interrupt handler to begin exec
17. for Acromag software to properly identify the model this ID space must remain as defined in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID information Execution of an ID Space Read operation requires 1 wait state Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 2 Series User s Manual Cyclone Based FPGA IP Module Table 3 2 2 Series ID Space Identification 10 1 The IP model number is represented by a two digit code within the ID space The IP EP2 Series models are represented by 48 Hex in Configuration Mode and 49 Hex in User Mode USER MODE Hex Offset From ID ASCII Numeric Base Character Value Field Description Equivalent pt 1 49 AIS2MHzIP s have IPAH IP Model Code Configuration Mode 48 User Mode 49 00 NotUsed Revision Not Used Driver ID Low Byte Not Used Driver ID High Byte Total Number of ID PROM Bytes CRC Configuration Mode BA User Mode DB 0 Example Altera FPGA Design The example design provided with the IP EP2 EDK consists of IP bus interface logic Altera interface to 64K x 16 static RAM Altera interface to the clock generator chip and I O interface to differential or TTL I O The IP EP2 Series hardware supports a direct connection to all IP bus signals as listed
18. in Table 2 4 As such hardware will support all IP bus cycles including ID I O Interrupt Memory and DMA The example design provided uses all but the Memory and DMA cycle types The space address map for this example design is given in Table 3 3 The differential or TTL I O clock generator chip and 64K x 16 static RAM be controlled and accessed through I O space The base address for the IP module space see your carrier board instructions must be added to the addresses shown in Table 3 3 to properly access the space Accesses can be performed on an 8 bit or 16 bit basis This memory map reflects byte accesses using the Big Endian byte ordering format Big Endian uses odd byte addresses to store the low order byte Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention The Intel x86 family of microprocessors uses Little Endian byte ordering In Little Endian the lower order byte is stored at even byte addresses Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual 008 007 Control Register Input Output Register Channels 15 lt gt 00 Input Output Register Channels 31 lt gt 16 Input Output Register Channels 47 gt 32 Direction Control Register Not Used Not Used Not Used Not Used Not Used Memory Data Register Clock Control Register 1
19. of their respective owners Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com http www vita com TABLE OF CONTENTS RELATED PUBLICATIONS 4 2 Series User s Manual Cyclone Based FPGA IP Module 1 0 GENERAL INFORMATION Table 1 1 The IP EP2 Series models KEY FEATURES The Industrial EP2 Series module is a reconfigurable digital input output board The modules use an Altera Cyclone II Field Programmable Gate Array FPGA This allows designers to implement logic functions unique to their application Furthermore the FPGA can be configured in system using either the industry standard JTAG interface or directly through the IP bus An example Altera FPGA configuration file and its corresponding VHDL source are provided with the IP EP2 Series Engineering Design Kit The example design includes an IP bus interface to ID space IO space and Interrupt space IO space is used to access a 64K x 16 RAM array control field data I O and configure a clock generation chip To take advantage of the example VHDL program the user must be proficient in the use of VHDL and the Altera Quartus II software tools The IP EP2 Series provides several different interface options which allow a mix of differential digital and TTL digital input output channels The models and their corresponding combination of channels are given in the table below All models use the EP2C20 Cyclo
20. of this model can be configured to generate interrupts for Change Of State COS and input level polarity match conditions at enabled inputs An 8 bit interrupt service routine vector is provided during interrupt acknowledge cycles on data lines DO D7 The interrupt release mechanism employed is RORA Release On Register Access Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 29 The field I O interface to the carrier board is provided through connector FIELD INPUT OUTPUT P2 refer to Table 2 1 Field points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operational errors and with extreme abuse possible circuit damage The IP EP2 series allows interface with a mix of up to 48 TTL I O channels or up to 24 differential I O signals The signals DIO 0 to DIO 47 are utilized for digital input output control to the field signals The six signals DIFF DIR 0 5 control data direction of the 24 differential I O signals The six signals DIR BANK 1 6 control data direction of the 48 TTL I O channels Digital Field inputs are 5V tolerant An additional External Clock input is available on all models This input is not buffered and requires LVTTL signaling levels i
21. the carrier board This connector is a 50 pin female receptacle header which mates to the male connector of the carrier board This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Mechanical Assembly Drawing in the Drawings sections of this manual for details Field and logic side connectors are keyed to avoid incorrect assembly The pin assignments of P1 are standard for all IP modules according to the Industrial I O Pack Specification see Table 2 4 However some logic signals not used for the IP interface are reserved for factory programming Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 1 1 Pin Pin Table 2 4 Standard Logic 1 Not Used by this IP Module 2 v 27 Reset DOO IDSEL DMARego MEMSEL DMAReqi IntSel Reserved AL 2 Reserved for Factory Programming The pound sign is used to indicate an active low signal Reserved EE e INTReqO INTReq1 Ai A2 STROBE e ACK R Reserved 28 29 30 32 93 Hc ew 395 96 97 DMAEnd 98 pa
22. this time the IP module will not respond to any request After this initial power on reset another 0 4 seconds maximum is required if loading the FPGA from FLASH During this time the board will act as if it is not configured until the download to the FPGA is complete It is good practice to reset the board using either an IP bus or software reset subsequent to power up EXTERNAL CLOCK INPUT POWER ON RESET Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 8 2 Series User s Manual Cyclone Based FPGA IP Module APPENDIX CABLE MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded cable according to model number The shielded cable is highly recommended for optimum performance with analog input or output modules Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 APC8610 or APC8620 1 non intelligent carrier board connectors both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Shielded cable model uses Acromag Part 2002 261 8M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief
23. use the Altera debugging tool SignalTap 28 The JTAG interface is powered by 3 3V Refer to the EDK documentation for further information of the JTAG interface and programming procedures EXAMPLE DESIGN Memory Interface The IP EP2 Series interfaces to a 64K word SRAM device This memory interface utilizes the address signals RAMa1 to RAMa16 data signals 0 to RAMd15 and the read write control signals RAM nBLE RAM nBHE RAM and nOE RAM The RAM device is the Integrated Device Technology IDT71V016SA GSI Technology part GS71116A or equivalent A complete listing of the SRAM interface pin and their assignments on the Cyclone FPGA is available in the IP EP2 EDK IP Bus Interface The IP EP2 Series interfaces to the carrier board per IP Module specification ANSI VITA 4 1995 The FPGA signals utilized are 16 data lines DATAO to DATA15 and six address lines A 1 to 6 The many control lines that comprise the IP bus include IP Reset nlOsel nlDsel nMEMsel nINTsel R_nW nAck nlntReqO nintReq1 nDMAReqO nDMAReq1 nDMAAck nDMAend nStrobe nBSO and nBS1 A complete listing of the IP interface pins and their assignment on the Cyclone Il FPGA is available in the IP EP2 EDK The IP bus 8 2 or 32MHz clock signal is present on pin CLK8MZ The function and timing requirements of all IP bus signals are specified in the ANSI VITA 4 1995 specification Copies of the ANSI VITA 4 1995 specification are available from VITA www
24. vita com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 3 1 A clock generator chip Cypress CY22150 is available to provide a user programmable clock frequency between 250KHz and 100MHz A total of four signals are utilized Ref Clock SCLK SDATA and Gen Clock as seen in the tale below Signal Description Ref Clock The Ref Clock or reference clock is a 8MHz clock generated by the FPGA from the IP carrier clock signal SCLK This is the serial clock to the CY22150 It is used for clock frequency programming SDATA The serial data is sent from the FPGA to the CY22150 on this pin for clock frequency programming Gen Clock The clock frequency generated by the CY22150 is input to the FPGA on this pin The FPGA pin definitions are in the FPGA Programming Guide provided in the IP EP2 Series Engineering Design Kit The Altera Cyclone Il FPGA can be initialized using several methods First the FPGA can be programmed over the IP Bus using the Passive Serial technique This technique requires the programming bus jumper to be set to the IP position The initialization interface utilizes six signals nConfig Conf Done Init Done nStatus DCLK and DataO The second and third method involve programming via the JTAG interface This interface can be used to either direct program the FPGA or indirectly program
25. 2 P1 LOGIC INTERFACE pip ETETA EXTERNAL CLOCK INPUT PIN 50 IS SIGNAL COMMON IP EP2 JTAG INT DIRECTION BUS p Cyclone Based FPGA IP Module ES BLOCK DIAGRAM ALTERA FPGA INPUT OUTPUT CHANNEL REGISTERS DIRECTION CONTROL REGISTERS n INTE RRUPT ENABLE REGISTERS CONTROL REGISTERS TYP NTERRUPT E REGISTERS TERRUPT POLARITY REGISTERS TERRUPT ADDRESS DECODING INTERRUPT AND IP BUS INTERFACE LOGIC 9 BUFFERED IP BUS STATUS REGISTERS USER APPLICATION WILL ALTER FUNCTION ID PROM MSEL CONFIGURATION SIGNALS SRAM 64K X 16 FLASH Configuration Device COMMON w DATA BUS DIRECTION CONTROL LINES 2 ENABLE CPLD ALTERA JTAG HEADER P3 CLOCK GENERATOR CPLD IP BUS BUFFER CONFIGURATION LOGIC 55 3 VOLTS Configuration Jumper POWER SUPPLIES SUPPLY FILTERING amp REGULATORS ERFACE JUMPER LOCATION LOOKING AT JTAG 10 PIN CONNECTION ON THE 2 PRIMARY COMPONENT SIDE OF IP EP2 x P2 10 INTERFACE FLASH P1 LOGIC INTERFACE IP BUS INTERFACE CONFIG
26. 295 0310 Fax 248 624 9234 Email solutions acromag com hittp www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 2 3 Memory Address Register Read Write 17H USER MODE The Memory Address register is used to point to one of 64K words in memory The 16 bits of this register are used to specify one of 64K words that can be accessed via a read or write to the Memory Data register Writing to this register is possible via 16 bit data transfers only The address specified in the Memory Address register will be automatically incremented after the read or write cycle to the Memory Data register is completed Thus when consecutive locations within the memory are accessed the Memory Address register need not be manually incremented by software A write access to this register requires one wait state A software or hardware reset will clear this register to zero Clock Control Reg 1 Read Write Base 19H The Clock Control Register 1 is a 16 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock The register contains the following control bits as specified in the Cypress CY22150 spec sheet Refer to Program procedure to set Clock Frequency later in this manual for information on determining the value of these bits A software or hardware reset will clear this register to zero Clock Control Reg 2 Read Write Base 1BH The Clock Control Registe
27. 4 2 Series User s Manual Cyclone Based FPGA IP Module An example program written in C and available from Acromag implements configuration of the IP EP2 Series module over the IP bus The program requires the configuration file to be in the Intel Hex format For information on generating hex files refer to the documentation supplied with the EDK IP EP2 IP Direct Configuration Procedure 1 Prior to power up set the Configuration Jumper to IP BUS as shown in the JTAG Interface Jumper Location drawing at the end of this manual 2 Start the configuration mode Upon system power up the 2 module is in configuration mode If the Altera FPGA is currently configured and operational configuration mode can be entered by driving pin L3 of the Altera FPGA to a logic high via the control register bit 0 Pin L3 is the EnableCPLD signal which upon system power up is held high by a pull up resistor 3 You can verify that you are in configuration mode by reading ID space at base address OBH The byte read will be 48H when in configuration mode and 49H when in user mode 4 Configuration is started by setting 61 0 of the control register at base address 01H to a logic high 5 This same register bit O must be read next When read as a logic high software can proceed to the data transfer phase A polling method should be used since this bit may not be read high for up to 160 seconds after the control bit is set high 6
28. Acromag 9 Series IP EP201 202 203 204 Industrial I O Pack Cyclone Il Based Reconfigurable FPGA Digital Modules USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 797 C12A021 2 2 Series User s Manual Cyclone Based FPGA IP Module TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY FEATURES oc ovate caras 4 may change without notice INDUSTRIAL I O PACK INTERFACE FEATURES 5 Acromag makes no warranty SIGNAL INTERFACE PRODUCTS 6 of any kind with regard to this IP EP2 ENGINEERING DESIGN KIT 7 material including but not IP MODULE DLL CONTROL SOFTWARE 7 limited to the implied IP MODULE VxWORKS SOFTWARE 7 warranties of merchantability IP MODULE QNX
29. Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board Use the unmodified example we provided If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted directly for technical assistance via telephone FAX or email through the information provided at the bottom of this page When needed complete repair services are also available Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 3 3 6 0 SPECIFICATIONS Single Industry Pack Board PHYSICAL Max Component Height 0 290 in 7 37 mm Length 3 880 in 98 5 mm Width 1 780 in 45 2 mm Board Thickness 0 062 in 1 59 mm IP EP201 E 0 84407 0 02626Kg Unit Weight IP EP202 E 0 81907 0 02548Kg IP EP203 E 0 8410z 0 02617Kg IP EP204 E 0 82407 0 02562Kg e IP Logic Interface Field I O Connectors 50 pin female receptacle Connectors header Comm Con 8066 50G2 or equivalent Table 6 1 Pow
30. Clock Control Register 2 1C Not Used Interrupt Enable Register Interrupt Type Register Interrupt Status Register Interrupt Polarity Register Interrupt Vector Register Memory Address Register 75 Clock Control Register 3 Clock Generator Trigger Not Used Register Cyclone Based FPGA IP Module 1 7 Table 3 3 2 Series Addr FPGA Address Map IO Space for Example Design DOO 1 Refer to the Input Output Register Description for mapping for the various IP EP2 series models 2 The board will return O for all addresses that are Not Used Not Used Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 8 2 Series User s Manual Cyclone Based FPGA Module USER MODE Conirol Register Read Write Base Addr 01H This read write register is used to transfer control back to configuration mode when in user mode set your specific model of the IP EP2 and issue a software reset Bit 0 controls operation of the IP EP2 module in user mode and configuration mode via control of pin L3 of the Altera FPGA When bit 0 is set to logic low the IP EP2 module will be in user mode Setting bit 0 to a logic high places the IP EP2 Series in configuration mode Upon issue of an IP bus reset this register bit will be clear placing the IP EP2 in user mode Also initial configuration of the Altera FPGA sets bit 0 t
31. ECTOR PIN 1 9 9 1004 512 PIN 1 NSE ON CABLE 8 8 NO MARKINGS STRAIN RELIEF 7 7 1004 534 6 6 5 5 FRONT VIEW 4 4 3 3 NOTE SEVEN DIGIT PART NUMBERS ARE 2 2 ACROMAG PART NUMBERS XXXX XXX 1 1 M MODEL 5025 551 x SCHEMATIC MODEL 5025 551 x SIGNAL CABLE SHIELDED 4501 463 12 34 5 6 7 B 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 so P1 12 54 5 6 7 8 9 10 111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TB1 MODEL 5025 552 TERMINATION PANEL SCHEMATIC 3 032 77 0 TB1 299 99 2929 22 299 29 299 9929 99 9 9 999 9 999 Y be 5 315 gt 135 0 TOP VIEW 2 4 6 B 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
32. ED AT THE TWO EXTREME ENDS OF THE BUS NOT AT EACH NODE THE PURPOSE OF THE TERMINATION IS TO PREVENT ADVERSE TRANSMISSION LINE REFLECTIONS TO MINIMIZE POWER DISSIPATION THE TERMINATION RESISTORS CAN BE LEFT OFF THIS IS POSSIBLE IF THE CABLE IS SHORT AND THE DATA RATE IS LOW IT IS ALSO POSSIBLE TO MINIMIZE POWER DISSIPATION BY USING AN RC TERMINATION IN PLACE OF THE RESISTOR TERMINATION MINIMIZE TRANSMISSION LINE PROBLEMS ALL NODES CONNECTED TO THE CABLE MUST USE MINIMUM STUB LENGHT CONNECTIONS IDEALLY ALL NODES SHOULD BE CONNECTED IN A DAISY CHAIN FASHION TO MINIMIZE HIGH LEVEL OF EMI THE GROUND WIRE ON PIN 5 MUST BE USED TO PROVIDE A PATH FOR NDUCED COMMON MODE NOISE AND CURRENTS THE GROUND PROVIDES A LOW IMPEDANCE PATH TO 4501 702 REDUCE EMMISSIONS M2 x 6 FLAT HEAD SCREW REE SIDE OF IP MODULE Sar THREADED M2 COMPONENT SIDE SPACER OF CARRIER BOARD pA mH moo ic NC P1 CONNECTOR FRONT PANEL CONNECTOR Og Ee Me wo x6 PAN HEAD SCREW ASSEMBLY PROCEDURE 1 THREADED SPACERS ARE PROVIDED FOR USE WITH AVME 9630 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF IP MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED THE RECOMMENDED TORQUE IS 0 226 NEWTON METER O
33. ERFACE Radiated Emissions Meets or exceeds European Norm 50081 1 for class B equipment Shielded cable with I O connections in shielded enclosure is required to meet compliance Mean Time Between Failure per MIL HDBK 217F Notice 2 IP EP201 1 240 750 hours IP EP201E 1 235 038 hours IP EP202 1 580 071 hours IP EP202E 1 580 413 hours IP EP203 1 580 413 hours IP EP203E 1 386 411 hours IP EP204 1 904 795 hours IP EP204E 1 904 795 hours Altera 2 20 256 8 18 for Extended Temperature e 18 752 Logic Elements e 239 303 Distributed RAM Bits 52 4Kbit Block RAMs 26 18x18 Embedded Multipliers e 4 Digital PLL Clock Managers 64K x 16 bit Integrated Devices Technology IDT71V016SA12PHGI or equivalent Clock Generator Chip Cypress CY22150 or equivalent e Generate Frequencies from 250kHz to 100MHz IP Compliance Conforms to Industrial I O Pack Specification per ANSI VITA 4 1995 for 8MHz or 32MHz operation Module 201 IP EP202 IP EP203 are Type Modules IP EP204 is a Type II Module since it has passive components on the back side of the board Space 16 bit and 8 bit read and write operations are supported ID Space 16 bit and 8 bit read operations are supported Supports Type ID ROM data 32 bytes per IP data on lower byte only IPAH is used to indicated 32MHz operation 8MHz is also supported Memory Space Supported by hardware but not implemented in example design I
34. ME9630 9660 APC8610 or APC8620 1 P1 50 pin male header with strain relief ejectors Use Acromag 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 0 to 70 C Storage Temperature 25 C to 85 C Shipping Weight 1 25 pounds 0 6kg packaged Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 3 O TRANSITION MODULE MODEL TRANS GP APPENDIX Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field
35. P EP2 use interrupt request line INTREQO Interrupt Request 0 The interrupt release mechanism employed is the Release On Register Access RORA type This means that the interrupter will release the Industrial Pack interrupt request line INTREQO after all pending interrupts have been cleared by writing a 1 to the appropriate bit positions in the input channel Interrupt Status Register In VMEbus systems the Interrupt Vector Register contains a pointer vector to an interrupt handling routine One interrupt handling routine must be used to service all possible channel interrupts When using interrupts input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a given input channel this could happen if multiple changes occur before the channel s interrupt is serviced The response time of the input channels should also be considered when calculating this bandwidth The total response time is the sum of the input buffer response time plus the interrupt logic circuit response time and this time must pass before another interrupt condition will be recognized The Interrupt Input Response Time is specified in section 6 The following programming examples assume that the IP EP2 Series module is installed onto an Acromag AVME9630 9660 9668 carrier board consult your carrier board documentation for compatibility details Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag
36. R 2 INCH POUNDS OVER TIGHTENING MAY DAMAGE CIRCUIT BOARD 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED 4 INSERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES THE RECOMMENDED TORQUE IS 0 226 NEWTON METER OR 2 INCH POUNDS OVER TIGHTENING MAY DAMAGE CIRCUIT BOARD IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY 4501 434C Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 IP EP2 Series User s Manual d Cyclone Based FPGA IP Module P2 50 50 P2 1 49 49 TO TO 48 48 9650 9660 MODEL 5025 552 47 47 CARRIER BOARD 1 0 TERMINATION 46 46 P3 OR P4 P5 P6 PANEL 45 45 44 44 43 43 bs x gt 4 4 42 42 FEET 40 40 TOP VIEW 39 39 38 38 37 37 36 36 35 35 E E STRAIN 50 PIN E 33 RELIEF RIBBON CABLE BLACK LINE ON CABLE CONNECTOR E 904 55 2002 261 INDICATES PIN 50 1004 512 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 POLARIZING 21 21 KEY 20 20 19 19 18 18 17 17 16 16 15 15 14 14 mi 11 11 50 PIN 10 10 CONN
37. RD 34 INDUSTRIAL I O PACK INTERFACE 34 DIFFERENTIAL 35 DIGITAL 36 LVDS 4 4 111 36 EXTERNAL CLOCK 1 37 POWER 6 44 4 11 100 37 APPENDIX CABLE MODEL 5025 551 38 TERMINATION PANEL MODEL 5025 552 38 TRANSITION MODEL 39 DRAWINGS 2 BLOCK 40 JTAG INTERFACE JUMPER LOCATION 40 RS485 41 4501 434 MECHANICAL 5 41 4501 463 CABLE 5025 551 SHIELDED 42 4501 464 TERMINATION PANEL 5025 552 42 4501 465 TRANSITION MODULE TRANS GP 43 The following manuals and part specifications provide the necessary information for in depth understanding of the IP EP2 Series board 2 FPGA Programming Guide Acromag IP EP2 EDK 71V016SA SRAM Specifications http www idt com Cyclone Data Book http www altera com CY22150 Specification http www cypress com IP Specification ANSI VITA 4 1995 Trademarks are the property
38. URATION JUMPER 2 1 INTERFACE CONFIGURATION JU SETTINGS CONFIGURE FPGA OVER IP BUS LOAD CONFIGURATION FROM FLASH OR PROGRAM FLASH VIA JTAG PROGRAM FPGA DIRECT JTAG SIGNALTAP II EITHER SETTING NOTE JTAG PROGRAMMING WILL OVERRIDE THE CURRENT CONFIGURATION SETTING HOWEVER TO LOAD THE FROM EITHER THE FLASH OR THE IP BUS THE JUMPER MUST BE SET CORRECTLY Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com LOGIC INTERFACE 1 GND 2 Seri UN es User s Manual RS485 IT 1 1 0 ae HALF DUPLEX MULTIPOI Cyclone Based FPGA IP Module 4 1 T NETWORK pue UNIT lt 33 1 0 1 0 1 0 CHANNEL DIRECTION MODULE LOGIC NOTES de 0 0 UNIT 2 CTION DIRE 1 0 CHANNEL MODULE LOGIC THE BUS IS A HALF DUPLEX B UNIT N 1 170 5 DIRECTION 1 0 CHANNEL MODULE LOGIC MODULE LOGIC 1 0 CHANNEL 1 0 DIRECTION THE 5 485 STANDARD ALLOWS UP 52 DRIVER RECEIVERS TO BE CONNECTED TO A SINGLE BUS DIRECTIONAL BUS BUT ONLY ONE DRIVER SHOULD BE ACTIVE AT A TIME TERMINATION SHOULD BE USED AND ONLY LOCAT
39. a 42 45 46 21 BEC EAE 49 50 The board is non isolated since there is electrical continuity between the Non Isolation logic and field I O grounds As such the field I O connections not Considerations isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 2 2 Series User s Manual 3 0 PROGRAMMING INFORMATION CONFIGURATION MODE Configuration Address Maps Table 3 1 IP EP2 Series I O Space Configuration Address Map 1 The IP module will return 0 for all addresses that are Not Used 2 The IP module will not respond to read write operations at these addresses Cyclone Based FPGA IP Module This Section provides the specific information necessary to program and operate the board The IP EP2 Series Module has two distinct operating modes The first is the Configuration Mode In this mode the board has limited functionality since the FPGA is not yet configured The second is the User operation mode where the FPGA is programmed Board operation in this mode is determined by the FPGA programming To determine the current mode read the Identification Space Refer to Table 3 2 The I O space address map for the IP EP2 Series when in configuratio
40. ammed after every power up The second method is to configure the part directly using a JTAG interface The JTAG interface will automatically over write any existing configuration and can be completed at any time using a standard Altera JTAG download cable such as the ByteBlaster 28 This cable is NOT provided by Acromag Once again all programming is lost at power down using the direct JTAG configuration approach Finally the IP EP2 Series module contains a Flash Configuration Device Altera EPCS4 or equivalent that can be programmed indirectly through the JTAG interface using the Altera Serial Flash Loader The Serial Flash Loader creates a logic bridge between the Cyclone II JTAG interface and the controls of the FLASH device This bridge allows the user to program the Flash via the JTAG interface The FLASH device cannot be programmed through the IP interface This method is recommended for debugged designs since the Flash device programs the Altera FPGA at power up The programming procedures for each of the three methods are below The IP EP2 Series can implement configuration of the Altera FPGA over IP EP2 IP Direct the IP bus interface The IP EP2 module uses the Altera passive serial Configuration Procedure scheme with the IP bus serving as the download path Thus download and configuration are implemented with no special hardware or cables Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1
41. com http www acromag com 26 2 Series User s Manual Cyclone Based FPGA IP Module USER MODE Programming Example for AVME9630 9660 Carrier Boards 1 2 Clear the global interrupt enable bit in the Carrier Board Status Register by writing a 0 to bit Perform Specific IP Module Programming see the Change of State or Level Match programming examples that follow as required for your application Write to the carrier board Interrupt Level Register to program the desired interrupt level per bits 2 1 amp 0 Write 1 to the carrier board IP Interrupt Clear Register corresponding to the IP interrupt request s being configured Write 1 to the carrier board IP Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled Enable interrupts from the carrier board by writing a 1 to bit 3 the Global Interrupt Enable Bit of the Carrier Board Status Register Programming Example for Change of State Interrupts 1 Program the Interrupt Vector Register with the user specified interrupt vector This vector forms a pointer to a location in memory that contains the address of the interrupt handling routine Select channel Change of State interrupts by writing a 1 to each channel s respective bit the Interrupt Type Register Note that Change Of State interrupts specified with 1 may be mixed with polarity match interrupts specified with
42. dule specification ANSI VITA 4 1995 The supplied FPGA logic example includes address decoding and ID read write control circuitry interrupt handling and ID storage implementation Address decoding of the six IP address signals A 1 6 is implemented in the FPGA in conjunction with the IP select signals to identify access to the IP module s ID or I O space In addition the byte strobes BSO and BS1 are decoded to identify low byte high byte or double byte data transfers The carrier to IP module interface allows access to both ID and I O space via 16 or 8 bit data transfers Read only access to ID space provides the identification for the individual module as given in Table 3 2 per the IP specification Read and write accesses to the space provide a means to control the IP EP2 The IP EP2 has 64K words of SRAM available Read and write accesses to the SRAM are implemented through the IP module space A start address is specified in the Memory Address register This start address will automatically be incremented by hardware for each access to the Memory Data register The IP EP2 also has a Clock Generator chip A clock frequency from 250KHz to 100MHz is programmable via the IP module space The generated clock frequency is input to the FPGA on pin 183 This clock can be used to synchronize operations with other IP modules Interrupt Operation For the supplied FPGA configuration digital input channels
43. el register Read Write is performed through 16 bit or 8 bit data transfer cycles in the IP module I O space e High Speed Access times for all data transfer cycles are described in terms of wait states For the supplied IP module example wait states are minimized for all read and write operations see specifications for detailed information Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 2 Series User s Manual Cyclone Based FPGA Module SIGNAL INTERFACE PRODUCTS This IP module will mate directly to any industry standard IP carrier board including Acromag s AVME9668 VMEbus APC8620A 21A PCI bus and ACPC8625 30 35 Compact PCI bus non intelligent carrier boards A wide range of other Acromag IP modules are also available to serve your Appendia mors signal conditioning and interface needs information about these The cables and termination panels described in the following products paragraphs represent some of the accessories available from Acromag Each Acromag carrier has its own unique accessories They are not all listed in this document Consult your carrier board documentation for the correct interface product part numbers to ensure compatibility with your carrier board Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or oth
44. er Power IP EP201 IP EP202 iP EP203 IP EP204 IP EP201E 202 IP EP203E IP EP204E pg for Example Typical 325mA 580mA 470 380 5V 5 m i m m 580mA 1100 850 680 Typical Not Used 5 Max Not Used 1 Monotonic ramp up required with 100ms maximum rise time 2 Typical operating amperage assumes of I O is driving a standard load Operating Temperature Standard Unit 0 C to 70 C ENVIRONMENTAL E Version 40 C to 85 C Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 3V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with no register upsets Conducted F Immunity Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no register upsets Electromagnetic Interference Immunity EMI No register upsets occur under the influence of EMI from switching solenoids commutator motors and drill motors Surge Immunity Not required for signal I O per European Norm EN50082 1 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 4 2 Series User s Manual Cyclone Based FPGA IP Module SPECIFICATIONS Reliability Prediction FPGA SRAM CLOCK GENERATOR INDUSTRIAL I O PACK INT
45. er base address offsets shown in Table 3 3 If the Input Output port is to be used as an output you should first set the output register bit as desired before setting the Direction Control register Note if you select as an output port before setting this Input Output register the output port will be logic low as this is the power up reset state of the output register bits Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 1 O Table 3 5 shows all channels and their corresponding 1 data register USER MODE bit for each of the IP EP2 models The register bits not listed will not be used See the memory map to identify the addresses required to control I O registers Used Input Output Channel Register Bits Table 3 5 Input Output Model VO Register Bits Register Module Mapping See Table 2 1 for Pin Assignments TTL Channels 0 to 47 Lodo Register Bits 0 to 47 Differential RS485 Channels 0 to 23 ids Register Bits 0 to 23 IP EP203 TTL Channels 0 to 23 Diff RS485 Channels 12 to 23 Register Bits 0 to 23 Register Bits 32 to 43 LVDS Channels 0 to 23 20 Register Bits 0 to 23 Channel read write operations use 8 bit or 16 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs on a power on or s
46. er compatible carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital while the shielded cable is recommended for optimum performance with precision analog I O applications Termination Panel Model 5025 552 A DIN rail mountable panel that provides 50 screw terminals for universal field I O termination Connects to all Acromag carriers or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 or 5025 551 X Transition Module Model TRANS GP This module repeats field connections of IP modules A through D for rear exit from a VMEbus card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is double height 60 single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth It connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 7 Acromag provides an engineering design kit for the 2 Series ENGINEERING DESIGN KIT boards sold separately
47. in groups of four Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 0 2 Series User s Manual Cyclone Based FPGA IP Module LVDS Input Output Logic LVDS I O on the IP EP204 are provided through the Field Connector refer to Table 2 3 LVDS channels 0 31 to the FPGA are buffered using multidrop LVDS line drivers and receivers The drivers and receivers are standard LVDS signaling characteristics TIA EIA 644 with double the current for multipoint applications Field inputs to these receivers include a 100 ohm termination resistor Signals received are converted from the LVDS voltages to the LVTTL levels required by the FPGA Likewise LVTTL signals are converted to the TIA EIA 644 LVDS voltages for data output transmission The direction control of the LVDS channels is controlled in groups of four Fail Safe Operation The IP EP2 Series operation is considered Fail safe That is the input output channels are always configured as input upon power up reset and a system software reset This is done for safety reasons to ensure reliable control of the output state under all conditions JTAG INTERFACE All IP EP2 models have a standard Altera JTAG header It readily connects to any compatible Altera programming cable such as the ByteBlaster 2 amp or MasterBlaster The JTAG interface pins connect only to the Altera FPGA This connection can be used to program the FPGA or
48. ing during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given t
49. mum e Vy 0 8V Maximum Vmax 5 5V Maximum Digital Propagation Delay e Driver Receiver Input to Output Delay 6 3ns Maximum Pull down Resistors 10K pull down resistors to GND are installed on each Digital I O line LVDS I O Channel Configuration 24 Channels IP EP204 Bi directional LVDS signals are direction controlled in groups of 4 LVDS 1 0 Electrical 247mV Min 454mV Max LVDS Driver Output Voltage with 50Q load Characteristics e 1 37 V Max Common Mode Output Voltage e 50 mV Min to 50mV Max LVDS Input Threshold Voltage e Compatible with either LVDS TIA EIA 644 or M LVDS TIA EIA 899 for Multipoint Data Interchange e Driver Propagation Delay Time 2 7ns Maximum e Driver Output Signal Transition Time 1 0ns Maximum e Receiver Propagation Delay Time 4 5ns Maximum e Receiver Output Signal Transition Time 1 5ns Maximum LVDS Propagation Delay Maximum Data Rate e Maximum Data Rate 100MHz 1m Termination Resistors Termination Resistors Non removable 1000 termination resistors are in place for each of the LVDS channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 3 7 Channel Configuration 1 External LVTTL Clock input DC Electrical Characteristics e 3 3V Maximum e Vy 0 8V Maximum e Vi 1 7V Minimum Power On Delay The IP EP2 has a power up time of 0 3 seconds During
50. n mode is as shown in Table 3 1 The module is always in configuration mode upon system power up when the direct IP programming method is selected or when the EnableCPLD line on pin L3 of the Altera FPGA is a logic high The EnableCPLD line is a signal that communicates to the IP EP2 Series hardware the status configured vs non configured of the FPGA This signal must be held low by the Altera FPGA after successful configuration to disable configuration mode If you have a configured FPGA and then wanted to re configure the FPGA you must enable the configuration mode This is accomplished by driving pin L3 of the FPGA to a logic high level via control register bit O If you change your mind and want to return control back to the FPGA an IP bus reset can be used to clear or drive pin L3 to a logic low level see example VHDL file Note that the Altera FPGA must not drive the IP bus data lines or the ACK signal after you return to configuration mode from a pre configured FPGA Also IP bus write cycles must be disabled from changing the registers of your configured FPGA while in configuration mode The space address map used to configure the FPGA is shown Table 3 1 16 or 8 bit register accesses are permitted Ree Base Addr D15 008 007 DOO Addr M Not Used m PER egister Not Used Configuration Data Register Not Acknowledged This manual is presented using the Big Endian byte ordering format Big Endian is the con
51. nable Register 20 Interrupt Type Configuration Register 20 Interrupt Status Register 21 Interrupt Polarity Register 21 Interrupt Vector Register 22 Memory Data Register 22 Memory Address Register 23 Clock Control 23 Clock Trigger Register 24 Clock Programming Procedure 24 Programming Interrupts 25 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 3 4 0 THEORY OF OPERATION INDUSTRIAL I O PACK INTERFACE 28 FIEED VO 29 JTAG 4 441041 4 30 EXAMPLE DESIGN cccssssssssssssssssssesssssseessssneesesssecs 30 FPGA 2 31 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE 32 PRELIMINARY SERVICE PROCEDURE 32 WHERE TO GET 32 6 0 SPECIFICATIONS PHYSICAE 33 ENVIRONMENTAL eene 33 BOA
52. nal must remain at a logic low until configuration has completed Writing to either bits 1 or 2 will have no effect Bits 4 is the CRC ERROR signal from the FPGA This function is disabled in the example program must be enabled within the Quartus Il software Refer to the Cyclone Manual for information on this signal Bit 5 is the value of MSELO as determined by the configuration jumper A logic high on this bit indicates that configuration will occur over the IP bus A logic low indicates that the configuration data is loaded from Flash Bits 3 and 6 to 7 are not used and will return logic 0 when read Configuration Data Register Write Only Base Addr 3H This write only register is a conduit for the programming data file when configuring the IP EP2 module over the IP bus Prior to configuration the user must write a logic 1 to bit zero of the Configuration Control Status Register Then after bit 0 of the Configuration Control Status register reads logic low again up to 160mS the programming file is written to this register one byte at a time The data is transferred serially to the FPGA therefore a write to this register requires 8 wait states The IP EP2 module has three methods of configuration The first is CONFIGURATION configuring the Altera FPGA directly over the IP Bus This method uses the METHODOLOGIES passive serial scheme to directly program the FPGA Note that this scheme requires the FPGA to be reprogr
53. ne FGPA TTL 485 422 LVDS Operating MODEL Channels Channels Channels Temperature Range 48 0 0 0070 0 0 8 lt Pera 2 0 050 24 9 405855 24 9 997 Pepas 24 12 9 400855 iege o o a 050 400850 e Reconfigurable Altera FPGA system configuration of the FPGA is implemented via a standard JTAG interface or the IP bus This provides a means for implementation of custom user defined designs High Channel Count Digital Interface 5485 LVDS and TTL interface options are available Models with up to 24 RS485 24 LVDS a mix of 12 RS485 and 24 TTL or up to 48 TTL digital input output channels are available External Clock An LVTTL external clock input is available on all models The external clock is connected directly to a global clock pin on the Altera FPGA e 5V Tolerance All TTL I O are 5V tolerant e Channel Input Output Control The direction of the TTL digital channels is controlled in groups of 8 channels The direction of the differential digital signals is controlled in groups of 4 channels e Long Distance Data Transmission Data transmission with RS485 RS422 Transceivers allow up to 32 nodes and up to 4000 feet of transmission cable Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series Use
54. nfiguration the board will be in User mode with the Altera FPGA in control of the IP bus interface RODE e Refer to the documentation provided with the IP EP2 EDK for further instructions on JTAG configuration Each IP module contains identification ID information that resides in the IP IDENTIFICATION SPACE ID space per the IP module specification This area of memory contains at Read Only most 32 bytes of information Both fixed and variable information may be present within the ID space Fixed information includes the IPAH identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP EP2 Series ID space does not contain any variable e g unique calibration information ID space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian Motorola or VME bus Even addresses are used on the Little Endian PCI bus The IP EP2 Series ID space will read differently in configuration mode than it does in user mode In configuration mode the IP model code at base address OBH will read a 48H while in user mode the same byte will read 49H In addition the CRC byte at base address 17H will read a BAH in configuration mode and read a DBH in user mode All other ID space bytes will read the same in both configuration mode and user mode In user mode the ID space must be defined in the internal logic of the FPGA In order
55. nterrupts Generates INTREQO interrupt request as configured in the example program An INT select cycle will return the Interrupt Vector Register INTREQ1 is available but not implemented in the example design Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 3 5 DMA Two IP requests are available but not implemented in the example SPECIFICATIONS design Wait States Each IP bus cycle in the example design consists of three states First is the Select state where the module is given its request Second is a wait or processing state implemented by the IP EP2 module Third is an acknowledge state The number of wait states in both Configuration and User mode is defined in the subsequent table Due to the design of the IP EP2 a minimum of 1 wait state is required for any IP bus operation when in User mode Failure to provide the wait state may result in read or write failure Configuration Mode User Mode ID Space 1 wait state 1 wait state Unless otherwise defined wait state definitions are for all read 1 wait state and write operations Space Write Configuration Data Register 8 wait states All other Read Write 1 wait state INT Space N A 1 wait state MEM Space N A N A Channel Configuration 24 IP EP202 or 12 203 Bi directional EIA 485 422 differential signal
56. nterrupts enabled will never set its interrupt status flag A channel s interrupt can be cleared by writing a 1 to its bit position in the Interrupt Status Register writing a 1 acts as a reset signal to clear the set state This is known as the Release On Register Access RORA method as defined in the VME system architecture specification However if the condition which caused the interrupt to occur remains the interrupt will be generated again unless disabled via the Interrupt Enable Register In addition an interrupt will be generated if any of the channels enabled for interrupt have an interrupt pending i e one that has not been cleared Writing 0 to a bit location has no effect that is a pending interrupt will remain pending Note that interrupts are not prioritized via hardware The system software must handle interrupt prioritization The Interrupt Status register at the carrier s base address offset OFH is used to monitor pending interrupts corresponding to channels 00 through 07 For example channel 00 is monitored via data bit 0 The unused upper 8 bits of this register are Not Used and will always read logic 0 All bits are set to 0 following a reset meaning that all interrupts are cleared Interrupt Polarity Registers Read Write Base 11H The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled f
57. o a logic low holding the FPGA in user mode Bits 10 to 8 are used to set the IP EP2 model corresponding to your I O mix This will allow the Altera FPGA to properly map Input Output registers to the I O transceivers present on your module Bits 10 to 8 should be set as identified in the following table to identify the model corresponding to your IP EP2 Table 3 4 Control Register Control Register Bits 10 9 and 8 Identification Bits IP Model Bit 10 Disabled IP EP201 IP EP203 IP EP204 Ege SIP 20 1 0 Bit 11 is reserved for factory testing For normal operation this bit should always be logic low Bit 15 can be used to issue a software reset When bit 15 is set to a logic high a software reset will occur Reading this register will return logic low on all data lines bits except for bits 11 to 8 which will reflect their last written state Input Output Registers Read Write Base Addr 03H to 07H Forty eight possible input output channels numbered 0 through 47 may be individually accessed via these registers The Input Output Channel registers are used to monitor read or set write channels 0 through 47 The first eight channels are accessed at the carrier base address 03H via the low data byte The next eight channels are accessed at the carrier base address 02H via the high data byte The remaining 32 channels are accessed similarly at the carri
58. o air filtering Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to the IP Mechanical Assembly Drawing located in the Drawings Section of this manual and the following discussion for configuration and assembly instructions Default Hardware Jumper Configuration There is one jumper on the board that is used to select the method for loading the FPGA either from FLASH or direct from the IP bus The jumper is set at the factory to load from IP bus Refer to the JTAG Interface Jumper Location diagram in the Drawings Section of this manual for the jumper location and settings Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Series User s Manual Cyclone Based FPGA IP Module 5 Field I O Connector P2 P2 provides the field I O interface connector for mating IP modules to the carrier board P2 is a 50 pin female receptacle header which mates to the male connector of the carrier board This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 Screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing in the Drawings Sections of this manual The field and logic side connectors are
59. of C functions which link with existing user code to make possible simple control of all Acromag PCI boards IP MODULE QNX Acromag provides a software product sold separately consisting of SOFTWARE board software This software Model IPSW API QNX is composed of QNX real time operating system libraries for all Acromag IP modules and carriers including the AVME9670 AVME9660 9630 APC8620A 21A ACPC8630 35 and ACPC8625 The software supports X86 PCI bus only and is implemented as library of functions These functions link with existing user code to make possible simple control of all Acromag IP modules and carriers Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 8 IP EP2 Series User s Manual Cyclone Based FPGA IP Module 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION CAUTION SENSITIVE ELECTRONIC DEVICES 00 SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation or conduction cooling must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Configuration Upon receipt of this product inspect the shipping carton for evidence of mishandl
60. oftware reset The unused upper bits of these registers will always read logic 0 Direction Control Register Read Write Base Addr 09H The data direction input or output of the digital channels is selected via this register The data direction of all differential channels are set as a group of two or four channels while data direction of all TTL channels is controlled as a group of 8 channels Setting a bit high configures the data direction for the identified channels as output Setting the control bit low configures the corresponding channel s data direction for input Refer to Table 3 6 for the corresponding channels for each bit in the Direction Control Register The default power up state of these registers is logic low Thus all channels are configured as inputs on system reset or power up All not used bits will read low logic See Table 2 1 for field I O pin assignments corresponding to each of the Differential and TTL channels listed below Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 20 2 Series User s Manual Cyclone Based FPGA Module Table 3 6 Direction Control Function by Model Register Bit s 202 204 0 Not Used Ch 0 1 12 13 Ch 12 13 Not Used Ch 2 3 14 15 Ch 14 15 Not Used Ch 4 5 16 17 Ch 16 17 Not Used Ch 6 7 18 19 Ch 18 19 Not Used Ch 8 9 20 21 Ch 20 21 s CANI 7
61. or level interrupts A 0 bit specifies that an interrupt will occur when the corresponding input channel is low i e 0 in the digital input channel data Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 2 2 Series User s Manual Cyclone Based FPGA IP Module USER MODE register A 1 bit means that an interrupt will occur when the input channel is high i e a 1 in the digital input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt Type Configuration Register The Interrupt Polarity register at the carrier s base address offset 11H is used to control channels 00 through 07 For example channel 00 is controlled data bit 0 as seen in the table below Interrupt Polarity Register MSB LSB 06 Ch 05 Ch 03 Ch 00 The upper 8 bits of this register are Not Used and will always read logic low All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are below TTL threshold provided they are enabled for interrupt on level Interrupt Vector Register Read Write Base 13H The Interrupt Vector Register maintains an 8 bit interrupt pointer for all channels configured as input channels
62. r 2 is a 16 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock The register contains the following control bits as specified in the Cypress CY22150 spec sheet D6 PB 014 CLKSRC1 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 4 2 Series User s Manual Cyclone Based FPGA IP Module USER MODE Refer to Program procedure to set Clock Frequency later in this manual for information on determining the value of these bits A software or hardware reset will clear this register to zero Clock Control Reg 3 Read Write Base 1DH The Clock Control Register 3 is an 8 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock In this register only DO bit 0 and D7 bit 7 are required The other bits D1 D6 are not used The value for DO is zero if the carrier board provides an 8MHz clock to the FPGA DO is one if the carrier board provides a 32MHz signal to the FPGA D7 is an enable disable signal for the CY22150 IC Writing one to D7 will disable the clock generator chip including the programming function Setting D7 to zero will allow for normal operation A software or hardware reset will clear this register to zero Clock Trigger Register Read Write Base 1FH The Clock Trigger Register is an 8 bit register To initiate programming of the Cyp
63. r s Manual Cyclone Based FPGA IP Module D 64K x 16 SRAM 64K x 16 static random access memory SRAM is KEY FEATURES directly accessed by the Altera device Custom user defined design logic for the Altera FPGA will permit use of the SRAM as FIFO memory or single port memory as required by the application e Example Design Provided An example VHDL design which includes implementation of the IP bus interface and control of digital I O with software programmable Interrupts is provided e Programmable Clock Generator A clock generator is provided for applications requiring a custom user specified clock frequency The clock generator can be programmed to any desired frequency value between 250KHz and 100 2 Power Up amp System Reset is Failsafe For safety all channels are configured as inputs upon power up and after a system reset Hardware Program Disable JTAG and IP bus reconfiguration of the FPGA can be hardware disabled by the removal of zero ohm resistors on the board INDUSTRIAL I O PACK e Clock Speed Supports an 8 or 32 MHz IP bus clock speed INTERFACE FEATURES e High density Single size industry standard IP module footprint Up to four units may be mounted on a 6U VMEbus carrier board or five units may be mounted on a PCI carrier board Local ID Each IP module has its own 8 bit ID information which is accessed via data transfers in the ID space e 16 bit amp 8 bit Chann
64. ress CY22150 Programmable Clock with the values set in Clock Control Registers 1 2 and 3 write a 1 to bit O of this register During programming bit 0 will remain logic high The programming process takes approximately 1 2ms to complete after the initial trigger A software or hardware reset has no affect on this register Program Procedure to Set Clock Frequency At power up the programmable clock has no valid output The clock can be programmed for an output frequency from 250 KHz to 100 MHz The clock can be programmed at any time during device operation Program the clock using the following process The program words required for Clock Control Register 1 2 and 3 can be calculated using a program provided by Acromag BitCalc2K1 Version 2 supplied with the EDK Alternately using the Clock Control Registers Data Maps and the CY22150 specification sheet the necessary values can be calculated Cypress has a program CyberClocks available to aid with calculations Note that the user will have to combine the individual variables into the control words as outlined in the register descriptions The CY22150 Specification Sheets and CyberClocks program are available from Cypress amp at www cypress com The reference frequency input to the Cypress CY22150 is the same as the carrier clock either 8MHz or 32MHz Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual
65. s are direction controlled in groups of four DIFFERENTIAL I O e 1 5V Min 3 3V Max Differential Driver Output Voltage with 54 load E e Max Common Mode Output Voltage aracteristics e 0 2 Min to 0 05 Max Differential Input Threshold Voltage 7 lt lt 12V e 15mV Typical Input Hysteresis 96 Minimum Input Resistance The receiver contains a fail safe feature that results in a logic high output state if the inputs are unconnected floating or shorted Differential Propagation e Driver Input to Output Delay 27ns Typical 40ns Maximum Delay e Receiver Input to Output Delay 33ns Typical 60ns Maximum Termination Resistors Termination resistors are not provided External Termination Resistors 120 Ohm termination resistors for EIA RS485 422 differential receivers are recommended Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 6 2 Series User s Manual Cyclone Based FPGA IP Module DIGITAL TTL TTL Channel Configuration 48 Channels IP EP201 or 24 Channels IP EP203 of bi directional TTL Transceivers Direction controlled in groups of eight Reset Power Up Condition All Digital Channels Default to Input Digital I O DC Electrical ia Characteristics Digital I O DC Electrical Characteristics Vou 3 1V Minimum e 0 55V Maximum e 24 0 24 0 e 2 0V Mini
66. tera Quartus Il software 4 Upon successful configuration the board will be in User mode with the Altera FPGA in control of the IP bus interface It is good practice to issue a software reset prior to operating the board Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 1 D Refer to the documentation provided with the IP EP2 EDK for further instructions on JTAG configuration The configuration FLASH can be programmed using the JTAG interface IP EP2 FLASH Configuration The JTAG interface can either program the FPGA directly or program the Procedure FLASH configuration memory When programming the FLASH the Altera FPGA acts as a logic bridge between the JTAG interface and the configuration device Once the FLASH is programmed the Altera FPGA will load that program at power up The following is the general procedure for programming the FLASH using the JTAG interface Connect the 10 pin Altera JTAG cable not provided to the board Set the programming jumper to the FLASH position Power up the carrier board Download the Configuration file to the FPGA using Altera Quartus II software An indirect FLASH configuration requires a jic file After download the board must be reset to load the proper configuration Either power down the board or write 01H to the configuration control register at address 01H 6 Upon successful co
67. the FLASH device When programming the FLASH device the FPGA acts as a bridge between the FLASH device and the JTAG interface Once programming the FLASH is completed the FPGA will load the program file from FLASH at power up if the programming jumper is set to the FLASH position Refer to the Configuring Chapter of the Cyclone Il Device Handbook from Altera for further information Clock Generator Interface FPGA Pin Definitions FPGA INITIALIZATION Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 2 IP EP2 Series User s Manual 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP www acromag com Cyclone Based FPGA IP Module Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair
68. ution Example of Generic Interrupt Handler Actions A Disable the interrupting IP by writing 0 to the appropriate bit in the AVME9630 9660 IP Interrupt Enable Register B Disable the interrupting channel s by writing a 0 to the appropriate bits in the IP EP2 Interrupt Enable Register C Clear the interrupting channel s by writing a 1 to the appropriate bits in the IP EP2 Interrupt Status Register D Enable the interrupting channel s by writing a 1 to the appropriate bits in the IP EP2 Interrupt Enable Register E Clear the interrupting IP by writing a 1 to the appropriate bit in the AVME9630 9660 IP Interrupt Clear Register F Enable the interrupting IP by writing a 1 to the appropriate bit in the AVME9630 9660 IP Interrupt Enable Register If the IP EP2 interrupt stimulus has been removed and no other IP modules have interrupts pending the interrupt cycle is complete i e the carrier board negates its interrupt request IRQ A f the IP EP2 interrupt stimulus remains a new interrupt request will immediately follow If the stimulus cannot be removed the IP EP2 should be disabled or reconfigured B If other IP modules have interrupts pending then the interrupt request IRQx will remain asserted This will start a new interrupt cycle Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 8 2 Series User s Manual Cyclone
69. vention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Thus byte accesses are done on odd address locations The Intel x86 family of microprocessors use the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such use of this module on a PC carrier board will require the use of the even address locations to access the 8 bit data while a VMEbus carrier requires the use of odd address locations Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IP EP2 Series User s Manual Cyclone Based FPGA IP Module 1 3 Configuration Control Status Register Read Write Base Addr 1H CONFIGURATION REGISTERS This read write register is used to initiate the reprogramming of the Cyclone FPGA and to monitor the status of the FPGA during configuration Bit O of this register is used to trigger FPGA programming Writing a logic 1 to bit O will enable a pulse on the FPGA nConfig signal If the IP carrier is providing a 32 2 clock the pulse length will be 40uS If the carrier provides a 8MHz clock the pulse length will be 160uS Bit 1 monitors the Altera nSTATUS signal which must remain high during configuration Bit 2 of the Status register reflects the status of the Altera FPGA CONF DONE signal The CONF DONE sig
70. xternal Clock Input Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 0 2 Series User s Manual Table 2 2 2 Model Channel Assignments 1 Refer to Table 2 1 for I O pin assignments Table 2 3 IP EP2 Model Global Clock Signals 1 These buffered I O are connected to global input pins on the FPGA Modification of the Example Design is required to use the global inputs Cyclone Based FPGA IP Module Model Register Bits IP EP201 TTL Channels 0 to 47 IP EP202 Differential RS485 Channels 0 to 23 TTL Channels Differential RS485 0 to 23 Channels 12 to 23 204 Differential LVDS Channels 0 to 23 The external clock pin is an LVTTL NOT 5V TOLERANT input that connects directly to a global clock input on the Altera FPGA In addition several buffered I O are routed to global input clock pins Table 2 3 summarizes the buffered I O are can be used for global input signals for each IP EP2 Series model Note that modification of the example file is required to utilize the additional global inputs Model Buffered Global Inputs IP EP201 TTL Channels 18 22 amp 46 IP EP202 RS485 Channels 9 11 amp 23 TTL Channels IP EP203 18 amp 22 RS485 Channel 23 IP EP204 LVDS Channels 9 11 amp 23 IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on

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