AXEL-X MB8AA3020 On-Chip Code User Manual
Contents
1. Disabling Ports Using Release Prior to 4 12 2007 Open up the PCS initialization and set M1 to 0 for each port you want to disable for example This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 15 PORT 00 Select port number 00 19 mode value M1 0 Select adaptive mode Next in the patch asm go to create task24_bp 4 and copy the following lines of code task24_bp4 Firmware Main Task skip skip data 0x0000 disable 15 0 data 0x0000 disable 23 0 21 0 19 16 The last two data fields correspond to the Port Disable Register in the register specification So for example if one wanted to disable ports 2 6 10 11 14 15 18 and 19 this would correspond to 0x800ccc44 in the Port Disable Register and is entered into the patch asm as such task24_bp4 Firmware Main Task skip skip data Oxcc44 disable 15 0 data 0x800c dxsable 23 0 211 60 19 16 2 4 4 2 Disabling Ports Using Release on or After to 4 12 2007 The release on or after 4 12 2007 open axelx_pcs_ph2. asm file task21_bp6 and task_23_bp6 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 29 Below is an excerpt from this file YO SSS task21_bp3 Task Port 21 bp 6 Link Up Wait Time data 40 10ms data 0 Oms data 0x0000 data 0x6006 PHY Addr 0 PHY Register 1 or a task23_bp3 Task Port 23 bp 6 Link Up Wait Time data 40 10ms data 0 Oms data 0x0000 data 0x6006 PHY Addr 0 PHY Register 1 ld PS Ss So a a SS a 2 4 11 Initializing 12C Master Ports Initialization of the 12C master ports is essential for proper operation of 12C master ports on AXEL X chip By default the on chip code initializes 12C port 2 as the master but user may use both I2C ports 1 and port 2 as master ports which would require both to be initialized properly Note No initialization of I2C slave ports is required This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other
3. bb cc dd ee ff data 0x0000 type 0x0000 data 0x0000 msw ee_ff data 0x0000 lsw2 cc_dd data 0x0000 lswl aa_bb Example MAC Address Assignment to REG STA Below is an example where a MAC address of 00 11 F5 76 82 61 and an EtherType of 88B5 to the REG_STA Ji Boas ae ASA eS RS ee eS BS ne eee A MAC Addresses API Access Up SSS saa a a Se Se a a ee Reg_STA 00 11 F5 76 82 61 data 0x88b5 type 0x88b5 data Ox8261 msw 82_61 data OxF576 lsw2 F5_76 data 0x0011 lswl 00_11 Example MAC Address Assignment to PORT 0 Below is an example where a MAC address of 00 11 F5 AB CD EF is applied to port 0 Recall that for ports an EtherType entry is not required This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 12 Hst_Adr_0 00 11 F5 AB CD EF data 0x0000 data OxCDEF data OxF5AB data 0x0011 2 4 2 Configuring 10GBE Transmitter and Receiver Fujitsu MB8AA3020 10GBE switch has an integrated 5 TAP FIR filter used for additional pre emphasis and a 2 order li
4. is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 33 Power On Port Reset MAC Address gt 3 z Downl firmwar Firmware is downloaded owngag are from EEPROM F N Papo s aa Se ee fe i f a i H This process is skip baa ag a gt when the AXEL X has i ese been warm restarted Start Multi task Environment p ICB_reg asm Firmware Task STATIC Set IRQ Handler CONFIGURABLE a Set Buffer Firmware asm i Management gt task_24 bp 3 i ee RER Set MAC co is Addresses ee aaron MAC_addres asm file gt a Set Switch Firmware asm Configuration gt task_24 bp 3 Register byteO byte 3 VLAN ICB Disable Ports MAC Address task_24 Firmware Table ICB Set Initialization Flag Complete This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for acc
5. 0 2 4 1 Assigning MAC Addresses By default the source code provided by the Fujitsu MB8AA3020 has a MAC address and EtherType of 0 So at the very minimum the user must assign a valid MAC address and Ethertype to every port and the station address in order for the switch to function properly These variables can be found in the MAC_address asm file under the symbol Hst_Adr_ 0 23 Shown in Figure 1 is the field description for the MAC address and EtherType field Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte O description Hst_Adr_O MAC Address xX XX XX XX XX1XX N A Port O Hst_Adr_1 MAC Address xX XX XX XX XXIXX N A Port 1 Hst_Adr_2 MAC Address xX XX XX XX XX1XX N A Port 2 Hst_Adr_3 MAC Address xx xx Xx XXIXX XX N A Port 3 Hst_Adr_4 MAC Address xX XX XX XX XX1XX N A Port 4 Hst_Adr_5 MAC Address xX XX XX XX XX1XX N A Port 5 Hst_Adr_6 MAC Address xX XX XX XX XX1XX N A Port 6 Hst_Adr_7 MAC Address xX XX XX XX XX1XX N A Port 7 Hst_Adr_8 MAC Address xX XX XX XX XX1XX N A Port 8 Hst_Adr_9 MAC Address xX XX XX XX XX1XX N A Port 9 Hst_Adr_10 MAC Address xX XX XX XX XX1XX N A Port 10 Hst_Adr_11 MAC Address xX XX XX XX XX1XX N A Port 11 Hst_Adr_12 MAC Address xX XX XX XX XX1XX N A Port 12 Hst_Adr_13 MAC Address xX XX XX XX XX1XX N A Port 13 Hst_Adr_14 MAC Address xX XX XX XX XX1XX N A Port 14 Hst_Adr_15 MAC Address xX XX XX XX XX1XX N A Port
6. 0 S2 0xc052 0x0000 PHY_TX23_MON_CTL Set Tx lane 3 MON_CTL 6 0 The coefficients can be modified either directly on Port 00 or via the pointer For example if a user wanted to modify Tap 0 on Lane 0 this is modified directly on Port 00 s template Below is the example S2 0xc010 0x03f2 PHY_TXO_EQ_CFGO Set Tx lane 0 tap 0 with 63 0 If instead the coefficients are using a pointer go to the pointer definition in the same file and modify the parameters Below is an example for Tap 1 Lane 0 which points to ICB_PCS_INDEX_1 S2 0Oxc011 ICB_PCS_INDEX_1 PHY_TXO_EQ_CFG1 Set Tx lane 0O tap 1 with 63 0 Going to ICB_PCS_INDEX_1 you can modify the value of this tap TABLE ICB_PCS_INDEX_1 PHY_TXn_EQ CFG1 0x03f2 Port 00 Once this is done you can simply apply the same template to other ports under the Copy_Config section of the same file Below is an example Copy_Config port reference copy port configuration Port_Disable port permanetly disabled port Power_Down port power off upon reset Copy_Config 0 0 CX4 template Copy_Config 1 XFI template Copy_Config 2 1 XFI Copy_Config 3 0 CX4 Copy_Config 4 0 CX4 Copy_Config 5 1 XFI Copy_Config 6 1 XFI Copy_Config ji 0 CX4 Copy_Config 8 0 CX4 Copy_Config 9 0 CX4 Copy_Config 10 0 CX4 Copy_Config gil 0 CX4 This document contains confidential information which shall not be reproduced or transferred to othe
7. 15 Hst_Adr_16 MAC Address xX XX XX XX XX1XX N A Port 16 Hst_Adr_17 MAC Address xX XX XX XX XX1XX N A Port 17 Hst_Adr_18 MAC Address xX XX XX XX XX1XX N A Port 19 Hst_Adr_19 MAC Address xX XX XX XX XX1XX N A Port 20 Hst_Adr_21 MAC Address xx xx Xx XX XX XX N A Port 21 Hst_Adr_23 MAC Address xX XX XX XX XX1XX N A Port 23 Reg_STA MAC Address xx xx xXx XX XX XX Ethertype vV Register Station Address Figure 1 Field Description MAC Address and EtherType Field This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 11 Note It is important to note that in order for the switch to function properly a valid MAC address must be assigned for every port and station address Below is an excerpt from the MAC_address asm file The first data field is two bytes long and refer to the EtherType the rest of the data field refer to the MAC address The EtherType is only used in the REG_STA address there is no requirement to assign an EtherType for the ports eS MAC Addresses API Access US is ee SR Oe Se She Se Se ee REG_STA aa
8. 7 ICB_PCS_INDEX_2 PHY_TX1_EQ_CFG2 Set Tx lane 1 tap 2 with 51 0 S2 0xc018 ICB_PCS_INDEX_3 PHY_TX1_EQ_CFG3 Set Tx lane 1 tap 3 with 63 1 S2 0xc019 0x0000 PHY_TX1_EQ_CFG4 Set Tx lane 1 tap 4 with 0 0 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained change without notice herein is believed to preliminary completeness be 17 in this document While the accurate and should not be relied upon for accuracy or information is subject to contained such information is S2 Oxc0Ola 0x03f0 PHY_TX2_EQ_CFGO Set Tx lane 2 tap 0 with 63 0 S2 Oxc01lb ICB_PCS_INDEX_1 PHY_TX2_EQ_CFG1 Set Tx lane 2 tap 1 with 63 0 S2 OxcOlc ICB_PCS_INDEX_2 PHY_TX2_EQ_CFG2 Set Tx lane 2 tap 2 with 51 0 S2 Oxc01ld ICB_PCS_INDEX_3 PHY_TX2_EQ_CFG3 Set Tx lane 2 tap 3 with 63 1 S2 OxcOle 0x0000 PHY_TX2_EQ_CFG4 Set Tx lane 2 tap 4 wit 0 0 S2 Oxc0O1f 0x03f0 PHY_TX3_EQ_CFGO Set Tx lane 3 tap 0 with 63 0 S2 0xc020 ICB_PCS_INDEX_1 PHY_TX3_EQ_CFG1 Set Tx lane 3 tap 1 with 63 0 S2 Oxc021 ICB_PCS_INDEX_2 PHY_TX3_EQ_CFG2 Set Tx lane 3 tap 2 with 51 0 S2 Oxc022 ICB_PCS_INDEX_3 PHY_TX3_EQ_CFG3 Set Tx lane 3 tap 3 with 63 1 s2 0xc023 0x0000 PHY_TX3_EQ_CFG4 Set Tx lane 3 tap 4 with 0
9. ANIE ATASE 2 4 4 Disabling POTTS cccccccccescceseessecenesesseeesecesseeeseeesee M 2 4 4 1 Disabling Ports Using Release Prior to 4 12 2007 s sssssssssssssisesssssrsrersrstrssrersrsnrsrsrsrtsrerererrsrereresreret 2 4 4 2 Disabling Ports Using Release on or After to 4 12 2007 oo eeeceeceseseesesesesseseeeseseceesesesteseaeeeeneees 2 4 5 Configuring Transmit Pre CMmphdSis i ccccceccesccsesseeseeseeseeeseeees 7 2 4 6 Configuring Transmit Receive Lane and Polarity Swapping 2 4 7 Configuring the Port Configuration Register ccccccccccsccsscssesscessessceseessceseesecsecsseeseseseeeeneseaeeaees 2 4 8 Configuring Link Aggregation s s s 2 4 9 Initializing GMII MII Registers 2 4 10 External PHY Initialization ZALI Initiahzing 2 CoMGSt r POr isiyi iniinis in AEA EAEEREN 30 3 0 MICRO ENGINE DESCRIPTION ssccscsssssssssssssssssssssssscessssnssssssssssscssesessessessessscessessessssessesseree 31 S ISTASK STRUCTURE inae a a EAE aa ea AAA EEE E a EE E E E ASEE 31 3 2 MB8AA3020 INITIALIZATION SEQUENCE c ccccsssccesssseceesseecessseecesseeecesseecesseecceeseeceeseeecesseeesenaeeeeses 33 3 3 1 Initialization Sequence for MII GMII o SA 3 3 2 Initialization Sequence fOr LOGBE Trin n e EE T E aE 39 4 0 BUILDING MB8AA3020 FIRMWARE IMAGE sssesesersssssscscscsceceeeceeeesesesesesososososososossesesesesesesoeeeeeee 41 4 1 BUMD PROCEDURE api a e E E E a E e E E a e r EA AER EAEE 41 This document contains confide
10. AXEL X MB8AA3020 On Chip Code User Manual REVISION 1 5 Release 10 29 2007 TABLE OF CONTENTS TABLE OF CONTENTSLIST OF FIGURES csccscsscsssssssssscsscsssssscssssssssessssessessessesessessessssessessessers 2 EES T OF FIGURES viscssssisccssenssnsssccsencvassscessscesessonsosecsvenssssssend ncesscecascasessedscccesesonssonecenegessiseaccescaensadseseseonsioe 3 LIST OF TABLEG cccccsccssscscecssssccessecsccsccsscessccsecessessescessscessessessecsssessessecssssssessessessssescescessssessesseceess 3 1 0 ABOUT THIS MANUA 0 scccsccsssccccccccescescessecsccsssessescececsessessessessssessecsesessessecsecsecessesseceesscsessesees 4 t T DOCUMENT OVER VIE Warih sd hit reren bassyedaigssitd E E EE E EEE 4 1 2 ACRONYM Soera ar E T OEO O R TEE TOTOE 6 20 INTRODUCTION vesssscsscssessassssesiacsseosendssetesssssssesensescsdendasssdeucensacsssusseasssasessssossssussusssscadessadsesessecssadesoese 7 2 1 BYTE DATA ORGANIZATION 328 2 2 MICRO COMMANDS ccscseccesessesesessesseseeeseenees sn 2 3 MB8AA3020 ON CHIP CODE DEFAULT SETTINGS cccccccceccssesscssescsseseesessesseecnessesseseesscsessesseseeneegs 10 2A GETING STARTED soin An aa AONE RER RER va leads Siew esas Wes E EAA 2 4 1 Assigning MAC Addresses 2 2 4 2 Configuring LOGBE Transmitter and Receiver s sccccccsccsccessssssessessceseesscesesseeseeeseeseeeseeeeneeeaeeaees 2 4 3 Mode Value Descriptio anenai aa cebea days casts Er ERE TELNE AEE LAT
11. Configuration Register As stated in 2 3 MB8AA3020 On Chip Code Default Settings there are certain default setting for the MB8AA3020 registers which are controlled by on chip code By default all 1OGBE ports are disabled with the generic firmware version In order to enable the ports by default follow the instructions below Below is an excerpt from the file CB_reg asm In this file the first two data fields of the pointer CB_Default_0 controls the Port Configuration Register i e base 000h as described in AXEL X MB8AA3020 Register Specification ICB_Default_0 all Port Config data 0x0001 0xd2000001 data 0xd100 31 Port Reset data 0x3800 data_ref ICB_Default_l In order to change the port from the default disable state to a forwarding state bits 16 17 in the port configuration register needs to change from their current state of 00 to 11 This is illustrated below ICB_Default_0 all Port Config data 0x0001 0xd2000001 data 0xd103 31 Port Reset data 0x3800 data_ref ICB_Default_l Although the value can be changed can be changed in CB_reg asm it is recommended the new value be placed in patch asm thus the patch asm file will look like the following a a ee Jf Device Initialization default 12KB Jumbo fo BS eS SS a a Ss Se SS ICB_Default_0 all Port Config skip data Oxd103 31 Port Reset This document contains confidential information which shall not be reproduced or transf
12. This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd in this While the accurate All information contained document change without notice herein is believed to preliminary completeness be such 31 information is subject to contained information is and should not be relied upon for accuracy or 31 task_RTC Ready Real Time Clock Table 6 Task Description This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 32 3 2 MB8AA3020 Initialization Sequence Shown in Figure 2 is the initialization sequence for the MB8AA3020 Fujitsu switch This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document
13. U Compiler Collection i e gcc The procedure for building the MB8AA3020 firmware image is described below 1 As stated in Section 2 4 1 Assigning MAC Addresses the user needs to assign an appropriate MAC address for the chip as well as each port This is done by editing the MAC_address asm file 2 Choose either fixed gain i e axel_pcs_phy_cfg_fixed_eval_board txt or adaptive gain i e axel_pcs_phy_cfg_adaptive_eval_board txt in the Makefile 3 Type make on the command line Two files named firmware dat and firmware sym will be generated and placed in the obj directory Firmware dat is the file that will be downloaded into the MB8AA3020 s EEPROM This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 41
14. arBox Reset i Fault Handler le Enable Link Wait Count 0 Execute PCS Restart ICB A Wait Timer C Wait Count PCS Status Clear Wait Time Read PCS Status 2 clear link handler bit 11 10 Check Link Status gt nen Read PCS Status 2 Wait Count 0 Wait Timer A Wait Count Threshold 1 Wait_Count lt Threshold Execute Link Fault p ICB Yes aA TA a Threshold 1 e End Wait_Count lt Threshold Figure 4 Initialization Sequence for 1OGBE Task This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 40 4 0 Building MB8AA3020 Firmware Image This section describes how to build the image for MB8AA3020 These same instructions can be found in the ReadMe file of the On Chip Code released with the chip 4 1 Build Procedure In order to compile the MB8AA3020 code the following is needed e MB8AA3020 on chip source code described above MB8AA3020 Make file e GN
15. ed in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 36 3 3 1 Initialization Sequence for MII GMII Shown in Figure 3 is the initialization sequence for task_ 21 23 MII GMII task This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 37 r 7 Wait_Count 0 Execute Port ICB es Wait_Count 0 Wait Link Down Polling Timer Wait_Count Wait Timer A 10ms Wait_Count wos a N y 3 _ heck Link N Status EN 4 ae yee NO geo SS UP i Phase D 2 Check Link Down _ Status Sy Up X Ln She o Threshold 1 A Threshold 1 i 5 wait_Count lt Threshold Wait Count lt Threshold ii No Wait Timer B 10ms l Execute Link up ICB A Wait Timer C 10ms Execute Link up ICB B Enable Link Fault Handler Execu
16. ent contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 1 0 About This Manual This document is intended to provide configuration description for Fujitsu MB8AA3020 10Gbps Ethernet switch on chip code 1 1 Document Overview The document includes a description of the following Getting started example Micro engine specification Memory map description Initialization sequence Global variable description Task descriptions Initialization code block On Chip Code Default Settings While all registers can be modified using the On Chip code these are the main registers that are supplied by default All setting in the switch configuration registers All setting in the port configuration registers All port interrupt status registers Switch status register Buffer management register Management port control register Host VLAN counter configuration register MAC configuration register MII GMII status control register Default MAC addresses for the switch and all ports Fixed or adaptive gain for receiver equalizer This doc
17. erred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 21 Note Although it is possible to modify the files directly this could have unknown side effects instead place the pointer and it s values for that you want to modify in patch asm 2 4 8 Configuring Link Aggregation The MB8AA3020 has the capability to initialize a link aggregation group using the on chip code Details of link aggregation set up can be found in AN207 Enabling Link Aggregation IEEE 802 3 clause 43 To set up link aggregation in the chip make sure that task24_bp4 is configured as described below task24_bp4 can be found in Firmware asm bp 4 Port Mode data_ref ICB_Post_Core_0 data_ref ICB_Post_Core_1 data_ref ICB_IRQ_O data 0x0000 The example below shows link aggregation for ports 2 6 10 11 14 15 18 and 19 this code should be placed in patch asm END_CODE_HEAP_NEW align_block ICB_SET_LAG_1 data 0x0008 disable LAG1 data 0x0000 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any o
18. ess document is subject to 2 3 MB8AA3020 On Chip Code Default Settings There are certain default settings for each register that are controlled using the on chip code Shown in Table 3 are the default setting for the on chip code Buffer Management Register 0x0020 BI Buffer Management Register 0x0020 Switch Config 0x0008 Switch Config 0x0008 26 24 Switch Config 0x0008 Switch Config 0x0008 Swtich Config 0x0008 Switch Config 0x0008 Switch Config 0x0008 L15 Switch Config 0x0008 L13 Switch Config 0x0008 o o HostWVLAN Counter Config 0x030c Table 3 Default Register Setting for On Chip Code Please note that Table 3 is an Excel Spreadsheet to see the complete listing of the registers double click on the Table and scroll down to the appropriate Register 2 4 Getting Started As mentioned in the introduction at the very least the user must set up the MAC address for every port as well as the chip for the 10GBE switch to function properly This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 1
19. hich shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 2 1 Byte data Organization In order to begin configuring the on chip code firmware we must first understand how the byte structure is set up in the assembly files Below is an example of a factious symbol and the data fields associated with the symbol Ll A O SaaS LY Example of data description PP SE ea ne ae Fe eS a Sa ee ee Example_symbol_0 Example of symbol data 0x0123 byte 1 01 byte 0 23 data 0x4567 byte 3 45 byte 2 67 data 0x8 9AB byte 5 89 byte 4 AB data OxCDEF byte 7 CD byte 6 EF Pl Epa RS ee es ee a Example of data description JJ SBS aa SaaS Aa SASS a ae a ea eS a The organization of the data fields always start with byte 1 and byte 0 corresponding to the first data field byte 3 and byte 2 corresponding to the second data field and so on Table 1 Data Byte Relationship describes the Data Byte relationship Data Bytes Byte 1 Byte 0 Byte 3 Byte 2 Byte 5 Byte 4 Byte 7 Byte 6 Table 1 Data Byte Relationship This document contains co
20. le the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 26 The default setting is for GMII however to convert from GMII to MII simply change the data_ref text from GMII to MII Below is an example Example Converting MDIO ports from GMIl to MII De es a a ee ee task28_bp3 MDIO Port 1 bp 3 skip data 0x0000 Interface Core ICB skip data_ref ICB_MDIO MII 0 Interface ICB Or a task29_bp3 MDIO Port 2 bp 3 skip data 0x0000 Interface Core ICB skip data_ref ICB_MDIO MII 0 Interface ICB H Seen a O Task Dependency fel SS SS Se RR a a ea MDIO 1 gt Port 21 MDIO 2 gt Port 23 Or Although the above examples show modification to Firmware asm in actuality you want to modify patch asm The modification for MDIO from GMIl to MII is shown below in the patch asm file task28_bp3 MDIO Port 1 skip skip skip This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or com
21. n contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 28 Mode Value Description GMII MII I F initialization skip link up monitor check PHY status check PHY status w link fault handler Table 5 MII GMII Mode Description By default the on chip code poll the PHY status check with link fault handler This may not be appropriate for all situations because the user may not have a PHY or the MDIO may not be connected up to the PHY If this is the case in then you will want to bypass the PHY status check by enabling Mode 2 Below is an example where the PHY status Example of MDIO with PHY status disable if BASES RR RS SSS RR ee a ea task21_bp3 Task Port 21 be 3 Port IRQ Service Required vector Mode data 0x4002 Use MDIO 0O for polling Mode 2 data 0x0000 Link up Check Threshold of ae aa task23_bp3 Task Port 23 bp 3 Port IRQ Service Required vector Mode data 0x8002 Use MDIO 2 for polling Mode 2 data 0x0000 Link up Check Threshold data 0x0801 11 Port Security Violation 0 Link Fault data 0x0000 JI aa Lastly by default of the PHY address on the AXEL X evaluation is 0 for both port 21 and port 23 however this is not universal for all design In order to change this refer to Firmware
22. near amplifier used for receiver equalization The details of which can be found in AXEL X MB8AA3020 PCS Register Specification Before programming the on chip the user must decide on the following configuration parameters XAUI mode of operation of XFI mode of operation for XFI 10GBE ports Transmit pre emphasis co efficient to be used Fixed gain or adaptive gain equalization for the receiver Transmitter lane swapping Transmitter polarity swapping Receiver lane swapping Receiver polarity swapping Below is an example of how to modify the on chip code for adaptive gain Example Modification of Receiver Gain In order to modify the receiver for fixed or dynamic gain open the Makefile Below is an excerpt from the Makefile AWK gawk PCS_AWK bin ICB_PCS awk PCS_CONF axelx_pcs_phy_cfg_adaptive_eval_board txt PCS_CONF register axelx_pcs_phy_cfg_adaptive_eval_board txt PCS_CONF register axelx_pcs_phy_cfg_fixed_eval_board txt This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy
23. nfidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 2 2 Micro commands Listed in Table 2 is a list of commonly used micro commands that are executed by the MB8AA3020 micro engine Micro command Description align_block Align the block frame N A Skip Skip the current data 0x1234 instruction Skip data 0x4567 data Assigns a 16 bit value data lt 16 bit value gt to the data data_ref The data is reference data_ref ICB PCS_0 to a pointer that is defined by the user ICB_PCS 0 using data 0x1234 data 0x4567 Skip Skip Table 2 Micro Commands This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completen
24. ntial information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness LIST OF FIGURES Figure Field Description MAC Address and EtherType Field oo eee eee eeeeeeeeeeee 11 Figure 2 Initialization Sequence eee seeseeseeseeseeeseceseeeseeeseesseesseesseesaeesaeeseeeseeeseesaees 36 Figure 3 Initialization Sequence for MII GMII Task 0 00 eseeeseeseeereeseeeseeeseeeseeenees 38 Figure 4 Initialization Sequence for LOGBE Task eee eeeeseeseeereeseeeseeseeeseeeneeenees 40 LIST OF TABLES Table 1 Data Byte Relationship 00 0 0 cece eseeseescesceeseeseeeeseesscessecsaeesaeesaeeaseeseaesesesaeeees 8 Table 2 Micro Commands i atsicios i isis dul aR aai Eae a as E ehee 9 Table 3 Default Register Setting for On Chip Code cece ceeeeeeceeeeeeeeseeeeeeeeeeeeaees 10 Table 4 LOGBE Mode Value Description eee ce eeeeceeceeecseeeeeceeeceseceneceeecneeceeeneecneees 15 Table 5 MII GMII Mode Description eee seeseesessecesecesecsseceeeceeeceeceseeeseseseceeesneeseees 29 Fable 6 Task Description icici ob tsn ennea eitsediauleebiode eine diene a aao 32 This docum
25. ocuments or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 14 There are 6 mode values that each port can take they are described below in Table 4 Mode Value Description skip PCS initialization XGMII Verif skip link up i Fixed gain PCS Initialization Fixed gain PCS Initialization check Link Status Fixed gain PCS Initialization w link fault handler Adaptive PCS Initialization O11 amp Go P O Table 4 10GBE Mode Value Description As an example if the user wanted to create a PCS initialization sequence with fixed gain the mode bit would be 2 PORT 00 Select port number 00 19 mode value g M1 2 Select adaptive mode 2 4 4 Disabling Ports The MB8AA3021 microcode allows a user to set certain ports in a disable or port down state to conserve power consumption In a port disable state the port is permanently disabled in the code and cannot be power up without a microcode change In a power down state the power is powered off on boot up The way ports are disabled will depend on the microcode release For release code prior to 4 12 2007 use the following method 2 4 4 1
26. oduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 2 0 Introduction This section focuses on a step by step example of how to configure and compile the MB8AA3020 AXEL X on chip code It uses the MB8AA3020 AXEL X evaluation board as an example for a more detail description of the MB8AA3020 AXEL X evaluation board please refer to AXEL X Evaluation Board Hardware Manual The generic firmware that is included with the Fujitsu MB8AA3020 AXEL X chip does not assign MAC addresses to the ports or the chip so at the very least the user must assign a MAC address for every port as well as the chip address for the 10GBE switch to function properly In addition to this the user must decide whether to use fixed or dynamic gain before compiling the firmware Before we begin our example we must first understand how the byte structure is organized in the assembly files as well as understand the various micro commands Section 2 7 Byte data Organization describes the byte structure organization while Section 2 2 Micro commands describes the micro commands This document contains confidential information w
27. on contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 23 ICB_Post_Core_0 ICB_Post_Core_1 ICB_IRQ_0 append lag configuration skip to the tail of ICB_Post_Core_0 skip skip data_ref ICB_SET_LAG_1 FIRMWARE_HEAP skip skip data_ref END_CODE_HEAP_LAG LF Device Initialization default 12KB Jumbo 2 4 9 Initializing GMII MII Registers The initialization of the MII GMII interface is dependent on the user environment By default the generic firmware version initialization sequence for the GBE interface is based on the AXEL X evaluation board which has two external PHYs connected to the AXEL X s MII GMII ports So by default the generic firmware initializes these two 10 100 GBE ports as GMII and assumes that there is an external PHY connected to these ports While this is appropriate for the AXEL X evaluation board it may not be suitable for all applications Below is an excerpt from the Firmware asm file which shows the initialization of the two Ethernet ports to GMII task24_bp3 Firmware Main Task bp 4 Port Mode data_ref ICB_Post_Core_0 data 0x0000 mode 23 0 21 0 0000 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for man
28. or completeness 13 By default the on chip code is set up to use adaptive gain If you wish to use fix gain comment out the line PCS_CONF axelx_pcs_phy_cfg_adaptive_eval_board txt and uncomment out the fixed gain line PCS_CONF axelx_pcs_phy_cfg_fixed_eval_board txt Below is an example of a Makefile that uses fixed gain AWK gawk PCS_AWK bin ICB_PCS awk PCS_CONF axelx_pcs_phy_cfg_adaptive_eval_board txt PCS_CONF register axelx_pcs_phy_cfg_fixed_eval_board txt Note Please remember to assign the right path to these files Without the correct path the Makefile will not compile properly For adaptive gain you do not need to modify any receiver co efficient since they are determined automatically using the adaptive equalization algorithm this is not the case for fixed gain For fixed gain you need to modify the following the gain co efficient The file that needs to be modified is axelx_pcs_phy_cfg_fixed_eval_board txt and the procedure used to modify the fixed gain parameters can be found in AXEL X MB8AA3020 PCS Register Specification 2 4 3 Mode Value Description The mode value appears across the M1 value as illustrated below PORT 00 Select port number 00 19 mode value M1 5 Select adaptive mode The mode value determines the PCS gain mode of operation and PCS initialization sequence This document contains confidential information which shall not be reproduced or transferred to other d
29. pleteness 27 data_ref ICB_MDIO_MII_0O0 Interface ICB task29_bp3 MDIO Port 2 skip skip skip data_ref ICB MDI MIT O Interface ICB In addition to the PHY initialization the ICB_mdio asm file needs to be modified based on the PHY initialization sequence This is especially true if the MDIO interface is connected to the PHY because the PHY address is embedded in the initialization code Using the AXEL X evaluation board as an example port21 is polling PHY register 1 at PHY address 0 via MDIO 1 and port 23 is polling PHY register 1 at PHY address 0 via MDIO 2 Below is an excerpt of the Firmware asm showing this Life RS a task21_bp3 Task Port 21 be 3 Port IRQ Service Required vector Mode data 0x4003 Use MDIO 0 for polling Mode 3 data 0x0000 Link up Check Threshold I Be ee a a task23_bp3 Task Port 23 bp 3 Port IRQ Service Required vector Mode data 0x8003 Use MDIO 2 for polling Mode 3 data 0x0000 Link up Check Threshold data 0x0801 11 Port Security Violation 0 Link Fault data 0x0000 Rae Resa eae aS a ee eae The mode bit controls how the MII GMII PHY is initializes the values are described in Table 5 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All informatio
30. purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 30 3 0 Micro Engine Description Fujitsu MB8AA3020 10Gbps Ethernet switch uses an integrated 312 5 MHz core 32KB RAM micro engine to decoded micro commands sent to the switch via a user designated Ethernet management interface The micro commands are encapsulated into an Ethernet frame and decoded by the micro engine The use of the micro engine gives users the added flexibility in programming the MB8AA3020 and at the same time reducing software development time 3 1 Task Structure There are a total of 32 individual tasks which are described in Table 6 The memory is context switched so each tasks uses the entire 2KBx64bytes of memory Task Number Thread Name Initial Task State Description 0 19 task_port 10G port monitor 20 task_none Reserved 21 task_port_1g MII GMII port monitor 22 task_none Reserved 23 task_port_1g MII GMII port monitor 24 Firmware Firmware Main 25 task_none Reserved 26 task_i2c 12C Port 1 Handler 27 task_i2c Ready 12C Port 2 Handler 28 task_mdio Ready MDIO Port 1 Handler 29 task_mdio MDIO Port 2 Handler 30 task_test Sleep For Firmware Test Purposes
31. r documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 18 Copy_Config 12 0 CX4 Copy_Config 13 0 CX4 Copy_Config 14 0 CX4 Copy_Config ES 0 CX4 Copy_Config 16 0 CX4 Copy_Config 17 0 CX4 Copy_Config 18 0 CX4 Copy_Config 19 0 CX4 In the example above we can see that 1 2 5 and 6 are pointing to Reference 1 s configuration and the remaining ports are pointing to Reference 0 s configuration 2 4 6 Configuring Transmit Receive Lane and Polarity Swapping By default the transmit polarity is swapped on the AXEL X evaluation board for XAUI ports i e ports 0 3 4 7 19 and transmitter and receiver polarity are swapped for XFI ports i e ports 1 2 5 6 This may not be appropriate for all applications In order to modify the lane or polarity swapping use XL LANE POLARITY SWAP CONTROL REGISTER i e 0xC002 as described in Table 49 of AXEL X MB8AA3020 PCS Register Specification Below is an example where the transmit XAUI ports lanes are swapped but the transmit polarity is not swapped This parameter can be found in both the axelx_pcs_phy_cfg_adaptive_eval_board txt or axelx_pcs_phy_cfg_fixed_eval_boa
32. ransmit Pre emphasis The default transmit pre emphasis parameters can be found in either axelx_pcs_phy_cfg_adaptive_eval_board txt or axelx_pcs_phy_cfg_fixed_eval_board txt depending if the user is using fixed or adaptive gain Below is an excerpt from the axelx_pcs_phy_cfg_adaptive_eval_board txt transmit pre emphasis coefficients for port 0 These transmit pre emphasis coefficients are optimized specifically for the AXEL X evaluation board and may not be appropriate for all applications PORT 00 Select port number 00 19 mode value M1 5 Select adaptive mode step addr data S2 0x0007 0x0001 PCS_CTL2 Select XAUI mode S2 0xc002 ICB_PCS_INDEX_O XL_LANE_SWAP_CTL Set Tx Rx lane polarity swap conditions S2 0xc003 0x86a0 PHY_PLL_MODE_CTL Set PHY PLL mode s2 0Oxc000 Ox00ff PHY_PWR_DOWN_CTL Assert PHY Tx Rx PD signals S2 0x0000 0x8000 PCS_CTL1 Reset PCS S2 0xc010 0x03f0 PHY_TXO_EQ_CFGO Set Tx lane 0 tap 0 with 63 0 S2 Oxc011 ICB_PCS_INDEX_1 PHY_TX0O_EQ_CFG1 Set Tx lane 0O tap 1 with 63 0 S2 0xc012 ICB_PCS_INDEX_2 PHY_TXO_EQ_CFG2 Set Tx lane 0 tap 2 with 51 0 S2 0xc013 ICB_PCS_INDEX_3 PHY_TX0_EQ_CFG3 Set Tx lane 0O tap 3 with 63 1 S2 0xc014 0x0000 PHY_TXO_EQ_CFG4 Set Tx lane 0 tap 4 with 0 0 S2 0Oxc015 0x03f0 PHY_TX1_EQ_CFGO Set Tx lane 1 tap 0 with 63 0 S2 Oxc016 ICB_PCS_INDEX_1 PHY_TX1_EQ_CFG1 Set Tx lane 1 tap 1 with 63 0 S2 0Oxc01
33. rd txt file TABLE ICB_PCS_INDEX_0 XU_LANE_SWAP_CTL 0x0030 Port 00 Ox0f0f Port 01 XFI Ox0f0f Port 02 XFI 0x000f Port 03 Ox000f Port 04 Ox0f0f Port 05 XFI Ox0f0f Port 06 XFI Ox000 Port 07 Ox000f Port 08 Ox000f Port 09 Ox000f Port 10 Ox000 Port 11 Ox000 Port 12 Ox000 Port 13 Ox000f Port 14 Ox000 Port 15 Ox000f Port 16 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 19 0x000f Port 17 0x000f Port 18 0x000f Port 19 ENDTABLE This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 20 2 4 7 Configuring the Port
34. t prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 25 skip Port 21 MII Port 23 GMII data 0x00a0 mode 23 0 21 0 0000 for 23 21 0 GMII 1 MII A similar procedure would apply to the other configurations 2 4 10 External PHY Initialization If external PHY are connected and the user wants to configure these PHYs in MIl mode then the following modification must be performed Below is an excerpt of task28 and task29 responsible for MDIO ports found in the Firmware asm file lO e a E task28_bp3 MDIO Port 1 bp 3 skip data 0x0000 Interface Core ICB skip data_ref ICB_MDIO_GMII_0 Interface ICB of Sa SS a aS task29_bp3 MDIO Port 2 bp 3 skip data 0x0000 Interface Core ICB skip data_ref ICB_MDIO_GMII_0 Interface ICB L Sa a as SS a SS ae Task Dependency Dlr MDIO 1 gt Port 21 MDIO 2 gt Port 23 Le SS SS Se This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice Whi
35. te Link Fault ICB End Figure 3 Initialization Sequence for MII GMII Task This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 38 3 3 2 Initialization Sequence for 10GBE Shown in Figure 4 is the initialization sequence for the 10GBE task This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 39 Execute PCS Stan Restart ICB B I Execute Port ICB fi Execute PCS ICB Wait Timer B Execute PCS Link up ICB Wait Time for GearBox Reset _ Execute Link up ICB gt Ge
36. ther purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 22 data 0x0058 ff Digtriouneion KUPEC Om 1 data_ref ICB_SET_LAG_2 Comment L Distribution Fu is set to 0x0000 ICB_SET_LAG_2 data 0x0100 LAG1 2 6 data 0x0100 data 0x0048 LAG L data_ref ICB_SET_LAG_ 3 ICB_SET_LAG_3 data 0x1100 LAG1 10 11 14 15 data 0x1100 data 0x0044 LAG M data_ref ICB_SET_LAG 4 ICB_SET_LAG_4 data 0x1100 LAG1 18 19 data 0x0000 data 0x0040 LAG H data_ref ICB_SET_LAG_5 ICB_SET_LAG_5 data Oxcc44 activate LAG1 data 0x000c data 0x0054 LAG Control data_ref ICB_SET_LAG 6 ICB_SET_LAG_6 data 0x0000 3 0 LAG1 data 0x0000 data 0x0050 Dsitribution Tuning data_ref ICB_SET_LAG_7 ICB_SET_LAG_7 data 0x0002 LAG1 DA SA data 0x0000 data 0x0058 Dsitribution Function 1 data 0x0000 lt EOL gt END_CODE_HEAP_LAG Fix heap memory This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All informati
37. ufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 24 for 23 21 0 GMII 1 MII The following configuration possibilities apply If the user wishes to modify both ports to MII the following modification needs to be performed Example Both ports converted to MII task24_bp4 data_ref ICB_Port_Core_0 data 0x00a0 Only port 21 converted to MII but port 23 left as GMII the following modification needs to be done Example Port 21 is MII Port 23 is GMIl task24_bp4 data_ref ICB_Port_Core_0 data 0x0020 Port 21 is GMII but port 23 is MII the following modification needs to be done Example Port 21 is GMIl Port 23 is MII task24_bp4 data_ref ICB_Port_Core_0 data 0x0080 Although the above examples show modification to Firmware asm in actuality you want to modify patch asm The modification for both Port 21 and Port 23 to MII mode is shown below a ee Change Port 21 23 to MII mode MDIO Port 1 MII initialization Sequence i a aa a aa task24_bp4 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose withou
38. ument contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness The above list while not exhaustive illustrates the programmability of the MB8AA3020 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 1 2 Acronyms EEPROM Electrically Erasable Read Only Memory ENV Environment GMII Giga bit Media Independent Interface ICB Initialization Code Block I F Interface IRQ Interrupt Request LAN Local Area Network MAT MAC Address Table MII Media Independent Interface MAC Medium Access Control RAM Random Access Memory VLAN Virtual Local Area Network This document contains confidential information which shall not be repr
39. uracy or completeness 34 From MAC Address Table ICB Set Initialization Completion Flag Dn task_ 26 27 Firmware asm task_ 28 29 Firmware asm task_24 Firmware asm task_ 0 19 Firmware asm task_ 21 23 Firmware asm Port Core ICB Port Tasks F I12C MDIO Task API Handler Ready Resolve Task Resolve Task Dependency Dependency Port ICB I F Reg ICB PCS ICB I F ICB I F ICB Done Wait Link Up Set Initialization See Completion Flag Set Initialization Completion Flag il Sleep and wait request This document contains confidential information wnicn sna not be reproduced or transferred to other documents o disclosed to others or used for manufacturing or any othe purpose without prior written permission from FUJITSU Ltd e Ey All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 35 Figure 2 Initialization Sequence This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contain
40. y_cfg_adaptive_eval_board txt or axelx_pcs_phy_cfg_fixed_eval_board txt depending if the user is using fixed or adaptive gain and add the Port Disable to permanently disable the port or Port down to power off the port upon reset Below is an example Copy_Config port reference copy port configuration Port_Disable port permanetly disabled port Power_Down port power off upon reset Copy_Config 0 0 CX4 template Copy_Config 1 1 XFI template Copy_Config 2 1 XFI Copy_Config 3 0 CX4 Copy_Config 4 0 CX4 Port_Disable 5 This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd All information contained in this document is subject to change without notice While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness 16 Port_Disable 6 Copy_Config 7 0 CX4 Copy_Config 8 0 CX4 Copy_Config 9 0 CX4 Copy_Config 0 0 CX4 Copy_Config 1 0 CX4 Copy_Config 2 0 CX4 Copy_Config 3 0 CX4 Copy_Config 4 0 CX4 Copy_Config 5 0 CX4 Copy_Config 6 0 CX4 Copy_Config 7 0 CX4 Power_Down 8 Power_Down 9 In this example port 5 and 6 are permanently disabled and ports 18 and 19 are in power down mode 2 4 5 Configuring T
Download Pdf Manuals
Related Search