Home

MPC5200 Quick Start - Freescale Semiconductor

1. aa ae eee oe i 51_START_ADDR 00000FE00 us Clock z M Enabled JoxFFooo000 JOxFFFFFFFF nabled JoxFFFFOOOO OsFFFFFFFF T Pue Clock tec onli cso nabled foxFFOD0000 OsFFFFFFFF ome OsFFFFOOOO OsFFFFFFFF CS2 START ADDR GOS C51 Enabled OxFE000000 OxFEFFFFFF css Enabled OxFFFFOO00 OxFFFFFFFF Gocce Coo M CS2 J Enabled OxFFFF0000 OxFFFFFFFF CS6 Enabled OxFFFFOO00 OxFFFFFFFF 0S4_START_ADDR O0000FFFF IZ Wait Stage Enable CS7 Enabled OxFFFFOD00 OxFFFFFFFF CS5_START_ADDR 0x0000FFFF See LocalPlus Bus Controller page for further Chip Select settings timing muliplexing mode etc CS6_START_ADDR 0x0000FFFF Note When making a standalone boot from Flash application the CS0 lt pace parameters may need to be used early CS7_START_ADDR 0x0000FFFF during a boot up phase Please see the STARTUP boot cantin BOOT_START_ADD Ox0000FFFF PP PINOUT MPC5200 3 CDM Clock Distribution Module IF CDM Clock amp Power Managem IV CORE MPC5200 G2_LE Core IV IPBI Memory Map LPC LocalPlus Bus Controller I LPC Chip Selects Settings IF LPC Chip Selects Burst amp Deac SIM System Integration Module SDRAM Map Warning detail CSO_STOP_ADDA 0 0000FFFF E ICTL Interrupt Controller f F SDRAM C51 is used but the C51 pin is now disabled in GPIO oxo000FEFF H GPIO General Purpose I O amp F SDRAM Size C
2. amp PSC6 IrDA UART Codec Serial Internal Memory Addressing Up to 13 bit row 11 bit col M MDQSODriven MDOS2 Driven atl a asec i Ma esece re IDiven Evoopt To Reed Il M MDQS1 Driven MV MDQS3 Driven T 122 12C2 Module SPI SPI Module Periodic Interval Of Refresh Command Read CAS Latency DDR Latency 2 5 7 Write Latency DDR Latency 3 x B47 CAN msCAN Modules Burst Read To Rd Prehrg Diy DDR Latency 4 7 T MSCAN1 msCAN 1 Module Single Read To Rd wr Prechrg Delay Memory Mode Settings loaded to memory T MSCANZ msCAN 2 Module Single Write To Rd Wt Prechra Delay Mode Register Value 12 bits 0x63 SJ FEC Fast Ethernet Controller DDR Extended Mode Register 12bits 0x2 7 FEC FIFO Control Active To Read Write Delay T BDLC Byte Data Link Controler 31 7 ATA ATA Drive Controller T PCI PCI Local Bus Controller Refresh To Active Delay EH SDMA BestComm Module Burst Write To Rd wr Prechrg Delay T SDMA BestComm Task Priorities Precharge To Active Delay alll alle ESDRAM SDR DDR Memo trol Burst Read To Rd wr Prechrg Delay XLARB XL Bus Arbiter B44 STARTUP Quick_Start Startup Cod 7 STARTUP Boot Time Options TF Unrecognized definitions I Change memory definition Update sc Figure 42 SDRAM Controller Control Page SDRAM In addition to the direct modification of the memory database file a new memory device can be defined by speci
3. The CORE control page enables setting of key bits in several PowerPC G2 core registers Namely this control page enables configuration of the MPC5200 B Peripheral Base Address register MBAR PowerPC core interrupts in the MSR register Memory Management Unit operation in the MSR and IBAT DBAT registers cache control in the HIDO register and other miscellaneous settings in the HIDO and HID registers test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool lt J PINOUT MPC5200 CDM Clock Distribution Module IPI LPC LocalPlus Bus Controller IA LPC Chip Selects Settings 7 LPC Chip Selects Burst amp Deadcycle Ww SIM System Integration Module 4 ICTL Interrupt Controller JV GPIO General Purpose I O amp Pin Mi JT GPT General Purpose Timers 7 SLT Slice Timers R ead onl a RTC Real Time Clock JA PSC PSC Modules Dwi JA PSC1 UART Codec AC97 Serial Ci TH PSC2 UART Codec AC97 Serial Ci 7 PSC3 UART Codec Serial Controlle TT PSC4 UART Serial Controller JT PSCS UART Serial Controller 7 PSC6 IrDA UART Codec Serial Co I2C I2C Modules T 12C1 12C1 Module T 12C2 12C2 Module T SPI SPI Module JE CAN msCAN Modules JO MSCANI msCAN 1 Module MSCAN2 msCAN 2 Module 7 FEC Fast Ethernet Controller FEC FIFO Control 7 BDLC Byte Data Link Controler 31850 f Read write a ATA ATA Drive Controller PCI PCI Local Bus Controller x SDMA Be
4. Tl Debug Interrupt Enable Use BestComm API calls to start stop tasks with or without generating interrupts 7 BDLC Byte Data Link Controler 31 7 ATA ATA Drive Controller 7 PCI PCI Local Bus Controller 8 MESDMA BestComm Module 7 SDMA BestComm Task Priorities JV SDRAM SDR DDR Memory Controll JV XLARB XL Bus Arbiter BM STARTUP Quick_Start Startup Cod T STARTUP Boot Time Options I Unrecognized definitions If a custom DMA functionality is needed use the BestComm Graphical Configuration Tool to configure DMA tasks and to build the BestComm microcode image The tool does not need to be used when using one of the standard pre built RTOS images Run BestComm GUI Tool for Current Project For more information about BestComm GUI contact gckstart freescale com r Interrupt Controller Settings Peripheral Source amp mask Source Priority D BestComm V mask 0 LO_int 7 Handler Function Using Floats F Using FP Figure 41 BestComm Control Page SDMA MPC5200 Quick Start Rev 3 Freescale Semiconductor Graphical Configuration Tool 6 4 19 SDRAM Memory Controller SDRAM The SDRAM controller must be configured properly in the MPC5200 system to enable RAM operation which is crucial for vast majority of applications As it is not always easy to determine the proper SDRAM controller settings for a given memory device the GCT contains a database of valid settings for the most
5. XL BUS clock setting XLB Clock 132 MHz Fractional Divider Clock OFF MHz _XTAL_IN x16 IDA PSC6 clock sourced from Fractional Divider 7 Bypass System PLL TEST_SEL_O hw pir DA PSCE clock sourced from external pin PSC6_3 I Crystal Oscilator Disabled USB clock sourced from Fractional Divider USB clock sourced from extemal pin PSC6_3 r Core Clock Reset Configuration 7 External USB clock synchronized to intemal clock CORE Clock Setting CORE Cik 62 MHz PSC Clocks MCLK MIP BUS Clock Domain MCLK F SYSTEM MCLK IP BUS Clock Setting IPB Clock Enable divider lt 1 512 gt Frequency XL BUS clock 7 2 X 5 MHz M psc fe a or vie T Psc2 fie 4 oF MHz m PCI Clock Domain 1 z PCI BUS Clock Setting PCI Clock T Pscs 16 F mke XLBUS clock 4 x 33 MHz C Pscs fic Orr MHz Figure 17 Graphical Configuration Tool CDM Control Page MPC5200 Quick Start Rev 3 NUM 4 24 Freescale Semiconductor Graphical Configuration Tool then be modified either by clicking on the jumper check boxes directly or clicking on the graphical controls representing a hardware configuration XLB Clock Core Clock etc SYS_XTAL_IN x 16 F_SYSTEM 4 XL BUS x 3 5 x 2 Figure 18 Enabling Hardware Configuration Items MPC5200 Quick Start Rev 3 Freescale Semiconductor 25 eee Graphical Configuration Tool 6 4 2 PowerPC Core CORE
6. File Edit View Module Help TEE est x we Target MPC5200B XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz TO LPC Chip Selects Burst amp Deadc a SJA SIM System Integration Module 8 4 ICTL Interrupt Controller 7 ICTL Critical amp Main Sources T ICTL Peripheral Sources IV GPIO General Purpose I O amp Pir 87 GPT General Purpose Timers I GPTO General Purpose Timer I GPT1 General Purpose Timer I GPT2 General Purpose Timer I GPT3 General Purpose Timer I GPT4 General Purpose Timer I GPTS General Purpose Timer IT GPT6 General Purpose Timer I GPT General Purpose Timer 47 SLT Slice Timers I RTC Real Time Clock BY PSC PSC Modules BIV PSC1 UART Codec AC97 Serie EJ PSC2 UART Codec AC97 Serie EJT PSC3 UART Codec Serial Contr EJT PSC4 UART Serial Controller J PSCS5 UART Serial Controller JT PSC6 IrDA UART Codec Serial T2C 12C Modules m General Settings Timer Mode PWM Mode 7 Prescaler lt 1 65536 gt 33000 IPB clocks Increment Frequency 2 kHz Count lt 1 65535 gt 1000 prese clocks PWM Period 500 ms Frequency 2 Hz I CPU Mode Counter Enable T Interrupt Enable Stop Continuous Flag n a operation always continuous nalo peration always continuous m Pin Control GPIO Mode Type eric Input z I Open Drain when Output High GPIO LOC PWM Mo
7. MPC5200 Quick Start Rev 3 Freescale Semiconductor 55 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com AN2757 Rev 3 06 2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright lic
8. Introduction 1 Introduction This document describes the MPC5200 Quick Start tool version 0 9 at the time of its release Version 0 9 brings support for a new MPC5200B processor while maintaining a fully backward compatible support for the original MPC5200 In this documentation MPC5200 B refers to both MPC5200 and MPC5200B devices 1 1 Features The MPC5200 Quick Start is composed of the following components e Framework for creating MPC5200 and MPC5200B non operating system applications CodeWarrior project stationery project templates Startup code enabling boot from flash standalone operation of Lite5200 and Lite5200B Linker command files for different targets debugging standalone etc Interrupt dispatcher with the support of GCT e Graphical Configuration Tool GCT An easy to use Windows based application All MPC5200 B modules supported except USB A graphical representation of all control bits and bit fields of peripheral modules Generates constants to be directly written to the processor control registers e MPC5200 B peripheral modules initialization code Applies GCT created configuration to the MPC5200 peripheral registers Optionally initializes the MPC5200 device before the main procedure is entered e Compatible with original Lite5200 board support package BSP sources included in the MPC5200 Quick Start BSP register space header files reused in MPC5200 Quick Start 1 2 Sugges
9. O Table of Contents ae ae E E T E E E E ENT 2 1 1 Feats rreo diredi dee roir kaain dade as 2 1 2 Suggested Reading 2 ites fe eile Sewer ar arte See arte ar er arin ea a erect arte errr 3 2 1 Configuring CodeWarrior IDE 3 Your First Hello World Application 4 MPC5200 Quick Start Projects 6 4 1 Project Stationery and Templates 6 42 Project Targets 2005sd0ee ees prites 7 4 3 Making the Application Standalone 8 Application Framework 20 0 5 12 5 1 Application Configuration Files 12 5 2 System Configuration Files 13 5 8 Startup Code 20cisceceeadseee ances 16 5 4 Interrupt Dispatcher 16 55 BSP Source Code i202 2c0 steed mintii 17 50 DMA FISS icii petidine eetehi 17 5 7 MPC5200_Quick_Start Source Code 17 5 8 ThemanGFile icii0idiedoadenaaens 18 Graphical Configuration Tool 19 6 1 Integration into CodeWarrior IDE 19 6 2 GCT User Interface 20 6 3 MPC5200 B Pinout Page 23 6 4 MPC5200 B Peripheral Modules 24 6 5 Side Bar Views 205020254080 40hehn0 54 50 Module Initialization Code 51 Sample Applications 53 MIP GS200 BOP resimi katt kiai i i 54 CONCIUSION lt 2ccocdcadicsdasscantovda nines 55 ROVISION PISTON rores anko catia e mikinoni 55 4 freescale semiconductor
10. OxFFFFFFFF C51 V Enabled OFE000000 OxFEFFFFFF css Enabled OxFFFF0000 OxFFFFFFFF cS2 J Enabled OxFFFFOO00 OxFFFFFFFF CSB Enabled OxFFFFO0000 OxFFFFFFFF IV Wait Stage Enable cs7 J Enabled OsFFFFOD00 JOXFFFFFFFF See LocalPlus Bus Controller page for further Chip Select settings timing muliplexing mode etc Note When making a standalone boot from Flash application the CS0 space parameters may need to be used early during a boot up phase Please see the STARTUP boot configuration for more details 7 PINOUT MPcs200 BV CDM Clock Distribution Module I COM Clock amp Power Manageme IV CORE MPC5200 G2_LE Core SJF LPC LocalPlus Bus Controller IV LPC Chip Selects Settings TO LPC Chip Selects Burst amp Deadc 8 SIM System Integration Module EJS ICTL Interrupt Controller p SDRAM Map SDRAM Size EJM GPIO General Purpose I O amp Pir fo zme z In most of the cases SDRAM CS0 space should start at B 7 GPT General Purpose Timers SDRAM CSO Start Addr 0x0 128 MB Ss 000000000 in order to run the application from RAM 17 SLT Slice Timers I RTC Real Time Clock SJA PSC PSC Modules SDRAM CS1 Start Addr foxe000000 ize MB 7 SDRAM C51 is now disabled in GPIO module See SDRAM Controller page for further SDRAM settings Nm 4 Figure 20 Memory Map Control Page IPBI Another useful GCT feature can also be demonstrated on the IPBI pag
11. PSC6 Mclock Enabled Divider 16 Clock 33 000 MHz t define CDM_PORCFG_READ_ONLY 0x00000C28 define CDM_IPB_CLK_SEL_INIT 0x01 define CDM_PCI_CLK_SEL_INIT 0x02 define CDM_EXT_48MHZ_EN_INIT 0x01 define CDM_FD_ENABLE_INIT 0x01 define CDM_FD_COUNTERS_INIT 0x0010 define CDM_OSC_DISABLE_INIT 0x00 define CDM_MCLKEN_DIV_PSC1_INIT 0x000F define CDM_MCLKEN_DIV_PSC2_INIT Ox800F define CDM_MCLKEN_DIV_PSC3_INIT 0x8013 define CDM_MCLKEN_DIV_PSC6_INIT Ox800F i Figure 14 Example of GCT Saved Configuration 6 2 2 GCT Options The File Options menu in the GCT opens the Configuration Tool Options dialog with a few settings controlling the appconfig h file output GCT Options IV Generate detailed comments Preserve user comments Current Project Options IV Generate all register values even if same as reset value Cancel IV Set as default Figure 15 GCT Options MPC5200 Quick Start Rev 3 Freescale Semiconductor 21 Graphical Configuration Tool e Generate detailed comments Enables saving of the human readable commentary describing the configuration of each module An example of the comments generated for the CDM module is on the Figure 14 above e Preserve user comments When checked this check in box assures that user comments placed after the individual macro values are not lost when generating the appconfig h file This option is rarely used as there is typically n
12. System Integration Module lt S17 ICTL Interrupt Controller E 3 PSC3 V mask l 0 LO_int Ba I Using FP C ICTL Critical amp Main Sources 4 PSCE IV mask 10 HI_int ss I Using FP EEICT Peripheral Sources 4 GPIO General Purpose I O amp Pir 5 FEC IV mask 0 LO_int T Using FP BHI GPT General Purpose Timers aU M mask otom fT Using FP 2 TATA mo Pa f T laina CO zl NUM 4 Figure 26 Peripheral Interrupt Controller Control Page ICTL MPC5200 Quick Start Rev 3 32 Freescale Semiconductor Graphical Configuration Tool 6 4 7 General Purpose I O SIM GPIO A configuration of a General Purpose I O is spread over seven control pages eight on MPC5200B All GPIO control registers are assigned to the main GPIO control page only so only the root GPIO item in the MPC5200 peripheral tree view contains the appconfig h output check box see Section 6 2 1 GCT Input Output File appconfig h The rest of GPIO pages are display only and their graphical controls are linked to the parent item s control registers This is why the check boxes at those pages are disabled and the pages cannot be selectively excluded or included in the appconfig h output test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool fF PINOUT MPC5200 CDM Clock Distribution Module 7 CDM Clock amp Power Manageme CORE MPC5200 G2_LE Core IPBI Memory Map LPC Loc
13. Application Framework Go back to the Program Verify page in the Flash Programmer and specify a path to the s record file to be programmed runram_bl mot for the Standalone BL target and press the Program button If the BDM interface is properly connected and the evaluation board is powered on the Flash Programmer Status line should display the progress of the operation The Show Log button can be used to display a detailed report of a Flash programming operation When the B H L jumper switch is set to the boot low option on the Lite5200 board the Standalone BL application is ready for booting from the Flash memory 5 Application Framework This section describes the content and key parts of each MPC5200 Quick _Start based project In the CodeWarrior project tree window a project can be seen logically divided into a tree like structure of virtual folders and project files Figure 10 The following subsections will describe each project item in detail hello_world mcp Lx Standalone BL x ia N4 B 5 B Files Link Order Targets g Fie Code Daa EE Framework 152K 26K e mA a Application Config 0 Oe a M appcontig h 0 Oe a M configure h 0 Oe a aE System Config 3K 645 e e xf M ppc_eabi_init c 156 0e ex M vectors asm 0 0 x M startup c 476 0s ex M board c 252 0 gt x E interrupt c 2284 645 e em M appconfig c 92 0 gt x H Linker Files 0 0 a G Prefix Files 0 D a 9 Lib 149K 25K o a mE BSP SK 75
14. C C Language Target Processor 5200 z Target OS BareBoad C C Warnings EPPC Assembler IV Use Target Initialization File Code Generation iProjectiSystemConfig intremcfg SS Browse Global Optimizations Project SystemConfig init_ram cfg EPPC Processor IV Use Memory Configuration File EPPC Disassembler Linker Project SystemConfig mmap_ram mem Browse EPPC Linker Editor Program Download Options Custom Keywords Debugger t Analyzer Connectio Executable Executable J Other Executables Constant Data Constant Data J Debugger Settings Initialized Data Initialized Data Remote Debugging Unitialized Data Unitialized Data J Debugger PIC Setti EPPC Debugger Initial Launch Successive Runs J Verify Memory Writes Factory Settings Import Panel Export Panel OK Cancel Apply Figure 12 Debugger Settings MPC5200 Quick Start Rev 3 Freescale Semiconductor 15 Application Framework 5 3 Startup Code Startup code is a key part of each MPC5200_Quick_ Start project It is implemented in the source files located in the SystemConfig sub directory of the project folder on a hard disk e startup c Contains the start global entry point The _ start function is relocatable which means it can be run from any location and its purpose is to call several other subroutines to initialize the PowerPC Core registers initialize board and memory initi
15. IV GPIO General Purpose I O amp Pir 7 GPT General Purpose Timers BY SLT Slice Timers ESL imer 0 T SLT1 Slice Timer 1 T RTC Real Time Clock AJA PSC PSC Modules v 4 gt General Settings Terminal count lt 256 16777215 gt 16777215 IPB clocks Roll Over Time 254 20022 ms Frequency 2 33391 Hz I Timer Enable T Interrupt Enable Run Wait Flag When terminal count is reached wait until status is cleared before resume Run continuously reset to 0 when terminal count reached r Interrupt Controller Settings Critical Interrupt Source Handler Function Using Floats I Using FP Source Priority fo lo 7 1 Slice Timer 0 Source NUM 4 Figure 29 Slice Timer Control Page SLT 6 4 10 Real Time Clock Module SIM RTC There is one Real Time Clock RTC module on the MPC5200 B The configuration page enables complete RTC configuration specifying post reset initial timer value as well as assigning the RTC interrupt service routines test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool Eile Edit View Module Help ve a E Z T n r General Settings 24 Hour Format 12 Hour Format with AM PM bit r Load New Time Date at Startup T Load New Time during Initialization Target MPC52008 XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000
16. Module Initialization Code MPC5200 Quick Start Rev 3 Freescale Semiconductor 49 Graphical Configuration Tool 6 5 Side Bar Views 6 5 1 Register Values View Any time when using the GCT a Register View toolbar like window can be shown to display the immediate register values as they are to be written to the appconfig h file For each module all the registers bound to the graphical controls on the page are displayed When a module configuration is modified all affected registers are red highlighted in the Register View see Figure 47 below There is also a possibility to modify the register values directly in the Register View window press Enter to accept a new value causing the graphical controls to be redrawn accordingly however there are often other run time bits in the control registers which are not supposed to be set during an initialization Modifying the register values without paying high attention to each individual bit or bit field of the register may cause the module settings to be invalid even if the configuration looks good in the GCT The Register View bar can be activated or deactivated by a menu View Register Summary test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help TUBE est m Cs gt Target MPC5200B r General Settings r Input Capture Mode XL Bus Clock 132 000 MHz Timer Mode PWM Mode bd Input Capture Type OCPW
17. NUM 4 MPC5200 Quick Start Rev 3 Freescale Semiconductor 43 Graphical Configuration Tool 6 4 17 PCI Local Bus Controller PCI There is a PCI Local Bus Interface bridge on the MPC5200 B The GCT Control Page can be used to configure the standard PCI Configuration Space of the MPC5200 B accessible by other devices on the PCI bus Also the page contains the XLB to PCI memory mapping windows and other parameters used when MPC5200 B accesses the PCI bus as an initiator test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool av GPIO General Purpose I O amp Pi PSC1 Pins AC97_1 U PSC2 Pins CAN1 2 A PSC3 Pins USB2 SPI USB1 Pins USB1 UAR PSC6 Pins IrDA UAR Ethernet Pins Eth US JS GPIO I2C Pins GPT General Purpose Timers SLT Slice Timers I SLTO Slice Timer 0 O SLT1 Slice Timer 1 TF RTC Real Time Clock JA PSC PSC Modules Psc1 O O PSC2 PSC3 O 0O 7 Psc4 7 Pscs IrDA UART Codec Serial I2C I2C Modules UART Codec AC97 Serie UART Codec AC97 Serie UART Codec Serial Conti UART Serial Controller UART Serial Controller T 12C1 121 Module T 12C2 12C2 Module 7 SPI SPI Module CAN msCAN Modules MSCANI1 msCAN 1 Module MSCAN2 msCAN 2 Module 7 FEC Fast Ethernet Controller 7 FEC FIFO Control BDLC Byte Data Link Controler 31 AT ATA Drive Controller 7 SDMA BestComm Task Pri
18. The Linker Command File syntax used in CodeWarrior is described in the Targeting Embedded PPC User Manual located in the CodeWarrior Help PDF folder Unlike the linkers from other vendors CodeWarrior s Linker Command File syntax does not support the AT or LOAD directives which are typically used when building a compact image suitable for writing into non volatile memory Instead of this feature there is a Generate ROM Image check box in the CodeWarrior linker settings With this option enabled when the linking is finished the linker walks through all initialized memory sections and puts them one after one starting at the specified ROM image address Simultaneously it generates a special array of data structures in which the original and ROM image addresses are specified for each such section In the MPC5200 Quick Start there are two targets that make use of the Generate ROM Image feature of the linker as follows MPC5200 Quick Start Rev 3 Freescale Semiconductor 13 Application Framework e The ROM Image target uses this feature to build an self extracting image which can be run by the firmware code In a startup code of the image the image uses the information from the CodeWarrior Linker generated descriptor array and copies all memory sections from the ROM Image to the destination addresses in RAM e The Standalone BL target uses this feature similarly like the ROM Image except that the SDRAM controller and SDRAM memory ar
19. 0x0 bit 0 must match ID r Baud Rate ET PSC4 UART Serial Controller TT PSCS UART Serial Controller AJ PSC6 IrDA UART Codec Serial SJ 12C 12C Modules 7 12C1 12C1 Module 7 12C2 12C2 Module 7 SPI SPI Module B47 CAN msCAN Modules MEMSCAN1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module Donon n o E SJ FEC Fast Ethernet Controller LJN FEC FIFO Control T BDLC Byte Data Link Controler 11 I ATA ATA Drive Controller T PCI PCI Local Bus Controller SJ SDMA BestComm Module T SDMA BestComm Task Priorities JV SDRAM SDR DDR Memory Controll JV XLARB XL Bus Arbiter a J STARTUP Quick_Start Startup Cod I STARTUP Ront Time oer 4 gt r Interrupt Sources I Wake Up Interrupt J Status Change Interrupt gt Reciver Never x T Overrun Interrupt i T RX Full Interrupt r Interrupt Controller Settings Peripheral Source amp mask Source Priority Handler Function Using Floats 17 CANT IV mask 0 LO_int x I Using FP Figure 37 Controller Area Network Control Page CAN MPC5200 Quick Start Rev 3 Freescale Semiconductor 41 6 4 15 Fast Ethernet Controller FEC The Fast Ethernet Controller of the MPC5200 B implements an interface to the standard 10 100 MB IEEE 802 3 ethernet network For its operation it requires an external ethernet transceiver PHY with which the MPC5200 B communicates either directly AMD industry s
20. 0x00 ae sen ee Timer Disabled CAPTYP 0x00 us Llock z Prescaler lt 1 65536 gt nput Capture p PCI Bus Clock 33 000 MHz Output Compare Bupe Compa Mods CNTRL 0x00 Increment Frequency Hamy MODSEL 0x03 PRESCL 0x03E8 JT PINOUT MPC5200 B CDM Clock Distribution Module CPU Timer oma torera Tes Count lt 1 65535 gt Watchdog Timer Output Compare Pulse Width T COM Clock amp Power Managem PWM Period fim CS 3 CNT 0042 7 CORE MPC5200 G2_LE Core Pulse Width 3 87879 u A 7 IPBI Memory Map Frequency fi kHz WIDTH 00000 aM o LocalPlus Bus Controller E CPIN Mode GounterEneple r PWM Mode PWMOP foo V LPC Chip Selects Settings F T LPC Chip Selects Burst amp Deac Interrupt Enable ON Time lt 0 65535 gt 0 prese clocks B SIM System Integration Module Stop Continuous Flag OFF Time fe prese clocks E M ICTL Interrupt Controller n a operation always continuous EMM GPIO General Purpose I O amp f f n a operation always continuous Pw ON OFF Times Always OFF IR GPIO PSC1 Pins AC97_1 8 GPIO PSC2 Pins CAN1 2 Pin Control Output Polarity Output High during ON Time S GPIO PSC3 Pins USB2 SF C Output High during OFF Time TR GPIO USB1 Pins USB1 U GPIO Mode Type jaro Input z ciel a 8 GPIO PSC6 Pins IrDA Ue 8 GPIO Ethernet Pins Eth 8 GPIO I2C Pins E GPT General Purpose Timers I GPTO General Purpose
21. 12C1 Module I 12C2 12C2 Module 7 SPI SPI Module S47 CAN msCAN Modules 7 MSCANI1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module SR MEFEC Fast Ethernet Controller 7 FEC FIFO Control 7 BDLC Byte Data Link Controler J1i I ATA ATA Drive Controller T PCI PCI Local Bus Controller ST SDMA BestComm Module T SDMA BestComm Task Priorities JV SDRAM SDR DDR Memory Controll JV XLARB XL Bus Arbiter a JV STARTUP Quick_Start Startup Cod I STARTUP Boot Time Options I Unrecognized definitions E e T 4Ha gt FEC Module I Enable FEC module after initialization I Keep Transmitter in Stop Graceful Stop Perform FEC module Reset prior initialization Physical Address hex 00 foo foo foo foo foo Warming The GPIO pin port multiplexer is not configured well for this module Set the ETH Ethemet 18 wire with MII mode in GPIO mux r Ethernet Interface C 7 wire 10 Mb s mode 18 wire 10 100 Mb s Mode RX Full Duplex Mode Receiver operates independently on Tx C RX Half Duplex Mode Receiver disabled when transmitting IV TX Full Duplex mode ignore Carrier Sense and Collision inputs I Flow Control Enable detect amp process Pause frames P Perform Heartbeat check after each transmission I Set Internal Loopback mode IPB Clock Rate must be at least 50 MHz for this duplex mode r Transmit amp Receive Control Maximum Frame Length default 1518 fi 518 T Promiscuous mode receive
22. ATOSI ETNO e mans E Jr on Setup your platform using Graphical Configuration Tool and put your code here printf Hello worldin while 1 asm nop 134 files Line 1 Colt 4 ae Figure 4 Hello World Application in CodeWarrior The Hello World application sends its output to the console which is initially configured as a PSC 1 UART serial line of speed 115200 bps no parity one stop bit How to use the MPC5200 GCT to re configure the PSCI console parameters will be described later in this document Use the null modem cable to interconnect the PSC1 UART port of the evaluation board with the COM port on the host PC Then run the console terminal application such as Hyperterminal for Microsoft Windows and configure the COM port for 115200 N 8 1 and open it MPC5200 Quick Start Rev 3 Freescale Semiconductor 5 MPC5200 Quick Start Projects The jumper switches on the evaluation board should be set in their default factory positions otherwise there is risk that the MPC5200 peripheral clock will run on a frequency different from the one configured for the Hello World application In this case the serial baud rate of the PSC1 interface will not match the COM port settings on the PC side and no output will be displayed on a console window BRAM Debug Settings Target Settings Panels Remote Debugging C C Language r Connection Settings C C Warnings EPPC Assembler Connection WireTAP ccs
23. Bus Clock 33 000 MHz General Settings Current GPIO configuration ATA chip selects 0 1 on CS4 and CS5 pins Length of PCI Arbiter Time Slot dedicated for ATA 128 IPB Clk J Enable Drive Interrupt To Pass To CPU in PIO Modes T RTC Real Time Clock a BAW PSC PSC Modules IV PSC1 UART Codec AC97 Serie I PSC2 UART Codec AC97 Serie I PSC3 UART Codec Serial Contr EJ PSC4 UART Serial Controller J PSCS5 UART Serial Controller I PSC6 IrDA UART Codec Serial SJ I2c 12C Modules T 12C1 12C1 Module T 12C2 12C2 Module T SPI SPI Module B47 CAN msCAN Modules 7 MSCANI1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module 8 7 FEC Fast Ethernet Controller T FEC FIFO Control T BDLC Byte Data Link Controler 31 ATA ATA Drive Controller PCT PCT Local Rus Controller of 4 gt Figure 39 ATA Hard Drive Interface Control Page ATA ATA Bus Timing PIO Mode Timing Detect best PIO Mode modes 0 4 x PIO Timing Number of clocks hold states to be added to all PIO times fo E Multiwrod DMA Timing Detect best MDMA Mode modes 0 2 x MDMA Timing Ultra DMA Timing Detect best UDMA Mode modes 0 2 z UDMA Timing When detecting I Skipdive0 Skip drive 1 Drive Ready timeout 5000 ms Interrupt Controller Settings Peripheral Source amp mask Source Priority Handler Function Using Floats TATA Mv mask 0 LO_int x I Using FP
24. Clock amp Power Management IV CORE MPC5200 G2_LE Core JV IPBI Memory Map a JV LPC LocalPlus Bus Controller MV LPC Chip Selects Settings IO LPC Chip Selects Burst amp Deadcycle SJA SIM System Integration Module 4 ICTL Interrupt Controller HJV GPIO General Purpose I O amp Pin Mi 47 GPT General Purpose Timers 47 SLT Slice Timers IT RTC Real Time Clock AJA PSC PSC Modules EJA PSC1 UART Codec AC97 Serial Ci J PSC2 UART Codec AC97 Serial Ci amp PSC3 UART Codec Serial Controlle EJ PSC4 UART Serial Controller J7 PSCS5 UART Serial Controller SJ PSC6 IrDA UART Codec Serial Co 8 TP 2c 12C Modules T 12C1 12C1 Module IP 12C2 12C2 Module T SPI SPI Module 8 JT CAN msCAN Modules T MSCAN1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module 8 JT FEC Fast Ethernet Controller T FEC FIFO Control T BDLC Byte Data Link Controler 31850 I ATA ATA Drive Controller T PCI PCI Local Bus Controller 8 IT SDMA BestComm Module T SDMA BestComm Task Priorities IV SDRAM SDR DDR Memory Controller JV XLARB XL Bus Arbiter 8 I STARTUP Quick_Start Startup Code I STARTUP Boot Time Options I Unrecognized definitions Done E t m Simple GPIO Disabled C2 4 Simple GPIO Disabled Simple GPIO Disabled ge Simple GPIO Disabled Int WWakeUp GPIO Disabled Simple GPIO Disabled C2 Simple GPIO Disabled Simple GPIO Disabled 6 Simple GPIO Disab
25. Here they are used by the module initialization code to set up the individual peripheral modules As it was already described in Section 5 3 Startup Code the GCT can be also used to select MPC5200 peripheral modules which are to be automatically configured before the code execution hits the application s main function 6 1 Integration into CodeWarrior IDE The most effective use of the GCT is to integrate it into the CodeWarrior IDE and assign a hot key or menu item for invoking it In such a configuration the GCT is automatically opened for the project currently active in the CodeWarrior IDE A detailed description of how to integrate the GCT into CodeWarrior IDE can be found in the todo_CW txt document in the MPC5200 Quick Start installation The procedure is also briefly described below In CodeWarrior select the menu Edit Commands and Key Bindings In the Customize IDE window see Figure 13 select the menu group in which you want to create a new GCT menu item such as Project 1 Click on the New Command button 2 Type MPC5200 Configuration Tool to the Name box 3 Click on Appears in Menus check box and check it 4 Click on button on the right hand side of the Execute edit box and browse for the gct 5200 exe GCT executable Typically you can find the executable file in C Program Files Freescale MPC5200 Quick Start rxX Y config_ tool 5 Click on the button on the right hand side of the Arguments edit box and select the Pro
26. IRO2 Level high Disabled IRO3 Level high Disabled CSO Addr 24 bits Data 1 byte CS1 Addr 24 bits Data 1 byte Disabled CS2 Addr 8 bits Data 1 byte Disabled CS3 Addr 8 bits Data 1 byte Disabled CS4 Addr s Data 1 byte Disabled CS5 Addr 8 bits Data 1 byte Disabled IntWakeUp GPIO Disabled IntWakeUp GPIO Disabled 12 1_10 I2C1 CLK 1202710 12027CLK GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input Package pins are labeled with both the official pin name including the BGA ball identifier and the pin function assigned by the MPC5200 B GPIO port multiplexer See Section 6 4 7 General Purpose I O SIM GPIO Most labels on the page are active hypertext links which when clicked open the appropriate control page in the GCT There are two kinds of hypertext labels as follows e Pin Labels blue Show the pin function currently assigned by the pin multiplexer The hypertext links of these labels activate the GCT page where the pin function can be re defined MPC5200 Quick Start Rev 3 Freescale Semiconductor 23 Graphical Configuration Tool e Mode Labels black list blue head item Each group of these labels display the peripheral modules and their operational modes supported by one pin port multiplexer The multiplexer mode currently selected in the GPIO configuration is highlighted in red A hypertext link of the mode labels activ
27. MHz 7 ICTL Peripheral Sources a GPIO General Purpose I O amp Pir 47 GPT General Purpose Timers S47 SLT Slice Timers I SLTO Slice Timer 0 7 SLT1 Slice Timer 1 MERTC Real Time Clock 8 JF PSC PSC Modules IV PSC1 UART Codec AC97 Serie EJ PSC2 UART Codec AC97 Serie i 7 PSC3 UART Codec Serial Contr I PSC4 UART Serial Controller T PSCS5 UART Serial Controller I PSC6 IrDA UART Codec Serial a JT 12C 12C Modules T 12C1 12C1 Module P 122 12C2 Module T SPI SPI Module S47 CAN msCAN Modules T MSCAN1 msCAN 1 Module of gt Hour lt 0 23 gt Minute Second fo fo 0 m Stopwatch amp Alarm Interrupts T Load amp Run Stopwatch during Initialization j I Load New Date during Initialization Stopwatch lt 0 255 gt min 0 Day lt 1 31 gt Mth lt 1 12 gt Year Weekday Hour lt 0 23 gt Minute I Alarm Enable Alarm Setting r Other Interrupts Master Periodic Enable I Midnight Rollover Periodic Interrupt Enable Minute Rollover Periodic Interrupt Enable I Second Rollover Periodic Interrupt Enable Interrupt Controller Settings Main Interrupt Source amp Mask Source Priority 5 ATC periodic mask O EXT x 6 RTC alarm J mask 0 EXT 7 Handler Function Using Floats I Using FP I Using FP Nm Z Figure 30 Slice Timer Control Page SLT MPC5200 Quick Start Rev 3 Freescale Semicon
28. MPC5200B project using one of the three available project templates Figure 3 When a new project is loaded into the Code Warrior workspace double click the main c file item in the project tree to open the file in the editor window A typical Hello World application code is prepared by default Figure 4 MPC5200 Quick Start Rev 3 Freescale Semiconductor Your First Hello World Application New Project xi Select project stationery E MPC5200 Lite5200 C_Application DMA4_Custom DMA_ImageRtos1 DMA_ImageRtos2 Cancel Figure 3 Quick Start Project Templates By default all the embedded side code of MPC5200_ Quick Start supports the WireTAP CCS BDM common on chip processor COP interface which is also the default interface included with the Lite5200 or Lite5200B evaluation board A different BDM interface can be selected in the project settings window after pressing the Alt F7 key Figure 5 Metrowerks CodeWarrior main c ofi xi AD Eile Edit View Search Project Debug Tools Window Help la x Bose Boe xh OAaMeae SU Ee as b M a f Path D Projects hello_world main c pte mar mo A g a RAM Debug m SRE FILE NAME main c 4 l 5 DESCRIPTION default MPCS200_Quick_Start stationery main c file Files Link Order Targets include qs h v EE Framework ee include lt stdio h gt e CQ BSP F i v m DMA
29. Quick Start projects to maintain compatibility with older code 10 Conclusion The MPC5200 Quick Start development environment can help users become familiar with the powerful and rather complex devices of the MPC5200 family With support for creating non operating system applications the user is capable of writing a fully functional code with a complete low level access to all peripheral modules of the processor Using the GCT the vast majority of processor features can be explored quickly and more effectively than by going through the Users Guide By looking at how the control registers changes in the GCT the user can also better understand the meaning of individual control bits and bit fields as they are described in the Users Guide The integration with and the support of the CodeWarrior IDE significantly reduces the code debug deploy loop as compared with other environments On the other hand it is still a subject of future MPC5200_ Quick Start development to widen the set of supported tools and platforms 11 Revision History Table 6 provides revision history details for this document beginning with Revision 3 Table 6 Revision History Rev No Substantive Change s 3 Added PowerPC trademarking information in first paragraph on page 1 and the back page removed references to Metrowerks now Freescale and added a revision history table to record future changes Minor editorial changes also made
30. Tin IF GPT1 General Purpose Tin I GPT2 General Purpose Tin I GPT3 General Purpose Tin I GPT4 General Purpose Tin T_GPTS General Purnnce a Done Nm 4 Figure 47 Register Summary View I Open Drain when Output High GPIO OC PWM Module pins are now enabled by GPIO pin port multiplexer m Interrupt Controller Settings Main Interrupt Source Source Priority Handler Function Using Floats 3 GPTO Time J mask 0 ExT x T Using FP 6 5 2 Warnings View Similarly as the Registers View described above the Warnings View bar can be shown or hidden any time when working with the GCT Warnings View shows a list of warnings collected from across all the control pages in a GCT project By default the Warnings View displays only the warnings from modules enabled MPC5200 Quick Start Rev 3 50 Freescale Semiconductor eee Module Initialization Code for appconfig h output those with a checkmark sign in the project tree All other warnings can be displayed if required A double click on a warning item in the list activates the control page where the potential conflict exists and a balloon like hint is shown as a notification see Figure 48 below The Warnings View bar can be activated or deactivated by a menu View Warnings Summary test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help ae E e t a Target MPC5200B r Memory Map CSE
31. Word Mode I SLT1 Slice Timer 1 First Bit Starts At Rising Edge Of Frame Sync Only One Data Word Per Frame TT RTC Real Time Clock First Bit Starts One Bit Clock After Frame Rising Edge C More Than One Data Word Per Frame BW PSC PSC Modules Bit Clock Polarity Shift Direction UART Codec ri C Data In On Falling Edge Data Out On Rising Edge MSB First 7 PSC2 UART Codec AC97 Seri Data In On Rising Edge Data Out On Falling Edge LSB First I PSC3 UART Codec Serial Contr amp 7 PSC4 UART Serial Controller Frame Sync Polarity amp 7 PSCS5 UART Serial Controller C Frame Syne Is Active Low EJT PSC6 IrDA UART Codec Serial Frame Syne Is Active High Sf 12c 12C Modules T 12C1 12C1 Module T 12C2 12C2 Module T SPI SPI Module I IPC Interrupt Enable J TxRDY Interrupt T PSC Error Interrupt SJT CAN msCAN Modules I D_CTS High Generates IPC Interrupt Overrun Error Interrupt Any of Break Framing Parity T MSCAN1 msCAN 1 Module I D_DCD High Generates IPC Interrupt D Underrun Error Interrupt Underrun Overrun sources TO MSCAN2 msCAN 2 Module I RxRDY FFULL Interrupt Enable J Delta Break Interrupt UART SIR only SJ FEC Fast Ethernet Controller J Detect End Of Frame Interrupt MIR FIF only LT FEC FIFO Control RADY Generates Interrupt Fac 7 BDLC Byte Data Link Controler 11 C FFULL Generates Interrunt I ac I ATA ATA Drive Controller T PCI PCI Local Bus Controller m Interrupt Co
32. displays the loaded configuration in its main application window The main GCT application window is split into three panes On the left hand side there is a tree like view of MPC5200 B peripherals Tree items are logically grouped into branches each representing a set of peripherals with similar or same functionality The following sections describe each item in the peripheral tree The right hand side of the window displays a configuration page for a peripheral module selected in the tree view Above the tree view on the left hand side there is a brief summary of key system clocks as configured in the current project See Section 6 4 1 Clock Distribution Module CDM for more details about setting system clocks 6 2 1 GCT Input Output File appconfig h The GCT opens and saves the MPC5200 configuration into the project s appconfig h file located in the ApplicationConfig subdirectory of the project folder on a disk A configuration is saved as a set of macro values define in the form of a standard C header file This header file is included by all MPC5200_ Quick Start project files and the values from this file are used to initialize the MPC5200 B control and PowerPC core registers MPC5200 Quick Start Rev 3 20 Freescale Semiconductor Graphical Configuration Tool Most of the items in the tree view do have a check box field Using it the user selects the modules for which the configuration is to be saved in the result
33. no need to use SDRAM memory 5 Flash Programmer olx Flash Programmer Target Configuration Flash Configuration Default Project hello_world mep Program Verify Y jal Erase Blank Check CER MEE St pE Checksum mS Use Custom Settings Target Processor 5200 Connection WieTAP ccs z AY Use Target Initialization Y EMBS EMBSW 1 05 stationerySMPC5200_Quick_Start_Cw MP Browse Target Memory Buffer r Options Target Memory Buffer Address Ox s0008000 IV Enable Logging Target Memory Buffer Size 0x 00004000 I Verify Target Memory Writes Show Log Load Settings Save Settings oros Figure 6 CodeWarrior Flash Programmer Target Configuration 8 Flash Programmer ojx Flash Programmer Flash Device Configuration Target Configuration Flash Configuration Program Verify Flash Memory Base Address Ox FFo00000 Erase Blank Check Checksum Device ization Sector Address Map FFOOOO00 FFOOFFFF a AM2SLVOB5D HAWK FF010000 FFOIFFFF AM29LV081B FF020000 FFO2FFFF AM29LV104BB FF030000 FFOSFFFF AM29LV104BT FF040000 FFO4FFFF AM29LV116BB FF050000 FFOSFFFF AM29LV116BT FF060000 FFOGFFFF AM29LV160BB FFO70000 FFO7FFFF AM29LV160BT FF080000 FFOSFFFF AM29LV200B FF090000 FFOSFFFF AM2SLV200BB FFOAOOOO FFOAFFFF AM29LV200BT FFOBOOOO FFOBFFFF AM29LV200T FFOCOOOO FFOCFFFF AM29LV320D8 FFODOO00 FFODFFFF AM29LV320DT FFOEOOOO FFOEFFFF AM29LV4008 FFOFOOOO FFOFFFFF AM2SLV400B
34. the Standalone BL target can be used to compile a standalone executable image When this image is programmed to the Boot Flash memory starting at Boot Flash address 0 the application is ready for boot low standalone operation that does not require any firmware The startup code takes care of relocating the Flash memory to the end of the address space initializing SDRAM controller and SDRAM DDRAM memory from address 0x00000000 relocating the code and invoking the main function from RAM As both the Lite5200 and Lite5200B come with their firmware as a boot high option by default address OxFFF00000 the application image built with Standalone BL target can co exist with the firmware The user selects the boot low or boot high option using a jumper switch on the evaluation board Table 1 Comparing MPC5200_Quick_Start Targets RAM Debug ROM Image Standalone BL SDRAM Memory Set up by debugger Set up by firmware Set up by application itself Flash Memory Not used Not required can be used _ Used for boot low at by firmware to store the address 0x00000000 Later image relocated to OxFFO0O0000 Code Execution From SDRAM only Starts by jumping to the Starts in Boot Flash Image base address continues in SDRAM continues in SDRAM Executable Name _ ramdebug elf romimage elf runram_bl elf ramdebug mot romimage mot runram_bl mot Entry Point __start offset 0 of the image Boot low 0x00000100 __reset Prefix File Ma
35. the MPC5200_ Quick Start implementation of the Dispatcher and the user is not allowed to specify his own handlers for them On the other hand thanks to the Interrupt Dispatcher being enabled the user is able to specify handler routines for each main and peripheral interrupt source regardless what physical exception vector they are routed to Using the Enable Floating Point Unit check box a support for Floating Point context saving can be enabled in the Interrupt Dispatcher A Floating Point context save can then be selectively enabled for individual peripheral interrupt service routines see Figure 26 below test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help TH Target XL Bus Clock Core Clock IP Bus Clock PCI Bus Clock MPC5200B 132 000 MHz 462 000 MHz 66 000 MHz 33 000 MHz T PINOUT MPC5200 BV CDM Clock Distribution Module I CDM Clock amp Power Manageme IV CORE MPC5200 G2_LE Core V IPBI Memory Map 84 LPC LocalPlus Bus Controller IV LPC Chip Selects Settings TO LPC Chip Selects Burst amp Deadc BM SIM System Integration Module ca ae ICTL Interrupt Controller IV GPIO General Purpose I O amp Pir 7 GPT General Purpose Timers 47 SLT Slice Timers I RTC Real Time Clock EW PSC PSC Modules BIV PSC1 UART Codec 4C97 Serie EJ PSC2 UART Codec AC97 Serie EJ PSC3 UART Codec Serial Contr EJT PSC4 UART Serial Contro
36. the PWM mode of the GPT timer module to control the LED light intensity rtc_demo Demonstrates a use of interrupts on the RTC module spi_demot1 Requires an externally connected MAX5152 DA converter to demonstrate a use of the SPI mode of the PSC2 module The voltage on the four DAC channels can be set using the console commands spi_demo2 Requires an externally connected ST95020 EEPROM device to demonstrate a use of the interrupt driven SPI module operations uart_demo Demonstrates a use of UART mode of two PSC modules 9 MPC5200 BSP MPC5200 Quick Start is built on top of the software support package called Board Support Package BSP distributed with the Lite5200 systems The latest version of the BSP package is included in the Quick Start distribution so there is no need to retrieve and install it separately The full BSP source code is also included in all MPC5200_Quick_ Start project templates so BSP functions are immediately ready to be used in user applications The following table summarizes the features of the BSP and shows the items reused by MPC5200_ Quick Start applications All BSP code is installed in the support bsp sub directory of the MPC5200 Quick Start src folder Table 5 BSP Reuse in MPC5200_Quick_Start BSP Item Quick Start Reuse Description MPC5200 and MPC5200B si Fully reused Quick Start uses its own structure types for mapping of MPC5200 Header Files peripheral registers However in most of th
37. which activate the GCT page where a change is needed or an attention is required Figure 32 shows the PSC control page in Codec 12S The Figure 33 shows the PSC control page in AC97 Mode test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help THE est tk amp a Target MPC5200B Module pins are now enabled by GPIO pin port multiplexer on PSC Operation Mode CODEC 16 bit Data x PSC1 CODEC without MCLK XL Bus Clock 132 000 MHz Core Clock 462 000 MHz CODEC Operation IP Bus Clock 66 000 MHz E e ae SPI CODEC Mode Codec x Channel Made Normal x 7 ICTL Critical amp Main Sources 7 ICTL Peripheral Sources SJV GPIO General Purpose I O amp Pir C Use Extemally Generated BitClk and FrameSyne Signals GPIO PSC1 Pins AC97_1 U Generate BitClk and FrameSync Signals Internally GPIO PSC2 Pins CAN1 2 Ai GPIO P5C3 Pins USB2 SPI Bit Clock Divider lt 2 65536 gt 257 clocks BitClk Freq OFF Source CDM MCLK Clock 7 GPIO USB1 Pins USB1 UAR Frame Sync Divider lt 1 256 gt fi 7 BitClks Frame Freq OFF Source Freg OFF GPIO PSC6 Pins IrDA UAR GPIO Ethernet Pins Eth US Frame Active Width lt 1 256 gt fi bits IV Frame Toggles for Each Data Word True 125 Mode GPIO I2C Pins 7 GPT General Purpose Timers r CODEC Settings Afm SLT Slice Timers are i p I S5LTO Slice Timer 0 Delay of the First Bit of Time Slot 1 Multi
38. with the numeric parameter values test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help Bee eo t ti a Target MPC5200B m CAN Operation XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz I CAN module enable One sample per bit Module pins are now enabled by GPIO pin port T CAN stops in wait mode C Three samples per bit Multiplexer on PSC2 CAN1 2 I WakeUp enable T Loopback mode I WakeUp low pass filter enable Listen only mode BV GPIO General Purpose I O amp Pir a I GPIO PSC1 Pins AC97_1 U I GPIO PSC2 Pins CAN1 2 A IX GPIO PSC3 Pins USB2 SPI I GPIO USB1 Pins USB1 UAR IF GPIO PSC Pins IrDA UAR 8 GPIO Ethernet Pins Eth US I GPIO I2C Pins 7 GPT General Purpose Timers B17 SLT Slice Timers I SLTO Slice Timer 0 Clock source Serial clock ITMHz 7 SLT1 Slice Timer 1 IP Bus clock T RTC Real Time Clock C EXTAL clock Time quantum fgo g0s1 ns i BAW PSC PSC Modules 2 dif PSC1 UART Codec ACO Serid Prescaler 6 Calculate parameters gt SYNC_SEG 1 TSEGI 13 suw fe T PSC2 UART Codec AC97 Seria Baud rate 500 kBaud _ lt Calculate baud rate TSEG2 e I PSC3 UART Codec Serial Contr J Time Stamp counter enable m Acceptance filters 0 i Mode 2 x 32 bit x ID acceptance 0x0 0x0 Mask bit 1 don tcare ID masks 0x0
39. 0 Instruction TLBMissExc Ox1100 DataLoadTLBMissExc 0x1200 Data Store TLBMissExc f 041300 Instr Addr Breakpoint FJ 041400 System Management Int f See also the configuration pages for Main and Peripheral interrupt controllers When Interrupt Dispatcher is enabled you pages Figure 24 Interrupt Controller Control Page ICTL MPC5200 Quick Start Rev 3 mz 30 Freescale Semiconductor Graphical Configuration Tool 6 4 6 2 MMU and Cache Control in Interrupt Dispatcher Since the MPC5200 Quick Start release 0 9 the Interrupt Dispatcher can also be configured to automatically re enable the PowerPC MMU before invoking any peripheral interrupt service routine The reason for implementing such a feature is simple In typical applications the user requires data and instruction caches to be enabled to achieve optimal MPC5200 B performance In most cases though together with enabling the data cache the user has to configure the PowerPC MMU as well and specify what areas of memory are not to be cached For example it would be a disaster for an application to keep accessing MBAR based peripheral register space with a data cache enabled Typically the user assigns one of the DBAT register pair to declare peripheral register space as cache inhibit and guarded memory space I and G bits in WIMG bit field of DBATxL When the PowerPC exception is being processed the MMU is automatically disabled in MSR register whil
40. 0B h MPC5200 Graphical Configuration Tool File Edit View Module Help a Target MPC52008 XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz JT PINOUT MPC5200 SJA CDM Clock Distribution Module 7 CDM Clock amp Power Manageme IV CORE MPC5200 G2_LE Core M IPBI Memory Map SJA LPC LocalPlus Bus Controller M LPC Chip Selects Settings TO LPC Chip Selects Burst amp Deadc BM SIM System Integration Module AJS ICTL Interrupt Controller IV GPIO General Purpose I O amp Pir 7 GPT General Purpose Timers 17 SLT Slice Timers 7 RTC Real Time Clock BW PSC PSC Modules IV PSC1 UART Codec AC97 Serie AJT PSC2 UART Codec 4C97 Seria I PSC3 UART Codec Serial Contr I PSC4 UART Serial Controller J PSCS5 UART Serial Controller EJT PSC6 IrDA UART Codec Serial S amp T 12 12C Modules PP 12 1 12C1 Module PP 12 2 12 2 Module T SPI SPI Module S47 CAN msC4N Modules wit e gt t 4a r Hardware Configuration Switch ID _CFG13 _CFG12 1ST_CFG11 Switch Name Boot in Large Flash Mode Boot in Most Graphics Mode Boot ROM Type Mux ed Boot ROM Size Byte Lane Swap Boot ROM Wait ETH_1 ETH_O ETH_6 ETH_5 ETH_4 ETH_3 must reconfigure switches jupmers on the board Pin CDM Reset Config Register Bit PORRCFG 16 PORRCFG 23 PORRCFG 17 PORRCFG 18 P
41. 6 000 MHz V CORE MMU MSR DBATs IBATs Tl psc2 P psca4 TJ PSc6 PCI Bus Clack 33 000 MHz IV CORE Caches HIDO Tr i2ci M cANi TF spl T lac2 T CAN2 El PSC1 UART Codec AC97 Seia j 2 MPC5200 System Modules J FEC Fast Ethemet Controller MII requires GPIO ready ar lis aelgcmg sa ded IV CDM Clock Distribution Module I BDLC Byte Data Link Controller 11850 E PSC3 UART Codec Serial Cor IV XLARB XLB Bus Arbiter A EJT PSC4 UART Serial Controller IV LPC LocalPlus Controller m7 Miscellanous IV IPBI Memory Mapping except SDRAM I ATA Disk Interface requires GPIO ready 7 PSC5 UART Serial Controller G7 PSC6 IrDA UART Codec Seri J PCI PCI Local Bus Controller m2 PowerPC CORE second chance EM I2C 12C Modules P ICTL Interrupt Controller 7 I2C1 12C1 Module I CORE HID powe T 12C2 12C2 Module I CORE MSR E ii ah J 8 PowerPC CORE third chance gt SPI SPI Module P CORE MMU MSR DBATs IBATs ite bi EMT CAN msCAN Modules CORE Caches HIDO IV CORE HID power management etc except caches T MSCAN1 msCAN 1 Module n 4 IV CORE MSR register except MMU and Interrupts I MSCAN2 msCAN 2 Module r3 BestComm CORE MMU MSR DBATs IBATs E J FEC Fast Ethernet Controller I Beste Mochil I CORE Caches HIDO 7 FEC FIFO Control eurom Moos I CORE Interrupts MSR 7 BDLC Byte Data Link Controler 31 4 SIM Timer Modu TD ATA ATA Drive Controller csi tea
42. 7 Edit Connection Code Generation Global Optimizations EPPC Processor EPPC Disassembler Linker EPPC Linker Editor Custom Keywords Debugger Analyzer Connectio Other Executables Debugger Settings Remote Debugging Debugger PIC Setti EPPC Debugger w Factory Settings Revert Import Panel Export Panel OK Cancel Apply Figure 5 CodeWarrior Remote Debugging Options Selecting BDM Interface The Hello World application can be built by pressing the F7 key in the CodeWarrior IDE The build process should finish with no errors and warnings If everything goes well pressing the F5 key should run the application under the CodeWarrior debugger The evaluation board is first configured over the BDM the SDRAM DDR on Lite5200B memory is automatically enabled and the compiled application executable is downloaded into the operation memory The application is automatically started and an execution is halted at the default breakpoint on the first line of the main function When the F5 key is pressed again the execution resumes and the Hello World output is sent over the serial line and displayed on the console window The following sections describe the MPC5200_Quick Start framework GCT project templates and other details briefly mentioned during running the Hello World application 4 MPC5200 Quick Start Projects This section describes different kinds of CodeWarrior projects tha
43. 8e em 9 DMA RTOS1 21K BK e ex wi os 5K 17K xf M main c 36 l4 exi 138 files 187K 206K y Figure 10 Project Content 5 1 Application Configuration Files The Application Config project folder contains two project header files physically located in the ApplicationConfig sub directory within a project folder on a hard disk The configure h file is included by the MPC5200 BSP source files see Section 9 MPC5200 BSP For the BSP only applications this file can define parameters of the PSC1 console and several macros for the MPC5200 clock frequency calculations This file is superseded by the appconfig h file in the Quick Start applications and is not used at all MPC5200 Quick Start Rev 3 12 Freescale Semiconductor Application Framework The appconfig h file is the main application configuration file for the Quick Start based applications It contains the initialization values of all important control registers for each MPC5200 B peripheral module the user wants to configure The GCT can be used to edit the content of this file graphically See Section 6 Graphical Configuration Tool for more details 5 2 System Configuration Files The System Config project folder contains startup files linker command files prefix files and some CodeWarrior configuration files required by the Quick Start project All these files are physically located in the SystemConfig sub directory within a project folder on a hard di
44. B FF100000 FFIOFFFF Show Log Load Settings Save Settings cea Figure 7 CodeWarrior Flash Programmer Flash Configuration MPC5200 Quick Start Rev 3 10 Freescale Semiconductor MPC5200 Quick Start Projects The second Flash Configuration page of the Flash programmer Figure 7 shows the type and address of the Flash device to be programmed For both the Lite5200 and Lite5200B the proper device is set already by loading the appropriate flash _prog xm1 configuration file A Flash Memory Base Address should be set to OxFF000000 which is the address assigned to the Flash CSO memory space by the script in the Debugger Configuration File Section 5 2 3 Debugger Initialization Files On the third Program Verify page of the Flash Programmer Figure 8 it is possible to specify an s record file with the mot extension to be programmed and to perform the Flash programming itself however before programming the Flash memory it should be first checked to ensure that the Flash sectors to be programmed are erased and blank Go to the fourth Erase Blank Check page of the Flash Programmer select the Flash sectors to be checked and press the Blank Check or Erase button The amount of memory a number of sectors to be checked or erased depends on the size of the s record file to be programmed The s record file can be examined with a text editor The last S3 record gives an information about how long the image is s
45. BestComm microcode images which are rather complicated and tricky For a vast majority of applications the RTOS Image based projects provide enough built in DMA functionality within the pre compiled BestComm images In this case the BestComm GCT is not needed at all BestComm GCT is not part of the MPC5200_Quick_ Start installation test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help SE Eest t a MPC52008 132 000 MHz 462 000 MHz 66 000 MHz 33 000 MHz Target r BestComm Initialization XL Bus Clock Core Clock IP Bus Clock PCI Bus Clock I Initialize BestComm Registers I Initialize BestComm API MV Load BestComm Image SRAM Image Offset 0x0 Registers only Initialization Use BSP s BestComm API to initialize the BestComm ET PSC3 UART Codec Serial Contr I PSC4 UART Serial Controller EJ PSCS5 UART Serial Controller I PSC6 IrDA UART Codec Serial eT 12C 12C Modules J TEA Interrupt Enable TM I2C1 12 1 Module I Execution Unit 3 Interrupt Enable 7 12C2 12C2 Module T SPI SPI Module rm BestComm Task Start Stop Control and Task Interrupts B17 CAN msCAN Modules 7 MSCAN1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module _ SJT FEC Fast Ethernet Controller BestComm Tasks I FEC FIFO Control gt BestComm Interrupts r BestComm Mescellanous Settings J CommBus Pre fetch Disable J Ignore TEA do not halt task
46. C Modules 7 12C1 12C1 Module JO 12C2 12C2 Module 7 SPI SPI Module CAN msCAN Modules JO MSCAN1 msCAN 1 Module JO MSCANZ2 msCAN 2 Module T FEC Fast Ethernet Controller Figure 33 Programmable Serial Controller PSC AC97 Mode test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool lt V GPIO General Purpose I O amp fF GPT General Purpose Timers JF SLT Slice Timers JT RTC Real Time Clock PSC PSC Modules SC1 UART Codec AC97 Sel acd TEEKI JO PSC2 UART Codec AC97 Sel JO PSC3 UART Codec Serial Co JO P5C4 UART Serial Controller JO PSCS UART Serial Controller JO PSC6 IrDA UART Codec Seri JO 12c 12C Modules JO 121 12C1 Module JO 12 2 12C2 Module 7 SPI SPI Module Figure 34 Programmable Serial Controller PSC FIFO Interface MPC5200 Quick Start Rev 3 38 Freescale Semiconductor Graphical Configuration Tool 6 4 12 12C Controller 12C There are two C Bus Controllers on the MPC5200 Like for many other modules the GPIO port multiplexer should be set properly for the I7C module The red message displays a hypertext warning when the port multiplexer is not configured well for the PC operation test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool a 1 TF SLT Slice Timers M RTC Real Time Clock F PSC PSC Modules SCL_Tap 9 SDA_Tap 3 x PSC1 UART Codec AC97 Sel Z PSC1 In
47. C5200_ Quick Start sample applications are based on this template e DMA ImageRtos2 and DMA_ImageRtos3 Same as the one above except that the RTOS2 and RTOS3 images are used This image contains slightly modified set of DMA tasks See BestCommA PIUserGuide pdf in the MPC5200_Quick_ Start installation for more details about RTOS images 4 2 Project Targets Except for the BestComm and DMA functionality all three project templates in the MPC5200 Quick Start Stationery are identical This section describes the project targets available in each project and how to use the targets to debug or to prepare a standalone application A project target is a named configuration of a project including the set of files to compile actual settings of the compiler linker and settings of the debugger environment The following targets are available in each MPC5200 Quick Start project e RAM Debug This target is primarily used for debugging of embedded application over a BDM link The CodeWarrior debugger uses the BDM interface to prepare the evaluation board Clocks SDRAM memory etc before it downloads the application which is executable directly into the RAM for debugging e ROM Image This target can be used for debugging without BDM interface or to deploy applications to firmware based systems The application is compiled into a compact self extracting executable image relocatable which can be loaded and started by the evaluation board firmware
48. CTL Critical amp Main Sources I ICTL Peripheral Sources IV GPIO General Purpose I O amp Pir 7 GPT General Purpose Timers J SLT Slice Timers 7 RTC Real Time Clock EY PSC PSC Modules Main Source amp Mask Handler Function Using Floats 0 Slice Timer1 M mask JiS SMi v fs I Using FP 1 1RQ1 Input Pin mask EXT I Using FP 2 IRQ2 Input Pin mask 0 EXT oS Using FE EXT Using FP EXT Using FP EXT Using FP EXT Using FP EXT Using FP EXT Ss Using FP EXT Using FP EXT Using FP EXT Using FP EXT ss Using FP gt 12 GPT3 Timer J mask aU e CYT w I Isina FE Figure 25 Main Interrupt Controller Control Page ICTL a ofj o 3 IRQ3 Input Pin mask A LO_int Periphs mask 5 RTC periodic mask amp ATC alarm T mask HI PSC1 UART Codec 4C97 Serie Z GPIO Standard mask So co of of 1 PSC2 UART Codec AC97 Serie h EJT PSC3 UART Codec Serial Contr amp GPIO WakeUp T mask E IT PSC4 UART Serial Controller 9 GPTO Timer J mask J PSCS5 UART Serial Controller 3 ee amp IT PSC6 IrDA UART Codec Serial 10 GPT1 Timer mask BJ I2C I2C Modules 11 GPT2 Timer mask T 12C1 I2C1 Module T1297 20 Modula of of ofa o MPC5200 Quick Start Rev 3 Freescale Semiconductor 31 Graphical Configuration Tool 6 4 6 3 Main and Peripheral Interrupt Controllers There are t
49. E CORE_INIT_HID Initializes the bits of HIDO and HID2 core registers not related to the CACHE or MMU operation CORE CORE_INIT_CACHE Initializes the CACHE related bits in the HIDO core register CDM CDM_INIT Initializes the Clock Distribution Module FEC FEC_INIT Initializes the Fast Ethernet Controller module GPIO GPIO_INIT Initializes the SIM GPIO module GPTO GPT7 GPT_INIT Initializes the General Purpose Timer module specified by the module identifier in the ioctl call 12C1 l2C2 I2C_INIT Initializes the 12C Controller specified by the module identifier in the ioctl call ICTL ICTL_INIT Initializes the Interrupt Controller module and the Quick Start Interrupt Dispatcher infrastructure IPBI IPBI_INIT Initializes the Memory Map module LPC LPC_INIT Initializes the LocalPlus Bus module CAN1 CAN2 CAN_INIT Initializes the MSCAN module specified by the module identifier in the ioctl call PCI PCI_INIT Initializes the PCI Local Bus Controller PSC1 PSC6 PSC_INIT Initializes the Programmable Serial Controller module specified by the module identifier in the ioctl call RTC RTC_INIT Initializes the Real Time Clock module SDMA SDMA_INIT Initializes the BestComm module and optionally also loads the DMA microcode image using a BSP calls SDRAM SDRAM_INIT In the most cases the SDRAM is initialized automatically during startup SDRAM_INIT is rarely used MPC5200 Quick Start Rev 3 52 Freescale Semiconductor Sample Applica
50. Freescale Semiconductor Application Note AN2757 Rev 3 06 2006 MPC5200 Quick Start and MPC5200 Graphical Configuration Tool by Michal Hanak Roznov Czech System Center TSPG Freescale Semiconductor This document describes the MPC5200_Quick_ Start environment for creating non operating system applications for the Freescale MPC5200 device The environment also includes an easy to use Graphical Configuration Tool GCT which simplifies definition of the startup configuration for MPC5200 on chip peripherals The MPC5200 microcontroller is based on an e300 CO core using the PowerPC instruction set A current version of the MPC5200 Quick Start tool is primarily designed for and integrated with CodeWarrior development tools There are more tools likely to be supported in the future please see the release_notes txt file n the MPC5200 Quick Start installation for an up to date list of tools supported by the latest release In this document it is assumed the user is already familiar with the target development environment All MPC5200 embedded side code was tested with the CodeWarrior MGT Edition Version 8 1 and the Lite5200 IceCube evaluation board New in the MPC5200_Quick_Start Release 0 9 The new MPC5200B device is now supported in MPC5200_ Quick Start The code was also tested with CodeWarrior MGT Edition Version 8 1 on a Lite5200B evaluation board Freescale Semiconductor Inc 2005 2006 All rights reserved
51. IO General Purpose I O amp Pir m UART Data Mode IF GPIO PSC1 Pins AC97_1 U IR GPIO PSC2 Pins CAN1 2 A Channel Mode Normal 7 Bits Per Character bits x PS GPIO P5C3 Pins USB2 SPI Parity Made Type No Parity v Stop BitLenath 7 1 000 bit 8 GPIO USB1 Pins USB1 UAR 8 GPIO PSC6 Pins IrDA UAR 8 GPIO Ethernet Pins Eth US UART Settings 8 GPIO I2C Pins 7 GPT General Purpose Timers RATS s TsRTS k J SLT Slice Timers Receiver Has No Effect On RTS Transmitter Has No Effect On RTS O SLTO Slice Timer 0 C Receiver Negates RTS If PSC FIFO Is Full C RTS Is Auto Cleared One Bit After Sent Character T SLT1 Slice Timer 1 EOF Tag TxCTS T RTC Real Time Clock Generate EOF Tag when PSC Error is Detected CTS Has No Effect On The Transmitter BW PSC PSC Modules C Do not Generate EOF Tag on Error Transmitter Checks The State Of CTS HI UART Codec AC rig mI PSC2 UART Codec AC97 Serie amp 7 PSC3 UART Codec Serial Contr M PSC Interrupt Settings amp Enable H PSC4 UART Serial Controller I IPC Interrupt Enable J TxRDY Interrupt PSC Error Interrupt I PSCS UART Serial paki M I D_CTS High Generates IPC Interrupt Overrun Error Interrupt Da of praak Framing ti 3 i godec Seria I D_DCD High Generates IPC Interrupt Underrun Error Interrupt Cee Seu ounces 2 T Delta Break Interrupt UART SIR only T 12C1 12 1 Module T ReADY FFULL Interrupt Enable T Detect End Of Fram
52. ORRCFG 19 PORRCFG 20 I Write Only Area TT write Swap Byte TT Read Swap Byte BOOT CS Configuration display only W CS Signal Enabled Multiplexed Operatior V Read Only Area G Long ALE p cik R ACK Input Active MUX Short ALE pul Address Bus Size 24 bit z Data Bus Size byte z Bank Bits MUX ony ID z r Wait States Waits as both RD and WR xP jis fi Read ciks Write ciks Wait fas jas r Chip Select 0 I Read Only Area J Write Only Area I Write Swap Bytes I Read Swap Bytes I CS Signal Enabled D Multiplexed Operation Address Bus Size 24 bits x Short ALE pulse 1 clk Data Bus Size 1 byte 7 Long ALE pulse 2 ciks Bank Bits MUX only I ACK Input Active MUX A oo m Wait States Wait as both RD and WR z xP J4 0 Read ciks Write clks ue ea r Chip Select 1 E Read Only Area test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help Data Bus Size CS Signal Enabled Multiplexed Operation Address Bus Size 24 bits v C Short ALE pulse 1 clk 1 byte m Wait States WaitX as both RD and WR x vD Ta Th z NUM 4 a S Target MPC52008 XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz 7 PINOUT MPC5200 AJY CDM Clock Distribution M
53. R Part MT48LC32M16A2TG 75 sSpeed1 133 MHZ speed2 100 MHZ Micron 256mMb 75 SDR Part MT48LC16M16A2TG 75 speed1 133 MHZ speed2 100 MHZ Micron 64mb 75 SDR Part MT48LC4M16A2TG 75 Speed1 133 MHZ speed2 100 MHz Micron 512mMb 75 DDR 133 MHz conf igl 0x73722930 conf ig2 0x47770000 mode 0x018C control 0x714F0F00 modex 0x0008 Micron 512Mb 75 DDR 100 MHz conf ig1 0x63611730 conf ig2 0x47670000 mode 0x008C control 0x714B0F00 modex 0x0008 Em Figure 44 Example of sdram ini Memory Definition File MPC5200 Quick Start Rev 3 Freescale Semiconductor 47 Graphical Configuration Tool 6 4 20 XLB Bus Arbiter XLARB The XL Bus Arbiter module is completely supported by the GCT test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool lt 4294967295 268435455 268435455 RTC Real Time Clock PSC PSC Modules BJZ PSC1 UART Codec AC97 Seri 7 PSC2 UART Codec AC97 Seri No Parking 7 PSC3 UART Codec Serial Cont 7 PSC4 UART Serial Controller O0 7 PSCS UART Serial Controller 7 PSC6 IrDA UART Codec Serial TP 12 12C Modules PP I2C1 12C1 Module 7 12C2 12C2 Module SPI SPI Module CAN msCAN Modules JT MSCANI msCAN 1 Module MSCAN2 msCAN 2 Module FEC Fast Ethernet Controller FEC FIFO Control DLC Byte Data Link Controler 31 TA ATA Drive Controller CI PCI Local Bus Controller DMA BestComm Module gt SDMA BestComm Task Prioritie
54. S1_STOP_ADDR 0x0000FEFF I gt GPT General Purpose Timers SDRAM CSO Start Addr oo 128 MB z CS2_STOP_ADDR Jox0000FFFF M517 Sice Timers SDRAM CS1 Start Addr Ox8000000 fi2eme z CS3_STOP_ADDA 0x0000FFFF T RTC Real Time Clock z Fi S PSC PSC Modules See SDRAM Controller page for further SDRAM settings CS4_STOP_ADDR Jox0000FFFF V PSC1 UART Codec AC97 Set V _PSC1 Initialization amp FIFO CS5_STOP_ADDR Jox0000FFFF gt 4 CS6_STOP_ADDR Ox0000FFFF xl Module Wamingtet 7 7 IPBI SDRAM CS1 is used but the CS1 pin is now disabled in GPIO module PSC1 The GPIO pin port multiplexer is not configured well for this module Set the PSC1 AC97_1 mode in GPIO mux I Show wamings even for non included modules Figure 48 Warnings View 7 Module Initialization Code The use of MPC5200 Quick Start tool and the GCT brings a standard way of peripheral module initialization Similarly as with Quick Start tools for other Freescale microprocessor platforms MPC500 MPC5500 56F800 E there is a special system call used to access the device s peripheral modules A general format of the Quick Start system call is ioctl MODULE MODULE COMMAND parameter Where the MODULE is an unique identifier of the peripheral module such as PSC1 SPI CAN etc and the MODULE COMMAND together with a parameter specify an action to be performed on a module such as PSC_INIT CAN TRAN
55. SMIT SPI_SET BIT RATE etc Unlike the other Quick Start platforms the MPC5200 Quick Start does not implement any commands except the ones used for the module initialization PSC_ INIT CAN_INIT etc One exception is the CAN MPC5200 Quick Start Rev 3 Freescale Semiconductor 51 Module Initialization Code module for which there is a complete low level driver implemented using the ioct1 system call as well as the sample application demonstrating its use The CAN low level driver is compatible with other MSCAN drivers of other Quick Start platforms for example 56F800 The list of initialization commands to be used with the ioct1 system call can be found in Table 3 below No initialization command requires the parameter value so the NULL value can be used Table 3 Module Initialization Commands Module Identifier Initialization Command Description ATA ATA_INIT Initializes the ATA Controller GPIO_INIT must be called before this command CORE CORE_INIT_MSR Initializes the PowerPC MSR register content except the MMU and Interrupt related bits CORE CORE_INIT_INT Initializes the exceptions related bits in the MSR core register CORE CORE_INIT_MMU Initializes the Memory Management Unit registers such as MMU related bits in the MSR and HID2 core registers IBATx and DBATx core registers COR
56. Source Priority 5 FEC V mask O L0_in x Handler Function T Using FP Using Floats Figure 38 Fast Ethernet Controller Control Page FEC MPC5200 Quick Start Rev 3 42 Freescale Semiconductor Graphical Configuration Tool 6 4 16 ATA Hard Drive Controller ATA The ATA Interface of the MPC5200 enables connection of the standard ATAPI 4 hard drive to the MPC5200 Although the most of the hard drive operations are performed in run time where GCT cannot help there are several timing control registers which need to be configured before accessing the ATA bus GCT automatically calculates timing parameters to be compliant with the ATAPI 4 standard The only input to the calculations is current MPC5200 peripheral bus IPB frequency so there are only few options to be configured on the ATA control page The timing parameters for all PIO MDMA and UDMA modes are saved to the appconfig h file so the user does not need to calculate these values in run time With the support of GCT generated values the MPC5200 Quick Start ATA initialization code is capable to detect the ATA Hard Drives and to initialize automatically the best timing parameters suitable for both drives or single drive connected 4 test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help TEE est tl m Target MPC52008 XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI
57. alPlus Bus Controller V LPC Chip Selects Settings ard JO LPC Chip Selects Burst amp Deadc SIM System Integration Module E E L ICTL Interrupt Controller ICTL Critical amp Main Sources ICTL Peripheral Sources ET GPIO General Purpose j TR SPIO PSC1 Pins AC97_1 U GPIO PSC2 Pins CANI1 2 A 3 E10 Poca Pins USB2 SP EPIO USB1 Pins USB1 UAR GPIO PSC6 Pins IrDA UAR EPIO Ethernet Pins Eth US BPIO 12C Pins j PT General Purpose Timers 7 SLT Slice Timers RTC Real Time Clock Figure 27 General Purpose I O Control Pages GPIO MPC5200 Quick Start Rev 3 Freescale Semiconductor 33 Graphical Configuration Tool 6 4 8 General Purpose Timers SIM GPT There are eight General Purpose Timers in the MPC5200 B The GCT control page enables a complete configuration of all timer features The GCT page is also a good example of a control page displaying mirrored settings from the Interrupt Controller page The Interrupt Controller settings interrupt source mask handler routine and Floating Point context save are displayed at the bottom side of the GPT control page Any changes made in the interrupt controller settings on this page will be automatically displayed also on the Main Interrupt Controller control page and vice versa see Section 6 4 6 Interrupt Controller SIM ICTL test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool
58. alize EABI registers and stack pointer relocate the code from flash ROM Image into a proper RAM destination jump to the RAM location and continue by invoking the main function e board c Contains the reset exception handler which invokes the start startup code It also contains some hardware specific operations like enabling the Flash memory in CSO space at address 0xFF000000 and preparing the SDRAM or DDRAM memory e ppe_eabi_init c Contains functions to initialize or free the C environment if used and tocall pre main and post _main user functions e appconfig c This file contains a default implementation of the pre main and __post_main functions In the MPC5200 Quick Start the pre _main function can be configured by GCT to perform automatic initialization of MPC5200 peripheral modules before the main function is entered 5 4 Interrupt Dispatcher The Interrupt Dispatcher is a thin piece of software layer which handles all exceptions generated by the MPC5200 system saves the EABI context and calls the user supplied exception service routine For the case of external interrupts External Interrupt Critical Interrupt System Management Interrupt the Dispatcher is also capable of decoding an interrupt source which needs to be serviced with highest priority and invoking the user supplied service routine Interrupt service routines can be assigned to each peripheral interrupt source either dynamically in run time o
59. as set pin as output test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help BelEl e9 t laa I Stop Clock Generation In Wait Mode T Interrupt Enable SPI Clock Divisor 2 1 2 1 7 IPB clocks SPI Module Clock 33 MHz SJ 12c 12C Modules T 12C1 12C1 Module B47 CAN msCAN Modules 7 MSCANI1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module SJ FEC Fast Ethernet Controller 7 FEC FIFO Control 7 BDLC Byte Data Link Controler J1i Target MPC5200B r SPI Operation XL Bus Clock 132 000 MHz I SPI Operation Enable Warming The GPIO pin port multiplexer is not configured well for this module Set for example Bee age eee ae SPI SlaveMode SPlinBidiectionalMode the PSC3 SPI mode in GPIO mux IP Bus Clock 66 000 MHz C SPIM Mode IX Slave Select 0 Enabl PCI Bus Clock 33 000 MHz Pedic Ae IF SLT1 Slice Timer 1 a PinName Pin Direction Pin Function Assigned by SPI Module Initial Value if GPIO Output v DRTC pea e con SPI_MISO Output GPIO Input Low C High Brae Pae Pac Modules i SPI_MOSI Output GPIO Input Low C High IV PSC1 UART Codec AC97 Serie A J SPI_SCK Output GPIO Input Low High mY PSC2 UART Codec AC97 Serie SPI SS Booo GPIO Input CL C Hich EIT PSC3 UART Codec Serial Contr P ou 9 ETT PSC4 UART Serial Controller TT PSCS UART Serial Controller r SPI Settings ef PSC6 IrDA UART Codec Serial SPI Clock P
60. ates the control page of applicable peripheral modules 6 4 MPC5200 B Peripheral Modules The use of the GCT is very intuitive and does not require a detailed description The following sections will display screen shots of each MPC5200 or MPC5200B configuration page and will give a brief overview of settings or specific behavior of the graphical controls 6 4 1 Clock Distribution Module CDM test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help a alei e9 t Target MPC5200B XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz gt PINOUT MPC5200 am JV IPBI Memory Map 47 SLT Slice Timers I RTC Real Time Clock BAW PSC PSC Modules Sf 12C 12C Modules T 12C1 12C1 Module I 12C2 12C2 Module T SPI SPI Module SJT CAN msCAN Modules T FEC FIFO Control IT ATA ATA Drive Controller SDMA RestComm Mod The control page of the Clock Distribution Module CDM is displayed above in Figure 17 A subset of CDM settings can be physically set only by installing electrical switches jumpers on the Lite5200 or Lite5200B boards The GCT displays such settings grayed and disabled until the user enables it by clicking on the Enable Hardware Configuration Items check box see Figure 18 below The hardware settings can CDM Clock Distribution Module CDM Clock amp Powe
61. commonly used SDRAM and DDRAM devices The central portion of the SDRAM GCT page displays the SDRAM settings for the selected memory device and a clock speed as retrieved from the database The user is not allowed to modify the settings unless he purposely enables them using the check box at the bottom side of the page When modified the database can be updated with new values A database is saved as a standard INI file format in the sdram ini file located in the sdram sub directory of the GCT application folder An advanced user can use a text editor to modify or to add new entries to the database test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help THE esT kt a Target MPC5200B General Memory Controller Settings r Predefined SDRAM Controller Configuration XL Bus Clock 132 000 MHz fe Enable mamor clock signal Configuration Lite52008 Board Micron 256Mb 75 SDR_7 _New Core Clock 462 000 MHz I Enable automatic refresh IP Bus Clock 66 000 MHz both options above should be set for Part Name MT46V32M16 75 Lite5200B 7 PCI Bus Clock 33 000 MHz normal SDRAM controller operation Mami gt T 16 bit Data Bus Mode cocco ELLE J PSC2 UART Codec AC97 Serie a J PSC3 UART Codec Serial Contr r SDRAM Controller Settings kT PSC4 UART Serial Controller s D eT PSCS UART Serial Controller SDR DDR Memory Type DDR Double Data Rate MDQS Pin Control DDR Only
62. cro TARGET_RAMDEBUG TARGET_ROMIMAGE TARGET_RUNRAM 4 3 Making the Application Standalone Once the application is debugged using the RAM Debug or ROM Image targets it can be rebuilt using the Standalone BL target and programmed into the non volatile Flash memory for a standalone operation The following sections will briefly describe how to use CodeWarrior s Flash Programmer to achieve standalone operation MPC5200 Quick Start Rev 3 8 Freescale Semiconductor MPC5200 Quick Start Projects 4 3 1 MPC5200 B Boot Process After the system reset signal is de asserted the MPC5200 boot process begins at one of two addresses 0x00000100 or OxFFF00100 in the Boot CS space The address selection depends on the state of the B H L board configuration jumper named HI LO on the Lite5200B Evaluation Board e Boot Low Execution starts at address 0x00000100 with an exception prefix set to 0x00000000 MSR IP bit cleared e Boot High Execution starts at address OxFFF00100 with an exception prefix set to OxFFF00000 MSR IP bit set After the Lite5200 B board reset is released the Boot CS space is automatically mapped to the small area of non volatile Flash memory at one of the two addresses above It is a responsibility of the boot code to enable the rest of the Flash space and to remap the Flash space using the CSO signal The CSO signal shares the physical pin with the Boot CS while using a different address mapping re
63. dBug on Lite5200 or U BOOT on Lite5200B The firmware is typically capable of loading the image over an ethernet network using a TFTP protocol and capable of saving the image into the non volatile memory In the case of debugging the image is typically downloaded and run manually using the firmware console commands When making an application standalone the firmware can be configured to run the image automatically after the system boots up When the image is run by jumping to its base address it relocates itself into operational RAM and begins execution of the main program Memory relocation typically means that the firmware s variables and exception vectors are lost and firmware operation can not resume even if the application finishes MPC5200 Quick Start Rev 3 Freescale Semiconductor 7 MPC5200 Quick Start Projects NOTE Since the MPC5200 system is not in the post reset state when running an application of the ROM Image target it is highly recommended to enable the Generate All Register Values setting in the GCT options Otherwise the GCT saves modified non reset value register values only into the appconfig h file As the firmware configures some modules for its own use there is a risk that the modules are only partially re configured by the Quick Start initialization code See Section 6 2 2 GCT Options for more details e Standalone BL After an application is debugged using one of the targets described above
64. detection code for DDRAM memories qs_sdram_dflts h Lite5200 board default values for SDRAM Controller qs_slt h qs_slt c Slice Timer Module support qs_spi h qs_spi c Serial Peripheral Interface support qs_usb h qs_usb c Placeholder for the future USB support implementation USB is not supported by the current version of MPC5200_Quick_Start qs_xlarb h qs_xlarb c XLB Arbiter Module support 5 8 The main c File Each MPC5200_ Quick Start project contains a single source file named main c This file contains typical Hello World application source code MPC5200 Quick Start Rev 3 18 Freescale Semiconductor Graphical Configuration Tool If a user application grows beyond the single source file which is most likely to happen with MPC5200 applications it is the user s responsibility to add other source files to the CodeWarrior project 6 Graphical Configuration Tool This section describes the Graphical Configuration Tool GCT which is included in the MPC5200 Quick Start development environment The GCT is a standard Microsoft Windows based application used to graphically edit read and write the project s appconfig h file All control bits and bit fields of each MPC5200 peripheral module are presented in an easy to understand graphical form The register initialization values edited by graphical controls can be immediately displayed and or written back to the appconfig h file
65. ductor 35 Graphical Configuration Tool 6 4 11 Programmable Serial Controller PSC There are six Programmable Serial Controllers PSC on the MPC5200 B each of which can be configured for different modes of operation UART Codec Codec SPI Codec I2S AC97 IrDA As not all of the PSC modules support all operation modes and the PSC control registers are mostly used in a different way in each mode setting up the PSC manually is a complicated task Thanks to its graphical interface a GCT can save much work when configuring the PSC for the required operation For each PSC mode selected by a drop down list box at the top of the page the content of the control page changes and displays only the graphical controls applicable to the selected mode Figure 31 shows the PSC control page in the UART mode test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help Wl e eo t a 2 Target MPC5200B i Warming The GPIO pin port multiplexer is not configured well PSC Operation Mode fuaRT DCD Ignored w for this module Set for example the PSC1 UART1 without CD XL Bus Clock 132 000 MHz mode in GPIO mux Core Clock 462 000 MHz UART Baud Rate IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz UART Clock Source fiPe 32 7 Th ICTL Critical amp Main Sources a Counter Timer lt 0 65535 gt fi 8 UART Baud Rate 114583 bps CDM IPB is 66 MHz 7 ICTL Peripheral Sources BV GP
66. dule pins are now enabled by GPIO pin port multiplexer m Input Capture Mode Any Transition v Input Capture Type m Output Compare Mode Output Compare Type Output Compare Pulse Width fas sj IPB clocks Pulse Width 3 Output Forced Low Y m PWM Mode ON Time lt 0 65535 gt 50q prese clocks OFF Time soo presc clocks PWM ON OFF Times 250 ms Z 250 ms Output Polarity Output High during ON Time C Output High during OFF Time Interrupt Controller Settings Main Interrupt Source Source Priority 3 GPTO Time mask O EXT x Handler Function Using Floats SE Using FP Figure 28 General Purpose Timer Control Page GPT MPC5200 Quick Start Rev 3 34 Freescale Semiconductor Graphical Configuration Tool 6 4 9 Slice Timers SIM SLT There are two precise Slice Timer modules SLT on the MPC5200 B The configuration page enables complete SLT configuration as well as assigning an SLT interrupt service routine test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help a el t t a 2 Target MPC5200B XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz T LPC Chip Selects Burst amp Deadc a BM SIM System Integration Module BV ICTL Interrupt Controller 7 ICTL Critical amp Main Sources 7 ICTL Peripheral Sources
67. e Interrupt MIR FIR only T 12 2 12C2 Module AsRDY Generates Interrupt M Acs Date Beceved I AGr Uhe 7 SPI SPI Module C FFULL Generates Interrupt AJT CAN msCAN Modules T MSCAN1 msCAN 1 Module T MSCAN2 msCAN 2 Module Data Overrun ACS Comn r Interrupt Controller Settings a FEC Fast Ethernet Controller Peripheral Source amp mask Source Priority Handler Function Using Floats T FEC FIFO Control 1 PSC1 M mask 0 LO_int 7 J Using FP TP BDLC Byte Data Link Controler 11 ame career on 4 gt Figure 31 Programmable Serial Controller PSC UART Mode Figure 31shows another GCT feature not yet described before in this document As the MPC5200 B hardware pins are mostly shared between different peripheral modules there is a pin port multiplexer which is part of the SIM GPIO module The port multiplexer must be configured properly for a given operational mode of each peripheral module that requires any MPC5200 device pins For example the PSC in the UART mode requires the port multiplexer to be configured a different way than when using the PSC in Codec mode A GCT displays a red warning message when there is any inconsistency between operation mode of the peripheral module and the current GPIO port multiplexer settings In most cases MPC5200 Quick Start Rev 3 36 Freescale Semiconductor Graphical Configuration Tool the warning message contains hypertext link or links
68. e cases the Quick Start types are just a typedefs equivalent to the original BSP types The Quick Start header files take care about including the original BSP header files so the re use is fully transparent to the user PowerPC basic types Re implemented Quick Start uses the same basic types as in the BSP uint32 uint16 The ppctypes h header file is duplicated in the Quick Start include folder PSC_UART and console Partially reused The PSC UART interface to the system stdio calls printf puts code gets is reused in Quick Start applications The BSP console initialization code is disabled so the GCT configuration of the PSC1 applies for the console BestComm code and DMA Fully reused The BSP contains the official BestComm support from Freescale RTOS images so it is fully reused in Quick Start The BestComm DMA images are integrated in the Quick Start project templates DMA_ImageRtos1 DMA_ImageRtos2 and DMA_ImageRtos3 MPC5200 Quick Start Rev 3 54 Freescale Semiconductor Conclusion Table 5 BSP Reuse in MPC5200_Quick_Start continued BSP Item Quick Start Reuse Description Exceptions BSP code Not used The Quick Start implements its own exception handling Not available mechanisms in Interrupt Dispatcher Time Sleep RTClock Core Not used The code is not used by the Quick Start However the applicable and Frequency BSP code Available BSP source files are included in
69. e example Like many other MPC5200 peripheral modules there are control registers specifying address values CS Start and Stop addresses in this case Control registers often intentionally do not implement full 32 bits of the address and rather implement for example only 16 upper address bits assuring the 64 kB address alignment On the other hand the GCT always displays the address fields as a full 32 bit value so it is better understood by the user When the address is modified in a way that a new value contains bits not implemented in the peripheral register the user is warned and offered a nearest aligned address value to be used Graphical Configuration Tool AN The value of BOOTCS Start Addr OxFFFFO010 is not valid and should be rounded The nearest acceptable value is OxFFFFOOOO Accept Figure 21 Automatic Address Correction MPC5200 Quick Start Rev 3 Freescale Semiconductor 27 Graphical Configuration Tool 6 4 4 LocalPlus Bus LPC LocalPlus Bus settings are spread over several control pages in the GCT Like the CDM module s control page see Section 6 4 1 Clock Distribution Module CDM the LPC Chip Selects control page displays the settings controlled by a configuration of electrical switches on the MPC5200 board Boot CS settings in this case Similarly as on the CDM page the user must purposely enable modification of hardware controlled configuration items test_projects appconfig_520
70. e initialized before the ROM Image is extracted See Section 4 3 1 MPC5200 B Boot Process for more details Standalone BL Settings Target Settings Panels Target Target Settings Access Paths Build Extras Runtime Settings File Mappings Source Trees EPPC Target E Language Settings C C Language C C Warnings EPPC Assembler E Code Generation Global Optimizations EPPC Processor EPPC Linker r Segment Addresses rm Link Options Link Mode Noma z V Generate DWARF Info V Use Full Path Names IV Generate Link Map I List Closure IV List Unused Objects I List DWARF Objects I Suppress Warming Messages I Heap Address I Stack Address 0x00c02000 v Generate ROM Image Use Linker Command File JV Generate S Record File I Sort Record Max Length 26 EOL Character DOS x r Entry Point _entry_point Import Panel Export Panel OK Cancel RAM Buffer Address Oxff000000 ROM Image Address OxffO00000 Factory Settings Revert EPPC Disassembler E Linker EPPC Linker X Figure 11 Project Linker Settings 5 2 3 Debugger Initialization Files Debugger initialization and configuration files are used by the CodeWarrior whenever it is about to connect to the board over a BDM interface There are two kinds of Debugger files both selected for each project target in the project settings window Figure 12 as follows Target In
71. e the caches remain enabled making the MBAR based area unusable The user has to choose one of the two possible actions before accessing the peripheral registers in the interrupt routine Both of the options are supported natively by Interrupt Dispatcher and GCT e Disable cache By disabling the cache the MBAR space can be safely accessed even without the MMU unit re enabled On the other hand disabling the caches may negatively affect the application performance and prolong the interrupt processing time e Re enable MMU By re enabling the MMU the I and G WIMG control bits assure safe MBAR based area access test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help THE e t 4m Target MPC52008 ICTL Hardware Operation Interrupt Dispatcher XL Bus Clock 132 000 MHz Gate 462 000 MHz Critical Source Handler Function Using Floats IP Bus Clock 66 000 MHz 0 IRQO Input Pin Source fofo x T Using FP PCI Bus Clock 33 000 MHz 1 Slice Timer 0 Source 0 lo z T Using FP E PINOUT MPC5200 2 HI_int Peripheral Source 0 lo z T Using FP BV CDM Clock Distribution Module i IT CDM Clock amp Power Manageme 3 CCS WakeUp Source 0 lo hd I Using FP IV CORE MPC5200 G2_LE Core V IPBI Memory Map 84 LPC LocalPlus Bus Controller IV LPC Chip Selects Settings TO LPC Chip Selects Burst amp Deadc BV SIM System Integration Module AJA ICTL Interrupt Controller IEE I
72. ee Figure 9 In the case of the Hello World application created in Section 4 MPC5200 Quick Start Projects the S record is about 0x9400 bytes long 8 Flash Programmer oix N Flash Programmer IS Program 2 Verity Flash Target Configurat hci I Use Selected File Flash Configuration Program Z Verify ENTER PATH TO THE S RECORD mot FILE HERE Browse File Type Auto Detect 7 Erase Blank Check Checksum Restrict Address Range Apply Address Offset Status Details Program Verity Show Log Load Settings Save Settings Figure 8 CodeWarrior Flash Programmer Program Verify i Lister D Projects hello_world Bin runram_bl mot File Edit Options Help Yo S319FF00926800005C2800005C2800005C2800005C2800005C2859 a S 319FF00927C00005BFC00005C2800005C2800005C2800005C2872 S 319FF00929000005C2800005C0C00005C2800005C2800005C1C59 S319FF0092A42000002D4 94E46002D696E66004 94E4 600696E6603 S319FF0092B8002D4E414E002D6E616E004E414E006E616E00000F S 309FFO0092D00000000095 S 319FF0092D8 0O00000000000000000000000000000004 3 3000000A S 319FF0092EC000000004 3 500000000000000000000000000000D6 319 0093004 3 5000000000000001A56E1FC2F8F3597E37E4 3CB3 s XLIFF009314880075 9c 3C90000000000000E3 70 UVUULOUUFA OxFF009314 0x11 5 OxFF009320 sa Figure 9 Examining the Image Size in the S Record File MPC5200 Quick Start Rev 3 Freescale Semiconductor 11
73. enses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for a
74. everything I Reject Broadcast frames IV Compute CRC during transmitting IV Append CRC to frame r Interrupt Settings T Heartbeat Error Interrupt Tl Late Collision Enable T Babbling Receiver Interrupt Collision Retry Limit Interrupt T Babbling Transmitter Interrupt TX FIFO Underrun Interrupt T Graceful Stop Interrupt TX FIFO Error Interrupt T Transmit Frame Interrupt T AX FIFO Error Interrupt T MII Interrupt Enable m MIB Statistics T Clear MIB counters during initialization IV Keep MIB counters disabled m MII Interface Settings MII Address lt 0 31 gt 10 MII Clk Divider lt 0 63 gt 15 2 IPB Clocks MII Speed 22 MHz T Do not use MII OxFFFF preamble m PHY Transciever Settings IV Setup PHY transciever over MII during initialization J Disable MII Clock after initialization set speed to 0 I Keep PHY in Low power made J Keep PHY isolated from Mil interface J Set PHY Loopback mode Selected values will be Speed 10Mb s 7 used as default when Duplex Mode Ful Dupes Noted or avaebl IV Auto Negotiate Speed and Duplex mode J Advertise 10BASE T capability IV Advertise 10BASE T Full Duplex capability J Advertise 100BASE TX capability IV Advertise 100BASE TX Full Duplex capability IV Wait for Auto Negotioation to complete during init Custom PHY Register Initialization Add Del r Interrupt Controller Settings Peripheral Source amp mask
75. fying the memory timing parameters from the data sheet When the New button is pressed on the SDRAM GCT page the dialog window appears Figure 43 and the user is able to specify a data sheet timing parameter for any clock speed which is to be supported MPC5200 Quick Start Rev 3 46 Freescale Semiconductor Graphical Configuration Tool SDRAM module configuration name New Configuration Datasheet Information SDR Memory Device part name JDEVICEID C DDR Memoy Number of rows 4096 Speed telated Datasheet Information For speed 133 MHz CAS Latency Bo f tHZInsk 54 tAcD Ins 20 tbgssmin tck o wAFCins fee Wains 15S tREF ims fos H SDRAM Registers Config 0xD2322800 Controt Ox505FO000 Config2 Ox84D70000 Mode Ox00CC You will be able to fine tune the register values later Add Delete Cancel Figure 43 SDRAM Memory Configuration The memory configuration created this way can be fine tuned in the GCT SDRAM page and later written to the database file There is no way to rename an existing memory configuration or to add a new clock speed entry to the list of supported speeds once the configuration is created The only way to manage the database is by editing the database sdram ini file i Lister C Program Files Freescale MPC5200_Quick_Start r0 9 tools gct sdram sdram ini Soubor Editace Mo nosti N pov da Micron 512mb 75 SD
76. gister Using the CSO signal even the Flash running code is capable of remapping its own Flash space to the area not overlapping with future RAM space As the last step the SDRAM controller and the RAM memory should be enabled and a code should be relocated from Flash to RAM for execution The startup code of the MPC5200 Quick Start Standalone BL target performs all the steps described above to prepare the evaluation board for running the application By default a firmware is factory programmed at the end of non volatile Flash memory for the boot high mode The Standalone BL target uses boot low mode so that the application may co exist with the firmware code in Flash memory Setting the B H L jumper to the boot low or boot high option selects either an application or a firmware for execution See also the Section 5 3 Startup Code later in this document 4 3 2 CodeWarrior Flash Programmer CodeWarrior Flash Programmer is an application which can be used to program a target Flash memory over the BDM interface In theory the Flash Programmer performs the following tasks e Uses the CodeWarrior debugger initialization file to reset and set up the MPC5200 target over the BDM see Section 5 2 3 Debugger Initialization Files e Uses the BDM interface to download a Flash burning algorithm a driver suitable for the Flash memory selected by the user e Uses the BDM interface to instruct a driver to perform requested operation Flash Blank Chec
77. h Flash Programmer as it does not require SDRAM memory to be valid Flash Programmer uses MPCS5200 built in static RAM for its operation There are two Memory Configuration Files in the MPC5200_Quick_ Start as follows The first one is used by all projects and project targets mmap_ram mem Defines the SDRAM memory area starting at address 0x00000000 Flash memory area starting at address OxFF000000 and two memory areas for MPC5200 memory mapped registers One such area is based at address 0x80000000 which is the reset value of the MBAR peripheral base address register This address is used by the script in the Target Initialization File The second memory mapped registers area is opened for MBAR at 0xF0000000 which is the default operational location of MBAR in Quick Start applications The MBAR base is defined in the appconfig h configuration file and can be set by the GCT For proper operation of the CodeWarrior debugger the mmap_ram mem file should be updated any time the MBAR is assigned different value in GCT See Section 6 4 2 PowerPC Core CORE for more details mmap_fb1 mem Is similar to the mmap_ram mem above with the exception that Flash memory is defined to start at address 0x00000000 and SDRAM memory is not used at all This Memory Configuration file can be used when debugging the Flash based boot low applications directly from the Flash memory Standalone BL Settings BE Target Settings Panels EPPC Debugger Settings
78. ing appconfig h file When the check box is not checked and the module configuration in the GCT differs from module post reset state the user is warned about that the modified configuration will be lost Depending on the GCT settings the configuration saved in the appconfig h file may also contain human readable comments describing the configuration values as they were displayed in the GCT As the MPC5200 Quick Start is built on top of the original MPC5200 BSP the GCT saves the configuration in the 8 16 and 32 bit BSP format of peripheral register values Be aware that this format often does not correspond exactly to the 32 bit register definitions as stated in the MPC5200 Users Guide f Lister EMBSW EMBSW105 config_tool Debug test ApplicationConfig appconfig h File Edit Options Help define APPCFG_MPC5200 define APPCFG_PARTNUM define APPCFG_EXTCLK 33000000L fE CDM Configuration XL BUS clock setting SYS_FVCO 8 Clock 66 000 MHz CORE Clock Setting XL BUS x 3 0 x6 2 Clock 198 000 MHz IP BUS Clock Setting XL BUS clock 2 Clock 33 000 MHz PCI BUS Clock Setting XL BUS clock 4 Clock 16 500 MHz USB clock source CDM Fractional Driver IRDA clock source External clock from GPIO 48 MHz Fractional Divider Enabled Clock 46 933 MHz PSC1 Mclock Disabled Divider 16 Clock OFF MHz PSC2 Mclock Enabled Divider 16 Clock 33 000 MHz PSC3 Mclock Enabled Divider 20 Clock 26 400 MHz
79. itialization amp FIFO PSC2 UART Codec AC97 Sel TT PSC3 UART Codec Serial Co PSC4 UART Serial Controller PSC5 UART Serial Controller fT PSC6 IrDA UART Codec Ser HIO 12C 12C Modules I2C1 12C1 Module CAN msCAN Modules 7 MSCAN1 msCAN 1 Module 7 MSCAN2 msCAN 2 Module T FEC Fast Ethernet Controller i FEC FIFO Control LC Byte Data Link Controler J 4 ATA Drive Controller T PCI Local Bus Controller MA BestComm Module SDMA BestComm Task Prioritie SDRAM SDR DDR Memory Contra XLARB XL Bus Arbiter ARTUP Ouj z Figure 35 I2C Controller Control Page I2C MPC5200 Quick Start Rev 3 Freescale Semiconductor 39 Graphical Configuration Tool 6 4 13 Serial Peripheral Interface SPI In addition to Programmable Serial Controller modules which do support the Serial Peripheral Interface SPI mode there is also one dedicated SPI module on the MPC5200 B The SPI interface uses at most four pins which must be properly configured by both the GPIO port multiplexer and the SPI module itself In addition to the GPIO port settings each pin of the SPI should also be configured for input or output directly in the SPI module The GCT displays all four SPI pins together with their operation assigned by the SPI In the case of any conflict some SPI operation modes require pins to be in certain mode a red warning message is displayed together with a hint of how to fix the problem such
80. itialization File Uses very simple language to initialize the PowerPC core registers and MPC5200 memory mapped control registers Typically its job is to configure Flash access space SDRAM controller and SDRAM memory before the Debugger downloads the application for debugging or before a Flash Programmer begins its operation Memory Configuration File Describes the memory areas of the target system Using a simple language the memory regions can be declared as Read Write Read Only or No Access A CodeWarrior Debugger uses the information from this file when it is about to display the content of memory or memory mapped registers This file is applied also when processing a Target Initialization File so the memory locations accessed by script in the Target Initialization File must also be defined as valid Read Write in the Memory Configuration File being used There are two Target Initialization files available in the MPC5200_Quick_ Start as follows The first one is used by all projects and project targets MPC5200 Quick Start Rev 3 Freescale Semiconductor Application Framework init_ram cfg Initializes Flash memory space to be in range 0OxFF000000 0xFFFFFFFF initializes SDRAM controller for 64MB RAM memory starting at address 0x00000000 256MB DDRAM on Lite5200B and enables the PowerPC Core time base counter TB special purpose register init _flashonly cfg Initializes only the Flash and TB counter only Can be used wit
81. ject File directory item from the popup menu 6 If you want to assign a key binding click on the New Binding button and press chosen key combination such as Ctrl F12 7 Press the Save button and close the dialog box MPC5200 Quick Start Rev 3 Freescale Semiconductor 19 Graphical Configuration Tool m Customize IDE Commands 2 Eg Commands Toolbar Items He File i Edit fl View fl Search E Project Name Configuration Tool MPC5200 IV Appears in Menus Action ks Add Window Execute BS W105 config_tool Debug gct5200_D exe S kit Add Files Arguments projectFileDir IE Create Group Bie 5 J Create Target Key Bindings New Binding Ctrl F12 a r Create Segment O verlay Auto Repeat fo Create Design Create Package Action Prefix Key Timeout 120 I Numeric Keypad Bindings Export Import Export Project as GNU Makefile New Group New Command Delete Factory Settings Revert Save Figure 13 Key Binding for MPC5200 GCT Now you can run the MPC5200 GCT using an assigned key shortcut or by selecting a newly created item in the CodeWarrior menu 6 2 GCT User Interface When starting the GCT the path to the project directory should be passed to it as a command line argument this is done automatically when invoking the GCT from CodeWarrior IDE GCT first locates the ApplicationConfig appconfig h file in the current project reads it and
82. k Sector Erase Memory Write When any data are needed to be passed to the driver it is downloaded by the BDM interface as well All the operations including resetting the device are performed by the Flash Programmer over a BDM interface The target MPC5200 does not need to be in known state prior programming The Flash Content may even be totally invalid while the Flash Programmer can still re program it To make the Standalone BL application really standalone select menu Tools Flash Programmer in the CodeWarrior IDE In the Flash Programmer window Figure 6 first press the Load Settings button and load the flash prog xml file located in the sample applications folder for selected evaluation board MPC5200 Quick Start Rev 3 Freescale Semiconductor 9 errr MPC5200 Quick Start Projects On the Target Configuration page the user specifies the debugger configuration file to be used to initialize the target system As the Flash Programmer was invoked with the CodeWarrior Project loaded and with Standalone BL target active the default Debugger Configuration file for the target will be used see Section 5 2 3 Debugger Initialization Files The Target Memory Buffer Address and Size define the RAM memory area used by the Flash programmer for its operation Note that addresses loaded from the flash_prog xm1 configuration file specify a post reset location of the MPC5200 Static RAM memory which is always valid and there is
83. k OK to finish MPC5200 Quick Start Rev 3 Freescale Semiconductor 3 Your First Hello World Application BIDE Preferences IDE Preference Panels Source Trees General Build Settings Name Path IDE Extras MPC5200_ Quick Start C Program Files Motorola MPC5200_ Quick Start r0 3 s Plugin Settings Shielded Folders Code Completion of Code Formatting Editor Settings Source Tree Information Font amp Tabs Name MPC5200_Quick_Start Source Text Colors Window Settings Global Settings G Debugger pas Path fo Display Settings C Program Files Motorola MPC5200_Quick_Start r0 3 src Choose Remote Connections Add Change Remove v Factory Settings Revert Import Panel Export Panel OK Cancel Apply Figure 1 CodeWarrior IDE Preferences Window 3 Your First Hello World Application After the MPC5200 Quick Start is installed run the CodeWarrior IDE and select menu File New The MPC5200 Quick Start stationery should appear in the list of available project templates New xl Project File Object Empty Project Project name EPPC New Project Wizard hello_world Makefile Importer Wizard MPC5200 Quick Start Cw Stationery Location D Projects hello_world Set CT Add to Project Project Figure 2 CodeWarrior Project Stationery Select the MPC5200 Quick Start stationery and create the MPC5200 or
84. led BG Interrupt GPIO Disabled 28 Interrupt GPIO Disabled 5 Simple GPIO Disabled Simple GPIO Disabled Interrupt GPIO Disabled 4 Int WWakeUp GPIO Disabled Int WakeUp GPIO Disabled B12 Int WakeUp GPIO Disabled Simple GPIO Disabled Simple GPIO Disabled Simple GPIO Disabled zzz 222 Foc cl ec o ri Simple GPIO Disabled H Simple GPIO Disabled F2 Simple GPIO Disabled F3 Interrupt GPIO Disabled Usb1_0 Usb1_1 Usb 12 Usb1_3 Usb1_4 Usb 15 Usb1_6 Usb1_ Usb 178 Usb 173 SORAM DDR Crtrl Bus 30 pins SDRAM DDR Memory Data Bus 32 pins PCI dedicated Signals 17 pins MOST Graphics A0 A15 Large Flash Al6 A25 gegala oeae ele el lel galactose Sas lo She lSlelelelSholSleelSiets s lei cyx ONTO o TO ody Sig 9333 22 5 Bee gode 5566 e S a 5o Bho Sedu cece S6 S h 2oJHe Bi Sde Sass 22 E p z 2gp ght pegan A 388 78 aa MMe one oe E L AC97 1 ETHERNET 18 pins Bh 4 UARTI wth CO lusez Br CODEC1 w o MCLK Bhemet 7 wie EP CODEC1 with MELK Bthemet 7 wire USB2 Eh 8 Bhemet 18 wire w o Mil Bh T0 Bhemet 18 wire with nail 2P PaRa Bthemet 7 wire UART4 31850 Bh 11 ANI CAN2 Bhemet 7 wire 31850 Sh eo 2 UART4 UARTS with CD J1860 BP UART w o CD UARTS with CDSs BhT15 UART2 with CD Bhi CODEC wo CD BhI17 CODEC with CD PSC3 10 pins ve IRO_D GPIO oe IROI use2 freescale IRG UART3 wio CD ped mete hebe
85. ller IT PSCS5 UART Serial Controller AJT PSC6 IrDA UART Codec Serial a 7 12C 12C Modules PP 12 1 12C1 Module PP 12 2 12 2 Module T SPI SPI Module CARLA me CAN Modular of Jeol t teme External Interrupts IRQ pins J Master External Enable all IRQ pins IRQO _ Enable Level sensitive active high IRQ1 Enable Level sensitive active high IRQ2 _ Enable Level sensitive active high gt IRQ J Enable Level sensitive active high gt r Critical Interrupt J Route Critical Interrupt to External Interrupt 0x500 m Quick Start Interrupt Dispatcher IV Enable Interrupt Dispatcher IV Enable Floating Point Unit in Selected Handlers IV Enable Data MMU in Ext Crit SMI Interrupt Handlers IV Enable Instr MMU in Ext Crit SMI Interrupt Handlers J Disable Data Cache in Ext Crit SMI Interrupt Handlers J Disable Instr Cache in Ext Crit SMI Interrupt Handlers Core Interrupt Handlers Core Interrupt Handler Function Ox0200 MachineCheckExc Ox0300 DSI Exception OoOO Ox0400 ISI Exception OoOO 0x0500 External Interrupt a 0x0600 Alignment Exception fs 0 0700 Program Exception Es Ox0800 FPUnavailableExc 0 0900 Decrementer Exception ts 0 04 00 Critical Interrupt j are able to assign interrupt service routines directly on those Core Interrupt Handler Function Ox0C00 System Call Exception Ox0D00 Trace Exception Ox100
86. ller e General Purpose I O Module e General Purpose Timers Slice Timers e Real Time Clock As there are no settings related to the SIM module as a block the control page does not contain anything but links to the control pages of individual sub modules test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool ri PINOUT MPCS200 CDM Clock Distribution Module IT CDM Clock amp Power Manageme JV CORE MPC5200 G2_LE Core M IPBI Memory Map LPC LocalPlus Bus Controller Chip Selects Burst amp Deadc tegration Module terrupt Controller GPIO General Purpose I O amp Pi PT General Purpose Timers SLT Slice Timers Figure 23 System Integration Module Control Page SIM MPC5200 Quick Start Rev 3 Freescale Semiconductor 29 Graphical Configuration Tool 6 4 6 Interrupt Controller SIM ICTL The Interrupt Controller ICTL pages contain graphical controls for both the hardware registers of the ICTL module as well as the controls for the MPC5200_ Quick Start Interrupt Dispatcher configuration Without an Interrupt Dispatcher enabled only the PowerPC G2 exception service routines can be specified in the GCT the vectors asm source file is implemented only see Section 5 4 Interrupt Dispatcher for more details 6 4 6 1 Interrupt Dispatcher Enabling the Interrupt Dispatcher causes three external exception handlers 0x0500 0x0A00 and 0x1400 to be hard routed to
87. n IRO UART with CD CODECS ee CODECS uith MCLK MPC5200B 12 pins cal SPI UART3 wio CD ATACS C82 SPI UART3 with CD T4 SPI CODECS 85 PSC6 IR IrDA 4 pins GPIO Blaster on ir_tx Remote on ir_tx GPIO 2 pins Gpio_wkup_6 SDRAM CS1 Gpio_wkup_ Psc6_3 Blaster and Remote i i2c1_io Ir_usb_clk UARTS IrDA eee i21 k CODECS IrDA ATACS gio USB1 10 pins T GPIO USBI Timers 8 pins Timerd UART4 UARTS GPIO Timer P SPI aE eo ATACS Timers PN BOR c CAN2 Timer4 pal x s 3 5 Timers 7 So e wee Timer6 2 ROR R R 389494358 IJt yg Timer 1 1 haa 6 Pere es sade eol DW 22 Cee Lind Li Li poc wftre o FRISFISIF SESE External Muxed Address Data ATA Bus 7 pins MOST Graphics A16 A22 MOST Graphics A23 Bus 32 pins ATA DO D15 40 43 PCI ADO AD31 MOST Graphics DO D31 Large Flash A0 A15 DO D16 Local Plus Bus 5 pins Figure 16 MPC5200B Pinout Page Output Only GPIO Disabled Output Only GPIO Disabled Output Only GPIO Disabled Output Only GPIO Disabled Output Only GPIO Disabled Output Only GPIO Disabled Output Only GPIO Disabled Output Only GPIO Disabled Simple GPIO Disabled Simple GPIO Disabled Simple GPIO Disabled Simple GPIO Disabled nia Interrupt GPIO Disabled Interrupt GPIO Disabled Interrupt GPIO Disabled Interrupt GPIO Disabled Int WWakeUp GPIO Disabled IROO Level high Disabled IRO1 Level high Disabled
88. n Tool are used to build DMA image and task C API files It is then the user s responsibility to add all generated source files to the CodeWarrior project In all cases the DMA files are located in the dma_image subdirectory of the project folder on the disk 5 7 MPC5200 Quick Start Source Code The last group of files included in all MPC5200_Quick_ Start projects contains the source files implementing the low level initialization code for each MPC5200 peripheral module All files are located in the QS virtual project folder in the CodeWarrior project tree In addition to several system files there is a pair of c and h files for each MPC5200 peripheral module The following table briefly describes the content of the QS source files Table 2 Quick Start Source Files File Name Description qs h This is a master header file for the Quick Start application It includes all other system and MPC5200 header files from the MPC5200_Quick_Start environment qs_version h Defines Quick Start version macros MPC5200 Quick Start Rev 3 Freescale Semiconductor 17 Application Framework Table 2 Quick Start Source Files continued File Name Description qs_system h Defines system macros used in Quick Start applications QSTRACE QSASSERT Also defines a key ioctl system call described in lt Blue gt Section 7 lt Blue Italic gt Module Initialization Code qs_arch h qs_periph h Define
89. nt After the MPC5200 Quick Start is installed before any project or sample application is opened in CodeWarrior the path to the MPC5200 Quick Start source code must be registered in the CodeWarrior development environment Unfortunately this step cannot be automated in the installation process and must be done manually by the user Actions required are specified in detail in the doc todo_CW txt file n the MPC5200_ Quick Start installation and are also briefly described in the following section 2 1 Configuring CodeWarrior IDE The following procedure registers the MPC5200 Quick Start source code path in the CodeWarrior Integrated Development Environment IDE This path is used by all projects created using the MPC5200_ Quick Start Stationery as well as by all sample applications 1 Launch the CodeWarrior IDE and select menu Edit Preferences The IDE Preferences dialog window should appear 2 Select the Source Trees panel on the left hand side IDE Preferences Panels list as displayed in Figure 1 3 Inthe Name box type exactly the string MPC5200 Quick Start Source there is a space before the word Source 4 Inthe Type drop down list select the Absolute Path type 5 Click on the Choose button and locate the src folder in the MPC5200 Quick Start installation directory This is typically the C Program Files Freescale MPC5200 Quick Start rX Y src 6 Click the Add button then the path specified above should be added to the list 7 Clic
90. ntroller Settings ca a an aE E Priorities Peripheral Source amp mask Source Priority Handler Function Using Floats M SDRAM SDR DDR Memory Controll 1 PSC1 V mask 0 LO_int 7 I Using FP JV XLARB XL Bus Arbiter m CODEC Bit Rate PSC Interrupt Settings amp Enable Status Data Recieved amp Jnexpected Rx Slot 97 Status Data Overrun ACS Command Send Ready Figure 32 Programmable Serial Controller PSC Codec Mode Like many other peripheral modules each PSC contains a FIFO to enable buffered data operation and BestComm DMA access There is a sub page under each PSC module page which contains a graphical controls to set up a FIFO parameters Figure 34 On the FIFO page there are also several check boxes not bound directly to any PSC control register These controls enable users to select what actions are performed on the PSC during initialization phase see Section 7 Module Initialization Code MPC5200 Quick Start Rev 3 Freescale Semiconductor 37 Graphical Configuration Tool test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool amp GPIO General Purpose I O amp f GPT General Purpose Timers JF SLT Slice Timers JT RTC Real Time Clock PSC i Modules JO psc2 UART Codec AC97 Ser JO PSC3 UART Codec Serial Co JO PSC4 UART Serial Controller JO PSCS UART Serial Controller JO PSC6 IrDA UART Codec Seri 7 12C 12
91. ny such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The described product is a PowerPC microprocessor core The PowerPC name is a trademark of IBM Corp and is used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 2006 All rights reserved 2 freescale semiconductor e Te Ie gs
92. o need for the user to manually edit any comments in the appconfig h file e Generate all register values Enables saving of all register values of selected peripheral modules into the appconfig h file When this option is not enabled only registers with non reset values such as those modified in the GCT are saved Omitting the reset value registers in the appconfig h file can reduce the size of the module initialization code Those values not defined in the file are not written to the peripheral registers This approach requires that all modules being initialized be in post reset state otherwise the result may be unpredictable NOTE The Generate all register values option should always be set when compiling the application for ROM Image target Such applications are typically invoked by the firmware code which may modify a configuration of peripheral modules so they will not necessarily be in post reset state MPC5200 Quick Start Rev 3 22 Freescale Semiconductor Graphical Configuration Tool 6 3 MPC5200 B Pinout Page When the GCT is started the MPC5200 Pinout page is displayed showing the schematic part like view of the processor test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help CESIS Target MPC52008 XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz E a JV CDM Clock Distribution Module I CDM
93. odule TO COM Clock amp Power Manageme IV CORE MPC5200 G2_LE Core V IPBI Memory Map SJA LPC LocalPlus Bus Controller IV LPC Chip Selects Settings I LPC Chip Selects Burst amp Deade BM SIM System Integration Module E J ICTL Interrupt Controller JV GPIO General Purpose I O amp Pir I _GPT General Purnose Tg gt 4a Note Burst Control only applies in Large Flash or Most Graphics Mode r Burst Control CSO I Burst Write Enable I Burst Read Enable r Deadeycle Control CSO Number of deadeycles to insert after read r Burst Control CS1 I Cache Wrap Capable T Long Burst Capable I Burst Write Enable J Burst Read Enable r Deadcycle Control CS1 Number of deadeycles to insert after read r Burst Control CS2 I Cache Wrap Capable T Long Burst Capable I Burst Write Enable I Burst Read Enable m Deadeycle Control CS2 Number of deadcycles to insert after read r Burst Control CS3 I Cache tran Csnshlo I Ruwot tustite Enable r Deadeycle Control C53 Nuimbher of deadeucles MPC5200 Quick Start Rev 3 Figure 22 LocalPlus Bus Control Pages LPC 28 Freescale Semiconductor Graphical Configuration Tool 6 4 5 System Integration Module SIM The System Integration Module SIM of the MPC5200 B contains several peripheral modules each described and configured on a separate control page in the GCT Interrupt Contro
94. olarity SCK Active High SCK Idles Low C SCK Active Low SCK Idles High SPI Clock Phase C First SCK Edge One Half Cycle into Data Bit First SCK Edge at Begening of the Data Bit Shift Direction MSB First C LSB First 7 ATA ATA Drive Controller r Interrupt Controller Settings Peripheral Source amp mask T PCI PCI Local Bus Controller S17 SDMA BestComm Module T SDMA BestComm Task Priorities Source Priority 13 SPI mod V mask int IV SDRAM SDR DDR Memory Controll ii n B LO_int 14 SPI spif IV mask 0 L0_int 7 Handler Function Using Floats F Using FP F Using FP at XLARB XL Bus Arbiter ae Sonn Sg gt Figure 36 Serial Peripheral Controller Control Page SPI MPC5200 Quick Start Rev 3 NUM 4 40 Freescale Semiconductor Graphical Configuration Tool 6 4 14 CAN Controller MSCAN There are two CAN interfaces MSCAN on the MPC5200 B compatible with a standard Controller Area Network 2A and 2B protocol The GCT can help especially with setting communication speed and bit timing parameters of the CAN interface The user is able to specify a desired communication speed directly in bits per second units Pressing the Calculate Parameters button builds a list of all timing parameter combinations suitable for the requested speed All important time quanta portions and sampling points are also drawn on a time graph which is displayed together
95. on the main c file This file contains detailed comment block describing the application functionality plus all the application source code The table below describes briefly the sample applications included with the current version of the MPC5200 Quick Start Table 4 Sample Applications Sample Pane Application Description ata_demo Demonstrates an automatic detection of ATA hard drive s timing modes PIO MDMA UDMA performed in the initialization code fec_demo Demonstrates a use of the Fast Ethernet Controller module Except FEC module initialization this application also uses two standard DMA tasks to demonstrate basic receive and transmit functions gpt_slt_demo Using a GPT and SLT timer interrupt sources this application demonstrates a use of the Interrupt Dispatcher and interrupt service routines mscan_demo Demonstrates a use of MSCAN module and MPC5200_Quick_Start low level CAN driver A CAN transmit and receive operations can be demonstrated using either a CAN link to PC or using two Lite5200 boards connected together pci_demo1 Demonstrates a use of the PCI Configuration Space read operations Displays an information about devices in the Lite5200 PCI slots including the MPC5200 PCI bridge itself MPC5200 Quick Start Rev 3 Freescale Semiconductor 53 MPC5200 BSP Table 4 Sample Applications Sample Sige Application Description pwm_demo Demonstrates a use of
96. orities SDRAM SDR DDR Memory Controll XLARB XL Bus Arbiter STARTUP Quick_Start Startup Cod i 7 STARTUP Boot Time Options Unrecognized definitions Figure 40 PCI Local Bus Control Page PCI MPC5200 Quick Start Rev 3 44 Freescale Semiconductor Graphical Configuration Tool 6 4 18 BestComm DMA Module SDMA The BestComm DMA module is the only MPC5200 module for which the MPC5200 Quick Start initialization code uses an external embedded side code There is a complete BestComm support in the BSP and BestComm API BAPTI package both the GCT and MPC5200_ Quick Start code re use this implementation The latest BSP code as well as the standard RTOS DMA images are included in the MPC5200 Quick Start distribution so there are no external resources needed to implement DMA operations in Quick Start applications See Section 9 MPC5200 BSP for more details about BSP package The GCT support for the BestComm DMA module is narrowed down to configuration of BestComm control registers and the BSP initialization sequence There are two control pages dedicated to the BestComm module in the GCT One for general BestComm and BAPI initialization Figure 41 and one for selecting individual BestComm task priorities Except other settings the main BestComm control page contains a button to run the BestComm GCT for a current project provided it is based on the DMA Custom template The BestComm GCT can be used to build custom
97. r Manageme V CORE MPC5200 G2_LE Core 84 LPC LocalPlus Bus Controller M LPC Chip Selects Settings TO LPC Chip Selects Burst amp Deadc BV SIM System Integration Module IV ICTL Interrupt Controller IV GPIO General Purpose I O amp Pir 7 GPT General Purpose Timers IV PSC1 UART Codec AC97 Serie mI PSC2 UART Codec AC97 Serie I PSC3 UART Codec Serial Contr I PSC4 UART Serial Controller eJ PSCS5 UART Serial Controller AJT PSC6 IrDA UART Codec Serial T MSCAN1 msCAN 1 Module TO MSCAN2 msCAN 2 Module 817 FEC Fast Ethernet Controller T BDLC Byte Data Link Controler 11 T PCI PCI Local Bus Controller ile Be gt AARNA r Hardware Configuration J Enable Hardware Configuration Items must reconfigure switches jupmers on the board Switch ID Switch Name Reset Config Register Bit Package Pin S xib_clk_sel PORRCFG 26 LP_TS sys_pll_efg0 PORRCFG 25 USB1_1 sys_pll_cfgl PORRCFG 24 USB1_2 AST_CFGO 4 ATA_DACK ATA_IOR EME ppe_pietad 0 PORRCFG 31 27 ATA IOW LP_RWB LP_ALE VCO Domain Reset Configuration T 48 MHz Fractional Divider Ext Clock EXT_XTAL_IN 3 z MHz 48MHz Fractional Divider Enable F_VCO Clock Setting F vco Fractional Divider Phase3 Fractional Divider Phase 2 x x foe MHz F_SYSTEM 8 F_SYSTEM 8 Fractional Divider Phase1 Fractional Divider Phase 0 F_SYSTEM 528 MHz fF system 8 m FsvsTem a gt
98. r statically using the appconfig h file and the GCT The user may also want to save Floating Point context and to re enable the Floating Point unit before passing an execution to the selected interrupt service routines In other words the Interrupt Dispatcher effectively hides the differences between various peripheral interrupt sources of the MPC5200 and makes the interrupt handling easy and straightforward The Interrupt Dispatcher is also natively supported by the GCT At each peripheral module configuration page it is possible to specify an interrupt service routine assign an interrupt source priority and mask or unmask the interrupt source For more information see the Section 6 4 6 Interrupt Controller SIM ICTL The Interrupt Dispatcher is implemented in the following two files all located in the SystemConfig subdirectory of the project folder on a hard disk e vectors asm This file contains Reset exception handler a branch to reset code in the board c file and prologue epilogue code for all other PowerPC exceptions Prologue and epilogue code take care of saving volatile EABI registers and exception return address onto the software stack and of invoking a user supplied exception handler routine MPC5200 Quick Start Rev 3 16 Freescale Semiconductor Application Framework e interrupt c This file implements an Interrupt Dispatcher functionality as described above in this section When the Interrupt Dispatcher is
99. s 7 STARTUP Boot Time Options JO Unrecognized definitions Figure 45 XLB Bus Arbiter Control Page XLARB MPC5200 Quick Start Rev 3 48 Freescale Semiconductor Graphical Configuration Tool 6 4 21 Startup Code Control Page STARTUP As it was already described in Section 5 3 Startup Code the MPC5200 Quick Start startup code invokes the _ pre _main function right before the user s main function is called The default implementation ofthe pre main function in the appconfig c file calls the initialization functions of all MPC5200 modules selected on the STARTUP page of the GCT The GCT saves the information about which modules are to be automatically initialized in several special purpose macro values in the appconfig h file The pre main code does not test whether there is a valid appconfig h configuration of the modules to be initialized For the selected modules the pre_main code simply invokes the ioctl initialization call Thanks to a conditional compilation the initialization functions are empty for modules not configured in the GCT test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help al e 93 t m Target MPC5200B pre main Automatic Module Initialization m6 Communication Modules XL Bus Clock 132 000 MHz 1 PowerPC CORE early in startup c code Core Clock 462 000 MHz M Psa T Psc J Pscs IP Bus Clock 6
100. s Notet The order of module initialization actions is coded in the T PCI PCI Local Bus Controller I sito I GPTO appconfig c file in your project The sequence numbers 7 SDMA BestComm Module I siti T GPTI in each group box here and the TAB key order reflects i ai the default order T SDMA BestComm Task Prioritie atc T GPT2 V SDRAM SDR DDR M Conti Note2 Any module can be re initialized manually using iocth gt lt Z E T T GPT3 3X INIT NULL system call 00 is the module identifier ee ES TARTUP Quick_Start Startup Co 5 GPIO Module I STARTUP Boot Time Options I Unrecognized definitions IV SIM GPIO Modules and Pin Multiplexers Figure 46 Startup Code Control Page STARTUP The order in which the MPC5200 modules are initialized is encoded inthe _ pre _main function in the appconfig c file By default the order of initialization calls is the same as the order of check box buttons on the STARTUP control page Except a simple prerequisite that the GPIO module and port multiplexer should be initialized before the FEC and ATA modules the user can modify the pre_main code and set the order of module initialization calls according to his specific needs The rest of MPC5200 B modules not initialized automatically inthe pre _main can still be initialized manually any time in the main function or other part of a user code The initialization calls are described in the Section 7
101. s the memory map special register bit values and other architecture dependent macros for the target processor qs_arch c Implements an architecture dependent code which was not made inlined in qs_arch h qs_ata h qs_ata c ATA Controller support includes ATA Hard Drive detection functions qs_core h qs_core c PowerPC Core Initialization Code qs_cdm h qs_cdm c Clock Distribution Module support qs_fec h qs_fec c Fast Ethernet Controller support qs_qpio h qs_gpio c General Purpose I O Module support qs_gpt h qs_gpt c General Purpose Tlmers support qs_i2c h qs_i2c c 12C Controller support qs_ictl h qs_ictl c Interrupt Controller support and Interrupt Dispatcher API definition qs_ipbi h qs_ipbi c IPBI Memory Map Module support qs_lIpc h qs_lpc c LocalPlus Bus Controller support qs_mscan h qs_mscan c MSCAN Module support includes complete MSCAN low level driver see the mscan_demo sample application for the low level driver usage qs_pci h qs_pci c PCI Local Bus Controller support includes PCI database lookup functions qs_pcidb h Content of PCI database PCI vendor and PCI device names qs_psc h qs_psc c Programmable Serial Controller support qs_rtc h qs_rtc c Real Time Clock Module support qs_sdma h qs_sdma c BestComm Module support qs_sdram h qs_sdram c SDRAM Controller support includes TAP delay
102. sk The files are described in the following sections 5 2 1 Prefix Files Prefix file is an standard C header file included by default into every C file being compiled A prefix file can be specified among other C compiler settings globally for all the C files in the project When set a prefix file behaves exactly like it is included using an include directive at the beginning of each C file of the project In the Quick Start there is a different prefix file for each project target All prefix files are located in the SystemConfig subdirectory of the project folder Each prefix file defines its macro such as TARGET RAMDEBUG in RAM Debug target using which a source code identifies the target it is being compiled for See Table 1 for prefix file defined macros of each target 5 2 2 Linker Command Files Linker Command Files are processed by the linker when it is placing code and data segments to specific memory locations The linker command file defines memory areas by the means of base address and size and assigns code and data segments declared by the C compiler into those areas In MPC5200 Quick Start there is a separate Linker Command File for each project target All Linker Command Files are located in the SystemConfig sub directory of the project folder on the disk In each target the file defines the location of the exception vectors placement of code and variables into RAM and defines a software stack of a reasonable size 256kB
103. stComm Module Read write iv T SDMA BestComm Task Priorities SDRAM SDR DDR Memory Controller W XLARB XL Bus Arbiter STARTUP Quick_Start Startup Code 7 STARTUP Boot Time Options o Unrecognized definitions RU Figure 19 G2 PowerPC Core Control Page MPC5200 Quick Start Rev 3 26 Freescale Semiconductor Graphical Configuration Tool 6 4 3 Memory Map Module IPBI The memory map module of the MPC5200 controls an assignment of various memory areas to the LocalPlus Bus interface and the SDRAM Controller On this control page like on many others there are hypertext links to the logically connected pages in the GCT LocalPlus Bus page and SDRAM Controller page GCT strictly follows the structure of MPC5200 peripheral modules control registers from different peripheral modules are never mixed on a single page The use of hypertext links is a convenient way how to display a logical connection between separate peripheral modules test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help THEE t m 2 Target MPC52008 XL Bus Clock 132 000 MHz Core Clock 462 000 MHz IP Bus Clock 66 000 MHz PCI Bus Clock 33 000 MHz r Memory Map Start Address End Address Start Address End Address BootCS Enabled OxFFFFO0000 OxFFFFFFFF CS3 Enabled OsFFFFOO0O OsFFFFFFFF cso JV Enabled foxFFooo000 OsFFFFFFFF CS4 Enabled OxFFFF0000
104. t can be created using project templates available in the MPC5200 Quick Start tool 4 1 Project Stationery and Templates A project template can be viewed as a completely prepared and configured project where copy is saved under a custom name and used as a starting point for the user s own development Such copying is done automatically by CodeWarrior when the user selects the project template and specifies a new project name MPC5200 Quick Start Rev 3 6 Freescale Semiconductor MPC5200 Quick Start Projects see Figure 2 and Figure 3 on page 5 A grouped set of different project templates is called Project Stationery Currently there are four project templates each for the MPC5200 and MPC5200B within the MPC5200 Quick Start Stationery The project templates differ in BestComm DMA microcode image and DMA tasks availability e DMA Custom An empty DMA microcode image by default The user is responsible for creating his own set of tasks building the DMA microcode and adding task C API source files to the project The GCT and BestComm Configuration Tool can be used to help implement the DMA functionality Please be aware that BestComm development tools are not included in the MPC5200 Quick Start installation e DMA ImageRtos1 Precompiled RTOS DMA image included in the project C API files for all RTOS1 tasks are already included in the project and the DMA image cannot be further configured by the BestComm Configuration Tool All MP
105. tandard interface or over the Media Independent Interface MII defined by IEEE 802 3 standard The GCT can be used to define initial configuration of the FEC controller as well as to specify parameters which are to be downloaded into the ethernet transceiver over the MII Two key PHY registers can be configured graphically in the GCT the control and auto negotiation registers There is also a way to specify initial values of the custom PHY registers not defined by the IEEE standard for example the LED control registers of the Intel LXT971 used on the Lite5200 board test_projects appconfig_5200B h MPC5200 Graphical Configuration Tool File Edit View Module Help a E Target XL Bus Clock Core Clock IP Bus Clock PCI Bus Clock MPC5200B 132 000 MHz 462 000 MHz 66 000 MHz 33 000 MHz AJA GPIO General Purpose I O amp Pira IR GPIO PSC1 Pins AC97_1 U TE GPIO PSC2 Pins CANI 2 A I GPIO PSC3 Pins USB2 SPI TS GPIO USB1 Pins USB1 UAR I GPIO PSC6 Pins IrDA UAR 8 GPIO Ethernet Pins Eth US IS GPIO I2C Pins 7 GPT General Purpose Timers S17 SLT Slice Timers I SLTO Slice Timer 0 T SLT1 Slice Timer 1 IT RTC Real Time Clock BAW PSC PSC Modules IV PSC1 UART Codec AC97 Serie mY PSC2 UART Codec AC97 Serie EJ PSC3 UART Codec Serial Contr ET PSC4 UART Serial Controller TT PSCS5 UART Serial Controller I PSC6 IrDA UART Codec Serial SJ 12 12C Modules T 12C1
106. ted Reading Before starting with MPC5200 programming the user should become familiar with 32 bit PowerPC architecture and G2_LE PowerPC core implementation The following books are freely available from www freescale com and the Freescale Literature Distribution Center in the PDF form e Programming Environments Manual for 32 Bit Implementations of the PowerPC Architecture MPCFPE32B Describes resources defined by the PowerPC architecture e G2 Core Reference Manual G2CORERM Describes the G2_LE core used in MPC5200 and MPC5200B e MPC5200 Users Guide MPC5200UM e MPC5200B Users Guide MPC5200BUM MPC5200 Quick Start Rev 3 2 Freescale Semiconductor Installation There are also several application notes available from www freescale com and the Freescale Literature Distribution Center in the PDF form that are related to the MPC5200 device e AN2551 MPC5200 Startup Code e AN2604 Introduction to BestComm e AN2458 MPC5200 LocalPlus Bus Interface 2 Installation The MPC5200 Quick Start tool setup pack is distributed as a single self extracting executable file Before installing this tool Microsoft Internet Explorer 5 5 or higher must be installed on the host computer It may also be an advantage to install the CodeWarrior MGT edition before installing MPC5200 Quick Start If this sequence is followed Quick Start project stationery will be installed and integrated directly into the CodeWarrior environment Importa
107. tions Table 3 Module Initialization Commands Module Identifier Initialization Command Description SLTO SLT1 SLT_INIT Initializes the Slice Timer module specified by the module identifier in the ioctl call SPI SPI_INIT Initializes the Serial Peripheral Interface module USB USB_INIT Not implemented There is no support for the USB module in current version of MPC5200_Quick_Start XLARB XLARB_INIT Initializes the XL Bus Arbiter module 8 Sample Applications To demonstrate use of the GCT and a basic access to the peripheral modules several sample applications are included in the MPC5200 Quick Start installation Each application focuses on a single peripheral module of the MPC5200 The appconfig h file contains valid configuration values for the module being demonstrated and also for the other modules needed to run the application CDM SDRAM and PSC1 for a console In most of the cases the STARTUP configuration is set up for an automatic pre main initialization of all modules used in the application All sample applications are located in the sample applications sub directory of the MPC5200_ Quick Start installation folder Applications are organized in folders by compiler and board for which they are tested Except the system files which match exactly the ones in the Project Stationery see Section 4 1 Project Stationery and Templates there is always only a single source file in each sample applicati
108. used the three external exceptions in the vectors asm code are hard routed to handlers supplied in the interrupt c file 5 5 BSP Source Code The MPC5200 Quick Start is based on original Board Support Package BSP code for the MPC5200 To maintain compatibility with older BSP based applications the most of the BSP source files are included in each project created using the MPC5200 Quick Start Stationery All BSP files are physically located in the src support bsp folder in the MPC5200 Quick Start installation In the CodeWarrior project all the BSP files used can be found in the BSP virtual project folder Section 9 MPC5200 BSP gives a brief overview of the BSP code reuse in the MPC5200 Quick Start applications 5 6 DMA Files Each MPC5200 Quick Start project includes a BestComm DMA microcode image as well as a set of the C source files implementing DMA tasks API As described in the Section 4 2 Project Targets there are three project templates in the MPC5200 Quick Start Stationery differing only by the DMA code The projects created using the any of the DMA _ImageRtos templates include all required DMA source files by default The source code files can be found in the DMA RTOSx virtual project folders in the CodeWarrior project tree The project created using the DMA Custom project template includes only the source files containing the empty DMA microcode image In this case the external tools such as BestComm Configuratio
109. wo sub pages under the Interrupt Controller page one for each Interrupt Priority Decoder of the MPC5200 B The first page Figure 26 displays four Critical Priority interrupt sources and all 17 Main Interrupt Controller sources The second page Figure 26 displays all 24 Peripheral Interrupt Controller sources Each source can be assigned a relative priority and can be generally masked disabled or unmasked enabled For the Main Interrupt Controller sources the priority selection also defines which PowerPC core interrupt is physically generated for each source either External 0x500 interrupt or SMI 0x1400 interrupt As the Peripheral Interrupt decoder operates as a client to both Main Interrupt decoder and Critical Interrupt decoder the priority selection of each Peripheral source also defines whether the main interrupt source LO_int or Critical Interrupt source HI_ int will be used by the peripheral source hello_world Graphical Configuration Tool File Edit View Help BH tt a Target MPC5200 ICTL Hardware Operation Interrupt Dispatcher XL Bus Clock 132 000 MHz E s 5 Core Clock 330 000 MHz Peripheral Source amp mask Source Priority Handler Function Using Floats IP Bus Clock 132 000 MHz D BestComm V mask 0 LO_int I Using FP PCI Bus Clock 33 000 MHz A 1 PSC1 V mask 8 HI_int I Using FP IT LPC Chip Selects Burst amp Deadc a 2 PSC2 A onom z r I Using FP BM SIM

MPC5200 Quick Start - Freescale Semiconductor

Contents

Download Pdf Manuals

Related Search

Related Contents