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SIS3300/SIS3301 65/100 MHz VME FADCs User Manual

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1. Position P1 J1 P2 J2 Row z Row d Row z Row d 1 VPC 1 2 GND GND 1 GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 GAP 10 GND GAO GND 11 RESP GA1 12 GND GND 13 GA2 14 GND GND 15 GA3 16 GND GND 17 GA4 18 GND GND 19 20 GND GND 21 22 GND GND 23 24 GND GND 25 26 GND GND 27 28 GND GND 29 30 GND GND 31 GND 1 GND 1 32 GND VPC 1 GND VPC 1 Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 61 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 11 Index 2 ZEN MIB ESE teh Ee ES eerst dei 6 11 15 4 ATE T 51 6 Ue de EE 51 A LE EE EE EE 6 EE EI EE HIER 6 12 54 address DaSE RR ege 54 Address Mapa a 13 address T T 12 addressing geographical isis 6 NEE AE EE EE IE 18 analog MPU in ss sesse KERE GEE bee EE Bee ERGE een 32 ANIME T 16 AUTOSTART EE EES GES Ee E E 58 avera diN E ee EE OE ees 10 30 B Bl FUE EE 58 B2 EB EE 58 IT EE 6 12 59 bank 1 address counter std 41 disable sample clock 22 enable sample clock 22 Event COUNLER sc cri ES 42 event L T 40 event time stamp drectorg eee 28 MEMO SE
2. Offset Size in BLT Access Function Bytes 0x00000000 4 W R Control Status Register J K register 0x00000004 4 R Module Id and Firmware Revision register 0x00000008 4 R W Interrupt configuration register 0x0000000C 4 R W Interrupt control register 0x00000010 4 R W Acquisition control status register J K register 0x00000014 4 R W Extern Start Delay register 0x00000018 4 R W Extern Stop Delay register 0x0000001C 4 R W Time stamp predivider register 0x00000020 4 KAW General Reset 0x00000030 4 KA W_ VME Start sampling 0x00000034 4 KAW VME Stop sampling 0x00000040 4 KA W Start auto bank switch 0x00000044 4 KA W Stop auto bank switch 0x00000048 4 KA W Clear bank 1 memory full 0x0000004C 4 KA W Clear bank 2 memory full 0x00001000 0x1000 BLT32 R Event Time Stamp directory bank 1 0x00002000 0x1000 BLT32 R Event Time Stamp directory bank 2 Event information all ADC groups 0x00100000 4 W only Event configuration register all ADCs 0x00100004 4 W only Trigger Threshold register all ADCs 0x0010001C 4 W only Trigger Flag Clear Counter register all ADCs 0x00100020 4 W only Clock Predivider register all ADCs 0x00100024 4 W only No Of Sample register all ADCs 0x00100028 4 W only _ Trigger setup register all ADCs 0x0010002C 4 W only Max No of Events register all ADCs
3. 4 18 3 MULTIPLEXER MODE Multiplexer mode was implemented to synchronize data acquisition of the SIS3300 1 with slow external multiplexing hardware Refer to section 10 1 1 for a description of this acquisition scheme Both bit 15 of the acquisition control register and bit 15 of the event configuration register have to be set to acquire data in multiplexer mode Page 30 of 64 SIS3300 3301 SIS Documentation SIS GmbH L 65 100 MHz FADCs VME 4 18 4 EXTERNAL RANDOM CLOCK MODE This mode allows for sampling at arbitrary low and non symmetric external clock The digitizer is set up for internal clock and will strobe one datum to memory with the leading edge of the internal clock cycle that follows the leading edge of an external clock pulse as illustrated below Pipelining between the actual analog input signal and the value stored to memory has to be taken into account Both bit 11 of the acquisition control register and bit 11 of the event configuration register have to be set to acquire data in external random clock mode External Clock ee T T Internal Clock HR HR a a PK Fp E Ps di ee ba Clock to Memory EE SG EE NS DE 4 18 5 Page size The page event size is defined by the 3 page size bits as follows Page size Page size Page size Page size Number of divisions Bit 2 Bit 1 Bit 0 Events Bank 0 0 0 128 K Samples 1 0 0 1 16K Samples 8 0 1 0 4 K Samples 32
4. W wrap around bit T1 T2 trigger information ADC 1 3 5 7 ADC 2 4 6 8 of channel group 4 28 Event directories bank 2 0x202000 0x202ffc 0x282000 0x282ffc 0x302000 0x302ffc 0x382000 0x382ffc define SIS3300 EVENT DIRECTORY BANK2 ADC12 0x202000 define SIS3300 EVENT DIRECTORY BANK2 ADC34 0x282000 define SIS3300 EVENT DIRECTORY BANK2_ADC56 0x302000 define SIS3300 EVENT DIRECTORY BANK2 ADC78 0x382000 read only D32 BLT32 size 0x1000 Same as above but for bank 2 Page 40 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 4 29 Bank 1 address counter 0x200008 0x280008 0x300008 0x380008 define SIS3300 BANK1 ADDR CNT ADC12 0x200008 read only D32 define SIS3300 BANK1 ADDR CNT ADC34 0x280008 read only D32 define SIS3300 BANK1 ADDR CNT ADC56 0x300008 read only D32 define SIS3300 BANK1 ADDR CNT ADCT78 0x380008 read only D32 These read only registers hold the current bank 1 address counter for ADC group 1 2 3 4 and bank The counter is 17 bit wide The counter will change while the ADC is sampling after the ADC was stopped the stop position can be retrieved in multi event mode it will have to be read from the event directory The address counter points to the next memory location that will be written to see Trigger event directory also The register is implemented on the channel group base but the information is r
5. W wrap around bit T1 T8 trigger information ADC 1 ADC 8 1 ADC channel has met trigger criterion for this event 0 ADC channel has not triggered for this event 4 26 Trigger event directory bank 2 0x102000 0x102ffc Hdefine SIS3300_ EVENT DIRECTORY BANK2 ALL ADC 0x102000 read only D32 BLT32 size 0x1000 Same as above but for bank 2 Page 39 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 27 Event directories bank 1 0x201000 0x201ffc 0x281000 0x281ffc 0x301000 0x301ffc 0x381000 0x381ffc define SIS3300 EVENT DIRECTORY BANK1 ADC12 0x201000 define SIS3300 EVENT DIRECTORY BANK1 ADC34 0x281000 define SIS3300 EVENT DIRECTORY BANK1 ADC56 0x301000 define SIS3300 EVENT DIRECTORY BANK1 ADC78 0x381000 read only D32 BLT32 size 0x1000 These arrays are redundant and not used in standard operation use the trigger event directory instead The event directories hold the stop pointer s i e end address 1 of each channel group of memory bank 1 The directories are 32 bits wide a wrap around bit i e bit 19 will be set if the page was filled at least once 1 e if the memory pointer has reached the end offset address Event Data End Address D16 DO a mg N D oi A IRI JA m m e ON OO CO N N QA 8 28 0x0 0 T2 T1 0 W JO End Address 1 of Event 0 Oxffc O T2 T1 0 W J0 End Address 1 of Event 1023
6. 0x00101000 0x1000 BLT32 R Event directory bank 1 all ADCs 0x00102000 0x1000 BLT32 R Eevent directory bank 2 all ADCs Event information ADC group 1 0x00200000 4 R W Event configuration register ADC1 ADC2 0x00200004 4 R W Trigger Threshold register ADC1 ADC2 0x00200008 4 R Bank address counter ADC1 ADC2 0x0020000C 4 R Bank2 address counter ADC1 ADC2 0x00200010 4 R Bank Event counter ADC1 ADC2 0x00200014 4 R Bank Event counter ADC1 ADC2 0x00200018 4 R Actual Sample Value ADC1 ADC2 0x0020001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00200020 4 R W Clock Predivider register ADC1 ADC2 0x00200024 4 R W No Of Sample register ADC1 ADC2 0x00200028 4 R W Trigger setup register ADC1 ADC2 0x0020002C 4 R W Max No of Events register ADC1 ADC2 0x00201000 0x1000 BLT32 R Event directory bank 1 ADC1 ADC2 0x00202000 0x1000 BLT32 R Event directory bank 2 ADC1 ADC2 Event information ADC group 2 0x00280000 4 R W Event configuration register ADC3 ADC4 Page 13 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH A 65 100 MHz FADC VME 0x00280004 4 R W Trigger Threshold register ADC3 ADC4 0x00280008 4 R
7. Function 0 GT unused threshold value 0 GT unused threshold value 1 LE ADC 1 3 5 7 1 LE ADC 2 4 6 7 default after Reset Ox3fff3fff Page 32 of 64 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH I VME The function of the trigger setup register is illustrated with the drawing below gt M AL oV OxFFF SE A Threshold F 5V 0x0 COMPARATOR_GT valid I invalid COMPARATOR_LE invalid valid GT N M TRIGGER valid invalid LE N M TRIGGER invalid valid GT_N_M_TRIGGER_PUL i S i vali P LE N M TRIGGER PULS valid P Example LEMO Out1 Page 33 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 20 Trigger Flag Clear Counter register 0x10001C 0x20001C 0x28001C 0x3001C 0x38001C define SIS3300 TRIGGER FLAG CLR CNT ALL ADC 0x10001C write only D32 define SIS3300 TRIGGER define SIS3300 TRIGGER define SIS3300 TRIGGER define SIS3300 TRIGGER LAG CLR CNT ADC12 OX20001C read write D32 LAG CLR CNT ADC34 OX28001C read write D32 LAG CLR CNT ADC56 0x30001C read write D32 LAG CLR CNT ADC78 0x38001C read write D32 F F F F This register is implemented on the base of the channel group Use the address 5153300 TRIGGER FLAG CLR CNT ALL ADC to write to the registers of
8. ir mr s ttt oral JY Dame IS er we Oss GmbH 02 2000 wwwstuckde SS3300 VI Page 50 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 8 Front panel The SIS3300 is a single width 4TE 6U VME module A sketch of the front panel without handles is show below D o a a Or O O Zu LD Ze at E O 000 gt 3 GN Page 51 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH l 65 100 MHz FADC VME 8 1 Control In Outputs The control I O section features 8 LEMOOO connectors with NIM levels Designation Inputs Outputs Designation 4 Clock In Clock Out 4 3 Start Ready for Start bank full output 3 2 Stop Ready for Stop bank full output 2 1 User in User out trigger Multiplexer Strobe bank full output 1 The ready for start and ready for stop outputs can be used to interfere with external deadtime logic Ready for start will become active as soon as the sample clock for one of the banks is active Ready for stop will go active as soon as the start signal was seen by the module The external clock must be a symmetric signal unless the module is operated in external random clock mode The width o
9. Bank 2 memory ADC5 ADC6 0x00780000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC7 ADC8 W in D32 only for memory test e g Note 1 The event information is identical for the four ADC groups unless the module has a hardware problem hence it will be sufficient for normal operation to retrieve the needed information from one group only Note 2 MBLT64 and 2eVME read access is supported from the memory banks only Page 15 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 Register Description The function of the individual registers is described in detail in this section The first line after the subsection header in Courier font like define SIS3300 CONTROL STATUS 0x0 read write D32 refers to the sis3300 h header file 4 1 Control Status Register 0x write read define SIS3300 CONTROL STATUS 0x0 read write D32 The control register is in charge of the control of basic properties of the SIS3300 1 board like output signal assignment in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same registe
10. e trigger generation e 4NIM control inputs 4 NIM control outputs e A32 D32 BLT32 MBLT64 2eVME e Geographical addressing mode in conjunction with VME64x backplane e Hot swap in conjunction with VME64x backplane e VME64x Connectors e VME64x Side Shielding e VME64x Front panel e Oo Note The SIS3300 1 shall not be operated on P2 row A C extensions like VSB e g due to the compatibility to the F1001 FADC modules clock and start stop distribution scheme Page 6 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 2 2 Module design The SIS3300 consists of four identical groups of 2 ADC channels and a control section as shown in the simplified block diagram below e Ee System Clock VME Interface and Control FPGA Front Panel Control VO N Clock Distribution MEM Dual Channel Group 4 Channels 7 and 8 pl Dual Channel Group 3 Channels 5 and 6 Dual Channel Group 2 Channels 3 and 4 VMEBus Dual Channel Group 1 Channels 1 and 2 Page 7 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH A 65 100 MHz FADC VME 2 2 1 Dual channel group Two ADC channels form a group which memory is handled by one Field Programmable Gate Array FPGA Data Memory pt SS address Bank 2 FPGA Event Data Memory Directo
11. 16 0 15 0 14 0 13 0 12 RORA ROAK Mode 0 RORA 1 ROAK 0 11 VME IRQ Enable 0 IRO disabled 1 IRQ enabled 0 10 VME IRQ Level Bit 2 0 9 VME IRQ Level Bit 1 0 8 VME IRQ Level Bit 0 0 H IRQ Vector Bit 7 placed on D7 during VME IRQ ACK cycle 0 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 0 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 0 4 IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle 0 3 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle 0 2 IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle 0 1 IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle 0 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle 0 The power up default value reads 0x 00000000 Page 19 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 4 Interrupt control register OxC define SIS3300 IRQ CONTROL OxC read write D32 This register controls the VME interrupt behaviour of the SIS3300 ADC Four interrupt sources are foreseen for the time being three of them are associated with an interrupt condition the fourth condition is reserved for future use Bit Function w r Default 31 unused Status IRQ source 3 user input 0 30 unused Status IRQ source 2 reserved 0 29 unused Status IRQ source 1 end of last event bank full 0 28 unused Status IRQ source
12. 5 4 2 5 161 R 1 enmaai 30 4 184 EXTERNAL RANDOM CLOCK MODE seep 31 ALSO RE 31 4 19 Threshold registers 0x100004 0x200004 0x280004 0x300004 0Xx380004 ee ee ee 32 4 20 Trigger Flag Clear Counter register 0x10001C 0x20001C 0x28001C 0x3001C 0x38001C 34 4 21 Clock Predivider register 0x100020 0x200020 0x280020 0x300020 0x380020 ee ee 35 4 22 No Of Sample register 0x100024 0x200024 0x280024 0x300024 0x380024 sees sees 36 Page 3 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 100 MHz FADC VME 4 23 Trigger setup register registers 0x 100028 0x200028 0x280028 0x300028 0X380028 eee 37 424 MAX No of Events registers 0x10002C 0x20002C 0x28002C 0x30002C 0x38002C uu 38 4 25 Trigger event directory bank 1 0x 101000 Ox101ffC oe eee 39 4 26 Trigger event directory bank 2 0x 102000 OX102ffC eee eee eee 39 4 27 Event directories bank 1 0x201000 Ox201ffc 0x281000 0x281ffc 0x301000 0x301ffc OxX381000 OX38 EE 40 4 28 Event directories bank 2 0x202000 0x202ffc 0x282000 0x282ffc 0x302000 0x302ffc 0x382000 0 ana OE A AR EE AR EE EE EN 40 4 29 Bank 1 address counter 0x200008 0x280008 0x300008 0x380008 ee ee ee Re ee 41 4 30 Bank 2 address counter 0x20000C 0x28000C 0x30000C Ox38000C ee ee ER 41 4 31 Bank 1 event counter 0x200010 0x280010 0x300010 OX380010 sss esse see eee eee 42 4 32 Bank 2 event counter 0x200014 0x280014 0x300014 0x
13. 59 61 I input EI RE ER iros ER ER 52 EE EE 52 USEF TT 52 IME TTT 19 interrupt Bank Pall sven secs N EE Ei 49 end OF SVEN TT 49 Page 62 of 64 SIS Documentation SIS3300 3301 interrupter MOE sees sees eee 19 DI aT O RTT 19 o N an 5 IRQ bank TNs a aso ice 20 end of EVENE TE 20 USC DLE EE RE 20 IRO m de EE N Ee 19 LE 19 iS ES ii 19 J ER EE EE RE 22 J112 54 REI EE 54 J29 JTAG ue ET aisha 5 54 56 A EE 54 Olas ER AE ARE ER 55 EE 54 K KA clear bank1 full flag ee eee 27 clear bank full flag eee eee 27 general resonar 26 start auto bank switch mode 27 stop auto bank switch mode 27 VME start sampling sese sesse esse se see see ee 26 VME stop sampling 0 0 eee sees sees sees se ese ee ee ee 26 Key address cui 13 L LED A 53 ACCESS deed RE EE EE 53 P 53 R 53 RY N EE MR EE ES 53 SRI EE EE RE ER N 53 c H EE AE EE EE N 53 PERG yah it AE HE 53 U 53 E AE Ed 16 17 53 LEDs front padel ss sera TES cet Nee sde 53 TEMO Raet ege negt ee eT naer 45 55 LINUX A OE EE NE AE EE 19 live insertion se eee 59 61 M M37 MBLETOA de ee Ee ede ei 6 11 15 MEMO Yesa EE EE EE ORE 6 8 management reses EER Fee Ds Ee dee Ese Ge ER Eed 8 lU CVENE ER N N ME ii 8 memory divisions sees sees eee eee 20 mode auto bank switch sees eee 58 SIS GmbH 65 100 MHz FADCs VME ES TTT 30 dual Danks TT 8 external random clock AAA 31 MEE EE 45 GER LE 30 44 A EES GEES Gee Ee ge ee 8 49 multiplexer eee 1
14. EER Se RE Ee ERGER Se ERGER gene d e EE dek euer gepos ech deed 58 10 1 3 Auto bank switchi mode eto 58 IO ee Dier OM seat 59 10 3 Operating conditions s iih nrs EE OE EE EE EE OE 59 ICT 00 EE EE EE EN EE EO EE EE EE OIE 59 10 32 Hotswap liv inSerHOR ies sd osse add 59 10 4 ConnECtO EO EE ER N RE EE EE EE 60 EO AF A C p ES ure EE EE OR OE EO EE EE IN 60 It GE Ed Pin Sa N N OE OE IE ON N 61 REG VT ML EE RR AE OE N 62 Page 4 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 1 Introduction The SIS3300 3301 are eight channel ADC digitizer boards with a sampling rate of up to 105 MHz for the individual channel and a resolution of 12 14 bit The boards are single width 6U VME card which has no special i e non standard VME voltage requirements Dual memory bank functionality in conjunction with multi event memory structure and a range of trigger options give the unit the flexibility to cover a variety of applications Applications comprise but are not limited to e digitization of slow detectors like calorimeters e spectroscopy with Ge detecors e beam profile monitor readout e serialized readout of u Strip detector data As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are
15. MHz FADC VME Note LEMO output 2 ready for stop reflects the phase in which the digitizer is sampling unless the signal was assigned to reflect the bank full pulse by setting bit 9 of the control register 5 3 Start logic summary The diagram below illustrates the implemented start conditions of the SIS3300 1 Autostart LEMO Start In P2 Sample In 2 VME Key Start Note Condition Register Comment I Bit 8 1 Acquisition Control Enable front panel start stop logic 2 Bit 9 1 Acquisition Control Enable P2 start stop logic Bit 6 1 Acquisition Control Start delay enable K Bit 6 0 Acguisition Control No start delay Page 46 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 5 4 Stop logic summary The diagram below illustrates the implemented stop conditions of the SIS3300 1 5 LEMO Start In trailing edge a MUX Internal Trigger LEMO Stop In STOP P2 Reset In 3 PERRY STOP VME Key Stop Autostop Note Condition Register Comment Bit 8 1 Acquisition Control Enable front panel start stop logic Z Bit 9 1 Acquisition Control Enable P2 start stop logic SS Bit 7 1 Acquisition Control Stop delay enable sa Bit 7 0 Acquisition Control No stop delay 5 Bit 10 0 Acquisition Control use start stop mode Bit 10 1 use gate mode 6 Bit 6 1 Control Route trigger Page 47 of 64 SI
16. all channel groups simultaneously The Trigger Flag bit is set as soon as an ADC channel meets the trigger criterion This flag remains latched until the next event start i e it will not be cleared as new ADC data which do not meet the trigger criterion come in with Wrap mode active The Trigger Flag Clear Counter register allows you to define a number of samples after which the Trigger Flag bit will be cleared unless a new trigger occurred A counter for the given ADC channel is preloaded with the value of the Trigger Flag Clear counter register when the trigger criterion for this channel is met Consecutive sampling clocks will decrement the counter and the Trigger Flag bit will be cleared as soon as the counter reaches 0 If a new trigger occurs before the counter has reached 0 it will be reloaded with the value from the register retrigger Note typically the user may want to set the value of the Trigger Flag Clear counter register to the memory page size but this is not mandatory The Trigger Flag Clear Logic is disabled if the counter is loaded with 0 power up default Bit 31 16 15 0 Function unused read back as O Trigger Flag Clear counter register The power up default value is 0 Page 34 of 64 SIS Documentation SIS3300 3301 SIS GmbH l 65 100 MHz FADCs VME 4 21 Clock Predivider register 0x100020 0x200020 0x280020 0x300020 0x380020 define SIS3300 CLOCK PREDIVIDER A
17. by two limit jumpers 2 mm the full range is available with both jumpers open Do not install both jumpers for a channel in parallel channel limit pos offset limit neg offset Offset Potentiometer 1 JP78 JP79 RP80A 2 JP76 JP77 RP70A 3 JP58 JP59 RP60A 4 JP56 JP57 RPSOA 5 JP38 JP39 RP40A 6 JP36 JP37 RP30A 7 JP18 JP19 RP20A 8 JP16 JP17 RP10A The position of the two jumpers JP78 and JP79 close to potentiometer RP80A for ADC channel 1 is illustrated in the portion of the board shown below The displayed area is the vicinity of the channel 1 LEMO input connector CON80 Page 55 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 9 4 JTAG The SIS3300 on board logic can load its firmware either from two serial PROMs or via the JTAG port on connector CON100 A list of firmware designs can be found under http www struck de sis3300firm htm Hardware like the XILINX HW JTAG PC in connection with the appropriate software will be required for in field JTAG firmware upgrades The JTAG connector is a 9 pin single row 1 10 inch header the pin assignment on the connector can be found in the table below Pin Short hand Description 1 VCC Supply voltage 2 GND Ground 3 nc not connected cut to avoid polarity mismatch 4 TCK test clock 5 nc not connected 6 TDO test data out 7 TDI test data in 8 nc not connected 9 TMS
18. clock active trigger can be used to start acquisition e module armed and started trigger can be used to stop acquisition The user can select between triggering on the conditions above and below threshold 2 9 Time Stamp Memory A 1024 x 24 bit Time Stamp Memory is implemented for each memory bank An internal counter starts with the first Stop trigger condition in multievent mode and it will be incremented with the sample clock or with the predivided sample clock factor 1 to 256 Each stop trigger condition end of event writes the counter value into Time Stamp Memory 2 10 VME Interrupts Two registers the Interrupt configuration and the Interrupt control register are implemented for interrupt setup and control Four Interrupt sources are implemented External User Input LEMO input 1 End of event End of last event in multievent mode Memory bank full in bank switch mode Dual bank Page 10 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 2 11 VME Readout Speed The VME interface is optimized for readout speed An internal FIFO pipeline structure allows for high speed readout in block transfer mode BLT32 MBLT64 2eVME The timings below were measured with the SIS3100 VME master and the SIS3300 SIS3301 VME Slave The upper scope trace shows the VME signal DS1 Data strobe low active The VME Master asserts the DS1 to request read data The lower signal shows the VME sign
19. counter is 12 bit wide The counter will change while the ADC is sampling as events are coming in The returned value is the current event number The register is implemented on the channel group base but the information is redundant and in the standard readout case you will want to retrieve the information from one channel group only Bit 31 16 15 0 Function unused read back as O event counter The event counter is not in a defined state after power up or Key Reset 4 32 Bank 2 event counter 0x200014 0x280014 0x300014 0x380014 define SIS3300 BANK2 EVENT CNT ADC12 0x200014 read only D32 define SIS3300 BANK2 EVENT CNT ADC34 0x280014 read only D32 define SIS3300 BANK2 EVENT CNT ADC56 0x300014 read only D32 define SIS3300 BANK2 EVENT CNT ADCT78 0x380014 read only D32 Same as bank 1 event counter but for bank 2 of ADC groups 1 4 Page 42 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 4 33 Actual Sample registers 0x200018 0x280018 0x300018 0x380018 define SIS3300 ACTUAL SAMPLE VALUE ADC12 0x200018 read only D32 define SIS3300 ACTUAL SAMPLE VALUE ADC34 0x200018 read only D32 define SIS3300 ACTUAL SAMPLE VALUE ADC56 0x200018 read only D32 define SIS3300 ACTUAL SAMPLE VALUE ADC78 0x200018 read only D32 Read on the fly of the actual converted ADC values The registers are updated with e
20. online under http www struck de manuals htm 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis3300firm htm The JTAG firmware installation procedure is described in http www struck de sis3300_jtagprog pdf Page 5 of 64 SIS Documentation SIS3300 5153301 65 100 MHz FADC SIS GmbH L VME 2 Technical Properties Features 2 1 Key functionality Find below a list of key features of the SIS3300 and SIS3301 digitizers SIS3300 SIS3301 65 SIS3301 105 Sampling rate per channel 105 MHz 65 MHz 105 MHz Minimum symmetric clock 1 MHz 15 MHz 15 MHz Resolution 12 bit 14 bit 14 bit Analog bandwidth gt 80 MHz 35 MHz Y Typical pedestal variance 0 7 bit 1 1 bit Differential input version A A 2 x 128 KSample default A A A 2 x 512 KSample option A A Timited for better resolution with symmetric input range Common properties of all boards are VME64x extractor handles on request F1002 compatible P2 row A C assignment 5 V 12V and 12 V VME standard voltages e 8 channels e special clock modes clock prescaling external arbitrary clock e channel to channel crosstalk below noise i e invisible in Fourier spectrum e external internal clock e multi event mode e N sample averaging N 2 4 8 128 e Read on the fly actual sample value e pre post trigger option e Two independent memory banks
21. 0 end of event 0 27 unused Status VME IRQ 0 26 unused Status internal IRQ 0 25 unused 0 0 24 unused 0 0 23 Clear IRQ source 3 Status flag source 3 0 22 Clear IRQ source 2 Status flag source 2 0 21 Clear IRQ source 1 Status flag source 1 0 20 Clear IRQ source 0 Status flag source 0 0 19 Disable IRQ source 3 0 0 18 Disable IRQ source 2 0 0 17 Disable IRQ source 1 0 0 16 Disable IRQ source 0 0 0 15 unused 0 0 14 unused 0 0 13 unused 0 0 12 unused 0 0 11 unused 0 0 4 unused 0 0 3 Enable IRQ source 3 Status enable source 3 read as 1 if enabled 0 if disabled 0 2 Enable IRQ source 2 Status enable source 2 read as 1 if enabled 0 if disabled 0 1 Enable IRQ source 1 Status enable source 1 read as 1 if enabled 0 if disabled 0 0 Enable IRQ source 0 Status enable source 0 read as 1 if enabled 0 if disabled 0 The power up default value reads 0x 00000000 Page 20 of 64 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH VME The generation of the status flags the IRQ flags and the actual IRQ is illustrated with the schematic below Eo Source 0 Status FLAG Source 0 Status IRQ Clear Sa Source 1 Enable 0 Source 0 Status FLAG Source 1 Status IRQ Clear ZE Source 2 Enable 1 Source 1 Clear Eg Source 3 Status FLAG Source 2 Status IRQ Enable 2 Source 2 Status IR
22. 0 1 1 2 K Samples 64 1 0 0 1 K Samples 128 1 0 1 512 Samples 256 1 1 0 256 Samples 512 1 1 1 128 Samples 1024 Page 31 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 19 Threshold registers 0x100004 0x200004 0x280004 0x300004 0x380004 define SIS3300 TRIGGER THRESHOLD ALL ADC 0x100004 write only D32 This register is implemented on the base of the individual channel group The address s1S3300 TRIGGER THRESHOLD ALL ADC can be used to write the same value simultaneously to the registers of all channel groups define SIS3300 TRIGGER THRESHOLD ADC12 0x200004 read write D32 define SIS3300 TRIGGER THRESHOLD ADC34 0x280004 read write D32 define SIS3300 TRIGGER THRESHOLD ADC56 0x300004 read write D32 define SIS3300 TRIGGER THRESHOLD ADC78 0x380004 read write D32 These read write registers hold the threshold values for the ADC channels 1 3 5 7 and 2 4 6 8 Via the bits 31 and 15 of the channel group the user can select between greater GT or less than equal as trigger criterion GT means trigger condition is valid if sample data greater then threshold data For SIS3300 Bit 31 30 28 27 16 15 14 12 11 0 Function 0 GT unused threshold value 0 GT unused threshold value 1 LE ADC 1 3 5 7 1 LE ADC 2 4 6 7 default after Reset OxOfffOfff disable Trigger For SIS3301 Bit 31 30 29 16 15 14 13 0
23. 00001300 i e the two channel group ID bits identify the four channel groups 4 18 1 Gate chaining mode Gate chaining mode was implemented to allow for effective acquisition of small events of arbitrary length Sampling in gate chaining mode will stop when e Maximum number of events see 4 24 is reached e End of bank is reached the last event gate may be incomplete in this case The first data word of a gate is marked with a 1 in the G ate bit in memory refer to the data format table in section 4 34 For up to 1024 events the information in the event directory is valid also For gate chaining mode you have to a enable multi event mode b enable gate chaining mode The deadtime between two gates is 8 clock ticks Note the page size bits 2 0 of the event configuration are ignored in gate chaining mode as the event size is defined by the gate length of the individual gate pulses which does not have to be constant 4 18 2 Averaging mode Averaging mode is implemented to improve the signal to noise ratio in lower speed digitization applications N consecutive samples are summed up in the FPGAs of the dual channel groups Averaging mode is activated by specifying a non zero value for bits 18 16 of the event configuration register s Average Bit 2 Average Bit 1 Average Bit0 averaged samples 0 0 0 1 no average 0 0 1 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
24. 18 4 3 Interrupt configuration register UH 19 4 3 1 UE RK 19 44 Interrupt Control register OKC PTT 20 4 5 Acquisition control register 0x10 read write s ee ee Se Se Ge GR RA Re Gee ee Ge ee ee ee ee ee Ge 22 4 6 Start Delay register 0x14 s Ts TO 1 T 24 4 7 Stop Delay register 0X18 read Write s eee ee Ye ee cee EOR ee Ge ee Tarare TERTRE OOE RET ES EEES Ts 24 4 8 Time stamp predivider register OX ICH 25 4 9 Key address general reset OX20 wte nono no nn nono cra cnn crac cnn Se Ge 26 4 10 Key address VME start sampling 0x30 we 26 4 11 Key address VME stop sampling 0x34 Write ee see see see see se ee se ee ee ee Ge GR Ge RA Re Gee ee se ee ee 26 4 12 Key address start Auto Bank Switch mode 0x40 Write sesse ese ee ee ee RA ee Ge ee RA ee ge 27 4 13 Key address stop Auto Bank Switch mode 0x44 Write ese see see se ee ee ee ee ee Se Re Ge RA Gee ee 27 4 14 Key address clear BANK1 FULL Flag 0x48 Write esse sees sees see se ee ee Ge GR GRA Gee ee Ge ee ee ee ee 27 4 15 Key address clear BANK2 FULL Flag Ox4C write iese esse esse ese ee se see Ge ee GR RA eed ee ee se ee ee 27 4 16 Event Time Stamp directory bank 1 0x1000 0x I ffc read only ees see sees eee 28 4 17 Event Time Stamp directory bank 2 0x2000 Ox2ffc read only ees see eee eee 28 4 18 Event configuration registers 0x100000 0x200000 0x280000 0x300000 0x380000 29 4 1831 Gate ue 30 4182 Averaging EE 30 4 183 1 91 B NT E
25. 19 Disable reserved 0 18 Disable auto bank switch mode Bank switch busy 17 Disable sample clock for memory bank 2 disarm sampling 0 16 Disable sample clock for memory bank 1 disarm sampling ADC_BUSY 15 Set multiplexer mode Status multiplexer mode 14 Set clock source Bit 2 Status clock source Bit 2 13 Set clock source Bit 1 Status clock source Bit 1 12 Set clock source Bit 0 Status clock source Bit 0 11 Enable external clock random mode Status external clock random mode 10 Enable front panel gate mode not Start Stop Status front panel gate mode 9 Enable P2 Start Stop logic Status P2 start stop logic 8 Enable front panel Lemo Start Stop logic Status front panel start stop logic 7 Enable stop delay value defined by stop delay register Status stop delay 6 Enable start delay value defined by start delay register Status start delay 5 Enable multi event mode Status multi event mode 0 Enable Sample Clock will be cleared with end of event 1 Enable Sample Clock will be cleared at end of bank only i e with last page of memory 4 Enable Autostart in multi event mode only Status Autostart 3 Enable reserved Status reserved 2 Enable auto bank switch mode Status auto bank switch mode 1 Enable Sample Clock for Memory Bank 2 arm for sampling Status sample clock bank 2 0 Enable Sample Clock for Memory Bank 1 arm for sampling Status sample clock bank 1 The power up default value reads Ox Page 22 of 64 SIS Do
26. 380014 sss eee 42 4 33 Actual Sample registers 0x200018 0x280018 0x300018 OXx380018 sese eee 43 4 34 Bank 1 memory 0x400000 OxS5ffffC s sese eee eee eee 44 4 35 Bank 2 memory 0x600000 Us ffe 44 5 Description of Start Stop and Gate operation moche 45 5 1 Start Stop EE 45 5 1 1 Front panel start Stop rere EE AE AE EE E E EE EE teas 45 5 2 Gate MOUS n MA EE EO EE EE EE EE EE N 45 5 3 Start logic Summary 325 5025 ER EE EE N OE EE EE H 46 5 4 SLOP LOGIC Us ie RE RE EE EE EE ER 47 67 A EG eege 48 6 1 COMM SUPA TT 48 6 2 ATMO LOK Sampdoria 48 6 3 Start Sample 48 6 4 Stop SamplinS Event eme EE EO EE IE 49 6 5 End of Sampling clear arm disable Sample Clock AAA 49 T Board la OU sass EEN GEREI be eneen pecan EE ee een 50 Front panel se EG EN ED E 51 8 1 Control In OW putts cae EE EE EER RE EE RE MO EE tees 52 8 1 1 User oU EE 52 8 1 2 Control input Train OE EE AE OR RR dese Eet sees 52 8 2 ANALOGS Oe 52 8 2 1 Singleended LEMO version E 52 8 2 2 Differential Version sr Serie aww BU ie Se es SR ta th eae eres 52 Ed EA EA ER OE EL ER OE NL OE OE 53 8 47 PECBLEDS SESDE nies ped EE EE GE Ee Ee A ne EE ee EG REG Ee ee ee 53 9 JUMPES CONRA SUPA ON io SES cnn EG RE ebe 54 QT EE 54 9 1 1 SISMO EE 54 9 1 2 SIS3300V2 and RE E 54 EE KREE 54 9 3 OP Set UE EE 55 A RE 56 10 Appendix ET 57 10 1 Data acquisition modes sss sss ee eee 57 10 1 1 Multiplexer mode ME NE EE EN OE ER EO N 57 10 12 Randomexternalclo kmode ui
27. 6 Event information ADC group 4 0x00380000 4 R W Event configuration Register ADC7 ADC8 0x00380004 4 R W Trigger Threshold register ADC7 ADC8 0x00380008 4 R Bank address counter ADC7 ADC8 0x0038000C 4 R Bank address counter ADC7 ADC8 0x00380010 4 R Bank Event counter ADC7 ADC8 0x00380014 4 z R Bank2 Event counter ADC7 ADC8 0x00380018 4 R Actual Sample Value ADC7 ADC8 0x0038001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00380020 4 R W Clock Predivider register ADC7 ADC8 0x00380024 4 R W No_Of_Sample register ADC7 ADC8 0x00380028 4 R W Trigger setup register ADC7 ADC8 0x0038002C 4 R W Max No of Events register ADC7 ADC8 0x00381000 0x1000 BLT32 R Event directory bank 1 ADC7 ADC8 0x00382000 0x1000 BLT32 R Event directory bank 2 ADC7 ADC8 Bank memory 0x00400000 0x80000 BLT32 MBLT64 2e VME R W Bank 1 memory ADC1 ADC2 0x00480000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC3 ADC4 0x00500000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC5 ADC6 0x00580000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC7 ADC8 Bank 2 memory Page 14 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 0x00600000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC1 ADC2 0x00680000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC3 ADC4 0x00700000 0x80000 BLT32 MBLT64 2eVME R W
28. 7 23 30 35 36 57 OU 37 random external clock 23 52 58 SIN GIS Vetusta idas 49 Star SLOP andina 10 45 IEDER ER EA 34 Module dEST ara OER TT ponet ERG Re Ge EE ee ER ee 7 multi event DETRESSE eege 8 multiplexer mode 17 57 N N 37 O T O Oi 55 Operating conditions 00 ee ee eee eee 59 USE EA OE EE 45 48 Operation modeg ee eee ee ee ee ee Se ee ee 8 output bank folls rst CT SR ER EE DE DS eren arat 52 IOGA a Beis te la dle ee 52 CIB SOL sie re Be eli et EG 10 17 52 USER T 52 P P 37 PI T 61 LE 6 61 pin assignments see ee ee Re ee Ge ee 60 PD CLOCK EL OE EE EE EE N 23 USE EE EE EE 8 PAPES EO ER tcs 31 PCB EE 54 61 Pipeline svi she ES dE EE KO 25 57 DAM EE AE AR 9 25 POU sate RO ER EE EE 49 potentiometer eT ARE Ee RE ER 55 power CONSUMPTION oo eee ee eee eee 59 PROM eege cots gege eege 56 R EE 44 register acquisition control8 10 22 24 45 46 49 57 58 actual sample ER SE ee ER ge RS ee cite 43 Clock predivider sss sss 35 38 57 COOL ON cin 18 45 46 DESCUIDO Adore 16 event configuration eee ee eee 8 29 firmware revisgton sesse see see se ee ee GR Re ee 18 Page 63 of 64 SIS Documentation SIS3300 5153301 interrupt configuration see sees eee eee 19 20 Memory Configuration ses sees ee ee ee eee 8 module T T 18 No Of Sample esse esse esse ee ee ee 36 57 start gll ss eleng Dee DE 22 24 SEER AE EE 52 stop delay iscsi OE EA EO 22 24 thf
29. Bank address counter ADC3 ADC4 0x0028000C 4 R Bank2 address counter ADC3 ADC4 0x00280010 4 R Bank Event counter ADC3 ADC4 0x00280014 4 R Bank2 Event counter ADC3 ADC4 0x00280018 4 R Actual Sample Value ADC1 ADC2 0x0028001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00280020 4 R W Clock Predivider register ADC3 ADC4 0x00280024 4 R W No_Of_Sample register ADC3 ADC4 0x00280028 4 R W Trigger setup register ADC3 ADC4 0x0028002C 4 R W Max No of Events register ADC3 ADC4 0x00281000 0x1000 BLT32 R Event directory bank 1 ADC3 ADC4 0x00282000 0x1000 BLT32 R Event directory bank 2 ADC3 ADC4 Event information ADC group 3 0x00300000 4 R W Event configuration register ADC5 ADC6 0x00300004 4 R W Trigger Threshold register ADC5 ADC6 0x00300008 4 R Bank address counter ADC5 ADC6 0x0030000C 4 z R Bank2 address counter ADC5 ADC6 0x00300010 4 R Bank1 Event counter ADC5 ADC6 0x00300014 4 R Bank Event counter ADC5 ADC6 0x00300018 4 R Actual Sample Value ADCI ADC2 0x0030001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00300020 4 R W Clock Predivider register ADCS ADC6 0x00300024 4 R W No Of Sample register ADCS ADC6 0x00300028 4 R W Trigger setup register ADCS ADC6 0x0030002C 4 R W Max No of Events register ADC5 ADC6 0x00301000 0x1000 BLT32 R Event directory bank 1 ADCS ADC6 0x00302000 0x1000 BLT32 R Event directory bank 2 ADCS ADC
30. E ES EN E 44 trigger event directOrV ees esse ese se see see ee 39 bank 2 address counter EE Ses RE rara 41 disable sample clock 22 enable sample clock 22 event COUNSEL ss EE ege een Are 42 event time stamp direCtOFW eee 28 L STT 44 trigger event CirectOry eee ee se se ee ee 39 bloc SERE HE EE EE 8 eo HER EE RE OE EE EE 6 11 board BT ri EERS RE ERGER e EED RE Gee DEEG EA 50 es EE AE Eesen 19 C old EE OE 6 extemal EL OE DATE 9 TTT EE OE ON 9 TS SE EE EE 9 Clock SOUT CES ui 9 22 CONTOU EE 56 STET LT 54 CONNECTION Gia 6 COMNECTON TYPES TTT 60 control MP a EE EN 10 EE EE ER OE 52 Control TO 52 Ca EE ge ee EG Ge ee ED od EE Ge Ee 52 COM ER OE AE EE 59 ErosStalk ss SEE RE ER Se Ee ES Ee Sibel Ee 6 D PERE AE RE EE EE ES EE 6 data format cise EE EE EE DS Berti totes et 44 DESY EE 60 difteria ed Se 52 DOS heats Se5 BAR aa Ghee aa 19 E edge EIER AR HE RE OE OR ees 10 Vi TA AE EE 10 GVENE Ee EE oa ee ee E ee Ee 8 event Counter eee 42 event CITECCOTY lt seet SER ES br SZ ee see see Ge nari n 29 40 41 EVENT SIZE een Siet cde Bese NE EE EE N 29 F BADG T 8 ig dl de N GE EE IE 5 56 oe EO EE N EE OE IE 60 A EG 44 FRG T 8 o OE EK 53 front panel sesse Ee eh Aude Ed Ee deeg giereg 6 51 G LS EE da 12 gate chammng ee se ee ee ee Se Se Ge ee ee ee 30 Bate MOde NE EG 10 geographical addressing sees sees se se ee ee ee 61 GN SE BERE eee OR eects 56 H HI EE E Se Ee ee ee ee estes cas Ee N eek 60 ESE EE EL
31. LE Page 26 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 4 12 Key address start Auto Bank Switch mode 0x40 write define SIS3300 KEY START AUTO BANK SWITCH 0x40 write only D32 A write with arbitrary data to this register key address will start the auto bank switch mode 4 13 Key address stop Auto Bank Switch mode 0x44 write define SIS3300 KEY STOP AUTO BANK SWITCH 0x44 write only D32 A write with arbitrary data to this register key address will stop the auto bank switch mode 4 14 Key address clear BANK1 FULL Flag 0x48 write define SIS3300 KEY BANK1 FULL FLAG 0x48 write only D32 A write with arbitrary data to this register key address will clear the BANK1 FULL Flag 4 15 Key address clear BANK2 FULL Flag 0x4C write define SIS3300 KEY BANK2 FULL FLAG ox4c write only D32 A write with arbitrary data to this register key address will clear the BANK2 FULL Flag Page 27 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 16 Event Time Stamp directory bank 1 0x1000 0x1ffc read only define SIS3300 EVENT TIMESTAMP DIR BANK1 0x1000 read only D32 BLT32 size 0x1000 The event time stamp directory can be used to measure time between triggers stops in multi event mode A scaler counting the ADC clock is enabled with the first stop hence the time stamp for the first event will read 0 always T
32. LL ADC 0x100020 write only D32 define SIS3300 CLOCK PREDIVIDER ADC12 0x200020 read write D32 define SIS3300 CLOCK PREDIVIDER ADC34 0x280020 read write D32 define SIS3300 CLOCK PREDIVIDER ADC56 0x300020 read write D32 define SIS3300 CLOCK PREDIVIDER ADC78 0x380020 read write D32 This register is implemented for each channel group and it has to be written with the same value Use the address S1S3300_ CLOCK PREDIVIDER ALL ADC to write to the registers of all channel groups simultaneously The Clock Predivider factor max 255 Oxff is defined by this register It is used in multiplexer mode only Bit Function Default 31 Unused read 0 0 8 Unused read 0 0 T Clock Predivider bit 7 MSB U U Clock Predivider bit 0 LSB 0 The power up default value reads 0x 00000000 Page 35 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 22 No_Of_Sample register 0x100024 0x200024 0x280024 0x300024 0x380024 define SIS3300 NO OF SAMPLE ALL ADC 0x100024 write only D32 define SIS3300 NO OF SAMPLE ADC12 0x200024 read write D32 define SIS3300 NO OF SAMPLE ADC34 0x280024 read write D32 define SIS3300 NO OF SAMPLE ADC56 0x300024 read write D32 define SIS3300 NO OF SAMPLE ADC78 0x380024 read write D32 This register is implemented for each channel group and it has to be written with the same value Use the a
33. Official release Page 2 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME Table of contents Table ge 3 LOCO TTT 5 1 1 OER MA EE ER EE ME RA EE et 5 2 Technical Propertes Peatures EE 6 2 1 Key functionality EENS Moai heehee EE Ge da 6 2 2 EE EE EE ER EE ER EI EE N OE EE 7 2 21 Tual channel epp KEER aba RE Beata tia ete AS GEE Ee SE EER AE ERE ge 8 2 3 Modes of SS ER EE Rout EER IE EE MO OE Bee eis EN 8 2 4 Memory management EER EE EES edhe BE RE GEVERG ee Se ESE VER aves Ee Geo DR GR eg Oe a ave es 8 2 4 1 Single Event Mode os EG REG Rese Ailes ie iss A Ge Te GE ee Be ee eh ected 8 2 4 2 Multi Event Mode es co Ee esas ESCH iain di ain acct eis Mata ai Ae a ae ee 8 2 4 3 Dual Bank Mode seg AE ER N RE EE EE EE N EA 8 2 5 Clock SsoUrcES EE EE TE EE EE EL ES 9 2 5 1 Internal Clock EE 9 2 5 2 e EA ti diu 9 2 5 3 Random External Clock cnica iio dnde 9 2 6 AVID ai ER EE EE es 10 2 7 Trigger control pre post start stop and gate mode 10 2 8 ANS A IAN 10 2 9 Time Stamp Memory A O 10 2 10 MME InterrupiS EE 10 A AS SEE se Gee Ge GEES Ge GEE ee ee ob ee Ee SEL Ee SEKS LR Oe oe Sae ee GR ee TES se RE Rek Eed 11 3 NVME Addr Ssg EE 12 3 1 Address EE 13 4 Register Description EE 16 4 1 Control Status Register Ox write read ag es e E EE E E EAS 16 4 1 1 BT Te 17 4 1 2 TPS SER TOUTING EE 17 4 2 Module Id and Firmware Revision Register 0x4 ready 18 4 2 1 Major revision numbers TT
34. Q Clear Status FLAG Source 3 Source 3 AND Enable 3 OR internal VME IDO X VME_IRQ_ENABLE ROAK Clear RD_IRQ_ACK g VME_IRQ Page 21 of 64 SIS Documentation SIS3300 5153301 65 100 MHz FADC SIS GmbH VME 4 5 Acquisition control register 0x10 read write define SIS3300 ACQUISTION CONTROL The acquisition control register is in charge of most of the settings related to the actual 0x10 configuration of the digitization process Like the control register it is implemented in a J K fashion read write D32 Bit Write Function Read 31 Clear multiplexer mode 0 30 Clear Clock Source Bit2 0 29 Clear Clock Source Bit1 0 28 Clear Clock Source Bit0 0 27 Disable external clock random mode 0 26 Disable front panel gate mode not start stop 0 25 Disable P2 Start Stop logic 0 24 Disable front panel LEMO start stop logic 0 23 __ Disable external stop delay Bank 2 full 22 Disable external start delay Bank 2 busy 21 Disable multi event mode Bank 1 full 0 Enable sample clock will be cleared with end of event 1 Enable sample clock will be cleared at end of bank only i e with last page of memory 20 Disable Autostart in multi event mode only Bank 1 busy
35. RAM JL TIL TL address 1 0 2 Illustration of multiplexer mode Page 57 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 4 65 100 MHz FADC VME 10 1 2 Random external clock mode Random external clock mode is activated by writing 0x800 to the acquisition control register 10 1 3 Auto bank switch mode Auto bank switch mode was introduced for efficient use of the two memory banks on acquisition The mode is activated by issuing a KEY START AUTO BANK SWITCH after the feature was activated by setting bit 2 in the acquisition control register The bank full flags B1_FULL and B2 PULL are cleared with the KEY at the same time a first start is generated if AUTOSTART is enabled also Data will be acquired into memory bank 1 until the bank is full At this point the flag BI FULL will be set and acquisition changes over to bank 2 if the flag B2_FULL is not set The user can read out data from bank 1 in parallel to ongoing acquisition into bank 2 and clear the B1_FULL flag after the readout was completed As soon as memory bank 2 is filled acquisition will be handed over to bank 1 again if B1_FULL has been cleared already The active memory bank will acquire data until the bank is filled if a KEY STOP AUTO BANK SWITCH is issued Page 58 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 10 2 consumption The SIS3300 1 is a single supply design to facilitate operation in any VME environment i e
36. S Documentation SIS3300 SIS3301 65 100 MHz FADC SIS GmbH VME 6 Operation 6 1 Configuration e Issue key reset e define in Interrupt configuration register VME IRQ Level and Vector type of IRQ requester e define in Interrupt control register enable IRQ source e define in Acquistion register Set Clock source Set Start Stop or Gate mode Enable Disable P2 External Start Stop Enable Disable LEMO External Start Stop Enable Disable External Stop Delay Enable Disable External Start Delay Set Single or Multi Event Mode if Multi Event then enable disable Autostart e define in Event configuration register Enable Disable Autostop at end address of Page Set Page size 6 2 Arm for sampling e define in Acquistion register Enable Sample Clock for Memory Bank or Bank 6 3 Start Sampling e in Single Event mode Issue key Start or External Start e in Multi Event mode with Autostart disabled Issue key Start or External Start for each Event e in Multi Event mode with Autostart enabled Issue key Start or External Start for the first Event only Note activation of auto bank switch mode with multi event mode enabled will start sampling automatically Page 48 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 6 4 Stop Sampling Event e in Single Event mode with Autostop enabled sampling stops automatically at the end address of the pag
37. SIS Documentation SIS3300 3301 SIS GmbH l 65 100 MHz FADCs VME SIS3300 SIS3301 65 100 MHz VME FADCs User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version 3 00 as of 27 05 02 Page 1 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME Revision Table Revision Date Modification 0 01 27 09 00 Generation 1 00 15 01 01 First official release 1 01 17 01 01 Trigger functionality added 1 02 21 01 01 MBLT64 readout 1 03 01 06 01 Bug fix in acquisition register 1 10 01 08 01 Documentation J190 description Design Version 2 added Multiplexer Mode Firmware Revision Register 0x33000102 new bit in Acquisition control register bit 15 MULTIPLEXER Mode new Clock Predivider registers new No_of_Sample registers new Output 1 function in MULTIPLEXER Mode 2 00 29 10 01 V2 hardware revision extended functionality 2 10 05 11 01 extended trigger functionality description 2 11 15 11 01 Bug fixes ADC chip frequency range 3 0x 24 05 02 Prerelease for major functionality firmware upgrade V3 implementation of gate chaining mode introduction of averaging 2e VME readout implementation change in trigger bit behaviour Combination of SIS3300 and SIS3301 manual to one document 3 00 27 05 02
38. al DTACK Data Acknowledge low active The VME Slave asserts the DTACK to acknowledge that the data is valid on VME Tek Run RIS Hi Res DEE F A 11805 E 78418 Edge Slope l SIS330x DS to DTACK 30 40ns See 32bit every 120ns gt 33 MByte sec BA ao a Za ias 1 84 V l d R 2 00 V N Ch2 2 00 VM Toons CH f vya Source Coupling TA Level Mode lt Edge gt Eht DC 1 84 Y Hoidoff BLT32 Tek Run 100MS s Hi Res DS EF i 1 Edge Slope SIS330x DS to DTACK 30 40ns 64bit every 125ns gt 64 MByte sec a 2 00 V N Ch2 2 00V M 100ns Chi A 1 84 V Tek Run DM alll Res DER SIS330x DS to DTACK 50 60ns e E 128bit every 200ns gt 80 MByte sec Lal T L E 1484 Y Level EN E IS7H Hoidorf Page 11 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 4 65 100 MHz FADC VME 3 VME Addressing As the SIS3300 VME FADC features memory options with up to 2 banks of 4 times 128 K samples each A32 addressing was implemented as the only option Hence the module occupies an address space of OXFFFFFF Bytes i e 16 MBytes are used by the module The SIS3300 1 firmware addressing concept is a pragmatic approach to combine standard rotary switch style settings with the use of VME64x backplane geographical addressing functionality The base address is defined by th
39. all groups what is done most straightforward by writing to the address SIS3300 MAX NO OF EVENTS ALL ADC This register is used in GATE Chaining Multi Event Mode only It limits the number of Events in the GATE Chaining Multi Event Mode ate chaining mode sampling will stop when a the maximum number of events is reached or b the end of bank is reached In this case the last event gate may be incomplete Bit 31 16 15 0 Function unused read back as 0 Max_No_Of_Events The power up default value is 0 Page 38 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 4 25 Trigger event directory bank 1 0x101000 0x101ffc define SIS3300 EVENT DIRECTORY BANKI ALL ADC 0x101000 read only D32 BLT32 size 0x1000 This Trigger event directory holds the stop pointer s i e end address 1 of memory bank 1 The directory is 32 bits wide a wrap around bit i e bit 19 will be set if the page was filled at least once 1 e if the memory pointer has reached the end offset address Event Data End Address D16 DO D21 20 D18 D17 19 D31 D30 D29 D28 D27 D26 D25 D24 End Address 1 of Event 0 vd vd N vd LA a as rd Nn 4 ON vd Ad OO 0x0 End Address 1 of Event 1023 LA d S vd 97 gt ON vd vd 00 o Oxffc Ti T2
40. ck mode allows to operate the SIS3300 1 with basically arbitrary external clock pulse trains or slow external clocks The module is clocked with the internal clock typically at 100 MHz and a data word will be stored to memory upon the next leading edge of the internal clock after a leading edge on the external clock input is detected Internal pipelining has to be taken into account the datum will precede the clock by 10 clock ticks i e about 100 ns on a SIS3300 clocking at 100 MHz Page 9 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 2 6 Averaging Averaging over N N 2 4 8 128 consecutive samples can be used to cover the domain of lower speed digitizers with the SIS3300 1 cards without compromising on the resolution signal to noise ratio side 2 7 Trigger control pre post start stop and gate mode The SIS3300 1 features pre post trigger capability as well as start stop mode acquisition and a gate mode in which start and stop are derived from the leading and trailing edge of a single control input signal The trigger behaviour is defined by the acquisition control register 2 8 Internal Trigger generation The trigger output of the SIS3300 1 can be either used to interact with external trigger logic or to base start stop on a threshold i e one individual threshold per ADC channel of the digitized data Trigger generation can be activated with two conditions e module armed i e sample
41. cumentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME Clock source bit setting table Clock Source Clock Source Clock Source Clock Source Bit2 Bitl BitO 0 0 0 internal 100 MHz 0 0 1 internal 50 MHz 0 1 0 internal 25 MHz 0 1 1 internal 12 5 MHz 1 0 0 internal 6 25 MHz 1 0 1 internal 3 125 MHz 1 1 0 external clock front panel 1 1 1 P2 Clock Refer to the table in section 2 5 2for allowed clock speeds Lower sampling rates into memory can be accomplished with a sampling clock within the specified range in combination with the clock predivider register in multiplexer mode or random external clock mode Page 23 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 6 Start Delay register 0x14 read write define SIS3300 START DELAY 0x14 read write D32 Pretrigger operation can be implemented via the start delay register in conjunction with front panel start stop or gate mode operation The external and autostart start signal or leading edge of the gate will be delayed by the value of the register 2 clocks if the external start delay is enabled in the acquisition control register Bit 32 unused read as 0 16 unused read as 0 15 START_DELAY_BITI5 U START_DELAY_BITO The power up default value is 0 4 7 Stop Delay register 0x18 read write define SIS3300 STOP DELAY 0x18 read w
42. ddress s1S3300 NO OF SAMPLE ALL ADC to write to the registers of all channel groups simultaneously The No_of_Sample factor max 255 Oxff is defined by this register It is used in MULTIPEXER mode only Bit Function Default 31 Unused read 0 0 8 Unused read 0 0 7 No_Of_Sample bit 7 MSB U 0 No_Of_Sample bit 0 LSB 0 The power up default value reads 0x 00000000 Note The value of these registers Clock Predivider No_of_Sample is copied autonomously to the 4 ADC groups As the register is write only the user will have to read back the value from one of the ADC groups in case read back functionality is desired Page 36 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 23 Trigger setup register registers 0x100028 0x200028 0x280028 0x300028 0x380028 define SIS3300 TRIGGER SETUP ALL ADC 0x100028 write only D32 define SIS3300 TRIGGER SETUP ADC12 0x200028 read write D32 define SIS3300 TRIGGER SETUP ADC34 0x280028 read write D32 define SIS3300 TRIGGER SETUP ADC56 0x300028 read write D32 define SIS3300 TRIGGER SETUP ADC78 0x380028 read write D32 This bit register is implemented on the channel group the register SIS3300_ TRIGGER SETUP ALL ADC is used to write to the registers of all channel groups simultaneously The behaviour of the trigger output of the SIS3300 can be controlled by this register The user can
43. de Dual bank mode Bank Switch mode is available on cards except SIS3300 V1 PCBs The single multi event selection will influence both memory banks in the same fashion Data from the inactive bank can be readout while the other bank is acquiring new data Page 8 of 64 SIS3300 3301 SIS Documentation SIS GmbH l 65 100 MHz FADCs VME 2 5 Clock sources The SIS3300 3301 features 3 basic clock modes e Internal clock e External symmetric clock e External random clock 2 5 1 Internal clock The internal clock is generated from an on board 50 MHz quartz It is either doubled by a delay locked loop to 100 MHz or divided down to lower clock frequencies The table below lists the valid clock settings for the different SIS3300 3301 boards Clock SIS3300 SIS3301 65 SIS3301 105 100 MHz X X 50 MHz X X X 25 MHz X X X 12 5 MHz X 6 25 MHz X 3 125 MHz X 2 5 2 External clock A symmetric external clock NIM level ratio between 45 55 and 55 45 can be fed to the module through a LEMOOO connector An ECL clock over rows A C of the J2 VME backplane can be used as an alternative For optimum performance the clock frequency should be within the specified range for the given ADC chip Module Min sym clock Max sym clock SIS3300 1 MHz 105 MHz SIS3301 65 15 MHz 65 MHz SIS3301 105 15 MHz 105 MHz 2 5 3 Random External Clock Random external clo
44. e e in Single Event mode with Autostop is disabled Wrap around mode Issue key Stop or External Stop e in Multi Event mode with Autostop is enabled sampling stops automatically at the end address of each page e in Multi Event mode with Autostop is disabled Wrap around mode Issue key Stop or External Stop for each Event 6 5 End of Sampling clear arm disable Sample Clock e in single event mode the Sample Clock Enable bit of the sampling bank is cleared by the logic at the end of sampling one event e in multi event mode the Sample Clock Enable bit of the sampling bank is cleared by the logic at the end of sampling last event The user software can poll on the status of the sample clock enable bit in the acquisition control register or use the end of event or bank full interrupt conditions Page 49 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 7 Board layout A printout of the silk screen of the component side of the PCB is shown below ber vars waaa 7 wanna 7 LEDS4LEDES LEDS2LEDA1 wa CEEI u133 133 _ dh ua aar 1 u en 2 S aas was aI d A 2 re a EE E 3 2 See eng Ba LI r rei Er Wd OF TH
45. e selected addressing mode which is defined by jumper array J1 and possibly SW1 and SW2 in non geographical mode Function EN_A32 c EN_GEO EN_VIPA reserved The table below summarises the possible base address settings J1 Setting Bits A32 GEO VIPA 31 30 29 28 27 26 25 24 D SW SW2 st lei edi al S D X l elel t a a a a GIGI GI G G X Not implemented in this design Shorthand _ Explanation Sw1 Sw2 Setting of rotary switch SW1 or SW2 respective GAO GA4 Geographical address bit as defined by the VME64x P backplane Notes e This concept allows the use of the SIS3300 1 in standard VME as well as in VME64x environments 1 e the user does not need to use a VME64x backplane e The factory default setting is EN_A32 closed SW1 3 SW2 0 i e the module will react to A32 addressing under address 0x30000000 e Early SIS3300 boards PCB SIS3300_V1 have a different base address scheme Page 12 of 64 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH I VME 3 1 Address Map The SIS3300 resources and their locations are listed in the table below Note Write access to a key address KA with arbitrary data invokes the respective action
46. edundant and in the standard readout case you will want to retrieve the information from one channel group only Bit 31 17 16 00 Function unused read back as O address counter The address counter is not in a defined state after power up or Key Reset Unused bits are not updated and may contain arbitrary data 1 e only the number of bits that corresponds to the selected page size will hold significant data example the lowest 7 bits are valid for a page size of 128 4 30 Bank 2 address counter 0x20000C 0x28000C 0x30000C 0x38000C define SIS3300 BANK2 ADDR CNT ADC12 Ox20000C read only D32 define SIS3300 BANK2 ADDR CNT ADC34 Ox28000C read only D32 define SIS3300 BANK2 ADDR CNT ADC56 0x30000 read only D32 define SIS3300 BANK2 ADDR CNT ADC78 0x38000 read only D32 Same as bank 1 address counters but for bank 2 of ADC groups 1 2 3 4 Page 41 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH l 65 100 MHz FADC VME 4 31 Bank 1 event counter 0x200010 0x280010 0x300010 0x380010 define SIS3300 BANK1 EVENT CNT ADC12 0x200010 read only D32 define SIS3300 BANK1 EVENT CNT ADC34 0x280010 read only D32 define SIS3300 BANK1 EVENT CNT ADC56 0x300010 read only D32 define SIS3300 BANK1 EVENT CNT ADCT78 0x380010 read only D32 This read only registers hold the current bank 1 event counter for ADC groups 1 2 3 4 The
47. eshold si EER nao ai 32 34 time stamp predivider sss sese sese eee 25 A EL GE Dee ER Ge Pe ER 37 FER 54 ROAK conato sain dey as 19 RORA EE 19 rotary Switch 12 A EE 19 SIDE COVED T 6 siele E T 52 A EE 12 KA 12 T TICK SERE EERS EE EE AR ON 56 TDD EER RR EE RE HA 56 TDO KERE HE EE EE EN 56 Technical Droperttesibeamures iese ese ee eee 6 threshold SS RE EE EG GE DEE dE 10 32 KEER ER EE EE EE 56 ST EE ER EE OE te 32 39 40 EE OR EE ER N 10 VERE EE AN 10 trigger Control sd Ee ot 10 trigger event directory sss sese eee 39 SIS GmbH 65 100 MHz FADC VME trigger Generatton ee eee see ee cee ee ee n 10 Tundra E 19 U Universe LEE 19 user LI 17 52 LED da 17 LE OE AL AE N 17 52 USER T 44 USER INPUT cid is 52 enable RE iia 17 user output CLEAN ss EE earthen sites BO lid 16 V Mee sE 56 VME ESE SA args at nae oes eg 11 59 backplane ER iia 9 ee else EE EL EE EE RE 60 sie de Lie ER OE RE EE OE EER 10 readout speed 11 NO EE EENS 54 VME addressing iese sesse eee 12 VMEGA Rice tot A 6 12 59 61 VMEOASP rag ch rra oo pic isos 61 VSB do 6 60 W width external start stop esse Re LESER ERGE SEE RAS ists 52 WAP EE 34 wrap around ees se ee ee ee ee ee ee ee 39 40 Page 64 of 64
48. f an external start stop pulse must be greater or equal two sampling clock periods 8 1 1 User input User input functionality was implemented to allow for synchronous recording of one external status bit like chopper on off e g with the ADC data stream The user bin information is recorded with the ADC data see section 4 34 The current status of the logic level is represented by Bit 16 of the status register 8 1 2 Control input termination The control inputs are configured for 50 2 termination 1 e with 47 2 by default Each input is terminated with a resistor network 5 pins 4 resistors common pin to socket pin 6 to ground the names of the input sockets are listed in the table below Designation Inputs Resistor Network 4 Clock In RN140A 3 Start RN140B 2 Stop RN140C 1 User in RN140D 8 2 Analog inputs 8 2 1 Single ended LEMO version The analog inputs of the single ended version are terminated with 50 2 The input range of the initial series is 5V it is shifted with the offset adjustment potentiometer to match the required user input voltage range of 0 5V or 42 5 V 2 5V 8 2 2 Differential version The differential input version will be based on another printed circuit design input termination and availbale input ranges are yet to be defined Page 52 of 64 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH l VME 8 3 LED s The SIS3300 has 8 fron
49. g input connector LEMO EPL 00 250 NTN 90 PCB LEMO Analog input connector LEMO EPG 00 302 NLN 3301 differential input version 10 5 P2 row A C pin assignments The P2 connector of the SIS3300 has several connections on rows A and C for the F1002 compatible use at the DESY H1 FNC subdetector This implies that the module can not be operated in a VME slot with a special A C backplane like VSB e g The pin assignments of P2 rows A C of the SIS3300 is shown below P2A Function P2C Function 1 5 2 V 1 5 2 V 2 5 2 V 2 5 2 V 3 5 2 V 3 5 2 V 4 not connected 4 not connected 5 not connected 5 not connected 6 DGND 6 DGND 7 P2 CLOCK_H 7 P2 CLOCK L 8 DGND 8 DGND 9 Pi START H 9 P2 START L 10 P2 STOP H 10 P2 STOP L 11 P2_TEST_H 11 P2_TEST_L 12 DGND 12 DGND 13 DGND 13 DGND 14 DGND 14 DGND 15 DGND 15 DGND 16 not connected 16 not connected SS He 17 La 31 not connected 18 not connected Page 60 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 10 6 Row d and z Pin Assignments The SIS3300 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing PCB revisions V2 and higher and live insertion hot swap The prepared pins on the d and z rows of the P1 and P2 connectors are listed below
50. gger output Status trigger output inversion 1 inverted O straight 3 Set reserved 3 Status Control 3 Page 16 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 2 Enable trigger output disable user output multiplexer mode 0 Status of user trigger output 1 trigger output user output multiplexer mode 1 output set by multiplexer out pulse 1 Set user output if bit 2 is not set Status User Output 1 output on O output off 0 Switch on user LED Status User LED 1 LED on 0 LED off denotes power up default setting 4 1 1 Trigger activation Trigger generation can be activated for two states of the SIS3300 1 By default trigger generation is active as soon as the module is armed i e a sample clock is active In this mode the trigger can be used to start the digitizer with stop condition end of event e g Trigger generation upon armed and started i e bit 6 of the control register set the trigger is used to stop the module what is a efficient mode of operation in conjunction with autostart e 8 4 1 2 Trigger routing The trigger status is present on LEMO output 1 with user output and multiplexer mode disabled It can be used to form a general trigger decision with external trigger electronics which is fed back to the corresponding input start stop on the digitizer s The trigger 1s routed on board to the stop input with the internal trigger routing b
51. he counter value of the 24 bit wide scaler is written to the corresponding location for subsequent events offset address Time Stamp D23 D0 0x0 Time Stamp 0 Oxffc Time Stamp 1023 4 17 Event Time Stamp directory bank 2 0x2000 0x2ffc read only define SIS3300 EVENT TIMESTAMP DIR BANK2 0x2000 read only D32 BLT32 size 0x1000 As for bank 1 offset address Time Stamp D23 D0 0x0 Time Stamp 0 Oxffc Time Stamp 1023 Page 28 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 18 Event configuration registers 0x100000 0x200000 0x280000 0x300000 0x380000 define SIS3300 EVENT CONFIG ALL ADC 0x100000 write only D32 define SIS3300 EVENT CONFIG ADC12 0x200000 read write D32 define SIS3300 EVENT CONFIG ADC34 0x280000 read write D32 define SIS3300 EVENT CONFIG ADC56 0x300000 read write D32 define SIS3300 EVENT CONFIG ADC78 0x380000 read write D32 This register is implemented for each channel group and it has to be written with the same value the best way is to make use of the address S1S3300 EVENT CONFIG ALL ADC to write to the registers of all channel groups simultaneously The number of memory divisions events is defined by this register in multi event mode The lowest three bits define the number of memory divisions as listed in the table below On dual bank units both memory banks will be affected by
52. it set Page 17 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 2 Module Id and Firmware Revision Register 0x4 read define SIS3300 MODID 0x4 read only D32 This register reflects the module identification of the SIS3300 1 and its minor and major firmware revision levels The major revision level will be used to distinguish between substantial design differences and experiment specific designs while the minor revision level will be used to mark user specific adaptations Bit Function Reading 31 Module Id Bit 15 30 Module Id Bit 14 29 Module Id Bit 13 3 28 Module Id Bit 12 27 Module Id Bit 11 26 Module Id Bit 10 25 Module Id Bit 9 3 24 Module Id Bit 8 23 Module Id Bit 7 22 Module Id Bit 6 21 Module Id Bit 5 0 20 Module Id Bit 4 19 Module Id Bit 3 18 Module Id Bit 2 1 17 Module Id Bit 1 Q 16 Module Id Bit 0 15 Major Revision Bit 7 14 Major Revision Bit 6 13 Major Revision Bit 5 12 Major Revision Bit 4 11 Major Revision Bit 3 10 Major Revision Bit 2 9 Major Revision Bit 8 Major Revision Bit 0 7 Minor Revision Bit 7 6 Minor Revision Bit 6 5 Minor Revision Bit 5 4 Minor Revision Bit 4 3 Minor Revision Bit 3 2 Minor Revision Bit 2 1 Minor Revision Bit 1 0 Minor Revision Bit 0 4 2 1 Major revision numbe
53. ock rate with the time stamp predivider value of O and 1 a prescale factor of 2 65535 is selected by writing the corresponding value to the register Bit 31 unused read as O 16 unused read as 0 15 Time stamp predivider BIT15 0 Time stamp predivider BITO The power up default value is 0 Note A predivider value of 0 can not be used with firmware V201 Page 25 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 9 Key address general reset 0x20 write define SIS3300 KEY RESET 0x20 write only D32 A write with arbitrary data to this register key address resets the SIS3300 to it s power up state 4 10 Key address VME start sampling 0x30 write define SIS3300 KEY START 0x30 write only D32 A write with arbitrary data to this register key address will initiate sampling on the active memory bank if a bank is armed for sampling 4 11 Key address VME stop sampling 0x34 write define SIS3300 KEY STOP 0x34 write only D32 A write with arbitrary data to this register key address will halt sampling on the active page In Single Event Mode or during the last page the sampling this command will halt the the sampling To Abort a sampling in Multi Event Multibank mode the following cycles have to be executed issue disable autostart issue KEY STOP AUTO BANK SWITCH issue SIS3300 KEY STOP issue clear BX ENAB
54. ode Different start and stop conditions can be used in combination with start stop mode as illustrated in the start and stop logic summaries Note LEMO output 2 ready for stop reflects the phase in which the digitizer is sampling unless the signal was assigned to reflect the bank full pulse by setting bit 9 of the control register Sampling LEMO Output 2 0 7 V 5 1 1 Front panel start stop One option to use start stop mode is with NIM front panel start and stop signals The width of the start and stop pulse has to exceed 2 sampling clocks Following steps are part of the setup in this case e enable front panel start stop logic by setting bit 8 of acquisition control register e connect start to LEMO input 3 e connect stop to LEMO input 2 5 2 Gate mode A single external signal is used to define sampling start and stop The start signal i e LEMO input 3 is used as gate input in this mode The leading edge of the signal defines the start the stop condition is given by the trailing edge as illustrated below The width of the gate has to exceed 2 sample clocks Following steps are required to activate gate mode e enable front panel start stop logic set bit 8 of acquisition control register e enable front panel gate mode set bit 10 of acquisition control register DV Start LEMO Input 3 Sampling LEMO Output 2 0 7V Page 45 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100
55. r represents the status register Bit write Function read Function 31 Clear reserved 15 30 Clear reserved 14 29 Clear reserved 13 28 Clear reserved 12 27 Clear reserved 11 26 clear bank full pulse to output 3 25 clear bank full pulse to output 2 24 clear bank full pulse to output 1 23 Clear reserved 7 22 Disable internal trigger routing 21 Activate trigger upon armed 20 Non inverted trigger output 19 Clear reserved 3 Status P2 SAMPLE IN 18 Enable user output disable trigger output Status P2 RESET IN 17 Clear user output Status P2 TEST IN 16 Switch off user LED Status User Input 15 Set reserved 15 Status Control 15 14 Set reserved 14 Status Control 14 13 Set reserved 13 Status Control 13 12 Set reserved 12 Status Control 12 11 Set reserved 11 Status Control 11 10 set bank full pulse to output 3 Status Bank full pulse on LEMO output 3 9 set bank full pulse to output 2 Status Bank full pulse on LEMO output 2 8 set bank full pulse to output 1 Status Bank full pulse on LEMO output 1 highest priority 7 Set reserved 7 Status Control 7 6 Enable internal trigger routing Status trigger routing 1 to input 0 don t route 5 Activate trigger upon armed and started Status trigger generation l armed and started O armed 4 Invert tri
56. rite D32 Posttrigger operation can be implemented via the stop delay register in conjunction with front panel start stop or gate mode operation The external stop signal or trailing edge of the gate will be delayed by the value of the register 2 clocks if the stop delay is enabled in the acquisition control register Bit 32 unused read as 0 16 unused read as 0 15 STOP_DELAY_BIT15 0 STOP DELAY BITO The power up default value is 0 Page 24 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME Note The user can generate a gate of defined length in clock ticks by fanning a short pulse to the start and stop input with start stop mode active stop delay enabled and the stop delay register programmed to the desired gate width Pipelining will have to be taken into account ie the digitised signal is about 40 ns with the module sampling at 100 MHz ahead of the respective control signal a fact that can be used in external trigger decisions For longer external trigger decisions one can consider to pipeline the ADC data in the FPGA in future firmware revisions before storing them to memory 4 8 Time stamp predivider register 0x1C define SIS3300 TIMESTAMP PREDIVIDER Ox1C read write D32 The read write time stamp predivider register is used to define a prescale factor for the frequency of the time stamp counter The time stamp counter counts at the cl
57. rs Find below a table with major revision numbers used to date Major revision number Application user 0x01 to OxOF Generic designs 0x10 Amanda Page 18 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 4 3 Interrupt configuration register 0x8 define SIS3300 IRQ CONFIG 0x8 read write D32 This read write register controls the VME interrupt behaviour of the SIS3300 ADC Four interrupt sources are foreseen for the time being three of them are associated with an interrupt condition the fourth condition is reserved for future use The interrupter type is DOS 4 3 1 IRQ mode In RORA release on register access mode the interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ source disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again ROAK IRQ mode can be used in conjunction with the University of Bonn LINUX Tundra Universe I driver by Dr J rgen Hannappel on Intel based VME SBCs Bit Function Default 31 0 0
58. ry address Bank 1 2 3 Modes of Operation The SIS3300 was developed with maximum flexibility in mind The FPGA based design of the card allows to meet the requirements of many readout applications with dedicated firmware designs in the future The initial firmware is supposed to furnish you with an easy to use yet powerful high speed high resolution Flash Analog to Digital Converter FADC implementation that covers many everyday analog to digital applications 2 4 Memory management The individual memory bank s can be used either as one contiguous memory or as a subdivided multi event memory In addition memory depth can be limited in single event operation to match the requirements of the given application The memory configuration is defined through the memory configuration register while bank handling on dual memory bank modules is under control of the acquisition control register 2 4 1 Single Event Mode The full memory of 128 K Samples of the SIS3300 1 is used as one big circular buffer or as single shot memory in single event mode unless memory size is limited by the event configuration register 2 4 2 Multi Event Mode The memory can be divided in up to 1024 pages or events to make the acquisition of shorter signals more efficient The stop pointers for the individual page can be retrieved from the event directory In auto start mode the ADC advances to the next page and starts sampling automatically 2 4 3 Dual Bank Mo
59. s the actual mode is selected by jumper array J1 The given mode is selected if its corresponding jumper is in place The four jumper positions are described in the table below The A32 jumper is closest to the modules front panel Jumper Function Factory default ER A32 enable A32 addressing closed C GEO enable geographical addressing open e VIPA not implemented yet open E reserved reserved open 9 2 J190 Reset Jumper 5 of jumper array J190 defines the reset behaviour of the SIS3300 upon VME Sysreset If the jumper is closed the module will be reset with VME Sysreset The other fields of the array are unused in the current firmware design ad Jumper Function Factory default ET 1 unused open Sa H 2 enable watchdog closed DU U 3 unused open oa 4 unused open n n 5 unused open DD 6 Connect module reset to VME_Sysreset_ closed o 0 7 unused open o U 8 unused open The enable watchdog jumper has to be removed during the initial JTAG firmware load Page 54 of 64 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 9 3 Offset adjustment The pedestal or offset of the ADC channels can be adjusted with the potentiometers RPIOA through RP80A see table below The sensitivity for the positive or negative offset can be reduced
60. select between a N over M under threshold or a pulsed trigger output with pulse width P At the same time the register holds the values for N M and P as shown in the table below Bit 31 reserved read 0 30 reserved read 0 29 reserved read 0 28 enable pulse mode 27 reserved read 0 26 reserved read 0 25 reserved read 0 24 enable N M mode 23 reserved read 0 20 reserved read 0 19 bit 3 of P 18 bit 2 of P 17 bit 1 of P 16 bit 0 of P 15 reserved read 0 12 reserved read 0 11 bit 3 of N 10 bit 2 of N 9 bit 1 of N 8 bit 0 of N H reserved read 0 4 reserved read 0 3 bit 3 of M 2 bit 2 of M 1 bit 1 of M 0 bit O of M The power up default value reads 0x 00000000 Page 37 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 24 MAX No of Events registers 0x10002C 0x20002C 0x28002C 0x30002C 0x38002C define SIS3300 MAX NO OF EVENTS ALL ADC 0x10002C write only D32 define SIS3300 MAX NO OF EVENTS ADC12 OX20002C read write D32 define SIS3300 MAX NO OF EVENTS ADC34 OX28002C read write D32 define SIS3300 MAX NO OF EVENTS ADC56 0x30002C read write D32 define SIS3300 MAX NO OF EVENTS ADC78 0x38002C read write D32 This register is implemented for each channel group and it has to be configured to the same value in
61. t panel LEDs to visualise part of the modules status The user and access LED are a good way to check first time communication addressing with the module Color Designator Function Red A Access to SIS3300 VME slave port Yellow P Power Green R Ready on board logic configured Green U User to be set cleared under program control Red SAM Sampling Yellow SRT Start lit with start input or leading edge in gate mode Green STP Stop lit with stop input or trailing edge in gate mode Green TRG Trigger lit if one or more channels are above threshold The on duration of the access sampling start stop and trigger LEDs is stretched to guarantee visibility even under low rate conditions 8 4 PCB LEDs The 8 surface mounted red LEDs D200A to D200H on the top left corner of the component side of the SIS3300 are routed to the control FPGA their use may depend on the firmware design Page 53 of 64 SIS3300 5153301 65 100 MHz FADC SIS Documentation SIS GmbH VME 9 Jumpers Configuration 9 1 J1 The function of J1 depends on the PCB printed circuit board revision level The board revision level is printed in white on the lower edge of the card on the component side as a text of the form SIS3300_V1 e g 9 1 1 SIS3300_V1 Selection of bits 31 28 of the 32 bit A32 address see base address section 9 1 2 SIS3300_V2 and higher The SIS3300 supports several addressing mode
62. ted from every channel group internal 17 bit address counter A18 to A2 e 2eVME cycles have to start on a 0x100 boundary 0x0 0x 100 0x200 Data format for SIS3300 offset address ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 29 D28 D27 16 D15 D14 13 D12 D11 0 0x0 U 00 OR bit 12 bit data G 00 OR bit 12 bit data Ox7fffc U 00 OR bit 12 bit data G 00 OR bit 12 bit data Data format for SIS3301 offset address ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 D29 16 D15 D14 D13 0 0x0 U OR bit 14 bit data G OR bit 14 bit data Ox7fffc U OR bit 14 bit data G OR bit 14 bit data Shorthand Explanation U status of user bit if enabled O otherwise OR out of range set with over or underflow 0 otherwise G set on the first sample in Gate Chaining Mode 0 otherwise 4 35 Bank 2 memory 0x600000 Ox7ffffc define SIS3300 MEMBASE BANK2_ADC12 0x600000 define SIS3300 MEMBASE BANK2 ADC34 0x680000 define SIS3300 MEMBASE BANK2_ADC56 0x700000 define SIS3300 MEMBASE BANK2 ADC78 0x780000 Bank 2 memory is installed to allow for parallel readout from one memory bank while the other memory bank is acquiring data The second memory bank has the same structure as bank 1 Page 44 of 64 SIS Documentation SIS3300 3301 SIS GmbH l 65 100 MHz FADCs VME 5 Description of Start Stop and Gate operation modi 5 1 Start stop m
63. test modus Page 56 of 64 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 10 Appendix 10 1 Data acquisition modes 10 1 1 Multiplexer mode Multiplexer mode was implemented to facilitate data acquisition with external multiplexing hardware One of the outputs of the SIS3300 can be used to control the external multiplexing circuitry Multiplexer mode is activated by setting Bit 15 of the acquisition control register Upon a start external or via VME key address the analog input will be latched to memory after N 10 clock cycles At the same time a pulse of width one clock cycle will be generated on ouput 1 Acquisition will terminate after M samples The ADC has an internal pipeline of 12 Clock cycles Note The minimum value for the Predivider register value is 4 Example Assume one multiplexing cycle consists of 20 words The analog signal will become valid after 11 us and will be written to memory after 12 us Set internal Sampling clock to 12 5 MHz gt Clock cycle 80 ns Preset Predivider register to 0x96 150 gt 150 x 80 ns 12 us Preset No Of Sample register to 0x14 20 Write 0x8000 set Bit 15 to acquisition control register SIS3300 Start Input 3 Start Ho Output 1 Next clock Puls Clear Next gt gt gt U MUX Analog Input Analog Inputs bi Start NIM N Output 1 NIM write to
64. the configuration of the event configuration register The maximum number of events is defined by the size of the event directory which has 1024 entries The maximum number of events is limited to 65535 in gate chaining mode to allow for shorter gates also Bit function 31 unused read O 20 unused read 0 19 Event CONF Bit 19 reserved function 18 Average Bit 2 17 Average Bit 1 16 Average Bit 0 15 MULTIPLEXER MODE 14 Event_CONF Bit 14 reserved function 13 Event_CONF Bit 13 reserved function 12 1 former enable trigger event directory 11 EXTERNAL CLOCK RANDOM MODE 10 Event_CONF Bit 10 reserved function 9 Channel Group ID Bit 1 Channel Group ID Bit 0 Event CONE Bit 7 reserved function Event CONF Bit 6 reserved function Event_CONF Bit 5 reserved function ENABLE_GATE_CHAINING_MODE WwW AIIAJN oo Enable Wrap around mode no address auto stop U Autostop at end of page 1 Wrap around page until STOP External or KEY 2 Page size Bit 2 1 Page size Bit 1 0 Page size Bit 0 Page 29 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 4 65 100 MHz FADC VME The power up default values of the registers are SIS3300 EVENT CONFIG ADC12 0x00001000 SIS3300 EVENT CONFIG ADC34 0x00001100 SIS3300 EVENT CONFIG ADC56 0x00001200 SIS3300 EVENT CONFIG ADC78 0x
65. the module does not require special backplanes or non standard VME voltages The power consumption of a two memory bank module digitizing at 100 MHz was measured to be Voltage Current 5V lt 6A 12 V lt 40 mA 12 V lt 60 mA P 32 W 10 3 Operating conditions 10 3 1 Cooling Although the SIS3300 1 is mainly a 2 5 and 3 3 V low power design substantial power is consumed by the Analog to Digital converter chips and linear regulators Hence forced air flow is required for the operation of the board The board may be operated in a non condensing environment at an ambient temperature between 10 and 40 Celsius A power up warm up time of some 10 minutes is recommended to ensure equilibrium on board temperature conditions 10 3 2 Hot swap live insertion Please note that the VME standard does not support hot swap by default The SIS3300 is configured for hot swap in conjunction with a VME64x backplane In non VME64x backplane environments the crate has to be powered down for module insertion and removal Page 59 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 10 4 Connector types The VME connectors and the two different types of front panel connectors used on the SIS3300 are Connector Purpose Part Number 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 LEMO PCB Coax control connector LEMO EPB 00 250 NTN 90 PCB LEMO Analo
66. very ADC clock unless a concurrent VME read access is pending The register contents is refreshed and can be read any time i e they are updated independent of the unarmed armed sampling state as long as a sampling clock is distributed on the ADC board internal clock or active clocking external clock For SIS3300 ADC 1 3 5 7 ADC 2 4 6 8 D31 29 D28 D27 16 D15 13 D12 D11 0 000 OR bit 12 bit data 000 OR bit 12 bit data For SIS3301 ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 D29 16 D15 D14 D13 0 0 OR bit 14 bit data 0 OR bit 14 bit data OR Out of range set with over or underflow Page 43 of 64 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 34 Bank 1 memory 0x400000 Ox5ffffc define SIS3300 MEMBASE BANK1 ADC12 0x400000 define SIS3300 MEMBASE BANK1 ADC34 0x480000 define SIS3300 MEMBASE BANK1 ADC56 0x500000 define SIS3300 MEMBASE BANK1 ADC78 0x580000 write D32 read D32 BLT32 MBL64 2eVME size 0x80000 Bank1 memory is divided into 4 channel groups of 128 KSamples each i e 512 KByte deep for every channel group 2MByte in total The 32 bit wide memory locations hold the data of 2 ADCs each Readout can be done with D32 BLT32 MBLT64 or 2eVME for memory tests D32 write cycles only are supported Notes e FIFO block transfer cycles i e readout from a constant VME address in block transfer are suppor

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