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PIX132 user`s manual

1. SER oa Input A timer value is based upon If the frequency setting is not 16MHz the filter time constant or timer value will differ DO PALFO 4 Bi directional A DO D7 Data Bus 3 state PALFO 3 signals for PA lower D1 PALF 1 3 Bi directional A bi directional 8 bit data bus 4 bit PAO 3 inputs to set the D2 PALF2 2 Bi directional A used in conjunction with system time constant of an integral data bus D7 is the highest filter PALF3 is the highest D3 PALF3 1 Bi directional A signal and DO is the lowest signal and PALFO is the lowest signal Low is 0 and Hi is 1 signal Low is 0 and Hi is 1 D4 PAHFO 64 Bi directional A When CSN is Low and RDN is PAHFO 3 signals for PA D5 PAHF1 63 Bi directional A Low these signals are for upper 4 bit PA4 7 inputs to D6 PAHF2 62 Bi directional A outputting set of the time constant of an integral filter PAHF3 is the Las highest signal and PAHFO is D7 PAHF3 61 Bi directional A the lowest signal Low is 0 and Hi is 1 A0 PBFO 10 Input A AO A2 Address address PBFO 3 signals for port PB A1 PBF1 9 Input A signals for host CPU to access PBO 7 inputs to set the time the read write registers A2 is constant of an integral filter the highest signal and AO is the PBF3 is the highest signal and PAE BE2 8 Input A lowest signal PBFO is the lowest signal Low Low is 0 and Hi is 1 is 0 and Hi is 1 Chip Select input signal for selecting PIX132
2. Switch RR4 5 6 and 7 registers to a display Real Time Input by writing Reference Page Read Register Display Selecting 2 command E6h 5 3 7 Read Register Display Reading RR4 5 6 and 7 registers corresponding to each port the current input Selecting 2 oe signal status the input value configured logical setting after passing the filter 47 RR4 5 6 7 Register 23 is available 5 Output Set Reference Page When the port is configured as output output signals can be set by writing the 4 4 WR4 5 6 7 Register 22 data in WR4 5 6 and 7 registers 5 3 9 Read Register Display To read out the output data currently set write Read Register Display Selecting Selecting 4 ae 4 command E8h and then switch RR4 5 6 and 7 registers to a display 47 RR4567Register 23 Output 2 2 Simultaneous Input Latch This function is to latch all the input signals of port PA PD simultaneously To latch simultaneously there are three ways strobe signal commands and the timer The user can specify which way is to be used by action mode interrupt setting command 1 Latch by Strobe Signal or Commands To perform simultaneous input latch by strobe signal INSTB or commands set 1 to WR2 D2 bit by action mode interrupt setting command and then specify whether to use the rising edge or falling edge of the strobe signal INSTB by WR2 D5 bit All the signals the input value after passing through the filter con
3. Timer Interrupt Delay Time 40 tCYC is a cycle time of CLK 2 VDD 3 3V 10 tDII INSTB Interrupt Delay ns Time tDIO OTSTB Interrupt Delay 59 ns Time tDIC Input Transition Interrupt tcyc 62 ns Delay Time tDIT Timer Interrupt Delay 62 ns 8 2 12 Delay Time in Independent Mode Time tCYC is a cycle time of CLK 1 VDD 5 0V 10 Input Output Transmission Delay Time Note1 HLDN Setup Time HLDN Hold Time OEN Output Delay Time OEN Output Z Delay Time Input Output Transmission Delay Time Note1 HLDN Setup Time HLDN Hold Time OEN Output Delay Time OEN Output Z Delay Time e Note1 Filter is disabled Port PC PD Output Port PC PD Output PIX132 M49 INSTB y INTN tDII OTSTB y Port Input y INN 0 tDIC Timer Internal Counter y Count Out Port PA PB Input HLDN Port PA PB Input tHH OEN 49 NOVA electronics PIX132 M50 9 Package Dimensions E y N A2 t a ee installation 3 1 0 25 Standard Size Face ry Pal 19 j 7 zs S X Section A CJ aaa Al A Details of Section A 50 PIX132 M51 NOVA electronics Symbol Size mm linen Description Minimum Standard Maximum A a 1 2
4. i P1X132 8 bit mf PA PC SAGE Eg Note 8 bit PB integral Filter PD Filter Time Constant Setting Output Enabler Holding Note1 In this figure the integral filter is illustrated by CR but the signal is digitally processed in the IC Fig 1 1 Two Operational Modes of PIX132 Fig 1 2 shows the functional configuration in the IC when used in slave mode i od Data Bus nea S i A CLK 16MHz RESETN VDD IMODEN Timmer 1 u 32sec Time Constant 1 Time Constant 2 Time Constant 3 i Port A High th gt Ga Port A Low pe eee 147 gt PD 3 0 INSTB OTSTB INSTB Simultaneous Input Latch Strobe OTSTB Simultaneous Output Latch Strobe Fig 1 2 Internal Circuit Configuration in Slave Mode NOVA electronics PIX132 M7 The PIX132 has 32 general purpose I O signals consisting of four 8 bit ports Port A Port B Port C and Port D Each 8 bit port is divided into upper and lower 4 bit ports and these can be independently configured for input output selection of filter time constant or input logic The input signal is equipped with a built in integral filter and each filter can select one time constant from three types Fig 1 3 shows the reading and writing flow of input output signals taking as an example a PAO signal one of the 32 bit I O signals Reding Path of Input Signal Realtime Input Latch Input i Input Output gt
5. NOVA electronics PIX132 M18 Signal Name PN Input Output Signal Description Number Slave Mode Independent Mode Interrupt output signal of Test input signal for testing interrupt request for host CPU If the internal circuits When in the interrupt is generated by any independent mode ee interrupt factor INTN will IMODEN Low this signal INTNITEST 14 Bi directional become Low After the interrupt must be connected to GND or is released it will return to Hi Z the internal test circuits will be level activated Independent Mode Set Low connect to GND when PIX132 is IMODEN 60 Input A operated in independent mode And set Hi connect to VDD when PIX132 is operated in CPU slave mode 47 48 51 Port A PA 8 bit I O ports PA 8 bit input ports 52 pa Upper 4 bit and lower 4 bit can These are for input only BAT RAD 53 54 55 Br directional A oi independently configured P s 56 input output by mode setting 37 38 41 Port B PB 8 bit I O ports PB 8 bit input ports 42 Pare i Upper 4 bit and lower 4 bit can These are for input only PBV B 43 44 45 BEATE ALA ed independently configured i 46 input output by mode setting 27 28 29 Port C PC 8 bit I O ports PC 8 bit output ports 30 HE Upper 4 bit and lower 4 bit can PA input signal is output POTSER 33 34 35 Ea a F independently configured ana oe filter P 36 input output by mode setting 17 18 19 Port D PD
6. to RDN CSN Setup Time to RDN Output Data Delay Time from RDN Output Data Hold Time from RDN 1 CSN Hold Time Address Hold Time from RDN 1 from RDN I Address Setup Time to WRN I tCW CSN Setup Time to WRN 1 0 ns tWW WRN Low Level Width 20 ns tDW Setup Time of Input Data to WRNT 15 ns tDH Hold Time of Input Data from WRN 0 ns tWC CSN Hold Time from WRN I 0 ns tWA Address Hold Time from WRN 0 ns 2 VDD 3 3V 410 Address Setup Time to RDN CSN Setup Time to RDN Output Data Delay Time from RDN Output Data Hold Time from RDN CSN Hold Time Address Hold Time from RDN 1 from RDN Address Setup Time CSN Setup Time to WRNI to WRNI WRN Low Level Width Setup Time of Input Data to WRNT Hold Time of Input Data from WRN 1 CSN Hold Time from WRN 1 Address Hold Time from WRN 1 46 NOVA electronics PIX132 M47 8 2 5 Port Input Delay Time The figure on the lower right side shows the delay time when port signals PA 7 0 PB 7 0 PC 7 0 PD 7 0 are read from RR4 7 registers by real time input when disabling the integral filter 1 VDD 5 0V 10 Item Input Transmission Delay Port Input Time RDN 2 VDD 3 3V 10 DI7 0 zal _ _4 Item nR Input Transmission Delay Time 8
7. C2h Time constant 3 Delay 128 u sec Input filter setting WR2 FOh PA Disabled PB Time constant 3 WR3 06h PC High Time constant 1 Low Time constant WRO Cth 2 RR4 5 6 Display WRO ESh Real time input Output Selecting Switching Reading of Input RR4 PA input value 0 Low 1 Hi level Value RR5 PB input value O Hi 1 Low level RR6 PC input value 0 Hi 1 Low level 40 PIX132 M41 NOVA electronics Output Value WR7 lt PD output value 0 Low 1 Hi level Setting Bit Control Output Bit Control Output 0 WRO 1Ah Set low to PD2 signal Bit Control Output 1 WR1 1Ah Set high to PD2 signal Reading of Output RR7 PD output value Read out the current output setting value Value MExample of Setting 2 When CLK is 16MHz Example for simultaneous output With the built in timer the user can set 32 bit of output simultaneously every Imsec at CLK 16MHz The CPU writes next output data in PIX132 by interrupt Initial Setting Input output setting WR2 lt FFh PA PB PC PD All outputs and logical setting of WR3 00h No need to set the logical level for input input signals WRO COh signal Timer value setting WR2 lt E8h 1000u 1msec WR3 03h WRO C3h i Action mode setting WR2 02h Enables simultaneous output set by the timer WR3 01h Enables interrupt by the timer WRO C8h Writing First WR4 PA output value
8. 2 How to Operate PIX132 2 1 General Input Output Operation This chapter shows the user how to operate PIX132 in slave mode which is used in conjunction with the CPU bus PIX132 has four 8 bit ports port PA PB PC and PD Each 8 bit port is divided into upper and lower 4 bit ports and these 4 bit ports can be independently configured input output input logic or filter The operating procedures such as configuration of each port input reading and output set are shown as follows 1 Input Output and Input Logical Setting Reference Page Configure each port whether to be used as input or output When used as input 5 1 Commands for Data Writing 26 input logic is also configured either Hi or Low to 1 5 1 1 Input Output and Input Logical 26 Setting 2 Input Filter Designation Concerning the port configured as input the user specifies whether to pass through the integral filter or not In the case of using the integral filter the Reference Page user can select one time constant from three types 5 1 Commands for Data Writing 26 5 1 2 Filter Time Constant Setting 27 3 Filter Time Constant Setting Configure the time constant of the integral filter of this IC There are three Reference Page types of time constants 1 2 and 3 Each time constant can configure the delay 51 Commands for Data Writing 26 time within the range from 1 u sec to 32msec 5 1 3 Filter Time Constant Setting 27 4 Input Reading
9. 3 registers respectively D7 D6 D5 D4 D3 D2 D1 DO WR2 l Time Constant 2 Setting Time Constant 1 Setting D7 D6 D5 D4 D3 D2 D1 DO WR3 0 0 0 0 Time Constant 3 Setting At CLK 16MHz 27 NOVA electronics PIX132 M28 Removable Removable Setting Value Signal Delay Setting Value Signal Delay Noise Width Noise Width HEX Time usec HEX Time msec u sec msec 0 1 00 0 875 8 0 256 0 224 1 2 00 1 75 9 0 512 0 448 2 4 00 3 50 A 1 02 0 896 3 8 00 7 00 B 2 05 1 79 4 16 0 14 0 C 4 10 3 58 5 32 0 28 0 D 8 19 7 17 6 64 0 56 0 E 16 4 14 3 7 128 112 F 32 8 28 7 Signal delay time shows the standard value It fluctuates within a range from standard value X 0 875 standard value 80nsec Removable noise width indicates the maximum time length of the noise which this filter can remove If the user raises the setting value the maximum width of removable noise becomes larger but signal delay time also bocomes larger so the proper value should be set as the setting value Noise Width n W m __ IN TC Noise Ratio TC However if the noise ratio the time ratio that the noise appears on a signal is larger than 1 2 the filter is unable to remove it MH The recommendation of the setting value Although it depends on the actual circuit configuration or circumstances the following setting values
10. Note1 UA 10 160 uA Input signalA Note 44 NOVA electronics PIX132 M45 Item Mark Condition Min Typ Max Unit Remark High level output on 100 UA voltage on 4mA oL 1004 A oL 4mA Low level output voltage Output leakage Vout Vpp or OV current OUT PP Smith hysteresis voltage Consuming llo OmA CLK 16MHz current lio OMA CLK 33MHz Note1 Input signal A CLK IMODEN A2 A1 AO CSN WRN RDN RESETN INSTB OTSTB E Pin Capacity ten ee coan Tin e ot fae Input capacity Input signal A Input Output Ta 25 C f 1MHz Besides input signal A capacity 8 2 AC Characteristics 8 2 1 Measuring Condition Operating Temperature 40 85 C Output Load D 7 0 85pF Other outputs 50pF Timing Threshold Voltage All the input output signals VDD x0 5 2 5V at VDD 5V 1 65V at VDD 3 3V Input Transition Time insec 5V 8 2 2 Clock VDD 3 0 5 5V tcyc CLK Frequency TWH CLK Cycle CLK Hi Level Wavelength CLK Low Level Wavelength CLK tWL 8 2 3 Reset Signal Width VDD 3 0 5 5V Ta tRS RESETN Pulse 10 ns Ltrs Width 45 NOVA electronics PIX132 M46 8 2 4 CPU Read Write Cycle Read Cycle Write Cycle Al2 0 A2 0 CSN f CSN RDN f RDN WRN WRN D 7 0 COA Data Output D 7 0 L ECR TAR tRC 1 VDD 5 0V 10 Address Setup Time
11. PAO Buffer Reading Input Valu RR4 D0 Input Hi 1 Low 1 Through Output Input iti Differential Transition External Time Constant 1 Latch ia Signal La Command Time Constant 2 La Timmer Time Constant 3 Output Value 0 1 1 0 Writing Path of Output Signal WR4 D0 Register Data Writing Writing Output Value WRO 1 Designated Number Bit Control Output Simultaneous Simultaneous Output Output Buffer External A Signal gt Command Timmer Fig 1 3 Reading and Writing path of input output signals Reading Flow of the Input Signal As shown in Fig 1 3 first an input signal passes through an integral filter a signal can be passed through without the filter When passing through the filter the user can select one time constant from types 1 2 and 3 which are each configurable for delay time from 1 u sec to 32msec Every 4 bit port can be specified as to which time constant to be used The signal passing the filter is set to the logical level where its level can be specified as Hi or Low to 1 The CPU can attain the following information regarding logical input values Real time Input Information about real time input signals Latch Input Information about all inputs which are latched simultaneously by external latch strobe signals command writing from the CPU or the time out of the timer Input Transition Information about the transition of the specified input from 0 to 1 or 1 to 0 The CPU reads
12. This function is to set an output signal by a single bit In the ususal way the output set is performed by writing to WR4 5 6 and 7 registers so that signals are set to each 8 bit port Therefore when the user tries to set one specified output signal to Hi or Low level the user first must set the specified bit of 8 bit output data to 1OR or OAND then write it to the register This IC does not need such a burdensome operation As shown in Fig 1 8 to set one specified signal to Low level write the designation number for the signal to WRO register then the signal will be set to Low or write the designation numbert for the signal to WR1 register then the signal will be set to Hi PAO io hi P 7 Set PDO signal to Low PBO 18h e WRO A Output P7 Set PA7 signal to Hi PAN Buffer PCO oh w WRI DO Low pi Fig 1 8 Example of Bit Control Output Interrupt Generation The interrupt signal can be generated by input transition external strobe and the timer Input Transition Interrupt can be generated at the transition of the specified input signal from 0 to 1 or 1 to 0 selectable concerning all the input signals External Strobe Interrupt can be generated at the transition of external strobe signal INSTB for simultaneous input latch or external strobe signal OTSTB for simultaneous output set The CPU can efficiently control because of no need to wait for these signals Timer Timer can be configured within the range from
13. is displayed The user does not need to write this command for every reading of RR4 5 6 and 7 registers This display selection is enabled until next ES E9h command is written For more details on RR4 5 6 and 7 registers see chapter 4 7 36 NOVA electronics PIX132 M37 5 3 10 Read Register Display Selecting 5 Input Transition Code Command Function E9 pean Register Display Makes RR4 5 6 and 7 registers display input transition Selecting 5 Five kinds of information can be displayed in RR4 5 6 and 7 registers by switching them When writing this command input transition is displayed The user does not need to write this command for every reading of RR4 5 6 and 7 registers This display selection is enabled until next E5 E9h command is written For more details on RR4 5 6 and 7 registers see chapter 4 7 5 3 11 Simultaneous Input Latch Code Command Function Latches all the inputs which are specified to input mode simultaneously EA Simultaneous Input Latch When writing this command the values passed through the filter and set the logical level can be simultaneously latched for all the inputs The D2 bit of WR2 simultaneous input latch 1 must be set to 1 enable by action mode interrupt setting command C8h in advance Latched input values can be read out from these registers if RR4 5 6 and 7 registers are switched to the display of input latch by Read Register Displa
14. the timer stops time out Activated timer value can be read out If the timer interrupt is enabled an interrupt occurs at the termination of the timer In addition simultaneous input latch or simultaneous output set can be performed by the time out of the timer To perform these operations they should be enabled by action mode interrupt setting command before writing this command 5 3 2 Timer Continuous Activation Code Command Function E1 Timer Continuous Activates the timer with continuous activation Activation Writing this command the timer starts to count up from 0 When the counter reaches the timer setting value timer stops and the counter value returns to 0 then counts up continuously To stop this operation write timer stop command E2h or timer cycle stop command E3h For timer interrupt at the count out simultaneous input latch or simultaneous output set can be performed as well as timer single activation 5 3 3 Timer Stop Code Command Function E2 Timer Stop Stops the timer Writing this command the activated timer stops counting up Once the timer is stopped by this command and then activated again the timer will start to count up from 0 5 3 4 Timer Cycle Stop Code Command Function E3 Timer Cycle Stop Stops the timer at the termination of the cycle This command is used to stop the timer at the count out when the timer reaches the timer setting value when the timer i
15. 2 6 Port Output Delay Time The figure on the lower right side shows delay time when port signals PA 7 0 PB 7 0 PC 7 0 PD 7 0 are set output after writing the output data to WR4 7 registers 1 VDD 5 0V 10 Item Output Transmission WRN Delay Time D 7 0 C Ttor 2 VDD 3 3V 10 Port Output Item Output Transmission Delay Time 8 2 7 Bit Control Output Delay Time The figure on the lower right side shows delay time when port signals PA 7 0 PB 7 0 PC 7 0 PD 7 0 are output by bit control after writing output designation number to WRO registers 1 VDD 5 0V 10 Item Output Transmission WRN D 7 0 Delay Time 7 0 d 2 VDD 3 3V 10 Port Output O O Item Output Transmission Delay Time 8 2 8 Strobe Signal Width The figure on the right side shows valid pulse width of INSTB signal and OTSTB signal INSTB OTSTB HER INSTB OTSTB Valid Pulse 10 Width INSTB OTSTB TSBW 47 NOVA electronics PIX132 M48 8 2 9 Simultaneous Input Latch Timing The figure on the lower right side shows timing of Setup Holding of input signals to the rising falling edge of INSTB signal when simultaneous input latch is operated 1 VDD 5 0V 10 w tem Tn eo tSSI Input Signal Setup Time 7 tHSI Input Signal Holding Time 18 ns INSTB Port Input 2 VDD 3 3V 10 are po ten Tn eo tSSI Input Signal Setup Time 7 tHSI Input Signal Holdin
16. Direction of INSTB Signal Selects for use either the rising or falling edge of the INSTB signal When 0 is set it will be the rising edge and when 1 is set it will be the falling edge TIM Timer Interrupt Enabling When 1 is set Timer Interrupt is enabled Start the timer and then when the timer is time out interrupt output signal INTN will be low and DO bit of RR1 register will be 1 Reading RR1 register interrupt output signal will be released returns to Hi Z and the RR1 register will be cleared When the timer is activated continuously an interruption occurs every time out so that the user needs to read the RR1 register each time INS Interrupt Enabling at the Transition of INSTB Input Signal When 1 is set Interrupt Enabling at the Transition of INSTB Input Signal is enabled The direction the rising or falling edge of the transition of the INSTB signal can be selected by WR2 D5 for this command When the INSTB input signal changes interrupt output signal INTN will be low and D1 bit of RR1 register will be 1 Reading RR1 register interrupt output signal will be released returns to Hi Z and RR1 register will be cleared Note Make sure that WR2 D2 SMI1 bit is set to 1 or this interrupt will not be enabled OTS Interrupt Enabling at the Transition of OTSTB Input Signal When 1 is set Interrupt Enabling at the Transition of OTSTB Input Signal is enabled The direction the rising or falling edge of the transition of the OTSTB
17. Not output yet at this time because Output Value WR5 lt PB output value simultaneous output set is enabled by the WR6 PC output value timer by action mode setting WR7 PD output value Timer Continuous WRO Eih Activation Interrupt RR1 Interrupt factor Interrupt factor reading INTN signal released Transaction WR4 PA output value Writing of next output data WR5 PB output value WR6 PC output value WR7 lt PD output value MExample of Setting 3 Example for simultaneous input latch With the built in timer the user can simultaneously latch 32 bit of input and read them every 10msec Initial Setting Input output setting WR2 and logical setting of WR3 input signals WRO Timer value setting WR2 WR3 WRO Action mode setting WR2 WR3 WRO Read register display WRO TT t tT tT TT T T 00h 00h COh OAh 80h C3h 08h 01h C8h E7h PA PB PC PD All inputs Set the logical level for input signal 10msec Enables simultaneous input latch by the timer Enables interrupt by the timer RR4 7 Displays latch input 41 NOVA electronics PIX132 M42 Timer Continuous WRO E1h Activation Interrupt RR1 Interrupt factor Interrupt factor reading INTN signal Transaction RR4 RRS RR6 RR7 gt P input value PB input value gt PC input value PD input value released Reads out the input value simultaneously latched by the time
18. PD Display of Real time Input Latch Input Output Input Transition 4 1 WRO Register Command Execution Bit Control Output 0 WRO Register is used for the following two functions Command Execution Writing a value more than CO hex to WRO register PIX132 takes it as a command and then the corresponding command is executed Please refer to chapter 5 for command execution Bit Control Output 0 The function for only one output signal to be set to low by writing the number corresponding to the output signal to WRO register Write the signal designation number corresponding to the signal shown in the table to D4 D0 of WRO register and the corresponding output signal will be low Note Bit control output 0 is disabled when the simultaneous output is set DO or D1 by C8 command 20 NOVA electronics PIX132 M21 D7 D6 DS D4 D3 D2 D1 DO WRO 0 0 0 Bit Control Output 0 Loo Output Low Signal Designation Number Signal Designation 2 Signal Designation Number Signa Pin Number Number Signal Pin Number Name Name HEX HEX 00 PAO 56 10 PCO 36 01 PA1 55 11 PC1 35 02 PA2 54 12 PC2 34 03 PA3 53 13 PC3 33 04 PA4 52 14 PC4 30 05 PA5 51 15 PC5 29 06 PA6 48 16 PC6 28 07 PA7 47 17 PC7 27 08 PBO 46 18 PDO 26 09 PB1 45 19 PD1 25 OA PB2 44 1A PD2 24 0B PB3 43 1B PD3 21 0c PB4 42 1C PD4 20 OD PB5 41 1D PD5 19 OE PB6 38 1E PD6 18 OF PB7 37 1F
19. PD7 17 It will be disabled when the designation of the signal is not defined as output Note Set 0 to D7 5 bits of WRO register or unexpected commands may be executed 4 2 WR1 Register Bit Control Output 1 The function for only one output signal to be set to Hi by writing the number corresponding to the output signal to WRI register Write the signal designation number corresponding to the signal shown in the table in section 4 1 to D4 D0 of WR1 register and the corresponding output signal will be Hi D7 D6 D5 D4 D3 D2 D1 DO WR1 0 0 0 Bit Control Output 1 Output Hi Signal Designation Number Note Bit control output 1 is disabled when simultaneous output is set DO or D1 by C8 command 4 3 WR2 3 Register Data Writing WR2 3 registers are used to set the data of commands for data writing Writing the command code to WRO register after setting the data to WR2 3 registers the contents of WR2 3 registers will be taken to the IC When the data is a 2 byte length set low byte data to WR2 register and high byte data to WR3 register When the data is a 1 byte length only set to WR2 register with no need to set 0 to WR3 register D7 D6 DS D4 D3 D2 D1 DO WR2 Low byte of Writing Data 21 NOVA electronics PIX132 M22 D7 D6 DS D4 D3 D2 D1 DO WR3 High byte of Writing Data 4 4 WR
20. and timer setting value is N At WR3 D7 0 Tr x16x N At WR3 D7 1 TR x 16000 x N 93 NOVA electronics PIX132 M54 Appendix B Noise Removal of Built in Integral Filter PIX132 is operated in independent mode The following are the waveforms of input signals mixing noise and output signals after passing a built in integral filter 1 Time Constant Setting Value O Delay Time 14 sec CLK 16MHz Output Signal 2 Time Constant Setting Value 7 Delay Time 128 usec CLK 16MHz Noise passed through Low speed Photo Coupler Pulse Width 50 100psec Input Signal Integrated ARRENE Qeeeteeerneee AERE Filter 4 Sd os ei ss i dik i i i T i i Removed Noise i Output Signal Output Signal when Filter is disabled 400 u 54
21. are recommended The noise to be removed or the signal noise to be removed setting value Cross talk in the logic circuit or other induction noise 0 2 The signal from the line receiver 0 2 The signal from high speed photo coupler TLP115A etc 0 3 The signal from low speed photo coupler TLP281 etc 7 9 At CLK 16MHz At resetting 0 1 u sec is set to the time constant 1 2 and 3 5 1 4 Timer Value Setting Code Command Function Sets the timer value within the range from 1 32 767 in units of C3 Timer Value Setting usecormse The timer of this IC is used for interrupt generation simultaneous input latch and simultaneous output set Set the timer value within 1 to 32 767 to WR2 3 registers When the D7 bit of WR3 register is set to 0 1 bit will be in a unit of u sec and when it is set to 1 1 bit will be in a unit of msec D7 D6 D5 D4 D3 D2 D1 DO WR2 Low byte Timer value low D7 D6 D5 D4 D3 D2 D1 DO WR3 High byte Timer value high 0 usec 1 msec 28 NOVA electronics PIX132 M29 The timer value is 1 bit 1 u sec or 1 bit 1msec at CLK 16MHz Start stop of the timer can be performed by EOh E3h commands and reading of the timer value can be performed by DAh command during activation of the timer Please refer to each command At resetting the timer value is 0 5 1 5 PAB Inpu
22. on this IC NOVA electronics 1 2 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 3 1 3 2 3 3 3 4 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 Outline How to Operate PIX132 General Input Output Operation Simultaneous Input Latch Input Transition Trapping Function Simultaneous Output Set Bit Control Output Built in Timer Interrupt Generation Status at Reset Pin Assignments and Signal Description Pin Assignments Signal Description Input Output Circuit Notes for Design Circuitry Register WRO Register Command Execution Bit Control Output 0 WRI Register Bit Control Output 1 WR2 3 Register Data Writing WR4 5 6 7 Register Port Output Value Setting RR1 Register Display of Interrupt Request Factor RR2 3 Register Display of Reading Data RR4 5 6 7 Register Display of Real time Input Latch Input Output Input Transition Commands Commands for Data Writing PIX132 M3 20 21 21 22 22 23 23 29 26 NOVA electronics 5 1 1 Input Output Designation and Logical Setting 5 1 2 Input Filter Designation 5 1 3 Filter Time Constant Setting 5 1 4 Timer Value Setting 5 1 5 PAB Input Transition Enabling Setting 5 1 6 PCD Input Transition Enabling Setting 5 1 7 PAB Input Transition Direction Setting 5 1 8 PCD Input Transition Direction Setting 5 1 9 Action Mode In
23. or higher for 60 seconds or less 4 Solder reflow count Up to twice within the maximum temperature of the heat proof profile The temperatures in the installation conditions are based on the package surface temperature The temperature profile indicates the upper limit of the heat proof temperature Install the IC within the following profile A 260 255 LS 1 4 C seconds g 5 220 190 a Max10 F 150 seconds Feng Main Preheating Heating 60 80seconds Max60seconds er gt a Y 1 4 C seconds La time second PIX132 Standard Soldering Reflow Heat Proof Profile 52 NOVA electronics PIX132 M53 Appendix A Clock Frequency Conversion Formula PIX132 standard frequency of input clock is 16MHz In this manual filter time constant or the timer will be based upon the assumption that all clock frequencies are 16MHz When the user inputs a clock frequency other than 16MHz please refer to the following formulas 1 Filter Delay Time Filter Delay Time Tp SEC can be calculated as follows when clock frequency is f Hz and time constant setting value is N To x 16x 2 2 Removable Noise Width Removable Noise Width Tyw SEC can be calculated as follows when clock frequency is f Hz and time constant setting value is N Tw x14x 2 3 Timer Value Actual time of the time out Tar SEC can be calculated as follows when clock frequency is f Hz
24. registers see chapter 4 7 5 3 7 Read Register Display Selecting 2 Real time Input Code Command Function E6 Read Register Display Makes RR4 5 6 and 7 registers display real time input Selecting 2 Five kinds of information can be displayed in RR4 5 6 and 7 registers by switching them When writing this command real time input is displayed The user does not need to write this command for every reading of RR4 5 6 and 7 registers This display selection is enabled until next ES E9h command is written For more details on RR4 5 6 and 7 registers see chapter 4 7 5 3 8 Read Register Display Selecting 3 Latch Input Code Command Function E7 Read Register Display Makes RR4 5 6 and 7 registers display latch input Selecting 3 Five kinds of information can be displayed in RR4 5 6 and 7 registers by switching them When writing this command latch input is displayed The user does not need to write this command for every reading of RR4 5 6 and 7 registers This display selection is enabled until next ES E9h command is written For more details on RR4 5 6 and 7 registers see chapter 4 7 5 3 9 Read Register Display Selecting 4 Output Code Command Function E8 Mead ned er epi Makes RR4 5 6 and 7 registers display output Selecting 4 Five kinds of information can be displayed in RR4 5 6 and 7 registers by switching them When writing this command output
25. set FA Wi Register 22 simultaneously If WR3 D2 bit is set to 1 by action mode interrupt setting command interrupt can be generated at the transition of the OTSTB signal 2 Simultaneous Output Set by Timer PIX132 is equipped with a built in timer which can set within the range from 1 u sec to 32sec Activating the timer the user can simultaneously output the output values already written in WR4 5 6 and 7 registers at the time out of the timer There are two modes of timer behavior single activation which works only once and continuous activation which repeatedly operates until the CPU stops it In continuous activation output values written in WR4 5 6 and 7 registers are simultaneously output every time out The procedures of simultaneous output set by the timer are shown as follows OD Set 1 to WR2 D1 bit by mode interrupt setting command Also set 1 to WR3 D0 bit if you need to generate the interrupt by the time out Reference Page Set the timer value 5 1 9 Action Mode Interrupt Setting 30 3 Write output values in WR4 5 6 and 7 registers 5 1 4 Timer Value Setting 28 Activate the timer by single activation command or continuous activation 5 3 1 Timer Single Activation 35 command 5 3 2 Timer Continuous Activation 35 Confirm the time out by reading the activated timer value or the interrupt 5 2 3 Activated Timer Value Reading 34 generation Output signals are set at the time out 4 4 WR4 5 6 7
26. signal can be selected by WR2 D4 for this command When the OTSTB input signal changes interrupt output signal INTN will be low and D2 bit of RR1 register will be 1 Reading RR1 register interrupt output signal will be released returns to Hi Z and RR1 register will be cleared Note Make sure that WR2 D0 SMO1 bit is set to 1 or this interrupt will not be enabled TRN Input Transition Interrupt Enabling When 1 is set interrupt occurs at the transition of any of the input signals which are enabled by C4 C5h commands PAB PCD Input Transition Enabling Setting When the enabled signal changes the transition direction is set by C6h C7h commands interrupt output signal INTN will be low Writing E9h command Read Register Display Selecting 5 in advance the input transition will be displayed in RR4 5 6 and 7 registers Reading the register which with the input transition interrupt will be released and transition information will be cleared Make sure that WR2 D6 7 and WR3 D7 4 bits are set to 0 31 NOVA electronics Interrupt Request Factor Summary of the Interrupt Generation and Release Enabling Setting Verification of Occurrence PIX132 M32 Release of the Interrupt Timer C8h Command RR1 DO 1 indicates Released automatically by reading WR3 DO 1 occurrence RR1 register Transition of INSTB Input C8h Command RR1 D1 1 indicates Signal at the WR2 D2 1 and occurrence same as above Simultaneous Inpu
27. values of ports PA PB PC and PD respectively Each register corresponds to RR4 PA 7 0 RR5 PB 7 0 RR6 PC 7 0 and RR7 PD 7 0 23 NOVA electronics PIX132 M24 D7 D6 D5 D4 D3 D2 D1 DO RR4 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO Port PA D7 D6 D5 D4 D3 D2 D1 DO RR5 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO Port PB D7 D6 D5 D4 D3 D2 D1 DO RR6 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO Port PC D7 D6 D5 D4 D3 D2 D1 DO RR7 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO Port PD RR4 5 6 and 7 registers also display not only real time input current input value but latch input input transition and current output value This displayed information can be switched by E5 to E9h commands Displayed Information Contents Command for Bit 1 0 Description Selecting Display Real time Input Displays input value which passed an Depends on input logic integral filter ES setting Latch Input Displays latched input value which passed E7 Depends on input logic an integral filter Note1 setting Output Displays the status of the output signal 0 Low level currently set 1 Hi level Input Transition Displays input transition Note2 0 No transition Information of input transition will be cleared E9 1 Transition occured once it is read out Real time Input Displays real time input when the signal is See above Output set to input mode and displays output value E5
28. when the signal is set to output mode Note1 Latch is performed by any of the three external signal INSTB command EAh or the timer Note2 It is necessary to enable input transition trapping and set the direction of transition in advance The user does not need to write commands for selecting display every reading of the input value Once the commands for selecting display are written they are valid until next commands for selecting display are written The user can confirm the current displayed information of each RR4 5 6 and 7 registers Writing commands for reading data D9h of read register display status the user can read the current selection from RR2 register For more details see chapter 5 2 2 24 NOVA electronics 5 Commands Commands for PIX132 are classified into three groups commands for data writing commands for reading data and other commands Commands for data writing can be performed by writing the command code to WRO after writing the data in WR2 and WR3 WR2 is for low byte data and WR3 is for high byte data If the data is a 1 byte length the user only writes in WR2 and no need to write 0 in WR3 Commands for reading data can be performed by writing the command code to WRO which sets reading data to RR2 3 If the data is a 1 byte length the data will be set to RR2 register and RR3 high byte will be 0 Other commands can be performed by writing the command code to WRO PIX132 M2
29. write the 42 WRI Register al designation number for the signal to WRI register then the corresponding signal will be set to Hi 14 NOVA electronics 2 6 Built in Timer PIX132 M15 PIX132 is equipped with a built in timer which can set within the range from 1 u sec to 32sec The following three operations can be performed at the time out of the timer Please refer to each section Simultaneous Input Latch Section 2 2 Simultaneous Output Set Section 2 4 Interrupt Generation Section 2 7 Procedures to activate the timer are shown as follows Reference Page OD Set the timer value 5 1 9 Action Mode Interrupt Setting 30 If you need to generate the interrupt by the time out set 1 to WR3 DO bit 5 1 4 Timer Value Setting 28 by mode interrupt setting command 5 3 1 Timer Single Activation 35 Activate the timer by single activation command or continuous activation 5 3 2 Timer Continuous Activation 35 command 5 3 3 Timer Stop 35 To stop the single activated timer write Timer Stop Command And to 5 3 4 Timer Cycle Stop 35 stop the continuous activated timer write Timer Stop Command or Timer 5 2 3 Activated Timer Counter Value Cycle Stop Command Reading 34 2 7 Interrupt Generation This IC has an interrupt output signal INTN to the CPU The INTN signal is the open drain output so that it is necessary to pull up to the VDD through resistance Interrupt can be generated by the following four ope
30. 1 u sec to 32sec Interrupt can be generated at the time out of the timer Reading Setting Value Configuration such as input output settings logical settings filter settings output data or all setting data set by the CPU can be read out The current setting data can be read any time so that the CPU does not need to separately keep such output data even when bit control output is performed 10 NOVA electronics PIX132 M11 Independent Mode Operation Independent mode is the operation mode that mainly uses only the integral filter function of this IC and does not connect this IC to the CPU bus Fixed 16 bit inputs are output to fixed output signals through the integral filter The filter time constant can be set to 4 bit of PA 3 0 4 bit of PA 7 4 and 8 bit of PB 7 0 respectively And each delay time of the time constants can be externally designated within the range from 1 u sec to 32msec 4 input signals PA 3 0 PC 3 0 4 input signals WI PA 7 4 Jp PC 7 4 8 input signals Integral Filter PB 7 0 PD 7 0 PA 7 4 Time Corstant Setting PA 3 0 Time Corstant Setting PB Time Constant Setting Note1 In this figure the integral filter is illustrated by CR but the signal is digitally processed in the IC Fig 1 9 PIX132 Independent Mode In addition the signal for filter enable disable output signal holding and output signal enabling enable high impedance are prepared 11 NOVA electronics PIX132 M12
31. 2 M39 Filter Enable Disable PAFE PBFE input signals select whether the filter is enabled or disabled Signals of port PA PA 7 0 are output to port PC PC 7 0 through the integral filter if PAFE input signal is set to Hi level and are output to port PC without the filter if it is set to Low level PBFE input signal selects the signal for port PB as well If PBFE input signal is set to Hi level signals of port PB PB 7 0 are output to port PD PD 7 0 through the integral filter Notes on switching Disable Enable When the filter is disabled filter calculation stops in the IC so that the level before disabling will be output for a maximum of the filter delay time when the filter is switched from disabling to enabling Output Enabling OEN signal is the input signal which enables output ports PC PD When OEN signal is set to Low PC PD output signals are enabled and when set to Hi level PC PD outputs become high impedance Output Holding PC PD port outputs can be kept at holding status When HLDN input signal is set to low level PC PD port outputs will be held and if it returned to Hi PC PD outputs will be free running status and then PA PB signals which passed the filter will be output Notes on Independent Mode 1 Make sure that IMODEN INTN TEST input signals are low short circuited to GND 2 CLK signal must be input or the filter does not work The filter time constant differs when CLK frequency is other th
32. 3 registers i i Displays the current input filter designation in D1 Input filter designation reading C1 RR2 3 registers i i Displays the current value of filter time constant D2 Setting filter time constant reading C2 1 2 and 3 in RR2 3 registers i Displays the current value of the timer in RR2 3 D3 Setting timer value reading C3 registers i i Displays the current setting value of PA PB input D4 PAB Input transition enabling reading H KOKS C4 transition enabling in RR2 3 registers me Displays the current setting value of PC PD input D5 PCD Input transition enabling reading i ons C5 transition enabling in RR2 3 registers E i i i Displays the current setting value of PA PB input D6 PAB Input transition direction reading a i C6 transition direction in RR2 3 registers E i Displays the current setting value of PC PD input D7 PCD Input transition direction reading Ha i mande C7 transition direction in RR2 3 registers i i i i Displays the current value of action D8 Action mode interrupt setting reading C8 5 2 2 Read Register Display Status Reading mode interrupt setting in RR2 3 registers Code Command Function D9 Read Register Display Status Displays the current status of RR4 5 6 and 7 registers Reading in RR2 register Displayed contents of RR4 5 6 and 7 registers differ depending on writing the command E5 E9h This D9h command is to confirm which i
33. 32 bit General Purpose I O Interface IC PIX132 User s Manual 2005 9 08 Ver 1 0 2012 2 20 Ver 2 1 NOVA electronics NOVA electronics PIX132 M2 Introduction Before using the PIX132 please read this manual thoroughly to ensure correct usage according to specifications such as signal voltage signal timing and operational parameter values In general semiconductor products can malfunction or fail to function Therefore when incorporating this IC into a system ensure that a safety system is designed to prevent injury or damage to property caused by any malfunctioning of this IC The PIX132 is designed for application to general electronic devices such as industrial automation and robotics measurement instruments computers office equipment household electrical goods and so on This IC is not intended for use in high performance high reliability equipment where failure or malfunctioning may directly cause death or injuries atomic energy control equipment aerospace equipment transportation equipment medical equipment and various safety devices and operations for such uses cannot be guaranteed The customer shall be solely responsible for the use of this IC in any such high performance and high reliability equipment Notes on independent mode Before using in independent mode make sure that INTN TEST signals 14 pins are short circuited to GND Keeping them open can cause malfunction due to running internal test circuits
34. 4 5 6 7 Register Port Output Value Setting These registers are configurable output values of each port PA PB PC and PD Low can be set to 0 to the corresponding bit of each signal and Hi to 1 as well If the user only sets each half of the port to output mode either value 1 or 0 can be set to the rest of signals configured as input mode They are ignored D7 D6 D5 D4 D3 D2 D1 DO WR4 PAT PA6 PAS PA4 PA3 PA2 PA1 PAO Port PA Output Value Setting O Low 1 Hi D7 D6 DS D4 D3 D2 D1 DO WR5 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO Port PB Output Value Setting D7 D6 DS D4 D3 D2 D1 DO WR6 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO Port PC Output Value Setting D7 D6 D5 D4 D3 D2 D1 DO WR7 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO Port PD Output Value Setting If the user enables simultaneous output 1 2 See action mode interrupt setting command C8h output does not alter immediately after writing the value to WR4 5 6 and 7 registers When the user does not set the input output of each signal to output mode by input output designation command COh data will not output by writing to these registers 4 5 RR1 Register Display of Interrupt Request Factor Displays the interrupt request factor except for input transition 1 indicates that is the interrupt requ
35. 45 45 46 47 47 47 47 48 48 NOVA electronics PIX132 8 2 11 Interrupt Delay Time 8 2 12 Delay Time in Independent Mode 9 Package Dimensions 10 PIX132 Storage and Recommended Installation Conditions 10 1 Storage of this IC 10 2 Standard Installation Conditions by Soldering Iron 10 3 Standard Installation Conditions by Solder Reflow Appendix A Clock Frequency Conversion Formula Appendix B Noise Removal of Built in Integral Filter M5 49 49 50 52 52 52 52 93 04 NOVA electronics 1 Outline PIX132 M6 PIX132 is a 32 bit general purpose I O interface IC equipped with a built in digital integral filter It can independently configure input output input logic or filter time constant every 4 bit port PIX132 provides various functions for output like bit control output and simultaneous output set with a single power supply within the 3 0 to 5 5V range so as to function on both 5V and 3 3V systems PIX132 has two operational modes as shown in Fig 1 1 The first is the CPU slave mode used in conjunction with the CPU bus and the other is the independent mode where sixteen input ports are output through a built in integral filter When the IMODEN input signal is set to Hi the PIX132 operates in slave mode and when set to Low it operates in independent mode CPU lt gt CPU Slave Mode PIX132 PA d spit d spit PC d spit PD d gt amp bit Independent Mode IMODEN Low
36. 5 Writing Reading Group Code Command Data Length Data Length Page Byte Byte co Input output designation and logical setting 2 26 C1 Input filter designation 2 26 C2 Filter time constant setting 2 27 C3 Timer value setting 2 28 Data C4 PAB Input transition enabling setting 2 29 Writing C5 PCD Input transition enabling setting 2 29 C6 PAB Input transition direction setting 2 29 C7 PCD Input transition direction setting 2 30 C8 Action mode interrupt setting 2 30 Do Input output designation and logical setting 2 reading D1 Input filter designation reading 2 D2 Setting filter time constant reading 2 D3 Setting timer value reading 2 33 D4 PAB Input transition enabling reading 2 Reading s Data D5 PCD Input transition enabling reading 2 D6 PAB Input transition direction reading 2 D7 PCD Input transition direction reading 2 D8 Action mode interrupt setting reading 2 D9 Read register display status reading 1 33 DA Activated timer value reading 2 34 E0 Timer single activation 35 E1 Timer continuous activation 35 E2 Timer stop 35 E3 Timer cycle stop 35 E4 Input transition information clear 35 E5 Read register display selecting 1 36 Real time input output E6 Read register display selecting 2 36 others Real time input E7 Read register display selecting 3 36 Latch input E8 Read register display selecting 4 36 Output E9 Read register displa
37. 8 bit I O ports PD 8 bit output ports 20 i i Upper 4 bit and lower 4 bit can PB input signal is output pers 21 24 25 a ki be independently configured through an integral filter 26 input output by mode setting Input Latch Strobe strobe pulse Hold hold the output of ports INSTB HLD 45 Input A to latch PA PD inputs Mode PC PD This signal is low N setting is necessary to function level to hold the port PC PD this Output Latch Strobe strobe Output Enable signal to pulse input for PA PD outputs enable PC PD output ports OTSTB OEN 16 Brdirectonal B to simultaneously output Mode When this signal is low PC uses input only setting is necessary to function PD output signals will be this enabled And when Hi they will be high impedance 5 22 31 5V or 3 3V Power Terminal VDD SS ae All of the 6 pins must be connected to the power pattern on the 39 49 59 substrate 7 23 32 Ground OV Terminal GND 40 50 57 All of 6 pins must be connected to the ground pattern on the substrate 18 NOVA electronics PIX132 M19 3 3 Input Output Circuit Input A More than 10k Q hundreds of kilo impedance is for internal impedance which can pull up the VDD to the TTL Level input of a Smith trigger CMOS and TTL can be connected The user should open or pull up to VDD if the input is not used Bi directional A Bi directional B 3 4 Notes for Des Input side is TTL Smith trigger which is h
38. COPAL ELECTRONICS EN C C SA7270 GZ Ga GZ Note 1 Make sure that IMODEN and TEST terminals are connected to GND 2 Pins for PBF3 2 1 0 are not in sequence 43 NOVA electronics PIX132 M44 8 Electrical Characteristics 8 1 DC Characteristics E Absolute Maximum Rated Power Voltage 0 3 6 5 Input Voltage 0 3 Vpp 0 3 Input Current 10 Storage Temperature E Recommended Power Voltage Operation Environment 40 125 Operating Temperature E DC Characteristics 1 At Vbo 5V Ta 40 85 C Vop 5V 10 Item Mark Condition Min Typ Max Unit Remark High level input voltage Low level input voltage Vin 2 0 Vppt0 3 v High level input current Low level input current High level output voltage Besides input signal A Note1 Input signal A Note1 100UA 8mA Low level output voltage 100uUA 8mA Output leakage current Vout Vpp or OV Smith hysteresis voltage Consuming current lo OMA CLK 16MHz lo OMA CLK 33MHz Note1 Input signal A CLK IMODEN A2 A1 AO CSN WRN RDN RESETN INSTB OTSTB MH DC Charactieristics 2 At Vpp 3 3V High level input voltage Ta 40 85 C Vop 3 3V 10 Condition Remark Low level input voltage High level input current Low level input current Besides input signal A 10
39. D3 PD2 PD1 PDO 5 1 7 PAB Input Transition Direction Setting Code Command Function C6 PAB Input Transition Specifies which transition of the input value is to be trapped Direction Setting from 0 to 1 or 1 to 0 for each input of ports PA PB Set the transition direction of the input of PA 7 0 to WR2 register and the input of PB 7 0 to WR3 register When 0 is set it traps the transition from 0 to 1 and when 1 is set it traps the transition from 1 to 0 29 NOVA electronics PIX132 M30 D7 D6 D5 D4 D3 D2 D1 DO WR2 PA7 PA6 PAS PA4 PA3 PA2 PAI PAO 0 Transition of the input value from 0 to 1 1 Transition of the input value from 1 to 0 D7 D6 D5 D4 D3 D2 D1 DO WR3 PB7 PB6 PBS PB4 PB3 PB2 PBI PBO Note If the direction of the transition is changed by this command after setting Input Transition Enabling Setting input transition may be 1 due to the change Clear the transition information by E4h command after writing this command 5 1 8 PCD Input Transition Direction Setting Code Command Function C7 PCD Input Transition Specifies which transition of the input value is to be trapped Direction Setting from 0 to 1 or 1 to 0 for each input of ports PC PD Set the transition direction of the input of PC 7 0 to WR2 register and the input of PD 7 0 to WR3 register When 0 is set it traps the transition from 0 to 1 and w
40. Height from installation face to top end of package 0 047 main unit A1 0 _ 0 25 Height from installation face to bottom end of 0 010 package main unit A2 0 95 1 0 1 05 Height from top to bottom of package main unit 0 037 0 039 0 041 b 0 15 0 22 0 28 Pin width 0 006 0 009 0 011 0 12 0 17 0 22 Pin thickness 0 005 0 007 0 009 D 11 8 12 0 12 2 Maximum length of package length direction 0 465 0 472 0 480 including pins D1 9 9 10 0 10 1 Length of package main unit excluding pins 0 390 0 394 0 398 E 11 8 12 0 12 2 Maximum length of package width direction 0 465 0 472 0 480 including pins E1 9 9 10 0 10 1 Width of package main unit excluding pins 0 390 0 394 0 398 e 0 5 Pin pitch standard size 0 020 L 0 45 0 6 0 75 Length of flat section of pins contacting the 0 018 0 024 0 030 installation face Z 1 25 TYP Length from center of outer most pin to outer most 0 049 TYP pin section of package main unit 0 0 10 Angle of pin flat section to installation face 0 10 Uniformity pin base permissible value of the 0 004 vertical bbb 0 10 Permissible error value of pin center position 0 004 horizontal 51 NOVA electronics PIX132 M52 10 PIX132 Storage and Recommended Installation Conditions 10 1 Storage of this IC Note the following items in regard to the storage of this IC 1 Do not throw or drop the IC Otherwise the packing material could be
41. Register 22 With the interrupt generation the user can validate the interruption from the timer by RR1 DO bit INTN signal will be released by reading RR1 D0 1 When the timer is activated in continuous activation write next output values in WR4 5 6 and 7 registers and then repeat to Notes on Simultaneous Output Set Output Port Capacitance Load Please do not set the capacitance load over 50pF per output port to all the outputs simultaneously as an operation error may occur In such a case place the driver IC after the output port Preventive measures for Simultaneous Switching In a customer system when the user tries to control switching on off of a large current in the back step of this IC using the simultaneous output set function it is necessary to take preventive measures that minimize the voltage fluctuation of GND Power or Cross Talk between the signals whch are generated by simultaneous switching of a large current Delay in Port PA PD To avoid malfunction by simultaneous switching in the IC outputs of ports PA PD are delayed about 7nsec VDD SV typ value from those of ports PB PC See section 8 2 9 2 5 Bit Control Output PEN i Ref P This function is to set an output signal by a single bit When the user tries to set ili age a specified output signal to Low level write the designation number for the 41 WRO aad 20 signal to WRO register then the signal will be set to Low And
42. ach register consists of 8 bit Writing Reading Operation In order to write the data of the write register select the register by A2 A0 signal if CSN signal is Low and WRN signal is set from Low to Hi values of the data bus D7 D0 will be written in the selected register Also in order to read the data of the read register select the register by A2 A0 signal if CSN signal is Low and RDN signal is set to Low values of the read register will be output to the data bus D7 D0 For more details on read write timing please refer to chapter 8 4 2 E Write Register Address i Symbol Function A2 A1 AO 0 0 0 WRO Command Execution Bit Control Output 0 0 0 1 WR1 Bit Control Output 1 0 1 0 WR2 Data Writing Lower 0 1 1 WR3 Data Writing Upper 1 0 0 WR4 Port PA Output Value Setting 1 0 1 WR5 Port PB Output Value Setting 1 1 0 WR6 Port PC Output Value Setting 1 1 1 WR7 Port PD Output Value Setting E Read Register Address i Symbol Function A2 A1 AO 0 0 0 RRO Not used 0 0 1 RR1 Display of Interrupt Request Factor 0 1 0 RR2 Display of Reading Data Lower 0 1 1 RR3 Display of Reading Data Upper 1 0 0 RR4 Port PA Display of Real time Input Latch Input Output Input Transition i 0 1 RR5 Port PB Display of Real time Input Latch Input Output Input Transition 1 1 0 RR6 Port PC Display of Real time Input Latch Input Output Input Transition 1 1 1 RR7 Port
43. an 16MHz 3 The function of RESETN signal in independent mode When RESETN signal is low level PC PD port outputs become low level regardless of PA PB port input signals After that if RESETN signal returns to Hi level input signal levels of ports PA PB will be output to ports PC PD after a delay time of the setting time constant 4 Please note that pins for PBF3 0 are not in sequence when the user designs the pattern for the printed circuit board 39 NOVA electronics PIX132 M40 7 Examples 7 1 Connection Example for the CPU Showing a connection example of PIX132 to H8 3052 from Renesas H8 3052 PIX132 high resistance pull up From the reset circuit of the system RESETN 7 2 Example Program MExample of Setting 1 Example for setting of input 24 bit output 8 bit Port A 8 bit input integral filter disabled positive logic Port B 8 bit input integral filter enabled delay time 128 u sec negative logic Port C 8 bit input integral filter enabled upper 4 bit delay timel u sec lower 4 bit delay time 4 u sec negative logic Port D 8 bit output Initial Setting Input output setting WR2 COh PA PB PC Input PD Output and logical setting of WR3 lt 3Ch PA Positive logic PB PC Negative logic input signals WRO COh 3 Filter time constant WR2 20h Time constant 1 Delay 1 u Time constant 2 setting WR3 07h Delay 44 WRO
44. as I O device Note Please note that the GONIPBES eats Set Low level for data reading pins for PBF3 0 are not in and writing sequence Write Strobe set Low when data PA Filter Enable signal to is written in the write registers enable the integral filter of PA When WRN is Low CSN and input Hi is enable and Low is A2 A0 must be valid When disable When it is disabled PA ERATE fe ul ca es WRN is up 1 the data will be input is directly output to port latched in the write register PC without the filter D7 D0O should be valid before or after WRN up 1 Read Strobe set Low when data PB Filter Enable signal to is read out from the read enable the integral filter of PB register When CSN is set to input Hi is enable and Low is Low and RDN is set to Low the disable When it is disabled PONDERE 8 Input A data of the read register PB input is directly output to selected by A2 A0 address port PD without the filter signal is output to the data bus during RDN Low Reset reset initialize signal for Reset reset initialize signal PIX132 Setting to Low PIX132 for PIX132 When RESETN will be reset Power on reset by signal is Low outputs of port RESETN signal is necessary PC PD will be Low regardless RESETN 6 Input A After PIX132 has been reset all of input signals of port PA PB of the ports of PA PD will be input And all of mode settings are also initialized See section 2 8 17
45. e simultaneous output set command or at the timing of the transition the rising or falling edge of the OTSTB signal When 1 is set it will be enabled WR2 D1 SMO2 Simultaneous Output 2 Timer When this bit is enabled the output signal does not change even though the output value is written in WR4 5 6 and 7 registers The value written in WR4 5 6 and 7 registers will be reflected in the output signal when the timer count reaches the timer value set by the timer after starting When 1 is set it will be enabled 30 NOVA electronics PIX132 M31 WR2 D2 WR2 D3 WR2 D4 WR2 D5 WR3 D0 WR3 D1 WR3 D2 WR3 D3 Note SMI1 Simultaneous Input Latch 1 Strobe Command When this bit is enabled all the inputs are taken to the IC by simultaneous input latch command or at the timing of the transition the rising or falling edge of the INSTB signal The values taken in are kept until next input latch command or next transition of the INSTB signal When 1 is set it will be enabled SMI2 Simultaneous Input Latch 2 Timer When this bit is enabled all the inputs are taken to the IC when timer count reaches the timer value set by the timer after starting Those values are kept until next input latch When 1 is set it will be enabled OTSD Direction of OTSTB Signal Selects for use either the rising or falling edge of the OTSTB signal When 0 is set it will be the rising edge and when 1 is set it will be the falling edge INSD
46. est factor D7 D6 DS D4 D3 D2 D1 DO RR1 0 0 0 0 0 OTS INS TIM 1 Interrupt Request DO TIM indicates the time out of the timer timer count the setting value When the timer is in continuous activation timer count at the setting value D1 INS indicates the transition of INSTB signal D2 OTS indicates the transition of OTSTB signal To generate the interrupt the interrupt factor which is needed must be enabled by action mode interrupt setting command C8h in advance Once the CPU reads out all the bits of RR1 register will be cleared 22 NOVA electronics PIX132 M23 E Common Interrupt Operation When the interrupt factor enabled by action mode interrupt setting command is generated the INTN signal will go from Hi Z to Low level and 1 will be set to the proper bit of RR1 register And after reading RR1 register during interrupt processing routine in the CPU the INTN output signal will return to Hi Z and all the bits of RR1 register will be cleared to 0 Next is the same too INSTB Input Signal STR NNE SEE INTN Output signa tow rr RR1 D1 vas oo TT TT et RR1 Lead RDN Lf TT A A INSTB down J RR1 reading releases outputs INTN and INTN output and RR RR1 D1 will be 1 1 will be cleared E In the case when next factor has been generated while reading RR1 register When the interrupt generation of each factor and the timing of reading from the CPU overlaps the interrupt generat
47. figured as Rss Page input are latched by the transiti f INSTB signal be latched by writin mpu SAE TE uaa ta eo Or oan id es y 18 5 1 9 Action Mode Interrupt Setting 30 Simultaneous Input Latch Command EAh Simultaneous input latch data will 5 3 11 Simultaneous Input Latch 37 be kept until next transition of INSTB signal or simultaneous input latch command EAh are written If WR3 D1 bit is set to 1 by action mode interrupt setting command an interruption can be generated by the transition of INSTB signal 12 NOVA electronics PIX132 M13 Note1 Depending on the level of the INSTB signal data may be latched at the writing of action mode interrupt setting command C8h For instance when INSTB signal goes Hi and action mode interrupt setting command C8h is written at the rising edge data will also be latched at the time of the command writing Note2 After latched by the transition of the INSTB signal the next latch is not performed for a maximum of 4CLK cycles even though INSTB signal alters 2 Latch by Timer PIX132 is equipped with a built in timer which can set within the range from 1 sec to 32sec All the input signals are simultaneously latched at the time out of the timer The timer can be operated by single activation command or continuous activation command which repeatedly operates until the CPU stops it In continuous activation command Input values are latched every time out The procedures for simultaneous
48. fy the direction of the transition whether to trap the input value from 0 to Setting R 1 or from 1 to 0 for each input signal 5 1 6 PCD Input Transition Enabling Enable Disable can be set by PAB Input Transition Enabling Command or PCD Setting me Input Transition Enabling Command And the direction of the transition can be 5 1 7 PAB Input Transition Direction set by PAB Input Transition Direction Command or PCD Input Transition Setting es Direction Command 5 1 8 PCD Input Transition Direction di Setting 2 Transition Trapping Behavior Regarding the signal enabled by Input Transition Enabling Command the transition trapping function is immediately operated When an input value goes to the specified direction the input transition becomes 1 This 1 is kept until the register corresponding to the input signal is read out even though the transition of the input signal occurs repeatedly 3 Reading Input Transition Input transition information can be read from RR4 5 6 and 7 registers At this Reference Page time RR4 5 6 and 7 registers should display Input Transition so write Read 5 3 10 Read Register Display Register Display Selecting 5 Command E9h in advance to switch RR4 5 6 Selecting 5 and 7 registers to a display Input Transition 4 7 RR4 5 6 7 Register 23 Input transition information will be cleared once read out 4 Clearing Transition Information Input transition informat
49. g Time 23 ns In case simultaneous input latch is performed by the command EAh the above time values are based on the point of CLK 1 which passes one or two cycles after WRN of the command writing In case simultaneous input latch is performed by the timer the above time values are based on the point of CLK at the time out 8 2 10 Simultaneous Output Set Delay Time The figure on the lower right side shows the delay time when the port output signal is set at the rising falling edge of OTSTB signal during simultaneous output set operation 1 VDD 5 0V 10 PB PC Port Output Delay OTSTB Time PA PD Port Output Delay PB 7 0 PC 7 0 Time 2 VDD 3 3V 10 PA 7 0 PD 7 0 PB PC Port Output Delay Time PA PD Port Output Delay Time To avoid malfunction by simultaneous switching outputs of ports PA PD are delayed about 7nsec 5V typ value from those of ports PB PC In case simultaneous output set is performed by the command EBh the above time values are based on the point of CLK 1 which passes one or two cycles after WRN of the command writing In case simultaneous output set is performed by the timer the above time values are based on the point of CLK at the time out 48 NOVA electronics 8 2 11 Interrupt Delay Time 1 VDD 5 0V 10 INSTB Interrupt Delay Time OTSTB Interrupt Delay Time Input Transition Interrupt Delay Time tcyc 40
50. garding all the input signals the user can specify the filter time constant from three types for 4 bit ports respectively by WR2 3 registers D7 D6 DS D4 D3 D2 D1 DO WR2 PBH PBL PAH PAL Designation Designation Designation Designation D7 D6 D5 D4 D3 D2 D1 DO WR3 PDH PDL PCH PCL Designation Designation Designation Designation Designation Value Filter Behavi Upper Lower Bits ilter Behavior 0 0 Without filter 0 1 Set the filter time constant 1 1 0 Set the filter time constant 2 1 1 Set the filter time constant 3 H indicates upper 4 bit ports and L indicates lower 4 bit ports Set 00 to the signal configured as output because its filter function does not work At resetting all the input ports will be without filter Notes on switching designation While the filter is disabled filter calculation of the IC stops so that input values before disabling will be read out for a maximum of the filter delay time when the filter is switched from disabling to enabling 5 1 3 Filter Time Constant Setting Code Command Function Filter Time Constant C2 Setting Sets the value for filter time constant 1 2 and 3 PIX132 has three types of filter time constants Each filter time constant can select a setting value from 16 values Write the setting value shown in the below list to specified 4 bit of the time constant of WR2
51. hen 1 is set it traps the transition from 1 to 0 D7 D6 DS D4 D3 D2 D1 DO WR2 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO 0 Transition of the input value from 0 to 1 1 Transition of the input value from 1 to 0 D7 D6 DS D4 D3 D2 D1 DO WR3 PD7 PD6 PDS PD4 PD3 PD2 PD1 PDO Note If the direction of the transition is changed by this command after setting Input Transition Enabling Setting input transition may be 1 due to the change Clear the transition information by E4h command after writing this command 5 1 9 Action Mode Interrupt Setting Code Command Function C8 Action Mode Interrupt Sets simultaneous input latch simultaneous output set the Setting direction of strobe signal and interrupt generation The user can enable disable each action mode by WR2 register and each interrupt by WR3 register D7 D6 D5 D4 D3 D2 D1 DO WR2 0 0 INSD OTSD SMI2 SMI SMO2 SMO1 0 Disable 1 Enable Action Mode Setting D7 D6 D5 D4 D3 D2 D1 DO WR3 0 0 0 0 TRN OTS INS TIM 0 Disable 1 Enable Interrupt Setting WR2 D0 SMO1 Simultaneous Output 1 Strobe Command When this simultaneous output bit is enabled the output signal does not change even though the output value is written in WR4 5 6 and 7 registers The value written in WR4 5 6 and 7 registers will be reflected in the output signal by writing th
52. igh impedance because it is not pulled up with high resistance in the IC Pull up signals which are not used with high resistance to VDD or pull down to GND Concerning data signals D7 D0O the user should pull up the data bus with high resistance for signal line not to attain high impedance Output side is CMOS level output 8mA driving buffer at VDD 5V High level output current IOH 8mA VOH 2 4Vmin Low level output current IOL 8mA VOL 0 4Vmax and 4mA driving buffer at VDD 3 3V Hi level output current IOH 4mA VOH 2 4Vmin Low level output current IOL 4mA VOL 0 44Vmax The same circuit as bi directional A but uses input only Input side is TTL Smith trigger which is high impedance because it is not pulled up with high registance in the IC When IMODEN is Low independent mode INTN TEST signal must be connected to GND or the internal test circuit will be activated and the OTSTB OEN signal will be output ign Circuitry Processing of GND VDD Terminals Make sure that all of GND and VDD terminals are each connected to the ground pattern and the power pattern on the substrate De coupling Capacitor Please connect VDD and GND with two to four De coupling capacitors about 0 1 u F 19 NOVA electronics PIX132 M20 4 Register This chapter indicates to the user how to access all the registers in PIX132 and what the mapping addresses are of these registers Both read and write registers have eight registers respectively and e
53. input latch by the timer are shown as follows OD Set 1 to WR2 D3 bit by mode interrupt setting command Also set 1 to WR3 D0 bit if you need to generate the interrupt by the time out Reference Page Set the timer value 5 1 9 Action Mode Interrupt Setting 30 Activate the timer by single activation command or continuous activation 5 1 4 Timer Value Setting 28 command 5 3 1 Timer Single Activation 35 Confirm the time out by reading the activated timer value or the interrupt 5 3 2 Timer Continuous Activation 35 generation When confirming by the interrupt generation the user can 5 2 3 Activated Timer Value Reading 34 validate the interruption from the timer by RR1 D0 bit INTN signal will 45 RRI Register 22 be released by reading RR1 D0 1 3 Reading Latched Input Value Latched input value can be read from RR4 5 6 and 7 registers At this time Reference Page RR4 5 6 and 7 registers should display Latch Input so write Read Register 5 3 8 Read Register Display Display Selecting 3 Command E7h in advance to switch RR4 5 6 and 7 Selecting 3 registers to a display Latch Input 4 7 RR4 5 6 7 Register 23 2 3 Input Transition Trapping Function This function is to trap the transition of input signals concerning all of the input signals 1 Setting Reference Page Configure whether to enable or disable the transition trapping function and 5 1 5 PAB Input Transition Enabling speci
54. ion of each register is cleared by reading RR4 7 Reference Page registers Or it can be cleared for all the registers by command 5 3 5 Input Transition Information 35 Clear Note This function is activated by clock CLK synchronization Even without the filter if the input transition occurs in less time than CLK cycle it may fail to be trapped 13 NOVA electronics PIX132 M14 2 4 Simultaneous Output Set This function is to set all of the output signals in PA PD ports simultaneously To set the output simultaneously there are three ways strobe signal commands and the timer The user can specify which way is to be used by action mode interrupt setting command 1 Simultaneous Output by Strobe Signal or Commands To perform simultaneous output set by a strobe signal OTSTB or commands set 1 to WR2 D0 Simultaneous Output 1 bit by action mode interrupt setting command and specify either the rising edge or falling edge of the strobe signal OTSTB by WR2 D4 bit If WR2 D0 Simultaneous Output 1 bit is set to 1 and action mode interrupt 4 i 5 ne Reference Page setting command is written then output signals cannot be changed by writing the output value in WR4 5 6 and 7 registers Write the output value to all of Se AS one eee WR4 5 6 and 7 registers and then make the strobe signal OTSTB change or ssl Simultaneous Quiput Set al write simultaneous output set command all the output signals will be
55. ion will be held internally until reading is finished so PIX132 does not miss next interrupt generation by reading INSTENInput Signal al U Kept low due to occurrence of next factor INTN Output soa mH ow tow RRVUD1Vaue__0 J Tiri TLE RRiLeadRDN SL LL OM L E In the case when next factor has been generated ahead of reading RR1 register after an interruption occurred When the same factor has been generated again ahead of reading RR1 after an interruption occurs this interrupt generation is ignored This generation of the factor is ignored INSTB Input so INTN Output soa TZ w ss RR1 D1 Value___0 1 RRI LeaRIN L AES 4 6 RR2 3 Register Display of Reading Data RR2 3 resigsters are used to set the data of commands for reading data Writing the command code to WRO register the data corresponding to the command will be set from the internal circuits to RR2 3 registers When the data is a 2 byte length low byte data will be set to RR2 register and high byte data will be set to RR3 register When the data is a 1 byte length data will be set to RR2 register and 0 will be set to RR3 register D7 D6 DS D4 D3 D2 D1 DO RR2 Low byte of Reading Data D7 D6 D5 D4 D3 D2 D1 DO RR3 High byte of Reading Data 4 7 RR4 5 6 7 Register Display of Real time Input Latch Input Output Input Transition RR4 5 6 and 7 registers are used to display input
56. ition once the RC elements are soldered the time constant will be fixed On the other hand the built in integral filter of this IC can alter delay time from 1 u sec to 32msec at CLK 16MHz any time depending on the circumstances of the noise Sampling Period ese Input Si gnal Acc umulation Thres hdd Level Output Si gnal Filter Delay Time Fig 1 4 Operation of Digital Integral Filter Simultaneous Input Latch This function is to latch all the input signals of port PA PD simultaneously in the following three ways The user can specify which way is to be used by action mode setting command Strobe Signal Latch at the rising falling edge of the external signal INSTB The rising or falling can be selected by action mode setting command Command Latch by writing the command EAh from CPU to WRO register Timer Latch at the time out of the timer The latched input information can be read out from RR4 7 registers However when RR4 7 registers are displaying other information the latched input information can be read out after writing the command E7h Input Transition Trapping Function This function is to trap the transition of input signals The transition of the input value from 0 to 1 or from 1 to 0 can be trapped concerning specified inputs It is effective to monitor the rare transition of a signal or unexpected impulse noise that mixes with a signal The user can specify the signal and the direction of the transitio
57. ly set all of the output signals of each port PA PD by setting action mode As shown in Fig 1 7 if the simultaneous output mode is set then the output data of port PA which is written in WR4 register is temporarily latched and not outputted to port PA yet Also values written in WRS 6 and 7 registers are not reflected immediately and they are temporarily latched Writing PA output vane LUUN WR4 hd on 11111111 Writing PB output value WR5 v Writing PC output value 01010101 WRG ai 14111111 Writing PD output value gt WR7 hd i i Eternal Signal All outputs are set simultaneously Writing the command EB Command Timer Fig 1 7 Simultaneous Output Set To output data simultaneously from output ports after writing output values in WR4 5 6 and 7 registers there are the following three ways Strobe Signal Output at the rising falling edge of the external signals OTSTB The rising or falling can be selected by action mode setting command Command Output by writing the command EBh from CPU to WRO register Timer Output at the time out of the timer Note In a customer system when the user tries to control switching on off of a large current simultaneously with this function it is necessary to take preventive measures that minimize the voltage fluctuation of GND Power or Cross talk between the signals which are generated by simultaneous switching of a large current NOVA electronics PIX132 M10 Bit Control Output
58. n 0 to 1 1 to 0 by the bit Input Value 0 f 1 0 Input Value 1 0 1 y Y Trapping of 0 1 Trapping of 0 1 Transition Transition Trap the transition of input value from 0 to 1 Trap the transition of input value from 1 to O Fig 1 5 Operation of Input Transition Trapping The input transition information can be read out from RR4 7 registers However when RR4 7 registers are displaying other information the input transition information can be read out after writing the command E9h Once input transition information is read out it will be cleared This function is activated by clock CLK synchronization If the input transition occurs in less time than CLK cycle it may fail to be trapped NOVA electronics PIX132 M9 Simultaneous Output Set Normally writing the signal value 0 Low and 1 Hi designated for output to WR4 5 6 and 7 registers will be set to each 8 bit output port Thus as shown in Fig 1 6 when the user tries to set all of the ports PA PD in the usual way the output set is delayed by each port because a time difference occurs at the time of writing to each port PA PD from the CPU PAO Writing PA output value aN WR4 sg P Ag PBO ma 11111111 Writing PB output value WR5 Output p7 bd 0101010 Buffer P Writing PC output value 1I WRG P67 hd PRO ii 11111111 Writing PD output value gt WR7 pi Delayed by each port Fig 1 6 Normal Output Set This IC can perform to simultaneous
59. nformation is displayed in the current RR4 5 6 and 7 registers Executing this command the user can find the current display status by bit D2 D0 of RR2 register D7 D6 D5 D 4 D3 D2 D1 DO RR2 0 0 0 0 0 Display status of RR4 5 6 7 33 NOVA electronics PIX132 M34 Value of D2 1 0 The current display status of RR4 5 6 7 000 Real time input output 001 Real time input 010 Latch input 011 Output 100 Input transition 5 2 3 Activated Timer Value Reading Code Command Function DA Activated Timer Value Reads the value of currently activated timer Reading Writing this command to WRO register the value of currently activated timer is set to RR2 3 registers RR2 is for low byte data and RR3 is for high byte data A unit of time is displayed in bit D7 of RR3 at CLK 16MHz D7 D6 DS D4 D3 D2 D1 DO RR2 Low byte D7 D6 D5 D4 D3 D2 D1 DO RR3 High byte 0 Usec 1 msec While the timer stops 0 is displayed 34 NOVA electronics PIX132 M35 5 3 Other Commands Other commands are executed by writing the command code to WRO 5 3 1 Timer Single Activation Code Command Function E0 Timer Single Activation Activates the timer with single activation Writing this command the timer starts to count up from 0 When the counter reaches the timer setting value the value set by C3h command
60. ote In case rotary SW is connected as shown in Fig 1 10 setting signal of the time constant must be pulled up with high resistance Fig 1 10 Independent Mode Operation Time Constant Setting Filter time constant of low byte for port PA PA 3 0 can be configured by 4 bit input signals PALF 3 0 and high byte for port PA PA 7 4 can be configured by 4 bit input signals PAHF 3 0 and also port PB PB 7 0 can be configured by 4 bit input signal PBF 3 0 Each filter time constant can be set by specifying Hi Low level of setting input signals as shown below Level of setting input signal Level of setting input signal PALF3 PALF2 PALF1 PALFO Signal Delay Time PALF3 PALF2 PALF1 PALFO Signal Delay Time PAHF3 PAHF2 PAHF1 PAHFO at CLK 16MHz PAHF3 PAHF2 PAHF1 PAHFO at CLK 16MHz PBF3 PBF2 PBF1 PBFO PBF3 PBF2 PBF1 PBFO Low Low Low Low 1 usec Hi Low Low Low 0 256 msec Low Low Low Hi 2 usec Hi Low Low Hi 0 512 msec Low Low Hi Low 4 usec Hi Low Hi Low 1 02 msec Low Low Hi Hi 8 usec Hi Low Hi Hi 2 05 msec Low Hi Low Low 16 usec Hi Hi Low Low 4 10 msec Low Hi Low Hi 32 usec Hi Hi Low Hi 8 19 msec Low Hi Hi Low 64 usec Hi Hi Hi Low 16 4 msec Low Hi Hi Hi 128 usec Hi Hi Hi Hi 32 8 msec Signal delay time shows the standard value It fluctuates within a range from standard value X 0 875 standard value 80Onsec 38 NOVA electronics PIX13
61. r out MExample of Setting 4 Example for input transition Monitors 32 bit of all the input transition and if any of inputs change then generates an interruption to the CPU Initial Setting Input output setting WR2 00h PA PB PC PD All inputs and logical setting of WR3 00h Set the logical level for input signal input signals WRO COh 0 Low 1 Hi PA PB direction WR2 00h 0 1 Traps the transition setting WR3 00h WRO C6h PC PD direction WR2 00h 0 1 Traps the transition setting WR3 00h WRO C7h PA PB enabling WR2 lt FFh setting WR3 lt FFh WRO C4h PC PD enabling WR2 lt FFh setting WR3 lt FFh WRO C5h Read register display WRO E9h RR4 7 Display the input transition Input transition WRO E4h Initial Clear information clear Interrupt setting WR2 00h WR3 08h Enables input transition interrupt WRO C8h Interrupt RR4 PAtransition value Altering signal shows 1 Transition Transaction RR5 PB transition value information is cleared once it is read out RR6 PC transition value INTN signal is released when all of the RR7 PD transition value altering signals are read out 42 NOVA electronics PIX132 M43 7 3 Connection Example for Independent Mode yvyyyyyy Laa ka kaa La La gt Lag 5V Low Active Rotary SW Complementary Type 987 Ex
62. rations To enable each interrupt generation specify it by action mode interrupt setting command 2 8 Time out of the timer Transition of INSTB signal at the simultaneous input latch Reference Page 5 1 9 Action Mode Interrupt Setting 30 Transition of OTSTB signal at the simultaneous output set Input Transition Status at Reset At resetting each configurable operation in slave mode of this IC is shown as follows Operation Port PA PD Input Output Status at Reset Related Commands All the signals are Input Designation of Input Output Port PA PD Input Logic All the signals are 0 Hito 1 and Logical Setting Port PA PD Filter Designation Filter Time Constant 1 2 3 All the signals are without filter All of 1 2 3 is 0 Delay Time 1 u Input Filter Designation Filter Time Constant Setting Timer Value PAB PCD Input Transition Enabling Disabling 0 Timer Value Setting PAB PCD Input Transition Enabling Setting All the signals are disabled PAB PCD Input Transition Direction All the signals are 0 Transition of input value from 0 to 1 PAB PCD Input Transition Direction Setting Simultaneous Output 1 Disable Strobe Commands Simultaneous Output 2 Timer Disable Simultaneous Input Latch 1 Disable Strobe Commands Simultaneous Input Latch 2 Timer Disable OTSTB Direction 0 the rising edge INSTB Direction Action Mode Interrup
63. s activated by the timer continuous activation command There is no need to write this command for timer single activation 5 3 5 Input Transition Information Clear Code Command Function Input Transition Clears all the input transition information when RR4 5 6 and 7 E4 i roe A ee Information Clear registers indicate the display of input transition The user can get input transition information by reading RR4 5 6 and 7 registers when these registers display input transition After reading each register transition information will be cleared by the register by the port 39 NOVA electronics PIX132 M36 This command clears the transition information of all the ports This command is enabled when RR4 5 6 and 7 registers indicate a display input transition so when indicating other states this command does not clear anything 5 3 6 Read Register Display Selecting 1 Real time Input Output Code Command Function E5 Read Register Display Makes RR4 5 6 and 7 registers display real time input Selecting 1 output Five kinds of information can be displayed in RR4 5 6 and 7 registers by switching them When writing this command real time input output is displayed The user does not need to write this command for every reading of RR4 5 6 and 7 registers This display selection is enabled until next E5 E9h command is written For more details on RR4 5 6 and 7
64. t Latch WR3 D1 1 Transition of OTSTB Input Signal at the Simultaneous Output Set Input Transition C8h Command WR2 D0 1 and WR3 D2 1 C8h Command WR3 D3 1 RR1 D2 1 indicates occurrence RR4 5 6 7 1 indicates occurrence Note1 same as above Released automatically by reading RR4 7 registers which have the input transition occurrence Notel It is necessary to write E9h command Read Register Display Selecting 5 in advance 32 NOVA electronics 5 2 Commands for Reading Data PIX132 M33 Commands for reading data can be performed by writing the command code to WRO which sets reading data to RR2 3 If the data is a l byte length the data will be set to RR2 register and RR3 high byte will be 0 It can read out all the data by commands for reading data set in the IC by commands for data writing 5 2 1 Reading Setting Data Commands for reading of DO D8 is in order to read the data already set by commands for writing of CO C8 to RR2 RR3 resigsters The data displayed in RR2 3 registers after executing commands for reading is the same as the value which is written in WR2 3 by commands for writing please refer to corresponding commands for data writing Corresponding Code Commands for Reading Function Commands for Writing DO Input output designation and logical Displays the current input output designation and co setting reading input logic setting in RR2
65. t Setting 0 the rising edge Interrupt by Timer Disable Interrupt by Simultaneous Input Latch Disable INSTB Signal Interrupt by Simultaneous Output OTSTB Disable Signal Interrupt by Input Transition Disable 15 NOVA electronics 3 Pin Assignments and Signal Description 3 1 Pin Assignments VDD GND PA5 PA4 PA3 PA2 PAI PAO GND CLK VDD I MODEN D7 PAHF3 D6 PAHF2 D5 PAHF1 D4 PAHFO PAG gt PAT gt PBO gt PBI gt PB2 gt PB3 gt PB4 gt PB5 D3 PALF3 D2 PALF2 5 Glossy circle D1 PALF1 DO PALFO GND VDD gt PB6 gt PB7 gt PCO gt PCI gt PC2 gt PC3 NOVA elec P X132 _Index Mark VDD RESETN GND A2 PBF2 A1 PBF1 A0 PBFO CSN PBF3 WRN PAFE RDN PBFE INTN TEST INSTB HLDN OTSTB OEN GND VDD gt PC4 gt PCS gt PC6 gt PC7 gt PDO gt PDI gt PD2 GND VDD gt PD3 gt PD4 gt PDS gt PD6 PD7 PIX132 M16 64 pin TQFP package external package 12 X 12mm lead pitch 0 5mm lead free See Chapter 9 for the package dimensions 16 NOVA electronics 3 2 Signal Description Pin Input Output PIX132 M17 See section 3 3 for Input Output in the table Signal Description Signal Name 9 Number Slave Mode Independent Mode Clock clock signal for internal synchronous circuits of PIX132 The standard frequency is 16MHz which the filter time constant or
66. t Transition Enabling Setting Code Command Function PAB Input Transition Enables the input transition trapping for each input of ports PA C4 i j Enabling Setting PB Set enable disable of the input of PA 7 0 to WR2 register and the input of PB 7 0 to WR3 register When 0 is set it is disabled and when 1 is set it is enabled Only the enabled input can trap the transition Each input can be specified as to which transition of the input value to be trapped from 0 to 1 or 1 to 0 by PAB Input Transition Direction Setting Command C6h D7 D6 D5 D4 D3 D2 D1 DO WR2 PA7 PA6 PAS PA4 PA3 PA2 PAI PAO 0 Disable 1 Enable D7 D6 D5 D4 D3 D2 D1 DO WR3 PB7 PB6 PBS PB4 PB3 PB2 PB1 PBO 5 1 6 PCD Input Transition Enabling Setting Code Command Function C5 PCD Input Transition Enables the input transition trapping for each input of ports PC Enabling Setting PD Set enable disable of the input of PA 7 0 to WR2 register and the input of PB 7 0 to WR3 register When 0 is set it is disabled and when 1 is set it is enabled Only the enabled input can trap the transition Each input can be specified as to which transition of the input value is to be trapped from 0 to 1 or 1 to 0 by PCD Input Transition Direction Setting Command C7h D7 D6 DS D4 D3 D2 D1 DO WR2 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO 0 Disable 1 Enable D7 D6 D5 D4 D3 D2 D1 DO WR3 PD7 PD6 PDS PD4 P
67. t ports and L indicates lower 4 bit ports and it is defined by 0 input and 1 output For instance when DO is set to 0 ports PA3 PA2 PAI and PAO will be configured as input and when D1 is set to 1 ports PA7 PA6 PAS and PA4 will be configured as output Also concerning D2 to D7 bits Port PB to PD can be configured as input output by each 4 bit port Logical level of each input signal can be configured for 4 bit ports respectively H indicates upper 4 bit ports and L indicates lower 4 bit ports and it is defined by 0 High of input signal to input value 1 and 1 Low of input signal to input value 1 It does not matter whether 0 or 1 is for the signals which are designated output This selection of logical level does not function for output D7 D6 D5 D4 D3 D2 D1 DO WR2 PDH PDL PCH PCL PBH PBL PAH PAL 0 Input 1 Output Input Output Designation D7 D6 D5 D4 D3 D2 D1 DO WR3 PDH PDL PCH PCL PBH PBL PAH PAL 0 Hi to Input Value 1 1 Low to Input Value 1 Logical Setting of Input Signal At resetting all the ports will be input mode and Hi level of input signals will be input value 1 5 1 2 Input Filter Designation Code Command Function C1 Input Filter Designation Specifies the time constant of the integral filter for input signals 26 NOVA electronics PIX132 M27 to each 4 bit input port Re
68. terrupt Setting 5 2 Commands for Reading Data 5 2 1 5 2 2 5 2 3 Reading Setting Data Read Register Display Status Reading Activated Timer Value Reading 5 3 Other Commands 5 3 1 5 3 2 5 3 3 5 3 4 5 3 5 5 3 6 5 3 7 5 3 8 5 3 9 5 3 10 5 3 11 5 3 12 Timer Single Activation Timer Continuous Activation Timer Stop Timer Cycle Stop Input Transition Information Clear Read Register Display Selecting 1 Real time Input Output Read Register Display Selecting 2 Real time Input Read Register Display Selecting 3 Latch Input Read Register Display Selecting 4 Output Read Register Display Selecting 5 Input Transition Simultaneous Input Latch Simultaneous Output Set 6 Independent Mode 7 Examples 7 1 Connection Example for the CPU 7 2 Example Program 7 3 Connection Example for Independent Mode 8 Electrical Characteristics 8 1 DC Characteristics 8 2 AC Characteristics 8 2 1 8 2 2 8 2 3 8 2 4 8 2 5 8 2 6 8 2 7 8 2 8 8 2 9 8 2 10 Measuring Condition Clock Reset Signal Width CPU Read Write Cycle Port Input Delay Time Port Output Delay Time Bit Control Output Delay Time Strobe Signal Width Simultaneous Input Latch Timing Simultaneous Output Set Delay Time PIX132 M4 26 26 27 28 29 29 29 30 30 33 33 33 34 35 35 35 35 35 35 36 36 36 36 37 37 37 38 40 40 40 43 44 44 45 45
69. these information inputs from RR4 to 7 registers RR4 7 registers are 8 bit configurations respectively corresponding to RR4 PA 7 0 RR5 PB 7 0 RR6 PC 7 0 RR7 PD 7 0 RR4 7 registers display not only with real time inputs but also latch inputs and input transition These information inputs are switched by the command E5 E9h Output Signal Setting As shown in Fig 1 3 output signals can be set by the following three ways when each I O port is designated for output Register Data Writing Writing output data in WR4 5 6 and 7 registers output is set by the 8 bit ports PA PB PC and PD Bit Control Output Writing the assigned number corresponding to the output signal output is set by a single bit Simultaneous Output Writing output data in WR4 5 6 and 7 registers in advance all outputs are simultaneously set at the timing of external strobe signal command writing from the CPU and time out of the timer NOVA electronics PIX132 M8 Digital Integral Filter The PIX132 is equipped with a digital integral filter for each input signal of port PA PD This filter takes samplings of input signal level at the designated period and then outputs the accumulation of value to the back It provides the function that removes impulse noise which is almost the same performance as the integral filter composed of RC Resistance Capacitor elements See appendix B and can reduce the space on the circuit board for RC elements and cost In add
70. torn damaging the airtightness 2 Store the IC under the temperature 40 C or lower and humidity 85 RH or lower with damp proof package and use the IC within 12 months 3 If the IC usage date has expired remove any dampness by baking it under the temperature 125 C 5 C for 24 hours The baking counts are up to five times If damp proofing is damaged before expiration apply damp removal processing also 4 Apply device corruption prevention using static electricity before applying dampness removal processing 5 After opening the damp proof package store the IC under 5 30 C and aver 30 60 RH per day and install it within seven days Make sure that baking processing is applied before installation of the IC that is left in the storage for a time that exceeds the expiration period as indicated above 10 2 Standard Installation Conditions by Soldering Iron The standard installation conditions for the IC by soldering iron are as follows 1 Installation method Soldering iron heating the lead section only 2 Installation conditions a 380 C for 5 seconds or less b 260 C for 10 seconds or less 10 3 Standard Installation Conditions by Solder Reflow The standard installation conditions for the IC by solder reflow are as follows 1 Installation method Far middle infrared solder reflow 2 Preheating conditions 150 190 C for 60 80 seconds 3 Solder reflow conditions a 255 260 C for 10 seconds or less b 220 C
71. y Selecting 3 Command E7h 5 3 12 Simultaneous Output Set Code Command Function Outputs the data written in WR4 5 6 and 7 registers as output signal simultaneously EB Simultaneous Output Set When writing this command the output data written in WR4 5 6 and 7 registers can be simultaneously set as output signal of each port The DO bit of WR2 simultaneous output 1 must be set to 1 enable by action mode interrupt setting command C8h in advance 37 NOVA electronics PIX132 M38 6 Independent Mode PIX132 can be operated in independent mode when IMODEN input signal is set to low In independent mode as shown in Fig 1 10 ports PA PB are fixed input mode and these input signals are output to ports PC PD respectively through the integral filter There are 3 types of time constants for the integral filter low byte signal of port PA high byte signal of port PA and port PB and these ports are each configurable for a different time constant To set the time constant 4 bit input signals are prepared respectively The delay time can be set within the range from 1 u sec 32msec at CLK 16MHz in 16 levels mememe mememe meas JJJ er JJJ WOOHOO AAT SE VVV VVVVUVUU WDOWWDWWWW YOON nr PA Filter Enable Disable PAFE PB Filter Enable Disable PBFE HLDN Hol d on OEN Output Enable Time Constant Time Constanti RESETN IMODEN A P EN C tD 14 32msec at CLK 16MHz A N
72. y selecting 5 37 Input transition EA Simultaneous input latch 37 EB Simultaneous output set 37 25 NOVA electronics PIX132 M26 Notes for the timing of writing commands This IC needs a time more than 2CLK cycles to proceed with the command After writing the command in the IC be sure to access for the next one after taking a time interval of more than 2CLK cycles When CLK 16MHz it will be 125nsec Command Writing Next command Writing Data Writing Reading data command Data Reading D 2x tcyc and over 2x tcyc and over Fig 5 1 PIX132 Access Timing Reading data 2x tcyc and over 5 1 Commands for Data Writing Commands for data writing can be executed by writing the command code to WRO after writing the data to WR2 WR3 WR2 is for low byte data and WR3 is for high byte data If the data is a 1 byte length the user only writes the data to WR2 and no need to write 0 to WR3 This IC can read out all the data by commands for reading data which is set in the IC by commands for data writing 5 1 1 Input Output Designation and Logical Setting Code Command Function Input output signals can be configured as input output with each Input Output Designation 4 bit port and Logical Setting Logical level for input signals can be set for 4 bit ports respectively co Each port can be configured as input or output by setting DO D7 bits of WR2 register H indicates upper 4 bi

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