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CM7000 Series - Digi International

1. 6 7 5 8 ssl gt Figure F 5 Prototyping Area Each power rail consists of alternating m power and ground pads The ground pads are square see Figure F 6 Hr Figure F 7 shows how to solder in various DIPs near the power and ground pads Figure F 6 Prototyping Board Power and Ground Bads 1 Figure F 7 Soldering DIPs to Power and Ground Pads CM7000 Prototyping Board 113 Reset The Prototyping Board has a reset button SWI that is used to restart the entire system on the Protoyping Board The CM7000 s ADM691 supervi sor will also generate a reset when the regulated 5 V goes
2. 4 RTC trou E 00000007002 jj Ut Break trace to H3 EPROM FI write protect 1 2 H1 Figure D 1 Location of CM7100 Write Protect Trace 102 EEPROM CM7000 Library Routines The following library routines can be used to read and write the EEPROM int ee rd int address int ee wr int address byte data The function ee rd returns a data value or if a hardware failure occurred The function ee wr returns 1 if a hardware failure occurred 2 if an attempt was made to write to the upper 256 bytes with the write protect trace cut enabled or 0 to indicate a successful write A write protection violation does not wear out the EEPROM These routines each require about 2 ms to execute They are not re entrant that is only one routine at a time will run The EEPROM has a rated lifetime of only 10 000 writes unlimited reads Do not write the EEPROM from within loop The EEPROM should be written to only in response to a human request for each write CM7000 EEPROM 103 Blank 104 EEPROM CM7000 APPENDIX E SERIAL INTERFACE BoARD 2 Appendix E provides technical details and baud rate configuration data for Z World s Serial Interface Board 2 SIB2 CM7000 Serial Interface Board 2 105 Introduction The Serial Interface Board 2 SI
3. 47 10 pF 0 1 171019 1 Figure J 1 Analog to Digital Converter Circuit The 12 bit A D converter chip is a Linear Technology LTC1294 It can be programmed to convert a signal at one of its inputs in either 12 bit unipolar or 11 bit sign bipolar mode Its 8 channels be configured as either eight single ended inputs or four differential inputs The LTC1294 s reference voltage comes from the precision 2 5 V voltage reference LT1019 The input reference and supply voltages to the LTC1294 must be free of noise and ripple Two input amplifier circuits perform signal conditioning The first circuit shown in Figure J 2 uses a high precision instrumentation amplifier LT1101 with selectable gain 10 or 100 5VA 5 gt ZA 3 to 1294 channel 5 m 6 171101 Figure J 2 High Precision Amplifier for A D Converter 140 Sample Applications CM7000 The other amplifier circuit shown in Figure 1 3 is a difference amplifier with a predetermined offset of 2 5 V INPUT to 1294 channel 2 5V R3 10 kQ R4 100 kQ Figure J 3 Difference Amplifier for A D Converter The gain equation 18 1 1 Vour g UNPUT 25 V 1 1 assuming R2 R3 and R4 The analog input voltage range is 0 V to 2 5 V unipolar and 2 5 V to 2 5 V bipolar Software controls the LTC1294 by writing to one of three CS4 addresses The addressable
4. Power Jack J SmartCore Evaluation Board D Reset o H2 n m HEHBEBEBHBH Configuration D C Q Jumpers 4 50000 1 Programming of 7000 zo H3 connector cmo location Serial Port Lt Battery H5 UY ys 0000000000000000 0000000000000000 swa LED 3 0000000000000000000000000000000000 0O0000000000000000000000000000000000 Form 0000000000000000000000000000000000 LEDS 0000000000000000000000000000000000 0000000000000000000000000000000000 SW4 e i 0000000000000000000000000000000000 NS 0000000000000000000000000000000000 6 LEDS le 0000000000000000000000000000000000 0000000000000000000000000000000000 46 0000000000000000000000000000000000 7 48 0000000000000000000000000000000000 49 0000000000000000000000000000000000 0000000000000000000000000000000000
5. 48 49 Prototyping Board 119 120 21 24 27 00 42 43 Prototyping Board 117 119 14 Prototyping Board 119 J5 Prototyping Board 111 J6 Prototyping Board des 22 23 117 118 119 J7 Prototyping Board 117 118 119 J8 Prototyping Board 117 118 119 J9 Prorotyping Board 119 Prototyping Board 23 117 118 119 CM U 30 32 Development Board 25 25 ee AI 25 jump vectors 100 jumper settings CM7100 21 24 27 EPROM size 25 42 43 Development Board EUR 23 25 27 123 Prototyping Board 23 117 120 154 Index 161 120 sense LINES 119 keypad connections 127 L LCD Keypad module 126 127 128 129 connections 127 keypad driver 129 keypad sense lines 129 LCD driver 128 mounting holes 126 sample programs 155 156 SOMWALE nee tme 128 LEDs Prototyping Board 120 liquid crystal display See LCD literal C term USE 84 ENDA
6. Capacitance Resistance 5 Vload Charge Time Backup Time F Q mA to 98 4 9 V to 2 0 V 0 00047 220 23 dig 0 1 1000 5 6 67 min 20h 0 25 510 10 8 5 50h 05 510 10 17 min 100 h 10 220 23 15 min 200 h 3 3 220 23 49 27d Current for a load at 5 V at initial power up The current will decrease as the capacitor charges up backup time at a discharge of 4 uA with RAM and Connect VBAT to ground if there is no backup circuit This connection prevents on the ADM691 from floating which could cause the switchover circuitry to malfunction 54 System Development CM7000 System Reset The RESET line located on pin 6 of header H2 connects directly to the CPU and synchronizes external devices When the ADM691 chip is present it drives the RESET line The RESET line is not pulled up internally The interface circuitry must manage this line if the ADM691 chip 1s not installed The CM7000 Prototyping Board provides a 10 pull up resistor on this line AY See Chapter 4 Design Considerations for more information about power on and reset management CM7000 System Development 55 Serial Communication Two serial channels support asynchronous communication at baud rates from 300 bps to 57 600 bps 115 200 bps with the 18 432 MHz cores Serial communication provides a simple and robust means for networking
7. 15 execution times 93 external clock 63 F 66 67 14 160 Index filter power supply 150 five key system 129 flash 45 Flash Programmer ns 132 133 134 135 136 BIOS 3 fester 136 CM7100 compatibility 137 copying applications to CM7200 flash EPROM 132 DIP switches 134 135 EPROM 133 operating procedure 135 spring pin 6 136 troubleshooting 137 ZIF socket 135 float 7 84 framing 2 222 422 66 frequency system clock 34 42 56 62 63 68 69 70 H HT 26 27 36 57 111 ittis 111 7100 36 111 Development Board 26 27 CM7200 36 111 E E 21 24 25 27 30 36 48 52 55 76 97 99 7000 76 99 CM7100 21 24 52 55 97 Development Board 25 27 CM7200 30 52 55 97 H3 21 24 25 27 30 110 111 CM7100 25 27 Prototyping Board ere 21 24 30 110 111 H4 Prototyping Board 23 110 111 5 Prototyping Board
8. 111 handshaking RS 232 5 epis ERES 57 CM7000 Hayes Smart 10061 59 high current driver 144 ase end 51 52 addressing 28 35 80 97 111 141 144 146 149 cycles 76 77 05 49 xg s 49 in system programming CM7200 32 initialization communications 60 60 inport 62 92 94 99 143 146 input digital ss 119 120 inputs outputs deViCes eeu 94 94 SPACE o 94 int type specifier use 84 interface 36 37 39 asynchronous serial ports 63 serial communications 70 interrupt handling 7180 Port 0 59 interrupts 64 65 66 98 99 100 interrupt service routines 100 interrupt vectors 64 98 100 default 98 vector table 60 nonmaskable 53 99 100 112 power failure 99 100 priorities 100 1 1 59 100 and debugging 60 serial communication 5 CM7000 J Jl 67100 53 200 53 Prototyping Board 112 J10 Prototyping Board 23 117 118 Prototyping Board edis 22 23 117 118 J2 CM7100
9. esee deed 40 SoftWare EE 41 Programmable Timers essere 42 SOMWA 42 43 VUA E 43 2 7200 Ee 45 SRAME cssasenadionaaerseacestooentoed anuseuteasegesnuveuser stg 46 EEPROM 4 ee terni e e e tee ee ES 47 Real Time Clock RTC eese 47 CM7000 Table of Contents iii Power Management enoei emer ttt Pe roni HEISSEN RR 48 Handling Power Fluctuations eese 49 The Watchdog Timer edi SHARE 52 Power Shutdown and Reset seen 52 PEL Early Watnin EE 52 Memory Protection 2 53 Capacitor Backup 53 System RESET e aea e erae Ea A aE a A TEES 55 Serial Communication seseina a i aa 56 RS 232 Communic tion eee eA 57 Receive and Transmit 58 Echo Option res eie eei REPE 58 CTS RTS Control perge re en 58 XMODEM File 58 Modem Communication 59 Interrupt Handling for Z180 0 2222 59 SoftWare Support eto eR HET 60 Master Slave 00 61 Us otthe Seri l Ports oae REPRE MES 62 Attainable Baud Rates 63 ZiIS0
10. 7100 has 512 byte EEPROM at location 11 The EEPROM is nonvolatile memory and holds system constants The CM7200 emulates this EEPROM in its flash EPROM and executes all of Dynamic C s EEPROM function calls Consequently despite the dissimilar hardware the memory map for both versions 15 exactly the same Table D 1 lists the constants that are stored and their locations Table D 1 EEPROM Arguments Address Definition 0x000 Operating mode 0 1 2 0 2 RS 485 with NMI 0 4 execute user program on startup 0x001 Baud rate code in multiples of 1200 bps 0 100 Unit serial number BCD time and date with the following format seconds minutes hours day month year 0x108 Microprocessor clock speed in multiples of 1200 Hz 16 bits This value is 7680 for a 9 216 MHz clock and is 15 360 for a 18 432 MEz clock 0 16 Long coefficient relating the clock speed of the microprocessor clock relative to the speed of the real time clock A nominal value is 107 374 182 which is 1 40 of a second where 232 is 1 second This constant requires 4 bytes of EEPROM stored least byte first The EEPROM has 512 bytes Bytes 0 255 can be written to at any time but the upper 256 bytes can be write protected To write protect the upper 256 bytes of the CM7100 s EEPROM cut the trace shown in Figure D 1 000 ooo
11. 112 LMM iste entente 147 140 140 1101294 140 master slave networking 60 command protocol 60 functional support 60 message format 60 serial communication 60 mechanical dimensions 87 mechanical specifications 86 memory battery backed 60 nonvolatile 35 47 102 random access 23 25 27 28 29 35 46 48 49 53 117 149 read only 21 23 24 25 27 28 29 34 39 43 117 118 memory cycles execution timing 93 162 Index memory map 92 MMU ettet eere 35 67 MODI 66 67 MOD2 rtr 67 modem commands 59 termination 2 22 2222 59 modem communication 60 serial link wiring 59 modem control lines 63 modem option 57 59 mounting holes LCD Keypad module 126 68 9 MPBRYIEFR 67 MPBT 69 MPE 68 multiprocessor bit receive error flag Teset eee en 67 multiprocessor bit transmit 69 multiprocessor enable 68 multiprocessor mode 67 69 N networking serial communication 56 NMI See nonmaskable interru
12. 72 75 carrier return as modem command terminator 59 61 chip selects 28 35 80 97 111 128 129 141 144 146 149 CKAT uno eu 67 disable 67 1 67 CKAD eR 67 Clear to Send prescaler 69 clock external 222 63 real time 35 47 53 time date 35 47 53 clock frequency 34 42 56 62 63 68 69 70 clocked serial I O CSI O 30 110 CM7000 interface 36 37 39 Prototyping Board 23 26 27 28 36 78 110 112 119 120 126 127 128 CM71 72 11 128 CM7100 block diagram 34 board layout 15 Developer s Kit 15 Development Board PUES 20 24 25 26 27 28 development setup 21 24 27 30 EEPROM 35 47 102 EPROM 14 15 43 Evaluation Kit 15 20 158 Index CM7100 experimenting 20 36 2 36 in system development 20 inodels 2 ete 14 programming methods 20 Prototyping Board 20 21 24 55 reset management 79 serial cable inue 23 special EPROM 21 43 7200 bloc
13. CM7000 Series C Programmable Core Module User s Manual Revision F 7000 Series Core Modules User s Manual Part Number 019 0018 Revision F Last revised on February 18 1999 Printed in U S A Copyright 1999 Z World All rights reserved Z World reserves the right to make changes and improvements to its products without providing notice Trademarks Dynamic C is a registered trademark of Z World Windows is a registered trademark of Microsoft Corporation PLCBus is a trademark of Z World Hayes Smart Modem is a registered trademark of Hayes icrocomputer Products Inc Notice to Users When a system failure may cause serious consequences protecting life and property against such consequences with a backup system or safety device is essential The buyer agrees that protection against consequences resulting from system failure is the buyer s responsibility This device is not approved for life support or medical systems All Z World products 100 percent functionally tested Additional testing may include visual quality control inspections or mechanical defects analyzer inspections Specifications are based on characterization of tested sample units rather than testing over temperature and voltage of each unit Z World may qualify components to operate within a range of parameters that is different than the manufacturer s recommended range This strategy is believed to be more economical and
14. and Ritchie C A Reference Manual by Harbison and Steel Knowledge of basic 780 assembly language and architecture GY For documentation from Zilog refer to the following texts Z180 MPU User s Manual Z180 Serial Communication Controllers Z80 Microprocessor Family User s Manual CM7000 About This Manual ix Acronyms Table 1 is a list of acronyms that may be used in this manual Acronym Table 1 Acronyms Meaning Erasable Programmable Read Only Memory Electronically Erasable Programmable Read Only Memory Liquid Crystal Display Light Emitting Diode Nonmaskable Interrupt Parallel Input Output Circuit Individually Programmable Input Output Programmable Reload Timer Random Access Memory Real Time Clock Serial Interface Board Static Random Access Memory UART Universal Asynchronous Receiver Transmitter Icons Table 2 displays and defines icons that may be used in this manual Icon Table 2 Icons Meaning Refer to or see Please contact Caution Factory Default Icon Meaning A High Voltage Tip x About This Manual CM7000 Conventions Table 3 lists and defines typographical conventions that may be used in this manual Table 3 Typographical Conventions Example Description while Courier font bold indicates a program a fragment of a program or a Dynamic C keyword or phrase IN 01 Program comments are
15. 0 35 36 RXAO 37 38 RXA1 39 40 GND Figure 3 4 CM7000 1 for Header H2 and Extension H1 36 System Development CM7000 Table 3 1 lists the 7000 interface signals Table 3 1 CM7000 Interface Signals Signal TUE er Direction Description 0 5 Address lines CMOS compatible D0 D7 Bi Data lines TTL CMOS compatible RD Out Read Defines a read cycle Directly connected to 7180 TTL CMOS compatible WR Out Write Defines a write cycle Directly connected to Z180 TTL CMOS compatible INTO In Maskable interrupt request 0 TTL CMOS compatible INTI In Maskable interrupt request 1 TTL CMOS compatible IORQ Out I O Request Defines an I O cycle Directly connected to Z180 TTL CMOS compatible CS1 Out Chip selects 6 Each selects a group of 64 0 CS6 addresses TTL CMOS compatible WAIT In Wait line Generates wait states for I O cycles Allows access to slow T O devices Directly connected to Z180 TTL CMOS compatible DREQO In DMA request lines Requests movement of one byte of DREQI data on specified DMA channel 0 or 1 Can be edge or level sensitive Ignored during memory to memory and serial to memory operations Directly connected to Z180 TTL CMOS compatible DREQO can be a clock input or output for serial port 0 running at 16 x baud rate TENDO Out transfer end lines Signa
16. 16 Overview CM7000 Software Development and Evaluation Tools Dynamic C Z World s Windows based real time C language development system 1 used to develop software for the CM7000 The host PC downloads the executable code through the CM7000 s RS 232 serial port or through the Serial Interface Board 2 to one of the following places battery backed RAM ROM written on a separate EPROM programmer and then substituted for the Z World development EPROM or flash EPROM Dynamic C allows fast in target development and debugging AN Z World s Dynamic C reference manuals provide complete software descriptions and programming instructions For ordering information or more details about the various options and prices call your Z World Sales Representative at 530 757 3737 CM7000 Overview 17 Blank 18 Overview CM7000 2 2 GETTING STARTED CM7000 Getting Started 19 Programming Setup Dynamic C Z World s C language development system is used to develop applications for the CM7000 As a program compiles Dynamic C down loads it directly to the CM7000 s memory via one of the PC COM ports Serial communication is normally at 19 200 bps and can be as high as 57 600 bps The CM7000 remains connected to the PC in most instances while a program is undergoing development The mechanics of connecting a CM7000 and a PC vary depending on the CM7000 version and the programming strategy The
17. 30 66 110 CTS 28 57 58 59 66 CIS enable eee 66 66 cyclic redundancy check 61 D data carrier detect 65 data format mode bits 67 DATA mode modem communication 59 52 112 Developer s Kit 7100 15 development EPROM 15 CM7200 ederet 16 development 21 24 0 CM7200 30 Software 222222 20 Development Board 25 27 122 board 122 7100 20 24 25 26 27 28 CM7100 capacitative loading 72 73 dimensions 124 programming port 123 7 123 tastes 123 7 123 7000 Development Board JB3 Scot SERE S 123 123 E 123 jumper 123 0 123 digital input 119 120 digital to analog converter 147 dimensions CM7100 tate aite 87 7200 87 Development Board124 Prototyping Board 115 107 Dinit 20 60 Dinit 21 60 DIP switches Flash Programmer 134 135 direct memory access DMA chan nels 34 39 40 41 1 40 41 software 41 42 fod SRA 39 display liquid crystal See LCD divide 22 2 2 22422 69 DMA See direct memory access
18. lo 5 J10fo o J11 ooonooonooooooonooonooo O00000000000000000000000 ooonooonooooooonooonooo ooonooonooooooonooonooo ooonooonooooooonooonooo ooonooonooooooono n ooonooonooo Figure 2 4 CM7100 Prototyping Board It is necessary to place jumpers across headers J2 J3 and 14 to enable headers 6 1 on the Prototyping Board Note that this disables chip selects CS1 CS2 and CS3 The LEDs will not work when CS1 is disabled The BIOS the special EPROM Z World part number 680 295x supplied with the CM7
19. 17 2 3 10 0 0 3 10 3 0 0 3 10 3 continued 74 Design Considerations CM7000 Table 4 2 7200 Capacitive Loading concluded Capacitative Load pF Signal cm7200 Prototyping 7200 Proto Max Board ss ol 0 3 1 3 05 0 0 0 cs 0 0 0 css 0 0 0 18 0 0 8 E 0 0 3 10 3 o 0 o RXA1 0 0 5 10 5 0 0 5 10 5 o 0 5 10 5 txo 0 0 5 10 5 0 0 0 1 0 0 0 0 0 IRESET 12 24 3 10 5 cTs0 0 0 5 10 5 0 0 0 0 ANTO 0 0 0 PFI 27 36 0 2 5 10 o o 5 The timing specifications for the 71807 outputs assume driving no more than a 100 pF load Each 50 pF above this nominal load adds a 10 ns delay for the signal to switch up to 200 pF for data lines and 100 pF for address and control lines The timing 1 measured to a 1 5 V transition for the 7180 All measurements were made with an additional load of 100 pF added to each address and data line This allows you to add up to 100 pF with your inter face hardware and realize the performance specified in Tables 4 1 and 4 2 CM7000 Design Considerations 75 Bus Timing Hardware used with the CM7000 must meet the timing require
20. 42 56 62 63 68 69 70 CM7000 T 42 TDR 64 67 TDRE 64 65 67 TE ner 67 threshold V 79 TIE iR 65 time date clock 35 47 53 96 oen 94 programmable PRT 34 42 43 watchdog 29 35 49 52 79 tm rdi 47 m 47 TMDR 42 transfer end 39 transient protection 151 transmit buffer 57 58 transmitter data register 65 65 transmitter enable 67 transmitter interrupt 64 transmitter interrupt enable 65 Tranzorbs sss 151 99 troubleshooting cables zz edes 82 COM 82 83 communication mode 83 expansion boards 82 Flash Programmer 137 grounds 20 82 operating mode 83 power 82 repeated resets 83 59 0 Ul 7100 47 102 03 CM7100 21 24 25 27 43 Development Board 24 27 Index 165 03 7200 45 Prototyping Board 112 04 CM7100 cette 80 67200 ess
21. 60 serial link wiring 59 serial ports 57 58 62 64 CM7000 serial ports asynchronous 63 baud rate 63 low level utility functions 62 multiprocessor communications 1 63 protecting 150 SIB S 30 106 110 baud rate en 106 dimensions 107 POWET 106 slave identification number 60 slave response format 61 software development 20 source C term USE cenae 84 source speed select 68 special EPROM 21 23 26 27 43 117 118 specifications 85 electrical innen 86 environmental 86 86 spring Flash Programmer 136 SRAM interface 149 SSU ioc aad ina 68 SS Tecan bue 68 2 68 standard EPROM 43 STATO edite oco ERR 65 static RAM 23 25 27 28 29 35 46 48 49 53 117 149 super 54 supervisor 691 35 48 49 52 53 54 55 79 99 112 114 SWI Prototyping Board 114 SW2 SW5 Prototyping Board 119 switching power supply 78 510 62 system clock frequency 34
22. J iss 0000000000000000000000000000000000 0000000000000000000000000000000000 0000000000000000000000000000000000 Figure F 1 Prototyping Board 110 Prototyping Board CM7000 Interfaces Besides the 40 pin socket header H3 where the CM7000 is plugged in the Prototyping Board has two sets of plated through holes for easy soldering One set J5 near the prototyping area provides most of the signals from the CM7000 The other set indicated optional comprises four signals that correspond to the interface extension H1 of the CM7000 Figure F 2 shows the location of the through holes and provides a pinout T NOOOOOOOOOO000000 0000 LED2 optional 30000000000000000000000000000000000 yoon 5 0 optional 5 5 lt 8 O Oo 5 Qo FF e NAN N ce Zazo y 0000000000000000 lt 5 5 000000 0 10 KR N NL E LE LU e e CN CO sb iO NO sx WO lt lt 2 Figure F 2 Prototyping Board Interfaces The Prototyping Board has two serial ports H4 and H5 shown schema
23. 1 25 1 35 1 45 0 375 0 54 0 725 20 6 29 7 39 9 Sample Applications 145 24 Bit Parallel I O The 24 bit parallel I O circuit shown in Figure J 6 demonstrates how to get a large number of parallel I O with the CM7000 The 82 55 provides 24 bits of TTL compatible I O 5 82C55A RD WR 4 186 Port A 744604 A1 5 1 4 00 7 5 Port C o vo o o o o o gt ovo o j oj om oo v 24 Bit Bidirectional Parallel I O Figure J 6 24 bit Parallel I O Circuit The 82C55 has four registers located at I O addresses 0x4140 through 0x4143 in this example The sample program below shows how to operate the ports Setup ports A out 0 3 C 4 7 out outport 0x4143 0x83 outport 0x4140 0x55 Write to port A pb inport 0x4141 Read from port B pe inport 0x4142 Read port C bits 0 3 Even though the 82C55 is a CMOS part internally the output drivers adhere only to TTL levels Therefore pull these outputs up when interfacing to CMOS inputs 146 Sample Applications CM7000 8 Bit Digital to Analog Converter The 8 bit digital to analog converter DAC circuit shown in Figure J 7 demonstrates a way to add an 8 bit DAC to a CM7000 based system An 8 bit latch at address 0x4100 drives the DAC The output is a unip
24. 5 V One way to make this connection 15 to solder together pads 2 and 3 at U5 Figure 3 10 provides a schematic representation of these connections Customer installed resistor to enable battery charging R1 Open when RO 6 vourlVRAM Voltage supply Ji to etc WDI WDO RAMCS 691 CSR PRESET RAM Chip Select Connect when ADM691 is not installed J2 Figure 3 10 CM7100 Power Management Circuit 48 System Development CM7000 For the CM7200 solder a jumper across headers J1 and J2 located under the ADM691 chip 05 connects the RAM signal to the RAM and J2 provides power to the RAM Further you must connect VRAM to 5 V One way to make this connection is to solder together pads 2 and 3 at US Conversely if a supervisor IC 18 installed on CM7000 shipped from the factory without one you would first have to remove the jumpers at headers J1 and J2 on the CM7200 and from header J2 on the CM7100 Be sure not to connect VBAT to ground if the ADM691 is present and battery or super capacitor has been included in the system The ADM691 chip performs the following services e Watchdog timer resets the microprocessor if software hangs Performs a power failure shutdown and reset e Generates an early warning power failure interrupt that lets the system
25. Standoff vv H3 Power Jack Battery I Prototyping Board CR Figure 2 15 Connecting CM7200 to Prototyping Board 3 Connect the 6 conductor RJ 12 cable provided with the Developer s Kit from the PC serial port adapter to the SIB2 as shown in Figure 2 16 Connect the 2 mm ribbon cable from the SIB2 to header JP1 on the CM7200 Be careful to match the arrow on the connector to Pin 1 of 4 Set the baud rate of the host PC s COM port to 9600 bps 19 200 bps or 57 600 bps 5 Apply power to the Prototyping Board As a minimum the power supply must have regulated 5 V and GND for the CM7200 The CM7200 is now ready for programming 30 Getting Started CM7000 6 conductor To PC COM RJ 12 Cable Port 6 pin RJ 12 to DB 9 RJ 12 Male Adapter l Zorro 1 6 RJ 12 Male S gt E X 5 gt Board 2 Marked Conductor to Pin 1 7200 1 Core module o on 0 0 0 6 Figure 2 16 7200 Connection to Serial Interface Board 2 CM7000 Getting Started 31 7200 Method 2 Embedded System l 2 Disconnect power from the system Connect the 6 conductor RJ 12 cable provided in the Developer s Kit from the PC s serial port adapter to the SIB2 Connect the 2 mm ribbon cable from the
26. and Interrupt Vectors 99 Jump Vectors These special interrupts occur in a different manner Instead of loading the address of the interrupt routine from the interrupt vector these interrupts cause a jump directly to the address of the vector which will contain a jump instruction to the interrupt routine This example illustrates a jump vector 0x66 nonmaskable power failure interrupt Since nonmaskable interrupts NMI can be used for Dynamic C communi cations an interrupt vector for power failure is normally stored just in front of the Dynamic C program Use the command JUMP_VEC NMI VEC name to store the vector here The Dynamic C communication routines relay to this vector when the NMI is caused by a power failure rather than by a serial interrupt Interrupt Priorities Table C 6 lists the interrupt priorities Table C 6 Interrupt Priorities Interrupt Priorities Highest Priority Trap illegal instruction nonmaskable interrupt INT 0 maskable interrupts Level 0 three modes INT 1 maskable interrupts Level 1 PLCBus attention line interrupt INT 2 maskable interrupts Level 2 PRT Timer Channel 0 PRT Timer Channel 1 Channel 0 DMA Channel 1 7180 Serial Port 0 Lowest Lowest Priority ZlS0SeralPot 7180 Serial Port 1 100 Memory Map and Interrupt Vectors CM7000 D ArPENDIX D EEPROM CM7000 EEPROM 101
27. bit 0 outport 654 1 1 clear 1294 CS fvalue value 2 5 1024 convert value if fvalue gt 2 5 fvalue 5 return fvalue main int i float ch0 for chO read 1294 1 printf Ch 0 bi 0 chO read 1294 0 printf Ch 0 uni fWn ch0 printf Mn for 1 0 1 lt 20000 1 a delay 142 Sample Applications CM7000 Optically Isolated Switch Reader This circuit in Figure J 4 demonstrates how to read a discrete field input inexpensively by using an optical isolator The input is a current loop powered by an external power supply that is not ground referenced to the 7000 When the external switch closes current flows through the isolator s internal diode and activates the output phototransistor pulling the input of the 74HC244 to ground The switch activation can also generate an interrupt by connecting the output of the optical isolator to one of the interrupt lines INTO or INT1 74HC32 74HC244 RD CS5 Do 5 5 10 O 2 2 from the field BN gt 4N 6 Switch ER 1 4001 Figure J 4 Optically Isolated Switch Reader The software to read the switch is very simple get switch status 0 closed 1 byte 51 swl inport 0x4100 12 CM7000 Sample Applications 143 Relay Circuit The circuit shown in Figure J 5 demonstrates a simple 8 relay interface Th
28. controllers and other devices Table 3 7 lists the RS 232 signals Table 3 7 RS 232 Signals Signal Name Description RXO Receive Channel 0 RXI Receive Channel 1 TXO Transmit Channel 0 Transmit Channel 1 CTSO Clear to send Channel 0 RTSO Request to send Channel 0 Figure 3 13 illustrates a configuration of two 3 wire RS 232 channels 232 TXAO RXAO zieo RXA1 CM7000 4 7 UF 4 7 UF 4 7 UF Figure 3 13 Configuration of Two 3 wire RS 232 Channels With the appropriate driver chips it is possible to construct two 3 wire RS 232 ports or one 5 wire RS 232 port with RTS and CTS and one half duplex RS 485 port An RS 485 channel can provide half duplex asynchronous communication over twisted pair wires for distances up to 3 km Other kinds of serial channels are possible 56 System Development CM7000 Figure 3 14 illustrates configuration of 5 wire RS 232 channel and one half duplex RS 485 channel MAX232 TXAO RXAO RTSO CTSO TXA1 RXA1 10 CM7000 Transmit Enable Figure 3 14 Configuration of One 5 wire RS 232 Channel and One Half Duplex RS 485 Channel RTSO 1 on the optional header not on the 40 pin header If additional handshaking lines are needed these easy to provide using registers and input buffers RS 232 Communication Z World has RS 232 support li
29. flag is not recoverable because the second and subsequent NMIs will have saved 0 to IEF2 Also depending on the number of fluctuations of the DC input and hence the number of stacked NMIs the processor s stack can overflow possibly into your program s code or data The following sample program shows how to handle an NMI This program assumes that the controller monitors power failures and that the CM7000 s watchdog timer is enabled main char dummy 24 define NMI_BIT 0 bit 0 JUMP_VEC NMI_VEC myint asm myint 1 sp dummy 24 force stack pointer to top of dummy vector to prevent overwriting code or data do whatever service within allowable execution time loop call hitwd ld bc NMI in a c bit jr z loop timeout timeout 50 System Development make sure no watchdog reset while low voltage load the read NMI register to bc read the read NMI register for PFO check for status of PFO wait until the brownout clears then a tight loop to force a watchdog timeout resetting the 2180 CM7000 If the watchdog is not enabled the following sample program can be used to force the processor to restart execution at 0x0000 char dummy 24 define NMI BIT 0 bit 0 JUMP_VEC NMI VEC myint asm myint 1 sp dummy 24 reset stack pointer to top of dummy array to prevent overwriting user code
30. mode is enabled RTSO Request to Send Channel 0 Store a 1 in this bit to set the RTSO line from the Z180 high This bit is essentially a 1 bit output port without other side effects 1 Disable This bit controls the function assigned to the multiplexed pin 1 TENDO 1 a DMA function and 0 CKAI external clock I O for Channel 1 serial port TE Transmitter Enable This bit controls the transmitter transmitter enabled 0 transmitter disabled When this bit is cleared the processor aborts the operation progress but does not disturb TDR or TDRE CM7000 System Development 67 This bit controls the receiver 1 enabled 0 disabled When this bit is cleared the processor aborts the operation in progress but does not disturb or the error flags MPE Multiprocessor Enable This bit 1 enabled 0 disabled controls multiprocessor communica tion mode which uses an extra bit for selective communication when a number of processors share a common serial bus This bit has effect only when MP in Control Register B is set to 1 When this bit is 1 only bytes with the MP bit on will be detected Others are ignored If this bit is O all bytes received are processed Ignored bytes do not affect the error flags or ASCI Control Register Control Register B configures the multiprocessor mode parity and baud r
31. Board typically draws 110 mA with the CM7000 attached The maximum allowed current draw for the entire board is 400 mA 112 Prototyping Board CM7000 Prototyping Area 2 2 x3 3 prototyping area consists of plated through holes spaced on 0 1 centers The area has four power rails Holes near the power rails are connected facilitating the soldering of 300 mil and 600 mil DIPs Figure F 5 shows the prototyping area c9 C10 DO C12 mooooooooooooooo lO h LED2 s 2 e 0000000000000000000000000000000000 m LEDS 2 6
32. Box Dynamic C Will Not Start Dynamic C Loses Serial Link e CM7000 Repeatedly Resets Common Programming Errors CM7000 Troubleshooting 81 Out of the Box Check the items mentioned in this section before starting development Verify that the CM7000 runs in standalone mode before connecting any devices Verify that the entire host system has good low impedance separate grounds for analog and digital signals Often the CM7000 is connected between the host PC and another device Any differences in ground potential from unit to unit can cause serious problems that are hard to diagnose Do not connect analog ground to digital ground anywhere e Double check the connecting ribbon cables to ensure that all wires go to the correct screw terminals on the CM7000 Verify that the host PC s COM port works by connecting a good serial device to the COM port Remember that COM1 COM3 and COM2 share interrupts on a User shells and mouse drivers in particular often interfere with proper COM port operation For example a mouse running on COMI can preclude running Dynamic C on COM3 Use the supplied Z World power supply If another power supply must be used verify that it has enough capacity and filtering to support the CM7200 Use the supplied Z World cables The most common fault of user made cables 1 failure to properly assert CTS Without CTS being asserted the CM7000 s RS 232 port will not transm
33. Keypad module installed SC1DM232 C Uses DMAO to receive and transmit data from and to Serial Port 0 of the Z180 SC1DMAPW C Uses DMAO DMAI to generate pulse widths on LED 2 and LED 4 SCINMI C Demonstrates power failure interrupt and brownout monitoring SCIRTC C Continuously displays time and date to the Dynamic C STDIO window SCIRTK C Demonstrates the real time kernel RTK SC1WDOG C Demonstrates how to monitor watchdog timeouts at startup All the sample programs referred to in this appendix are also available in the regular Dynamic C SAMPLES CM71_72 directory 156 Libraries and Sample Programs CM7000 Symbols HINT 59 60 98 HJUMP 99 100 28 1 120 129 ICS1 ICS6 28 35 80 97 111 128 129 141 144 146 149 92 inns tee 119 129 166 sae 117 128 ICS sts 141 144 149 ICS5 sd eee ten 149 53 axes 64 65 69 5 69 ICTSO 58 IDCDO 63 64 65 66 line to ground 64 IDREQD 1s 39 DREQI esee 39 99 INT inn 99 IINT2 singe tiles 99 IKH0 imet 129 IKHT 129 99 112 52 53 55 79 67 nen 63 39 67 TEND1 39 WAIT 222 22 52 77 52 assignment USC OR ei 84 12 bit ADC 14
34. Serial Potts 63 Asynchronous Serial Communication Interface sss 65 ASCI Status Registers 0 4 65 DCDO Data Carrier 2 65 TIE Transmitter Interrupt 1 2 65 TDRE Transmitter Data Register Empty sess 65 CTSIE CTS Enable Channel 0 66 RIE Receiver Interrupt 66 6 66 7 66 Receiver Data Register 66 ASCI Control Register essere 67 MODO0 MOD2 Data Format Mode Bits 67 MPBR EFR Multiprocessor Bit Receive Error Flag Reset 67 RTSO Request to Send Channel 0 67 CKAID Disable eese 67 TE Transmitter Enable seen 67 RE Receiver Enable sess 68 MPE Multiprocessor Enable see 68 iv Table of Contents CM7000 ASCI Control Register SS Source Speed Select sse DR Divide Ratio PEO Parity Even Odd sse CTS PS Clear to Send Prescaler MP Multiprocessor Mode sene MPBT Multiprocessor Bit Transmit Chapter 4 Design Considerations Bus Loading sae tee B us Timing nae ete er I eH HR ER Standard V
35. System Development CM7000 7100 7100 has 32 pin socket U3 that accepts 32K to 512K EPROM The socket accepts either 28 pin or 32 pin EPROM chips The access time must be less than 70 ns at 18 MHz or less than 100 ns at 9 MHz Figure 3 5 shows how to seat the EPROM chip in the socket according to the number of pins 04 U4 RAM RAM 28 pin EPROM 32 pin EPROM Figure 3 5 Placement of 28 pin and 32 pin EPROM on CM7100 Header J3 on the micropro cessor side of the CM7100 NER ROM gt 128K reflects the EPROM size as J3 shown in Figure 3 6 the CM7100 Z World part number 680 290x supports the full Dynamic C soft ware development system This standard EPROM has Figure 3 6 CM7100 Header J3 Configurations 28 pins for Different EPROM Sizes A special 32 pin 128K EPROM Z World part number 680 295x comes with the CM7100 Evaluation Kit This special EPROM supports the trial version of Dynamic C that comes with the kit and contains eight sample programs J2 PAL n When using the CM7100 Development Board ROM emula tor header J3 on the 7100 must have pins 2 3 connec
36. Transmitter Data Register Empty A 1 means that the channel is ready to accept another character A high level on the CTS pin forces this bit to 0 even though the transmitter is ready CM7000 System Development 65 CTS1E CTS Enable Channel 1 The signals RXS and CTSI are multiplexed on the same A 1 stored in this bit makes the pin serve the CTS1 function 0 selects the RXS function The pin RXS is the CSI O data receive pin When RXS is selected the CTS line has no effect RIE Receiver Interrupt Enable A 1 enables receiver interrupts and 0 disables them receiver interrupt 18 requested under any of the following conditions 20 00 Channel 0 only read data register full OVRN overrun PE parity error and FE framing error The condition causing the interrupt must be removed before the interrupts are re enabled or another interrupt will occur Read ing the receiver data register RDR clears the RDRF flag The EFR bit in CNTLA is used to clear the other error flags FE Framing Error A stop bit was missing indicating scrambled data This bit is cleared by the EFR bit in CNTLA PE Parity Error Parity is tested only if MODI in CNTLA is set This bit is cleared by the EFR bit in CNTLA OVRN Overrun Error Overrun occurs when bytes arrive faster than they can be read from the receiver data register The receiver shift register RSR and receiver data register RDR are both full This
37. WAIT line at the falling edge of T or T clock CM7000 WAIT cycles Design Considerations 77 System Power The CM7000 requires a regulated 5 V power source to operate Depend ing on the amount of current required by the application different regula tors can be used supply this voltage The Prototyping Board has an onboard LM340 T5 to provide the necessary 5 V The 340 5 is an inexpensive linear regulator that is easy to use Its major drawback is its inefficiency which 1s directly proportional to the voltage drop across it This voltage drop causes heat and wastes power 340 5 regulator comes in several packages having different heat dissipation characteristics TO 220 packages are most typical Appendix E Sample Applications provides an example of using an LM340 A switching power supply may be used in applications where better efficiency is desirable The LM2575 is an example of an easy to use switcher This part greatly reduces the heat dissipation of the regulator The drawback in using a switcher 1s the increased cost 78 Design Considerations CM7000 Power On Reset Management The designer employing the CM7130 or CM7230 needs to provide a supervisory circuit that monitors the power supply and develops a power on reset signal RESET Upon power up RESET needs to remain low for at least 50 ms after rises above an appropriate reset threshold This delay allows
38. as shown in Figure 2 3 Cus tom burned EPROM are also installed at location U3 32 pin EPROM Figure 2 3 Installation of 32 pin EPROM CM7000 Getting Started 21 5 Place jumpers across headers 72 13 and 14 on the Prototyping Board to enable headers J6 J11 on the Prototyping Board The Prototyping Board is shown in Figure 2 4 Power Jack SmartCore Evaluation Board lt D Reset D HBBBBEHBBBH Configuration D Jumpers m TID 0 0000 1 Programming T o n 0 H3 connector location Serial Port 280 H5 45 5 LED2 S O0000000000000000000 O0000000000000000000 O000000000000000000 e 5 LED3 O0000000000000000 0 E LED4 2 LED5 9
39. backup battery or super capacitor is used make sure J1 is not connected J1 may be jumpered to ground VBAT only when the ADM691 supervisor is not installed Factory default except CM7230 not con Connect only when there is no ADM691 supervisor otherwise RAM will not operate Factory default except CM7230 not Header JP1 located on other side of board Specifications 89 Blank 90 Specifications CM7000 C Memory I O AND INTERRUPT VECTORS Appendix C provides detailed information on memory provides map and lists the interrupt vectors CM7000 Memory Map and Interrupt Vectors 91 CM7000 Memory Figure C 1 shows the memory map of the 1M address space 0x80000 0x00000 Figure C 1 Memory Map of 1M Address Space 1024K Socket U8 RAM 512K Socket U7 EPROM Figure C 2 shows the memory map within the 64K virtual space 64K XMEM UNITIALIZED DATA STACK UNUSED USER CODE LIBRARY RAM Based Figure C 2 Memory Map of 64K Virtual Space XMEM UNITIALIZED DATA STACK UNUSED USER CODE ROM LIBRARY ROM Based RAM ROM The various registers in the input output I O space can be accessed in Dynamic C by the symbolic names listed below These names are treated as unsigned integer constants The Dynamic C library functions inport and outport
40. bit is cleared by the EFR bit in CNTLA RDRF Receiver Data Register Full This bit is set when data is transferred from the receiver shift register to the receiver data register It is set even when one of the error flags 15 set in which case defective data is still loaded to The bit 1 cleared when the receiver data register 15 read when the DCDO input 15 high and by RESET and IOSTOP 66 System Development CM7000 ASCI Control Register Control Register affects various aspects of the asynchronous channel operation CNTLAO 00H 3 MPE RE 50 O R W R W RW RW RW Rw Rw RW CNTLA1 01H 3 MPE RE MEER 2 Data Format Mode Bits MODO controls stop bits 0 1 stop bit 1 2 stop bits If 2 stop bits are expected then 2 stop bits must be supplied MODI controls parity 0 gt parity disabled 1 parity enabled See PEO in ASCI Control Register B for even odd parity control MOD2 controls data bits 0 7 data bits 1 8 data bits MPBR EFR Multiprocessor Bit Receive Error Flag Reset Reads and writes on this bit are unrelated Storing a byte when this bit is 0 clears all the error flags OVRN FE PE Reading this bit obtains the value of the MPB bit for the last read operation when the multiprocessor
41. channels downloading data 57 58 programs 2 2 2 60 69 DRIVERS LIB 47 DOR ue Dn 59 Dynamic 15 17 20 39 COMMUNICATION 100 echo option 57 58 ee rd uou 103 ee SITO ed 103 EEPROM 35 44 47 62 102 7100 35 47 102 159 CM7200 simulated m 35 45 47 102 constants 98 function calls 35 library routines 103 writes 103 EPR 66 EFR oor t 66 electrical specifications 86 environmental specifications 86 EPROM 21 23 24 25 27 28 29 34 39 43 60 117 118 access time 43 choosing 2222 424 44 7100 s 43 copyright 22222 44 Taster 133 Options 2 22 44 sample programs 23 26 27 sizes Flash Programmer 133 special sss 21 23 26 27 43 117 118 156 2 43 startup vector 28 29 34 39 Epson 72423 real time clock 47 Evaluation 15 Dynamic C trial version 15 Prototyping Board jumper settings 154 sample programs 154 155 156 special EPROM 21 154 upgrading for normal application development
42. close attention to the capacitive loading of each CM7000 signal Tables 4 1 and 4 2 give the loading in picofar ads for the CM7100 and CM7200 for the Prototyping Board and for the Table 4 1 CM7100 Capacitive Loading Capacitative Load pF Signal CM7100 ib Development bs 09 Both Typ Max Typ Max Board Board Boards A00 26 44 12 40 19 30 38 45 57 A01 26 44 3 10 19 30 29 45 48 02 26 44 3 10 19 30 29 45 48 03 26 44 0 0 14 20 26 40 40 04 14 20 0 0 14 20 14 28 28 05 14 20 0 0 14 20 14 28 28 00 33 54 9 30 29 52 42 62 71 pi 28 46 6 20 29 52 4 57 6 2 28 46 6 20 24 42 34 52 58 03 28 46 6 20 24 42 34 52 58 04 16 22 6 20 21 32 32 37 43 05 16 22 6 20 21 32 32 37 43 06 16 22 6 20 21 32 32 37 43 07 16 22 6 20 21 32 32 37 43 RD 17 32 3 10 10 20 20 27 30 WR 17 32 3 10 10 20 20 27 30 CS1 0 0 3 10 3 0 3 CS2 0 0 3 10 3 0 3 continued 72 Design Considerations CM7000 Development Board Be sure to add the loads for the devices you using in your custom system to these numbers to determine the total load When loads exceed specifications degraded performance will occur and timing requirements might not be met Table 4 1 CM7100 Capacitive Loading concluded Capacitative Load pF signal CM7100 Prototypin
43. connected to the CM7200 106 Serial Interface Board 2 CM7000 External Dimensions Figure E 1 illustrates the external dimensions for the SIB2 Serial Interface Board 2 572 Top View 12 0 3 60 305 91 4 4 Side View Figure E 1 SIB2 External Dimensions CM7000 Serial Interface Board 2 107 Blank 108 Serial Interface Board 2 CM7000 PROTOTYPING BOARD Appendix F provides technical details for Z World s Prototyping Board CM7000 Prototyping Board 109 Description The Prototyping Board is a 4 7 x 6 0 119 mm x 152 mm circuit board with the following features e A22 x 33 56 mm 84 mm prototyping area with 5 V and GND power rails Power jack and voltage regulator e Backup battery Sample circuits 40 pin socket that accommodates either a CM7100 or a CM7200 Supports an optional 2 x 20 LCD and 2 x 6 keypad The CM7100 is programmed using the Prototyping Board s serial port header H4 The Prototyping Board is also used with the CM7200 but programming is done via the CM7200 CSI O port and a SIB2
44. data space do whatever service within allowable execution time loop ld bc NMI load the read NMI register i EO DE in a c read the read NMI register for PFO bit NMI_BIT a check for status of PFO jr z loop wait until the brownout Clears restart 1 2 make sure 0x0000 points to start of EPROM BIOS outO CBAR a set the CBAR 00008 jump to logical also physical address 0x0000 endasm Of course if the DC input voltage continues to decrease then the controller will just power down If the watchdog timer is enabled call the Dynamic C function hitwd during the power failure service routine to make sure that the watchdog timer does not time out and thereby reset the processor The controller can continue to run at low voltages and so it might not be able to detect the low voltage condition after the watchdog timer resets the processor CM7000 System Development 51 The Watchdog Timer To increase reliability the ADM691 s watchdog timer forces a system reset if a program does not notify the supervisor nominally every second The assumption is that if the program fails to hit the watchdog the program must be stuck in a loop or halted The Dynamic C function for hitting the watchdog timer is hitwd To hold the watchdog timer at bay make a call to hitwd in a routine that runs periodically at the lowest software priority level A program can read the state of the WDO line wi
45. effective Additional testing or burn in of an individual unit is available by special arrangement Company Address Z World Telephone 530 757 3737 2900 Spafford Street Facsimile 530 753 5141 Davis California 95616 6800 Web Site http www zworld com USA E Mail zworld zworld com 5 About This Manual ix Chapter 1 Overview 13 Introd ctiOm 3 ene e ees 14 pu M M 14 Options une RR RR REN E RENATA MR HIER 14 CM7TTOO Series dietis 14 CM7200 Series dre 16 Software Development and Evaluation Tools 17 Chapter 2 Getting Started 19 Programming Setup mete ted de ite eden 20 7100 5 20 CM7100 Method 1 Prototyping Board 21 CM7100 Method 2 Development 24 CM7100 Method 3 Embedded in 5178001 27 CM7100 Method 4 In Target Direct Development 28 29 7200 30 CM7200 Method 1 Prototyping Board 30 CM7200 Method 2 Embedded In System 32 Chapter 3 System Development 33 General Description e m HR Re eee 34 Interface Description aire tete d e t e e RS 36 7 39 DIMA c 39 DMA 6
46. has two rows of six keys Figure H 1 shows the LCD keypad module and provides its dimensions Z World 2 A LCD oo 4 4 4 4 g g menu item field dg help g 4 4 g 4 1 Fr F2 F4 del add amp WEM 2 lt 1 1 eG c BE 6 32 clear 4 TIT 4 7 Figure 1 LCD Keypad Module The mounting holes of the module match the indicated mounting holes on the Prototyping Board as shown in Figure H 2 4 7 119 0 5 5 gt 0 22 4 26 gt lt 5 5 108 Se 000 Reset ies d Ri Ui U2 7 6 rs 21 Buzzer H2 E u a a Regulator 4 BHBBBBHBBH 2 2 5 SSS 18 5 05 H H I 1 8 Latch 1D z 22 RN2 C6 a 4 0 6 1 00000000000000000000 H4 Tri MUX H3 0150 dia 4x Figure H 2 Mounting LCD Keypad Module on Prototyping Board 126 LCD Keypad Mo
47. latch 74HC259 controls the flow of information into the LTC1294 as follows e To control the LTC1294 clock write to address 0 40 0 control the LTC1294 chip select write to address 0x40C1 To send the input word write to address 0 40 2 CM7000 Sample Applications 141 The following sample program shows how to read the A D converter in bipolar mode eee ee ke ke ke k 12 bit ADC sample circuit for the CM7000 Channel 0 single ended bipolar kk e H e e e e He H ke e e e ke H ke ke ke ke ke k k k k k k k k kk k kkk define CS4 0x40C0 void set_clock int state sets the clock as 0 or 1 if state outport CS4 1 else outport CS4 0 float read 1294 int j k control value float fvalue ST 5610 UNI always control 0xC3 1 1000 0 11 value 0 outport 654 1 0 assert CS on the 1294 outport 654 2 0 set the DIN bit to 0 set clock 0 set clock 1 set clock 0 set clock 1 3 7 3 gt 0 3 send control word set clock 0 MSB first outport CS4 2 control gt gt j set_clock 1 outport 054 2 0 set DIN to 0 for k 0 k lt 12 k read 12 bits of the set clock 0 1294 MSB first set clock 1 value value lt lt 1 inport CS4 amp 1
48. programming strategy for a CM7100 depends on the hardware setup Only one programming method is available for the CM7200 regardless of whether the Developer s Kit or in target development is used CM7100 Four methods are available to program the CM7100 1 Using the Prototyping Board This method is recommended for gramming the CM7110 supplied in the Evaluation Kit This CM7110 has a special EPROM that contains the BIOS and sample programs Method 1 may also be used to program other CM7100s Since an EPROM is not normally included with CM7100s except for the CM7110 in the Evaluation Kit which comes with a special EPROM a custom EPROM with the contents of the Dynamic C 2903 BIN file must first be burned according to the details in the section Program ming EPROMs in Chapter 3 System Development 2 Using the Development Board The Development Board is included in the Developer s Kit with full Dynamic C and is also sold separately 3 Using the Development Board with full Dynamic C and with the CM7100 embedded in your target system 4 Directly in your system without a Development Board This method requires some hardware setup and minor modifications to the Dynamic C EPROM code Methods 1 and 2 are normally used for evaluation or experimentation Method 3 requires some hardware setup and ultimately must be used to program a working system Method 4 can be the fastest and most power ful Once program developm
49. time for the power supply and microprocessor to stabilize The nominal reset threshold is 4 65 V Figure 4 3 illustrates the reset sequence Vcc RESET treset lt gt treset gt Vt Reset Threshold 4 65 V nominal treset Reset Low Period 0 ms Figure 4 3 CM7000 Reset Sequence On powerdown the RESET signal should remain low until drops below 1 V Keeping RESET low until the power supply voltage drops below 1 V to ensure that the microprocessor stays in a stable condition preventing it from emitting spurious outputs The VBAT on all versions of the CM7000 needs to be grounded if VBAT is not used The battery switchover circuit in the ADM691 supervi sor IC compares V to the VBAT input and connects to whichever is higher the switchover occurs when V is 50 mV higher than VBAT Allowing VBAT to float by not connecting it can cause erratic operation The 7130 and CM7230 have no ADM691 supervisor IC and so the SRAM and the real time clock RTC cannot be battery backed Watchdog Timer The watchdog timer will time out after a nominal 1 0 second 1 0 second minimum 2 25 seconds maximum Hitting the watchdog timer every second is therefore a conservative method of avoiding a watchdog timeout CM7000 Design Considerations 79 Addressing When software places an address 0x4000 0x41FF on the address lines the decoder CM7100 U7 CM72
50. written in Courier font plain face Italics Indicates that something should be typed instead of the italicized words e g in place of filename type a file s name Edit Sans serif font bold signifies a menu or menu selection An ellipsis indicates that 1 irrelevant program text is omitted for brevity or that 2 preceding program text may be repeated indefinitely 1 Brackets in a C function s definition or program segment indicate that the enclosed directive is optional lt gt Angle brackets occasionally enclose classes of terms alble A vertical bar indicates that a choice should be made from among the items listed Pin Number 1 A black square indicates pin 1 of all headers 1 o Measurements diagram and graphic measurements are in inches followed by millime ters enclosed in parenthesis CM7000 About This Manual Blank xii About This Manual CM7000 1 1 OVERVIEW CM7000 Overview 13 Introduction CM7000 is a microprocessor core module The CM7000 combines a complete system engine with integrated development software You build your own controller around the plug in CM7000 Features Small size 1 80 x 2 05 45 7 mm 52 1 mm Microprocessor Z180 running at 9 216 MHz or 18 432 MHz includ ing two DMA channels two serial ports and two programmable timers PRTs SRAM 32K or 128K 512K factory installed SRAM is also av
51. 0 141 142 24 bit parallel I O 146 691 supervisor 35 48 49 52 53 54 55 79 99 112 114 TAH C374 149 8 bit sss 147 CM7000 82655 146 9th bit address mode 61 Oth bit transmission 60 A A D conversion 140 141 142 IOS AS usen 97 ASE 67 68 70 Control Register A 67 Control Register B 68 status 1 65 ASCII characters and modem commands 59 asynchronous channel operation 67 AT29CO10 etes 45 B backup battery 35 49 53 54 110 super capacitor 49 53 54 battery backup35 49 53 54 110 baud rates 23 25 56 62 63 69 70 118 119 serial ports 63 beeper Prototyping Board 120 155 BIOS 45 recovery Flash Programmer 136 update Flash Programmer 136 block diagram CM7100 iicet 34 67200 34 board layout CMT TOU ier rete 15 67200 cessere 16 Development Board 122 Prototyping Board 110 Index 157 buffer 57 58 59 transmit 07 57 58 bus 72 75 bus timing ociera 76 77 buzzer Prototyping Board 120 155 C capacitive loading
52. 0 143 144 146 147 149 Prototyping Board 119 sample programs 154 156 DMA channels 156 LCD Keypad module 155 156 nonmaskable interrupts 156 real time clock 156 real time kernel 156 8 156 SC1DM232 C 156 5 156 SCINMI C eint 156 SCIRTC Q ungue 156 SCIRTK G eed 156 156 5 156 7180 Serial Port 0 155 7180 Serial Port 1 156 sample programs EPROM 23 26 27 154 155 155 SCIPTTRN C 155 155 155 SCIZ20232 C vene 155 SCIZ21232 C eee 156 SERO 59 serial cable 26 27 serial channel 0 block diagram 63 serial channel 1 63 serial communication 20 27 28 34 56 57 58 59 60 62 63 64 65 67 68 70 94 111 master slave 60 Serial Interface Board 2 See SIB2 serial interrupts 59 100 and debugging
53. 0 can generate standard baud rates when the clock frequency 1s 9 216 MHz or 18 432 MHz 7180 Serial Ports The Z180 s two independent full duplex asynchronous serial channels have a separate baud rate generator for each channel The baud rate can be divided down from the microprocessor clock or from an external clock for either or both channels The serial ports have a multiprocessor communications feature When enabled this feature adds an extra bit to the transmitted character where the parity bit would normally go Receiving Z180s can be programmed to ignore all received characters except those with the extra multiprocessing bits enabled This provides a 1 byte attention message that can be used to wake up a processor without the processor having to intelligently monitor all traffic on a shared communications link The block diagram in Figure 3 16 shows Serial Channel 0 Serial Channel 1 is similar but control lines for RTS and DCD do not exist The five unshaded registers shown in Figure 3 16 are directly accessible as internal registers Microprocessor Internal Bus TXAO Shift Register Out Shift Register In Baud Rate Generator Figure 3 16 2180 Serial Channel 0 RTSO CNTLAO CKAO CNTLBO STATO CM7000 System Development 63 The serial ports can be polled or interrupt driven A polling driver tests the ready flags TDRE and RDRF until a ready condition appears transmitter data regist
54. 00 U6 and PAL CM7100 U6 CM7200 04 decode the address Address bits 0 5 appear the header Address bits 6 8 select one of eight output lines which are listed in Table 4 3 Table 4 3 Output Addresses Address Range Output Line 0x4000 403F CS1 0x4040 407F CS2 Ox4080 40BF CS3 Ox40CO 40FF CS4 0x4100 413F CS5 0 4140 417 CS6 0 4180 41 real time clock 0x41C0 41FF WDI Watchdog The selector decodes all addresses in the range 0x4000 that is addresses 0x4200 423F 0x4400 443F Ox7E00 7E3F all select CS1 Addresses 0x4240 427F select CS2 and so on Whichever range is selected the program can select exactly 384 I O addresses using the fol lowing bits 1514131211109 8 7 6 54 32 1 0 01 cccaaaaaa where represents chip select represents address bits and bits can be ignored for your I O addresses chip selects must be RD and or qualified if INTO is used Failure to qualify chip selects can result in false input output cycles because of the unqualified IOE cycle that is without RD or which occurs during the interrupt acknowledge of INTO 80 Design Considerations CM7000 ArPENDIX TROUBLESHOOTING Appendix A provides procedures for troubleshooting system hardware and software The sections include the following topics Outofthe
55. 07F CS2 Chip Select 2 4080 40BF 3 Chip Select 3 40C0 40FF 54 Chip Select 4 4100 413F CS5 Chip Select 5 4140 417 6 Chip Select 6 41C0 41FF WDOG 0 Watchdog 8000 2 DO EEPROM serial data CM7100 8000 FSHWE Flash EPROM write enable CM7200 000 NMI DO Bit 0 is the power failure state C000 WDO Watchdog output CM7200 Addressing Six chip select lines 51 56 and six address lines A0 A5 appear on header H2 These lines give six groups of 64 29 addresses or 384 addresses When an application places an address 0x4000 0x41FF on the address lines the decoder and the PAL decode the address Address bits 0 5 appear on header H2 Address bits 6 8 select one of eight output lines the first six of which are CS1 to CS6 The selector decodes all addresses in the range 0x4000 7FFF that is I O addresses 0x4200 423F 0x4400 443F 0x 7E00 7E3F all select CS1 too Addresses 0x4240 427F select CS2 and so on Whichever range is selected the range provides exactly 384 addresses using the following bits 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 c C C a a Here represents chip select represents address bits and bits can be ignored for I O addresses CM7000 Memory Map and Interrupt Vectors 97 Interrupt Vectors Table C 5 presents a suggested interrupt vector map Most of these interrupt vectors
56. 110 in the Evaluation Kit does not support chip selects CS1 CS2 and CS3 22 Getting Started CM7000 6 Set the Prototyping Board s jumpers Jumpers across headers 110 and J11 affect the operational mode and the baud rate as shown in Fig ure 2 5 When both headers J10 and J11 are jumpered the CM7100 checks headers 16 19 at startup If none of these headers is jumpered the CM7100 will execute the program if any stored in RAM If some of these headers are jumpered a sample program stored in the special CM7100 EPROM will begin executing See Appendix Prototyping Board for more information on the Prototyping Board and the sample programs in the special EPROM Prototyping Board Jumper Settings Program Baud Rate 10 11 19 200 bps 9600 bps 57 600 bps J10 J11 Baud Rate Run program in RAM or special EPROM 0 1 10 1 0 1 Figure 2 5 CM7100 Prototyping Board Program Mode Jumper Settings 7 Connect the serial cable Con nect one end to the PC COM port Then connect the 10 pin Serial cable to PC end to header H4 of the Proto typing Board as shown in Fig ure 2 6 Be careful to match the 3 arrow on the connector to the location of pin 1 on header H4 8 Apply power from the 9 V pow er supply to the Prototyping Board The CM7100 is ready for programming unless the jumpe
57. 32K 512K 128 256 4 5 GND Supervisor VRAM edd Timer RTC VBAT gt Power Failure Warning Reset Control cs Battery Backup Control gt VRAM Figure 3 2 CM7200 Block Diagram The microprocessor is a Z180 running at either 9 216 MHz or 18 432 MHz The Z180 has two asynchronous serial ports two DMA channels and two programmable reload timers PRTs Two of the Z180 s interrupt lines are available for use in the system 34 System Development 7000 7180 supports address space with its internal memory manage ment unit It has 20 address lines The data path is 8 bits wide lines 00 07 Six chip select lines CS1 CS6 enable one of six groups of 64 input output addresses Thus single tier addressing can directly access 384 distinct devices or registers The optional power supervisor IC an ADM691 provides several services It has a watchdog timer performs power failure detection and supports battery backup When power fails it protects the RAM from being accidentally overwritten Your application can obtain the time and the date from the optional real time clock IC an Epson 72423 The optional CM7100 EEPROM 24C04 stores 512 bytes of nonvolatile data for system constants and other important values The upper 256 bytes of the EEPROM can be write protected by breaking a circuit board trace The CM7200 simulates the EEPROM 1n its flash memory This simu
58. 6 D 0 7 45V H swe KVO 10 45V EH swa 2 10 10 74HC257 LU SW5 MUX 45V J6 adl IKV4 J7 e 45V ru 18 10 ka 45V pry 19 10 ka E X 10 WV 45V J3 e 74HC257 1092 0 MUX Figure F 11 Sample Digital Input Circuit on Prototyping Board The multiplexers are enabled when J3 is connected this is the factory default setting When enabled CS2 governs the circuit CS2 represents addresses from 0x4040 to 0x407F Address line 0 selects A or B in the multiplexers Thus reading address 0x4040 retrieves the state of the CM7000 Prototyping Board 119 keypad sense lines and the baud rate jumper configuration whereas reading address 0x4041 gets the state of the pushbuttons and the settings of headers 16 19 C expression CS2 1 is equivalent to 0x4041 The pushbutton values return in the low order bits 0 3 of the data byte The jumper settings return values in bits 4 7 Digital Output The Prototyping Board provides four LEDs 02 05 and a self resonating buzzer to simulate outputs The Prototyping Board also drives the keypad with the selector chip that drivers the LEDs and the buzzer The sample circuit is shown in Figure F 12 45V 10 kQ bo ICS1 42 to Keypad pol Buzzer 74HC259 Figure F 12 Sample Digital Output Circuit on Prototyping Board The selector is enabled when header J2 is connected this is
59. 7000 Nonmaskable Interrupts The NMI line normally connects to the power failure output of the ADM691 supervisor A nonmaskable interrupt NMI occurs when PFI falls to 1 25 V 0 05 V This advanced warning allows the program to perform some emergency processing before an unwanted power down occurs The NMI is edge sensitive and cannot be masked by software When activated the NMI disables all other interrupts except TRAP and begins execution from logical address 0x66 If there is no ADM691 supervisor connect PFI to NMI directly by solder ing US pads 9 and 10 together The following function shows how to handle a power failure interrupt JUMP_VEC NMI_VEC myint interrupt retn myint body of interrupt routine while IBIT WDO 0 input voltage is still below the threshold that triggered the NMI return if just a power glitch return INTO is available for use and appears on header 2 INTO has a 10 pull up resistor INTO is set up in Mode 1 This setup requires a jump vector at address 0x0038 to identify its service routine INT1 IINT1 is available for use and appears on header H2 1 has a 10 pull up resistor INT1 is referenced by an interrupt vector at address 0 0 INT2 IINT2 is reserved for the Development Board and does not appear header H2 INT2 has a 10 pull up resistor An interrupt vector at address 0x2 points to INT2 CM7000 Memory Map
60. B2 is an interface adapter used to pro gram the CM7200 The SIB2 is contained in an ABS plastic enclosure making it rugged and reliable The SIB2 enables the CM7200 to commu nicate with Dynamic C via the Z180 s clocked serial I O CSI O port freeing the CM7200 s serial ports for use by the application during pro gramming and debugging The SIB2 s 8 pin cable plugs into the target CM7200 s processor through an aperture in the backplate and a 6 conductor RJ 12 phone cable con nects the SIB2 to the host PC The SIB2 automatically selects its baud rate to match the communication rates established by the host PC 9600 19 200 or 57 600 bps However the SIB2 determines the host s commu nication baud rate only on the first communication after reset To change baud rates change the COM baud rate reset the target CM7200 which also resets the SIB2 then select Reset Target from Dynamic C Chapter 2 provides detailed information on connecting the SIB2 to the CM7200 The SIB2 receives power and resets from the target CM7200 via the 8 pin connector 11 Therefore do not unplug the SIB2 from the target CM7200 while power is applied To do so could damage both the CM7200 and the SIB2 additionally the target may reset Never connect or disconnect the SIB2 with power applied to the CM7200 The SIB2 consumes approximately 60 mA from the 5 V supply The target system current consumption therefore increases by this amount while the SIB2 1
61. CTS clear to send pulled low by the RS 232 device to which it 18 talking The CM7000 does not support CTS for the Z180 s Port 1 If the CTS RTS option 18 selected the support software will pull the RTS request to send line high when the receive buffer has reached 80 of its capacity This stops the transmitting device if its CTS is enabled The RTS line goes low again when the receive buffer has drops below 20 of its capacity If the device with which your software is communicating does not support CTS and RTS tie the CTS and RTS lines on the CM7000 side together to make communication possible If CTSO is not used ground it XMODEM File Transfer The CM7000 supports the XMODEM protocol for downloading and uploading data Currently the library supports downloading an array of data in multiples of 128 bytes An application writes data to be uploaded to a specified area in RAM The targeted area for writing should not conflict with the current resident program or data Echo 1 automatically suspended during XMODEM transfer 58 System Development CM7000 Modem Communication Modems and telephone lines facilitate RS 232 communication across great distances If you choose the software s modem option character streams that are read from the receive buffer are automatically scanned for modem commands When a modem command is found the software takes appropriate action Normally the communication package would be in COMMAND m
62. Communication Interface The Z180 incorporates an asynchronous serial communication interface ACSI that supports two independent full duplex channels ASCI Status Registers A status register for each channel provides information about the state of STATO 04H 7 6 5 4 3 2 1 0 RDRF OVRN PE FE RIE coo TDRE TIE R R R R R W R R R W STATI 05H 7 6 5 4 3 2 1 oo RDRF OVRN PE FE RIE TDRE TIE R R 4 R RW R R each channel and allows interrupts to be enabled and disabled DCDO Data Carrier Detect This bit echoes the state of the DCDO input pin for Channel 0 However when the input to the pin switches from high to low the data bit switches low only after STATO has been read The receiver is held to reset as long as the input pin is held high This function is not generally useful because an interrupt is requested as long as DCDO is a 1 This forces the program mer to disable the receiver interrupts to avoid endless interrupts A better design would cause an interrupt only when the state of the pin changes This pin is tied to ground in the CM7000 TIE Transmitter Interrupt Enable This bit masks the transmitter interrupt If set to 1 an interrupt is re quested whenever TDRE is 1 The interrupt is not edge triggered Set this bit to 0 to stop sending Otherwise interrupts will be requested continu ously as soon as the transmitter data register is empty TDRE
63. Development Board CM7000 Table G 1 lists the functions of the Development Board s headers and their jumper settings Table G 1 Development Board Headers and Jumpers Description RS 232 programming port H2 JP1 JP2 JP4 JP5 Connects to H3 on the CM7100 This header has no I O Connect for 512K SRAM No connections Connect for 32K or 128K factory default SRAM Not used Program at 19 200 bps factory default JP3 connected 124 not connected Program at 9600 bps JP3 not connected JP4 connected Program at 57 600 bps JP3 connected JP4 connected Run program in Development Board RAM Not used CM7000 JP3 Connects to socket U3 on the CM7100 Development Board 123 Figure G 2 shows the dimensions of the Development Board 0 125 3 2 3 20 81 13 5 eL nnn nn an Y U U ot Figure 6 2 Development Board Dimensions CM7000 124 Development Board LCD MopuLE Appendix H provides technical details for Z World s LCD Keypad Module used with 9 MHz versions of the CM7000 CM7000 LCD Keypad Module 125 The optional LCD keypad module comes with standoffs for mounting on the Prototyping Board The LCD has two rows of 20 characters The keypad
64. Jumper headers J6 J7 and J8 Run sample program 8 Jumper header J9 No headers jumpered Header J3 must jumpered to run the sample programs the special EPROM or in RAM Headers J10 and J11 are used to set the operating mode or the program ming baud rate for the CM7000 connected to the Prototyping Board Table F 4 lists the jumper configurations Table F 4 Prototyping Board Configuration Jumper Settings for CM7100 Headers Connections Description No connections Program at 19 200 bps 110 connected not connected Program at 9600 bps 111 not connected J11 connected Program at 57 600 bps J10 connected Run program in RAM or in J11 connected EPROM Header J3 must be jumpered to be able to set the program ming rate or run mode with headers J10 and J11 118 Prototyping Board CM7000 Sample Circuits The Prototyping Board contains a few sample circuits The settings of headers J2 J4 affect these circuits as described earlier in this appendix Digital Input Four pushbutton switches SW2 SWS5 on the Prototyping Board simulate asynchronous inputs Four readable headers J6 J9 simulate fixed conditions The Prototyping Board multiplexes these signals with the keypad sense lines and the baud rate headers as shown in Figure F 11 U
65. O Cycles un Wait State Insertion System Power On and Reset Management Watchdog Timer sec WB LI O Addressing eie EROR IHR SUR Appendix A Troubleshooting Out of th Box e RC deter deg Dynamic C Will Not Start essere Dynamic C Loses Serial Link essere CM7000 Repeatedly Common Programming Errors 1 Appendix B Specifications Electrical and Mechanical Specifications Mechanical Dimensions eese Jumpers and Headers sese CMTIOQ i eee er ier ede ent e reete deese 6 7200 Appendix C Memory Map and Interrupt Vectors EM7000 MEMOLY Oa Execution Timing eese iion Input Output Select 7180 Internal Input Output Register Addresses 0x00 Ox3F Epson 72423 Timer Registers 0x4180 0x418F Other Addresses ee tentes Addressing essen CM7000 Table of Contents v Interrupt Vectors ettet 98 Nonmaskable Interrupts 99 99 TNT 99 IN 99 Jump 100 Interrupt ree Reg E
66. PROM is larger than the available target memory no copying will occur and the red Error LED will blink indicating an error Back Panel DIP switches Four DIP switches SW1 SW4 on the Flash Programmer s back panel see Figure I 3 set the size of the master EPROM SW5 indicates whether the Flash Programmer will copy an application to flash EPROM or whether the Flash Programmer will copy the BIOS V DIP Lever Switches Figure I 3 Flash Programmer Side View Showing DIP Switches and Power Supply Input Table I 1 provides the DIP switch settings Table I 1 Flash Programmer DIP Switch Settings for Master EPROM Size EPROM Size SW1 SW2 SW3 SW4 SW5 SW6 32K on on off off copy off 64K on off off off application off 128K off off off off off copy BIOS on 256K off off on off off Always turn off Flash Programmer s power when changing the DIP switch settings 134 Flash Programmer CM7000 Operating Procedure to Copy Application 1 Place the Flash Programmer s power switch in the off position and connect the 12 V power supply to the power jack on the Flash Pro grammer s rear panel as shown in Figure I 3 2 Raise the Flash Program mer s ZIF socket s lever see Figure 1 3 to the ver tical position Place the master EPROM in the 32 pin ZIF socket ofthe Flash Programmer Pin 1 ofthe EPROM should be in the upper part of the socket If yo
67. R 100 Appendix D EEPROM 101 Library Routines sci nh e td odit dr euge 103 Appendix E Serial Interface Board 2 105 Introductions 52652 uie obo a e e etu e ers 106 External Dimensions 107 Appendix F Prototyping Board 109 D SCEIDUOD crie ie E T c RO e n ee DR eos 110 Intetfaces 111 112 Prototyping DDR RH Hoe HERES edi 113 0 114 7 115 Jumpers and 116 Sample iod e eatur ded 119 Digital Input 2 moet duce aaa eee 119 Digital OUMU ania e 120 Appendix G Development Board 121 Appendix H LCD Keypad Module 125 The LCD Driver ei dec des 128 The Keypad Driver 129 Appendix Flash Programmer 131 Introduction Gee aec ede e ee ied 132 Nonremovable Flash EPROM een 132 Requirements 133 Selecting a Master 133 EPROM ael 133 Back Panel DIP switches 0 0 134 vi Table of Contents CM7000 Operating Procedure to Copy Application 135 BIOS Update Recovery Mode essen 136 Troubleshooting eei Neth alioi e 137 CM7100 Compatibility eese 137 Appendix J Sample Applications 139 12 Bit Analog to Digital Converter 140 Optically Isolated Switch Reader sss 143 Relay Circuito RR duRUH CI SU ns 144 24 Bit Parallel uo SER RR RR e d E a 146 8 B
68. SIB2 to header JP1 on the CM7200 Be careful to match the arrow on the connector to Pin 1 of Set the baud rate of the host PC s COM port to 9600 bps 19 200 bps or 57 600 bps Reconnect power to the system As a minimum the power supply must have regulated 5 V and GND for the CM7200 The system is now ready for programming 32 Getting Started CM7000 3 CHAPTER 3 SYSTEM DEVELOPMENT CM7000 System Development 33 General Description The CM7000 15 a complete system engine that contains the microprocessor and memory around which a controller is built Figure 3 1 shows a block diagram of the CM7100 EEPROM m Decoder gt CS1 CS6 0 19 2180 0 5 2 PRTs FT 00 07 Request 2 Serial Ports End 2 DMA Channels SRAM Interrupt MMU 32 512 32 512 lt lt 5 GND Supervisor VRAM 2 gt Power Failure Warning Reset Control cs Battery Backup Control VRAM Figure 3 1 CM7100 Block Diagram Figure 3 2 shows a block diagram of the CM7200 Decoder gt gt CS1 CS6 Clocked 0 19 T Serial 0 S 0 T ES DMA Request 2 PRTs LJ 2 Serial Ports DMA End 2 DMA Channels SRAM Flash Memory Interrupt MMU
69. Z1 LIB contain the functions to support serial communication Refer to the Dynamic C Function Refer ence manual for details Master Slave Networking Z World has library functions for master slave 2 wire half duplex RS 485 9th bit binary communication This protocol is supported only on 7180 Port 1 A network may only have one master which has a board identifica tion address of 0 Slaves should each have their own distinct board number from 1 to 255 Functional support for master slave serial communication follows this scheme 1 Initialize 7180 Port 1 for RS 485 communication 2 The master sends an inquiry and waits for a response from a slave 3 Slaves monitor for their address during the 9th bit transmission The targeted slave replies to the master The binary command message protocol is similar to that used for the new Opto 22 binary protocol The following format is used for a master message slave id len 1 CRC hi CRC lo 60 System Development CM7000 The following format is used for slave s response len 1 1 CRC hi CRC lo The term 1en is the length of the message that follows During a transfer from the master the address byte is transferred in 9th bit address mode and only the slave that has this address will listen to the rest of the message which is sent in regular 8 bit data mode Software Support Table 3 8 lists function calls from NETWORK LIB for use with RS 485 n
70. access the I O registers directly data value outport CNTLAO 92 Memory and Interrupt Vectors inport CNTLAO data value CM7000 Execution Timing The times reported in Table C 1 were measured using Dynamic C and they reflect the use of Dynamic C libraries The time required to fetch the argu ments from memory but not to store the result is included in the timings The times are for a 9 216 MHz clock with 0 wait states Table C 1 CM7000 Execution Times for Dynamic C Operation SEE Time DMA copy per byte 0 73 Integer assignment 1 5 3 4 Integer add j k 4 4 Integer multiply j k 18 Integer divide j k 90 Floating add p q typical 85 Floating multiply 113 Floating divide 320 Long add 1 m 28 Long multiply 1 m 97 Long divide 1 m 415 Floating square root sqrt q 849 Floating exponent exp 2503 Floating cosine cos 3049 The execution times be adjusted proportionally for clock speeds other than 9 216 MHz Operations involving one wait state will slow the execu tion speed about 25 CM7000 Memory Map and Interrupt Vectors 93 Input Output Select Map The Dynamic C library functions and IRES in the BIOS LIB library allow bits in the I O registers to be tested set and cleared Both 16 bit
71. ailable EPROM CM7100 32 pin socket accommodates up to 512K EPROM CM7200 128K flash EPROM at 128 bytes sector 256K factory installed flash EPROM is also available I O support six chip select lines supporting 64 addresses each control the application s hardware Low electromagnetic interference Software written for either CM7100 or CM7200 Series is binary compatible with the other Options The CM7000 is available with two types of memory CM7100s have ROM and CM7200s have flash EPROM CM7100 Series Table 1 1 lists the features of each model in the CM7100 Series Table 1 1 CM7100 Series Features Features 7100 18 432 MHz clock 128K SRAM 512 byte EEPROM real time clock and ADM691 supervisor 7110 7100 with 9 216 MHz clock CM7120 CM7100 with 9 216 MHz clock and 32K SRAM CM7130 7100 with 9 216 MHz clock and 32K SRAM Without ADM691 supervisor real time clock and EEPROM 14 Overview CM7000 CM7100 is available in one of the models listed in Table 1 1 or part of the Evaluation Kit The Evaluation Kit contains the following items e CM7110 with special EPROM containing sample programs Prototyping Board Manual with schematics cables AC adapter trial version of Dynamic C development software The trial version of Dynamic C included with the Evaluation Kit contains only the libraries associated with the Evaluation Kit Once a decision is
72. and 8 bit I O addresses can be used Z180 Internal Input Output Register Addresses 0x00 0x3F The internal registers for the I O devices built into to the 7180 processor occupy the first 40 hex addresses of the I O space These addresses are listed in Table C 2 Table 2 2180 Internal Registers Addresses 0x00 0x3F Address Name Description Serial Channel 0 Control Register A 0x00 CNTLAO 0x01 CNTLAI Serial Channel 1 Control Register A 0 02 CNTLBO Serial Channel 0 Control Register B 0 03 CNTLBI Serial Channel 1 Control Register B 0 04 STATO Serial Channel 0 Status Register 0 05 5 Serial Channel 1 Status Register 0 06 TDRO Serial Channel 0 Transmit Data Register 0 07 TDR1 Serial Channel 1 Transmit Data Register 0 08 RDRO Serial Channel 0 Receive Data Register 0 09 Serial Channel 1 Receive Data Register 0x0A CNTR Clocked Serial Control Register OxOB TRDR Clocked Serial Data Register 0 0 TMDROL Timer Data Register Channel 0 least 0x0D TMDROH Timer Data Register Channel 0 most 0 0 RLDROL Timer Reload Register Channel 0 least OxOF RLDROH Timer Reload Register Channel 0 most 0 10 Timer Control Register 0 11 0 13 Reserved 0 14 TMDRIL Timer Data Register Channel 1 least 0 15 TMDRIH Timer Data Register Channel 1 most 0 16 RLDRIL Timer Reload Regi
73. ate for each channel CNTLBO 02H and CNTLB1 03H 7 6 5 4 3 2 1 0 2 ssi sso R W R W R W R W R W R W R W R W SS Source Speed Select Coupled with the prescaler PS and the divide ratio DR the SS bits select the source internal or external clock and the baud rate divider as shown in Table 3 11 Table 3 11 Baud Rate Divide Ratios for Source Speed Select Bits 552 551 sso Divide Ratio 1 2 4 8 16 32 64 external clock ere c not exceed system clock 40 68 System Development CM7000 The prescaler PS the divide ratio DR and the SS bits form a baud rate generator as shown in Figure 3 17 Prescaler Baud Rate PS Divider 10 1 or to 30 64 Figure 3 17 2180 Baud Rate Generator DR Divide Ratio This bit controls one stage of frequency division in the baud rate generator If 1 then divide by 64 If 0 then divide by 16 This is the only control bit that can affect the external clock frequency PEO Parity Even Odd This bit affects parity 0 even parity 1 odd parity It is effective only if MODI is set in CNTLA parity enabled ICTS PS Clear to Send Prescaler When read this bit gives the state of external pin CTS 0 low 2 high When CTS is high RDRF is inhibited so that incoming receive characters are ignored When written this bit has an en
74. below 4 5 V to 4 75 V Figure F 8 illustrates the reset schematically to CPU and RTC 5 1010 to U5 and other devices CM7200 T Figure F 8 Reset Operation 114 Prototyping Board CM7000 Dimensions Figure F 9 shows the Prototyping Board s dimensions 0 58 15 dia 4 0 60 0 gs 15 2 152 lt 0 22 0187 dia 4x 0 22 5 6 4 75 5 6 p 4 7 oO 120 Of Figure 9 Prototyping Board Dimensions CM7000 Prototyping Board 115 Jumpers and Headers Figure F 10 shows the location of headers on the Prototyping Board 0 0 SmartCore Evaluation Board Configuration Jumpers Programming Port Serial Port Figure F 10 Prototyping Board Headers 116 Prototyping Board CM7000 Table F 1 describes the headers Table F 1 Prototyping Board Headers Description LCD display LCD Keypad module H2 Keypad on LCD Keypad module H3 Connection for header H2 on CM7000 H4 RS 232 programming port H5 RS 232 serial port Power supply input jack Headers J2 J4 are used to configure the Prototyping Board when develop ing an application for the CM7100 Table F 2 provides the jumper configurations Table F 2 Prototyping Board Configuration Jumper Settings for CM7100 Header Description 12 Connected factory default enables output to the LEDs and buzzer tw
75. braries for Z180 Port 0 and Port 1 The following functional support for serial communication is included nitialing the serial ports Monitoring and reading a circular receive buffer Monitoring and writing to a circular transmit buffer Anecho option CTS clear to send and RTS request to send control XMODEM protocol for downloading and uploading data Amodem option CM7000 System Development 57 Receive Transmit Buffers Serial communication is easier with a background interrupt routine that updates receive and transmit buffers Every time a port receives a charac ter the interrupt routine places it into the receive buffer A program can read the data one character at a time or as a string of characters terminated by a special character A program sends data by writing characters into the transmit buffer If the serial port is not already transmitting the write functions will automatically initiate transmission Once the last character of the buffer is sent the transmit interrupt is turned off A high level application can write data one character at a time or in a string Echo Option If the echo option is turned on during initialization of the serial port any character received is automatically echoed back transmitted out This feature is ideal for use with a dumb terminal and also for checking the characters received CTS RTS Control The Z180 s hardware constrains its Port 0 to have the
76. can be altered under program control The addresses are given here in hex relative to the start of the interrupt vector page as determined by the contents of the I register These are the default interrupt vectors set by the boot code in the Dynamic C EPROM Table C 5 Interrupt Vectors for Z180 Internal Devices Address Name Description Used for power failure detection INTO Available for use 0 00 Available for use as expansion bus attention vector 0x02 INT2 VEC Reserved for Development Board CM7100 not available for use on CM7200 0 04 PRTO VEC PRT Timer Channel 0 0 06 PRT1 VEC PRT Timer Channel 1 DMA0 VEC DMA Channel 0 Ox0A DMA1 VEC DMA Channel 1 0 0 CSI O VEC Available for programming 7200 not available for use on CM7100 OxOE SERO VEC Asynchronous Serial Port Channel 0 0x10 SER1 Asynchronous Serial Port Channel 1 To vector an interrupt to a user function in Dynamic C use a directive such as the following SINT VEC 0x10 myfunction The above example causes the interrupt at offset 10H Serial Port 1 of the 7180 to invoke the function myfunction The function must be declared with the interrupt keyword as shown below interrupt myfunction 24 Refer to the Dynamic C manuals for further details on interrupt functions 98 Memory and Interrupt Vectors CM
77. chottky diode clamps neg levels to IN 030 gas 5 85 V 25 Digital 5 1 kQ 5 47 V 40 C ae Vo Resistor sets Line max current Schottky diode ntroller 0 01 51V 033yF ZX clamps neg levels to Controlle Cap filters 0 35 V 25 C RF spikes 0 47 V 40 C COM Vss e e e 1N4003 IN 5 1 KQ 1N4003 Digital o e 1 0 Resistor sets Line max current 0 001 pF 51 0 33 pF AiG Controller Cap filters RF spikes COM Vss e Figure 11 Digital I O Protection Circuits 152 Sample Applications CM7000 SAMPLE PROGRAMS Appendix presents sample programs included in the special EPROM with the Evaluation Kit and other sample programs to illustrate the development of applications for the CM7000 CM7000 Libraries and Sample Programs 153 Sample Programs Special EPROM The special EPROM that comes with the Evaluation Kit contains eight sample programs Select a sample program to run by configuring the jumpers on the Prototyping Board according to Table K 1 See CM7100 Method 1 Prototyping Board in Chapter 2 Getting Started for complete details on how to set up the CM7110 Appendix Prototyping Board provides more information on the Prototyping Board Table K 1 Prototyping Board Jumper Settings for Sample Programs in Special EPROM Operation Run sample program 1 Run sample program 2 Hea
78. ck 18 432 MHz SRAM 128K standard surface mounted EPROM 7100 option up to 512K Flash EPROM CM7200 128K 7100 512 bytes Counters Two using DMA channels Serial Ports Two TTL level UARTs Serial Rate Up to 57 600 bps Watchdog Yes Time Date Clock Yes Backup Batter Header H2 pin 3 provides connection for user P y supplied backup battery on main controller 86 Specifications CM7000 Mechanical Dimensions Figure B 1 shows the mechanical dimensions for the CM7100 and the CM7200 0125 dia 81 8 1 57 40 1 8 46 7100 31 8 6 1 5g b CM7200 Figure 1 Mechanical Dimensions 46 e Y CM7000 Specifications 87 Jumpers and Headers CM7100 Table B 2 lists the roles of the headers and presents the jumper configura tions for the CM7100 The header locations are shown in Figure B 2 Table B 2 CM7100 Headers and Jumpers Header 2 soldering Description 5 point interface extension with plated through holes for easy H2 40 pin interface fits in socket H3 on the Prototyping Board only for the Development Board with EPROM removed Generally disregard J1 However if a backup battery or super capacitor is used make sure J1 is not connected J1 may be jumpered to ground VBAT only when the ADM691 supervisor nected is not i
79. data register 66 receiver data register full 66 receiver enable 68 Index 163 receiver interrupt enable 66 receiver interrupts 64 65 66 receiver shift register 66 registers 94 relay circuit 97 144 reload vec 60 request to send 67 RESET eee 79 reset 35 42 49 52 55 78 114 delay x aeter teta 79 management 79 Prototyping Board 114 threshold 79 resistors PTC 151 RETN guide 49 RJZ12 106 uie eue 42 ROM programmable 21 23 24 25 27 28 29 34 39 43 44 60 62 117 118 RS 232 communication 21 28 34 56 57 58 59 111 expansion card 60 handshaking 57 serial 57 RS 485 communication 34 56 57 60 111 66 See real time clock RIS uei 28 57 58 59 a 67 RUN 28 29 117 running program in 23 26 27 in special EPROM 23 26 27 RX line iussus 59 RXS side Re 66 S sample applications 140 143 144 146 147 149 164 Index sample circuits sess 14
80. date values into the RTC The Dynamic C Function Reference manual describes these functions and the associated data structure tm The following points apply when using the RTC 1 The AM PM bit is 0 for AM 1 for PM The RTC also has a 24 hour mode 2 Setthe year to 96 for 1996 97 for 1997 and so on Constantly reading the in a tight loop will result loss of accuracy CM7000 System Development 47 7000 has optional ADM691 supervisor chip whose location is shown in Figure 3 9 CM7100 CM7200 J2 Ji 6 pe PAL Ji U8 08 k 05 2180 2180 06 PAL Tie VBAT to GND if there is no battery or super capacitor and the ADM691 is installed Figure 3 9 Locations of ADM691 Supervisor Chip and Associated Headers If the ADM691 supervisor chip is installed and there is no battery or super capacitor connect the VBAT input to ground using the VBAT pin of header H2 as shown in Figure 3 9 Alternatively for the CM7100 a jumper may be soldered across header J1 The grounding keeps the ADM691 VIN from floating If the CM7100 ADM691 supervisor chip is removed solder a jumper across header J2 J2 connects the RAMCS signal to the RAM Further you must connect to
81. der Configuration Jumper header J6 Jumper header J7 Run sample program 3 Run sample program 4 Run sample program 5 Run sample program 6 Run sample program 7 Run sample program 8 Jumper headers J6 and J7 Jumper header J8 Jumper headers J6 and J8 Jumper headers J7 and J8 Jumper headers J6 J7 and J8 Jumper header J9 Run program in RAM No headers jumpered Header J3 on the Prototyping Board must jumpered to run the sample programs in the special EPROM or in RAM The source code for the sample programs 15 included on the diskette containing the trial version of Dynamic C in the DCBBNSAMPLESNCM71 72 directory The eight sample programs are described below Sample Program 1 SC1LAD C translates the inverse of the state of the pushbutton switches to the LEDs on the Prototyping Board An LED is on when the adjacent pushbutton switch is pressed down and goes off when the pushbutton switch is not pushed down The software actuates the beeper for 100 ms every time a pushbutton switch is pushed down 154 Libraries and Sample Programs CM7000 Sample Program 2 5 changes the blinking rate of the LEDs on the Prototyping Board Press the pushbutton switch adjacent to an LED to increase the blinking rate of that LED the maximum rate 1 10 flashes second The blinking rate decreases when the adjacent push button switch is not pressed the minimum rate is 1 flas
82. dule CM7000 Connect the cables from the LCD keypad module to the Prototyping Board before mounting the LCD keypad module on the Prototyping Board First put the keypad flat cable in socket H2 Clamp it securely Then connect the short 14 wire ribbon cable from the header under the LCD the arrow matches pin 13 to header H1 of the Prototyping Board the arrow must match pin 1 When installed the LCD keypad module will extend out from the Prototyping Board as shown in Figure H 3 Keypad LCD Prototyping Board Figure H 3 LCD Keypad Module Mounted on Prototyping Board CM7000 LCD Keypad Module 127 The LCD Driver Two three state buffers drive the LCD from header H1 on the Prototyping Board The buffers are shown in Figure H 4 LCD Header R3 R4 H1 1kQ 620 a s 135914 11 12 ALCDO D 0 7 WRX lt lt 95910 LCDX DLCDO 75698 DLCD1 DLCD2 5608 DLCD3 3 4 DLCD4 DLCD5 1502 DLCD6 DLCD7 RD 74HC245 3 State Buffer A 0 18 0 17 16 15 5 14 1000 13 12 11 4 7 kQ 10 kQ 1009 CS3 e mE 4 74HC245 3 State Buffer Figure H 4 Prototyping Board LCD Buffers The buffers are enabled when header J4 on the Prototyping Board is jumpered this is the factory default setting When enabl
83. e interface requires only three readily available ICs CS4 RESET 424V 74HC259 24 V 24 24 a 1 3 2 1 4 SPST SPST 24 24 V 24 241 3 2 1 3 2 1 a 1 4 SPST 4 SPST 4 SPST 4 SPST Relays 24 V lt 500 mA Figure J 5 Eight Relay Interface Circuit Each relay occupies a unique I O address and is activated or deactivated by writing a 1 or 0 respectively to that address Because CS4 is used relay 1 is at address 0 40 relay 2 is at 0 40 and so on The software to operate the relays is very simple outport 0x40C0 1 Energize relay 1 outport 0x40C4 0 Deenergize relay 5 Although the ULN2803 sinking driver has a maximum current drive capability of 500 mA per channel its thermal resistance from junction to case is 55 C W Table J 1 describes the heating characteristics of the ULN2803 at various currents The part is rated for a maximum junction temperature of 125 C It is a good idea to limit the coil current to less then 150 mA per relay when operating all eight relays simultaneously which will produce a 66 C junction temperature rise 144 Sample Applications CM7000 Table J 1 ULN2803 Charactreristics at Selected Currents Channel Current mA Vcr V Power W Channel Junction Temperature Rise 300 400 500 CM7000
84. e possibly corrupt a program or data Read operations access the flash EPROM just like an EPROM The access time must be less than 70 ns for the 18 MHz CM7200 or less than 90 ns for 9 MHz versions The CM7200 uses a portion of its flash EPROM to simulate the 512 bytes of EEPROM However the access times for the flash EPROM are different from EEPROM The CM7200 executes the same Dynamic C EEPROM function calls as the CM7100 accommodating hardware differences in its BIOS An 8 byte section of the flash EPROM contains the CM7200 BIOS Dynamic C software drivers handle the read and write operations Flash EPROM is rated for 10 000 writes In practice flash EPROM has performed for up to 100 000 writes Z World recommends that any writes to the flash EPROM be made by the programmer rather than automatically by the soft ware to maximize the life of the flash EPROM If you modify the driver software do not overwrite the sections of the flash EPROM that contain the BIOS and that simulate the EEPROM CM7000 System Development 45 SRAM The RAM is not socketed but is soldered to the board as shown in Fig ure 3 8 CM7000s may be ordered with 32K or 128K RAM already in stalled CM7000s with 512K RAM are also available U2 RTC 0 01000010001 U3 Flash EPROX EEPROM 7100 7200 Figure 3 8 Locations of CM7100 and 7200 SRAM ROM addresses range f
85. ed 3 governs the circuit CS3 represents addresses from 0x4080 to 0x40BF The C expression CS3 1 is equivalent to 0x4081 See Appendix F Prototyping Board for more information Q pp yping on header configurations The Dynamic library CM71 72 LIB provides routines to cu i operate the LCD and keypad These functions are described in the Dynamic C Function Reference manual 128 LCD Keypad Module CM7000 The Keypad Driver To operate the keypad low level software first negates a keypad row line KHO or KH1 then reads the keypad sense lines If a key is pressed in that row the sense line will be a 0 Doing this operation for each row identifies which key had been pressed The keypad sense lines are multiplexed with the pushbutton switches and headers CS2 controls the multiplexers and a jumper connection across header 13 enables them Reading address CS2 0 returns the keypad sense lines for the recently selected row in bits 0 5 low order ICS1 and address lines A0 A2 select the keyboard row lines Address CS1 6 0x4006 is row 1 and address 1 7 0 4007 is row 0 Writing a 1 to data bit 0 activates the row line A V See Appendix Prototyping Board for more information on header configurations Figure H 5 on page H 6 shows the configuration of the keypad multiplexers on the Protoyping Board Note the words menu item field up down and help These c
86. ent 97 05 7100 48 49 53 99 7 53 06 CM7100 80 97 Development Board 25 27 CM7200 irit 97 07 100 80 97 ULN2803 sinking driver 144 uploading data 57 58 V VBAL zung 53 54 79 threshold sss 79 aterert en 5 voltage regulator Prototyping Board 110 VRAM 48 49 53 54 166 Index wait states 76 77 watchdog timer 29 35 49 52 79 timeout sess 79 ewe 52 X XMODEM protocol 57 58 Z Z180 t 34 internal I O registers 94 Serial Port 0 58 60 155 interrupt handling 59 Serial Port 1 60 98 156 initialization 60 Serial Ports 0 and 1 57 2180 62 ZIF socket Flash Programmer 135 CM7000 Z World 2900 Spafford Street Davis California 95616 6800 USA Telephone Facsimile Web Site E Mail 530 757 3737 530 753 5141 http www zworld com zworld zworld com Part No 019 0018 Revision F Printed in U S A
87. ent has been completed recompile the program for An EPROM 1 burned in a separate operation and is then installed in the EPROM socket on the CM7100 20 Getting Started CM7000 CM7100 Method 1 Prototyping Board l 12 8 Check header J3 on the micro J3 processor side ofthe CM7100 Check to make sure the power to the Prototyping Board is not con nected The surface mounted jumper should connect pins 2 3 to re 6 the 128K memory of the PAL J special EPROM This factory default setting is shown in Fig Figure 2 1 7100 Header J3 ure 2 1 Configured for Special EPROM Plug the CM7100 into the Prototyping Board as shown in Figure 2 2 Plug header H2 of the CM7100 into connector H3 of the Prototyping Board Pins 1 of the header and connector must match The CM7100 will hang over the battery on the Prototyping Board For maximum stability install the supplied standoff between the CM7100 and the Prototyping Board Special EPROM 680 295x CM7100 H2 Standoff il H3 Power Jack Battery Prototyping Board Figure 2 2 Connecting CM7100 to Prototyping Board If using the CM7110 from the Evaluation Kit make sure the CM7110 has the special 32 pin RAM EPROM Z World part num ber 680 295x installed at U3
88. er bits in byte 72 0x74 mask 0x0 FF Active bit s of input byte one bit suffices 0x75 polarity 0 1 Polarity of input bit 28 Getting Started CM7000 Modify the Dynamic EPROM file in your Dynamic C directory and burn a new EPROM with the appropriate new data When a system resets the Dynamic C monitor in the EPROM consults the 6 bytes If the monitor finds valid data the system will start operating according to the data The monitor will attempt to read the specified input port If it is successful the monitor will either enter programming mode communicating with Dynamic C in PC or run the program stored in the CM7100 s RAM For example the C structure 70 0x00 serial channel 0 71 Ox10 109 200 bps 72 73 0x4040 CS2 74 0x80 active bit is bit 7 75 0x00 active bit 0 69 PROGRAM mode else RUN mode would work and might use an input port such as the one shown in Figure 2 14 45V 10ko 52 ma cyo ao 74HC32 D7 44 Jumper 74HC2 5 Connected for PROGRAM mode 57 Open for RUN mode Figure 2 14 Input Port With the standard CM7100 BIOS 2903 or later setting the I O address bytes 0x72 and 0x73 to 0x0000 will force the CM7100 into development mode This setting eliminates the need to use a RUN PROGRAM jumper Direct development is not supported by the BIOS of the CM7110 included in the CM7100 Evaluation Kit Safeguards The following safeg
89. er empty or receiver data register full If an error condition occurs on receive the routine must clear the error flags and take appropriate action if any If the CTS line is used for flow control transmission of data is automatically stopped when CTS goes high because the TDRE flag is disabled This prevents the driver from transmitting more characters because it thinks the transmitter 1s not ready The transmitter will still function with CTS high but exercise care because TDRE is not available to synchronize loading the data register TDR properly An interrupt driven port works as follows The program enables the receiver interrupt as long as it wants to receive characters The transmitter interrupt is enabled only while characters are waiting in the output buffer When an interrupt occurs the interrupt routine must determine the cause receiver data register full transmitter data register empty receiver error or IDCDO pin high channel 0 only None of these interrupts is edge triggered Another interrupt will occur immediately if interrupts are re enabled without disabling the condition causing the interrupt The signal IDCDO is grounded on the CM7000 Table 3 10 lists the interrupt vectors Table 3 10 Serial Port Interrupt Vectors Address Name Name Description SERO VEC Z180 Serial Port 0 higher priority NN SER1 VEC Z180 Serial Port 1 64 System Development CM7000 Asynchronous Serial
90. ese important points in mind 1 The EPROM size must be larger than the size of the application size 2 The DIP switch configuration must match the size of the EPROM not the size of the flash EPROM on the CM7200 3 Even if the application will fit in the CM7200 s flash EPROM the EPROM s size must be equal to or smaller than the size of the flash EPROM For example if you attempt to transfer a 32K application contained in a 256K EPROM to a 128K CM7200 flash EPROM the Flash Programmer will signal an error because the 256K EPROM is larger than the 128K flash EPROM In general the safest course is to use an EPROM that is the same size as the CM7200 s flash EPROM EPROM Sizes The Flash Programmer supports EPROM with standard pinouts 32K and 64K 28 pins and 128K and 256K 32 pins If your proposed master EPROM pinouts match the pinouts shown in Figure I 2 the EPROM will work in the Flash Programmer NC VPP or A15 vec A17 or NC A12 A14 A14 A13 A13 A6 A8 A8 AS 9 A9 Att A3 JOE OE 2 10 10 AO D7 D7 DO D6 D6 D1 D5 D5 D2 D4 D4 GND D3 D3 Figure l 2 EPROM Pinouts Recognized by Flash Programmer CM7000 Flash Programmer 133 The 7200 currently supports 128K and 256 flash EPROM Before copying begins the Flash Programmer compares the size of the as indicated on the DIP switches with the size of the flash EPROM If the E
91. etworks Table 3 8 RS 485 Network Software Functions Function op init z1 Description Initializes 7180 Port 1 for RS 485 9th bit binary communication check opto command Checks for a valid and completed command or reply in the receive buffer sendOp22 Master sends a message and waits for a reply ReplyOpto22 Slave replies to the master s inquiry misticware Gateway for RS 485 9th bit binary communication optodelay Produces a delay of 50 ms uses the suspend function if the RTK is in use rbuf_there Monitors the receive buffer for a completed command or reply _ 21 Called misticware to initiate transmission 21 Called by misticware to ready the receiver for data reception op kill 21 Kills Z180 Port 1 21 op int Interrupt service routine for Z180 Port 1 used in master slave networking A Refer to the Dynamic C Function Reference manual for more information on these functions CM7000 System Development 61 Use of the Serial Ports If you plan to use the serial ports extensively or if you intend to use synchronous communications Z World recommends that you obtain copies of the following Zilog technical manuals available from Zilog Inc in Campbell California Z180 MPU User s Manual Z180 SIO Microprocessor Family User s Manual To get started Z World provides these low level utility functions int sysclock i
92. g Development 7100 7100 7100 Dev Both Typ Typ Max Board Board Boards cess of of 3 5 3 of 3 54 0 0 0 0 0 3 55 0 o 3 56 0 0 0 0 0 3 18 0 0 5 10 8 3 23 E olol3 3 0 3 of 0 0 0 RXA1 0 0 5 10 5 0 5 1 olols Nae mm 5 0 5 RXAO 0 o 5s 10 5 0 5 0 o 5 10 5 0 5 lREQQ 0 0 0 0 0 0 0 0 0 0 0 0 0 12 24 10 15 2 15 0 0 5 10 5 0 5 of 0 0 o 0 6 0 o o 0 PFI 27 36 0 o a a VBAT 5 10 0 5 5 5 7000 Design Considerations 73 Table 4 2 7200 Capacitive Loading Signal A01 A02 A03 A04 A05 DO D1 D2 D3 04 05 06 07 CS1 00 CS2 Capacitative Load pF CM7200 Proto Typ Max Max Board 26 44 12 40 38 26 44 3 10 29 26 44 3 10 29 26 44 0 0 26 14 20 0 14 14 20 0 0 14 33 54 9 30 42 28 46 6 20 34 28 46 6 20 34 28 46 6 20 34 16 22 6 20 32 16 22 6 20 32 16 22 6 20 32 16 22 6 20 32 17 32 3 10 20
93. g a function s definition with an instance of its use in a listing Notending statements with semicolons Not inserting commas as required in functions parameter lists Leaving out ASCII space character between characters forming a different legal but unwanted operator Confusing similar looking operators such as amp amp with amp with and with nadvertently inserting ASCII nonprinting characters into a source code file 84 Troubleshooting CM7000 B SPECIFICATIONS Appendix B provides comprehensive CM7000 physical electronic environmental specifications CM7000 Specifications 85 Electrical and Mechanical Specifications Table B 1 lists electrical mechanical and environmental specifications for the CM7100 and CM7200 cores Table B 1 CM7100 and CM7200 General Specifications Parameter Specification 1 80 x 2 05 x 0 85 46 52 22 Board Size 1 80 x 2 05 x 0 63 46 52 18 Operating Temperature 40 to 70 Humidity 5 to 95 noncondensing Power 5 V DC 100 mA 9 216 MHz 5 V DC 130 mA 18 432 MHz Configurable I O Six groups of 64 I O addresses Digital Inputs See Configurable I O Digital Outputs See Configurable I O Analog Inputs No Analog Outputs No Resistance Measure ment Input No Processor Z180 Clo
94. g written to the CM7200 s flash EPROM The green bottom LED will blink to indicate that the written data are being verified The green bottom LED will shine steadily once the copying 18 completed successfully You can turn off the power and remove the programmed CM7200 8 If the red top LED lights an error has occurred Refer to the Trouble shooting section on the next page BIOS Update Recovery Mode The Flash Programmer can be used to update the CM7200 s BIOS In the unlikely event that an accidental write to the flash memory has corrupted the BIOS the Flash Programmer can also be used to restore this vital section of code To copy a new BIOS into the CM7200 first burn an EPROM with the Dynamic 29xx BIN where is greater than or equal to 01 found in the Dynamic C BIOS subdirectory Follow the instructions for copying a master EPROM to the CM7200 flash EPROM but set DIP switch SW5 to the on position A BIOS copy takes less than two seconds because only 13K gets copied from the EPROM 136 Flash Programmer CM7000 Troubleshooting If the red top LED remains illuminated an error has occurred and the copying was not successful Table I 2 lists possible solutions to correct the problem Table 2 Flash Programmer LED Error Indicators LED Indicates Remedy Blinking Red DIP switches indi Make sure that DIP switch set cate master ting agrees with the size of the size is master EPROM
95. gure J 9 Digital Noise Filter Serial Port Protection Maxim Sunnyvale CA notes that a serial port pro Output T vides an open door for ov 9 W ervoltages and overcur Input Your rents from the outside 9 W Serial world The extra compo nents in the circuit Fig bd 10 will protect a se add e X rial port against even 30 15 V 117 V AC V Figure J 10 Serial Port Protection 150 Sample Applications CM7000 The solid state Tranzorbs shunt overload currents to ground initially Then after about 0 2 seconds the positive temperature coefficient PTC resistors heat up cutting off current flow The circuit will reset itself when the overload stops General Semiconductor Tempe AZ and General Instruments Hicksville NY sell Tranzorbs Midwest Components Muskegon MI makes PTC resistors Digital I O Protection Motorola s Automotive Product Division Phoenix AZ recommends the three circuits in Figure J 11 to protect low speed digital I O lines against transients three circuits use a 100 kHz low pass filter formed by a 0 01 uF capacitor and 5 1 resistor along with various clamping components The first and simplest circuit uses a zener diode to clamp positive going transients and a Schottky diode to clamp negative going transients However the Schottky diode exhibits 50 mA leakage at 125 C and its forward voltage rises to 0 47 V at te
96. h second Sample Program 3 SC1SEQ C selects an LED blink sequence Press any of the pushbutton switches to select another pattern The software actuates the beeper for 100 ms when a selection is detected Sample Program 4 SC1TIMO C uses the periodic interrupt by Timer 0 to modulate the on off time of the LEDs The LEDs grow brighter then dimmer as the program runs e Sample Program 5 SC1PTTRN C continuously displays an LED pattern using the four LEDs The program starts by displaying a default pattern with all the LEDs alternately on then off Set a new pattern by pressing any pushbutton The LEDs will blink four more times and stop As soon as the beeper sounds press any sequence with the pushbutton switches The beeper will sound after a pause which means the pattern has been accepted The software will resume blinking the LEDs according to the new pattern Sample Program 6 SC1Z0232 C uses Serial Port 0 of 7180 as a simple diagnostic port connected to a dumb terminal Set the PC termianl or communication program for 9600 bps 8 data bits 1 stop bit and no parity Connect a cable from the termianl s COM port to H5 on the Prototyping Board being careful to match the arrow on the 10 pin connector to pin 1 on header H5 The sample program provides the following menu a Toggle LEDs b Beep for 1 second Move time adjust field u Increment time adjust field d Decrement time adjust field Type y
97. he chip in the RAM socket as shown in Figure 2 11 Figure 2 11 Position of 28 Pin Chip in 32 Pin Socket Serial cable to PC 8 Connect the serial cable F Connect one end to the PC Hir COM port Then connect the s 10 pin end to H1 of the w JP2 Development Board as shown S in Figure 2 12 Be careful to match the arrow on the connector to the location of Figure 2 12 Serial Cable Connection pin 1 on header H1 to CM7100 Development Board 9 Reconnect the 9 V power supply to the Prototyping Board The CM7100 is ready for programming unless the jumpers were set in Step 5 to run a program in the Development Board s RAM 26 Getting Started 7000 7100 Method 3 Embedded in System Method 3 assumes that the CM7100 is already mounted in a system and that the CM7100 is properly connected At a minimum regulated power 5 V and ground must be provided The Development Board plugs into the EPROM socket of the CM7100 The Development Board emulates the system EPROM normally installed in the CM7100 providing up to 504K of program space in addition to the RAM on the CM7100 used as a data space The Development Board has its own RS 232 port and communicates directly with the PC during program development 1 Disconnect power from the CM7100 2 If an EPROM is installed in socket U3 on the CM7100 remove the EPROM Plug a Dynamic C de
98. igure 1 Flash Programmer The Flash Programmer socket cannot handle CM7200s that have a header installed at H1 During normal development Dynamic C loads applications into a CM7200 s flash EPROM But once an application has been developed successfully the Flash Programmer facilitates loading the application to CM7200s in production quantities Dynamic C requires a host PC and takes about 1 5 minutes at 19 200 bps to load a 128K application The Flash Programmer operates standalone and takes about 10 seconds to load the same 128K application Nonremovable Flash EPROM The flash EPROM is surface mounted on the CM7200 circuit board This gives the CM7200 a low profile and enhanced reliability However this makes it much harder to remove the flash EPROM to reprogram it The Flash Programmer reprograms the CM7200 s flash EPROM with the flash EPROM remaining soldered to the board 132 Flash Programmer CM7000 The Dynamic development EPROM also be used as a master with the Flash Programmer to update the CM7200 s onboard BIOS This feature will work even if the CM7200 s onboard BIOS has been damaged or corrupted Requirements To load a program into a CM7200 s flash EPROM with the Flash Pro grammer all you need is an original EPROM of the appropriate size containing the compiled application Selecting a Master EPROM When selecting an EPROM from which to transfer an application to a CM7200 s flash EPROM keep th
99. ion program with the following compiler directive VEC SERO routine However if the same serial port is used for Dynamic C programming the program has to be downloaded first with Dynamic C before the address of the serial interrupt service routine is loaded into the interrupt vector table CM7000 System Development 59 That is the service routine must be loaded at runtime The function reload vec int vector int serv function will load the address of the service function into the specified location in the interrupt vector table In this case do not use the INT_VEC directive Once the service routine takes over the program can no longer be de bugged in Dynamic C If you communicate with a serial device other than the Dynamic C pro gramming port on the PC the program has to make sure that the hardware is properly configured before sending any serial messages When you recompile your application programs for EPROM or for download to RAM they will not need to communicate with Dynamic C At this point you may use the compile time directive SINT freely Software Support This section lists functions for Port 0 of the Z180 For Z180 Port 1 simply substitute 21 for 207 in the function name For example the initializa tion routine Z180 Port 0 is called Dinit_z0 The equivalent function for 7180 Port 1 would be Dinit 21 20232 LIB Z1232 LIB MODEM232 LIB AASCZO LIB and AASC
100. it Assert CTS by either connecting the RTS signal of the PC s COM port or looping back the CM7000 s RTS Experiment with each peripheral device connected to the CM7000 to determine how it appears to the CM7000 when powered up powered down and or when its connecting wiring 1s open or shorted 82 Troubleshooting CM7000 Dynamic Will Not Start In most situations when Dynamic C will not start an error message announcing a communication failure will be displayed The following list describes situations causing an error message and possible resolutions Wrong Baud Rate Either Dynamic C s baud rate is not set correctly or the CM7000 s baud rate 1 not set correctly Wrong Communication Mode Both sides must be talking RS 232 Wrong COM Port A PC generally has two serial ports COMI and 2 Specify the one being used in the Dynamic C Target Setup menu Use trial and error 1f necessary Wrong Operating Mode Communication with Dynamic C will be lost when the CM7000 is configured for standalone operation Reconfigure the board for programming mode as described in Chapter 2 Getting Started Wrong Memory Size Jumper J3 on the CM7100 and jumper JP1 on the Development Board set the size of the EPROM and SRAM respectively If all else fails connect the serial cable to the CM7000 after power up If the PC s RS 232 port supplies a large current most commonly on portable and industrial PCs
101. it Digital to Analog Converter essere 147 SRAM Iriterface o iure ERE 149 Protection eoe RENTRER DU QUE 150 Digital Noise 7 7 150 Serial P rt Protection x tere 150 Digital T O Protection ordre REPRE 151 Suppliers of Board Level Protection 151 Appendix K Sample Programs 153 Sample Programs on Special EPROM 154 Other Sample Programs sss 156 Index 157 CM7000 Table of Contents vii Blank viii Table of Contents CM7000 THis MANUAL This manual describes the CM7000 Series core modules their subsystems and the CM7100 Evaluation Kit For ease of reference this manual uses 7000 as a generic term referring to any of the CM7100 or CM7200 Series modules CM7100 refers to any of the CM7100 Series modules and CM7200 refers to the CM7200 Series Specific models are refer enced when appropriate Instructions are also provided for using Dynamic C functions Assumptions Assumptions are made regarding the user s knowledge and experience in the following areas Ability to design and engineer a target system that uses a CM7000 Understanding of the basics of operating a software program and editing files under Windows on a PC Knowledge of the basics of C programming G For a full treatment of C refer to the following texts The C Programming Language by
102. k diagram 34 board layout 16 copying applications to flash EPROM 132 Developer s Kit 16 development setup 30 EEPROM simulated 45 47 102 flash EPROM 14 45 E E E S 36 36 in system development 32 models 5 eee 16 optional accessories 16 Flash Programmer 16 programming 1601008 30 Prototyping Board 30 reset management 79 Serial Interface Board 2 SIB2 07 30 110 VW 45 CNELA 66 68 CNTEBO 62 CNTEB T 62 COM 3 icc 9 30 32 COM port 20 23 26 27 COMMAND mode modem communication 59 command protocol master slave 60 common problems programming errors 84 CM7000 communication Dynamic C 100 initialization routines 60 232 27 28 34 56 57 58 59 111 RS 485 34 56 57 60 111 20 27 28 34 56 57 58 59 60 62 63 64 65 67 68 70 94 111 interrupts 58 master slave 60 CR2325 backup battery 53 ORG a hein a eter 61 CSI O clocked serial I O
103. know when power is about to fail Memory protection feature prevents writes to RAM when power is low Supports battery or super capacitor backup Handling Power Fluctuations During a normal power down an interrupt service routine 1 used in response to a nonmaskable interrupt to save vital state information for the application for when power recovers The amount of code that the interrupt service routine can execute depends on the rate of decrease of voltage to the controller Theoretically a power failure would cause a single NMI Then the inter rupt service routine would restore the previous state data when the voltage recovers However fluctuations in the DC input line could cause the supervisor IC to see multiple crossings of the 1 3 V input power reset threshold These multiple negative edge transitions would in turn cause the processor to see multiple NMIs When the Z180 generates an NMI it saves the program counter PC on the processor s stack It next copies the maskable interrupt flag IEFI to IEF2 and zeroes IEF1 The Z180 will restore saved state information when it executes a RETN return from nonmaskable interrupt instruction A y See Appendix C Memory I O Map and Interrupt Vectors for more information on interrupts CM7000 System Development 49 Ideally the processor should be able to pop the stack and return to the location where the program was first interrupted But the original IEF1
104. larger than flash Use an EPROM that is the same EPROM size size or smaller than CM7200 s flash EPROM Steady Red Verification failed Indicates defective CM7200 If re peated attempt to program produces steady red LED contact Z World for assistance Red Yellow Watchdog timed out Make sure CM7200 is properly and Green seated in socket blinking once Make sure spring pin makes con tact with the CM7200 Make sure DIP switches are set correctly Make sure master EPROM is properly seated in ZIP socket with lever in horizontal position CM7100 Compatibility The Flash Programmer 1 not compatible with the CM7100 When compil ing source code intended for a CM7200 be sure to use a CM7200 as the target not a CM7100 N Never plug a CM7100 into the Flash Programmer CM7000 Flash Programmer 137 Blank 138 Flash Programmer CM7000 APPENDIX J SAMPLE APPLICATIONS Appendix J presents several circuits and describes them briefly These sample circuits demonstrate some of the ways the CM7000 can be used CM7000 Sample Applications 139 12 Bit Analog to Digital Converter The circuit shown in Figure J 1 serves as an A D converter for the CM7000 7 Do ________ ics4 gt 74 2 74HC259 RESET 1 mp 6 LTC1294 74HC244 10 pF ICL7662 AV vE 3
105. lation is software compatible with the CM7100 s Dynamic C EEPROM function calls See Appendix D EEPROM for more information on the software function calls and details about write protecting the CM7100 EEPROM CM7000 System Development 35 Interface Description The CM7000 physical interface to a controller is a 40 pin header H2 with a 5 pin extension H1 Figure 3 3 shows the location of header H2 and extension H1 Figure 3 3 Location of Header H2 and Extension H1 The 40 pin header H2 plugs directly into a 40 pin connector on the controller s printed circuit board The connector on the Prototyping Board provides an example of this arrangement The headers use 0 025 square pins on 0 1 centers The 5 pin interface extension H1 comprises five plated through holes allowing an additional 5 pin header to be added if needed Figure 3 4 provides the pinouts for header H2 and extension H1 40 Pin Interface Extension H2 H1 GND 1 o2 5 regulated 1f GND VBAT 01 4 PFI 2 VRAM 948 RESET 8 o TENDO 02 8 055 o TEND1 9 o 10 CS6 5 0 D4 11 1 12 51 05 13 14 CS2 signals active low D6 15 o 16 DO 54 17 o 18 AO 1 19 o 20 CS3 1 21 o 22 INTO 23 24 A2 IWAIT 25 26 4 07 27 28 IWR 29 30 IORQ DREQO 31 o 32 RD DREQ1 33 o 34 TXA1
106. le for k 0 k lt 1000 k do 1000 sawtooth cycles for 1 0 1 lt 255 1 outport 0x4100 i ramp up delay delay determines slop outport 0x4100 0 back to 0 148 Sample Applications CM7000 SRAM Interface The circuit in Figure J 8 demonstrates a simple way to add more memory to a system You can obtain 14 address lines using data bits 0 7 address lines 0 5 and two chip selects First the 74HC374 latches the data bits written with CS4 Then the SRAM is written or read using address lines and CS5 0 5 D 0 7 0 7 CS5 RD Figure J 8 Adding SRAM to CM7000 System CM7000 Sample Applications 149 Protection Circuits The circuits described here have been proven in the field Nevertheless they are not the only way nor necessarily the best way to protect a controller from unwanted natural and man made interference in a particu lar application Z World does not guarantee that these circuits will protect personnel and equipment Ensuring such protection 1s the buyer s responsibility Digital Noise Filter Analog Devices Norwood MA recommends the simple power rail filter shown in Figure J 9 to help keep digital noise out of sensitive analog circuitry RAW 45 V DIGITAL IRCUITRY GND Ferrite Beads 3 Turns Fair Rite 42677006301 Clean Analog GND Fi
107. ls the end ofa TENDI transfer on channel 0 or 1 Directly connected to 7180 TTL CMOS compatible TXAO Out Transmit Serial data for channels 0 and 1 Directly TXAI connected to 2180 TTL CMOS compatible RXAO In Receive Serial data for channels 0 and 1 Directly RXAI connected to 2180 TTL CMOS compatible 0 In Clear to send channel 0 Serial control signal Channel 0 will not transmit when this line is high Directly connected to 7180 TTL CMOS compatible RTSO Out Request to send channel 0 Serial control signal Directly connected to Z180 TTL CMOS compatible continued CM7000 System Development 37 Table 3 1 CM7000 Interface Signals concluded Signal Direction Description VBAT In Battery voltage Connects to the ADM691 supervisor Must be grounded if no battery installed VRAM Out Battery backed supply voltage for RAM real time clock and other devices PFI In Power failure input Connects to the ADM691 supervisor which generates a nonmaskable interrupt NMJ when this line falls below 1 3 V 0 05 V RESET Bi System reset Driven by the ADM691 supervisor Must be pulled up when supervisor is not installed E Out 6800 compatible timing reference Directly connected to Z180 TTL CMOS compatible 38 System Development CM7000 CM7000 Subsystems This section describes the various subsystems and their signals Source code software drivers are available for m
108. m development 20 PROGRAM mode 28 29 programmable ROM 7 21 23 24 25 27 28 29 34 39 43 117 118 programmable timers See PRTs programmable timers programming esee 20 CM7100 etse 20 CM7200 30 7000 protection c bitte 151 protocol command master slave 60 prototyping area 110 111 113 Prototyping Board 20 23 26 27 28 36 55 78 110 112 119 120 126 127 128 7100 21 24 7200 30 CUMIN terne 112 H1 LCD header 127 128 H2 keypad header 127 3 129 128 jumper 154 programmable timers 34 42 43 PRT O creer 42 PRI 42 PTC resistors 151 pushbuttons Prototyping Board 119 120 129 R RAM eig 60 addtesses 4 ues 46 67100 27 Development Board 25 27 static 23 25 27 28 29 35 46 48 49 53 117 149 RDR 66 64 66 68 RE 68 read data register full 66 read only memory 21 23 24 25 27 28 29 34 39 43 44 60 62 117 118 real time clock RTC 35 47 53 receive buffer 57 58 59 receiver
109. made to proceed with normal development the standard or deluxe version of Dynamic C must be purchased The Development Board supplied with the Developer s Kit and the development EPROM are also available for separate purchase For help with upgrading to a full scale system call your PY Z World Sales Representative at 530 757 3737 A Developer s Kit is available for the CM7100 The Developer s Kit contains the following items Development EPROM Development Board which plugs into the CM7100 EPROM socket to emulate ROM with RAM to make it easier to develop and debug large programs Manual with schematics cables and AC adapter A 128K EPROM and an LCD Keypad module the LCD Keypad module requires a 9 216 MHz clock are available separately Figure 1 1 shows the CM7100 board layout nu oO du cessit onnon J3 us of ue U2 PAL RAM 5 1 00000 H Bi Us RI Sel ze H E 2 H3 EPROM 691 z E B 000 B H1 Top Side Microprocessor Side Figure 1 1 CM7100 Board Layout CM7000 O
110. ments of the CM7000 s I O cycles to ensure reliability The I O cycles have four wait states by default Four wait states are the maximum number programmable in the Z180 Normally there is no need to change this default Custom hardware can insert more wait states by pulling the WAIT line low on header H2 eo The Z180 MPU User s Manual provides more detailed information on hardware generated wait states Standard Cycles The standard four wait states I O cycle timing shown in Figure 4 1 is for the 9 216 MHz CM7000 Figure 4 2 shows the standard I O cycle timing for 18 432 MHz The format for numbers in parenthesis on the drawing 1s min max in nanoseconds The grey areas indicate where the signals may change Ons 100 ns 200 ns 700 ns 800 ns bor ot d ee ee Clock T J up J Us 20 1 gt 0 80 gt Address gt REM 20 4 periods ER 0 60 Twi Twa 0 60 RD WE 8 211980 10 60 gt WR WEE 2 0 35 10 30 gt 0 30 CSx 8 0 80 15 1 Data Out _ 30 0 Data 2222 C 9 216 MHz I O Read amp Write Timing CPU 8 MHz Period 108 507 ns Note 0 For I O read cycles data must have a minimum setup time of 30 ns before the falling edge of T3 Wait state
111. mperatures below 40 C which is too close to the 20 50 V maximum most HCMOS inputs can tolerate This second circuit s Schottky diodes clamp both positive and negative going voltage transients This third circuit uses only silicon diodes avoiding the problems Schottky diodes contribute at temperature extremes but forgoing their lower forward voltages Suppliers of Board Level Protection Devices Advanced Thermal Prod Inresco Inc Teccor Electronics Box 249 2411 Atlantic Ave 1801 Hurd Dr St Marys PA 15857 Manasquan NJ 08736 Irving TX 75038 814 834 1541 908 223 6330 214 580 1515 AVX Corp MCG Electronics World Products Box 867 12 Burt Dr Box 517 yrtle Beach SC 29577 Deer Park NY 11729 Sonoma CA 95476 803 448 9411 516 586 5125 707 996 5201 General Semiconductor Motorola Inc 2001 W Tenth Pl Power Prod Div Tempe AZ 85281 5005 E McDowell Rd 602 731 3221 Phoenix AZ 85008 602 244 3035 Harris Corp Philips Components Box 591 Box 760 Sommerville NJ 08876 Mineral Wells TX 908 685 6000 76067 817 325 7871 CM7000 Sample Applications 151 5 1 Digital Resistor sets Line max current e 0 01 pF 54V 1N5231 ZX MBR030 Controller Cap filters Zener diode clamps Schottky diode RF spikes positive levels to 5 1 V clamps neg levels to and negative levels 0 35 V 25 COM to 0 7 V 0 47 V 40 C Vss gt e S
112. ns 27 010 128 32 pins 27C020 256K 32 pins Copyrights The Dynamic C library is copyrighted Place a label containing the following copyright notice on the EPROM whenever an EPROM that contains portions of the Dynamic C library 1s created 01991 1995 Z World Inc Your own copyright notice may also be included on the label to protect your portion of the code Z World grants purchasers of the Dynamic C software and the copyrighted CM7100 EPROM permission to copy portions of the EPROM library as described above provided that 1 The resulting EPROMs are used only with the CM7100 cores manufactured by Z World and 2 Z World s copyright notice is placed on all copies of the EPROM 44 System Development CM7000 7200 CM7200 has a 32 flash EPROM soldered to the board at U3 as shown in Figure 3 7 The standard flash EPROM for the CM7200 is a 128K AT29C010A A 256K 29 020 chip is available as an option Unlike most memory devices which program a bit or byte at a time flash EPROM programs a sec tor at a time That is even if only a single byte within a sector needs updating the CM7200 overwrites the entire sector All bytes not spec Figure 3 7 Location of CM7200 ified in the sector being pro Flash EPROM grammed will erase to OxFF Write cycles execute under both software and hardware data protection These extra measures prevent invalid write cycles to the flash EPROM that would otherwis
113. nstalled Factory default except CM7130 not con Connect only when there is ADM691 supervisor otherwise J2 RAM will not operate Factory default except CM7130 not connected 6 connector located underneath EPROM position used 1 2 Connect for any other use Connect for EPROM 2 128K or when the Devel opment Board is in use factory default pins 2 3 connected Header H3 located other side of board under EPROM 03 H2 H1 pin 1 ROB 3 OB 2 Y1 M 1 U8 H3 Z180 U5 U7 Figure B 2 Locations of CM7100 Headers 88 Specifications CM7000 7200 Table 3 lists the roles of the headers and presents the jumper configura tions for the CM7200 The header locations are shown in Figure B 3 Table B 3 CM7200 Headers and Jumpers Header soldering Description 5 point interface extension with plated through holes for easy H2 40 pin interface fits in socket H3 on the Prototyping Board 6 pin connector located underneath EPROM position U3 used only for the Development Board with EPROM removed J2 CM7000 H3 Ji nected connected 8 pin header for SIB2 connection 08 2180 1 oo o o Figure 8 2 Locations of CM7200 Headers 07 05 691 JP1 Generally disregard J1 However if a
114. nt for the RAM depends strongly on the storage tempera ture CM7000 System Development 53 An alternative to a battery is a large capacitor and resistor that create an RC discharge circuit on the VBAT line When power is applied the capacitor will charge up until it reaches VRAM When power is removed the capacitor will power the RAM and RTC until discharged As stated above the RAM and RTC require a total of 4 pA This current draw means that the capacitor s full backup time is approximately 725 ks F The larger the value of this capacitor the longer the available backup time Connect this capacitor between the VBAT line and ground as shown in Figure 3 12 The CM7000 provides a resistor location R1 to add a series resistor to complete an RC charging circuit The value of this resistor affects the recharge time and limits the load on the power supply as the capacitor recharges The resistor has an insignificant effect during discharge because the resistance from VBAT to on the ADM691 8 typically 15 The capacitor will recharge to 98 percent of its nominal capacity in about four time constants 4 RC This recharge time limits the system s ability to withstand closely spaced power outages Panasonic sells a line of gold capacitors ideally suited for this application with capacitance up to 10 F Table 3 6 provides backup times for several scenarios Table 3 6 Representative Backup Times for Various Capacitors
115. nt z180baud int clock int baud The sysclock function returns the clock frequency in multiples of 1200 bps as read from the EEPROM The clock frequency was stored at location 0x108 at the factory The z180baud function returns the byte to be stored in CNTLBO or CNTLBI considering only the bits needed to set the baud rate You must supply the clock and baud rate in multiples of 1200 Hz Thus 7680 specifies a 9 216 MHz clock and 16 specifies a baud rate of 19 200 bps The return value is 1 if the function cannot derive the baud rate from the given clock frequency Each serial port appears to the CPU as a set of registers Each port can be accessed directly with the inport and outport library functions using the symbolic constants shown in Table 3 9 Table 3 9 2180 Serial Port Registers Address Name Description 00 CNTLAO Control Register A Serial Channel 0 01 CNTLAI Control Register A Serial Channel 1 02 CNTLBO Control Register B Serial Channel 0 03 CNTLBI Control Register B Serial Channel 1 05 5 Status Register Serial Channel 1 04 STATO Status Register Serial Channel 0 06 TDRO Transmit Data Register Serial Channel 0 07 TDRI Transmit Data Register Serial Channel 1 08 RDRO Receive Data Register Serial Channel 0 09 RDRI Receive Data Register Serial Channel 1 62 System Development CM7000 Attainable Baud Rates The serial ports built into the Z18
116. o keypad drive lines are also enabled Uses CS1 J3 Connected factory default enables input from the four pushbutton switches SW2 SW5 the six keypad sense lines and jumpers J6 J11 Uses CS2 J4 Connected factory default enables the LCD Uses CS3 To use the associated chip selects CS1 CS2 or CS3 for other purposes disconnect the corresponding jumpers across header J2 J3 14 accord ing to Table F 2 Remember to disable the associated components on the Prototyping Board When headers J10 and are configured for the program mode jumpers across headers J6 J9 are used to select a sample program the special EPROM supplied in the Evaluation Kit for the CM7100 The CM7100 checks headers J6 J9 at startup The CM7100 will execute the program if any stored in RAM when J6 J9 are all unjumpered CM7000 Prototyping Board 117 Table F 3 identifies which headers to connect to run program in RAM or to run one of the sample programs in the special EPROM Table F 3 Prototyping Board Jumper Settings for Sample Programs in Special EPROM Operation Header Configuration Run sample program 1 Jumper header J6 Run sample program 2 Jumper header J7 Run sample program 3 Jumper headers J6 and J7 Run sample program 4 Jumper header J8 Run sample program 5 Jumper headers J6 and J8 Run sample program 6 Jumper headers J7 and J8 Run sample program 7
117. ode while waiting for valid modem commands or mes sages Once a link is established the communication is in DATA mode regular RS 232 However the software continues to monitor the modem for a CARRIER message The software assumes that modem commands are terminated with CR that is a carrier return 0x0D The modem option is easiest to use when the user protocol also has CR as the terminating character Otherwise the software has to check for two different terminating characters The user s terminating character cannot be any of the ASCII characters used in modem commands nor can it be a line feed character The Dynamic C RS 232 library supports communication with a Hayes Smart Modem or compatible The CTS RTS and DTR lines of the modem are not used If the modem used is not truly Hayes Smart Modem compatible tie the CTS RTS lines on the Modem Controller modem side together The CTS and Side Side RTS lines on the controller also have RX RX to be tied together A NULL mo TX 2 TX dem cable is also required for the GND GND TX and RX lines A commercial RTS RTS NULL modem cable would have its CTS CTS CTS and RTS lines tied together al DTR ready on both sides Figure 3 15 Connections Between Figure 3 15 shows the correct mo Controller and Modem dem to controller wiring Interrupt Handling for Z180 Port 0 Normally a serial interrupt service routine is declared in an applicat
118. olar analog signal from 0 V to 5 V whose value is digital value 256 Voor x5 0 V 1 2 74HC32 10 VV D 0 7 J R2 10 V 500 1N5240 45V 10V ar 10 uF ICL7662 0 1 2 c vl 45 UEM 6 v VIN VOUT 1 T cs LM340 T5 Y Ou 87 pF E Q 10H 35V 4 F V ce 0 pF Figure J 7 8 bit Digital to Analog Converter Circuit In this case the DACOS will draw current at a rate of 10 V 5 kQ x digital value 256 into the 1 This current flows through and provides the output voltage range at the amplifier output The LM741 has an offset up to 15 mV bit R5 can null this offset or be left out Different amplifier configurations can create different output ranges including bipolar operation This circuit illustrates a way to get inexpensive voltage regulation using a Zener diode The 10 V can supply 40 mA before the voltage drop across R2 is greater then 2 V The LM741 can source up to 25 mA so this current this suffices the DACOS uses an additional 2 mA R2 is required to keep the power dissipated in the zener diode from exceeding 500 mW 10 V x 40 mA 400 mW CM7000 Sample Applications 147 The following sample program shows how to use the digital to analog converter circuit with CM7000 Sawtooth Wave int i k Examp
119. orrespond to the key identities in Z World s five key system see Dynamic Application Frameworks manual The five key system is described in detail in the Dynamic C Application Frameworks manual The Dynamic library CM71 72 LIB provides routines to operate the LCD and keypad These functions are described in the Dynamic C Function Reference manual CM7000 LCD Keypad Module 129 5 2 cS1 oo RESET 5 45V 45V 45V to LEDs to buzzer 74HC259 5 45V 3481 F2 F3 F4 DEL ADD menu item field up down help gt 0 4 74HC257 MUX 07 5 J3 10 kQ ics2 74HC257 MUX Figure H 5 Multiplexing and Reading Keypad Lines 130 LCD Keypad Module CM7000 FLASH PROGRAMMER Appendix I provides technical details for Z World s Flash Programmer used to program flash EPROMs for the CM7200 CM7000 Flash Programmer 131 Introduction The Flash Programmer shown in Figure I 1 is used to program the flash EPROM of CM7200s in medium to large quantities The Flash Program mer transfers a compiled application from a master EPROM to a target CM7200 s flash EPROM O Error O Copying O Pass F
120. ost of these subsystems Sample programs included with Dynamic C are provided Pra See Appendix J Sample Applications for sample circuits to illustrate the use of the CM7000 DMA Two DMA channels are accessible on the CM7000 interface and support memory memory and memory I O transfers The transfer modes sup ported by the Z180 are request burst and cycle steal DMA transfers can access the full address range with a block length of 64K and can cross over 64K boundaries Transfers can occur every 6 clock cycles The DMA channels can also function as high speed counters operating at up to 500 kHz on the 9 216 MHz CM7000 by using the request line as a counter input The signals DREQO and DREQI are the DMA request lines The DMA channels monitor these lines to determine when an external device is ready for a read or write operation The signals TENDO and TENDI are the transfer end lines A DMA device asserts these outputs during the last write cycle of a DMA operation By monitoring these lines a system can detect the end of a DMA transfer The DMA channel can be programmed to be either edge or level sensitive If a DMA channel is edge triggered a single byte gets transferred over the channel when the DMA device asserts the request line If the DMA channel is level sensitive multiple bytes will continue to transfer as long as the device asserts the request line that 1 holds it low Channel 0 perform
121. our choice Press any of the menu s key choices and observe the response Sample Program 7 SC1LCD C use the LCD Keypad Module optional accessory on the Prototyping Board The LCD displays the time and date Use the FIELD key to scroll across the date time display and use the arrow keys to change the date or time displayed The function keys 1 toggle the LEDs on or off CM7000 Libraries and Sample Programs 155 Sample Program 8 8SC121232 C demonstrates RS 232 communica tion between Serial Port 1 of the Z180 and a dumb terminal Set the PC termianl or communication program for 9600 bps 8 data bits 1 stop bit and no parity Connect a cable from the termianl s COM port to H5 on the Prototyping Board being careful to match the arrow on the 10 pin connector to pin 1 on header H5 The sample program provides the following message This program shows the use of 2180 port 1 for RS 232 communication Type a short string terminated with CR and the same string is sent back from the CM7000 The prompt gt follows the message Type anything followed by a return Other Sample Programs These sample programs listed in Table K 2 are included on the diskette containing the trial version of Dynamic C in the DCB SAMPLES CM71_72 directory Table K 2 Other CM7100 Sample Programs Description SCI5KEY C Five key menuing program for the Prototyping Board with an LCD
122. pt line Memory Protection When RESET is active the ADM691 supervisor disables the RAM chip select line preventing accidental writes Battery Super Capacitor Backup You can connect a battery or super capacitor to protect data in the RAM and Solder a connector across pins 1 3 on header H2 Connect the battery or the super capacitor across VBAT and ground as shown in Fig ure 3 12 Use a resistor to recharge the battery if it is rechargeable or the super cap Make sure jumper J1 on the CM7100 is not connected The RAM cannot be battery backed unless the ADM691 similar supervisor chip is present R1 22kQ Battery Backup Super Capacitor Backup Figure 3 12 Battery or Super Capacitor Installation VRAM the voltage supplied to the RAM and RTC can also protect other devices attached to the system against power failures The ADM691 supervisor switches VRAM to VBAT or whichever is greater To prevent hunting the switchover actually occurs when V is 50 mV higher than Both the RAM and the RTC require 2 V or more to retain data A3 V lithium battery such as the coin type CR2325 from Panasonic works well The RTC draws 3 during powerdown the RAM draws 1 pA The CR2325 is rated at 185 mA h and will provide current for total downtime of 46 250 hours or 5 27 years The circuit draws no current from the battery once regular power is applied The standby curre
123. pts NMI VEC 99 100 NO CARRIER message 59 nonmaskable interrupts 49 53 99 100 112 power failure 49 nonvolatile memory 35 47 102 null modem 59 0 operating procedure Flash Programmer 135 operation mode 23 118 optically isolated switch reader 143 Opto 22 binary protocol 60 outport 62 92 94 146 148 output RS 232 GA ee tente 57 CM7000 eese 66 66 66 7 parity NIRE 69 GITOE Literae eene 66 even odd nh 69 PC ss 20 23 27 1 PE 66 67 69 49 52 53 99 112 PFI resistor divider Prototyping Board 112 ports serials iiu 57 58 62 64 asynchronous 63 baud rate 63 multiprocessor communication unsere 63 power 23 26 27 52 78 99 filter Aes 150 Prototyping Board 112 SIB2 anteire vous 106 power failure 35 49 Interrupts 0 eee 99 100 sample program 50 power jack Prototyping Board 110 power rails Prototyping Board 113 power fail NMI 49 power on reset 79 prescaler 2 69 progra
124. rom 0x0 to Ox7FFFF The range of RAM addresses depends on the RAM chip as shown in Table 3 5 Table 3 5 SRAM Addresses SRAM Size Address Range 32K 0x80000 to Ox87FFF 128K 0xA0000 to OXBFFFF 512K 0 80000 to 7000 address decoder makes data appear to be replicated Data 32K RAM appear to be replicated 16 times throughout the range 0x80000 FFFFF Data in 128K RAM appear to be replicated throughout the range 0 0000 46 System Development CM7000 7100 has an optional 512 byte EEPROM at location U1 EEPROM is nonvolatile memory and holds system constants The CM7200 emulates this EEPROM its flash EPROM and executes all of Dynamic C s EEPROM function calls Consequently despite the dissimi lar hardware the memory map for both versions is exactly the same Ai See Appendix D EEPROM for more information on the software function calls and details about the EEPROM Real Time Clock RTC CM7000 has an optional Epson 72423 chip as shown in Figure 3 8 The chip stores time and date and accounts for the number of days in a month and for leap year A user supplied backup battery will allow the values in the RTC to be preserved if a power failure occurs The Dynamic C function library DRIVERS LIB provides the following functions tm rd Reads time and date values from the RTC tm wr Writes time and
125. rs were set in Step 6 to run a program stored in RAM or to Figure 2 6 Serial Cable Connection run one of the sample programs to CM7100 Prototyping Board stored in the special EPROM Serial CM7000 Getting Started 23 CM7100 Method 2 Development Board 1 Check to make sure the power to the Prototyping Board is not con nected 2 Check header J3 on the microprocessor side of the CM7100 The surface mounted jumper should connect pins 2 3 to use the Develop ment Board This factory default setting 18 shown in Figure 2 1 3 Plug the CM7100 into the Prototyping Board as shown in Figure 2 7 Plug header H2 of the CM7100 into connector H3 of the Prototyping Board Pins 1 of the header and connector must match The CM7100 will hang over the battery on the Prototyping Board For maximum stability install the supplied standoff between the CM7100 and the Prototyping Board CM7100 COLI Ww H2 Standoff uu H3 Power Jack Battery Prototyping Board Figure 2 7 Connecting CM7100 to Prototyping Board 4 If an EPROM is installed in socket U3 on the CM7100 remove the EPROM Plug a Dynamic C development EPROM Z World part number 680 290x into the EPROM socket U3 of the Development Board See Figure 2 8 lt Dynamic C EPROM f 680 290x Development Board H2 ye CM7100 Figure 2 8 Installation of CM7100 Development Board and Development EPROM 24 Ge
126. s must be added if this condition cannot be satisfied For CPU and DMA cycles that access external I O 1 to 4 wait states are automatically inserted depending on the programmed value of DCNTL bits 4 and 5 Figure 4 1 Standard Cycle Timing at 9 216 MHz 76 Design Considerations 4 wait states CM7000 Ons 50 ns 100 ns 350 ns 400 ns 1 dag Cok f C vs 120 10 30 Address GET 0 25 gt 5 a 4 wait periods OoOO M 0 25 gt Twi Tw4 10 2514 RD 10 10 25 0 25 gt INR A M 0 11 5 3 1 115 0115 ICSx kk 9 1 0 25 10 7 10 1 0 Data in 18 432 MHz I O Read amp Write Timing CPU 20 MHz Period 54 253 ns For I O read cycles data must have a minimum setup time of 10 ns before the falling edge of T3 Wait states must be added if this condition cannot be satisfied For CPU and DMA cycles that access external I O 1 to 4 wait states are automatically inserted depending on the programmed value of DONTL bits 4 and 5 Figure 4 1 Standard Cycle Timing at 18 432 MHz 4 wait states Wait State Insertion The WAIT line inserts wait states into an I O request cycle under the control of the custom hardware The Z180 CPU samples the
127. s are disabled at system reset By manipulating the bits of the TCR the timers can be made to cause an interrupt when they time out Counting can also be enabled and disabled When reading the TMDR registers read the low byte first then read the high byte The accuracy of the reading depends on this order Before writing to a TMDR you must stop the channel by setting the appropriate bits in the TCR In general do not set a reload register unless you have first stopped its timer channel Refer to the Z180 MPU User s Manual for details on the 65 operation of the Software Table 3 4 lists Dynamic C functions that support the programmable reload timer Table 3 4 Programmable Timer Library Functions Function Description Library init timerO Places a count in the timer s s i DRIVERS LIB init timerl reload register Timer 0 interrupt service routine Runs RTK Real Time Kernel DRIVERS DIB timer0_isr Timer 1 interrupt service routine int_timer1 Drives a beeper and keypad Runs KDM LIB RTK if RUNKERNEL is defined Waits specified number of DRIVERS LIB ponte milliseconds using timer 1 S lk_tdelay Similar to Tdelay KDM LIB lk_int_timer1 Similar to int_timer1 KDM LIB l au init Initializes timer 1 KDM keypad KOM LIB eyp driver and graphic LCD Dynamic Function Reference manual describes these 65 functions in detail 42
128. s memory memory transfers Such transfers include memory mapped I O and transfers to and from the serial channels The transfer modes for Channel 0 are burst and cycle steal Channel 0 has memory address increment decrement and no change modes Channel 1 performs only memory I O transfers It supports memory address increment and decrement Channel 0 has a higher priority than Channel 1 CM7000 System Development 39 Registers Table 3 2 lists the registers associated with channels Table 3 2 DMA Registers Register Address Description Channel 0 SARO 0 20 22 Source Address DARO 0x23 25 Destination Address BCRO 0 26 27 Byte Count Channel 1 MARI 0 28 2 Memory Address IARI Ox2B 2C I O Address BCRI Ox2E 2F Byte Count Both Channels DSTAT 0x30 DMA Status DMODE 0x31 DMA Mode DCNTL 0x32 DMA Control Memory address registers span 20 bits I O address registers on the other hand span only 16 bits The byte count register has 16 bits The higher order bits of the registers are stored in the bytes with higher addresses For details on DMA registers and timing refer to the Zilog Gu Z180 MPU User s Manual and the sample Dynamic C programs SC1DM232 C and SC1DMAPW C 40 System Development CM7000 Software Table 3 3 lists Dynamic C functions that support the DMA channels Table 3 3 DMA Library Functions Function Description Librar
129. some RS 232 level converter ICs go into a nonde structive latch up Connect the RS 232 cable after powerup to eliminate this problem Dynamic C Loses Serial Link If the application disables interrupts for a period greater than 50 ms Dynamic C will lose its serial link with the application Make sure that interrupts are not disabled for a period greater than 50 ms CM7000 Repeatedly Resets 7000 resets every 1 0 second if the watchdog timer is not hit If a program does not hit the watchdog timer then the program will have trouble running in standalone mode To hit the watchdog make a call to the Dynamic C library function hi 6 CM7000 Troubleshooting 83 Common Programming Errors Values for constants or variables out of range Table A 1 lists accept able ranges for variables and constants Table A 1 Ranges of Dynamic C Function Types Type Range int 32 768 25 to 432 767 25 1 long int 2 147 483 648 23 to 42147483647 2 1 float 6 805646 1038 to 6 805646 x 10 char 0 to 255 Mismatched types For example the literal constant 3293 is of type int 16 bit integer However the literal constant 3293 0 is of type float Although Dynamic C can handle some type mismatches avoiding type mismatches is the best practice Counting up from or down to one instead of zero In software ordinal series often begin or terminate with zero not one Confusin
130. ster 0 34 Interrupt Trap Control Register 0x35 Reserved 0x36 RCR Refresh Control Register 0x37 Reserved 0x38 CBR MMU Common Base Register 0x39 BBR MMU Bank Base Register Ox3A CBAR MMU Common Bank Area Register Ox3B O0x3D Reserved Ox3E OMCR Operation Mode Control Register osr 0 3 ICR Control Register CM7000 Memory Map and Interrupt Vectors 95 Epson 72423 Timer Registers 0 4180 0 418 Table C 3 lists the Epson 72423 timer registers Table C 3 Epson 72423 Timer Registers 0x4180 0x418F 418D TREGD D0 D7 Register D 418 0 07 Register E 418F TREGF D0 D7 Register F Address Name Data Bits Description 4180 5 D0 D7 seconds 41181 5 0 D0 D7 10 seconds 4182 MINI 20 27 minutes 4183 10 20 07 10 minutes 4184 HOURI D0 D7 hours 4185 HOURIO D0 D7 10 hours 4186 DAYI 20 07 days 4187 DAYIO D0 D7 10 days 4188 D0 D7 months 4189 10 D0 D7 10 months 484 YEARI 20 27 years 4188 YEARIO D0 D7 10 years 41800 WEEK 20 27 weeks 96 Memory and Interrupt Vectors CM7000 Other Addresses Table C 4 lists the other registers Table C 4 Other I O Addresses Address Name Data Bits Description 2000 SCL DO EEPROM serial clock CM7100 4000 403F CS1 Chip Select 1 4040 4
131. ster Channel 1 least 0 17 RLDRIH 94 Memory and Interrupt Vectors Timer Reload Register Channel 1 most continued CM7000 Table 2 2180 Internal I O Registers Addresses 0x00 0x3F concluded Address Name Description 0x18 FRC Free running counter 0 19 0 1 Reserved 0x20 SAROL source address Channel 0 least Ox21 SAROH DMA source address Channel 0 most 0x22 SAROB DMA source address Channel 0 extra bits 0 23 DAROL DMA destination address Channel 0 least 0 24 destination address Channel 0 most 0 25 DAROB DMA destination address Channel 0 extra bits 0 26 BCROL DMA Byte Count Register Channel 0 least 0 27 BCROH DMA Byte Count Register Channel 0 most 0 28 MARIL DMA Memory Address Register Channel 1 least 0x29 MARIH DMA Memory Address Register Channel 1 most Ox2A MARIB Memory Address Register Channel 1 extra Ox2B Address Register Channel 1 least 0 2 IARIH Address Register Channel 1 most 0 2 Reserved 0 2 BCRIL DMA Byte Count Register Channel 1 least 0 2 Byte Count Register Channel 1 most 0 30 DSTAT DMA Status Register 0 31 DMODE Mode Register 0 32 DCNTL DMA W AIT Control Register 0 33 IL Interrupt Vector Low Regi
132. ted This configuration 1s the factory default Also note that the connection on header J3 is a soldered jumper consisting of a 00 resistor CM7000 System Development 43 Programming EPROMs Dynamic C can be used to create a file for programming an EPROM by selecting the Compile to File option in the COMPILE menu with the standard EPROM Z World part number 680 290x installed The CM7100 must be connected to the PC running Dynamic C during this step because essential library routines must be uploaded from the standard EPROM and linked to the resulting file The output is a binary file optionally an Intel hex format file that can be used to build an application EPROM The application EPROM is then programmed with an programmer that reads either a binary image or the Intel hex format file The resulting application EPROM can then replace the standard EPROM When doing program development with Dynamic C it 1s best to use a 128K SRAM or larger Dynamic C will work with a 32K SRAM but the total program space will be limited to 16K of root and 16K of extended memory This is enough for many programs but it is inconvenient to run out of memory during development Once a program 1 burned into EPROM there 1 no reason to use SRAM larger than 32K unless the data space is larger than 32K Choosing EPROMs Socket U3 can accommodate several different types of EPROMs includ ing the following 27 256 32K 28 pins 27C512 64K 28 pi
133. th a call to wderror This makes it possible to determine whether a watchdog timeout occurred The following sample program shows how to do this when a program starts or restarts main if wderror wd_cleanup hitwd Power Shutdown and Reset When V 5 V drops below V n between 4 5 V and 4 75 V the ADM691 supervisor asserts RESET and holds it until V goes above V umn and stays that way for at least 50 ms This delay allows the system s devices to power up and stabilize before the CPU starts PFI Early Warning A power supply like that of the Prototyping Board Figure 3 11 allows power failures to be detected before they cause operational failures Connect the signals PFI and V 5 V to the CM7000 via header H2 1N5819 DCIN 9 V LM340 T5 E739 Y gt 691 10 7 KQ za 330 uF 1 dev CM7000 1N5230B 2 1 V Figure 3 11 Prototyping Board Power Supply When PFI drops below 1 3 V 0 05 V 1 e DCIN drops below 7 5 V the supervisor asserts NMI nonmaskable interrupt and allows the program to clean up and get ready for shutdown The underlying assump tion is that PFI will cause the interrupt during a power failure before the ADM691 asserts RESET 52 System Development CM7000 If the CM7000 has ADM691 supervisor solder together pads 9 and 10 at U5 to connect PFI directly to NMI for a nonmaskable interru
134. the factory default setting When enabled CS1 governs the circuit 1 represents addresses from 0x4000 to 0x403F Address lines 0 3 select one of the eight outputs Thus writing address 0x4000 selects the first LED D2 Writing address 0x4004 selects the buzzer The C expression CS1 4 is equivalent to 0x4004 The only data bit of interest is bit 0 Writing 1 to bit 0 turns on the selected output writing a 0 turns it off 120 Prototyping Board CM7000 DEVELOPMENT BOARD Appendix provides technical details for Z World s Development Board used with the CM7100 CM7000 Development Board 121 Development Board is included with the 7100 Developer s Kit The Development Board plugs into the EPROM U3 and H3 sockets of the CM7100 when an application 1s being developed The Evaluation Kit includes the Prototyping Board and a trial version of Dynamic C with a CM7110 The standard or deluxe version of Dynamic C and a Development Board are needed to have a complete development system Figure G 1 shows the board layout for the Development Board Ora Batey 2 U1 U2 01 Super i UART 05 0 Op PAL Figure G 1 Development Board Layout 122
135. ti cally in Figure F 3 A PC is connected to header H4 during program development for a CM7100 CM7200s are always connected to the host PC via the SIB2 CM7000 Prototyping Board 111 5 45V 10 10 ka R2 CTSO 6 RTSO 2kQ 5 1 2 10 e 2180 1091 li 10 910110 Serial C10 AV CM7000 47 WF A H4 16V 1 2 10 09 309 4 7 uF A k 16V sido T 7608 90 19 Programming Figure F 3 Prototyping Board Serial Ports Power Power 9 V DC from the wall transformer comes in through the DC input jack J1 and goes to the LM340 regulator U3 which supplies 5 V to the CM7000 and other circuits on the Prototyping Board DCIN also feeds a resistor divider R1 and R8 which develops the power failure interrupt signal PFI Figure F 4 shows a schematic of the power supply DCIN 9V 01 1N5819 from DC jack LM340 T5 to CM7000 C4 330 uF 16V 71 1 5230 V V V V V Figure F 4 Prototyping Board Power Supply When DCIN goes below 8 V PFI goes below 1 3 V the threshold at which the CM7000 s ADM691 supervisor generates a nonmaskable interrupt NMI An application can take advantage of the PFI early warning to perform cleanup and shutdown before the supervisor causes a reset because of low power The Prototyping
136. tirely different function Ifa 0 is written the baud rate prescaler is set to divide by 10 If a is written it is set to divide by 30 MP Multiprocessor Mode When this bit 1 set to 1 the multiprocessor mode 15 enabled The multi processor bit MPB is included in transmitted data as shown here start bit data bits MPB stop bits The MPB is 1 when MPBT is 1 and 0 when MPBT is 0 MPBT Multiprocessor Bit Transmit This bit controls the multiprocessor bit MPB When MPB is 1 transmit ted bytes will get the attention of other units listening only for bytes with MPB set 7000 System Development 69 Table 3 12 relates the Z180 s ASCI Control Register B to the baud rate ASCI Table 3 12 Baud Rates for ASCI Control Register B Baud Rate at Baud Rate at ASCI Baud Rate at Baud Rate at B Vade 9 216 MHz 18 432 MHz 9 216 MHz 18 432 MHz bps bps bps bps 00 57 600 115 200 20 19 200 38 400 01 28 800 57 600 21 9600 19 200 02 08 14 400 28 800 22 or 28 4800 9600 or 09 7200 14400 23 or 29 2400 4800 04 or OA 3600 7200 24 or 2A 1200 2400 05 or OB 1800 3600 25 or2B 600 1200 06 or 0C 900 1800 26 or 2C 300 600 0D 450 900 2D 150 300 0E 225 450 2E 75 150 70 System Development CM7000 4 4 DESIGN CONSIDERATIONS CM7000 Design Considerations 71 Bus Loading When designing an interface pay
137. tting Started CM7000 5 Plug the Development Board into the EPROM U3 and H3 sockets the CM7100 as shown in Figure 2 8 Headers U6 and H2 on the under side of the Development Board must match the CM7100 EPROM and H3 sockets exactly A Be careful The U6 and H2 pins on the Development Board are delicate and bend easily 6 Check the jumpers on the Development Board Figure 2 9 shows the locations of the relevant headers Ks 7 a EPROM cp Batey C3 ry U1 Super UART 0 ay Us eom RAM 4 232 aE Luce Buffer 0 Buffer PSSST STS SSE Figure 2 9 7100 Development Board Figure 2 10 shows the jumper settings for different RAM sizes operational modes and baud rates Development Board Development Board Jumper Settings RAM Jumper Settings Program Baud Rate JP3 19 200 bps 32K 128K JP4 JP3 9600 bps JP3 JP4 57 600 bps JP3 Run program in Devel 0 opment Board RAM Figure 2 10 CM7100 Development Board Jumper Settings CM7000 Getting Started 25 1 7 Ifyou using 28 pin RAM chip seat t
138. u are using a 28 pin EPROM position the IC at the bottom ofthe socket as shown in Figure I 4 so that the top four socket pins are Hr m m ugguggHgHHHEHHEHEHUH empty Figure 1 4 Positioning 28 pin and 32 pin EPROMs in Flash Programmer ZIF Socket 3 Lower the lever to the horizontal position 4 Setthe Flash Programmer s back panel DIP switches to indicate the size of the master EPROM see Table I 1 Switches SW4 SW5 and SW6 should be off 5 Insert the target CM7200 in the 40 pin socket on the Flash Programmer as shown in Figure I 5 Spring Pin A touches micro processor side O Error O Copying O Pass a E 0000 0000 ut 7200 0 amm Flash Pro grammer Socket cannot handle CM7200s that have header H1 installed Figure 5 Placement of 7200 in Flash Programmer Socket CM7000 Flash Programmer 135 6 Make sure the Flash Programmer s spring pin shown in Figure 1 5 makes contact with the CM7200 circuit board If the spring pin does not make proper contact the Flash Programmer will not work There fore take care never to bend or otherwise damage the spring pin 7 Turn on the power 8 All three LEDs will light momentarily to indicate that the Flash Pro grammer is resetting The yellow middle LED will blink to indicate data are bein
139. uards have been adopted l If there is no valid program in RAM the Dynamic C monitor will re peatedly go into a tight loop forcing a watchdog timeout If byte 0x70 is not a O or 1 the monitor is forced to RUN mode 3 If byte 0x71 18 not a multiple of 8 the monitor 1 forced to RUN mode If bytes 0x72 and 0x73 have an address less than 0x4000 or greater than Ox417F the monitor is forced to RUN mode The Dynamic C development EPROM has the six locations all set to OxFF CM7000 Getting Started 29 7200 CM7200 uses its 7180 microprocessor s CSI O clocked serial I O line for communicating with Dynamic C running on a host PC Z World s SIB22 makes the CSI O port look just like an RS 232 port Since the CM7200 s flash EPROM is electrically reprogrammable in a circuit the flash EPROM requires no ROM emulation during development Conse quently the CM7200 s programming strategy 1 very simple when com pared to the CM7100 s CM7200 Method 1 Prototyping Board 1 Check to make sure the power to the Prototyping Board 1 not con nected 2 Plug the CM7200 into the Prototyping Board as shown in Figure 2 15 Plug header H2 of the CM7200 into connector H3 of the Prototyping Board Pins 1 of the header and connector must match The CM7200 will extend over the battery on the Prototyping Board For maximum stability install the supplied standoff between the CM7200 and the Prototyping Board CM7200
140. uilt in serial port without using a Development Board In this method the program is held in RAM while the application is under development At least 128K of RAM is highly recommended Note that the CTSO input must be asserted for channel 70 to transmit Tie CTSO to ground if RTS CTS handshake support is not needed 1 Build an input port into your hardware using one of the CS lines One bit of the input will specify whether the Dynamic C monitor in the EPROM enters RUN mode or PROGRAM mode 2 Build serial driver into your system based on the one on the Prototyp ing Board see Figure 2 13 2180 7100 A 10 ka 232 H4 TX1 1 Q O 4 7 uF V 4 7 uF Figure 2 13 CM7100 Prototyping Board Serial Driver If your serial driver has a 10 pin header that conforms to Z World s programming cable you will not need to build another programming cable CTS and RTS are tied together and pulled up 3 Six bytes of the Dynamic C EPROM starting at 0x70 in the file are reserved as indicated in Table 2 1 Table 2 1 Dynamic C EPROM Addresses Address Name Range Meaning 0 70 channel 0 1 Selects serial programming port baud Programming baud rate in multiples of 0x71 NM 1 48 1200 bps 8 9600 bps 16 19 200 bps 48 57 600 bps 0x4000 Address of input port corresponds to CS 03723 address 0x417F line low ord
141. velopment EPROM Z World part number 680 290x into the EPROM socket U3 of the Development Board See Figure 2 8 3 Plug the Development Board into the EPROM U3 and H3 sockets on the CM7100 as shown in Figure 2 8 Headers U6 and H2 on the under side of the Development Board must match the CM7100 EPROM and H3 sockets exactly Be careful The U6 and H2 pins on the Development Board are delicate and bend easily 4 Check header J3 on the microprocessor side of the CM7100 The surface mounted jumper should connect pins 2 3 to use the Develop ment Board This factory default setting 1 shown in Figure 2 1 5 Check the jumpers on the Development Board Figure 2 9 shows the locations of the relevant headers Figure 2 10 shows the jumper settings for different RAM sizes and for the operational mode and baud rates 6 If you are using a 28 pin RAM chip seat the chip in the RAM socket as shown in Figure 2 11 7 Connect the serial cable Connect one end to the PC COM port Then connect the 10 pin end to H1 of the Development Board as shown in Figure 2 12 Be careful to match the arrow on the connector to the location of pin 1 of 1 8 Reconnect power to the CM7100 The CM7100 is ready for program ming unless the jumpers were set in Step 5 to run a program stored in the Development Board RAM CM7000 Getting Started 27 CM7100 Method 4 In Target Direct Development It is possible to program directly through CM7100 s b
142. verview 15 CM7200 Series Table 1 2 lists the features of each model in the CM7200 Series Table 1 2 CM7200 Series Features Model Features CM7200 18 432 MHz clock 128K SRAM real time clock ADM691 supervisor and 128K flash EPROM CM7210 CM7200 with 9 216 MHz clock CM7220 CM7200 with 9 216 MHz clock and 32K SRAM CM7230 CM7200 with 9 216 MHz clock and 32K SRAM Without ADM691 supervisor and real time clock A Developer s Kit is available for the CM7200 The Developer s Kit contains the following items Prototyping Board Manual with schematics cables and AC adapter Serial Interface Board 2 The following optional accessories are available for the CM7200 Flash Programmer to program flash EPROM e 256K factory installed flash EPROM LCD Keypad module 2 x 20 LCD and 2 x 6 keypad for use with CM7200 modules with a 9 216 MHz clock Figure 1 2 shows the CM7200 board layout 2 691 00000000000000000 E B 2000 B JP Flash E B 08 E irs E E PAL B irs 00880 1 cb H2 2 1 Hio mE Top Side Microprocessor Side Figure 1 2 CM7200 Board Layout
143. y DMAOCount DMA channel acts as a high speed DRIVERS LIB DMA1Count counter interrupting when done Reads the number of pulses a channel has counted DRIVERS LIB DMA0_Off Turns DMA channel off LIB DMA1 Off Initializes a serial port 0 or 1 for DMAO0 SerialInit DMA transfer DMA LIB Initiates a transfer Rx DMAO Rx 0_ receive Tx transmit from a DMA LIB DMAO Tx serial port Initiates a DMA transfer from memory to an I O port The DMAO MIO external device must generate DMA LIB DMA1 MIO negative pulse to request each byte transferred Initiates a memory to memory DMAO MM DMA LIB transfer Initiates a DMA transfer from an I O port to memory The external DMAO IOM device must generate a negative DMA LIB DMA1 IOM pulse to request each byte transferred a The Dynamic C Function Reference manual describes these functions in detail CM7000 System Development 41 Programmable Timers The Z180 has a two channel programmable reload timer PRT Each channel PRTO and has a 16 bit down counter TMDR and a 16 bit reload register RLDR A single 8 bit timer control register TCR sets up both timers The down counters decrement every 20 clocks 2 17 at 9 216 MHz When the counters reach 0 they automatically reinitialize with the value stored in their respective reload registers The two channel

CM7000 Series - Digi International

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