SMT387 User Manual
Contents
1. 16 P 18 Figure 5 RSL COMOCIOEP optet eee pid pid pile ub odis 21 Figure 6 Global Bus constraints file signal 22 Figure 7 FPGA PCI Command Sequences 23 Figure 8 SATA daughter module 44444444 anne 28 Figure 9 SMT387 with SATA daughter module installed 28 Figure 10 SMT387 Components placement Top 36 Figure 11 SMT387 Components placement Bottom view 37 Figure 12 Top View SHO ces nicer hector ER PEE eh HER EIE ER EE UID entente 38 Figure 13 Top View of JTAG Multilinx 40 Table of Tables Table 1 Choices t 15 1 2 2 51265 2 17 Table 3 RSL Speed vs FPGA Speed 22 Table 4 FPGA PCI Register Offsets de 23 Table S ed Tn 25 Table 6 Powering the devices 25 Table 7 Power GODSUmplOLD zu access meme mem nome ud ne eee age 27 Table 8 SHB interfaces table huissier 39 Tabl2. gy NE A e M e am 9012 ane gt go 9 e eig ee omn gc 5 gx e e 9 amp 09067725 rw conc a a CO cin meg 5 NN mE mm mm mms g a lalala ESS gs Pt RIT e e e ee Su 6012 0112 p ERST a an e e o e e gt S HERREN 111000 O O ee as S e e 0 ac 299 929999 935000000 Oe 58 83885 55020 109 e ee wm ccyl69 Zi meas 002 ee Tor ee am oi Olo e o eo zl SERRE ER EES Em le a eee oe ee SEN in EIL 163 69 69 ge e e e mue EE 755 ee 18028 ee e e e oe eve e maso an ac 79 a e soo E EGETI Whg as ps E ee zo e e e ocus m ON WO E 19 ign IL SLI e e 9 9 aai EL 12 naonna ee 297 1 IE g 0 799 ao 88 Tu aS ns ee mM 8 ee oe amp 9 9 0 ee Bi 0 99 260072 192 a i oz 17 wee ome an 0 0 0 0 e e eoo 181816 eve
3. NS SOME SoMa 13 Pc EP PUDE 14 eel 15 COMMOURAUOM 15 JTAG Boundary SCAN ated ceto DR Er Toa e t e totg tores 15 Configuring with MultiLINX res exeo eee ex et 16 en ete ce 17 Pipelined ZB TRAM zn tete oe 17 COMPOS uod oii oae mud pice mud meine cen Dae Du RUD RC nee 17 SIIB 18 SHB COHIBCIOE s x oaa 18 SHB Cable ee ee ne 19 SHB Inter Modules 5 19 Version 1 0 3 Page 4 of 42 SMT387 User Manual Half Word Interface 16 bit SHB Interface 19 Constraint File Signal Names nnne nnne 20 i PM 21 GODDeC IO cosmos ook ol o dpa pi DURO pi te oS p pp op pp iMd 21 RSL Cable Assembly enone rette ie eee 21 RSU Interface oa atero m enne Dal Ha tte eed Iu d Aa AR RU ITIN a e Fa 21 Global busiz eid med ud Du i Qu mln male 22 Constraints File Signals Names 22 2 IOGKS Li PD DU QU DAN EROR 23 549 ne 23 FPOR POI COMD uc cada d edu cad cui 24 FPOA oannes ct D a due 24 FESSA TO
4. 5 Replace the carrier board in the host system or power on for a stand alone Carrier Version 1 0 3 Page 11 of 42 SMT387 User Manual TMS320C6415 xe TMS320C6201 The processor will run with zero wait states from internal SRAM An on board crystal oscillator provides the clock used for the C60 which then multiplies this by 12 internally Boot Mode xe Boot Mode The SMT387 is configured to boot from Flash only after a reset Flash boot 1 The processor copies a bootstrap XE bootstrap program program from the first part of the flash memory into internal program RAM starting at address 0 2 Execution starts at address 0 The standard bootstrap supplied with the SMT387 then performs the following operations 1 All relevant C60 internal registers are set to default values 2 The FPGA is configured XE FPGA configuration from data held in flash memory and sets up the communication ports the global bus and the Sundance High speed Buses This step must have been completed before data can be sent to the Comports from external sources such as the host or other TIMs 3 A C4x style boot loader is executed This will continually examine the six communication ports until data appears on one of them The bootstrap will then load a program in boot format from that port the loader will not read data arriving on other ports 4 Finally control is passed to the loaded program The delay between the release of the board
5. As RSL are based on RocketlO transciever blocks the speed is limited by the speed grade of FPGA installed Version 1 0 3 Page 22 of 42 SMT387 User Manual Speed grade 7 6 5 RSL speed Gbps 3 125 3 125 2 0 Table 3 RSL Speed vs FPGA Speed Grade Based on the above the 4 bi directional links of SMT387 can provide a combined bandwidth of up to 12 5Gbps The RSL connector is J3 See Figure 10 SMT387 Components placement Top view Refer to the latest SUNDANCE RSL specification for technical information on how it works Global bus The global bus is compatible with the TIM standard The Global Bus Interface is a memory Interface that follows Texas Instruments TMS320C4x External Bus operation standard Additional information on the standard is available in the TMS320C4x User s Guide chapter 9 External Bus operation When Writing the FPGA sends data across the global bus to the external device When Reading the external device writes data across the global bus to the FPGA Constraints File Signals Names GBUS RW1N Global Bus signal Active level N Active low STATn 3 0 are also global Bus signals Figure 6 Global Bus constraints file signal names Version 1 0 3 Page 23 of 42 SMT387 User Manual Clocks The FPGA clock is provided by the EMIFA of the DSP This can be configured as 4 or 1 6 of the DSP core speed e g if the DSP core speed i
6. SMT387 User Manual Certificate Number FM 55022 User Manual Version 1 0 2 4 8 04 Sundance Digital Signal Processing Inc 2004 Version 1 0 3 Page 2 of 42 SMT387 User Manual Revision History Date Comments Engineer Version Frstreleased version em 100 amm Wmrdemum em 101 4 8 04 Edits from feedback PTM 1 0 2 6 23 04 Update of jumper details LED info added Version 1 0 3 Page 3 of 42 SMT387 User Manual Table of Contents REVISION HISLOEV ne PE pede 2 Table CF en Sienne ee eee 3 Table OT FIQUPOSS 6 es nn Ste RS ANS M 6 Physical Properties ES es 7 sacs sic oka e 8 Related Documents courier at Cro HR Te I Dl Le a HR TOU DIE I 8 Block DIagr ant oett RE RERO RR RET 8 Mechanical Interface TIM Standard ss 9 iR FSU PO OME 9 SMT387 lnstallatlON rco sro ne See M MEN DAN 9 SMTSSI AIO Scot f opponent n 9 SMIS67 DSP TIM ec 10 D Even 11 BOOUMOGOG CH GELT QU ent STA HU UE RUE CL ta ARAM aah 11 EMIF Control Registers ouod oeste nn nn E nn nr ose 11 SDEANS ee de se 12 ee ee ee Re e ce ua d LM 12 MER e Me Ns MR e
7. The PCI specifications state that the maximum power allowed for any PCI board is 25 Watts and represents the total power drawn from all power rails provided at the connector 5V 3 3v VI O 12V 12V 3 3Vaux The expansion board in our case the TIM carrier board and the TIM modules may optionally draw all this power from either the 5V or 3 3V rail Nevertheless it is anticipated that many systems will not provide a full 25 Watts per connector for each power rail because most boards will typically draw much less than this amount For this reason it is recommended that you analyse the total FPGA device power drawn by using Xilinx XPOWER before implementing your design in the FPGA This will tell you if you need to use the external power connector provided on our carrier boards Like the SMT310Q carrier board TI 6415 DSP FPGA Sil3512 XC2VP Vccint Vdd Vcco Vddq Vpci Vccaux Table 6 Powering the devices Version 1 0 3 Page 26 of 42 SMT387 User Manual This module must have 5V supplied through the TIM connectors In addition a 3 3V supply is required and should be supplied through the TIM mounting holes This is compatible with the SMT310Q SMT327 and future Sundance TIM carrier boards Contained on the module are linear regulators for the DSP core 3512 core FPGA VCCAUX and FPGA PCI A DC DC converter supplies the core voltage for the FPGA DC DC converter An International Rectifier IP1001 Powe
8. Torun the example you will need e The Sundance board support package SMT6025 e The Diamond Windows Server This is made available as part of the installation of Diamond This part of the product can also be installed using a kit contained in newer versions of Diamond The kit can be included in distributions of the Logger under simple licence conditions 2 To modify and rebuild the DSP application you will need e Diamond e The Texas Instruments C6000 tools compiler and linker 3 To modify and rebuild the user interface you will need e Microsoft Visual C The Kit The distribution kit contains a number of files in several directories Copy the complete contents of the kit into a working directory which this document will assume is called Logger Building the Example The Logger directory contains a makefile that will build the complete application see Prerequisites The directory Logger DSP contains a makefile that will build only the DSP portion Logger app Note that the Microsoft VC compiler may object to the existing intermediate files and complain about precompiled headers This can be cured by selecting the VC option Build Clean and then rebuilding the application The DSP configuration is specified in the file Logger DSP Logger cfg The Root processor is currently identified as an SMT361 because the SMT387 has not been included in the standard Diamond release The type of the Node processor is not particularl
9. at an 18 0 or 14 8 CPU to PCI clock frequency ratio only e g 600 MHz or 490 MHz CPU for 33 MHz PCI Refer to TMS320C6414 TMS320C6415 and TMS320C 6416 Digital Signal Processors Silicon Errata SPRZO11 for more information Virtex FPGA The SMT387 incorporates a Xilinx Virtex XC2VP20 FPGA XC2VP7 or XC2VP30 are also possible This device controls the majority of the I O functionality on the module including the Comports SHBs global bus timers and interrupts This device requires configuring after power up the Virtex technology is an SRAM based logic array This configuration is performed by the DSP as part of the boot process Two control register bits are needed for this purpose one to put the FPGA into a waiting for configuration state and another to actually transfer the configuration data The PROG pin causes the FPGA to enter the non configured state is accessed at address 0x6C02000X Writing to address 0x6C020000 will assert this pin and address 0x6C0200001 will de assert this pin The configuration data clock is accessed at address 0x6C080001 Each bit of the FPGA s configuration bit stream must be serially clocked through this address Note This configuration process is part of the standard boot code and does not need to be implemented in any user application Version 1 0 3 FPGA Page 15 of 42 The module can be fitted with XC2VP7 XC2VP20 or XC2VP30 Only flip chip FF896 package will fit on t
10. 13 Top View of JTAG Multilinx headers JTAG Boundary scan User defined jumpers pinout JP1 JP2 SMT387 User Manual Name Pin Function Connections JMP1 1 User defined function To FPGA pin Pulled up to 3 3V with 4 7k when unconnected ARTE JMPO 2 User defined function To FPGA pin Pulled up to 3 3V with 4 7k when unconnected ARTS GND 3 Ground Board ground Designed to pull down pin 1 by using a 0 1 jumper GND 4 Ground Board ground Designed to pull down pin 2 by using a 0 1 jumper VCC 5 Power To target Version 1 0 3 SMT387 User Manual Page 41 of 42 Supplies VCC 3 3V 10 mA typically to the cable system VCC TCK 6 Test Clock Connect to This clock drives the test logic for all devices on SYStem TCK boundary scan chain pin GND 7 Ground To target Supplies ground reference to the cable system ground TMS 8 Test Mode Select Connect to This signal is decoded by the TAP controller to control test operations pin TDO 9 Read Data Connect to Read back data from the target system is read at this TDO pin 1 TDI 10 Test Data In Connect to This signal is used to transmit serial test instructions system and data pin Table 9 Connector JTAG Jumper Header Version 1 0 3 Page 42 of 42 SMT387 User Manual Safety This module presents no hazard to the user EMC This module is designed
11. bit SHB Interface The SHB connectors provide to the FPGA connections to the external world You can implement your own interface to transfer data over using these connectors but if you want to communicate with other Sundance TIM modules you can implement a Half Word Hw interface sitting on 25 pins of an SHB connector Then the SHBs are parallel communication links for synchronous transmission An SHB interface is derived from the SDB interface which is a 16 bit wide synchronous communication interface SUNDANCE SDB specification The differences are a The SHB interface can be made Byte 8 bits Half Word 16 bits or Word 32 bits wide The transfer rate can be increased thanks to better quality interconnect As an example let us consider the Half Word Hw SHB interface You can implement 2 x 16 bit SHB interfaces per SHB connector and have some spare signals for User defined functions no differential lines are needed thanks to our SHB cable assembly described in SHB Cable Assembly The SMT387 provides one SHB interface on one connectors and can support data rates of 400MB s at 100MHz You must refer to the latest SUNDANCE SDB specification for technical information on how it works Version 1 0 3 Page 20 of 42 SMT387 User Manual Constraint File Signal Names According to the SUNDANCE SHB specification 5 Byte interfaces from 0 to 4 can be implemented on the 60 pins of a SHB connector Each Byte interface h
12. reset and the FPGA configuration is around 4s for a SMT387 600MHz clock A typical time to wait after releasing the board reset should be in excess of this delay but no damage will result if any of the I Os are used before they are fully configured In fact the comm Ports will just produce a not ready signal when data transfer is attempted during this time and then continue normally after the FPGA is configured EMIF Control Registers xe EMIF Control Registers The C6415 has two external memory interfaces EMIFs One of these is 64 bits wide the other 16 bits Version 1 0 3 Page 12 of 42 SMT387 User Manual The C60 contains several registers that control the external memory interfaces EMIFs xe memory space CEO to CE3 A full description of these registers can be found in the C60 Peripherals Reference Guide The standard bootstrap will initialise these registers to use the following resources Memory Resource Address range space EMIFA Internal program memory 0x00000000 1MB CEO SDRAM 2x 8MB chips 0x80000000 0x807FFFFF CE3 Virtex 0xB0000000 OxBFFFFFFF Memory Resource Address range space EMIFB CE1 15 3 section of flash 2MB 0x64000000 0x641FFFFF each CE2 2 4 section of flash 2MB 0x68000000 0x681FFFFF each SDRAM xe RAM Memory space CEO is used to access 16MB of SDRAM over EMIFA The SDRAM operates at one quarter or on
13. 000 and RS 232 serial Version 1 0 3 Page 17 of 42 SMT387 User Manual communication from the PC The Parallel Cable 11 supports only parallel port communication from the PC to the Boundary Scan chain Memory Pipelined ZBTRAM Up to 4MB of pipeline ZBT memory is provided with direct access by the FPGA The ZBTRAM is designed to sustain 100 bus bandwidth by eliminating the turnaround cycle when there is transition from Read to Write or vice versa This device is well suited for SDR applications that experience frequent bus turnarounds need to operate on small data chunks especially one word chunks and need to operate at higher frequencies than permitted by the flow through version For more complete information please read General Information on how to choose your memory type according to your application For the parts datasheet please read ZBTRAM datasheets Chips parts and densities are shown in the table below ZBTRAM part Sizein Sizein Actual Amount of number bits Bytes Memory memory size per board K7N801801M 8Mb 1MB 512kx18 1MB K7N161801A 16Mb 2MB 1Mx18 2MB K7N321801M 32Mb 4MB 2Mx18 4MB Table 2 ZBTRAM sizes The total available ZBT RAM on the board is therefore 1 MB 2 MB or 4 MB Comports The SMT387 provides 6 Comports numbered 0 1 2 3 4 and 5 These are described in http sundance com docs Firmware pdf The Comport drives at 3 3v signal levels Version 1 0
14. 3 Page 18 of 42 SMT387 User Manual SHB SHB Connector The SMT387 includes a single 60 pin connector to provide SHB communication to the outside world The connector is referenced on the PCB by J2 See Figure 10 SMT387 Components placement Top view All 60 pins of the SHB connector are routed to the FPGA in all available configurations of SMT387 Figure 4 SHB Connector Features a High speed socket strip QSH 030 01 L D A K on the SMT387 mates with QTH 030 01 L D A K a QTH are used for cable assembly or PCB connecting 2 TIMs a Centreline 0 5mm 0 0197 Q QSH Connector An adapter is available for Agilent probes for the 16760A Logic Analyser The 2 probes supported are the E5378A 100 pin Single ended Probe and the E5386A Half Channel Adapter with E5378A Version 1 0 3 Page 19 of 42 SMT387 User Manual SHB Cable Assembly The cable is custom made by Precision Interconnect and a cable assembly solution builder can be found at http www precisionint com tdibrsb content howtouse asp SHB Inter Modules solutions High speed data transfer can be achieved between TIM modules thanks to the use of a 60 way flat ribbon micro coax cable or via PCB connections InterModule PCBs can be found at Inter Module Connections As a result NO DIFFERENTIAL lines are required to transfer data on long distances and at speeds in excess of 100MHz which allows the full use of the SHB connector 60 pins Half Word Interface 16
15. 3 Page 32 of 42 SMT387 User Manual used The first few blocks of data read from the SDBs will be discarded to ensure a continuous data stream Stop Stop Playback or Record When a Record operation is stopped information will be written to the discs to note the amount of data recorded Exit This has the same effect as Stop but also terminates the example SDBs You can select how many SDBs to use by clicking either 1 SDB or 2 SDBs Version 1 0 3 Page 33 of 42 SMT387 User Manual Discs You can select the discs to use by clicking IDE 0 and IDE 1 The discs will be used as follows IDE 0 Use only the disc connected as IDE 0 IDE 1 Use only the disc connected as IDE 1 Start using the disc connected as IDE 0 Once that is full IDE 0 amp IDE 1 for Record or has been read to the end Playback the selected operation will continue using IDE 1 The setting will be changed automatically if the DSP reports it can only find one disc Information The window at the bottom right of the display is used to show various status and error messages Status The user interface displays information about each disc in the system Capacity The size of the disc report by the controller Recorded The amount of information that has been written to the discs Playback Record the percentage of the disc that has been written Playback the percentage of the recorded data that have been read Rate The current rat
16. Comport links between all the modules fitted and a pathway to the host for a non stand alone system The SMT387 requires an additional 3 3V power supply as present on all Sundance TIM carrier boards which must be provided by the two diagonally opposite mounting holes SMT387 Support The SMT387 is supported by the SMT6087 software package available from SUNDANCE Please register on the SUNDANCE Support Forum if not yet registered Then enter your company s forum and you can request the SMT6087 from there SMT387 Installation Do NOT connect any external TTL 5v signals to the SMT387 I Os as the FPGA is NOT 5v compliant This implies that the Comports and global bus lines of the carrier board MUST be LVTTL and that any device driving signals on the SHB connectors must drive at LVTTL 3 3v Two types of configuration are described here nevertheless you shouldn t be restricted and should consult Sundance if your system architecture differs SMT387 Alone You can fit the SMT387 on its own on the first TIM site of one of Sundance s 3 3v compatible carrier boards plugged in a host computer PC PCI VME carrier etc like SMT310Q SMT328 SMT300 etc Please follow these steps to install the SMT387 module on a Host system 1 Remove the carrier board from the host system 2 Place the SMT387 module on the first TIM site This TIM site communicates with the host See your carrier board User Manual This allows you t
17. DR 32 bit PCI Address for Reads Writes Low 2 bits must be 00 for configuration transactions Byte enables are decoded from low 2 bits for I O transactions a FPGA PCI ADDR 1 0 00 means byte 0 is read effected a FPGA PCI ADDR 1 0 01 means byte 1 is read effected a FPGA PCI ADDR 1 0 10 means byte 2 is read effected a FPGA PCI ADDR 1 0 7 11 means byte 3 is read effected FPGA PCI DOUT 32 bit PCI Data for Write transactions FPGA PCI DIN 32 bit PCI Data for Read transactions valid only until the next PCI access Miscellaneous 1 0 There are two user defined jumper locations on SMT387 Refer to the section JTAG Multilinx headers for information on the location of these jumpers The software interface to the jumpers is located in the LED register of the standard Sundance firmware Bits 2 and reflect the status of JMPO and JMP1 respectively Bits 0 and 1 of the LED register control FPGA LEDO and LED1 respectively See Table 5 for details on LED identification LED Designator LED Color Meaning D1 Green IDEO Disk Activity D2 Green IDE1 Disk Activity D3 Red FPGA DONE Version 1 0 3 Page 25 of 42 SMT387 User Manual D4 Red DSP GPO D5 Red DSP GP1 D6 Red FPGA LEDO D7 Red FPGA LED1 PCI SATA IDSEL FPGA is used for PCI SATA IDSEL on SMT387V1 PCBs Table 5 LED Identification See Figure 10 SMT387 Components placement Top view Power Supplies
18. ES om am 2 eve 628 a s ugin oe aS a m Figure 11 SMT387 Components placement Bottom view U1 Xilinx FPGA Power Supply U2 Sil3512 U3 amp U12 SDRAM U4 Xilinx FPGA U5 Xilinx CPLD U6 TI 6415 DSP U7 ZBTRAM U14 Flash Y1 PCI Clock 33MHz Y2 EMIFA External Clock optional Y3 DSP Core Clock 12 50MHz SMT387 User Manual Page 38 of 42 Version 1 0 3 Headers Pinout SHB Header Figure 12 Top View QSH 30 Version 1 0 3 Page 39 of 42 SMT387 User Manual SHB Pinout LVTTL only J2 In the constraints file provided for the SMT387 FPGA the SHB signals have been named to match 2 16 bit SDB interfaces or Hw SHB interface pinout according to the SUNDANCE SHB specification Half Word configuration QSH Pin number QSH Pin number 1 2 SHBxUSERO 16 SHBxUSERO 17 SHBxUSERO 18 SHBxUSERO 19 SHBxUSER1 23 SHBxUSER1 24 SHBxUSER1 25 SHBxUSER1 27 SHBxUSER1 28 SHBxUSER1 26 SHBxUSER1 29 SHBxUSER1 31 SHBxUSER1 33 SHBxUSER1 34 SHBxUSER1 30 SHBxUSER1 32 SHBxUSER2 52 SHBxUSER2 53 SHBxUSER2 54 SHBxUSER2 55 Table 8 SHB interfaces table Version 1 0 3 Page 40 of 42 JTAG Multilinx headers The JTAG Multilinx headers have the following pinout TIM TINConnector XC2VP FF896 TIM Connector Figure
19. I ne 24 FPGA ADIN itte eae ns ei aa 24 Miscellaneous C 2 ons sen Suns en un en ons en 24 PONS SUP BUCS ere cc cs tua ia 25 DCDC CONVEFIE RES 26 Linear Voltage regulator tette tte TE 26 Power ConsurmpllOF i22 e doces ananas 27 Serial on ooo PPS Oben nS ts 28 Nlis e 29 COMNGUEALION DE 29 PPETOOIHISIIBS ent PROPRIA DONOR Ame eumd dee RATER 30 Hio 1 Pv ctt 30 Building the Example E Bee Bee Bee BREE BREE BREE BREE ENE Baek 30 Running the Exam law E Em 31 Yser INntetaCe i en get e FIR te CI EC E ROS QU Re n 31 Playback fut HY 31 PIayDackoto hs ssh st 31 ce eter Ne E 32 DISCS nonae a ein a E UE 33 IMTOTNAONESS shite vith 33 SAIS LE Aeneas ae nt eran A M oe E oa nk 33 Version 1 0 3 Page 5 of 42 SMT387 User Manual F rther de ASE EC e TT 33 Verification R RES EE RR RAREEERGERRERMRRR ARR 34 REVIEW 1 1 mani MI DM entente 34 Valida
20. as its own CLK WEN REQ and ACK The signal names going from the FPGA to the SHB connector use the configuration of 2 SDB interfaces So when in Half Word configuration e 16 bit data D 0 to 15 e CLKO is borrowed from Byte configuration 0 WEN1 REQ1 and ACK1 are borrowed from Byte configuration 1 to make configuration SDBA control signals and e CLK3 is borrowed from Byte configuration 3 WEN4 REQ4 ACK4 are borrowed from Byte configuration 4 to make configuration SDBB control signals The SHB connector is J2 See Figure 10 SMT387 Components placement Top view Please refer to SHB Header Version 1 0 3 Page 21 of 42 SMT387 User Manual RSL RSL Connector The SMT387 includes a single 28 pin 14 pair RSL connector The connector is referenced on the PCB by J3 See Figure 10 SMT387 Components placement Top view 16 pins 8 pairs of the RSL connector are routed to the FPGA in all available configurations of SMT387 Figure 5 RSL Connector Features a High speed socket strip QSE 014 xx DP on the SMT387 mates with QTE 014 xx DP a PCB adapters with QTE connectors on one side and QSE on the other are used for connecting 2 TIMs Samtec for details RSL Cable Assembly Cable assemblies with QTE connectors on one side and QSE on the other are like the flexible versions of the PCB adapters mentioned above RSL Interface The RSL connectors are the fastest FPGA connections available on SMT387
21. e 9 Connector JTAG Jumper 41 Version 1 0 3 Page 7 of 42 SMT387 User Manual Physical Properties Dimensions See Physical specifications of TIM specification amp user s quide Weight 68 44 with daughter module Supply Voltages See See Figure 10 SMT387 Components placement Top view Power Supplies Supply Current See See Figure 10 SMT387 Components placement Top view Power Supplies Version 1 0 3 Page 8 of 42 SMT387 User Manual Introduction Related Documents 1 Sundance High speed Bus SHB specifications Sundance http sundance com docs SHB 20Technical 20Specification pdf 2 RocketlO Serial Links RSL specifications Sundance http sundance com docs RSL 20 20 Technical 20Specification 20Rev01 20Iss03 pdf 3 TIM specifications http sundance com docs TIM Spec v1 12 pdf 4 External Interface User Manual Sundance http sundance com docs Firmware pdf Block Diagram SDRAM 128MB max 32 320 6415 S ATA Conn S ATA Conn 6 x ComPort Global Bus Figure 1 SMT387 Block Diagram Version 1 0 3 Page 9 of 42 SMT387 User Manual Mechanical Interface TIM Standard This module conforms to the TIM standard Texas Instrument Module See TI TIM specification amp user s quide for single width modules It sits on a carrier board The carrier board provides power Ground communication links
22. e accessed using the address range 0x67E00000 0x681FFFFF This gives a 4MB continuous space The flash can be divided into the four logical sections shown in the following figure paging bit is bit 21 0x67C00000 2 MBytes Section 1 CEO 0x67E00000 Page1 2 MBytes Section 2 0x68000000 Page0 2 MBytes Section 3 CE1 0x68200000 Page1 2 MBytes Section 4 0x68400000 Figure 2 Flash logical sections To change the state of the page bit you need to write to the following address as shown the data written are irrelevant Address Flash page selected 0x6C000000 0 17 and 3r sections enabled 0x6C000001 Page 1 2 and 4 sections enabled The EMIFB CEO space control register should be programmed with the value The integrated 33MHz PCI32 bus interface of the 6415 6416 DSP is used to access the Serial ATA host controller For more information on the DSP PCI interface see TMS320C6000 DSP Peripheral Component Interconnect Reference Guide SPRU581 Version 1 0 3 Page 14 of 42 SMT387 User Manual One limitation of the DSP PCI interface is that it is incapable of byte oriented reads or writes This limitation has been circumvented by implementation of this feature in the FPGA Refer to the description of the PCI interface in the FPGA section below Note Due to a defect in the DSP PCI interface the DSP should only be operated
23. e at which data are being transferred Further details Please consult the documentation included with the SMT6087 package for details on the internals of this software Version 1 0 3 Page 34 of 42 SMT387 User Manual Verification Procedures The specification design requirements will be tested using the following 1 Power module test FPGA configuration using DSP and or JTAG connector Comport transfers between a SMT376 and the SMT387 4 SDRAM memory tests SHB connector Pins Test using SHB tester PCBs Global Bus transfers between SMT387 and SMT310Q onboard SRAM Not yet implemented 7 External clock I O tested with scope 8 Serial ATA disk transfers Review Procedures Reviews will be carried out as indicated in design quality document QCF14 and in accordance with Sundance s ISO9000 procedures Validation Procedures The validation procedure is happening during the verification procedure Test that all the memories are accessible by the FPGA as well as all the communication links FPGA Constraint File General Information Since only the FF896 package type is supported on SMT387 one constraints file is provided Some pins will not be supported on VP7 Ordering Information Currently the SMT387 is available in 2 configurations Basic and Custom Basic In the basic configuration a Virtex 11 Pro 20 is used and allows interfacing to ALL the memories and ALL I Os available on the SMT387 Basic configuration inc
24. e sixth of the core clock speed with a max frequency of 133MHz Depending upon the application the best performance may be obtained whilst running the DSP at a lower clock speed Eg At 600MHz the external EMIF will only run at 100MHz core clock 6 as we are constrained by the TI imposed limit of 133MHz But if the core were running at 533MHz then the EMIF would be at the max possible speed of 133MHz 533 4 This speed adjustment is not a user option but must be adjusted during manufacture The EMIFA CEO memory space control register should be programmed with the value 0x00000030 Note that the DSP only has 20 address pins on the EMIFA but since address bits are multiplexed for SDRAM a maximum addressable space of 128MB is possible FLASH xe Flash An 8MB Flash ROM XE Flash protection algorithm device is connected to the C60 EMIFB The ROM holds boot code for the C60 configuration data for the FPGA and optional user defined code Version 1 0 3 Page 13 of 42 SMT387 User Manual The EMIFB CE1 and CE2 space control registers should be programmed with the value OxFFFFFFO3 As the C60 only provides 20 address lines on its EMIFB both CE1 amp CE2 are used to access this device This in itself allows the direct access of 4MB A paging mechanism is used to select which half of the 8MB device is visible in this 4MB window As the EMIFB CE1 amp 2 memory spaces alias throughout the available range the flash device can b
25. his board The choice of FPGA will be price performance driven The following table shows the main FPGA characteristics The choice of the FPGA also determines which board architecture you will get amount of logic available speed number and type of I Os on board Memory size and type For a complete list of the different board architectures please consult Ordering Information This Xilinx Virtex Il Pro is responsible for the provision of one SHB 6 Comports a PCI interface 8 RSLs the global bus and the ZBT memory In FULL configuration see Ordering Information SMT387 User Manual Device er a SelectRAM Blocks en Sona Blocks Blocks Slices RUE ae DCMs XC2VP7 8 1 11 088 4 928 154 44 44 792 4 XC2VP20 8 2 20 880 9 280 290 88 88 1 584 8 XC2VP30 8 2 30 816 13 696 428 136 136 2 448 8 Table 1 FPGA Choices Configuration The FPGA can be configured 2 different ways e Using SMT6001 to update the FPGA loaded from flash by the DSP See http www sundance com docs SMT6001 20User 20Manual pdf e Using the on board JTAG header and Xilinx JTAG programming tools JTAG Boundary Scan The JTAG Programmer software is a standard feature of the Alliance Series and Foundation Series software packages JTAG Programmer is a part of Web Pack which can be downloaded from the following site Xilinx JTAG programme
26. ludes 16MB of SDRAM and no ZBT SRAM Version 1 0 3 Page 35 of 42 SMT387 User Manual Custom The ordering code for custom configuration is as follows SMT387 VP20 5 x Zy Board Type Virtex II part Virtex Il speed grade On board SDRAM in MB On board ZBTRAM in MB FPGA a Part options VP7 VP20 VP30 a Speed grades 5 6 7 Note With VP7 part installed SATA connectivity is not possible and no ZBT memory can be used Memories a SDRAM 16MB 32MB 64MB 128MB a ZBTRAM 1MB 2MB 4MB SHBs a One SHB connectors is available in all configurations to allow the implementation of up to 2x16 bit SDB interfaces Comports a 6 Comports are available in all configurations Global Bus a 1 Global Bus External Clock 1 External clock I O Version 1 0 3 Page 36 of 42 PCB Layout Details Components placement eti 1 H 1 A 3 m EG 200 m Sundance Digital Signal Inc C20 m mC15 m m m 5 US Nui R3 m a Figure 10 SMT387 Components placement Top view Ct C4 J2 zs mmt in R16 E Se SMT387 User Manual 71 ze lt Version 1 0 3 Page 37 of 42 SMT387 User Manual 0 R70 RO RR HSHEHSHZHSHHHELE E LITT Be d td cm mm e e e e
27. nectors on the daughter module conforms to the Serial ATA Specification 1 0 M Figure 8 SATA daughter module Clas mulum mut 2 SS aw mmm H Digital Signal Processing Inc i Sundance S m etete settee V an PETTITT a DC MINNN Figure 9 SMT387 with SATA daughter module installed Version 1 0 3 Page 29 of 42 SMT387 User Manual Software The software developed to support the SMT387 Data Logger will transfer data between one or two SDBs and one or two discs in two modes 1 Record Read in continuous mode from the SDBs and write to the discs stopping under user control or when the discs are full 2 Playback Read from the saved data on disc and write to the SDBs This document assumes the reader is familiar with Diamond PCI Visual C and Sundance TIMs Configuration The following diagram shows the hardware configuration Root Sundance Digital Bus SDB Node Comport The Host PC runs a Visual C program Logger exe to provide a user interface Ul The two DSPs Root and Node run a Diamond application Logger app 1 Connectors for IDEO and IDE1 are labelled as and JA2 on the SATA daughter module respectively Version 1 0 3 Page 30 of 42 SMT387 User Manual Prerequisites 1
28. o use Global Bus and Comport 3 to communicate with the host 3 Make sure that the board is firmly seated and then provide the 3 3V to the board by screwing the SMT387 on the two main mounting holes with the bolts and screws provided with the board 4 Connect the SHB links if required by your application Version 1 0 3 Page 10 of 42 SMT387 User Manual 5 Replace the carrier board in the host system or power on for a stand alone carrier SMT387 DSP TIM You can fit the SMT387 coupled with a DSP module on any of Sundance carrier boards Stand alones or plugged in a Host Please follow these steps to install the SMT387 module and the DSP TIM on a carrier 1 Remove the carrier board from the host system or turn the power off for a stand alone carrier 2 Place the SMT387 module onto one of the TIM sites on the carrier board e Preferably fit the DSP TIM on the first TIM site This TIM site communicates with the host See your carrier board User Manual This allows the processor board to handle the interactions with the Host e Fit the Comport communication links between the DSP TIM and the SMT387 respecting the rules on polarity at reset See your carrier board User Manual 3 Make sure that the board is firmly seated and then provide the 3 3V to the board by screwing the SMT387 on the two main mounting holes with the bolts and screws provided with the board 4 Connect the SHB links if required by your application
29. r The JTAG chain is composed of the CPLD and the FPGA The CPLD is pre programmed by Sundance Do NOT try to reprogram the CPLD without SUNDANCE approval Version 1 0 3 Page 16 of 42 SMT387 User Manual TOI c 353b l sce vpel BYPASS BYPASS TDO Figure 3 JTAG Chain on the SMT387 When accessing the board using JTAG the CPLD can be bypassed and you can configure the FPGA only Xilinx describe how to connect both download cables at Parallel cables Xilinx describe how to configure their devices using these cables at Configuration Mode General Information For complementary and more detailed information please go to Xilinx 5 software Manuals and Help See board header pinout in Table 9 Connector JTAG Jumper Header Configuring with MultiLINX The Mutilinx cable can be used to configure the FPGA via JTAG See board header pinout in Table 9 Connector JTAG Jumper Header The MultiLINX cable set is a peripheral hardware product from Xilinx For additional information on the MultiLINX cable set go to the following site Xilinx MultiLINX cable Using MultiLINX Parallel cable III or IV The JTAG header is provided to enable device programming via suitable software Typically this will be Xilinx iMPACT Xilinx iMPACT supports both the Xilinx MultiLINX and Parallel Cable Ill download cables for communication between the PC and FPGA s The MultiLINX cable supports both USB Windows 98 and Windows 2
30. r Block is used to supply the 1 5V core voltage to the FPGA The current limit is configured for 20A Linear Voltage regulator The DSP core 3512 core FPGA VCCAUX and FPGA PCI voltages are supplied through linear voltage regulators drawn from 3 3V Version 1 0 3 Page 27 of 42 SMT387 User Manual Power Consumption Measurements were made on an SMT387 at idle with the standard FPGA configuration loaded Requirements will vary depending on software activity FPGA configuration environment and other factors Supply V Current A Power W 3 3 0 84 2 77 5 0 0 07 0 35 Total 3 12 Table 7 Power Consumption Note Figures do not include power required for the carrier board itself FPGA Depending on the implemented design the power consumption can reach 30 Watts or more Please consider connecting an external power supply to the carrier board for demanding designs Version 1 0 3 Page 28 of 42 SMT387 User Manual Serial ATA The Silicon Image 3512 host controller allows for 2x Serial ATA 1 0 compliant interfaces This device is under the control of the DSP and FPGA and requires special application software such as SMT 6087 Details of the functionality of the host controller can be found in Si 3512 PCI to Serial ATA Controller Datasheet which can be obtained from Silicon Image with an NDA Connection to Serial ATA devices requires that the daughter module be installed on the SMT387 Placement of con
31. s 600MHz the FPGA is running at 100MHz by default There is a place to install an oscillator of a different frequency on the PCB but keep in mind that this clock will also be used for the SDRAM PCI The FPGA PCI interface is required to perform byte oriented reads and writes over the PCI bus The following are the offsets of the associated PCI registers Address PCI Function 0xB0060000 FPGA PCI CMD 0xB0068000 FPGA PCI ADDR 0xB0070000 FPGA PCI DOUT 0xB0078000 FPGA PCI DIN Table 4 FPGA PCI Register Offsets Reset Configuration Read Write Set Set 3 Write Write FPGA PCI CMD FPGA PCI CMD Reset bit IDSEL FPGA PCI ADDR FPGA PCI ADDR Perform PCI Set Write Wait 1ms configuration via FPGA PCI CMD DSP PCI interface 0x2 PES Dare Clear Clear Poll for Set FPGA PCI CMD FPGA PCI CMD FPGA PCI CMD FPGA PCI CMD Reset bit IDSEL Idle 0x3 Poll for Read from FPGA PCI DATA re RONDE Figure 7 FPGA PCI Command Sequences Version 1 0 3 Page 24 of 42 SMT387 User Manual Note An example of these procedures is available in software package SMT6087 FPGA_PCI_CMD a FPGA PCI CMD 3 0 FPGA PCI Command 0 2 O Read 0 3 Write a FPGA PCI CMD 12 DSP IDSEL a FPGA PCI CMD 13 SATA IDSEL a FPGA PCI CMD 15 PCI Reset a FPGA PCI CMD 16 FPGA PCI Idle read only FPGA PCI AD
32. tion ee SacabesaSamsnaesenasucesuansesunencbesaneuasioune 34 FPGA Constraint File General Information 34 Ordering Information tn 34 E ER rs edd tice sea nus kes Soa Ds Puits BA Eee ue BU PP 34 CUSIOM 35 DEDE DUDEN CE eM OMNE TM 35 juice Oar 35 on PN 35 COMPOS enas a a a a a 35 CIA UE UE E EDEN 35 External GIOCK ct e Ua eR a a CE CIUS AR HIS QUT 35 PCB Layout Detalls iecit cet CEPS CP DIEI 36 Components eare ereere tete RE 36 Headers PIBOUL aa a ee ce ap a eh ed sara ene nee ee eva vee ce eee nese 38 SHB nn 38 SHB Pinout EVITE Only reir ret tto rao tae eot UE 39 JTAG M ltilinx headers mme on aded dte ame he eee 40 JTAG Boundary scan User defined jumpers pinout JP1 JP2 40 p OEE 42 Version 1 0 3 Page 6 of 42 SMT387 User Manual Table of Figures Figure 1 SMT387 Block Dice rein oi Seis once Hbc tee 8 Figure 2 Flash logical sections eeren 13 Figure 3 JTAG Chain on the SMT387
33. to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot
34. y significant as any Sundance TIM with one or two SDBs may be used The application in the kit has been built assuming an SMT376 you will need to modify Logger DSP Logger cfg and reconfigure the application if a different type of TIM is to be used Version 1 0 3 Page 31 of 42 SMT387 User Manual Running the Example The example is executed by running Logger exe This resets the DSPs loads them with Logger app and starts them running It assumes that Logger app is in the same directory that contains Logger exe Note that it takes a few seconds to reset the SMT387 User Interface Once the DSPs have been successfully started running the following window will appear Sundance Logger Disc information Playback to file Capacity Recorded Playback Rate IDEO 232 9GB 1 4GB 0 OKB s 2329GB 270GB 0 12MB s ERES EE RT E RR E ER ER RR ER RE RE E REL ER Terminating ee Recording finished IDEO M IDE 1 The top five buttons are Playback Start transferring data from the discs to the SDBs The transfer will stop once all the written data have been moved Playback to Ask for an output file name and start transferring data from the discs to that file The transfer will stop once all the written data have been moved Record Delete any existing data on the discs and start transferring new data from the SDBs to the discs The transfer will stop once all the available space on the discs has been Version 1 0
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