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DPC31 User Manual

1. Sampling_ Sampling_ Mode Bit 1 Mode Bit 0 Sampling_Mode o Depending on the sampling mode setting a window of uncertainty results for the differentiation of a short pulse or long pulse when the physics unit is operated in energy saving mode see Section 5 7 3 3 00 gt 2 5 us to 3 0 us 01 gt 3 0 us to 3 5 us 10 gt 3 5 us to 4 0 us 11 gt 4 0 us to 4 5 us 4 ASIC Interface Interrupt Controller Register Int Mask Reg Int Ack Reg Int Req Reg Int and Int EOI Reg The meaning of these registers will be explained in later chapters The interrupt controller exiDXB twice for ext uP and C31 Both are instances are mapped onto the same addresses Mode Register1 ext uP and C31 write access Mode Register1 is used for parameterizing single bits These bits are control bits and internally directly affect the hardware The meaning is described below Different addresses are used for setting and resetting Mode Register1 set reset A logical 1 is written to those bit positions that are to be changed All other bit positions must be logical 0 Int_ Is Dis_Clkout1X4 Dis Clkout1X2 Stop_Del Polarity aytimer 7 0 Stop_Delay Timer The delay timer is stopped 0 The delay timer is not stopped default 1 The delay timer is stopped Dis_Clkout1X2 The clock output Clkout1X2 is switched off of the internal clock asyn 24MHz syn 1 to 8 MHz After being switched on and in the reset phase th
2. Table 5 1 3 Overview of Indications and Confirmations Note MAC_Stop confirmation confirms the MAC transition to the Offline mode after the current request has been processed SAP_Act Deact Confirmation confirms the execution of this FMA request Get_Ind_Resp_Buffer Confirmation confirms retrieval of the buffer 5 2 DPS Module Description of the Interface DPS is enabled in the param register with DP_Mode 1 and started in the Instruction_Queue with the MAC request MAC_ Start The user can disable the SAP55 Set_Slave_Address The DPS protocol is integrated completely into the DPC31 All other DP SAPs are always enabled except for the following default SAP SAP 56 SAP57 and SAP58 The remaining four SAPs are enabled only when the Data_Exchange mode is entered 3 DPC31 HW Description Version V2 1 Page 33 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Daa Default SAP Ind_Puffer Ptr H grg T SE Resp_Puffer Ptr bn or p ee aper Resp Puffer Pr EECH a a 2 gt el mac_ec Putter EE U_Diag Puffer ses Reap FOE PE a EM ecru epes md Pufler Pr L_SSA Puffer ES 2 eet Ind Puer Pr U_Prm Puffer EE eer Ia Puer Pr e Wu ota Putter EE Sapss JS Eet Jk kel W pm DXB_SCB DXBO_D_Puffer Ptr DXB7_D_Puffer Prr vier DXB7 Puffer Pufferanordnung Fig ure 5 2 1 DPS Buffer Structure Figure 5 2 1 shows the DP
3. 0 The improved quick synchronizer is off 1 The improved quick synchronizer is on EOI Timebase Time base of the EOI timer 0 The interrupt inactive time is 1 to 2 usec 1 The interrupt inactive time is 1 to 2 msec Early_Ready Early Ready Signal 0 Ready is generated if the data is valid Read or if the data is taken over write 1 Ready is moved ahead by one clock pulse En_Clock_Sync Enable time of day synchronization 0 The time of day synchronization is blocked 1 The time of day synchronization is enabled DP_Mode Enable of DPS 0 DPS is not enabled 1 DPS is enabled Sync_Supported Support of Sync_Mode 0 The Sync_Mode is not supported 1 The Sync_Mode is supported Data is made available in the N Buffer of the Dout SM not comparable to ASIC LSPM 2 Freeze Supported Support of Freeze_Mode 0 The Freeze Mode is not supported Page 20 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS Failsafe_Mode XDP FDL_MinTSDR New GC Int Mode DPC31 HW ComDeC 1 The Freeze Mode is supported Data is frozen from the N buffer of the Din SM not comparable to LSPM 2 Support of Failsafe_Mode 0 Failsafe_Mode is not supported 1 Failsafe_Mode is supported Default setting of MinTSDR according to Baud rate Detect for DPS or combo operation 0 Pure DPS operation 1 Combo operation XDP FDL_MinTSDR XAsyn Syn Baud rate Twintsor tgit 9 6
4. User_Cfg_Ok Cmd the above mentioned buffers are exchanged The exchange is confirmed with the interrupt Get_Cfg_Buffer_Changed Syn_Clkin o Setting the external clock pulse supply at Pin XTAL1_CLK not via PLL The internal C31 processes with half the clock frequency 00 External clock 2 MHz gt Baud rates 31 25 01 External clock 4 MHz gt Baud rates 31 25 10 External clock 8 MHz gt Baud rates 31 25 11 External clock 16 MHz gt Baud rates 31 25 Check DV Enable Control of the MSAC1S SAPs SAP50 52 is tied to the cyclic machine if DPV1_Enable 1 in the Set_Prm frame 0 Nocheck of DPV1_Enable in Set_Prm frame 1 DPV1_Enable is checked in Set_Prm frame Preamble 0 For the syn physics the preamble length is parameterized in number of bytes 00 gt 1 byte 01 gt 2 bytes 10 gt 4bytes 11 gt 8 bytes En_DXB _ Publisher Enable as Publisher for internode communication 0 Publisher mode is blocked DDB request frames are filtered basic setting 1 Publisher mode is enabled for all SAPs for the FDL SAPs the user must set Access_Value 8h Check_En_Prm_Cmd In the Set_Prm frame the En Pm Cmd bit DPV1_Status_3 Bit7 is scanned and brings about the appropriate responses 0 No check of the En_Prm_Cmd bit in the Ger Pm frame 1 The En_Prm_Cmd bit is checked in the Set_Prm frame En_Erw_Prm This bit enables the expanded parameter register at address 083Fh 0 No expanded parameter re
5. 1 and for a write access from the falling edge of the E_Clock in addition XCS 0 RW 0 DPC31 HW Description Version V2 1 Page 93 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EM E N S Un E Clock Pulse Width Address AB 2 setup time to E_Clock T Address AB al hold time after E_Clock J E Clock T to Data Active Delay E Clock T to Data valid access to RAM E Clock T to Data valid access to the registers Data hold time after E_Clock J R_W setup time to E_Clock T R_W hold time after E_Clock J XCS setup time to E_Clock T XCS hold time after E_Clock 4 Data setup time to E_Clock 4 Data hold time after E_Clock J XCS AS log 1 Figure 9 5 8 Synchronous Motorola Mode Processor Read Timing Page 94 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC E_Clock XCS Figure 9 5 9 Synchronous Motorola Mode Processor Write Timing 9 5 2 5 4 Asynchronous Motorola Mode for example 68HC16 In the asynchronous Motorola mode the DPC31 behaves in principle like a memory with Ready logic and the access timing depends on the type of accesses The request for a Read access to the DPC31 is generated from the rising edge of the AS signal in addition XCS 0 R_W 1 and for a write access from the rising edge of the AS signal in addition XCS 0 RW 0 60 Address se
6. DPC31 HW SIEMENS 12 2 2 Wiring Example RS485 Interface plays aiqissod se poys se d y aq jsnw Sau nofe Sdz pue Sd sn 0 UoI eIOS je0119918 Jueyodw A009 duzz gZ AZ lt ebeyon rezu ele JOALIG axy axl cELOHbZ SLY Page 109 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved ComDeC DPC31 HW SI EMENS Explanation of the Circuit At the bus driver 75ALS176D the EN2 input is to be connected to ground so that the DPC31 can listen in during transmission No additional filters are to be installed in the send and receive line in order to keep the capacity of the lines as low as possible 15 25 pF 13 Appendix 13 1 Addresses PROFIBUS Trade Organization PNO Office Haid und Neu Strasse 7 76131 Karlsruhe Germany Phone 0721 9658 590 Technical Contact Persons at the Interface Center in Germany Siemens AG A amp D SE RD73 Mr Putschky Mailing Address Postfach 2355 90713 Fuerth Germany Street Address Wuerzburger Strasse 121 90766 Fuerth Germany Phone 0911 750 2078 Fax 0911 750 2100 EMail Gerd Putschky siemens com Technical Contact Persons at the Interface Center in the USA PROFIBUS Interface Center One Internet Plaza Johnson City TN 37602 4991 Fax 423 461 2103 Your Partner Phone 423 461 2576 E Mail profibus center sea siemens com 13 2 General Definitions of Terms ASPC2 Advanced Siemens PROFIBUS Co
7. Data_Ex state When Enable Prm_Cmd 0 a Leave Master is executed In the case of this Leave_Master the diagnostic bit Diag_Prm_fault is set DPS evaluates the first 7 bytes or the first 10 bytes for longer Prm messages refer to Figure 5 2 3 The evaluation is performed according to EN 50 170 Volume 2 and will not be discussed in more detail in this description In the case of negative validation DPS sets corresponding diagnostic bits and branches into the Wait_Prm mode If the master requests Sync_Req or Freeze_Req and the application does not support Sync or Freeze Sync_Supported 0 Freeze_Supported 0 in the param register the Prm message is not accepted and the diagnostic flag Diag Not_Supported 1 is set In case of positive validation new valid message DPS makes the transition to Wait_Cfg and executes the following responses depending on the data length e If Lock_Reg 0 and Unlock_Regq 0 only the parameter MinTSDR is accepted internally S R unit and no response is initiated to the user If MinTSDR 00H the old value is saved The S R unit waits at least 11 Ten prior to sending its response messages If a MinTSDR lt 11 is parameterized the time is set to 11 by the ASIC e If Lock_Reg 1 and Unlock_Reg 0 the DPS accepts the following values Flag WD ON watchdog factors WD_FACT1 2 the min station delay response MinTSDR if i
8. ComDeC DPC31 HW SI EMENS DPC31 l l l l l l l l l l l l c1 XTAL1_CLK l l l I l l I ux CLK_UNIT OSC PLL c2 XTAL2 CLKOUT1X2 CLKOUT1X4 Figure 7 8 1 Block Diagram of Clock Supply eo e XTAL1_CLK Quartz connection direct clock input for syn mode XTAL2 Quartz connection XPLLEN Selection PLL or clock input CLKOUT1X2 Half of the internal clock clock for In Circuit Emulator or the internal clock CLKOUT1X4 Quarter of the internal clock Supply pin of PLL Supply pin of PLL Table 7 8 1 Pins for the Clock Supply C1 198 XTAL1_CLK GND 99 XTAL2 GND Page 80 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Component Value Q1 12 MHz quartz Epson type MA505 MA506 MA406 MA406H Rs 2 7 KQ Rf 1 0 MQ C1 22 pF C2 22 pF Table 7 8 2 Component Values of Oscillator Wiring Notes on PCB layout e Place all components of the quartz interface connection as close as possible to Pins 98 and 99 e No other signals should cross the area of the quartz interface connection nor the other signal positions e The CLKOUT1X2 signal Pin 100 should be routed in the maximum possible clearance to the quartz interface connectio
9. Page 104 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved ComDeC DPC31 HW SIEMENS Table 10 1 1 Dimensions of PQFP Housing of AMI in mm Page 105 05 04 Version V2 1 Copyright Siemens AG 2004 All rights reserved DPC31 HW Description ComDeC DPC31 HW SI EMENS 11 DPC31 Pinout Pn Name O e ees n Name e re o mw CT z po fw efo ew o pe p o e e mon ma BER m Senna Is PB moun ma Te Ps mon am TB PB mon am TE Be PB mon am Pe mon jmA e PM mau ma PL a L e ppe mo a e o e A e e S es e a Emo Jona es PO L am a a a S A e e K ic e ma Pe ee ca on er ee ak 20 fm emo Jama a Ps mon am Te mon Jama 7a Ps mau am Te mon Jam 75 PO mau am ape ma m e PO o ma EES Te o ope ma a U CK BE u EEE Cafe out fama at Bor m Ce pe rout fama e Boom m OT m PPG wo Jam Ba Bus m Sie wor Is BC OS eT pa o Jam as e m ___ mon Jana er mo ANS Im Sohmmrme EE u je nr Sem eo pesona on om Ef o ojm fem o I o DR E a ft me for To C epe pe o ee fon a Ca f mo e LS oora als mon Is a JI Jm TR EE PR mon Jama IB L m TR mon Jam S om Table 11 1 Pin Assignment of the QFP 100 Casing signals starting with X are low active Page 106 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 12 Application Notes 12 1 DPC31 Wiri
10. and because of the normally relatively long catch time of a phase control loop it is necessary to provide the clock recovery with a quick synchronization setup quick synchronizer which at the beginning of each receive process quickly synchronizes the recovered clock with the receive signal The signal RxA generated by the line activity detector switches the synchronizer into a quick synchronization mode at the beginning of a message In this mode the fourth zero crossing or the first four zero crossings of the signal supplied by the preamble filter leads to resynchronization Zero_Phase transition to the initial state respectively After the quick synchronization phase the receive clock is corrected only with 1 16 clock period regarding phase deviation from the signal FRxS This state is retained until the next falling edge of the signal RxA The DPC31 has an improved quick synchronizer To activate it the user must set the bit Quick_Sync_New 1 in the param register refer to Chapter 3 3 In this mode the DPC31 attempts to more accurately determine the bit center during the preamble phase by recording the duration of the last high and low phase before the A edge From the average of these two numbers it calculates a correction value which is taken into account when the bit center is specified The data decoder scans the filtered receive signal with the recovered receive clock positive edge and passes on the sc
11. numbers the compatible versions DPC31 Release gt is the index within a compatible version Bit 3 0 Meaning 0000 DPC31 Step A 0001 DPC31 Step B 0010 DPC31 Step C Rest not possible so far DPC31 HW Description Copyright Siemens AG 2004 All rights reserved Version V2 1 Page 19 05 04 ComDeC DPC31 HW SI EMENS In the Param Register individual parameter bits are transferred that are to be changed only in the MAC state Offline however When the request MAC Start refer to Chapter 5 1 2 is executed these parameters are distributed by the sequential control system to the individual modules Subsequent changes are not taken into account En Clock Early_ EOI Quick_Sync GIM_EN XRTS Sync Ready Timebase _New ADD 7 Check_No_ CheckNo New_GC_ XDP FDL Failsafe Freeze_ Sync_ DP_Mode GC Desen Pom Int_Mode MinTSDR Mode Supported Supported ed Reserved 15 En Change XAsyn Syn Syn Baud Syn_Clkin Syn Clin Check _Cfg_Buffer DP V1 Enable Disable C En LM Valt EN Erw Prm Check En EnDXB Preamble Preambleo Buffer Prm Cmd Publisher 27 24 XRTS ADD Switchover Output TxE syn physics for different driver control 0 RTS Signal 1 ADD Signal GIM_EN Galvanic Isolation Mode for syn physics 0 The power saving interface is switched off 1 The power saving interface is switched on possible only for 31 25kBd Quick_Sync_New Switching on the improved quick sync
12. that on the basis of IEC 61158 support or completely process the data traffic between the individual automation stations To support intelligent master slave solutions that is implementations with a microprocessor the following ASICs are available All ASICs do the following support the transmission rates of 9 6 kBits s 12000 kbit s autonomously set themselves to the transmission rate specified by the master and monitor it After these ASICs receive a correct message they autonomously generate the requested response messages In the ASPC2 Advanced Siemens PROFIBUS Controller many components of Layer2 of the OSI model are already integrated according to ISO but it still needs the support of a processor This ASIC supports baud rates up to 12000 kbit s however in its complexity it is conceived more for master applications The SPC3 Siemens PROFIBUS Controller through the integration of the complete PROFIBUS DP slave protocol considerably relieves the processor of an intelligent PROFIBUS slave However in the field of automation there are also simple devices such as switches thermoelements etc that do not require a microprocessor for recording their states For a low cost adaptation of such devices two additional ASICs are available the SPM2 Siemens PROFIBUS Multiplexer Version 2 and LSPM2 Lean Siemens PROFIBUS Multiplexer These chips process as DP slaves in the bus system The LSPM2 has the same functions as the
13. the clock pulse is generated with an integrated oscillator and an analog PLL in the DPC31 The oscillator pins XTAL1_CLK and XTAL2 are as shown in Figure 7 8 1 wired with the values according to Table 7 8 2 The following PLL quadruples the input frequency of 12 MHz pin XPLLEN low The DPC31 now has the internal system frequency of fsys 48MHz It is not possible to connect the PLL with an external clock pulse generator The internal system clock has an inaccuracy from the external quartz here assumed to be 150 ppm plus the inaccuracy of the PLL 200 ppm The rise time of the PLL is at 1 ms after the supply voltage and the external quartz have stabilized In the synchronous mode the lower system frequency fsys 16 8 4 2 MHz is supplied via an external clock pulse generator directly at pin XTAL1_CLK The integrated oscillator and the PLL are switched off in that case pin XPLLEN high power save mode 2 MHz system frequency is not enabled To connect an external Processor the output CLKOUT 1X2 fsys 2 or fsys and or CLKOUT 1X4 fsvs 4 can be used The outputs are active after being switched on also during the reset phase and can be switched off via Mode Register0 The internal processing clock pulse is fsys 2 The bus physics unit is operated with the scanning frequency 4 fold for asynchronous 16 fold for synchronous DPC31 HW Description Version V2 1 Page 79 Copyright Siemens AG 2004 All rights reserved 05 04
14. z B Hitex MX51AH mit PV Kabel und SAB C501 AB DB RD WR CS Addr Latch RAM AB DB DOE ROM Jequod MH 1 Odd SN3WN3IS SIEMENS 9 Electrical Specifications 9 1 Maximum Limits DPC31 HW ComDeC EE DC voltage supply Input voltage e Al inputs except Pin 98 e Pin 98 XTAL1_CLK Output voltage e All outputs except Pin 95 96 99 e Pin 95 96 99 DC output current min Vo OV short circuit Ambient temperature Topt Storage temperature Tas Power loss for PQFP 100 Pimax Junction temperature Vimax Rip junction case Hu Du case ambient Du Rin junction ambient Du Table 9 1 1 Maximum Limits 9 2 Permitted Operating Values 0 3 to 4 0 0 3 to 6 0 0 3 to Vpp 0 3 0 3 to 6 0 0 3 to Vpp 0 3 lo 4 0mA 13 lo 8 0mA 26 40 to 85 55 to 125 125 In DPC31 Step A B Pin 98 was not examined separately in this table Re In DPC31 Step A B Pins 95 96 and 99 were not examined separatedly in this table e The output itself can supply a maximum voltage of Vpp 0 3 V Higher voltages at the output pins have an external cause e g pull up resistors DPC31 HW Description Copyright Siemens AG 2004 All rights reserved Version V2 1 Page 83 05 04 ComDeC DPC31 HW SI EMENS Parameter DC supply voltage Input voltage Low Level K Input voltage High Level 1 51 Input voltage Low Level trigger Input voltage High Level tri
15. 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC BREN Baud rate Enable Bit 0 Baud rate generator is disabled power save 1 Baud rate generator is enabled Control2 Register Bit Position 7 6 5 4 3 2 1 0 Dede le es Wee ed Default 0 0 0 0 0 0 0 0 r r r r r r w r w r w Bit Function DW Data Width Selection 000 Transfer data with 8 bit length 001 Transfer data with 1 bit length 010 Transfer data with 2 bit length 011 Transfer data with 3 bit length 100 Transfer data with 4 bit length 101 Transfer data with 5 bit length 110 Transfer data with 6 bit length 111 Transfer data with 7 bit length Status Register Bit Position 7 6 5 4 3 2 1 0 BUSY REC PERR RBFU TBEM e Feen Default 0 0 0 0 0 0 0 1 r r r r r w r w r r TBEM Transmit Buffer Empty Flag 0 Transmit buffer is full 1 Transmit buffer is empty RBFU Receive Buffer Full Flag 0 Receive buffer is empty 1 Receive buffer is full PERR Parity Error Flag 0 No parity error in data byte 1 Parity error in data byte has to be reset by the user RECERR Receive Error Flag 0 No receive buffer overflow 1 Receive buffer overflow has to be reset by the user BUSY Busy Flag 0 No action SSC module can be reparameterized EN Action on the bus reparameterization not permitted These bits are ORed to the interrupt SSC_Interface They must have been enabled in the Interrupt Enable Register Interrupt Enable R
16. All rights reserved SI EMENS DPC31 HW ComDeC 9 5 2 6 C31 Memory Interface internal C31 on external memory Sg Om ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to XPSEN XPSEN pulse width XPSEN to valid instr in 6T 27 0 Input instruction hold after XPSEN Input instruction float after XPSEN 2T 4 0 Address to valid instr in 10T 45 6 Address float to XPSEN XPSEN to XCSCODE 5 0 XCSCODE pulse width Input instruction hold after XCSCODE Input instruction float after XCSCODE C for Port A 120pF C for XPSEN 10pF C for all others 80pF Table 9 5 11 Timing Values for Accesses to Code Memory E tLHLL SS De ALE tpLscL 4 tscLscH XCSCODE i tPLPH XPSEN j taviL tpL v tbx z tazp tLLax tex tiv taviv tscx z tsbxix PA A0 A7 Instr In i A0AT PC A8 A15 A8 A15 Figure 9 5 12 Code Read Cycle DPC31 HW Description Version V2 1 Page 97 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Symbol Uni ALE pulse width 4T 4 5 XRD pulse width 12T 1 8 XWR pulse width 12T 1 9 Address hold after ALE 4T 4 3 XRD to valid data in 10T 33 9 Data hold after XRD Data float after XRD AT 2 3 ALE low to valid data in 16T 31 7 Address to valid data in 18T 41 7 ALE to XWR or XRD 6T 1 5 Address valid to XWR or XRD XWR or XRD high to ALE high 2T 03 Data valid to XWR D
17. BitAddress Adr_F BitAddress Adr_Fz BitAddress Adr_F3 BitAddress Adr_Fa BitAddress Adr_Fs BitAddress Adr_Fe BitAddress Adr_F7 BitAddress Version V2 1 Dir_Reg_E7 o 0 Out 1 In Addresses Adr_E7 9 ByteAddress Adr_Eo BitAddress Adr_E BitAddress Adr_Es BitAddress Adr_Es BitAddress Adr_Ea BitAddress Adr_Es BitAddress Adr_Es BitAddress Adr_E7 BitAddress Page 55 05 04 ComDeC DPC31 HW SI EMENS 7 1 3 Interface Signals Pin Name Signal Names Comment uP Interface IO Interface Intel Intel Motorol Motorol sync async sync async PE7 0 D ai D o D o D o V PE7 0 O high resistance at reset AB7 0 O PF7 o ABis As AB7 0 AB7 0 I PF7 0 UO PGa 0 GND ABi3 9 ABi2 8 ABi2 8 PGa o IO PGs X INT X INT X INT X INT O PGs O Interrupt polarity can be parameterized PGe Von XCS XCS XCS PGs O Chip select PGr XWR XWR E Clock GND I PGr O Intel Write Motorola E Clock PHo XRD XRD R_W R_W l PHo VO Intel Read Motorola Read Write PH ALE Von Von AS PH O Address Latch Enable PH2 XRDY XDSACK O PH2 O Ready Signal BUSTYP2 0 001 000 011 010 I 1 71 Setting of the interface RESET RESET RESET RESET RESET I RESET Reset input Table 7 1 3 Interface Signals for uP and IO Interface The data bus outputs are high resistance during the reset phase In the test mode all outputs are switched to high resistance 7 1 4 Interrupt Contr
18. FDL Ph layer interface the sublayers Ph DIS DCE independent sublayer and Ph MDS medium dependent sublayer for wire media and the corresponding MDS MAU interface In addition the station management physical layer interface is implemented parts of the service primitives optionally defined in Standard IEC 1158 2 The so called medium access unit MAU is not implemented which includes the following the initial pulse shaper the line driver the receive amplifier the receive filters and the line coupling if needed with remote supply setup The MAU can be set up with little effort with the SIM1 Analog ASIC l Manchester TxS Ran ncoder Tx Register Be bk RTSIAD Tx Buffer Generator A Tx Control Gap Timer FCS Generato i A Receiver s lt C S R_Unit Rx Control Clock i 4 gt FCS Check ee EI l l 1 A v i Rx Register Manchester r Rx B fn a Decoder Receive lt RxS eect Delimiter Filter Table7 5 2 Block Diagram of the Synchronous Interface 7 5 2 1 Transmitter The transmitter converts the parallel data structure into a serial data stream The synchronous transmission procedure according to IEC 1158 2 processes with Manchester coding and start and end delimiters Each message is preceded by a preamble The length of the preamble is stored in the preamble register refer to 3 3 In contrast to t
19. Ports A B D E F G and H This is not necessary for Port C since it is permanently configured as output A bus contention is permitted for a maximum of 20ns DPC31 HW Description Version V2 1 Page 11 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 3 Memory Assignment 3 1 Memory Area Distribution in the DPC31 Table 3 1 1 shows the distribution of the internal 8k address space of the DPC31 Via this address space the user interface to communication DPS is mapped It does not matter whether the user program is running internally on the C31 or on the external microprocessor the interface is identical in both cases The address area is subdivided into a 2K address space for the register cells and a 6k address space for the internal RAM The internal registers interrupt controller Mode Register1 DPS control units SSC interface are located in the register area Certain registers can only be read or written The RAM starts at address 800h In the first area the internal work cells are located bit array variables The user is not to access this area The sequential control system uses these cells for processing the protocol Starting with address 0840h the organizational parameters parameter cells buffer ptr pointer are located in the RAM In the parameter cells general parameter assignment data is transferred Param Register station address Ident No etc or status displays are stored stat
20. Reserved 0010h C31_Control Registerz o Refer to Chapter 4 ES ae 001Fh 0020h SSC_Recev Buf7 o Receive buffer of the SSC interface 0021h SSC_Sta Regs3 o Status register of the SSC interface 0022h SSC_Citrl1 Regz o Control register of the SSC interface Reserved EEE Reserved positively prm message positively prm message negatively a prm message positively Cmd o a prm message negatively positively negatively 0037h User_Diag_Read Cmd The user makes a new diag buffer available 0041h User New _DXB4 Cmda o The user fetches the last DXB4 buffer from the N state 0042h User _New_DXB5_ Cmda o The user fetches the last DXB5 buffer from the N state 0038h User _Get_Cfg Read Cmd The user makes a new Get_Cfg buffer available DPC31 HW Description Version V2 1 Page 13 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS User_New_DXB6_ Cmd2 0 The user fetches the last DXB6 buffer from the N state 0044h User_New_DXB7_ Cmd2 o The user fetches the last DXB7 buffer from the N state Reserved l 07FFh Table 3 2 1 Assignment of the Internal Register Cells for READ Page 14 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Interrupt Controller Register 0001h Int Req Regis e 0002h Int Reg Reg s 1s 0003h Int Reg Reg s 24 0004h Int Ack Regz o 0005h Int Ack Reg ss 0006h Int A
21. SPM2 but with a lower number of I O and diagnostic ports The DPC31 DP Controller with integrated 8031 core is a highly integrated PROFIBUS slave ASIC The DPC31 is a slave controller for both PROFIBUS DP DPV1 and PA applications The uses of this chip cover a wide area On the one hand it can be used for simple intelligent applications that make do with the integrated C31 core On the other hand it can be used for high performance slave solutions that have increased communication requirements This requirement is met with an internal RAM that has been increased to 6kByte Approximately 5 5kByte of communication memory is available to the user The DPC31 has the following main features e integrated standard C31 core with an additional 3 timer Timer 2 e low processor load through the integration of the complete DP slave protocol e simple processor interface for a large number of processors INTEL 8032 80x86 Siemens C166 Motorola HC11 HC16 HC916 e SSC interface SPI for interfacing serial EEPROMs A D converters etc e integration of synchronous as well as asynchronous bus physics This document explains the hardware configuration and the wiring of the DPC31 DPC31 HW Description Version V2 1 Page 7 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS In addition Siemens offers a separate software package that relieves the user of local H W register manipulations and memory calculations T
22. Set_Ext_User_Prm Frame Once DPS has received a plausible frame an Indication occurs i e DPS swaps the Indication buffer in the Ext_User_Prm SAP for the Ext_User_Prm Buffer from the DPS buffer management and a New_Ext_User_Prm_Data Interrupt is generated No reaction occurs at this time during the sequence The user must check the Eat User Pm Daten and provide either a positive or negative acknowledgement see above The Ext_User_Prm_Ok Cmd Ext_User_Prm_Not_Ok Cmd acknowledgements are read accesses to defined register cells with the corresponding messages Not Allowed Ext_User_Prm_Finished or Ext_User_Prm_Conflict Ext_User_Prm_Ok Cmd Read Operation Fo fo o fo fo o LserAk JL User Acko User Ack a 00 Ext_User_Prm_Finished User_Ack o 01 Ext_User_Prm_Conflict User_Ack o 11 Not_Allowed User_Ack o 10 not possible Ext_User_Prm_Not_Ok Cmd Read Operation fo fo fo fo o o ser Ack User Acko User_Ack o 00 Ext_User_Prm_Finished User_Ack o 01 Ext_User_Prm_Conflict User_Ack o 11 Not_Allowed User_Ack o 10 not possible Table 5 2 8 Coding of Ext_User_Prm_ Not _Ok Cmd DPS memorizes the current Master Add at each trigger When the DPS interrupts are processed DPS first checks to determine whether the current Master Add still corresponds to the previously stored Masier Add If not a different master has taken over in the meantime and thus events
23. Ty 95 C 7 68 mA 8 mA cell 3 3 V Von 3V Output current 1 level lon Von 2 4 V Ty 95 C 7 68 mA 8 mA cell 3 3 V Vbo 3V Output current 0 level lo Vor 0 4 V T 95 C 1 92 mA XTAL2 pin 3 3 V Vpp 3 3V Output current 1 level lon Von 2 4 V Ty 95 C 1 92 mA XTAL2 pin 3 3 V Vpop 3 3V Tristate output leakage current loz Vo Von or GND 10 uA Short circuit current los Vo 0V 145 mA Vpp 3 6V T 40 C Input capacity Cn f 1 MHz 10 20 pF Output capacity Cour f 1 MHz 10 20 pF I O capacity Cio f 1 MHz 10 20 pF Table 9 5 1 DC Specification of the Pad Cells 14 All inputs except Pins 6 87 88 and 98 15 al outputs except Pins 95 96 and 99 Each output can cause a maximum level of Voo to flow if a higher level exists at an ouput this is dependent on an external component e g pull up resistors Applies to Pins 95 96 and 99 18 Applies to Pins 6 87 and 88 DPC31 HW Description Version V2 1 Page 87 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 9 5 AC Specification 9 5 1 Driver Capability The run times at the chip outputs always depend on the driver capacity of the pad cells as well as on the assumed capacitive load The capacitive load that was used as a basis for the following timing specifications is shown in Table 9 6 1 To specify the maximum and minimum runtimes the variations of temperature range and supply voltage range shown in Table 9 3 1 w
24. in Data_Exchange User Leave Master If bit En LM _Val1 0 in the parameter register the user then uses this request to initiate a Leave Master without the bit Diag Cfg_Fault being set simultaneously in the diagnostics If on the other hand bit En LM Vali 1 is set in the parameter register the user uses this request if bit 0 in Value1 is set to initiate a Leave_Master amp Diag Cfg_Fault 1 or if the bit is not set to initiate a Leave_Master without bit Diag Cfg_Fault being set simultaneously in the diagnostics Special Operating Cases 1 Ifa User Leave Master is provided with Cfg_Fault in the request interface and the diagnostic buffer is being sent during this evaluation then e Only one internal memory bit is set e Diagnostic bit Diag Cfg_Fault is set once the diagnostic buffer is available again due to the set memory bit 2 If two User Leave Master one with and one without Cfg_Fault are placed in direct succession in the request interface diagnostics are not fetched at the present time That is the diagnostic buffer is available then e The request sets the diagnostic bit Diag Cfg_Fault with Cfg_Fault e A subsequent request without Cfg_Fault on the other hand does not reset the diagnostic bit Diag Cfg_Fault 3 If two User Leave Master one with and one without a Cfg Fault are place in direct succession in the request interface and the diagnostic bu
25. interrupt latency To bypass it the interrupt DX_OUT can directly be applied to the port PB3 if a global control message is received with Sync provided Enable DX_OUT_Port 1 was parameterized in the C31_Control register beforehand Thus external HW support or separate interrupt processing could bring about the transfer from the buffer to the I O in a fixed time reference DPC31 HW Description Version V2 1 Page 43 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS With Freeze the available Din buffer in N is frozen to D Thus in distinction to the LSPM2 no updating is provided at this time from the I O To circumvent this the user would have to make the input data if it changes available immediately in the N buffer high processor capacity required For each valid Global_Control message the Control Command byte is stored in the RAM cell GC_Command At initialization DPS preassigns FFh not a valid value to the RAM cell GC_Command The user can read and interpret this cell Depending on the setting of New_GC_Int mode refer to Param Register the interrupt New_GC_Command is generated With New_GC_Int mode 0 the interrupt is generated only if the Control_ Command byte for the last received Global Control message has changed With New GC Int mode 1 the interrupt is generated after each receipt of a GC message Equidistant Cycle Sync Cl
26. kBd 19 2 kBd 45 45 kBd 93 75 kBd 187 5 kBd 500 kBd 1 5 MBd 3 MBd 6 MBd 12 MBd 31 25 kBd Interrupt Mode for New GC Command 0 The New_GC_Command Int is generated only if there is a change in the GC_Command basic setting 1 The New_GC_Command Int is generated for each receipt of a GC 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 4 message Check_No_Prm_Reserved Reserved bits in Prm frame are not tested 0 Reserved bits are tested 1 Reserved bits are not tested Check_No_GC_Reserved Reserved bits in the GC frame are not tested XAsyn Syn Syn_Baud 0 Reserved bits are tested 1 Reserved bits are not tested Setting the bus physics 0 Asynchronous physics the work clock pulse is fixed at 48 MHz via PLL Baud rate 9 6 kBd to 12 MBd basic setting 1 Synchronous physics the work clock pulse can be set 2 4 8 or 16 MHz Baud rate fixed at 31 25 kBd Setting of synchronous baud rate 0 Only 31 25 kbaud is supported as a synchronous baud rate irrespective of the clock pulse supply basic setting 1 The synchronous baud rate is variable irrespective of the clock pulse supply see below En_Change_Cfg_Buffer Enable of the DPC31 HW Description Copyright Siemens AG 2004 All rights reserved buffer exchange User_Cfg_Buffer for MAC_GCfg_Rbuffer 0 The buffers won t be exchanged Version V2 1 Page 21 05 04 ComDeC DPC31 HW SI EMENS 1 With
27. quartz must be connected With it the PLL generates the internal 48MHz clock pulse for the asynchronous mode In the synchronous mode the PLL is switched off and an external clock pulse of 2 to 16 MHz is applied In addition power management is implemented in the clock unit that switches off internal clock pulses in certain states As outputs the internal working clock pulse divided by 2 and by 4 is available DPC31 HW Description Version V2 1 Page 9 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS L Reset BootTyp1 o DBX eo 8 8 AB DB 4 8 VO PB7 Interrupt Controller Interface SPI Bus Interface Intel Motorola I O C31 Interface Emulator Port Register Cells DPS Control Units Multiport Code RAM 0 4k RAM RAM for C31 Controller 6kByte Communication RAM 5 5 0 5k C31 Core Send Receive Unit Sequence Control Physics Unit PLL Timer Unit Interrupt Clock Unit Controller Fite bs Vdd XPLLE Clkout1X2 Test Vdd Vss Vss ae Clkout1X4 Figure 2 3 1 Block Diagram DPC31 2 4 Pin Description The DPC31 has a 100 pin PQFP package with the following signals Page 10 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Function Group Function a Il IMIM C31 I
28. subscriber function applies only to the I O data Default_SAP under DXB response frame DPC31 HW Description Version V2 1 Page 45 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS e Publisher mode is enabled with EN_DXB_Publisher 1 in the Param register Subscriber mode is only enabled in DPC31 if EN _DP_DXB 1 was communicated in the Set_Param frame or the command EN_DP_DXB is issued via the request interface e When the DPC31 is used as a Publisher the master must parameterize a Twintspr 35 Ten Configuration of the Data Exchange Broadcast The configuration for the DXB tap can occur with the Set_User_Prm Frame SAP53 or via DPV1 a Ext_User_Prm Frame SAP53 The Set_DDB_Prm Frame can be locked by the user by setting the MAC_Ext_User_Prm Buffer 00h during startup This SAP is then available as a FDL_SAP Otherwise two alternating buffers of the same length are available for this SAP One buffer is integrated in the SAP SCB as an Indication buffer MAC_Ext_User_Prm Buffer and the other is attached in the DPS buffer management as a Ext_User_Prm Buffer The Indication is always transferred to the user in the Ext_User_ Prm Buffer This service is accepted by DPS in Wait_Cfg state only and by Master Add In the Data_Exchange state this frame involves a Leave_Master DPS ignores this call under all other faulty constellations The user takes on the evaluation of the
29. the current U buffer to the user are invalid The substitute values must be output in place of the data from the U buffer Bit 3 0 The data transferred to the user in the current U buffer are valid and can be output by the user Additional particularities in conjunction with this operating mode e Inthis operating mode bit U_Buffer_Cleared in the User New_Dout Cmd register is not updated and can therefore also not be used for evaluation e f Bit 3 in the req_ssap byte of the current U buffer is set and this buffer is entered by the MAC as a reply buffer for the read output SAP SAP 57 the data length is always set to the value from the Dout_Buffer Length register in this buffer header in byte Resp_Data_Length The data sent as a response for a Read Output SAP are invalid incidental e Under certain circumstances the content of the U_Buffer_State register can be inconsistent with the content of the user s buffer For this reason the req_ssap byte from the buffer header should be used Page 40 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS e The req_ssap byte in the buffer header is only updated if an output buffer is present i e Dout_Buffer Length is gt 0 DPC31 HW ComDeC 5 2 5 1 DX Entered Interrupt If the MAC_State_Machine changes from passive Idie state to a Set_Param_Frame SAP61 and the Check_Config Frame SAP62 ei
30. the parameter assignment GIM_EN 0 Galvanic Isolation Mode refer to Param Register Chapter 3 3 in the interface of the power saving serial interface The output levels RxA and RxS are adjusted via the supply input Vu SIM1 To galvanically isolate the lines for the data and auxiliary signals different isolated components and circuits can be used Figure 7 5 7b and c The conventional type provides for an optocoupler each for the signals TxS TxE RxS and RxA Otherwise processing the send and receive signals in the interface of the power saving serial interface is as shown in Figure 7 5 7a To implement a power saving method of working with optocouplers an interface logic was conceived Figure 7 5 7c which is to be activated via the parameter assignment GIM_EN 1 This circuit generates short pulse width modulated transmission pulses only in the case of edge transitions of the data stream from which the data signal is recovered in the secondary circuit The mean power input can thus be reduced to low values The following are pointed out as special features e Combination of the control and data signals in a transmission channel TxSD RxSD thus reducing the interface width for send and receive direction from 4 to 2 optocoupler channels e Suitable for 5V and 3V engineering e Use of conventional optocoupler blocks with simple selection at the manufacturer can also be used for optocouplers with higher power requirements
31. to Vpp 5V This pull up is needed only if a 5V CMOS input is to be driven For reasons of interference immunity TTL level is recommended DPC31 HW Description Version V2 1 Page 85 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Von 3 3V Von 3 3V Vpp2 5 0V Protection Circuit DPC31 Board GND GND Figure 9 5 2 Wiring of an Output Pad Cell with 5V Tolerance Page 86 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 9 4 3 DC Specification of the Pad Cells Be ee Be Input voltage 0 level V Input voltage 1 level X V Output voltage 0 level Vor lo 0 mA 0 1 V Output voltage 1 level Von lon 0 mA Vbo 0 2 5 5 V Output voltage 1 level Vou lou 0 mA Vbo 0 2 Von V Schmitt trigger ve threshold Vp 2 1 V Schmitt Trig ve threshold VN 0 7 V Schmitt Trig hysteresis Vu 0 4 V Schmitt Trig input voltage Me 5 5 V Input leakage current li Vi Voo or GND 1 uA Output current 0 level lo Vor 0 4 V Ty 95 C 3 84 mA 4 mA cell 5 V tolerant Vbo 3V Output current 1 level lon Von 2 4 V Ty 95 C 3 84 mA 4 mA cell 5 V tolerant Vbp 3V Output current 0 level lo Vor 0 4 V Ty 95 C 7 68 mA 8 mA cell 5 V tolerant Von 3V Output current 1 level lon Von 2 4 V Ty 95 C 7 68 mA 8 mA cell 5 V tolerant Vbo 3V Output current 0 level lo Vor 0 4 V
32. to be output 5 2 7 Read_Inputs SAP56 The Read_Input message is accepted by the MAC only with request data length 0 in the mode Data_Exchange from any master For this DPS enters the corresponding validation values in Page 44 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC SAP56 of the SAP_SCB In the other modes the DPC31 responds with no service activated modes Wait_Prm Wait_Cfg or no resource request data length 0 The exchange of the Head Input buffer has been described previously Between the initial call and the repetition if there is a buffer change from U gt N gt D through User New Dm command the new input data is sent at the repetition 5 2 8 Read _Outputs SAP57 The Read_Output message is accepted by the MAC only with request data length 0 in the mode Data_Exchange from any master For this DPS enters the corresponding validation values in SAP57 of the SAP_SCB In the other modes the DPC31 responds with no service activated no resource The exchange of the Read_Output buffer has been described previously Between the initial call and the repetition if there is a buffer change from N gt U through User_New_Dout command the new output data is sent at the repetition 5 2 9 Get_Config SAP59 The Get_Config message is accepted in all modes If the ca
33. 1 HW Description Version V2 1 Page 39 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 5 2 5 Write_Read_Data Default SAP The MAC accepts the Write_Read_Data message only in the Data_Exchange mode and only from the Master Add i e the locking master otherwise a negative acknowledgement RS is generated If the received net data output data does not fit into indication buffer D the service is ignored and the response is no resource The length of the indication buffer D corresponds exactly to the data output configuration of the respective slave If the received output data is less than the length of the indication buffer there is a configuration error In this case DPS does the following it sets Diag Cfg_Fault 1 refer to diagnostic data executes the Leave_Master macro transitioning to Wait_Prm and transmits the input data from the response buffer Otherwise the received net data is written to the assigned indication buffer and the net data that is to be sent is fetched from the assigned response buffer For the output data 4 exchange buffers are available and for the input data 3 exchange buffers Two operating modes must be able to be taken into account e Operation without Clear Buffer This operating mode occurs if bit Disable_C_Buffer 1 in the parameter register In this case only three alternating buffers are operated and the Clear buffer is block
34. 1 Page 75 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Table7 5 9 Circuit of the Demodulator in principle 1 Ausgang Optokoppler Ne RX Mahal 2 Ausgang Komparator 6 Ausgang Oder RxE1 Table7 5 10 Signal Evaluation of the Demodulator The rising edge of each incoming pulse 2 triggers a monoflop at runtime t3 The following condition applies t1 lt t3 lt t2 When t3 elapses a scan is made to see if the pulse is still pending that is the input signal still corresponds to a logical 1 e If the pulse is no longer pending a short pulse is detected t1 e If the pulse is still pending a long pulse is detected t2 Depending on the detected pulse duration t1 falling edge or t2 rising edge the flip flop FF 1 is set to L or H The output of the flipflop thus corresponds to the serial data signal RxS1 4 The output signal 5 of an additional flip flop FF 2 is logically connected to the signal 4 via an OR function When two short pulses in a row occur both flip flops are reset frame end The OR function yields an L which is recognized as the end of static signal RxE1 6 At scan time t8 an uncertainty window is specified because a jitter in the amount of the pending clock pulse period always occurs in the switching system In this case the jitter is 0 5 us Time t3 is permanently set in Step A B of the DPC31 However because the time durations t1 an
35. 11 gt Buffer3 Table 5 2 4 Coding of User New Dout Cmd User Dout Butter State With the read operation User Din Butter State the user receives the current buffer assignment without the buffer being exchanged User_New_Din Cmd Read Operation a a a ee ee Are gt FEB U_Buffer o 00 not possible U_Bufferi o 01 Butter LU Butter a 10 Buffer U_Buffer o 11 Buffer3 User_Din_Buffer State Read Operation HIN Butter a 00 gt Nil U D Buffer o 00 not possible U D Buffer o 01 Buffer U D Buffer o 10 gt Buffer2 U D Buffer o 11 gt Buffer3 EIN Butter o 01 gt Buffer F N Buffer o 10 Buffer2 F N Buffer o 11 Buffer DPC31 HW Description Version V2 1 Page 41 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Table 5 2 5 Coding of User_New_Din Cmd and User_Din_Buffer State At startup the DP_SM goes to Data_Exchange only after a positive user acknowledgement of User_Cfg_OK cmd has followed a Check_Config message and additionally the first valid Din buffer was made available in N with the User_New_Din cmd DPS_User Watchdog After power up Data_Exchange mode it is possible that the DPC31 continuously replies to Write_Read_Data messages without the user fetching the received Dout buffers or making new Din buffers available If the user processor should hang the master would not notice it For that reaso
36. D Output Send Data RXD Input Receive Data The PROFIBUS interface is implemented as 9 pole SUB D connector with the following pin assignment Pin 1 free Pin 2 free DPC31 HW Description Version V2 1 Page 107 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Pin 3 B line Pin 4 Request to Send RTS Pin 5 Ground 5V M5 Pin 6 Potential 5V potential free P5 Pin 7 free Pin 8 A line Pin 9 free The line shield is to be connected to the connector housing The free pins are used optionally in the EN 50170 Vol 2 and should correspond to this description if the user uses them Attention The designations A and B for the lines at the connector correspond to the names in the RS485 standard and not to the pin name of driver ICs The line length from the driver to the connector is to be kept as short as possible If the higher baudrates of 3 to 12 MBaud are used suitable connectors are to be used These connectors compensate for line influences regarding all possible line combinations 12 2 2 Optimizations of the bus cycle For optimizations of the bus cycle the following adjustments of the max TSDR timings can be done in the GSD file Transmission 187 5 500 1500 3000 6000 12000 rate kbit s Optimized 15 15 25 50 100 200 Max TSDR Page 108 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved ComDeC
37. DX_OUT can be applied directly to Port PBs DPS has received a Write_Read_Data GC message and has made the new output data available in the N buffer However the old data wasn t fetched and is no longer available In the sync mode the frozen output data in the D buffer was overwritten because there was no GC message DPS has tapped data from a configured connection and provided the new output data in the N buffer in the appropriate DXB_Buffer_SMO 7 During the last watchdog cycle at least one connection failed or was returned The memory was accessed outside the communication memory The SSC interface generated an interrupt The Sync_Clock clock pulse beater has been triggered at Port PBs Comes after the transition to Data Exchange synchronously with the first DX_OUT interrupt in which diagnostics are not pending Version V2 1 DPC31 HW Description Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Interrupt Register IR readable only For bit assignment refer to Interrupt Request Register Interrupt Mask Register IMR writable can be changed during operation For bit assignment refer to Interrupt Request Register Bit 1 Mask is set and the interrupt is disabled Bit 0 Mask is cleared and the interrupt is enabled After reset all bits are set Interrupt Acknowledge Register IAR writable can be changed during operation For bit assignment refer to Interrupt Request Re
38. Description Version V2 1 Page 63 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Figure 7 3 1 Operation in Boot Type 2 7 3 2 80C31 Core 7 3 2 1 Data Area The processor has an internal work memory consisting of 256 bytes The data area of the processor is broken down into different blocks Figure 7 3 2 The register cells interrupt controller DPS control units etc are located from Address 000h to 004Fh From Address 0050h to 008Fh the I O ports E F G and H can be addressed From 0090h to 07FFh is an unused area The internal RAM follows starting with address 0800h broken down into the block work cells parameter cells and buffer management which consiDXB of approx 0 5 kByte and the communication area which consiDXB of 5 5 kByte Starting with 2000h the external RAM is accessed signal pin XCSDATA low Page 64 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC External RAM FFFFh Data Memory 1FFFh int CRAM 5 5 kByte S R_UnitTemp Buffer approx O9FFh Internal Stack for sequential control system Buffer Management Parameter Cells EH Variables Start internal RAM Bu En Ube used 07FFh Direction Register Port H 1 Input 0 Output ByteAddress Ho BitAddress H3 BitAddress H BitAddress Ho Port G Direction Register Port G 1 Input 0 Output ByteAddress G7 BitAddress G7 BitAd
39. LLEN Direct Clock Supply 1 CLK Quartz Connection 12 MHz gt Internal Clock 48 MHz 20 83 ns Table 9 5 2 Definition of the Elementary Period T Page 88 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 9 5 2 1 Clock Supply XPLLEN 1 Clock High Time Clock Low Time Rise Time Fall Time Max frequency Table 9 5 3 Input Clock TCLH TCLL CLK Figure 9 5 1 Clock Timing 9 5 2 2 Clock Outputs The clock outputs CLKOUT1X2 and CLKOUT1X4 are active during the RESET also For switched on PLL XPLLEN 0 In this mode the two clock outputs are derived from the output clock of the PLL The clock outputs thus have the inaccuracy of the PLL frequency stability 200 ppm phase jitter maximum of 3 ns The electrical characteristics are shown in Table 9 6 4 Duty factor CLKOUT1X2 Hi Low Duty factor CLKOUT1X4 Hi Low Response time of PLL Frequency stability of PLL Table 9 5 4 Clock Outputs For switched off PLL XPLLEN 1 In this mode both clock outputs are derived from the input clock at the XTAL1_CLK pin The clock outputs thus have the inaccuracy of the pending clock The data for the duty factor is shown in Table 9 6 4 9 5 2 3 Reset For switched on PLL XPLLEN 0 The reset does not reset the PLL After voltage is restored the reset duration should be a multiple of the build up duration for sa
40. List 66 bytes must always be available but only the enabled SAPs are entered in the SAP_SCB SAPs not enabled are entered in the SAP_List with SAPx_Ptr FFh The entries in the SAP_SCB must not exceed 256 bytes 10 DPS 26 FDL and 1 SM Time SAP The user enters all FDL_SAPs in the SAP management and sets the DPS_SAP_ Start Ptr to the next position after the FDL_SAPs With the MAC_ Start request the MAC affixes the DP SAPs following this if Bit DP_Mode 1 is set in the Param Register The entries in the SAP_SCB differ between the DP SAPs and the FDL SAPs However the first three entries for each SAP are always identical Specifically the following entries are stored req_sa When a Request frame is received the MAC makes the received Remote_Adr plausible with this specified value If this field is preassigned with FFh All access protection is not set If the field is assigned 7Fh SAP is blocked and the MAC replies with no Service activated RS Otherwise the MAC compares the received Remote_Adr with the specified req_sa If they do not match the frame is rejected and replied to with RS Attention must be paid that the highest bit has to be set to log 0 in the default SAP and to log 1 in all other SAPs For the FDL SAPs the MAC enters the access protection automatically This always occurs if this field is preassigned All and a Request Pdu is received in Idle ISM mod
41. OM or an A D converter such as AD7714 This interface is laid out only as a master interface The user must create an appropriate program for the C31 for control of this interface The C31 interface includes the ports of the standard controller Via this interface an external memory and I O expansion can be implemented Via corresponding CS signals the code and data address areas are coded out that are not used internally In addition up to 13 bits of I O can be connected via these ports The C31 32 emulator Hitex etc is also controlled via this interface Via the register cells the following are accessed internal registers the DPS DP Slave control units and the SSC module The DPS control units represent the user interface to the DPS layer that is implemented via individual buffers These control units exchange the buffers The integrated C31 is fully compatible with the standard microcontroller Also integrated is a 256 byte data RAM Via a second interrupt controller the interrupt events mentioned above can also be entered in the C31 This makes it possible to distribute interrupt events between an external and an internal application The bus physics unit includes the asynchronous Layer1 RS485 9 6kBd to 12 MBd and the synchronous Layer1 IEC 1158 2 Manchester encoded 31 25kBd which also allows the chip to be operated in an intrinsically safe environment In the clock unit an analog PLL is integrated to which an external 12MHz
42. PC31 Processor Interface supports the following micro controllers DPC31 HW MOTOROLA micro controller with the following features Synchronous rigid bus timing without evaluation of XDSACK PH 8 Bit non multiplexed bus DB PE7 o AB42 0 PG4 o PF7 o The following can be connected HC11 types K N M and F1 HC16 and HC916 types with programmable ECLK timing For all other HC11 types with a multiplexed bus the addresses AB have to be selected externally from the data D o Address decoder is switched off in the DPC31 CS signal is supplied from the outside For micro controllers with chip select logic K F1 HC16 HC916 the chip selection signals can be programmed regarding the address area priority polarity and the window width in the write and read cycle For micro controllers without chip selection logic N M and others an external chip select logic is needed This means additional HW effort and fixed assignments Condition The DPC31 output clock CLKOUT1 X2 4 has to be at least four times larger than the E Clock The DPC31 clock 48MHz has to be at least ten times larger than the desired system clock E Clock Pin CLKOUT1X4 is to be wired with this E_Clock 3MHz at 48MHz DPC31 clock MOTOROLA micro controller with the following features Asynchronous bus timing with evaluation of XDSACK PH 8 Bit non multiplexed bus DB PE7 9 AB42 0 PGa 0 PF 7 0 The following can be conne
43. Register to the Score_Register which contains the received links of the last turn If no difference is detected all of the links arrive and the Score_Actual_ Register is deleted for the next pass If a difference is detected DPS transfers the Score_Actual_ Register to the Score_Register then deletes the Score_Actual_Register and generates the DXB_Error Interrupt As a result the user receives information on failed or returned links in the new Score_Register This state is now taken as the basis for the subsequent watchdog cycle If for example a failed link comes up again a difference between the Score_Actual_Register and the Score_Register arises again at the end of the cycle and the DXB_ Error interrupt is generated again If the user preassigns the Score_Register with configured DXB connections for each disconnection of DXB mode monitoring for failed links starts When 00h is preassigned all received links are first registered one time in the Score Register following a turn and consulted as monitoring for the next turn 5 3 Additional FDL Functions 5 3 1 FDL_Monitoring Timer For monitoring a connection a 16 bit monitoring timer FDL_Timer_Count H L is available for each FDL_SAP This timer is operated with a cycle clock of 10 ms 1 ms for WD_Test 1 This enables implementation of monitoring times up to 655 sec Each timer can be individually controlled via the FDL_Timer control Table 5 3 1 gives the assig
44. S buffer structure The buffers length and buffer ptr are configured by the user in the Offline Mode in the DPS buffer management For the Dout data four buffers of the same length are available and for the DXBO 7 data separate management in DDB_SCB three buffers each of the same length are available which are implemented as alternating buffers One buffer each is assigned to the incoming data transfer D and the user U The third buffer is either in a Next N or Free F mode whereby one of the two modes is always unoccupied The MAC clears the data in D After receiving D is moved to N and a new buffer is fetched from the N or F The user fetches its output data from N In the fourth buffer C the user makes the substitute values available for the Clear mode failsafe If the DPC31 receives Clear messages or if DPS leaves the Data_Exchange mode the C buffer is transferred to the user in the state U The buffers are moved through the corresponding exchange DPS then also performs the buffer exchange for the user The Din data is controlled via three exchange buffers of the same length One buffer each is assigned to the data transfer D and the user U The third buffer is either in a Next N mode or Free F mode When sending the MAC fetches the Din data from D The user prepares new Din data in U and then moves it to N DP
45. S then changes the buffers from N to D For the diagnostic SAP and the Get_Cfg SAP SAP60 59 two buffers respectively are available that may have different lengths The D buffer is always assigned to the MAC for sending and the U buffer belongs to the user for preparing new data DPS exchanges the buffers upon user request Page 34 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC In SAP55 Set_Slave_Address SAP53 Set_Ext_Param SAP61 Set_Param and SAP62 Check_Config one indication buffer respectively is available in which the received data are cleared At the indication this buffer is exchanged for the corresponding buffer in DPS buffer management User_SSA buffer User_DDB_Prm buffer User_Prm buffer or User_Cfg buffer and then the corresponding DPS control unit is triggered 5 2 1 Set_Slave_Address SSA SAP55 Two exchange buffers of the same length are available for this SAP One buffer is integrated as indication buffer in the SAP_SCB MAC_SSA buffer and the other is included in DPS buffer management as User_SSA buffer The indication is always transferred to the user in User_SSA Buffer The user can disable the SSA service by setting the MAC_SSA_Buffer Ptr 00h at power up The DPC31 then responds to an SSA request with no service activated The new Station Address and the parameter Real_No_Add_Change are stored b
46. SIMATIC NET DPC31 Siemens PROFIBUS DP Controller with C31 Core Hardware Description Date May 19 2004 SIEMENS SIMATIC NET DPC31 Hardware Description of Step C Siemens PROFIBUS DP Controller according to IEC 61158 with Integrated C31 Core ComDeC DPC31 HW SI EMENS Liability Exclusion We have tested the contents of this document regarding agreement with the hardware and software described Nevertheless deviations can t be ruled out so that we are not guaranteeing complete agreement However the data in this document is checked periodically Required corrections are included in subsequent editions We gratefully accept suggestions for improvement Copyright Copyright Siemens AG 2004 All Rights Reserved Unless permission has been expressly granted passing on this document or copying it or using and sharing its content is not allowed Offenders will be held liable All rights reserved in the event a patent is granted or a utility model or design is registered The trade marks SIMATIC SINEC L2 are protected by law for Siemens through application registration All other product and system names are registered trade marks of their respective proprietors and are to be treated as such Subject to technical change Page 2 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Overview of Versions Herston Ne Dale rasen uaua Cd Fistversio
47. The DPC31 starts the search for the set baud rate always with the highest baud rate If during the monitoring time no SD1 SD2 or SD3 message has been received completely and faultlessly the search is continued with the next lower baud rate After detecting the correct baud rate the DPC31 switches to the Baud_Control mode and monitors the baud rate The monitoring time can be parameterized WD_Baud_Control_Val The watchdog processes in this case with a clock of 100 Hz 10 msec Each faultlessly received message to its own station address resets the watchdog If the timer expires the DPC31 reswitches to the Baud_Search mode 7 7 2 Baud rate Monitoring In Baud_Control the baud rate that was found is monitored continuously With each faultless address to the DPC31s own station address the watchdog is reset The monitoring time is the result of multiplying WD Baud Control Val to be parameterized by the user by the time base 10 ms If the monitoring time expires the WD_SM reenters Baud_Search If the user handles the DP protocol with the DPC31 DP_Mode 1 refer to Mode Register 0 the watchdog is used for the DP_Control mode after a Set_Param message with enabled response monitoring WD On 1 was received If the master monitoring WD_On 0 is switched off the watchdog timer remains in the baud rate monitoring mode The PROFIBUS DP state machine is not reset if the timer expires that is the sla
48. TxA1 Datensignal 2 TxS1 Summensignal zur LED Ansteuerung 3 TxS_IM t2 ti ti Datensignal 2 m RES a t1 E e RES BE Begleitsignal 21 en Re t2 TSM Tr Page 74 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC statisches Begleitsignal N TxA1 Datensignal 2 HITTITE tt HTT TTT iii TXS1 HITT TE I HITTITE tl BERBEBER Summensignal zur LED Ansteuerung 3 TxS_IM t2 t1 t1 Datensignal TxS1 t2 2 RES 7 A E _ RES AZ gt Begleitsignal 21 b TxA1 2 3 TxS_IM A SH In Table7 5 8 Signal Shaping in the Modulator Pulse Duration Demodulator In the galvanic isolation mode GIM_EN 1 the useful signal for the PDM is recovered from the collector signal of the optocoupler transistors by using a comparator The following digital circuit component integrated into the DPC31 evaluates the length of the output pulses of the comparator and recovers from it the data signal and the auxiliary signal The circuit diagram of the demodulator is shown in Figure 7 5 9 The signal characteristic with respect to time is shown in Figure 7 5 10 When using RxS_IM the pin RxA is to be applied to GND DPC31 HW Description Version V2
49. V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC When the buffers are exchanged by the user the internal Diag_Flag is set in Furthermore the Diag_Flag is entered in the status register If Diag_Flag is activated the MAC responds at the next Write_Read_Data message with high priority response data This signals to the associated master that new diagnostic data is present at the slave If DPS does not have any input data it responds with a high priority SD2 message with a dummy net byte 00h After this high priority reply the master fetches the new diagnostic data with a Slave_Diagnosis message The Diag_Flag is then reset and the user Diag_Fetched interrupt is generated However if the user signals Diag Stat_Diag 1 static diagnosis refer to structure of the Diagnosis_Reply buffers the Diag_Flag remains activated even after the associated master has fetched the diagnosis The user can poll the Diag_Flag in the status register DPS sets Diag_Flag 0 for Power_On caused by a reset or the startup of the watchdog timer in the DP_Control mode or Diag_Flag 1 when entering Data_Exchange The Diag_Buffer_SM is also reset when DPS is powering up That is after the user has transferred MAC_ Start in the request list or the watchdog has expired in the DP_Control mode A Diag_Buffer_Changed interrupt i
50. XWR Pulse Width Address hold time after ALE 4 ALE Pulse Width XRD XWR cycle time ALE J to XWR 4 XWR to ALE T Table 9 5 7 Timing Values in the Synchronous Intel Mode In the synchronous Intel mode the DPC31 stores the least significant address bits with the falling edge of ALE At the same time it expects the most significant address bits at the address bus from them it generates itself a chip select signal The request for an access to the DPC31 is generated from the falling edge of the read signal or the rising edge of the write signal XWR log 1 Figure 9 5 4 Synchronous Intel Mode Processor Read Timing DPC31 HW Description Version V2 1 Page 91 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS XRD log 1 Figure 9 5 5 Synchronous Intel Mode Processor Write Timing 9 5 2 5 2 Asynchronous Intel Mode X86 Mode In 80X86 operation the DPC31 in principle behaves like a memory with Ready logic the access timing depends on the type of access The request for an access to the DPC31 is generated from the falling edge of the Read signal or the rising edge of the Write signal A ees ee m Address setup time to XRD J or XWR L XRD J to Data valid access to RAM XRD J to Data valid access to the registers Address AB 2 0 hold time after XRD or XWR T XCS J Setup time to XRD J or XWR 4 XRD Pulse Width Data hold time after XRD T Read Write inactive Time XCS hold time af
51. _Indication buffer these bits have no significance The alternating buffer is always available here i e in the case of an Indication the Indication buffer in the SAP_SCB is exchanged for another and the corresponding DPS_SM is triggered thus generated a DPS interrupt In the case of FDL an entry is generated in the Indication Queue of Request_Pdu Indication type and the IndQ_Entry Interrupt is also generated The user must then fetch the entry from the Indication Queue This enables him to receive the SAP_No and Indication_ Buffer Address After readout he must set bit Event_Indication 0 If the user provides a Response Buffer for FDL he must also set bit Response 1 in Buffer_State 1 The data are sent at the next Request frame to this SAP Request Pdu or Poll Pdu After the Response buffer has been sent an entry is made in the Indication _ Queue of type Poll_End Indication timing only after any new request frame has been received In so doing the bit No_Ind_Reset controls whether the buffer is available afterwards in the SAP as an Indication buffer No_Ind_Reset 0 gt Buffer_State 0 Response 0 or continues to be available to the user for entering a new response No_Ind_Reset 1 gt Buffer_State 1 Response 0 In the case of a DP_SAP the Response buffer is available in SAP_SCB until the user causes it to be swapped The Butter In Use bit is a MAC internal control bit which in the case of an Ind
52. _Puf_Ptr 0 gt nicht vorhanden Puffer_Control7 o Service _Supported7 o Puffer_ Event_ Res Puffer No Ind Res State Indication ponse In_Use Reset 2 0 lt lt Puffer buffer gesperrt blocked gt gt EEE je ale Se ees ee ee Figure 5 1 1 Structure of SAP List Buffer Structure Page 26 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Service Access Values Service Access _Values o All SRD Low High or DDB Request SDN Low SRD Low SDN High SRD High SDN Low High SRD Low High not allowed not allowed SDA Low not allowed SDA High not allowed SDA Low High not allowed Table 5 1 1 Coding of Access_ Value In the Enable field the XDP FDL bit specifies whether a DP_SAP XDP FDL 0 or an FDL_SAP XDP FDL 1 is involved Ind_Resp_Buffer Ptr1 2 3 In the case of FDL SAPs up to 3 resources can be hooked in The Ind_Resp_Buffer Ptr points to the swapped out indication or response buffer Each buffer operates in 1 buffer mode that is the buffer is available to the SAP as an Indication buffer or as a Response buffer When buffer lengths are different the smallest buffer must be assigned the first buffer and the largest buffer the last The MAC operates according to the Best Fit method i e it always attempts to accommodate the received data in the first possible Indication buffer If all of the Indication buffer
53. an value weighted with the polarity information POL 1 or POL 0 that was transferred by the decoder state machine as receive signal RxD i only the zero crossings in bit center can be utilized for clock recovery 7 According to IEC 1158 2 Chapter 9 6 at least four bits are available to the preamble for synchronization Multiple synchronization during this phase does not provide advantages A decrease in the error frequency would be attainable through notification via several bits three maximum The estimated improvement however does not justify the probably much greater effort In the example shown it is assumed that the spike that possibly occurs at the start of the preamble is to be counted with two transitions worst case The signal QSync indicates the duration of the synchronization process Through this rigid phase control loop the required detection according to IEC 1158 2 Chapter 9 7 of half bit slip errors is ensured DPC31 HW Description Version V2 1 Page 71 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 7 5 2 3 Power Saving Serial Interface Figure 7 5 8 shows three different interfaces of the SIM1 at the DPC31 If no galvanic isolation of the bus interface SIM1 is required by the application specific electronics the send signals TxS TxE and receive signals RxS RxA are passed on without processing in the DPC31 to the synchronous bus physics unit Figure 7 5 8a with
54. and approval for intrinsically safe circuits e The power saving interface can be used only for a transmission rate of 31 25kBd refer to Param Register Chapter 3 3 Page 72 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC IEC MAU RTSIADY Syn Physik RTSIADD Syn IEC MAU Physik c Stromsparende Trennung mit Optokopplern Table7 5 7 Interface to communication controller DPC31 The interface logic of the power saving serial interface includes a pulse modulator and a pulse demodulator as in the SIM1 The comparator for regeneration of the analog receive signal behind the optocoupler is not integrated into the DPC31 but must be set up externally Pulse Duration Modulator In the galvanic isolation mode GIM_EN 1 the PDM Figure 7 5 8 converts the serial signal that is to be transmitted into a duration modulated pulse sequence the rising edge of the send signal TxS1 is assigned a long pulse and the falling edge is assigned a short pulse Likewise with the edges of the static auxiliary signal TxE1 or RTS ADD a long and short pulse is generated which are added to the pulse sequence of the data signal The summation signal thus generated TxS_IM is used for sampling the LED of an optocoupler DPC31 HW Description Version V2 1 Page 73 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS statisches Begleitsignal D
55. arameters Page 18 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS DPC31 HW Meaning of the Register Cells Status Register W D State 0 DPS State 9 Baudrate o 4 ComDeC MAC State The status register displays the current MAC status the DPS status and the watchdog timer status In addition the baud rate that was found and the release number of the DPC31 is also entered MAC State Diag_Flag DPS State o WD State o Baudrate o DPC31 Release Param Register The state ofthe MAC 0 The MAC is in the Offline state 1 The MAC is in Passive Idle State Diagnostic Buffer 0 The diagnostic buffer was fetched by Diag Stat_Diag 0 1 The diagnostic buffer was not fetched by the master The state of the DPS State Machine 00 State Wait_Prm 01 State Wait_Cfg 10 State Data_Exchange The state of the Watchdog SM 00 State Baud_Search 01 State Baud_Control 10 State DP Control The baud rate found by the DPC31 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 12 MBd asyn 6 MBd asyn 3 MBd asyn 1 5 MBd asyn 31 25 kBd syn 500 kBd asyn 187 5 kBd asyn 93 75 kBd asyn 45 45 kBd asyn 19 2 kBd asyn 9 6 kBd asyn the master if Release number of the DPC31 The release number consiDXB of two groups DPC31 Release o
56. are rejected Otherwise DPS evaluates the acknowledgements If during operation the New_Prm_Data New_Ext_User_Prm_Data und New_Cfg_ Data interrupts are pending simultaneously for the user he must adhere to the following acknowledgement order Set_Param Set_Ext_User_Param and then Check_Config A reset is also performed during startup of DPS thus once the user has transferred MAC Start to the request list or the watchdog has expired in DP Control state b DPV1 Configuration The Set_Ext_User_Prm frame must be locked by the user by setting the MAC_Ext_User_Prm buffer 00h during startup The user communicates the links taps to DPS in the Ext_User_Prm Page 46 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC buffer In addition the MAC must still be enabled for the internode communication This occurs via the request DXB _Enabled Disabled in the Instruction _Queue This same request can be used at any time to end internode communication In addition internode communication mode is tied to DPS This mode is permitted only in Data_Exchange state If DPS leaves Data_Exchange state internode communication will be disabled simultaneously Link Buffer DXB Butter The link buffer is the Ext_User_Prm buffer that was received and checked by the user One to eight entries can be made in this buffer The buffer end is defined based
57. ata byte is always in the receive buffer To receive user data dummy data bytes have to be sent so that the SSC module generates a clock pulse Register Assignment of the SSC Module The user external uP or C31 addresses the SSC module in the address range from 0020h to 0025h It can be polled or operated with interrupt output The interrupt runs to the two interrupt controllers refer to Chapter 7 1 4 Control1 Register Bit Position 7 6 5 4 3 2 1 0 BREN est PODD PPOS CPOL CPHA Default 0 0 0 0 0 0 1 1 rw r rw rw rw rw rw rw CPHA Clock Phase Control Bit 0 Acceptance of the receive data at the leading clock edge sending at the back clock edge 1 Shifting the send data at the leading clock edge receiving at the back clock edge CPOL Clock Polarity Control Bit 0 Clock idle state is low leading clock edge is a low to high edge EN Clock idle state is high leading clock edge is high to low edge HCB Heading Control Bit 0 Send receive LSB first 1 Send receive MSB first PEN Parity Control Bit 0 Generating checking parity disabled 1 Generating checking parity enabled PPOS Parity Position Control Bit 0 Send receive parity bit last 1 Send receive parity bit first PODD Parity Selection Bit 0 Even parity bit parity bit generates in the data byte an even number of Tel 1 Uneven parity bit parity bit generates in the data byte an uneven number of 1 s Page 60 Version V2 1 DPC31 HW Description
58. ata setup to XWR Data hold after XWR Address float after XRD Address valid to XCSDATA XCSDATA pulse width C for Port A 120pF C for XPSEN 10pF C for all others 80pF Table 9 5 12 Timing Values for Accesses to the Data Memory twHLH ALE Re Z XPSEN tspLsoH XCSDATA tLowL Gm Io pu XRD trHpz ke ioun PA Instr A0 A7 a C Daan Gm PC A8 A15 Figure 9 5 13 Data Read Cycle Page 98 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC tWHLH ALE Br XPSEN tspLsoH XCSDATA tLowL a twLwH XWR tavwL tavwx twHax tLLax2 taviL tavwH PA OO A0 A7 Data Out a _ PC A8 A15 Sp Figure 9 5 14 Data Write Cycle 9 5 2 7 Emulator Interface LLC __Peremetey E ALE pulse width Address setup to ALE Address hold after ALE ALE to XPSEN XPSEN pulse width ALE to valid instr out Output instruction hold after XPSEN Output instruction float after XPSEN Address float to XPSEN XPSEN to XCSCODE XPSENT to XCSCODET C for Port A 120pF C for XPSEN 10pF C for all others 80pF Table 9 5 13 Timing Values for Emulator Accesses to Code Memory Gi After this time the output driver of the DPC31 is switched off The signal level at the bust then depends on the bus load the size of the pull up resistors DPC31 HW Description Version V2 1 Page 99 Copyright Siemens AG 2004 All right
59. ation 49 5 3 2 1 Support of MSACS1 SAPs 50 Page 4 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 6 USER FUNCTIONS ON THE C31 CONTROLLER 50 7 DESCRIPTION OF THE HARDWARE BLOCKS 50 7 1 Universal Processor Interface 50 7 1 1 Bus Interface Unit BIU 51 7 1 2 1O Interface 55 7 1 3 Interface Signals 56 7 1 4 Interrupt Controller of the uP Interface in the DPC31 56 7 2 Synchronous Serial Interface SSC Interface 59 7 3 80C31 Core and Interface 62 7 3 1 Reset Phase of the C31 63 7 3 1 1 Boot Type Setting 63 7 3 1 2 Boot Type 2 63 73 2 80C31 Core 64 7 3 2 1 Data Area 64 7 3 2 2 Code Area 66 7 3 3 Code RAM 66 7 3 4 Expansion Interface to the 80C31 Core 67 7 3 5 Interface Signals 67 7 4 C31 Interrupt Controller in the DPC31 68 7 5 Serial PROFIBUS Interface 68 7 5 1 Asynchronous Physics Unit NRZ 68 7 5 1 1 Transmitter 68 7 5 1 2 Receiver 68 7 5 1 3 Interface Signals 69 7 5 2 Synchronous Physics Unit Manchester 69 7 5 2 1 Transmitter 69 7 5 2 2 Receiver 71 1 5 2 3 Power Saving Serial Interface 72 7 5 2 4 Interface Signals 78 7 6 DPS Watchdog Timer 78 7 7 Watchdog Timer 78 7 7 1 Automatic Baud Rate Detection 78 7 7 2 Baud rate Monitoring 78 7 1 3 Response Monitoring 79 7 8 Clock Supply 79 7 8 1 PLL 79 8 TEST SUPPORT 81 8 1 Emulator Connection for the C31 81 9 ELECTRICAL SPECIFICATIONS 83 9 1 Maximum Limits 83 9 2 Permitted Operating Values 83 9 3 Guaranteed Operat
60. ay Response FDL FMA1 2 Data high 00001010b amp Send Data okay Remote_Adr req_sa The MAC enters the received Remote_Address in the Indication buffer unoccupied in the Response buffer Remote_SAP req_ssap The MAC enters the received Remote_SAP here in the Indication buffer unoccupied in Response buffer Special handling for default SAP In the case of the default SAP this byte has a different meaning Data Field The MAC stores the received net data here in the Indication buffer The user provides the Response net data in the Response buffer The maximum data length is 244 characters 5 1 2 Request Interface for DPS and FDL Instruction Queue User requeDXB to the DPS and MAC modules are transferred via a request interface This request list is a polling list onto which the user transfers communication requeDXB Figure 5 1 4 shows the organization of the Instruction Queue With each entry 5 bytes respectively the user must also transfer the command to the sequential control system This is done with a write operation with any data value to the register cell User_InstQ_Write Cmd The organization of the Instruction_ Queue includes the following parameters InstQ_Base Ptr The Instruction_Queue segment pointer InstQ_Length Describes the length of the Instruction_Queue and is a multiple of the length of an entry n 5 InstQRd Ptr An Offset_Pointer which points to the next entry that is to be read and is managed by
61. ck Reg s 1s 0007h Int Ack Reg s 2s 0008h__ Int Mask Regr o 0009h Int Mask Reg s s 000Ah__ Int Mask Reges 16 000Bn Int Mask Reg s 24 000Ch__ Int EOI Rego o00Dh reserved 000Fh 0010h C31_Ctri Regso RefertoChapter6 S O 0011h Mode Reg1 Setzo RefertoChapter6 0012h __ Mode Reg1 Resetz o Refer to per 0013h__ User_InstQ_Write Cmdr o Transfers a new request to the sequential control system _ 0014h ee reserved O01Fh 0020n SSC_Transmit Buf o Receive buffer of the SSC interface 0024h SSC_Int_Enable Reg3 o Interrupt_Enable register of the SSC interface 0025h SSC_Baudrate Reg7 o Baud rate register of the SSC interface 0026h reserved O7FFh Table 3 2 1 Assignment of the Internal Register Cells for WRITE 3 3 Organizational Parameters RAM The organizational parameters are stored by the user in the RAM under the addresses specified in the table below These parameters primarily describe the parameter cells and the buffer pointers of the communication profile buffer management DPC31 HW Description Version V2 1 Page 15 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 0800h Internal working area reserved 0827h 0828h Master_Add7 0 Address of parameter assignment mask 0829h Internal working area reserved 0833h 0834h U_Buffer_State Status of user buffers if Disable C Buffer is in parameter regis
62. cted HC16 and HC916 types Address decoder in the DPC31 is switched off CS signal is applied from the outside Chip select signals are present in all micro controllers and can be programmed INTEL CPU Basis 80C31 32 micro controllers of various manufacturers Synchronous rigid bus timing without XRDY PH evaluation 8 Bit multiplexed bus ADB PE7 0 The following can be connected Micro controller families such as INTEL SIEMENS PHILIPS Address decoder is switched on in the DPC31 CS signal is generated internally The lower address bits AB are stored with the ALE signal in an internal address latch In the DPC31 the internal CS decoder is activated that generates its own signal from the addresses AB o The integrated address decoder is permanently wired so that the DPC31 Always has to be addressed under the fixed addresses AB7 o 000xxxxxb Whereby the DPC31 selects the corresponding address window from the Signals AB z o In this mode the CS pin PGs has to be on VDD high potential Wiring refer to Figure 7 1 1 Figure 7 1 2 Apply ADB7 p to DPC31 Pin PE7 5 AB45 8 to DPC31 Pin PE a and the DPC31 Pin PG to VSS INTEL and SIEMENS 16 8 Bit micro controller families Asynchronous bus timing with evaluation of XRDY PH2 8 Bit non multiplexed bus DB7 0 PE7 o AB12 0 PGa 0 PE a The following can be connected Micro controller families for example SIEMENS 80C16x and INTEL X86 Address deco
63. d t2 can change due to distortions caused by the optical coupler interface module an assignable time window was implemented in Step C This corresponds exactly to the values that were implemented in SPC4 2 see Table 7 5 1 The various scan times t3 are set by the bits within the expanded parameter register designated for scan mode see Section Organizational Parameters Expanded Parameter Register The scan mode set by default after reset deviates from the permanently set scan mode in Step A B Page 76 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Scan Mode Uncertainty Window 1 0 min max 01 after a 00 Table 7 5 11 Uncertainty Window Alternative Suggestion regarding Comparator Circuitry The wiring of the comparator output described under Figure 7 5 has the disadvantage that the comparator has to be supplied with the external voltage 5V via the input Vir and a level adaptation is necessary at the output In addition a control area up to the positive supply voltage has to be ensured The circuit variant below Figure 7 5 11 avoids these disadvantages The two voltage dividers R2 R3 and R4 R5 move the work area of the comparator to the center of the internal supply voltage Vcc an offset results from the difference of the values R2 and R4 in the idle state R6 causes a decrease in amplitude C2 a delay of the reference voltage
64. d yt E Group_Select Table 5 2 6 Data Format of the Global Control Message The parameter Group Select establishes which group s is are to be addressed The Global Control message becomes effective if the bit by bit AND operation of the Group_Ident transferred in the Set_Parameter message with the Group_Select parameter supplies a value unequal to 0 on at least one bit position If Group_Select is equal to 0 all slaves are addressed Byte Control_Command Bit 7 6 0 Reserved The designation Reserved indicates that these bits are reserved for future function expansions If such a bit is set DPS sets Diag Not_Supported 1 and the Leave_Master macro is executed However if the user parameterizes Check_No_GC_Reserved 1 in the param register the Reserved bits are not checked Bit 5 Sync The output data transferred with a Write_Read_Data message is changed from D to N DX_OUT interrupt is generated The subsequently transferred output data is kept in D until the next Sync command is made The same reaction occurs for Sync_Supported 0 as does for a set Reserved bit Bit 4 Unsync The command Unsync cancels the Sync command In addition as in the case of Sync the previously transferred output data is changed from D to N Bit 3 Freeze The input data is fetched from N to D and frozen New input data will be fetched only if the master sen
65. de Table7 3 2 Interface Signals of the C31 DPC31 HW Description Version V2 1 Page 67 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 7 4 C31 Interrupt Controller in the DPC31 Via this interrupt controller the C31 can be provided with the same interrupt events as the external uP refer to Chapter 7 1 4 It is structured exactly as the other interrupt controller Each event is stored in the IRR Via the IMR individual events can be suppressed If for instance the DPS indications are to be evaluated by the external processor the corresponding masks have to be set here and be enabled in the interrupt controller for the external processor The entry in the IRR is independent of the interrupt mask The event signals that are not masked out in the IMR generate the C31 interrupt via a summation network For debugging the user can set any event in the IRR activate only the bits that are to be reset Before leaving the interrupt routine the C31 has to set the End of Interrupt signal EOI 1 in the EOI register With this edge change the interrupt line is switched inactive If an event should still be stored the interrupt output becomes active again only after an interrupt inactive time of at least 1 us but no more than 2 us refer to Section 9 6 2 2 The interrupt registers IRR IR IMR IAR and the EOI register are described in Chapter 7 1 4 The PD XINTO pin is always an outpu
66. deleted An entry was made in the indication queue The Indication_Queue is full The pending indication could not be transferred DPS has entered the Data_Exchange mode or has exited it DPS has received a Global_ Control message with a modified GC_Command byte New_GC_Int_Mode 0 and has stored this byte in the RAM cell GC_Command If New_GC_Int_Mode 1 this interrupt is set for every received Global_ Control message DPS has received a Set_Slave_Address message and has made the data available in the User_SSA buffer DPS has received a Set_Param message and has made the data available in the User_Prm buffer DPS has received a Set_DDB_Param Frame and provided the data in the User DDB_Prm Buffer DPS has received a Check_Cfg message and has made the data available in the User_Cfg buffer Upon request by User_New_Get_Cfg_Buf DPS has exchanged the Get_Config buffers and has made the old buffer available again to the user Upon request by User_New_Diag_Buf DPS has exchanged the diagnostic buffers and has made the old buffer available again to the user DPS has received a Write_Read_Data GC message and made the new output data available in the N buffer In the case of Power On Clear or Leave Master the DPS_SM makes a cleared C buffer available and generates this interrupt also By parameterizing Enable DX_Out_Port 1 in the C31_ Control register the interrupt
67. der in DPC31 is switched off CS signal is applied from the outside External address decoding is always required External chip selection logic if not available in micro controller Table 7 1 1The Different Configurations of the Processor Interface Page 52 05 04 Version V2 1 DPC31 HW Description Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC RTS_TXE er TXD_TXS Latch E RXD_RXS XCTS_RXA Port 0 SER Bus Interface Bus Type 2 0 RESET 001 Figure 7 1 1 Low Cost System C31 Mode 12 24 MHz 80C32 C501 A se cs er PG 6 PG 4 0 BusType 2 0 RESET SER Bus Interface Figure 7 1 2 C31 System with External Memory C31 Mode DPC31 HW Description Version V2 1 Page 53 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 12 MHz 12 24 MHz Reset Scaler 2 4 RTS_TXE TXD_TXS a RXD_RXS 80286 Bus Contr CTS_RXA 82288 PG 4 0 PF 7 0 BusType PG 6 2 0 Adress SER Decoder Bus 000 Interface ge met CSEPROM Figure 7 1 3 80286 System as an Example for Mode X86 XReset RTS_TXE TXD_TXS RXD_RXS M68HC11 XCTS_RXA Bus Type 2 0 RESET SER Bus 011 Interface a Figure 7 1 4 M68HC11 System as an Example for Synchronous Motorola Mode Page 54 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights r
68. dress Go Port F Direction Register Port F 1 Input 0 Output ByteAddress F o BitAddress F7 BitAddress F Port E Direction Register Port E 1 Input 0 Output ByteAddress Ez 9 BitAddress E BitAddress Eg BitAddress E5 BitAddress E BitAddress E3 BitAddress E gt BitAddress E BitAddress Eo DPS Control Units SSC Interface Parameter Register Delay Timer Interrupt Controller Figure 7 3 2 X Data Area of the Internal Processor DPC31 HW Description Version V2 1 Page 65 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 7 3 2 2 Code Area The code area normally includes all 64 Kbytes of the address space The XCS_CODE and XPSEN signals are active when the code memory is accessed If a code RAM is programmed by means of the C31 control register the address area 0000H 1000H is reserved for the code RAM and the external code memory is no longer addressed in address area 0000H 1000H 7 3 3 Code RAM During normal operation no code RAM all accesses go in the code area on the external program memory XCSCODE low However the C31 Control Register can be used to show a portion of the internal RAM in the code area as so called Code RAM The C31 then no longer obtains the program code from the external code memory but rather from the internal code RAM shown on the same address FFFFH External Data Memory 56 Kbytes Banko 2 Kbytes 0800H Bank3 2 Kbytes No m
69. ds the next Freeze command The same reaction occurs for Freeze_Supported 0 as does for a set Reserved bit Bit 2 Unfreeze With Unfreeze freezing the input data is cancelled In addition as in the case of Freeze new input data that was made available is fetched from N to D Bit 1 Clear_Data In operation with Clear buffer the Dout buffer is not deleted and it is not changed rather the mode N_Cl 1 is set in the Dout_Buffer_ SM and the user interrupt DX_OUT is generated If the user then fetches his new Dout data the C and U buffers are exchanged and the user gets the message U_Buffer_Cleared In operation without Clear buffer this command causes a completely normal buffer exchange and interrupt DX OUT is generated If the user fetches his new Dout data from it he must use the req ssap byte in the buffer header or the U_Buffer_State register to determine whether the data are to be output from the buffer or if the substitute values are to be output instead The DDB DXBout data are not subject to Clear control The Clear has a higher priority than Sync With sync data buffers are made available synchronously However this does not provide for synchronous mapping directly to the I O as is the case with the LSPM2 Although the application is interrupted via the DX_OUT interrupt the transfer time from the buffer that was made available to the I O is subject to
70. e The access protection can then only be removed via the request interface using SAP_Act Deact Service_Supported This field is divided into two The Access value is in the lower 4 bits Ser_Supported s o If OH All is preassigned plausibility step is omitted Otherwise the MAC makes the function code from the FC field EC al of the Request frame plausible with the specified Gen Gupported o If no hits occur the MAC replies with RS DPC31 HW Description Version V2 1 Page 25 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC SAP_List_Base Ptr an GAP List Def_SAP DP DPC31 HW SAP_SCB SAP_SCB_Base Ptr req_sa 7Fh gesperrt FFh all Service_Supported Ind_Resp_Puffer_Ptr1 Ind_Resp_Puffer_Ptr2 Ind_Resp_Puffer_Ptr3 FDL_Timer Control FDL_Timer_Count Low FDL_Timer_Count High req_sa 7Fh gesperrt FFh all Control Service_Supported Ind_Resp_Puffer_Ptr1 Ind_Resp_Puffer_Ptr2 Ind_Resp_Puffer_Ptr3 req_sa 7Fh gesperrt FFh all Service_Supported DPS_SAP_ Start Ptr SIEMENS Puffer Puffer_Base Ptr Puffer_Control Length_Data_Puffer Req Resp_Data_Length Req Resp_FC Remote_Adr req_sa res f r Remote SAP req _ssap Data 0 Data 1 Ind_Puffer_Ptr 0 gt nicht vorhanden Resp_Puf_Ptr 0 gt nicht vorhanden Data 243 251d SAP62 req_sa 7Fh gesperrt FFh all Service_Supported Ind_Puffer_Ptr 0 gt nicht vorhanden Resp
71. e instruction queue InstQ_Lengthz o length of the instruction queue in bytes multiple of the length of an entry gt n 5 nstQ_Read Pirz o nstQ_Write Ptrz o 084Fh 0850h 0851h 0852h 0853h 0854h 0855h 0856h 0857h 0858h 0859h Page 16 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS DPC31 HW ComDeC segment pointer to the indication queue length of the indication queue in bytes multiple of the length of an entry 085Bh IndQ_Length7 o gt n 3 Dout Butter Length o Length of the 4 Dout buffers 0866h Din_Buffer3 Pir7 o Segment Pointer to Din Buffer3 0867h _ User_SSA Buffer Ptrz o 086Bh User _DDB_Prm_Buffer Segment Pointer to User DDB Prm Buffer Dir o 086Ch MAC_DDB_Prm_Buffer Segment Pointer to Mac DDB Prm Buffer Dir o 086Dh User_Cfg_Buffer Pir7 o Segment Pointer to User Cfg Buffer 086Eh MAC Co Butter Bir o Segment Pointer to Mac Cfg Buffer Ptrz o Ptrz o Ptrz o Ptrz o 087Bh DXB2_Buffer2 Ptr7 o Segment Pointer to DXB2 Buffer2 DPC31 HW Description Version V2 1 Page 17 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS DXB7 Butter Dir o Segment Pointer to DXB7 Buffer1 088Ah DXB7_Buffer2 Ptr7 o Segment Pointer to DXB7 Buffer2 088Bh DXB7_Buffer3 Ptr7 o Segment Pointer to DXB7 Buffer3 reserved Preset with 0x00 Ee en Buffer Area 1FFFh Table 3 3 2 Assignment of the Organizational P
72. e output is initially active 0 Clkout1X2 is active default 1 Clkout1X2 is inactive Dis_Clkout1X4 The clock output Clkout1X4 is switched off of the internal clock asyn 12MHz syn 0 5 to 4 MHz After being switched on and in the reset phase the output is initially active 0 Clkout1X4 is active default 1 Clkout1X4 is inactive Dis_C31 The internal C31 is switched off clock switched off 0 C31 is active default 1 C31 is inactive absolute powerdown mode Int_Polarity Polarity of the interrupt output 0 The interrupt output is low active basic setting 1 The interrupt output is high active DPC31 HW Description Version V2 1 Page 23 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS C31_Control Register ext uP and C31 read write access In the C31_Control register the settings specific to the C31 are made The boot type bits are not to be parameterized by the user the assignment of the chip pins BOOTTYP_0 _1 determines the boot type Enable Enable GC OC Reserved 0 Boot Type DX_Out_Port ock Bit Position Default Value Boot type These two bits can be used to scan the status at the BOOTTYPO and BOOTTYP1 pins These two pins and the two bits in the register have no specified function any longer Nevertheless the pins are to be connected as follows Bit 0 0 Bit 1 1 Enable GC_Clock The clock pulse striker GC_Clock is fed to Port PB 0 Port PB i
73. e realized The value must be at least 2 SAP_List and the SAP_SCB for all FDL_SAPs incl SM_Time must be configured by the user int C31 or ext uP during startup Changes in the SAP_List and SAP_SCB may only be made in Offline status Dynamic reconfiguring of the SAP list is not permitted During operation the DP_SAPs are established and controlled by the DPS module access protection FDL_SAPs can be opened or locked dynamically The request SAP Act Deact is used for this purpose DPC31 HW Description Version V2 1 Page 27 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 5 1 1 Configuration of Buffer The figure below presents the configuration of the Indication and Response buffer for the FDL and DPS SAPs Both types of buffer appear the same but do not occupy all of the header bytes in the Response buffer Indication Buffer1 2 Header Field Buffer_Control Response Buffer Length_Data_Buffer Request Response_Data_Length Request Response_FC Remote_Adr req_sa Remote_SAP req_ssap Data Field Data 0 Data 243 Figure 5 1 2 Configuration of Indication Response Buffer The individual entries are explained in more detail below Header Field Butter Control The Indication buffers are controlled using the Buffer_State bit In the case of an Indication the MAC sets Buffer_State 1 thus assigning the buffer to the user In addition Event_Indication 1 is set For a DPS
74. e used here the interrupt of the sequential control system is located that is always taken permanently to the outside In addition the following signals are generated XCSDATA chip select external data memory RAM and XCSCODE chip select external program memory ROM XCSDATA low if the access is made to the external data area starting with address 2000h XSCODE low if the external code area is accessed if code RAM is not used starting at address 0000h to the end otherwise starting at address 1000h These signals are always to be connected so that there will not be driver conflicts when connecting an In Circuit Emulator ICE This makes connecting a standard In Circuit Emulator for an 8052 controller 24 MHz possible For this the pin has to be wired DBX high 7 3 5 Interface Signals Function Alternative Fct DebugMode ICE Comment DBX 1 Signal Type Name VO AB oi Multiplexed address data bus DB7 0 VO P1 0 VO P1 1 PBo 7 VO P1 2 P1 7 PCr o IO Abus Address bus more significant byte PDo UO P3 0 PD VO P3 1 PD VO XINTO Interrupt of the seq ctrl syst PD3 UO P3 3 Ext interrupt PD4 O P3 4 PDs O P3 5 De VO WP PD7 VO XRD XRD ALE VO ALE ALE Address Latch Enable XPSEN VO XPSEN XPSEN Output Enable for Code Memory XCSDATA O XCSDATA XCSDATA Chip Select for Data Memory XCSCODE O XCSCODE XCSCODE Chip Select for Code Memory DBX DBX DBX In Circuit Emulator debug mo
75. ead Cycle DPC31 HW Description Version V2 1 Page 101 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS d twHLH ALE ea XPSEN tavsoL XCSDATA tLowe oo twLwH XWR twHax TT PA OO A0 A7 Data In PC A8 A15 Figure 9 5 17 Emulator Data Write Cycle PA data bus of DPC31 is only active if e Access is to the internal register or the area of the multiport RAM e inthis case XCSDATA konst 1 9 5 2 SSC Interface SPI EL Tr TE Operating Frequency Cycle Time Clock High Time Clock Low Time Data Setup Time Inputs Data Hold Time Inputs Data Valid Time after Enable Edge Data Hold Time Outputs after Enable Edge Table 9 5 15 Timing Values of the SSC Interface Page 102 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC SE tv je SSCLK 0 1 j Ge e h SSCLK 0 0 7 SSCLK 1 1 N SSCLK 1 0 EC J SSDO M SSDI EEE GE GE emm Figure 9 5 18 SSC Interface Timing Diagram 10 Mechanical Specification 10 1 PQFP 100 Casing 100 pin plastic QFP 14x 20 pin pitch 0 65mm NEC CODE S100GF 65 JBT INDICATOR DPC31 HW Description Version V2 1 Page 103 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS SEE DETAIL A SEATING PLANE J RADIUS DETAIL A Figure 10 1 2 Detail A on Housing
76. ed from use The clear buffer is no longer automatically injected A check by adding substitute values at the outputs is now done with the user software e Operation with Clear Buffer This operating mode occurs if bit Disable_C_Buffer 0 in the parameter register In this case four alternating buffers are operated The Clear buffer is now automatically injected and discharged in the buffer circulation A check by adding the C buffer and thus the substitute values occurs automatically Operation with Clear buffer is always preferred over operation without Clear buffer If operation without Clear buffer is employed the Clear buffer is not used Rather the current D is transferred to the N buffer with DPS Dout Change and an DX_Out_Interrupt is initiated However in comparison with a normal DON buffer changeover the data in the buffer are now invalid In place of the invalid data the substitute values must now be output by the user In this operating mode the user must determine for each User_New_Dout Cmd whether the data from the buffer or the substitute values are to be output Two registers are available to the user for evaluation e The U_Buffer_State register on address 834h e The req_ssap byte in the buffer header of the current U buffer applies only to the buffer of the default SAP In these two registers only Bit 3 has a function all other bits are log 0 Bit 3 1 The data transferred in
77. egister Bit Position 7 6 5 4 3 2 1 0 Default 0 0 0 0 w w w w DPC31 HW Description Version V2 1 Page 61 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS ENTBEM EnableTransmit Buffer Empty Interrupt 0 Transmit Buffer Empty Interrupt is disabled EN Transmit Buffer Empty Interrupt is enabled ENRBFU Enable Receive Buffer Full Interrupt 0 Receive Buffer Full Interrupt is disabled EN Receive Buffer Full Interrupt is enabled ENPERR Enable Parity Error Interrupt 0 Parity Error Interrupt is disabled EN Parity Error Interrupt is enabled ENRECERR Enable Receive Error Interrupt 0 Receive Error Interrupt is disabled EN Receive Error Interrupt is enabled Baud rate Register An 8 bit division factor G is loaded in the baud register This value specifies the baud rate according to the following formula fsys internal system clock At 48 MHz synchronous transmission of 12 MBaud maximum is possible BR fys 4 G 1 7 3 80C31 Core and Interface The internal C31 core is SW compatible with Industrial Standard 8031 including command execution times In addition it has Timer2 from the 80032 and the internal work memory consisting of 256 bytes Below this internal processor is called C31 All functions of the controller can be used by the user except port PD2 where the interrupt of the sequential control system is located The C31 runs with half of the input frequency for a
78. emory i y Bank2 1 Kbytes Bank3 2K Bank 2 Kbytes Bank2 1 Kbytes External Code External Code External Code Memory Memory Memory 60 Kbytes 60 Kbytes 60 Kbytes 2000H Bank 2 Kbytes Bank2 1 Kbyte Bank1 1 Kbyte 1000H Bank 1 KI y 2 Kbytes of 3 Kbytes of 4 Kbytes of Code RAM Code RAM Code RAM Data Memory Code Memory Table7 3 1 Allocation Between KRAM and Code RAM When Code RAM is used the following must be observed e Code RAM is composed of the individual blocks of the multiport RAM e Prior to programming as Code RAM the program code must be landed in the RAM through accesses on the data memory e As long as a RAM bank is used as code RAM access to the relevant RAM bank via the data area is no longer permitted e Ifacode RAM is used the lowest 4 Kbytes can no longer be addressed by the external code memory e Areset resets the register settings for the code RAM The content of the internal RAM can also be affected by a reset Page 66 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 7 3 4 Expansion Interface to the 80C31 Core Via the ports A B C and D the ALE and XPSEN signal all signals of the C31 are taken outside The C31 must always be operated with address and data bus because the external memory of the DPC31 is connected to it The exact assignment is provided in Table 7 3 2 function alternative function PD2 is not to b
79. en the DPS is powered up that is after the user has transferred MAC_Start in the request list or the watchdog has expired in the mode DP_Control If the SSA message is repeated because the short acknowledgement was faulty on the bus the MAC ignores it because it has already accepted the new station address DPC31 HW Description Version V2 1 Page 35 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 5 2 2 Get Param Prm SAP61 For this SAP two exchange buffers of the same length are available One buffer is integrated as the indication buffer MAC_Prm buffer and the other is located as the User_Prm buffer in DPS buffer management The indication is always transferred to the user in the User_Prm buffer The DPS module accepts this request in any DPS mode Wait_Prm Wait_Cfg Data_Ex However the message has to have at least a length of gt 7 bytes otherwise it is ignored 7 4 3 2 1 0 Byte Name 0 5 Buffer Header 6 Station Status 7 WD_Fact_1 8 WD_Fact_2 9 MinTSDR 10 Ident_Number_High 11 Ident_Number_Low 12 Group_Ident DPV1_ Failsafe EN_D res res WD_ res res 13 DPV1_Status_ 1 14 DPV1_Status_ 2 EN PM 15 DPV1 ol spine PE 16 2489 Rem_Slave Data Figure 5 2 3 Assignment in the Data Field of the PRM Indication Buffer Byte 13 is permanently reserved for the DPC31 and must not be used for User Prm data The bytes 13 to 15 are reserved acc
80. ere included also Signal Name Driver Type In Out Tristate 5V tolerant 4 mA 120 pF is In Out Tristate 5V tolerant 4mA 80 pF PC In Out Tristate 5V tolerant 4mA 80 pF PD In Out Tristate 5V tolerant 4mA 80 pF ALE In Out Tristate 5V tolerant 4mA 80 pF XPSEN In Out Tristate 5V tolerant 4mA 10 pF XCSDATA Out Tristate 5V tolerant 4mA 80 pF XCSCODE Out Tristate 5V tolerant 4mA 80 pF PE In Out Tristate 5V tolerant 4mA 100 pF PF In Out Tristate 5V tolerant 4mA 100 pF PG In Out Tristate 5V tolerant 4mA 100 pF PH In Out Tristate 5V tolerant 4mA 100 pF SSCLK Out Tristate 5V tolerant 8mA 100 pF SSDO Out Tristate 5V tolerant 8mA 100 pF CLKOUT1X2 Out Tristate 5V tolerant 8 mA 50 pF CLKOUT1X4 Out Tristate 5V tolerant 8 mA 50 pF RTS_TXE Out Tristate 3 3V 8 mA 50 pF TXD_TXS Out Tristate 3 3V 8 mA 50 pF No pull up resistors including the capacity of the emulation connection 70 pF XPSEN to be used only for activating the emulator otherwise XCSCODE is to be used Table 9 5 1 ID Data of the Outputs If in reality the capacitive load deviates from the assumed values the result will be a change of 0 7 ns maximum per 10pF 9 5 2 Timing Diagrams Signal Run Times In general the following applies all signals that start with X are low active The signal runtimes are based on the capacitive loads shown in Table 9 6 1 All timing that refers to the elementary period T is defined according to Table 9 6 2 XP
81. eserved SIEMENS XReset Driver Control Logic DPC31 HW BusType 2 0 RESET ComDeC RTS_TXE SER Interface Figure 7 1 5 M68HC16 System as an Example for Asynchronous Motorola Mode 7 1 2 10 Interface If the DPC31 is to be operated without external processor an I O interface is available instead of the processor interface can be set via the bus type pins This I O interface consiDXB of four ports PEz o PF7 0 PGz 0 PHa o Each port bit can be configured as input or output by the internal application C31 The outputs can be addressed bit by bit as well as byte by byte Reading is always byte by byte To configure the I O bits each port has a Direction Register Dir Reg The output status is kept in a register bit refer to Table 7 1 2 After reset all ports are switched to input The addressing of these I O ports is provided in Chapter 7 3 2 Dir Reg H 0 Out 1 In Addresses Adr H 9 ByteAddress Adr_Ho BitAddress Adr_H BitAddress Adr_H gt BitAddress 125 I O Interface Dir_Reg_G o 0 Out 1 In Addresses Adr_G7 o ByteAddress Adr_Go BitAddress Adr_G BitAddress Adr_Go BitAddress Adr_Gs BitAddress Adr_Ga BitAddress Adr_Gs BitAddress Adr_Ge BitAddress Adr_G7 BitAddress Table 7 1 2 IO Interface on the Processor Interface DPC31 HW Description Copyright Siemens AG 2004 All rights reserved Dir_Reg_F o 0 Out 1 1n Addresses Adr_F7 0 ByteAddress Adr_Fo
82. established as it is used for the interface of an intrinsically safe bus station The combination RxS TxS is an advantage when activating a transformer It is useful to make the signals RTS and ADD available at a joint output RTS ADD Switching between the two modes can be parameterized Param Register refer to 3 3 In order to ensure the minimum gap between two messages the transmitter is disabled at the end of a message for the duration of a minimum interframe gap time The gap timer is loaded with the current value for the interframe gap time from the interframe GAP_Time register Chapter 3 3 gt according to IEC 1158 2 Chapter 7 Page 70 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC SC 10101010 Fire 1 01 i j l ADD I l j j 1 Fa 1 Table7 5 6 Output Signals of the Synchronous Transmitter 7 5 2 2 Receiver Receive Filter The receive filter conditions the receive signal RxS for clock recovery and for decoding Manchester Decoder and Clock Recovery This unit includes all the resources that are needed to decode the data from the filtered receive signal The Clock Recovery recovers the clock CLK1 from the filtered receive signal and the system clock CLK16 whose nominal frequency corresponds _ to the 16 fold data rate Because of the ambiguity of the zero crossings
83. f present is not deleted Structure of the Diagnosis_Reply Buffers The user transfers the Diagnostic_Reply buffer shown in Figure 5 2 4 The buffer control area is located in the first 6 bytes In the 7 byte the user only enters the bit Diag Ext_Diag and in the 8 byte the bit Diag Stat_Diag The remaining bits in these two bytes can be assigned as required The user sets up Byte 9 StationStatus_3 Byte 11 12 dent Number and Byte 13 250 Ext_Diag data completely Byte 10 is used as wildcard for Master Add and can be assigned as required During buffer exchange DPS enters the internal Diagnosis_Flags in Bytes 7 and 8 and also enters the Master_Add in Byte 10 refer to Figure 5 2 5 7 6 5 4 3 2 1 0 Byte Name EIERE N 0 5 Buffer Header ga i SR iag Diag BE 8 StationStatus_3 Diag_ Be 9 Wildcard ne Dr es es a ar a 10 Ident_Number_High BE DE EE EG E HE ER E Ident_Number_Low BE EHER EE EE RENNEN FREE gt gt Ext_Diag Data Figure 5 2 4 Structure of the User_Diag_Reply Buffer 7 4 2 1 Byte Name Buffer Header DS zk Not B Ext a Le StationStatus 1 Prm_ Sup _Diag Cfg_ Station_ ES ported Fault Not_Rd Diag Diag Diag Diag Diag StationStatus_2 Sync_ Freeze_ WD_On Stat_ Prm_ Mode Mode Diag Req Diag fea StationStatus_ 3 Diag_ ae a Master_Address Ident_Number_High Ident_Number_Low Ext_Diag Data Figure 5 2 5 Structure of the MAC_Diag_Reply Buffer DPC3
84. fer This service is accepted by DPS in any DP mode If the Check_Config message does not come from Master Add i e the locking master DPS ignores this message The user evaluates the configuration data After DPS has received a plausible Cfg message there will be an indication That is DPS exchanges the indication buffer in the Cfg SAP for the User_Cfg buffer from DPS buffer management and generates the New_Cfg_Data interrupt There is no response at this time in the DP_SM The user must then check the User_Config_ Data and acknowledge either positively or negatively see below User_Cfg_Ok Cmd Read Operation fo fo fo fo o o ser Ack User Acko User_Ack o 00 User_Cfg_Finished User_Ack 9 01 gt Cfg_Conflict User_Ack o 11 Not_Allowed User Ach o 10 not possible User_Cfg_Not_Ok Cmd Read Operation Fo jojojo o o ser ze JL User Acko User_Ack o 00 User_Cfg_Finished User Ach a 01 gt Cfg_Conflict User_Ack o 11 Not_Allowed User_Ack o 10 not possible Table 5 2 3 Coding of User_Cfg_ Not _OK Cmd During operation if the interrupts New_Prm_Data New Ext_User_Prm_Data and New_Cfg_Data are pending at the user at the same time the user must follow the sequence Set_Param Set_Ext_User_Param and then Check_Config acknowledgement 5 2 4 Slave_Diagnosis SAP60 The diagnostic data of DPS in the DPC31 can be fetched by the master any time Page 38 Version
85. fer remains for the user and can be used again as a Response buffer Buffer_State 1 Response 0 Lengt Data Butter This value specifies the length of the data field in the Indication buffer unoccupied in the Response buffer If the net data length of the Request frame exceeds the available buffer length the MAC responds with no Resource Comment SAP is made plausible according to the following sequence Request_SA resp status RS Access Value resp status RS Length_Data_Buffer resp status RR Request Response_Data_Length This value specifies the length of the entered net data in the Indication or Response buffer 0 to 244 bytes Request Response_FC The MAC enters the function code of the Request frame here in the Indication buffer The following codes are available SM Time 0 01xx0000b SM Time 1 11xx0000b Send Data with Acknowledge low 01xx0011b Send Data with no Acknowledge low 01xx0100b Send Data with Acknowledge high 01xx0101b Send Data with no Acknowledge high 01xx0110b DXB Request 01xx0111b DXB Response low 00xx1000b DXB Response high 00xx1010b Send and Request Data low 01xx1100b Send and Request Data high 01xx1101b xx received FCB FCV The user stores the Responder status in this field in the Response buffer The following codes are permitted 900010005 DPC31 HW Description Version V2 1 Page 29 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS amp Send Data ok
86. fety reasons see Table 9 6 4 For switched off PLL XPLLEN 1 The reset duration should be greater than 40 clock cycles at the XTAL1_CLK pin 9 5 2 4 Interrupt After acknowledging an interrupt with EOI there is at least a 1us or 1 ms wait in the DPC31 prior to a new interrupt being read out DPC31 HW Description Version V2 1 Page 89 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Table 9 5 5 Interrupt Inactive Time after EOI X INT EOI Figure 9 5 2 Peripheral Mode Interrupt EOI Timing Profibus Interface RTS 7 to TXD Setup Time XAsyn Syn low 7T 7T Ter XAsyn Syn high 0 RTS J to TXD Hold Time XAsyn Syn low 5T 6T XAsyn Syn high 0 T elementary period TBIT elementary period of the transition clock pulse of the Profibus Interface XCTS_RXA 0 Table 9 5 6 Specification of the Profibus Interface RTS TxD Figure 9 5 3 Transmit Timing XCTS constant log 0 9 5 2 5 uP Interface 9 5 2 5 1 Synchronous Intel Mode 80C32 Page 90 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Address to ALE J Setup time Address AB 15 hold time after XRD T or XWR T XRD J to Data Out access to RAM XRD J to Data Out access to the registers ALE J to XRD J Data hold time after XRD T Data hold time after XWR T Data setup time to XWR T XRD T to ALE T XRD Pulse Width
87. ffer is being sent i e the diagnostic buffer is occupied during evaluation of both requeDXB then e The request with Cfg_Fault sets only one internal memory bit e A subsequent request without Cfg_Fault resets this internal memory bit i e the User Leave Master with Cfg_Fault is suppressed in this case Set Addr The user uses this request to initiate an immediate change of the node address The node address is evaluated by DPC31 only when each new frame is received The new node address must be lt 125 The new node address can be read back after the successful conversion in the TS_Adr_Register 846h 5 1 3 Acknowledgement Interface for FDL and FMA Indication_Queue FMA confirmations for example MAC_Reset con refer to Chapter 5 1 2 are transferred to the user in an Indication_Queue polling list Figure 5 1 5 shows the organization of the Indication_Queue With each entry 3 bytes respectively the IndQ_Entry Int is additionally generated for the user If the queue is full and the MAC is to make another entry this indication is abandoned and the IndQ_Full Int is set refer to Chapter 7 1 4 The user should avoid this condition by dimensioning the queue accordingly large There is no effect on the bus for example no RR if the queue is full Page 32 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC The organization of the Indication_Queue i
88. gger Hysteresis Input rise time Input dropout time Bus fight time Schmitt trigger input rise time Schmitt trigger input dropout time Table 9 2 1 Permitted Operating Values 9 3 Guaranteed Operating Range for the Specified Parameters DC Supply Voltage Von 3 0 3 6 V Operating Temperature Topt 40 85 C Table 9 3 1 Guaranteed Operating Range of the Specified Parameters 9 4 Power Loss Power Loss all values worst case estimate Asynchronous approx 325 mW at 12 MBd Synchronous approx 7 mW at 31 25 kBd and 2MHz clock C31 switched off approx 11 mW at 31 25 kBd and 2MHz clock C31 core 1MHz approx 35 mW at 31 25 kBd and 16MHz clock C31 core 8MHz Power Loss all values measured typically Asynchronous no values Synchronous no values 9 4 1 Power Up of the Supply Voltage If the DPC31 is used in modules with mixed voltage supply 3 3V and 5V the voltage difference between the supply pins Vpp 3 3V 10 and the signal pins Vio is to be no larger than 3 0V at any time Vio Von lt 3 0V If this value is exceeded the DPC31 will be destroyed All pins except Pin 95 96 98 and 99 Ke DPC31 Step C does not apply to Input Pins 6 87 88 and 98 13 DPC31 Step C only applies to Input Pins 6 87 and 88 Page 84 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS DPC31 HW ComDeC Einschalten der Ausschalten der Baugrup
89. gister Bit 1 The IRR bit is cleared Bit 0 The IRR bit remains unchanged After reset all bits are cleared Interrupt EOI Register EOI writable can be changed during operation EOI is triggered based on the write operation to the register cell Interrupt EOI Register The write data is don t care 7 2 Synchronous Serial Interface SSC Interface In the DPC31 a universal synchronous serial interface is integrated In addition several SPI slave blocks ser E7PROMs or AD transformers can be connected to this interface Figure 7 2 1 This SSC interface has full duplex capability and only supports the master mode CS N SCK SO SI CS N SCK SO Sl E PROM AD Transf AT25640 AD7714 Figure 7 2 1 SPI Interface at the DPC31 To connect SPI devices ser EPPROM AD transformer an output port is needed per SPI device in addition to the SSC channel in order to generate the chip select signal Description of the SSC Module The SSC module consiDXB of a transmit channel and a receive channel Each channel contains a 9 bit shift register and an 8 bit buffer Character widths of 1 to 8 bit are supported The user operates the transmit buffer If the transmit buffer is empty the transmitter generates the Transmit Buffer Empty which can be polled via the status register or which with a corresponding enable in the Interrupt Enable Register activates the SSC interrupt After loading the transmit buffer Transmit B
90. gister present i e all bits of this register are set to the default value The register is read only 1 The expanded parameter register is enabled and can be written to En_LM Val This bit enables additional evaluation of the Value1 byte for the request interface when User Leave Master is requested 0 No evaluation of Value Byte 1 1 The content of Value Byte 1 is evaluated also Disable_C_Buffer This bit determines whether the Clear Buffer is applied by the user or automatically by the DPC31 However due to a hardware defect automatic application of Clear Buffer is not available on the DPC31 Step B 1 User must output the Clear state to the outputs when required 0 When required the DPC31 automatically applies the Clear Buffer using the DP DOut_SM If the user outputs the Clear Buffer to the outputs this is signaled using two means Expanded Parameter Register Additional parameter bits are transferred in the expanded Param Register These bits may only be changed in MAC state Offline When the MAC_Start request is executed these Page 22 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC parameters are distributed to the individual modules Subsequent changes are not taken into account by KRISC The expanded parameter register is available starting with DPC31 Step C but only if Bit 28 En_Erw_Prm is set to log 1 in the parameter register
91. he asynchronous interface the most DPC31 HW Description Version V2 1 Page 69 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS significant data bit is transmitted first The transmitter generates a 16 bit CRC field and attaches it to the data field PREAMBLE SD FC DA SA Data FCS CRC 1 8 Byte 1 Byte 1 249 Byte 2 Byte Table7 5 3 Frame Structure of the Serial Interface Figure 7 5 5 shows the coding rules Figure 7 5 6 shows the structure of the preamble and of the delimiters These figures show that the elementary characters smallest quantization unit at the transmitter output have the length of half a bit period Their generation requires the double bit clock Binary 0 Binary 1 NON DATA NON DATA Table7 5 4 Bit Coding of the Synchronous Interface Bit Boundaries 1 0 1 0 1 0 1 0 Preamble 1 8 Byte 1 N N 1 0 N N 0 Start Delimiter 1 N N N N 1 0 1 End Delimiter Table7 5 5 Preamble and Delimiters The transmitter makes different output signals available Figure 7 5 6 In addition to the signals RTS enable of the send driver and TxS send signal the signal ADD can be utilized With the combination of TxS and ADD an adder circuit for activating a current control unit can easily be
92. he package provides a convenient C interface for interfacing Profibus communication with the slave process 2 Overview 2 1 General Data Package 100 Pin PQFP Baud rate Asynchronous 9 6 19 2 45 45 93 75 187 5 500 kBd 1 5 3 6 amp 12 MBd Synchronous 31 25 kBd Bus Interface C31 Ports 8 Bit asynchronous synchronous Intel and Motorola interface Standard Port Interface 4 Ports for external memory expansion and emulator interface Synchronous serial interface SPI for connecting serial E7PROMs A D converters etc 6 kByte approx 5 5 kByte utilizable can be directly addressed and can be broken down into data and code memory Environmental Cond 3 3V 10 40 to 85 C SSC Interface Memory Area 2 2 Differences Between the DPC31 and the SPC3 SPC4 Characteristics General Package External uP Interface Family Preprocessing External Memory Expansion C31 SSC Interface SPI I O Interface Internal PLL Communication RAM PB Communication Baud rate async RS485 sync Manchester DP Slave Receive Resources Integrated User Functions E PROM Read Write DPV1 Protocol DPC31 100 Pin PQFP parallel 8 bits Siemens Intel Motorola yes via int C31 yes Flash RAM etc yes for example E PROM up to 64 kByte A D conv AD7714 yes up to 40 bits yes input 12 MHz max 5 5 kByte 9 6 kBd to 12 MBd 31 25kBd fully integrated exchange buffer SPC3 44 Pin PQFP paralle
93. ication buffer indicates that an Indication has been buffered and thus the buffer is occupied not for DP_SAPs or in the case of the Response buffer indicates that the Response data are being sent With the corresponding FDL indication Req_Pdu Indication or Poll_End Indication the MAC resets this flag Butter Control o Butter Giate Event Response Buffer No_Ind_Reset 2 0 Indication In_Use Reserved Figure 5 1 3 Assignment of Buffer_Control Buffer_State Access control to the buffer only relevant for FDL SAPs 0 MAC 1 User Event_Indication Display an Indication only relevant for FDL SAPs Page 28 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 0 No Indication 1 Indication Response Control of Response data 0 The user has provided no response data 1 The user has provided response data Buffer_In_Use Indication buffered or response data are being sent 0 No indication buffered or response data are not being sent 1 An indication is stored in the Indication buffer not for DP_SAPs or the data are being fetched from the response buffer No nd Reser Control of Response buffer after the Poll_End Indication only relevant for FDL SAPs In the case of Req_Pdu Indication this bit is overwritten by DPC31 O The buffer becomes the Indication buffer and is assigned to the MAC Buffer_State 0 Response 0 1 The buf
94. ime SAP is enabled in the SAP_SCB the delay timer is reloaded and started in the DPC31 directly after the receipt of SM2_Time0 and the receipt is indexed In addition the MAC saves the Remote Adr of this Time of Day_Master With the SM2_Time1 frame Broadcast FC COh the Time of Day_Master now communicates the time at which it sent the SM2_TimeO frame time of send completion and thus the time at which the DPC31 started its delay timer Upon receipt the MAC checks to determine whether SM2_Time1 has come from the same Time of Day_Master as SM2_Timet If so the MAC enters this Indication in the Indication queue and goes to Wait_New_Enable state Otherwise this frame is ignored S max 280ns nach ED Ende DPC31 HW Description Version V2 1 Page 49 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS If the user now processes the indication he must stop and read out the delay timer see Mode Register1 The real time of day is now calculated by adding the received time of day to the value in the delay timer Then the user must enable another time of day synchronization For this purpose the command En_New_SM_Time Sync must be transferred via the request interface The delay timer is a 16 bit timer with a resolution of 1us This enables implementation of a time of 65 5 ms If an overflow occurs the Delay_Timer Overrun interrupt is generated and the timer starts over If the MAC receives an
95. in the active circuit state The capacitor C1 decouples the external voltage 5V and the internal Vcc This comparator circuit is not integrated into the DPC31 and must be implemented externally 5V Vcc peran R2 R SG Ausgang Optokoppler R1 R4 S nach Koppelkondenstor C 5 6k 22k 27K D GR DEER C1 R6 Referenzspannung in IE IL rem 56k NZ anal 1 a CS R3 R5 c2 7 68k 68k J 68pf Si Ausgang Komparator GND Table7 5 12 Wiring of the Comparator with Bridge Network DPC31 HW Description Version V2 1 Page 77 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 7 5 2 4 Interface Signals Pin Name Signal Name Input l Comment Output 0 TxS TxS_IM Send signal for asyn physics TxD RxS RxS_IM Receive signal for asyn physics RxD TxE Enable of the send drivers addition signal for asyn physics RTS RxA Auxiliary signal for receive has not been needed so far in the syn physics unit apply to GND for asyn physics XCTS Figure 7 5 13 Synchronous PROFIBUS Interface of the DPC31 In the test mode all outputs are switched to high resistance 7 6 DPS Watchdog Timer 7 7 Watchdog Timer 7 7 1 Automatic Baud Rate Detection The DPC31 is able to recognize the baud rate automatically The Baud_Search mode is entered after each RESET as well as after the expiration of the Watchdog WD timer in the Baud_Control mode
96. ing Range for the Specified Parameters 84 DPC31 HW Description Version V2 1 Page 5 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS 9 4 Power Loss 84 9 4 1 Power Up of the Supply Voltage 84 9 4 2 Structure of the Pad Cells with 5V Tolerance 85 9 4 3 DC Specification of the Pad Cells 87 9 5 AC Specification 88 9 5 1 Driver Capability 88 9 5 2 Timing Diagrams Signal Run Times 88 9 5 2 1 Clock Supply XPLLEN 1 89 9 5 2 2 Clock Outputs 89 9 5 2 3 Reset 89 9 5 2 4 Interrupt 89 9 5 2 5 uP Interface 90 9 5 2 5 1 Synchronous Intel Mode 80C32 90 9 5 2 5 2 Asynchronous Intel Mode X86 Mode 92 9 5 2 5 3 Synchronous Motorola Mode E_Clock mode for example 68HC11 93 9 5 2 5 4 Asynchronous Motorola Mode for example 68HC16 95 9 5 2 6 C31 Memory Interface internal C31 on external memory 97 9 5 2 7 Emulator Interface 99 9 5 2 8 SSC Interface SPI 102 10 MECHANICAL SPECIFICATION 103 10 1PQFP 100 Casing 103 11 DPC31 PINOUT 106 12 APPLICATION NOTES 107 12 1DPC31 Wiring 107 12 2PROFIBUS Interface 107 12 2 1 Pin Assignment 107 12 2 2 Wiring Example RS485 Interface 109 13 APPENDIX 110 13 1Addresses 110 13 2General Definitions of Terms 110 13 30rder Numbers 111 Page 6 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 1 Introduction Siemens offers to its users several ASICs for data exchange between automation devices
97. ist SAPx_Ptr FFh This means they will not be controlled by the DPC31 either Check_En_Prm_Cmd 1 in the Param Register enables the check of Enable _Prm_Cmd in the Set_Prm frame DPV1_Status_3 Bit 7 However this only occurs in the Data_Ex state and Operation Mode V1 when a new Prm frame V1 is received from the same master If Enable_Prm_Cmd 1 DPS remains in the Data Ev state When Enable_Prm_Cmd 0 a Leave_Master is executed 6 User Functions on the C31 Controller The DPC31 contains an integrated C31 core that is available entirely for user functions One of the two external interrupts XINTO is already being used for interfacing the communication component and is therefore no longer available to the application 7 Description of the Hardware Blocks 7 1 Universal Processor Interface The DPC31 has a parallel 8 bit interface with a 13 bit address bus It supports all 8 bit processors and micro controllers as follows 80C31 32 by Intel and the Motorola HC11 family It also supports the 8 16 bit processors and micro controllers of the 80C166 family by Siemens X86 by Intel and the HC16 HC916 family by Motorola In addition a clock pulse scaler is integrated which makes the internal work clock pulse divided by 2 pin CLKOUT1X2 or 4 pin CLKOUT1X4 available as system clocks in order to be able to connect a slower controller without additional effort in a lowcost application refer to Chapter 7 8 1 Bo
98. l 8 bits Siemens Intel Motorola no no no no no 1 4 kByte 9 6 kBd to 12 MBd no fully integrated exchange buffer Table 2 2 1 Differences with respect to SPC3 and SPC4 Page 8 05 04 Version V2 1 SPC4 44 Pin PQFP parallel 8 bits Siemens Intel Motorola no no no no no 1 14 kByte 1 64 for SPC41 9 6 kBd to 12 MBd 31 25 kBd partially integrated polling list DPC31 HW Description Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 2 3 Function Overview Block Diagram Figure 2 3 1 shows the block diagram of the DPC31 The DPC31 has a bus interface for connecting an external microprocessor It is a parameterizable synchronous asynchronous 8 bit interface for various Siemens Intel and Motorola micro controllers processors Via the 13 bit address bus the user can directly access the internal 5 5k RAM or the register cells If the application does not need an external processor the ports of the bus interface can be used as I O This makes 27 I O bits available that the internal C31 can address individually The sequence control enters various events for example indication events error events etc in the interrupt controller that are signaled to the slave firmware via the interrupt pin These events can be enabled individually via a mask register Acknowledgement is made via the acknowledge register The SSC interface SPI is used for connecting a serial E PR
99. ll message contains request data the MAC acknowledges with no resource 5 2 10 Data Exchange Broadcast DXB Requirements for Data Exchange Broadcast e Every DP slave must be able to receive data from another DP node master or slave without going through its own master see Figure 5 2 5 e Each DP node master or slave must be able to send data to another DP slave without going through its own master e Up to 8 links per DP slave are possible Master Master Slave11 Slave1 Slave2 Slave10 Figure 5 2 6 Data Exchange Broadcast between different Masters and Slaves Implementation of Internode Data Communication e The DXB service Write_Read_Data with DXB enables internode communication from one DP slave publisher to several other DP slaves subscriber using a single data frame The master addresses the publisher with a special call service DXB request and the publisher responds under the broadcast address All slaves are thus in the position to receive this response frame e Configuration is used to inform each DP slave of which information is defined for it link buffer This configuration information is communicated to the node e The address relationship under which a DP slave is to receive data from one of these frames is entered in the respective link In addition the link includes the data range continuous that is to be tapped from the frame e The Publisher function applies to all DPS SAPs and the
100. n 24 G Dec 14 div RS485 wiring corrected 2000 RXD_RXS and XCTS_RXA Data Buffer EC EE 2002 2003 12 2 2 ER E 2004 May 19 Chap 13 3 Correction of the Order number 2004 DPC31 HW Description Version V2 1 Page 3 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS Table of Contents 1 INTRODUCTION 7 2 OVERVIEW 8 2 1 General Data 8 2 2 Differences Between the DPC31 and the SPC3 SPC4 8 2 3 Function Overview Block Diagram 9 2 4 Pin Description 10 3 MEMORY ASSIGNMENT 12 3 1 Memory Area Distribution in the DPC31 12 3 2 Control Unit Parameters Latches Registers 12 3 3 Organizational Parameters RAM 15 4 ASIC INTERFACE 23 5 COMMUNICATION FUNCTIONS OF THE SEQUENTIAL CONTROL SYSTEM 24 5 1 Structure of SAP List 25 5 1 1 Configuration of Buffer 28 5 1 2 Request Interface for DPS and FDL Instruction Queue 30 5 1 3 Acknowledgement Interface for FDL and FMA Indication_Queue 32 5 2 DPS Module Description of the Interface 33 5 2 1 Set_Slave_Address SSA SAP55 35 5 2 2 Get Param Prm SAP61 36 5 2 3 Check_Config Chk_Cfg SAP62 38 5 2 4 Slave_Diagnosis SAP60 38 5 2 5 Write_Read_Data Default SAP 40 5 2 5 1 DX Entered Interrupt 41 5 2 6 Global Control SAP58 42 5 2 7 Read_Inputs SAP56 44 5 2 8 Read_Outputs SAP57 45 5 2 9 Get_Config SAP59 45 5 2 10 Data Exchange Broadcast DXB 45 5 3 Additional FDL Functions 48 5 3 1 FDL_Monitoring Timer 48 5 3 2 Time of Day Synchroniz
101. n e Shield the entire quartz interface connection and Pins 98 and 99 against possible interferences e The voltage supply of PLL should be as free of interference as possible If required provide external support or filtering 8 Test Support The DPC31 has three test pins TST1 NTEST1 NTEST2 For operation all pins are to be at 0 Volt To switch the outputs to high resistance In Circuit Test NTEST1 2 are to be at 1 8 1 Emulator Connection for the C31 To emulate the C31 that is integrated in the DPC31 a standard emulator such as Hitex MX51AH can be connected The interfacing is shown in Figure 8 1 1 The emulator must be used with the SAB C501 40 or a type compatible with the timing because of the more relaxed timing of the processor Problem Case If the C165 20MHz without tristate time waitstate for DPC31 accesses and the C31 emulator 24MHz are operated together there may be access conflicts to the internal DPC31 RAM Remedy For accesses by the C165 to the DPC31 the tristate time waitstate is to be set accordingly DPC31 HW Description Version V2 1 Page 81 Copyright Siemens AG 2004 All rights reserved 05 04 70 S0 zg bed pen asa s yBu Iy 7002 OY susweis Iu uAdog uondusseq MH LEIdA L ZA vols on RESET CLKOUT1X2 XPSEN ALE PA PB PC PDrest PD2 PD6 WR RD DB 7 0 AB 15 0 CLKIN PSEN ALE PO P1 P2 P3rest P3 2 P3 6 IN CIRCUIT EMULATOR
102. n a DPS_User watchdog is implemented in DPS This timer can be enabled or disabled any time via the request interface DPS_User WD Enable or DPS_User WD Disable Note In the case of the SPC3 the processor is monitored via a counter The DPS_User_Watchdog is an internal 16bit RAM cell that is started by a user parameterized value DPS_User WD Value e o and is decremented every 10 msec If the timer reaches the value 0000h DPS does the following it executes Leave Master locks the DPS_User WD and enters the event DPS_User_WD Expired in the Indication_Queue The user has to cyclically set this timer to its initial value To do this the user must transfer DPS_User WD Reset via the request interface DPS then reloads the timer to the parameterized value DPS User WD Valuejs5_0 With DPS_USER WD Enable request the DPS_User WD is automatically set to its initial value and started 5 2 6 Global_Control SAP58 The MAC accepts the Global Control message only in the Data_Exchange mode and only from Master Add Under all other instances the service is ignored If more than two net data bytes Control_Command Group_Select are received refer to Table 5 2 6 or if there is no indication buffer DPS also does not accept this service Page 42 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 7 6 5 4 3 2 1 0 Byte Name ets Buffer Header e
103. n the IRR To make sure the position must be cleared in the IRR prior to the mask enable Prior to exiting the interrupt routine the processor has to set the End of Interrupt Signal EOI 1 in the EOI register see below With this edge change the interrupt line is switched Page 56 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS DPC31 HW ComDeC inactive If an event should still be stored the interrupt output becomes active again only after an interrupt inactive time of at least 1us or 1ms or at most 2us or 2ms refer to Chapter 9 6 2 2 Via EOL Timebase Param Register refer to Chapter 3 3 this interrupt inactive time can be set EOI_Timebase 0 gt 1us EOL Timebase 1 gt 1ms This makes it possible to reenter the interrupt routine when using an edge triggered interrupt input Host IRR IRR Write IAR Read IRR EOI INT Pol INT E NA EN Dee eee RE Ee D __ IAR SS 8 IRR IMR E FF gt Hi ab 3 2 EE 88 Oe Ge IRR IMR gt FF gt IAR IRR IAR IRR IRR EOI Write Read DPC31 C31 Core Figure 7 1 6 Interrupt Controller of the uP Interface and C31 Core in the DPC31 The polarity of the interrupt input can be parameterized Mode Register1 refer to Chapter 3 3 INT_Pol After the HW reset the ou
104. ncludes the following parameters IndQ_Base Ptr The Indication_Queue segment pointer IndQ_Length Describes the length of the Indication_Queue and is a multiple of the length of an entry n 3 IndQRd Ptr An Offset_Pointer and points to the next entry that is to be read and is managed by the user IndQ_Wr Ptr An Offset_Pointer and points to the next free entry and is managed by the MAC The queue is empty if IndQ_Wr Ptr and IndQ_Rd Ptr point to the same position One entry in the queue always has to remain empty Table 5 1 3 lists all possible indications with the associated command codes _ IndQ_ Base Pir Value1 Value2 IndQ_Rd Ptr User ear Entry 2 Command_Code u Valuei Value2 IndQ_Wr Ptr MAC Entry 1 Command_Code IndQ_Len Entry n Command_Code Value1 Value2 Wildcard reserved reserved reserved Figure 5 1 5 Organization of the Indication_Queue Request Com_Code Value1 Value2 Comment Req_Pdu Ind Buf_Ptr Request_Pdu received Poll_End Ind Buf_Ptr Response sent Poll end Stop_C1 Ind MSAC1S SAPs have been closed SAP_Act Deact Confirmation req_sa FDL_SAP activated deactivated MAC_Stop Confirmation MAC_Stop was executed Get_Ind_Resp_Buffer Ind_Resp_ The requested Indication Response Confirmation Buffer_Ptr buffer has been retrieved FDL_Timer Expired FDL_Timer_ FDL monitoring timer expired Control DPS_User WD Expired DPS_User Watchdog timer expired
105. nd XXXXXXXXD Points to the last byte that is to be tapped Link7 Destination Address 01111111b Source Address Oxxxxxxxb DXB_Data Length XXXXXXXXb Check byte 000000006 Response 01000000b Request Off_Data_Start XXXXXXXXD Off_Data_End XXXXXXXXD DPC31 HW Description Version V2 1 Page 47 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS End End coding of link buffer Table 5 2 9 Structure of Link Buffer User_New_DXB0 7 Cmd Read Operation fo o fo fo ou Buffer State U Buffer U Buffero U_Buffer_State 0 No new U_Buffer U_Bufferi o 00 Buffer U_Buffer_State 1 gt New U_Buffer LU Butter oa 01 gt Buffer2 LU Butter o 10 Buffer3 Table 5 2 10 Coding of User_New_DXB Cmd Timeout Monitoring of DXB Connections For timeout monitoring of the DXB connections the watchdog must be operated in DP Control state For this purpose the master must transfer a valid watchdog value with WD_On 1 in the Set_Param frame All configured links must have sent data at least once in a watchdog cycle The links are hereby registered in a Score_Actual_ Register When DXB mode is disconnected DPS deletes this Score_Actual_ Register Each signaled link is arranged in the appropriate bit position in the Score_Actual_Register Bit 0 to 7 with a log 1 according to its entry 0 to 7 in the link buffer If the watchdog has reached its parameterized value DPS compares the Score_Actual_
106. ng p 8H XPLLEN RXD_RXS 8 e Clock gt mek ma Profibus Interface f 2 el XTA SE CLKOUT1X2 A re nterface o a COUIRE SE e AVDD 92 eno ssoix tr SSC Interface 93 p Gg Fe NTEST1 pao 44 ADo 2 NTEST2 45 AD GND SS TST PAI La ADe D 1 PA 2 Mode Pins o P gz 20010 ar ADe LO BOOT PA 4 ADs 84 A 8 EE E WH PAs L p ADs _ O GND BUS2 PA L I qp Ar os Sey hee SE Ae oO 1 PC ie BS al PE a An 3 PC 9 8 gt rc zp az C31 Interface 5 qpy 15 6 A13 c De PEs PCs 868 p A3 _ PE 69 Ara ES Host Ds ar16 pe 8 ci Memory I Os x gt li w gs 18l pr op 54 P1 0 T2 S Interface ale ee 2 or A p a BE E E 22 pr PBs LU a 2 O Interface gt pr pa 2 qp P18 LAS p24 PBs Io 8 Aye 25 pr ee ei ES As ged P3 0 RXD PGo D Enn A 27 72 4p_P3 1 TXD SE Piai SES XINTO RESERVED Ait 31 Ge PD 74 _P3 3 XINT1 A12 gt 32 PGs PDs Se PDs P3 5 7 WINT 4 33 77 XWR XCS 34 PO Pos 78 p XRD XWR p 35 pg e m me i VDD __p 37 PH 42 SE XPSEN 42 _ ___ XBDY 4 281 py ALE D p 6 _ gt RESET 83 vex e Debug 12 2 PROFIBUS Interface 12 2 1 Pin Assignment Data is transmitted in the operating mode RS485 RS485 physics The DPC31 is connected to the galvanically isolated interface driver via the following signals Signal Name Input Function Output RTS Output Request to Send TX
107. nment FDL_Timer control With Timer_Enable 1 the FDL_Timer is enabled After each elapsed time interval 10 ms the timer FDL_ Timer_Count H L is decremented If it reaches a value of 0000h the reaction assigned in Timer_Action o is executed and the timer is disabled The following reactions are defined e No reaction e Lock SAP req_sa 7Fh e Remove access protection req_sa FFh all Timer_States Timer_States Timer_State Timer_Stateo o Timer Action Timer Actions Timer_Enable 7 0 Timer_States o User defined Timer_Action o 00 nothing Timer_Enable 0 disable Page 48 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Timer_Action o 01 gt req_sa 7Fh Timer_Enable 1 enable Timer_Action o 10 gt req_sa FER Timer_Action o 11 Reserved Table 5 3 1 Assignment of FDL_Timer Control In addition when an FDL_Timer elapses an entry is made in the Indication queue The SAP_No in which the FDL_Timer elapses and the FDL_Timer control is thereby transferred to the user The user recognizes the state of the connection monitoring in which the FDL_Timer elapses via the Timer_State o user defined not modified by DPC31 The FDL_Timer can be started stopped or reloaded on a sap specific basis using the request FDL_Timer_Change The new FDL_Timer Control and the Reload value FDL_Timer_Co
108. ns the serial data stream with the 4 fold transmission speed One requirement of the PROFIBUS protocol is that no idle states are permitted between the message characters The DPC31 transmitter ensures that this specification is adhered to In order to check outside systems for example S W solutions with respect to this point supplementary logic is implemented in the DPC31 receiver The receiver checks whether start bit synchronization takes place not at the ED character of a message after the stop bit By parameterizing DIS_START_CONTROL 1 in the param register or Set_Param message for DP this subsequent start bit check is switched off Page 68 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Due to the 4 fold scan a maximum distortion of the serial input signal of X 47 to y 22 in reference to the falling start bit edge is permissible 7 5 1 3 Interface Signals Pin Name Signal Name Input Comment Output O Send Data Receive Data Enable of the send drivers Sender Enable Table7 5 1 Asynchronous PROFIBUS Interface of the DPC31 In the test mode all outputs are switched to high resistance 7 5 2 Synchronous Physics Unit Manchester The synchronous interface makes data transmission according to IEC 1158 2 possible It includes services of the interface defined in this standard between the following data link layer and physical layer
109. nterface PA 8 vo SV Corresponds to PO forthe discretetype Corresponds to PO for the discrete type Corresponds to P1 for the discrete type Corresponds to P2 for the discrete type Corresponds to P3 for the discrete type Address Latch Enable For emulation only Chip select for external RAM Chip select for external ROM Type for loading the user program x Switch to In Circuit Emulator uP Interface SSC Interface SSCLK SSDO SSDI PLL Clock Unit XTAL1_CLK XTAL2 AVDD AGND XPLLEN Connection for SPI Chips Clock Connection for SPI Chips Data_Out Connection for SPI Chips Data_In Quartz connection Clock supply Quartz connection Separate Vpp supply for PLL Separate GND supply for PLL 5V Switching off the PLL and supply clock pulse via XTAL1_CLK 5V Clock pulse output CLK 2 without reset 5V Clock pulse output CLK 4 without reset 3 3V 3 3V aM Test Pin Test Pin Test Pin CLKOUT1 X2 CLKOUT1 X4 Physics Unit RTS_TXE TXD_TXS XCTS_RXA RXD_RXS RESET _ Test TEE NTEST2 TST1 ae Figure 2 4 1 DPC31 Pin List e 8 8 1 1 1 1 2 1 8 8 8 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Ht ft 1 1 FE 9 1o00 Because of the 5V tolerant I O and in order to ensure the least possible power loss no pull up or pull down resistors are integrated in the pad cells that is all unused inputs or all output ports since these are switched as input after reset are to be applied to one defined level
110. ntroller 2 Generation DPS DP Slave Din Input Data Page 110 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Dout Output Data MAC Medium Access Control MSAC1 Master Slave Acyclic Communication Class1 Master SPC2 Siemens PROFIBUS Controller 2 Generation SPC3 Siemens PROFIBUS Controller 3 Generation SPM2 Siemens PROFIBUS Multiplexer 2 Generation LSPM2 Lean Siemens PROFIBUS Multiplexer 2 Generation DP Distributed IO FMS Fieldbus Message Specification MS Micro Sequencer PLL Phase Lock Loop SM State Machine 13 3 Order Numbers The DPC31 Step C can be ordered via your Siemens contact person on location Please use the order numbers with the number of units reference provided below Product Order Number Delivery Units No of Units ASIC DPC 31 6ES7 195 0BF00 0XA0 Mini Package 6 6ES7 195 0BF10 0XA0 Single Tray 66 6ES7 195 0BF20 0XA0 Tray Box 660 6ES7 195 0BF301 0XAO 7 Tray Box 4620 FW DPV1 DPC 31 6ES7 195 2BB00 0XA0 Diskette DPC31 HW Description Version V2 1 Page 111 Copyright Siemens AG 2004 All rights reserved 05 04 Siemens AG Division Automation Engineering Combination Engineering Siemens AG PO Box 23 55 D 90713 Fuerth Germany Subject to change without prior notice SIEMENS Aktiengesellschaft Printed in the Fed Rep of Germany Order No J31070 E2257 R300 A1 0009
111. ock The ASPC2 Step E supports an equidistant cycle i e it begins with the DP cycle exactly on the clock pulse resolution approx 1 us For closed loop control systems such as an electronic shaft the DPC31 can generate a Sync clock clock pulse beater after receipt of the last bit of the first DP request This request must be a global control frame in its own group The Sync clock low active pulse of 2 3 usec length is output on Port PB and interrupt GC Clock is also generated So that Port PB is isolated for this function bit Enable GC_Clock 1 must be set in the C31_Control Register The special group for the Sync clock must be parameterized for the DPC31 by the user group clock During receipt of any GC frame by the DP master Master_Add the DPC31 makes a bit by bit AND operation of the second received data byte Group Select with Group_Clock If a hit occurs the Sync clock is initiated at the end of the GC frame The values for the jitter and the delay of the Sync clock are presented in Table 5 2 7 for asynchronous operating mode of the DPC31 and a load of 80 pF at Port PBo Baud Rate Delay after ED of GC frame _ Jitter max Tait 7 Tag 20 ns lt 6 MBd Ter 7 Tag 20ns Table 5 2 7 Timing Values for Sync Clock Failsafe Mode To support the failsafe mode a Spec_Clear_Mode is implemented in the DPC31 The master generates such a Clear mode by sending a Global Contr
112. ol message with Clear_Data 1 The Din data has to continue to be fetched during this Clear_Mode For this the master has to send the Write_Read_Data message with the parameterized number of Dout data bytes 00h However in the case of many slave applications the value 00h does not correspond to the Clear mode for example substitute values for analog modules Here the user generates the corresponding substitute values If the Global_ Control message was not received because of a bus fault this slave does not know that it should be in the Clear mode therefore the subsequently received Dout data bytes with the value 00h can t be replaced with the substitute values To support the failsafe mode the DPC31 also accepts Write_Read_Data messages without output data even though the parameterized Dout length Dout_Buffer length 0 is set After the receipt of this message the C buffer where the substitute values are stored is then included in the buffer circulation If the user fetches this buffer in operation with Clear buffer the display U_Buffer_Cleared is set with User_New_Dout Cmd refer to Table 5 2 4 and the user receives the information that it is cleared data substitute values If the user fetches this buffer in operation without Clear buffer he receives information with req_ssap byte in the buffer header or with the U_Buffer_State register on whether the data from the data buffer or substitute values are
113. oller of the uP Interface in the DPC31 Via the interrupt controller the processor is informed of various events These consist primarily of indication messages and different error events The controller has no prioritization level and does not provide an interrupt vector not compatible with 8259A It consiDXB of the following an interrupt request register IRR interrupt mask register IMR interrupt register IR and an interrupt acknowledge register IAR The structure is shown in Figure 7 1 6 In the IRR every event is stored Via the IMR individual events can be suppressed If for example the DPS indications are evaluated only by the internal C31 the corresponding masks have to be set here and enabled for the C31 in the interrupt controller The entry in the IRR is independent of the interrupt mask Events that are not masked out in the IMR generate the X INT Interrupt Pin PGs via a cumulative network For debugging the user can set every event in the IRR only those bits are activated that are to be set Each interrupt event that was processed by the processor has to be cleared via the IAR except for New_Prm_Data New_DDB_Prm_Data New_Cfg_Data A log 1 is to be written to the corresponding bit position If anew event and an acknowledgement of the previous event are pending at the same time at the IRR the event remains stored If the processor subsequently enables a mask it has to be ensured that there is no past entry i
114. on an End Character FFh When a DXB response frame is received the MAC makes this frame plausible with the link entries In so doing the received DA and SA addresses are compared to the corresponding entries In addition the received net data length must correspond to the value assigned in DXB_Data length Because each DP master can also be a DP slave the frame type Request or Response must also still be made plausible If the received frame is now plausible with a link entry the preset data area tap which is specified by two offset pointers start Off_Data_Start End Off_Data_End is tapped and placed in the appropriate D buffer Three alternating buffers apiece are available for each configured link Of these the D buffer is integrated in the DXB_SCB as a DXBn_D buffer Data Unit SSE Example O Off_Data_Start 2 Off Data End 4 Example Off_Data_Start 0 Off_Data_End 0 Figure 5 2 7 Programming of Off_Data_Start and Off Data End Entries Coding Comments Cntl Header 6 Bytes Loes Section 5 1 Destination Address 01111111b Compared to the received DA Source Address Oxxxxxxxb Compared to the received SA DXB_Data Length XXXXXXXXD Must correspond to the net data length of the tapped frame Check byte 00000000b Response Compared to the masked frame type bit of the 01000000b Request received FC Off_Data_Start XXXXXXXXD Points to the first byte that is to be tapped Off_Data_E
115. ording to DPV1 and should not be used for User Prm data in order to make a compatible change to DPV1 possible Page 36 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Byte 13 Bit 2 WD_Base This bit specifies the time base of the watchdog in DP_Control the following assignment applies WD_Base 0 time base of 10 ms WD_Base 1 time base of 1 ms Default state WD_Base 0 Byte 13 Bit 4 Must be assigned log 0 Byte 13 Bit 5 EN _DP_DXB The bit specifies whether DDB Request and DDB_ Response frames filter or pass through on the default SAP EN _DP_DXB 0 Only DXB_Request frames are filtered EN_DP_DXB 1 Error free DDB Request and DXB_Response frames are are passed through and processed by the MAC Default state EN _DP_DXB 0 Byte 13 Bit 7 DPV1_Enable This bit enables the coupling of the MSAC1S SAPs to the cyclic machine if Check_DPV1_Enable 1 Param register and the parameter assignment frame contains a data length gt 10 bytes DPV1_Enable 0 No coupling of MSAC1S SAPs DPV1_Enable 1 Coupling of MSAC1S SAPs Byte 15 Bit 7 Check_En_Prm_Cmd 1 in the Param register enables Enable _Prm_Cmd in the Set_Prm frame DPV1_Status_3 Bit 7 to be checked However this occurs only in the Data_Ex and Operation Mode V1 state when a new Prm frame V1 is received from the same master If Enable Prm_Cmd 1 DPS remains in
116. other SM2_TimeO frame from the same time of day master a fault occurs For example it is possible that the SM2_Time1 frame has been lost due to a bus malfunction The Ignore_Delay_Timer_ Overrun interrupt is thereby generated to the user The user must then stop the delay timer and enable a new synchronization with the En_New_SM_Time Sync request 5 3 2 1 Support of MSACS1 SAPs To support Master Slave Acyclic Class 1 opening and closing of SAPs 50 51 and 52d can be coupled to the cyclic machine To do so the user must set Bit Check_DPV1_Enable 1 in the Param Register If the DPC31 is now assigned in DPV1 mode DPV1 Enable 1 in the Set_Param frame DPV1_Status_1 Bit 7 and this frame contains at least 10 data bytes DPS opens these SAPs for the DP master Master_Add upon entrance in Data_Exchange No message is sent to the user When the Data_Ex state is left these SAPs are again locked and any buffered Indications are deleted Buffer_In_Use 0 However the buffer control Buffer_State Response in Butter Control Byte is not changed In addition an Indication is made to the user Stop_C1 Ind in the Indication_Queue The user must then readjust the buffers of SAPs 50 52 and confirm this to the DPC31 Stop_C1 Con in the Instruction Queue Return to Data_Ex is only possible after this confirmation If the acyclic machine does not require all of the SAPs 50 52 the user must lock them in the SAP_L
117. pe Baugruppe Vio pmax 3 0V She a p Ss ES Pa Pa Se ae A S Table9 4 1 Voltage Ramp for 5 V Tolerant UO During switching on and off the voltage at the 5 V tolerant signal pins must not exceed a value of 6 0 V or fall below a value of 0 3 V The 5V tolerant outputs can themselves only cause a voltage of 0 3 V up to VDD 0 3 V to flow A higher voltage at the pin can only be brought about by external components e g pull up resistors These values must not be exceeded otherwise the DPC31 may be destroyed Pins 95 96 98 and 99 only Einschalten Betrieb Ausschalten Table 9 4 2 Voltage Ramp for LVTTL I O During switching on and switching off the voltage at the indicated signal pins must not exceed a value of Vpp 0 3 V or fall below a value of 0 3 V These values must not be exceeded otherwise the DPC31 may be destroyed 9 4 2 Structure of the Pad Cells with 5V Tolerance The input pad cells used have a tolerance of 5V that is they are provided with a protective circuit This means that although they are supplied internally with only 3 3V the input level may be 6 V maximum Table 9 5 1 shows the operating points The 5V tolerant output pad cells are also provided with a special protective circuit When driving the 0 level there is no difference with respect to the conventional pad cells The 1 level is driven actively up to Vpp 0 3V Starting with this voltage the external pull up resistor pulls the level
118. s are too small or occupied see next section it replies with No Resource RR If only two buffers or one buffer is made available more than one pointer must point to the same buffer When the response is generated the MAC of Ind_Resp_Buffer Ptr1 3 searches for a Response buffer and sends the response data from the first one found Ind_Buffer_Ptr In the case of DP_SAPs a fixed Indication_Buffer is available In so doing the respective MAC_Buffer Ptr eg Ind_Buffer Ptr MAC_Prm_Buffer Ptr in SAP61 is always hooked in Because all Indication resources are designed as alternating buffers a receive resource is available at all times For DP_SAPs that require no receive resources eg diagnostic SAP60 the Ind_Buffer Ptr 00h is set by the MAC Resp_Buffer Ptr In the case of DP_SAPs the Response_Buffer Ptr points to the swapped out Response buffer In the case of DP_SAPs without a Response buffer e g Set_Param Check_Config etc the MAC enters a value of 00h in the pointer during startup It then answers a Request with a short acknowledgement For the FDL_SAPs the following entries still have to be made FDL_Timer Control The control for the FDL monitoring timer is stored in FDL_Timer control The control includes an Enable_Bit and a Reaction coding for timer expiration see Section 5 3 1 FDL_Timer_Count Low High 16 bit timer for monitoring of FDL connections The timer interval is 10 ms Times up to 655 s can b
119. s controlled by C31 default 1 The clock pulse striker GC Clock is fed to Port PBs Ena DX_Out_Port The Interrupt DX OUT IRR can be applied directly to Port PB3 0 Port PB is controlled by C31 default 1 The interrupt DX_OUT is fed to Port PBs 5 Communication Functions of the Sequential Control System PROFIBUS Layer2 and the DP slave module are implemented in the sequential control system Layer2 is composed of a MAC media access control part and an FLC interface services part In the following the Layer2 module is simply called MAC module The user can influence only the cells that are described here Page 24 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 5 1 Structure of SAP List All liDXB and buffer elements are located in the communication memory and are addressed via an 8 bit segment buffer pointer When a list or buffer is accessed the communication control adds an 8 bit offset address to the segment address shifted by 5 bits result 13 bit physical address A granularity of 32 bytes results for the list and buffer start addresses The SAP structure includes an SAP_List addressed via the SAP_List_Base Ptr and an SAP_SCB System Control Block addressed via the SAP_SCB_ Base Ptr In the SAP_List a pointer is entered for each SAP Default_SAP SAPO 63 and the SM_Time_SAP which points to the SAP SCB as an offset The SAP_
120. s reserved 05 04 ComDeC DPC31 HW SI EMENS tLHLL CHE tLLPL ALE KE j tpLscL EN XCSCODE teLPH XPSEN Lu tbx z tpx PA A0 A7 Instr out A0A7 ES A8 A15 A8 A15 Figure 9 5 15 Emulator Code Read Cycle PA data bus of DPC31 is only active if e Internal code RAM is programmed e Address created by emulator is lt 1000H e Inthis case XCSCODE konst 1 Syme ____Feremeter_ __Min_ __Mex__ _nt ALE pulse width Address setup to ALEL XRD pulse width XWR pulse width Address hold after ALE XRD to valid data out Data hold after XRDT Data float after XRDT ALE to XWR or XRD Address valid to XWR or XRD XWRT or XRDT high to ALE high Data setup to XWRT Data hold after XWRT Address float after XRD Address valid to XCSDATAL C for Port A 120pF C for XPSEN 10pF C for all others 80pF Table 9 5 14 Timing Values for Emulator Accesses to Data Memory SS After this time the output driver of the DPC31 is switched off The signal level on the bus depends on the bus load and the size of the pull up resistors Page 100 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC pt twHLH ALE XPSEN tavsoL XCSDATA d Dat TI tRLRH XRD tavwL Int pu taLaz tanz tLLax2 ed k tRHD PA instr A0 A7 Data Out EB PC A8 A15 SE Figure 9 5 16 Emulator Data R
121. synchronous with 24MHz for synchronous with 2 4 or 8 MHz Page 62 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC In order to get the original performance of the C31 Ports A B and D must be wired with external pull up resistors Address Port C is always on Output and thus does not have to be wired with pull up resistors The same applies to Port D2 XINTO Port D XWR and Port D7 XRD Notes The ports E F G and H are configured as input or output channels by the user program if the interface is set to I O BUSTYPE2 0o 1 7 3 1 Reset Phase of the C31 The reset phase of the C31 needs a minimum time span of 30 elementary periods The build up time of the PLL is at 200 us after the supply voltage and the external quartz have stabilized 7 3 1 1 Boot Type Setting In order to start the DPC31 the boot type has to be set Presently only Boot Type 2 is permissible BOOT TYPE Table 7 3 1 Boot Type Settings 7 3 1 2 Boot Type 2 Two variants are possible for Boot Type 2 1 The internal C31 core processes the program that is stored in the externally connected EPROM Port A D Ports E H are free and can be used for I O 2 The uP VO interface ports E H can be used for connection to an external uP system with EPROM or as I O channels Via the SPI interface an A D transformer and or an EPROM can be connected in addition DPC31 HW
122. t negative active The state of the C31 interrupt controller can be observed externally at this output In contrast to a normal C31 this pin can be used neither as an IO port nor as an interrupt input These interrupt registers assigned only to the C31 can be accessed by the C31 under the same addresses as the interrupt registers assigned to the host interface Only the interrupt outputs ports PG5 and PD2 are different 7 5 Serial PROFIBUS Interface 7 5 1 Asynchronous Physics Unit NRZ 7 5 1 1 Transmitter The transmitter converts the parallel data structure into a serial data stream The asynchronous UART process processes with a start bit and a stop bit that frame 9 information bits 8 data bits 1 even parity bit The start bit is always log 0 and the stop bit as well as the idle state are always log 1 The least significant bit is transmitted first The transmitter switches the request to send RTS active first After a minimum waiting time of 4 elementary periods at XCTS active it then starts the transmission process To connect a modem the XCTS input is available After RTS is active the transmitter must hold back the first message character until the modem activates XCTS During message transmission the transmitter no longer queries the XCTS When closing transmission the transmitter deactivates the RTS 7 5 1 2 Receiver The receiver converts the serial data stream into the parallel data structure It sca
123. t differs from 0 and gt 10 group generation Group_Ident the master address Master Add For messages that are longer than 7 net parameter data bytes the bits from the Spec_User_Prm_Byte are also accepted otherwise these bits are assigned default values The user indication New_Prm_Data is then triggered The acknowledgements User_Prm_OK cmd User_Prm_Not_OK cmd are read accesses to defined register cells with the corresponding messages Not_Allowed User_Prm_Finished or Prm_Conflict refer to Table 5 2 2 DPC31 HW Description Version V2 1 Page 37 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS User_Prm_OK Cmd Read Operation of ofotfoit o o UerAk User_Acko User_Ack o 00 User_Prm_Finished User_Ack o 01 Prm_Conflict User_Ack o 11 Not_Allowed User Ach o 10 not possible User_Prm_Not_OK Cmd Read Operation Fo fo fo fo fo a ser Ack User Acko E User_Ack o 00 User_Prm_Finished User_Ack o 01 Prm_Conflict User_Ack o 11 Not_Allowed User_Ack o 10 gt not possible Table 5 2 2 Coding of User Pm Not Ok Cmd 5 2 3 Check_Config Chk_Cfg SAP62 For this SAP two exchange buffers of the same length are allocated One buffer is integrated as the indication buffer MAC_Cfg buffer and the other is included as the User_Cfg buffer in DPS buffer management The indication is always transferred to the user in the User_Cfg buf
124. t_Ind_Resp_ Ind_Resp_B uffer_Ptr h Im Parameterregister ist das Bit En_LM_Val1 0 S Im Parameterregister ist das Bit En_LM_Val1 1 DPC31 HW Description Copyright Siemens AG 2004 All rights reserved Version V2 1 Timer _ High_Val InstQ_Rd Ptr MAC InstQ_Wr Ptr User Comment MAC enters Pas Idle MAC enters Offline Transfer of Troy Activate deactivate FDL_SAP New synchronization is enabled User initiates a Leave Master without Cfg_Fault User initiates a BitO 1 Leave Master with Cfg_Fault Bit0 0 Leave Master without Cfg_Fault User Confirmation of Stop_C1 Indication Set new station address Control of DPS User Watchdog Timer Change to an FDL Timer Activate deactivate internode communication Retrieve an Indication Response buffer Page 31 05 04 ComDeC DPC31 HW SI EMENS Table 5 1 2 Overview of User_MAC DPS Requests The FMA requeDXB SAP_Act Deact MAC_Stop and Get_Ind_Resp_Buffer are confirmed to the user after execution For this purpose an appropriate entry is made in the Indication_Queue Only one SAP_Act Deact Request and one Get_Ind_Resp_Buffer Request can be transferred each time A new SAP_Act Deact Request or Get_Ind_Resp_ Buffer Request is possible only after the corresponding confirmation With Stop_C1_Con the user acknowledges that the MSAC1S SAPS 50 52 are closed This enables a new opening entrance
125. ter 0835h Internal working area reserved 0844h 0845h 0846h Profibus station Address of the DPC31 this slave 0847h Real_No_Add_Change7 0 This parameter indicates whether the DP slave address may be changed at a later time After reset the slave firmware must set this parameter if it permits the Set_Slave_Address SAP 0 Address may be changed Otherwise Address may not be changed If the DPC31 then receives a Set_Slave_ Address message it enters the current value here 0848h 0849h Interframe GAP Times o The Interframe GAP time 4 32 bits is to be parameterized here for synchronous bus physics 084Ah DG User Wd Val In the DPS_Mode the user is monitored with an internal 16 bit watchdog timer The timer is decremented every 10 ms and must be reset by the user cyclically to the start value DPG User WD Value a Resetting enabling and disabling the timer is initiated with DPS_User Wd request in the Instruction Queue 084Bh DPS_User_Wd Val s s 084Ch Score_Registerz o Specification for the next WD cycle for monitoring the configured slave to slave connections 084Dh 084Eh Ident_Highz o DR Sue Group Clock Temp Base Prz o SAP_List Dese Pr SAP_SCB_Base Ptr7 o Segment address that points to the start of the SAP SCB system control block DPS_SAP_Start Ptr7 o Offset address that points to the start of the DPS SAPs being established by the DPC31 in the SAP SCB InstQ_Base Ptr7 o segment pointer to th
126. ter XRD Tor XWR T XRD XWR J to XRDY J normal Ready XRD XWR J to XRDY J early Ready XREADY hold time after XRD or XWR Data setup time to XWR T Data hold time after XWR T XWR Pulse Width XRD XWR cycle time last XRD J to XCS 4 XCS T to next XWR T XWR T to next XWR 7 XCS don t care Table 9 5 8 Timing Values in the Asynchronous Intel Mode Page 92 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC XRD XCS XREADY normal XREADY early XWR log 1 Figure 9 5 6 Asynchronous Intel Mode Processor Read Timing The Ready signal is generated by the DPC31 synchronously to the clock supplied and reset by the deactivation the Read or Write signal With XRD 1 the data bus is switched to Tristate XWR XCS XREADY normal XREADY early XRD log 1 Figure 9 5 7 Asynchronous Intel Mode Processor Write Timing 9 5 2 5 3 Synchronous Motorola Mode E_Clock mode for example 68HC1 1 If the DPC31 supplies the CPU with the clock the output clock has to be 4 times larger than the E CLOCK The DPC31 input clock CLK has to be at least 10 times larger than the desired system clock E_Clock Therefore the clock output CLKOUT1x4 that specifies the E_Clock of 3 MHz is to be used asyn physics The request for a read access to the DPC31 is generated from the rising edge of the E_Clock in addition XCS 0 R_W
127. th clock outputs can be switched off separately via Mode Register1 For asynchronous physics the DPC31 is wired to a quartz of 12MHz XTAL1_CLK XTAL2 An integrated PLL generates the internally needed work clock pulse 48MHz refer to Chapter 7 8 1 In the case of synchronous physics the DPC31 can be operated in a mode that is particularly low in power loss This can be achieved only Page 50 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC for low clock pulse rates The PLL is switched off in this case XPLLEN VDD and the variable supply clock pulse of 2 4 8 or 16 MHz is applied directly to XTAL1_CLK 7 1 1 Bus Interface Unit BIU The BIU is the interface to the connected processor microcontroller It allows the CPU accesses to the internal 5 5kByte dual port RAM and the registers It is a synchronous or asynchronous 8 Bit interface with a 13 Bit address bus The interface can be configured via 3 bus type pins BusType2 o refer to Table 7 1 1 With it the connected processor family Intel Motorola bus control signals such as XWR XRD and R_W the data format and the synchronous rigid or asynchronous bus timing is specified Figure 7 1 1 Figure 7 1 2 Figure 7 1 3 and Figure 7 1 4 show different Intel and Motorola system configurations In the C31 mode the internal address latch and the integrated decoder must be used In Figure 7 1 1 the minimum config
128. the DPC31 InstQ_Wr Ptr An Offset_Pointer which points to the next free entry and is managed by the user The queue is empty if InstQ_Wr ptr and InstQ_Rd ptr point to the same position One entry in the queue always must remain empty wildcard any content otherwise an empty queue can t be distinguished from a full queue The user must control the wrap in the queue After each entry the user places the InstQ_Wr pir behind this entry on the next free position If this is the end of the queue the InstW_Wr ptr will then have to be placed on the beginning of the queue wrap around Page 30 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SIEMENS DPC31 HW ComDeC InstQ_Base Ptr Command_Code Entry 1 Value1 Value2 Value3 Value4 Command_Code Value1 Value2 Value3 Value4 Adar Entry 2 Command_Code Value1 Value2 Value3 Value4 reserved reserved reserved reserved reserved Wildcard Figure 5 1 4 Organization of the Instruction _Queue Table 5 1 2 lists all possible requests the necessary command codes Request MAC_ Start MAC_Stop MAC_N EW Tops SAP_Act Deact En New GM Time Sync User_Leave Master User_Leave Master Bit 0 Cfg_Fault Bit 7 to 1 0 Stop_C1_Con Set_Addr DPS User Wd Station_Addr OOh reset 01h enable 02h disable FDL_Timer_ SAP_Nr Timer_ Change Control DDB_ OOh disable Enable Disable 01h EN_DP_DDB Ge
129. ther through a Write_Read_Data Frame Default_SAP a fail safe frame Default SAP or a Global_Control_Clear Frame SAP58 in Data_Exchange state the DX Out Interrupt is triggered after each of these frames provided it is enabled In addition the DX Entered interrupt is triggered with the first of these frames if diagnostic messages are no longer present This interrupt is only triggered again if the Data_Exchange state is left and then reachieved With the read operation User_Dout_Buffer state the user receives the current buffer assignment without initiating a buffer exchange User_New_Dout Cmd Read Operation o o o o U_Buffer_Cleared U_Buffer_State U_Buffer U_Buffero U_Bufferi 0 00 Buffer4 U_Buffer o 01 Buffer1 U_Bufferi o 10 Buffer2 U_Bufferi o 11 Buffer3 U_Buffer_State 0 gt no new U_Buffer U_Buffer_State 1 gt new U_Buffer U_Buffer_Cleared 0 received data U_Buffer_Cleared 1 gt substitute values User_Dout_Buffer State Read Operation F_Buffer FE Buffer LU Butter U_Buffero N_ Buffer N_Buffero D Butter D Butter PN Butter o 00 gt Nil F N Buffer o 01 gt Buffer F N Buffer o 10 Buffer F N Buffer o 11 Buffer U Buffer o 00 gt Buffer4 U Buffer o 01 gt Buffer U Buffer o 10 Buffer U Buffer o 11 gt Buffer3 D Buffer o 00 not possible D Buffer o 01 Buffer D Buffer o 10 gt Buffer2 D Buffer o
130. tput is low active Interrupt Request Register IRR writable readable IndQ_Full IndQ_Entry Ignore Del Delay_Time Diag_ WD Gate Timer_Overr r_Overrun Fetched Changed un 0 Get_Cfg_ New_Cfg New_DDB New_Prm New_SSA Butter Data Pm Data Data Data Changed 8 New GC Go Leave_ Command Data_ Exchange 7 DX_OUT_ DX_OUT Overflow 15 Diag_ Buffer_ Changed DXB7_OUT DXB6_OUT DXB5_OUT DXB4 OUT DXB3_OUT DXB4_OUT DXB1_OUT DXBO_OUT 16 23 DPC31 HW Description Version V2 1 Copyright Siemens AG 2004 All rights reserved Page 57 05 04 ComDeC WD_State_Changed Diag_Fetched Delay_Timer Overrun Ignore_Del_Timer Overrun IndQ_Entry IndQ_Full Go Leave_Data_Exchange New_GC_Command New_SSA_Data New_Prm_Data New_DDB_Prm_Data New_Cfg_Data Get_Cfg_Buffer_Changed Diag_Buffer_Changed DX_OUT DX_OUT_Overflow DXBO 7_OUT DXB_Error RAM_Access_Violation SSC_Interface GC_Clock DX Entered After reset the IR is cleared Page 58 05 04 DX Entered GC_Clock SSC_ Interface 28 SIEMENS RAM _ DPC31 HW DXB_Error Access _ Violation 24 The state of the WD_SM has changed change between Baud_Search Baud_Control or DP_Control The master fetched the diagnostic buffer The delay timer has expired and has been started over The time of day synchronization has been aborted External Del Timer Overrun Timer must be
131. tup time to AS 4 0 ns 61 AS J to Data valid access to RAM AS J to Data valid access to the registers 62 Address AB al hold time after AS T 63 R_W J setup time to AS 1 64 AS Pulse Width 65 Data hold time after AS T 66 AS inactive time 67 R_W hold time after AST 68 XCS J setup time to AS 69 XCS hold time after AST 70 AS J to XDSACK J standard Ready 71 AS J to XDSACK J early Ready 72 XDSACK hold time after AS T 73 AS cycle time 74 Data setup time to AS T 75 Data hold time after AS T 76 AS Pulse Width 77 last AS J Read to XCS J 78 XCST to next AS T Write 79 AS to next AS Write XCS don t care Table 9 5 10 Timing Values for the Asynchronous Motorola Mode DPC31 HW Description Version V2 1 Page 95 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS XCS XDSACK normal XDSACK early E_Clock log 0 Figure 9 5 10 Asynchronous Motorola Mode Processor Read Timing The Ready signal XDSACK is generated by the DPC31 synchronously to the supplied clock pulse and it is reset with the deactivation of the AS signal AS 1 switches the data bus to Tristate AB 12 0 e I D As Lo d ok Gemen e gt VE XCS G e Fa Ei e normal e QJ a NE early O E_Clock log 0 Figure 9 5 11 Asynchronous Motorola Mode Processor Write Timing Page 96 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004
132. uffer Empty enters inactive As soon as the transmit shift register is free the data byte is DPC31 HW Description Version V2 1 Page 59 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC DPC31 HW SI EMENS transferred there and shifted out The clock SSCLK is generated only as long as the shift process is running During continuous sending the user always writes the next data byte to the transmit buffer while one is being shifted out In the receiver the arriving bits are shifted to the Receiver Shift Register After 8 data bits have been received or 9 bits with enabled parity this data byte is accepted in the receive buffer and Receive Buffer Full is generated This state can be polled via the status register or it can be activated as SSC _Interface interrupt if there is a corresponding enable in the Interrupt Enable Register If there is continuous receiving the user reads a data byte from the receive buffer while the next one is arriving at the receiver shift register Error states Receive Buffer Overflow RECERR or Parity Error PERR can be polled in the status register or can be generated as SSC_Interface interrupt enable in the Interrupt Enable Register Because of the full duplex channel in the SSC module it can receive while it is sending However the protocols process only half duplex SPI E PROM etc For that reason the received data is to be ignored disable the corresponding interrupts The last received d
133. unt H L is always transferred with this request The FDL_Timebase Timer is an internal free running counter that generates an interrupt after every time interval 10 ms All FDL SAPs are then scanned and the enabled FDL_Monitoring timer is decremented Only SAPs 0 54d are considered 5 3 2 Time of Day Synchronization Figure 5 3 1 presents the main sequence However this service is only enabled with En_Clock_Sync 1 in the Param Register Otherwise the SM_Time0 1 frames are filtered by the MAC Time of Day Time of Day eg DPC31 Sender Receiver SM2_SYNC_LINK req Send Time Generate Time message message 0 Recei ve Ti me SM2_TIMEO req First message Transfer Ti me message SM2_TIMEO con SYN S_UNK TIME B A Detect Time message 0 Start Receive Delay Timer RD1 M2_TIME1 ma e Store SM2_Time0 remadr Erzeuge time message Send Time message 1 Time A SYNC_LINK_T IME A B A B Die Zeit ist die Sendedauer seit dem letzten Bit der vorherig Second Transfer Time time mess age m Receive Ti me SM2_TIME1 con message Store SM2_Time1 remadr If SM2_Time0 remadr E SM2_Time 1 remadr then SM2_TIME1 ind Formel f r Time Ab solute T A Detect Time mess age t TA Time in Time message Receive Delay RD1 Read RD1 F B B F B F Calc Time Abs ol TA Figure 5 3 1 Sequence of Time of Day Synchronization A time of day master first sends the SM2_Time0 frame broadcast FC 40h If the SM_T
134. uration of a system with external uP and DPC31 is shown the chip is connected to an EPROM version of the controller In terms of additional components only a quartz crystal is needed in this configuration If a controller is to be used without integrated program memory the addresses have to be latched additionally for the external memory refer to Figure 7 1 2 The connection diagram in Figure 7 1 3 applies to all Intel Siemens processors that offer asynchronous bus timing and interpret the Ready signal Notes If the DPC31 is connected to an 80286 or something similar it is to be taken into account that the processor accesses words that is either a swapper is needed that switches during reading the corresponding characters from the DPC31 to the corresponding byte position of the 16 Bit data bus Otherwise the least significant address bit is not connected and the 80286 must make word accesses and correspondingly only interpret the lower byte as shown in Figure 7 1 3 Wiring of the C31 Core Port Pins for Unused C31 Core Set the pin DBX to VDD then the internal C31 is in permanent reset Ports A B C and D except for port D 2 must each be wired with a pull up resistor DPC31 HW Description Version V2 1 Page 51 Copyright Siemens AG 2004 All rights reserved 05 04 ComDeC BusTypez o 01 1 synchronous Motorola 010 asynchronous Motorola 001 synchronous Intel 000 asynchronous Intel SIEMENS The D
135. us register GC_Command Score_Register etc The buffer pointers describe the entire buffer management for the SAPs At address 08A0h the buffers generated by the user start corresponding to the parameter assignment of the organizational parameters The sequence of the buffers can be selected as required All buffers or liDXB must be located on segment addresses 32 bytes segmentation 1FFFh Code Area for the Internal C31 Communic Buffer Area ation Area 08A0h Organizational 0840h Parameters 0800h Internal Work Area ecw Ct Control Unit Parameters 0000h ew Latches Registers Table 3 1 1 Memory Area Distribution in the Internal RAM of the DPC31 The stack for the sequential control system needs 64 bytes A buffer for temporarily storing the receive message requires 32 bytes 3 2 Control Unit Parameters Latches Registers The register cells that are for example in the interrupt controller and the DPS control units are located in the address area of 0000 0044h XDATA These cells can either be read or written only The address assignments are shown in Table 3 2 1 When writing the register cells the unassigned bit positions are don t care Page 12 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC Address Meaning read access Interrupt Controller Register Int Req Regpes 24 0004h Int Reg7 o 0005h 0006h 0007h Int Reges 24 P
136. ve remains in the DATA_Exchange mode Page 78 Version V2 1 DPC31 HW Description 05 04 Copyright Siemens AG 2004 All rights reserved SI EMENS DPC31 HW ComDeC 7 7 3 Response Monitoring The DP_Control mode is used for response monitoring of the DP master Master Add The set monitoring time is the result of multiplying both watchdog factors and then multiplying by the time base valid at the moment 1 ms or 10 ms Twp 1 ms or 10 ms WD_Fact_1 WD_Fact_2 refer to Byte 7 of the parameter assignment message The two watchdog factors WD_Fact_1 WD_Fact_2 and the time base that represent a value for the monitoring time can be loaded by the user with the Set_Param message with any value between 1 and 255 Exception the setting WD_Fact_1 WD_Fact_2 1 is not permissible This setting is not checked by the circuit With the permissible watchdog factors monitoring timing between 2 ms and 650s can thus be implemented regardless of the baud rate If the monitoring time expires the DPC31 reenters Baud_Control and the DPC31 generates the WD_DP_Control_Timeout interrupt In addition the state machine is reset that is the reset modes of buffer management are generated If another master takes over the DPC31 it either switches to Baud_Control WD_On 0 or it remains in DP_Control WD_On 1 depending on the enabled response monitoring 7 8 Clock Supply 7 8 1 PLL In the asynchronous mode
137. y the user and retransferred to the software modules MAC and DPS after every restart caused by a voltage failure for example If the DPC31 receives a Set_Slave_Address message and if the SAP55 is enabled the MAC first checks whether the indication buffer has the corresponding size If not the MAC responds with No Resource Otherwise it sends a short acknowledgement and after the send process transfers this buffer to the DPS module The MAC has already accepted the new station address however Byte Name 0 5 Buffer Header 6 New_Slave_Address 7 Ident_Number_High 8 Ident_Number_Low 9 No_Add_Change 10 249 Rem_Slave Data Figure 5 2 2 Assignment in the Data Field of the SSA Indication Buffer In the following states the DPS module ignores the SSA indication e DP GM mode Wait_Cfg Data_Exchange Net data length less than 4 bytes Parameter PHeal No Add Change is True FFh New station address is larger than 125 Ident No is wrong User_SSA_OK Cmd Read Operation Po o oo fo fo fo UserAk JL User Acko User_Acki 9 00 gt User_SSA_Finished User_Ack o 01 SSA_Conflict User_Ack o 11 Not_Allowed User Ach o 10 not possible Table 5 2 1 Coding of User SSA_OK Cmd The acknowledgement User_SSA_OK Cmd is a read access to a register cell with the corresponding codes Not_Allowed User_SSA_Finished or SSA_Contflict The SSA_State_Machine is reset also wh

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