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how to use ddr sdram um - Electrical and Computer Engineering

1. 15 Differences in Command Skai eoi ccce dece tec e e eee e EE Rus 16 Address Pins of 128M bit DDR 5 2 0 20000 000 ennt 23 Bank Address and Selected Bank nennen nennen nennen nennen 23 128M bit DDR SDRAM x4 x8 x16 bit Organization Command 31 Access Time of DDR SDRAM SDR SDRAM and EDO 38 128M bit DDR SDRAM x4 x8 x16 bit Organization Command Truth 51 Command Executable 0 0 entrer nnns 52 AC Characteristics of Data Strobe Signal and Output Data in Read 68 AC Characteristics of Data Strobe Signal and Output Data in Read 69 AC Characteristics of Data Strobe Signal Read Preamble and Read Postamble 70 AC Characteristics of DQ DM in Write Cycle nene rennen nennen nnne 72 AC Characteristics of Data Strobe Signal Write Preamble and Write 73 DQ Write Mask Enable Signal Truth Table sssssssssseseeeneenenenneeenneenneee nennen nnne nnns 75 User s Manual E0234E30 Ver 3 0 9 CHA
2. ennt nnns 51 7 1 DDR SDRAM Command Truth Table sessssssssssseseeeeeeeee nennen nenne 51 7 2 Gommand Execution Conditions 2 no i dine NARRA 52 7 3 Command Operation of 128M bit DDR SDRAM 1216 53 CHAPTER 8 BASIG OPERATION MOBDES 2 eco RO EGO t eO HRS 59 Sul Read Mode tiU e tie Het o e elie eel 59 8 2 WEMAS m 62 8 3 Refresh Mode ne a Ted Let ee ER eee ad 64 User s Manual E0234E30 Ver 3 0 5 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL 65 9 1 Data Strobe Signal DOS d dete eter cer te E bee DU e dc E E ure p AA earns lee 65 9 1 1 Data strobe signal DQS in read eene nnne nnn 66 9 1 2 Data strobe signal DQS in write cycle sssssseseseeeeneeneneeneee nnnm 67 9 2 Relationship between Data Strobe Signal DQS Output Data DQ and Clock CK CK during Read Cycle occire diiit e i nnne nnne reset niaaa 68 9 3 Relationship between Data Strobe Signal DQS and Output Data DQ in Read Cycle 69 9 4 Data Strobe Signal DQS Read Preamble and Read Postamble 70 9 5 Relationship between Data Strobe Signal DQS and Input Data D
3. 46 CHAPTER 6 SIMPLIFIED STATE DIAGRAM sssseeeeeneeneeeneee nennen nenne nnne nennt rese nnns tres eterne nennen 47 6 1 Simplified State Diagram of DDR 5 4 4 12000420000 47 6 2 Gurrent State Definition recen etude e LE e cR T arre a Pe Pec oe det 49 6 271 E M M 49 6 2 2 Bank activating Row 49 6 2 3 Bank active BANK ACTIVE Row active ssessssssssseeeeeeneennenneeen nennen nnne nene nennen nnne 49 6 2 4 Prechiarge s ete e e edo lr dct t 49 6 2 5 Read and write READ 22044 4 0 00 600 enne nnne nenne nnn estne n resin nnne nnns ennt nnne nns 49 6 2 6 Read and write with auto precharge READA 49 0 2 7 Mode register Set oio ete dee e EHE RE ORG ER AERE 49 6 2 8 CBR Auto reftesh i gn ERE he e dtc e ERE A E Ded E es 49 6 2 9 Selt IIR 4 eatin ten 50 6 2 10 gt 5 50 6 2 11 ade 50 CHAPTER 7 COMMAND
4. sessssssssssssesseeeeeeneenenen nennen nennen 11 1 1 1 Data transfer frequency data 4222 12 1 1 2 Clock input uiuere ede ee ba ton ege ee meus 13 11 3 Data strobe signal DQS ite teh de a mee etd n cibo es nied 13 1 4 Interface ir bee eroe D 14 1 1 5 Power supply uito tette eig et matt utet tulo 15 1 1 6 CAS read latency CAS write latency burst length and burst sequence 15 Tz Use of DEL s iiio eee I ec A UE e eL eben pee FU Pe ate ee 15 TES Data mask aeo eet e Ra taies ale e p et 15 1 2 Differences in Comimands z inui et 16 1 21 Clockisuspend aia ed rc ette ete tp i es sles De dE e Ee De ce UE 16 1 2 2 F l page coe e o ette co d o eme e idus rto d cs 16 1 2 3 Burststop ee REOR RM RM RON ORA MSAN 16 1 2 4 Single write after H rstreadt cei due band iterat Re Ree Lr e Ee Eon death dee Enn 16 1 3 Differences in Operation Timing oorr qr em tei Eee asl 17 CHAPTER 2 PRODUCT OUTLINE s Rn s E C Ce eps 19 24 Pin Gonflg ratlons doceo eet dine D aiii OR
5. Mode MRS EMRS REF Register Set gt CBR auto Refresh tMRD Pw D gt N S P d NS 4 Bank Activating Down x 908 amp 11 READA ES READA amp 5 Y S i 5 amp S M PRE PALL i Precharge POWER Y 1 Automatic sequence Manual input User s Manual E0234E30 Ver 3 0 CHAPTER 6 SIMPLIFIED STATE DIAGRAM 6 2 Current State Definition 6 2 1 Idle IDLE The state in which the bank has been precharged and tre has been satisfied The bank active command ACT mode register set command MRS EMRS and refresh command REF SELF may only be issued when the device or the bank to be selected is in the idle state 6 2 2 Bank activating Row activating For an operation read or write for a particular row in a particular bank the bank has to be activated first to receive an operation request read or write command Bank activating is the state in which the bank active command ACT has been issued but trcp has not been satisfied The device automatically changes states from bank activating to bank active when taco is satisfied 6 2 3 Bank active BANK ACTIVE Row active When troop is satisfied bank active the device is ready to receive an operation request read or write command 6 2 4 Precharge When current operation read or writ
6. AO to 12 BAO 1 DQO to DQx DQS LDQS UDQS DM LDM UDM Vss VDDQ VssQ VREF NC Remark xxx indicates active low signal User s Manual 0234 30 Ver 3 0 Clock inputs Clock enable input Chip select input Row address strobe input Column address strobe input Write enable input Address inputs Bank address inputs Data inputs outputs Date strobe inputs outputs DQ write mask enable inputs Power supply for the intermal circuit Ground for the intemal circuit DQ power supply DQ ground Referential voltage No connection 21 CHAPTER 2 PRODUCT OUTLINE 2 2 Pin Functions This section explains the pin functions of DDR SDRAM 2 2 1 Clock input CK CK Clock input CK CK for memory operation CK has the same period but the reverse phase of CK All input signals except data input output DQ data strobe DQS and DQ write mask enable DM are synchronized with the rising edge of CK The intersection of CK and CK is used as the reference timing for input output 2 2 2 Clock enable input The clock enable signal CKE determines whether the clock Ck is valid or not If CKE is high at the rising edge of a given CK the next rising edge of CK is valid Otherwise the next rising edge of CK is invalid 1 Self refresh mode When the device is in the idle state self refresh mode is set by issuing the self refresh command CKE is low
7. High level L Low level High or low level Don t care Illegal Device operation and or data integrity are not guaranteed Current state Power down CS RAS CAS Address Command Action Note ilegal Impossible Impossible PDEX Ext power down le state eee Remark High level L Low level x High or low level Don t care Illegal Device operation and or data integrity are not guaranteed 80 User s Manual E0234E30 Ver 3 0 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION Current state All banks idle CS RAS CAS WE Address Command Action Note n w Pepe pete pe room eran comma orcas x Pwon Porrdwneny Note nc Cope pepe pe 89g jme PT RD b OL dem S S Note Self refresh can be entered only from the all banks idle state Power down can be entered only from the all banks idle or row active state Remark High level L Low level x High or low level Don t care V Valid data Illegal Device operation and or data integrity are not guaranteed Current state Row active CS RAS CAS WE Address Command Action Note D DEL eeesmerenz es Remark High level L Low level x High or low level Don t care V Valid data Current state Other than above
8. 2 Illegal for the same bank these commands may be valid depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed 54 User s Manual E0234E30 Ver 3 0 CHAPTER 7 COMMAND OPERATIONS Current state Read with auto precharge No operation T _ _ wamama ber e for the same bank these commands be valid depending the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed Current state Write with auto precharge xs moe Nooperaton ie atertny i S ma amm mm ma enr LL Note Illegal for the same bank these commands be valid depending on the state of the bank specified by the bank addresses BAO 1 Remark Illegal Device operation and or data integrity are not guaranteed User s Manual E0234E30 Ver 3 0 55 CHAPTER 7 COMMAND OPERATIONS Current state Precharge pes _ oe Nei m pa ee C Notes 1 Illegal for the same bank these comma
9. In this mode CKE must be kept low For details about self refresh mode control by CKE refer to 11 2 3 Clock enable signal CKE command truth table 128M bit DDR SDRAM EDD1216ALTA 2 Power down mode When the device is in the idle or bank active state power down mode is set by setting CKE low In this mode CKE must be kept low As refresh is not performed automatically in power down mode the power down mode period needs to be shorter than the device refresh cycle For details about power down mode control by CKE refer to 11 2 3 Clock enable signal CKE command truth table 128M bit DDR SDRAM EDD1216ALTA 2 2 3 Chip select input CS When the chip select CS is low command input is valid When CS is high commands are ignored but the operation continues 2 2 4 Row address strobe input RAS Column address strobe input CAS Write enable input WE The row address strobe RAS column address strobe CAS and write enable WE functions are same as those used for SDR SDRAM Each combination of RAS CAS and WE in conjunction with chip select CS at the rising edge of the clock CK determines the DDR SDRAM operation For details refer to 7 1 DDR SDRAM Command Truth Table 22 User s Manual E0234E30 Ver 3 0 CHAPTER 2 PRODUCT OUTLINE 2 2 5 Address input 0 to Ax 1 Row address Determined by addresses 0 to Ax when an active command is issued 2 Column address Determined by addresses 0 to
10. when a read or write command is issued 3 Precharge mode select address AP The function differs depending on the input level of the precharge mode select pin AP when a precharge or read write command is issued When precharge command is issued E O e High level Precharge all banks Precharge only one bank selected by bank addresses 0 BA1 When read write command is issued High level Auto precharge after read write burst Low level Precharge command is necessary to start precharge Table 2 1 Address Pins of 128M bit DDR SDRAM Part Number Organization Address Row Column AP words x bits x banks Pins Address Address EDD1204ALTA 8 4 4 0 11 0 11 A9 A11 EDD1208ALTA 4M x8x4 AO A11 AO A11 AO A9 EDD1216ALTA 2M x 16 x 4 AO 11 AO 11 AO A8 2 2 6 Bank Address input BAO 1 The bank to be selected differs depending on the input level of the bank addresses BAO BA1 when a command is input Read write or precharge is applied to the bank selected by BAO and 1 Table 2 2 Bank Address and Selected Bank User s Manual E0234E30 Ver 3 0 23 CHAPTER 2 PRODUCT OUTLINE 2 2 7 Data input output 000 to DQx The data input output DQO to DQx functions are the same as those used for SDR SDRAM 2 2 8 Data strobe input output DQS LDQS UDQS Data strobe signals DQS LDQS UDQS are used to control the I O buffer All data input outputs are synchronized with the
11. CS RAS CAS Address Command Action Note p DD eeessmeren commana orenarions apee o enm Remark High level L Low level x High or low level Don t care V Valid data Illegal Device operation and or data integrity are not guaranteed User s Manual E0234E30 Ver 3 0 81 CHAPTER 12 BURST OPERATION This chapter explains the burst operation 12 1 Terminating Burst Operation The burst operation can be terminated in the following ways 1 By using read command READ 2 By using write command WRIT 3 By using burst stop command BST 4 By using precharge command PRE 12 1 1 Data interrupt by read command 1 Read cycle The preceding burst read operation can be aborted by inputting a new read command READ b The data for the new read command is output after the lapse of the CAS latency Figure 12 1 Read Read Command Command DQS Remark CL CAS latency BL Burst length 82 User s Manual E0234E30 Ver 3 0 CHAPTER 12 BURST OPERATION 2 Write cycle The preceding burst write operation can be aborted by inputting a read command READ a In the case where the write to read command interval is 1 clock cycle all the write data is masked by the read command In the case where the write to read command interval is greater than 1 clock cycle DQ write mask enable DM must be used to mask the last two input data which precede the read comman
12. DDR SDRAM Write Cycle Timing i n n Command WRIT 1 1 1 DQS Remark BL Burst length User s Manual E0234E30 Ver 3 0 29 CHAPTER 3 PRODUCT FEATURES 3 2 Command Control Similar to SDR SDRAM DDR SDRAM is controlled by commands combinations of logic levels of control signals Typical commands include the active command read command write command and precharge command For further details about the commands of the 128M bit DDR SDRAM refer to CHAPTER 7 COMMAND OPERATIONS 3 2 1 Command input timing All the commands are latched in synchronization at the intersection of the rising edge of the clock CK and the falling edge of the clock CK A clock enable signal is provided as a signal to activate the clock To input command at the rising edge of CK n CKE must be high 1 cycle before the command input high at CK n 1 Figure 3 3 Command Input Timing ICK CK CKE Contril Signals 30 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES 3 2 2 DDR SDRAM command table The commands of 128M bit DDR SDRAM are listed below Table 3 1 128M bit DDR SDRAM x4 x8 x16 bit Organization Command List Bank active ACT Open or activate a row in a particular bank for a subsequent access 000 CBR auto refresh REF Start CBR auto refresh Remark Each operation is valid when the current state satisfies the command execution conditi
13. 20 2 2 PIM Functions a a euet estende 22 2 2 1 Olockinput ACK us iue coe oh a erede cei DER bred cina 22 222 Glock enable input ERE P RT Utt D ERE 22 2 2 3 Ghip select input CS eee ie e d e eR E rela i et fe 22 2 2 4 Row address strobe input RAS Column address strobe input CAS Write enable input WE 22 2 2 5 Address input 0 to 23 2 2 6 Bank Address input BAO 23 2 277 Datainput output DQO to naa acted ped Unete ne 24 2 2 8 Data strobe input output DQS LDQS UDQJS sssesssssseeeeneeeeen nennen nnne nnne nnne 24 2 2 9 DQ write mask enable input DM LDM 24 2 2 10 Power supply for the internal circuit 24 2 2 11 Power supply for DQ VDDQ 0 04 4 0 a e nter a a E e 24 2 27 12 Referential Voltage 5 pei eh b eei ite Aedes A ey d 24 2 3 Block Diagraman ddp EE EE 25 2 3 1 Memory cell array of 128M bit DDR SDRAM 1216 26 2 3 2 Address decoder Row address decoder Column address decoder 2 27 2 9 3 J Q D ffer nee ne nee a dele i ee Ee Rete deos 27 2 3 4 Refresh COUnter s si o ice eo Eco m d ede t 27 2 3 9 DEE Delay Lock
14. 4 Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 60 CHAPTER 8 BASIC OPERATION MODES Figure 8 2 shows the read cycle with auto precharge READA In this cycle it is not necessary to input the precharge command PRE because precharge starts automatically When using auto precharge in the read cycle it is necessary to know when the precharge operation starts in order to satisfy tras and tae The next bank active command ACT for the bank cannot be issued until the auto precharge cycle is completed until tre is satisfied Auto precharge will start after the lapse of burst length 2 clocks from the READA command Caution The auto precharge start timing may differ depending on the DDR SDRAM product For details refer to the data sheet of each product Figure 8 2 Read Cycle with Auto Precharge CL 2 Command ACT i Hi Z EE Bg ene CL 2 5 Hi Z jp Auto precharge starts Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 61 CHAPTER 8 BASIC OPERATION MODES 8 2 Write Mode A write operation is executed by issuing the write command WRIT for an active bank The write operation sequence is as follows 1 To activate a particular row in a particular bank the bank active command ACT is issued along with a row address and bank address 2 A
15. Strobe Signal Write Preamble and Write Postamble BL 4 ICK CK Command twPRE twPST DQS preamble postamble Remark CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 73 CHAPTER 10 DQ WRITE MASK ENABLE SIGNAL DM CONTROL OPERATION This chapter describes DQ write mask enable signal DM control DM masks input data Unlike SDR SDRAM data masking is only available in the write cycle for DDR SDRAM The burst stop command BST is available during burst read but burst stop during write is illegal Data masking is available during write but data masking during read is not available 10 1 DQ Write Mask Enable Signal DM DQ pins controlled by the DQ write mask enable signal DM differ depending on the bit organization 1 x4 bit organization DM controls DQO through 2 x8 bit organization DM controls DQO through DQ7 3 x16 bit organization LDM controls through DQ7 lower bit control UDM controls DQ8 through DQ15 upper bit control 74 User s Manual E0234E30 Ver 3 0 CHAPTER 10 DQ WRITE MASK ENABLE SIGNAL DM CONTROL OPERATION 10 2 DQ Write Mask Enable Signal DM Control in Write Cycle The DM latency in the write cycle is O regardless of the CAS latency As shown in Figure 10 2 write data is masked when the corresponding DQ write mask enable signal DM is high Figure 10 1 DQ Write Mask Enable Signal Control during Write Cycle
16. rising and falling edges of these signals x16 bit products use LDQS and UDQS for the lower byte and upper byte respectively 2 2 9 DQ write mask enable input DM LDM UDM DQ write mask enable signals DM LDM UDM mask write data at both the rising and falling edges of the data strobe signal DQS For x16 bit products LDM and UDM are used to control the lower byte and upper byte respectively If DM is high during a write operation write data is masked Unlike the DQ mask enable signal used for SDR SDRAM these signals are not used to control read operations 2 2 10 Power supply for the internal circuit Vss and Vss are power supply pins for the internal circuit 2 2 11 Power supply for DQ VDDQ VssQ VppQ and VssQ are power supply pins for the I O buffer 2 2 12 Referential voltage VREF Vner is the reference voltage supply for the SSTL_2 interface 24 User s Manual E0234E30 Ver 3 0 CHAPTER 2 PRODUCT OUTLINE 2 3 Block Diagram Following figure shows the block diagram of 128M bit DDR SDRAM EDD1216ALTA Figure 2 3 Block Diagram of 128M bit DDR SDRAM EDD1216ALTA Row Address AO to A11 BAO BA1 Buffer and Refresh Mode Register Counter CS o Sense Amplifier RAS Column Control 2 d CAS O Decoder Logic Column Decoder ANE po Address Buffer and Burst Counter DQS 25 User s Manual E0234E30 Ver 3 0 CHAPTER 2 PRODUCT OUTLI
17. with auto precharge es NewemmWemend No operation de ators uomwm 1 wammm mm ma cma 71 m Note Illegal for the same bank these commands be valid depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed User s Manual E0234E30 Ver 3 0 57 CHAPTER 7 COMMAND OPERATIONS Current state Refresh mo Noperaton eateries S Noopeaton ite wi her Notes 1 Illegal for the same bank these commands be valid depending on the state of the bank specified by the bank addresses BAO BA1 2 Precharge may be enabled depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed Current state Mode register set 58 DESL No operation Idle after turp Po READ WRIT ACT REF SELF MRS EMRS Note Illegal for the same bank these commands be valid depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed User s Manual 0234 30 Ver 3 0 CHAPTER 8 BASIC OPERATION MODES This chapter describes the three basic operation modes of DDR SDRAM R
18. with the rising and falling edges of the data strobe signal DQS The valid data window is affected by DQS DQ skew Timing specifications and examples for DQ vs DQS are shown below Table 9 2 AC Characteristics of Data Strobe Signal and Output Data in Read Cycle DQ output hold time from DQS tHP 0 75 me Remark thr tcu MIN Figure 9 5 Data Strobe Signal and Output Data in Read Cycle tcH CL 2 5 Remark CL CAS latency User s Manual E0234E30 Ver 3 0 69 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 4 Data Strobe Signal DQS Read Preamble and Read Postamble The data strobe pattern for a read operation consists of preamble toggling and postamble portions When DDR SDRAM receives the read command READ in the bank active state the data strobe signal DQS changes from the high impedance state to low level This is the read preamble portion The read preamble occurs approximately 1 clock prior to the first data output Following the read preamble the strobes will toggle at the same frequency as the clock signal while data is present on the data input output pin DQ The low time following the last data transition is known as the read postamble The read postamble occurs approximately 1 2 clock from the last data edge When a burst read is completed and another new burst read is expected to follow read to read data bus transition a read postamble and preamble are not r
19. write while burst read burst write for different bank is in progress Current State Bank X Next Operation Bank Y 2 Activate and burst read burst write while burst read burst write for different bank is in progress 3 Burst read burst write while burst read burst write with auto precharge for different bank is in progress Current State Bank X Next Operation Bank Y Burst read with auto precharge Completed Interrupted Burst read with auto precharge Completed Interrupted Burst write with auto precharge Completed Interrupted Burst write with auto precharge Completed Interrupted Caution For the detailed timing charts of the operations described above sections 1 2 and 3 refer to SDR SDRAM User s Manual All the examples for SDR SDRAM are same as for DDR SDRAM except CAS latency and write latency User s Manual E0234E30 Ver 3 0 33 CHAPTER 3 PRODUCT FEATURES 3 4 Burst Operation Since DDR SDRAM performs pipelined processing internally like SDR SDRAM it can successively input output a fixed number of data in synchronization with an external clock In pipelined architecture operations from column address input to data input output are divided into several processing blocks each block operating in parallel to boost the transfer capability Burst transfer in EDO DRAM SDR SDRAM and DDR SDRAM is explained below using the read cycle as an example 1 EDO DRAM The next read operation has to wait until a ser
20. 0234 30 Ver 3 0 7 6 5 4 3 2 1 0 CHAPTER 5 MODE REGISTER SET 3 CAS latency The CAS latency is the number of clocks required between a read command READ and the first data output The value of CAS latency is limited by the operating frequency and speed grade of DDR SDRAM A CAS latency of 2 or 2 5 is available for DDR SDRAM Figure 5 4 Timing Differences between CAS Latency 2 and 2 5 Command pag ee sede debe REL Hi Z pee Se ae Remark CAS latency 4 Option Addresses A7 and A9 through 11 are used for the option fields of the mode register set command 5 DLL reset Address A8 is used to reset DLL when the mode register set command is input 6 Extended mode register set If the bank addresses BAO 1 1 0 when the mode register is set the device enters the extended mode register set cycle DLL is enabled disabled according to the information of address AO during the cycle Although DLL is usually enabled disabling DLL in the power down mode reduces the power consumption of the device 7 Option Addresses A1 through A11 are used for the option fields of the extended mode register set command User s Manual E0234E30 Ver 3 0 45 CHAPTER 5 MODE REGISTER SET 5 3 Mode Register and Extended Mode Register Fields with 128M bit DDR SDRAM To set the burst length burst sequence and CAS latency using the mode register set co
21. 2 2 22 4 40 000 75 Signal Input Timing Controlled by Clock Enable Signal 76 Example of Clock Enable Signal 77 Power Down eie oe dh eine coe 78 Refresh Mode ie eate ed eie et aam tem ense di ee s 79 Read R ad Command is scot Macca deter el ee ee ed ed ann ees 82 Rp CR ERR edi ee 83 Write Write eite ie dette eene aded 84 Read Burst Stop Write 224 44 1 eene enne einn nnn ennt nnne nennt rn 85 Read Burst Stop Commarid n ee a eee tee e e d eio d e Ere do ade 86 Read Precharge Commana senisesse ie ei n n eee e ed crea ctt 87 Wiite PrechargeGommiand iiiter 88 User s Manual 0234 30 Ver 3 0 Table Table 1 1 Table 1 2 Table 1 3 Table 2 1 Table 2 2 Table 3 1 Table 3 2 Table 7 1 Table 7 2 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 10 1 LIST OF TABLES Title Page Differences in Functions and Specifications cccecceeeceeeseseneeeeeeeeeeeeeeeeceeeeeeeseaeeseaeeeaeeseaeeeeeeseneeeseeeeeaees 11 55 _2
22. 28M bit DDR SDRAM 2M words x 16 bits x 4 banks as an example Unless otherwise specified all the examples use EDD1216ALTA throughout this manual User s Manual E0234E30 Ver 3 0 19 CHAPTER 2 PRODUCT OUTLINE 2 1 Pin Configurations This section shows the pin configurations and the pin names of the 128M bit 256M bit and 512M bit DDR SDRAM Figure 2 1 Pin Configuration of 128M bit DDR SDRAM 2 OANDARWNAO x4 128M bits x8 128M bits x16 128M bits CK CK Clock inputs CKE Clock enable input ICS Chip select input RAS Row address strobe input ICAS Column address strobe input Write enable input AO to A11 Address inputs BAO BA1 Bank address inputs DQO to DQx Data inputs outputs DQS LDQS UDQS Date strobe inputs outputs DM LDM UDM DQ write mask enable inputs VDD Power supply for the intermal circuit Vss Ground for the intemal circuit VDDQ DQ power supply VssQ DQ ground VREF Referential voltage NC No connection Remark xxx indicates active low signal 20 User s Manual 0234 30 Ver 3 0 CHAPTER 2 PRODUCT OUTLINE Figure 2 2 Pin Configuration of 256M 512M bit DDR SDRAM amp ee x NON 4 256 512 bits x8 256 512 bits x16 256M 512M bits CK CK CKE 5 RAS 5
23. CK CK Command 1 1 OR KIRSS 5 ean BRK RRR KK KKK KR RR KK KKK KRY 555665556655 665555655566 65555 A NN YN ee Bais atts pe E Cu pao DaDa Da3 gt E DM Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 85 CHAPTER 12 BURST OPERATION 12 1 3 Ending burst operation by burst stop command The burst read operation can be aborted by inputting the burst stop command BST in the read cycle The data bus becomes high impedance after the lapse of the CAS latency from the burst stop command The burst stop command is only available in read cycles for DDR SDRAM Figure 12 5 Read Burst Stop Command ICK CK Command DQS DQ CL 2 5 DQS Remark CL CAS latency 86 User s Manual E0234E30 Ver 3 0 CHAPTER 12 BURST OPERATION 12 1 4 Terminating burst operation by precharge command 1 Read cycle The burst read operation is terminated by inputting the precharge command PRE To input the precharge command tras must be satisfied To activate the same bank again tre must be satisfied Figure 12 6 Read Precharge Command Hi Z DAS i ff NSM DG BL 8 ICK i CK I 1 1 I 1 1 1 1 I I 1 1 I 1 I 1 1 I 1 I I 1 1 I 1 READ PRE I I 1 I 1 1 I I 1 I 1 1 I 1 I 1 1
24. DIFFERENCES BETWEEN SDRAM AND DDR SDRAM 1 2 Differences in Commands Similarly to SDR SDRAM DDR SDRAM is controlled by commands but the commands supported by DDR SDRAM differ from those supported by SDR SDRAM Table 1 3 Differences in Commands Burst stop Valid only for read operation 1 2 1 Clock suspend In the case of SDR SDRAM operation can be suspended by making the clock enable signal CKE low during a read or write operation but in the case of DDR SDRAM clock suspend is not supported 1 2 2 Full page burst The burst lengths of DDR SDRAM are 2 4 and 8 Full page burst is not supported 1 2 3 Burst stop In the case of DDR SDRAM data output is suspended by the burst stop command during a burst read operation but the burst stop command is not available for a write operation Instead write data can be masked using the DQ write mask enable signal DM during a burst write operation but read data cannot be masked during a burst read operation 1 2 4 Single write after burst read DDR SDRAM does not support single write after burst read This is because whereas command input is synchronized only with the rising edge of the clock data input output is synchronized with both the rising and falling edges and thus the operation frequency is twice as high For details about the commands of DDR SDRAM refer to 3 2 Command Control and CHAPTER 7 COMMAND OPERATIONS 16 User s Manual E0234E30 Ver 3 0 CHAPTER 1 DIFFERENCES BE
25. DM write latency 0 BL 4 WRIT WRIT Remark BL Burst length 10 3 DQ Write Mask Enable Signal DM Truth Table Table 10 1 shows the command truth table of the DQ write mask enable signal DM Table 10 1 DQ Write Mask Enable Signal Truth Table idi Data write enable O e umewewmmm hostewmn Remark High level L Low level x High or Low level Don t care User s Manual E0234E30 Ver 3 0 75 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION This chapter explains the basic control method using the clock enable signal CKE CKE is a signal that controls clock CK CK enable disable 1 When CKE is high at the rising edge of the preceding CK The rising edge of CK is valid and signals are input 2 When CKE is low at the rising edge of the preceding CK The rising edge of CK is invalid and signals are ignored 11 1 Basic Control Figure 11 1 shows the signal input timing controlled by the clock enable signal CKE Figure 11 1 Signal Input Timing Controlled by Clock Enable Signal CKE SS Ca Ce EE Invaiid Valid Valid Valid Invalid When is high at the rising edge of the clock CK as in lt 2 gt 3 and 4 abov
26. I 1 1 I 1 cL 2 mE 08 UM Ne I 1 1 I 1 I 1 I 1 1 1 I 1 1 1 I 1 I 1 I 1 1 I 1 i i i Hi Z dede OXXX EJ de E I 1 I 1 I 1 O Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 87 CHAPTER 12 BURST OPERATION 2 Write cycle The burst write operation can be terminated by inputting the precharge command PRE To input the precharge command tras must be satisfied To activate the same bank again tre must be satisfied Data prepared twn before the precharge command will be correctly written to the memory cell Figure 12 7 Write Precharge Command ICK 1 1 1 1 1 1 1 1 1 1 BH a SS SS RSS RSS SN XOXOXO XXX XXX XX XXX XXX OX KIKI KOK OO SON 5 Hi Z pou j Hi Z des Da0X 2 is Data masked Remark CL CAS latency BL Burst length 88 User s Manual E0234E30 Ver 3 0 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices
27. L Delay Locked Loop circuit The DLL circuit is designed to realize fast access and high operation frequencies by controlling and adjusting the time lag between external and internal clock signals By employing DLL timing skew between the clock CK CK and DQ DGS is minimized User s Manual E0234E30 Ver 3 0 27 CHAPTER 3 PRODUCT FEATURES Elpida Memory s DDR SDRAM is a JEDEC compliant 2 5V device with a 133MHz clock frequency next generation DDR SDRAM supports clock frequencies of 167MHz or more This chapter explains following features of DDR SDRAM 1 Synchronous operation 2 Command control 3 Multibank operation 4 Burst operation 5 5 Access time 28 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES 3 1 Synchronous Operation Each control signal command is latched at the rising edge of the clock CK Input output data DQ is transmitted along with the data strobe signal DQS and captured by the receiver at the rising and falling edges of DQS thus making it easy to perform high speed operation The following examples show the relationship between the clock input of DDR SDRAM various control signals and the data input output timing For details about the clock input of DDR SDRAM refer to 1 1 2 Clock input and for details about DQS refer to CHAPTER 9 DATA STROBE SIGNAL DQS CONTROL OPERATION Figure 3 1 DDR SDRAM Read Cycle Timing Remark CL CAS latency BL Burst length Figure 3 2
28. NE 2 31 Memory cell array of 128M bit DDR SDRAM EDD1216ALTA A DDR SDRAM memory cell consists of one transistor and one capacitor like SDR SDRAM DDR SDRAM EDD1216ALTA has a total capacity of 128M bits and consists of 4096 word lines x 512 digit pairs x 16 I O lines x 4 banks Figure 2 4 Memory Cell Array of 128M bit DDR SDRAM EDD1216ALTA Bank A i T E E Word 1 La 7 Word 2 ij I Vu Vu z z Word 3 I I T m P 1 z 1 1 o 1 e 1 aun Lili ena 1 FC ai Word 4096 l 2 T ANI 512 digit pairs Note The above figure is a conceptual diagram It may differ from the layout of actual products 26 User s Manual E0234E30 Ver 3 0 CHAPTER 2 PRODUCT OUTLINE 2 3 2 Address decoder Row address decoder Column address decoder Similar to SDR SDRAM DDR SDRAM employs the address multiplex method First a bank address and a row address are loaded with an active command and the corresponding word line is selected Next a bank address and column address are loaded with a read or write command and the corresponding digit line is selected 2 3 3 I O buffer Buffer for data input output 2 3 4 Refresh counter This counter automatically generates row addresses internally 2 3 5 DLL Delay Locked Loop DDR SDRAM is provided with a DL
29. P V aa M DDR SDRAM i 66MHz SDR SDRAM JC 66MHz Burst cycle time 30 50 70 90 110 130 150 Access time ns Table 3 2 Access Time of DDR SDRAM SDR SDRAM and EDO DRAM Access time EDO DRAM SDR SDRAM DDR SDRAM EDO DRAM SDR SDRAM DDR SDRAM SDR SDRAM DDR SDRAM 60 100 MHz 100 MHz 133 MHz 133 MHz 10 ns 10 ns 7 5 ns 7 5 ns 38 User s Manual E0234E30 Ver 3 0 CHAPTER 4 INITIALIZATION This chapter explains initialization after power on 4 1 Initialization after Power On The logical state of the internal circuit of DDR SDRAM is undefined right after power on DDR SDRAMs must be powered up and initialized in a predefined manner to ensure correct operation DDR SDRAM power on and initialization sequence is as follows 1 Apply power first to then to and finally to and 2 Keep the clock enable signal CKE low in order to guarantee that DQ and DQS pins will be in the high impedance state 3 After all power supply and reference voltages are stable and the clock is stable wait 200us before applying an executable command Once the 200us delay has been satisfied a device deselect command DESL or no operation command NOP must be applied and CKE must be made high 4 Precharge all banks the precharge all banks command PALL is recommended 5 Enable DLL by the extended mode register set command EMRS Then reset DLL by the mo
30. PTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM DDR SDRAM double data rate synchronous DRAM is a type of DRAM that realizes twice the data transfer rate of conventional SDRAM here after in this document conventional SDRAM is referred to as SDR SDRAM single data rate synchronous DRAM in contrast with DDR SDRAM This chapter explains the differences between DDR SDRAM and SDR SDRAM in the following areas 1 Differences in functions and specifications 2 Differences in commands 3 Differences in operation timing 10 User s Manual E0234E30 Ver 3 0 CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM 1 1 Differences in Functions and Specifications DDR SDRAM is a type of SDRAM that inherits technologies from SDR SDRAM and realizes faster operation and lower power consumption It shares many common aspects with SDR SDRAM which enables easy transition to DDR SDRAM This section explains the differences in functions and specifications between DDR SDRAM and SDR SDRAM Table 1 1 Differences in Functions and Specifications uswmmwy S Note Full page 256 burst of SDR SDRAM is an option Remark Clock cycle time User s Manual E0234E30 Ver 3 0 11 CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM 1 11 1 Data transfer frequency data rate DDR SDRAM achieves a data transfer rate that is twice the clock frequency by employing 2 bit prefetch architecture The 2 bit prefetch architecture is explained here using
31. Q DQ Write Mask Enable Signal DM during Write Cycle sesseseeseeeeeeenenennenenee nnne 72 9 6 Data Strobe Signal 095 Write Preamble and Write 000010 73 CHAPTER 10 DQ WRITE MASK ENABLE SIGNAL DM CONTROL OPERATION 74 10 1 DQ Write Mask Enable Signal nennen nnne neret nennt 74 10 2 DQ Write Mask Enable Signal DM Control in Write 75 10 3 DQ Write Mask Enable Signal DM Truth 00 nennen nnne 75 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION eene enn 76 11 4 B sic Gontrol iie d E e EE E e ELE e E ELE ve 76 11 2 Example of Clock Enable Signal Control ssssssseseeeeeeneenenee nennen nennen nnne 77 W221 Powerdowrimode iet RERO RH BRIAN 78 11 2 2 Self retresh mode etaed eb date e ru a dede eate Re eter 79 11 2 3 Clock enable signal command truth table 128M bit DDR SDRAM EDD1216ALTA 80 CHAPTER 12 BURST OPERATION 5 utei I B E 82 2 Terminating B rst Operation i c cite che e c eee 82 12 1 1 Data interrupt by read 82 12 1 2 Data interrupt by write 84 12 1 3 Ending burst operation by burst stop 86 12 1 4 Terminating burst operation by pr
32. R SDRAM Read Cycle Timing esses rent nennen nennen nennen 29 DDR SDRAM Write Cycle Timing ssssesesseeeeeeeeneenneenneen nennen nnne neret neret 29 Gommand Input TIMING its ii roin e tec b Dee RED e Dore DU d EE etme ted 30 Four Bank Configurations ioo rens rre coti ceu Eo eerte Ed i e pde dte dee ao 32 B trst Op rations 5 Inte e eed et bl ce ia e a foe een led Situ 35 Burst Read Cycle iv siete ettet tee oh sd ce C cep ctt tee red 37 Access Time of DDR SDRAM SDR SDRAM and EDO 2 38 Initializing DDRiSDRAM eene 40 Mode Register Extended Mode Register Set 2 0000 0 00 41 Read Write Cycle with Burst Length of 8 nennen nennen nnne en nnne 42 Burst SEQUENCE s oe eie Ne ipe pi re Pe ten amd ne ere 43 Timing Differences between CAS Latency 2 and 2 5 nennen 45 Mode Register and Extended Mode Register fields with 128M bit DDR 5 2 22222 1 46 Simplified State Diagram of 128M bit DDR SDRAM 1216 48 Read Gycle sun amd Eb BR S au Vp rt etu tm duree oot bier Tes 60 Read with Auto Prechatge nte EE EO ORUM MEE IND LR APER 61 Write Cycle icici ui uino e Eel atc EE E E s Rete ei e E EZ 62 Write Cycle with Auto Precharge ciertas et bites dt Pitt eie Eng aate e e oa eR pde iiae 63 CBR Auto Refresh Cycle odere etie re Pe a La eet ge dace divide
33. TWEEN SDRAM AND DDR SDRAM 1 3 Differences in Operation Timing Similarly to SDR SDRAM DDR SDRAM is controlled by inputting commands at the rising edge of the clock CK However the data input output timing of DDR SDRAM differs from that of SDR SDRAM DDR SDRAM employs a differential clock CK CK and data strobe signal DQS to realize high speed data transfer DQS is synchronized with CK and data input output DQ is synchronized with both the rising and falling edges of DQS The following examples show the relationship between the clock input of DDR SDRAM SDR SDRAM their control signals commands and the data input output timing Figure 1 4 DDR SDRAM Read Cycle Timing Remark CL CAS latency BL Burst length Figure 1 5 SDR SDRAM Read Cycle Timing CL 2 BL 4 TO 1 2 T3 T4 T5 T6 T7 T8 i CK Command eiie E 1003062632 5 Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 17 CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM Figure 1 6 DDR SDRAM Write Cycle Timing WRIT Command DQS Remark BL Burst length Figure 1 7 SDR SDRAM Write Cycle Timing BL 4 T8 T7 T6 5 T4 T3 T2 T1 TO CK Command Remark BL Burst length User s Manual E0234E30 Ver 3 0 18 CHAPTER 2 PRODUCT OUTLINE This chapter provides an outline of DDR SDRAM products taking the EDD1216ALTA 1
34. User s Manual ELPIDA HOW TO USE DDR SDRAM Documen t No E0234E30 Ver 3 0 Date Published April 2002 K Japan URL http www elpida com Elpida Memory Inc 2002 INTRODUCTION This manual is intended for users who design application systems using double data rate synchronous DRAM DDR SDRAM Readers of this manual are required to have general knowledge in the fields of electrical engineering logic circuits as well as detailed knowledge of the functions and usage of conventional synchronous DRAM SDRAM Purpose This manual is intended to give users understanding of basic functions and usage of DDR SDRAM For details about the functions of individual products refer to the corresponding data sheet Since operation examples that appear in this manual are strictly illustrative numerical values that appear are not guaranteed values Use them only for reference Conventions Caution Information requiring particular attention Note Footnote for items marked with Note in the text Remark Supplementary information Related Documents Related documents indicated in this manual may include preliminary versions but they may not be explicitly marked as preliminary EDD1204ALTA EDD1208ALTA EDD1216ALTA DATA SHEET E0136E HOW TO USE SDRAM USER S MANUAL E0123N User s Manual E0234E30 Ver 3 0 CONTENTS CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM nemen 10 1 1 Differences in Functions and Specifications
35. bles accurate memory control Figure 1 2 Clock Input 1 clock Single Clock SDR SDRAM CK 50 50 Dotted line shows the 50 duty ratio position 1 clock ICK Differential Clock DDR SDRAM CK 50 50 CK is an input signal that has the same clock period but the reverse phase of CK The high level period and low level period can be made equal by using the intersection of CK and CK as an input reference level In the case of DDR SDRAM data input output is synchronized with both the rising and falling edges of the data strobe signal DQS which has the same period as clock input CK Employing a differential clock scheme enables DDR SDRAM to support a higher clock frequency and limit the negative influence of noise and other factors 1 1 3 Data strobe signal DQS Similarly to SDR SDRAM DDR SDRAM is controlled by command input at the rising edge of the clock CK but the data input output timing differs from that of SDR SDRAM To achieve high speed data transfer DDR SDRAM adopts a data strobe signal DQS DQS is output from the device and received by the receiver which adjusts the data DQ capture timing using DQS For details refer to CHAPTER 9 DATA STROBE SIGNAL DQS CONTROL OPERATION User s Manual E0234E30 Ver 3 0 13 CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM 1 1 4 Interface DDR SDRAM employs the JEDEC compliant SSTL_2 Stub Series Terminated Logic f
36. ck CK The receiver captures the data DQ using DQS as a timing reference The operation of DQS in the read cycle is as follows 1 High impedance while data is not output lt 1 gt in figure 2 After read command READ input DQS changes to low level approximately 1 clock prior to data output lt 2 gt in figure 3 DQS starts toggling at the same frequency as the clock CK 3 in figure 4 DQS toggling continues until the burst read operation is completed When the burst read operation is completed DQS changes back to high impedance lt 4 gt in figure Figure 9 2 shows the operation timing of DQS for the read cycle Figure 9 2 Data Strobe Signal in Read Cycle Command DQS DQ Remark CL CAS latency BL Burst length 66 User s Manual E0234E30 Ver 3 0 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 1 2 Data strobe signal 005 in write cycle In the write cycle the controller drives the data strobe signal DQS which is in synchronization with the clock CK DDR SDRAM captures the data DQ using DQS as a timing reference The operation of DQS in the write cycle is as follows 1 High impedance while data is not input lt 1 gt in figure 2 Approximately 1 2 clock after the write command WRIT DQS starts toggling at same frequency as the clock CK 2 in figure 3 DQS toggling continues until the burst write operation is completed 1 2 clock after the last burs
37. cy of 66MHz for SDR SDRAM and DDR SDRAM and RAS access time of 60ns for EDO DRAM The first data access RAS access time is approximately 60ns for all the devices with little difference in time This is because the internal memory structure is almost the same By contrast as the burst length becomes longer i e the second third and fourth data the data output time difference becomes bigger for the reason described in section 3 4 Burst Operation 36 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES Figure 3 6 Burst Read Cycle BL 8 EDO DRAM RAS ICAS 90 C92 gt ANE High level Data out 60 ns SDR SDRAM T12 T13 T2 T3 T4 T5 T6 T7 T8 719 T10 T11 T1 CK eh nm uot n eps eum ete Se REN Essen T tSt LM RE E ar Command Address Data out DDR SDRAM Cr P prm B eae age eg e reos G3 0907 H i eitis 2 45 6 i S i ol 4 a SORE ry Syd e Fag ogee tonem DQS Address Data out Caution EDO DRAM is asynchronous Remark BL Burst length 37 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES Figure 3 7 Access Time of DDR SDRAM SDR SDRAM and EDO DRAM i 183MHz iF
38. d The data of the read command is output after the lapse of the CAS latency Figure 12 2 Write Read Command ICK e N EM se uet pU WRIT a READ a i 1 cycle lt DM 0144001 004 914 04 0140419140911 000192 09 01 9 01 9 19 9 9 99 59 54054054054 54 054 054505450 4 4 59 99 1 1 1 1 1 1 DQS 1 1 1 1 I 1 1 1 WRIT READ 1 1 1 1 lt i ORAN ANN ANNA OY XXX XXX X UG XX NS A A KXAN DQS DQ Command DM DQS DQ Data masked 1 Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 5 QSS IRRI 83 CHAPTER 12 BURST OPERATION 12 1 2 Data interrupt by write command 1 Write cycle The preceding burst write operation can be aborted by inputting a new write command WRIT b Figure 12 3 Write Write Command CL 2 2 5 BL 4 Command DQS DQ Remark CL CAS latency BL Burst length 84 User s Manual E0234E30 Ver 3 0 CHAPTER 12 BURST OPERATION 2 Read cycle To abort the preceding burst read operation and start a burst write operation the burst stop command BST is required before the write command WRIT a Figure 12 4 Read Burst Stop Write Command I
39. d mode register set CBR auto refresh Self refresh exit Power down entry Power down exit Remark High level L Low level x High or low level Don t care V Valid data User s Manual E0234E30 Ver 3 0 51 CHAPTER 7 COMMAND OPERATIONS 7 2 Command Execution Conditions The state in which each command can be executed is shown below Also refer to 6 1 Simplified State Diagram of DDR SDRAM and 6 2 Current State Definition Table 7 2 Command Executable Condition Selected bank is active trcp after active command Selected bank is active trcp after active command 52 User s Manual E0234E30 Ver 3 0 CHAPTER 7 COMMAND OPERATIONS 7 3 Command Operation of 128M bit DDR SDRAM EDD1216ALTA This section describes the command operations in 128M bit DDR SDRAM Current state Idle a Weeewee erae oe Ce RERDREADA Nei Ne foon S REF SELF CBR auto refresh or self refresh Notes Notes 1 Illegal for the same bank these commands be valid depending the state of the bank specified by the bank addresses BAO BA1 2 Precharge may be enabled depending on the state of the bank specified by the bank addresses BAO BA1 3 Illegal if there is a bank that is not idle Remark Illegal Device operation and or data integrity are not guaranteed Current
40. d tics 64 User s Manual E0234E30 Ver 3 0 7 Figure Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 10 1 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 LIST OF FIGURES 2 2 Title Page Relationship between Data Strobe Signal and Data 65 Data Strobe Signal in Read Cycle ecceeccesseeeseeeeneeeeaeeeseeeeeeeseaeeseaeeeeeseaeeseaeessaeeseeesnaeessaeeesaeeseaeeenatee 66 Data Strobe Signal in Write eins cc ad et YE e tin 67 Data Strobe Signal and Output Data Timing as Related to Clock in Read 68 Data Strobe Signal and Output Data in Read 69 Timing of Data Strobe Signal Read Preamble and Read Postamble 1 71 Timing of Data Strobe Signal Read Preamble and Read Postamble 2 Read to Read Data Bus transition cis tei ned t ete e e rt esto eet ted tae 71 Timing Parameters of DQ DM during Write Cycle nennen nnne 72 Timing of Data Strobe Signal Write Preamble and Write Postamble 73 DQ Write Mask Enable Signal Control during Write
41. d time oot m Remark Clock cycle time Figure 9 8 Timing Parameters of DQ DM during Write Cycle DQS XK om Des 72 User s Manual 0234 30 Ver 3 0 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 6 Data Strobe Signal DQS Write Preamble and Write Postamble The data strobe pattern for a write operation also consists of preamble toggling and postamble portions When DDR SDRAM receives the write command WRIT in the bank active state the data strobe signal DQS input changes from the high impedance to low level This is the write preamble portion The write preamble occurs at the falling edge of the clock at which the WRIT command is input Following the write preamble the strobes will toggle at the same frequency as the clock signal while data is present on the data input output pin DQ The low time following the last data transition is known as the write postamble The write postamble occurs approximately 1 2 clock from the last data edge When a burst write is completed and another new burst write is expected to follow a write postamble and preamble are not required between the two burst write operations Timing parameters for the DQS write preamble and write postamble are shown below Table 9 5 AC Characteristics of Data Strobe Signal Write Preamble and Write Postamble Write preamble 0 25 tck Clock cycle time Figure 9 9 Timing of Data
42. de register set command MRS with A8 high 200 cycles are required between DLL reset and any read command 6 After precharging all the banks again input two or more CBR auto refresh commands REF 7 Input the mode register set command MRS to program the operating parameters User s Manual E0234E30 Ver 3 0 39 CHAPTER 4 INITIALIZATION Figure 4 1 Initializing DDR SDRAM 200 5 Min ICK Undefined CK Command NOP 200 gt tMRD tMRD tRP tRFC tRFC CKE Command wes DLL DLL Minimum 2 REF enable reset commands are required 40 User s Manual E0234E30 Ver 3 0 CHAPTER 5 MODE REGISTER SET 5 1 Programming the Mode Register The mode register is used to define various operating parameters of DDR SDRAM such as the latency mode burst sequence wrap type WT and burst length The extended mode register is used to enable disable DLL The addresses AO through Ax and the bank addresses BAO BA1 are used as input data to set the mode register and the extended mode register Once the parameters are set these registers retain the stored information until they are reprogrammed or the power is turned off 1 Execute the precharge all banks command PALL to precharge all banks After tre all banks become idle 2 Execute the mode register set command MRS and extended mode register set command EMRS to program
43. e is finished the bank has to be idle state at first to activate a different row in the bank To return to the idle state the precharge command PRE PALL has to be issued Precharge is the state in which the precharge command has been issued but tre has not been satisfied As mentioned in 6 2 1 Idle IDLE the bank will return to idle state when trp is satisfied 6 2 5 Read and write READ WRIT The state in which a read or write operation is in progress By issuing the read or write command READ WRIT along with a column address for the active bank the read or write operation will start When the operation is completed the bank automatically returns to the bank active state 6 2 6 Read and write with auto precharge READA WRITA When the read or write with auto precharge command READA WRITA is issued the device automatically starts precharging and the bank returns to the idle state after the read or write operation is completed 6 2 7 Mode register set The mode register set or extended mode register set command MRS EMRS can only be issued when all banks of the device are in the idle state When data has been written to the mode register the device automatically returns to the idle state after 1 6 2 8 CBR Auto refresh The CBR auto refresh command REF can only be issued when all banks of the device are in the idle state When the REF command is issued a certain row address of every bank is selected and refres
44. e where setup time tis and hold time are satisfied commands and D at the rising edge of the next CK can be loaded When is low at the rising edge of CK as in 1 and 5 the command at the rising edge of the next CK is ignored 76 User s Manual E0234E30 Ver 3 0 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION 11 2 Example of Clock Enable Signal Control There are two operation modes controlled by the clock enable signal CKE Power down mode Self refresh mode Figure 11 2 shows command input controlled by CKE In the figure the command is loaded only during the period 1 and 3 and the command is ignored during 2 Figure 11 2 Example of Clock Enable Signal Control 1 2 3 CKE lt 4 gt Command ae User s Manual E0234E30 Ver 3 0 77 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION 11 2 1 Power down mode In the power down mode the internal clock of the device is deactivated to reduce the power consumption of the device Figure 11 3 shows the timing in the power down mode 1 Starting power down mode The power down mode is started at T2 when the clock enable signal is changed from high to low T1 T2 in the all banks idle or bank active state When power down mode is started all the input signals other than CKE are ignored don t care state high or low level and the data bus becomes high impedance CKE must be kept l
45. e Specifications ee pu vones seca veo Lowel am v vote vane versos v van _ v Remark These specifications may differ depending on the product For details refer to the corresponding data sheet of each DDR SDRAM 1 1 5 Power supply Compared to the 3 3V power supply of SDR SDRAM the power supply of DDR SDRAM is 2 5V This reduction in power supply voltage reduces the power consumption of the DDR SDRAM circuits 1 1 6 CAS read latency CAS write latency burst length and burst sequence Similarly to SDR SDRAM DDR SDRAM has mode register set commands for the latency burst length and burst sequence Refer to CHAPTER 5 MODE REGISTER SET 1 1 7 Use of DLL DDR SDRAM is provided with a DLL Delay Locked Loop circuit The DLL circuit is designed to realize a fast access time and high operation frequencies by controlling and adjusting the time lag between the external clock and internal clock Refer to 2 3 Block Diagram 1 1 8 Data mask DDR SDRAM uses a DQ write mask enable signal DM which masks write data SDR SDRAM can mask both read and write data but the read mask is not supported by DDR SDRAM For details about the DM control operation refer to CHAPTER 10 DQ WRITE MASK ENABLE SIGNAL DM CONTROL OPERATION User s Manual E0234E30 Ver 3 0 15 CHAPTER 1
46. e precharge operation starts As long as tpa is satisfied the next bank active command ACT for the same bank can be issued Caution The auto precharge start timing may differ depending on the DDR SDRAM product For details refer to the data sheet of each product Figure 8 4 Write Cycle with Auto Precharge CL 2 2 5 BL 4 TO T1 T2 T3 T4 T5 T6 7 T8 T9 T10 T11 Command ACT Hi Z 1 DQ Auto precharge starts Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 63 CHAPTER 8 BASIC OPERATION MODES 8 3 Refresh Mode Similar to SDR SDRAM a refresh operation is necessary for DDR SDRAM There are two refresh modes CBR auto refresh Self refresh The CBR auto refresh sequence is as follows 1 The CBR auto refresh command REF can only be issued in the idle state If the device is not idle the precharge all banks command PALL has to be issued first 2 Input the REF command Since the refresh address is generated internally it is not necessary to specify refresh address 3 The device becomes idle after trrc For the self refresh mode operation refer to 11 2 2 Self refresh mode Figure 8 5 shows the basic operation timing chart for the CBR auto refresh cycle Figure 8 5 CBR Auto Refresh Cycle TO T1 T2 T3 T4 T9 T10 T11 T16 T17 T18 2 ae EM tRFC tRFC gt g
47. ead mode Write mode Refresh mode 8 1 Read Mode A read operation is executed by issuing the read command READ for an active bank The read operation sequence is as follows 1 To activate a particular row in a particular bank the bank active command ACT is issued along with a row address and bank address 2 After the lapse of trep from the ACT command the starting column and bank addresses are provided with the READ command 3 After the lapse of the CAS latency from the READ command the read burst data is available starting from the column address specified in 2 The number of successive burst data is determined by the burst length BL 4 After the lapse of tras from the ACT command the precharge command PRE is input To output all the burst data the earliest timing for PRE command is burst length 2 clocks after the READ command Caution The precharge command input timing tras may differ depending on the DDR SDRAM product For details refer to the data sheet of each product 5 After the lapse of tre the corresponding bank becomes idle User s Manual E0234E30 Ver 3 0 59 CHAPTER 8 BASIC OPERATION MODES 4 Figure 8 1 shows the basic operation timing chart for the read cycle when the burst length Figure 8 1 Read Cycle BL 4 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 TO ICK READ CK ACT Command 2 DQS 4 APEE Command DQS CL 2 5 4 4
48. echarge 87 6 User s Manual E0234E30 Ver 3 0 Figure Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 4 1 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 6 1 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 LIST OF FIGURES 1 2 Title Page 2 Bit Prefetch Architecture cn epo a ROGER URN GREGOR UOS 12 Glock Input PER eg e ec eene 13 SSTLE 2 Interface case of DIMM droite cca t ic dei te 14 DDR SDRAM Read Cycle 44 000000000000 nennen enne nennen enne nn nenne enne nnne 17 SDR SDRAM Read Cycle 17 DDR SDRAM Write Cycle TIMING cC eth e mr eo PER 18 SDR SDRAM Write Cycle Timing 5 tcr eee ete deter enn Dee rede ded 18 Pin Configuration of 128M bit DDR SDRAM ssssseeeeeneneennenenneeennennnren nennt rennen ren ennnne trennen nnne 20 Pin Configuration of 256M 512M bit DDR 21 Block Diagram of 128M bit DDR SDRAM 1216 25 Memory Cell Array of 128M bit DDR SDRAM EDD1216ALTA Bank A 26 DD
49. ed when address 1 the interleave type is selected Which type is to be selected depends on the type of CPU used in each system Figure 5 3 Burst Sequence Sequential Start address Carry not used Sequential address Address A B Binary counter Interleave Start address Interleave address Binary counter User s Manual E0234E30 Ver 3 0 43 CHAPTER 5 MODE REGISTER SET Burst length and burst sequence The following tables show the start column address and addressing sequence of each burst length Burst length 2 Start Address column address AO binary Sequential Burst Sequence decimal Interleave Burst Sequence decimal Burst length 4 Start Address column address A1 through 0 binary Sequential Burst Sequence decimal Interleave Burst Sequence decimal Burst length 8 Start Address column address A2 through 0 binary Sequential Burst Sequence decimal 0 1 2 3 4 5 6 7 Interleave Burst Sequence decimal 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 44 7 0 1 2 3 4 5 6 User s Manual
50. ed Loop iri nni ten eer us tae Dt RH HERE RECO 27 4 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES emp Sd ee RG ap ese ee 28 3 1 Synchronous Operation Aa an ee heii Mina 29 3 2 Command Control e a de d eie se ede E de eo VETE Ee EHE V E VERE LE E EY e vL ee 30 3 21 Gommianid input timirig eee pde De cen ed cde Dat SE ec etos 30 3 222 DDR SDRAM comma d tA D E aaae ar a E EROR REGE RR ERO BRERGM RR MEE 31 3 3 M ltiBank Operation nein ane dete etes Ld eee ec e Loa pc n LE ee eee 32 3 9 1 Four bark confIg ratiOn dem cte e o abe c o E odio da me Ste 32 3 3 2 Multibank operatiOhs 5 e t ERI HAUTE UE SR NAHE READER CORE GR LENSES 33 344 B rSE Operation ione SR te Lo c e e lat ste Lee Po af eM etes 34 3 5 ACCESS TIM ordei e nde ette reste i d chee E dete niet 36 CHAPTER 4 INITIALIZATION enni trio tmc Re Rae dee ei eite met a ede ae 39 4 4 Initialization after PoWer Oris intem ERU RDUM BURCH 39 CHAPTER 5 REGISTER SET sido reet ttl red ceat tia dp d eee a a cts 41 5 1 Programming the Mode 41 5 2 Parameters nipote nee alo e ii D teri epa eise e dr nnd 41 5 3 Mode Register and Extended Mode Register Fields with 128M bit DDR
51. equired between the two burst read operations Timing parameters for the DQS read preamble and read postamble are shown below Table 9 3 AC Characteristics of Data Strobe Signal Read Preamble and Read Postamble Remark Clock cycle time 70 User s Manual E0234E30 Ver 3 0 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION Figure 9 6 Timing of Data Strobe Signal Read Preamble and Read Postamble 1 Command READ tRPRE Read preamble CL 2 5 DQS preamble DQ Remark CL CAS latency BL Burst length p postamble Figure 9 7 Timing of Data Strobe Signal Read Preamble and Read Postamble 2 Read to Read Data Bus transition CK 1 i 1 1 d 1 1 1 Command READ a READ b i tRPRE Das preamble Dg deeem j Remark CL CAS latency BL Burst length User s Manual E0234E30 Ver 3 0 tRPST Ta postamble 71 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 5 Relationship between Data Strobe Signal DQS and Input Data DQ DQ Write Mask Enable Signal DM during Write Cycle Input data DQ and the DQ write mask enable signal DM are center aligned to the data strobe signal DQS during write cycle Timing parameters of DQ DM for DQS are shown below Table 9 4 AC Characteristics of DQ DM in Write Cycle DQ and DM input setup time 0 075 ons DQ and DM input hol
52. fter the lapse of trcp from the ACT command the starting column and bank addresses are provided with the WRIT command 3 During write bursts the first valid data in element will be registered on the first rising edge of the data strobe signal DQS and subsequent data elements will be registered on successive edges of DQS 4 After the lapse of tras from the ACT command the precharge command PRE is input 5 After the lapse of tre the corresponding bank becomes idle Figure 8 3 shows the basic operation timing chart for the write cycle when the burst length 4 Figure 8 3 Write Cycle 2 2 5 BL 4 TO T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 toass MIN Command ACT tpass i Hi Z 1 Das 1 1 1 i Hi Z momim mim tm eb mm Ra m im Lie Seem in hacen ee i jee hea i fos ie ey L 1 1 toass MAX J DQ 1 ciim i 4 pass i i Hi Z 1 DOS DQ fl2z smLz baIlns ss cLe2 e 2 5DOYXD1YD2YXD3y i 22b x 2 b 2 22 b222 2 b22 2 2 22 52 Remark CL CAS latency BL Burst length 62 User s Manual E0234E30 Ver 3 0 CHAPTER 8 BASIC OPERATION MODES Figure 8 4 shows the write cycle with auto precharge WRITA In this cycle it is not necessary to input the precharge command PRE because precharge starts automatically When using auto precharge in the write cycle it is not necessary to know when th
53. h is executed When CBR auto refresh is completed the device automatically returns to the idle state after tnrc User s Manual E0234E30 Ver 3 0 49 CHAPTER 6 SIMPLIFIED STATE DIAGRAM 6 2 9 Self refresh The self refresh command SELF can only be issued when all banks of the device are in the idle state In the self refresh state the device automatically performs refresh It is not necessary to execute the refresh command externally 6 2 10 Self refresh recovery The state in which the self refresh exit command SREX has been issued but txsnr has not been satisfied The device automatically returns to the idle state after txswn 6 2 11 Power down When the clock enable signal CKE is made low in the idle state or bank active state power down mode is set In this mode all input buffers except clock CK CK and CKE are turned off to reduce the power consumption of the device To return to the original state idle or active CKE must return to high 50 User s Manual E0234E30 Ver 3 0 CHAPTER 7 COMMAND OPERATIONS 7 1 DDR SDRAM Command Truth Table The command truth table of DDR SDRAM is shown below Table 7 1 128M bit DDR SDRAM 6 bit Organization Command Truth Table Command Symbol CS RAS 5 COIT fn x wpe px x aem D pw Dopo est EE SENE ERES UN MMMMMN Precharge selected bank Precharge all banks Mode register set Extende
54. ies of operations from address input to data output is completed 2 SDR SDRAM A column operation is divided into three processing blocks Y decoder Data amplifier and Output buffer As each processing block can operate in parallel each block can start the next process as soon as the current process is finished and handed over to the next processing block When a column address is input the internal address counter automatically increments the internal column address in synchronization with the clock Ck The number of times the column address is incremented is determined by the burst length This internal structure enables reading or writing of successive address Data is continuously output in synchronization with the rising edge of CK 3 DDR SDRAM The basic transfer scheme is the same as SDR SDRAM except that a 2 bit prefetch architecture is employed by DDR SDRAM In this architecture 2n bits of data are transferred from the memory cell array to the I O buffer every clock cycle Data transferred to the I O buffer is output n bits at a time even and odd addresses every half clock cycle As a result data is output continuously in synchronization with the rising and falling edges of the clock For further details about 2 bit prefetch architecture refer to 1 1 1 Data transfer frequency data rate 4 Comparison between EDO DRAM SDR SDRAM and DDR SDRAM The time required for first data output is almost the same for all these DRAMs But
55. mmand MRS set the option field addresses A7 and A9 through A1 0 and bank addresses BAO 1 0 0 To set DLL operation mode using the extended mode register set command EMRS set bank addresses BAO 1 1 0 Figure 5 5 Mode Register and Extended Mode Register fields with 128M bit DDR SDRAM BA1 BAO A11 A10 A9 8 A7 5 4 2 1 BAO 11 10 AQ oTo Te pule T DLL reset Mode register set Burst length Normal WT 0 WT 1 Reset reserved R reserved 2 4 8 reserved reserved reserved reserved reserved reserved reserved reserved Burst sequence Sequential Interleave CAS latency R reserved R reserved 2 R reserved R reserved R reserved 2 5 R reserved User s Manual E0234E30 Ver 3 0 CHAPTER 6 SIMPLIFIED STATE DIAGRAM 6 1 Simplified State Diagram of DDR SDRAM Figure 6 1 shows a simplified state diagram of DDR SDRAM Circles in the figure indicate the current state and arrows indicate the allowable transition User s Manual E0234E30 Ver 3 0 47 48 CHAPTER 6 SIMPLIFIED STATE DIAGRAM Figure 6 1 Simplified State Diagram of 128M bit DDR SDRAM EDD1216ALTA Set __ SREX no Refresh 2 Recovery x Refresh N 2 SEM
56. nds be valid depending on the state of the bank specified by the bank addresses BAO BA1 2 Precharge may be enabled depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed Current state Bank activating 56 DESL No operation Bank active after trcp C a o m SSCS 7 MRS EMRS Note Illegal for the same bank these commands be valid depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed User s Manual E0234E30 Ver 3 0 CHAPTER 7 COMMAND OPERATIONS Current state Write recovery ks Nooperaion Ganache atertw moe No operation fast _____ Noopaaton Sta adread ith asto Statwitswiewihatopectage he CC mur we Note Illegal for the same bank these commands be valid depending on the state of the bank specified by the bank addresses BAO BA1 Remarks 1 Write recovery In order to write all burst data to the memory cell correctly the asynchronous parameter twn must be satisfied twn defines the earliest time that a precharge command can be issued after the last input data 2 Illegal Device operation and or data integrity are not guaranteed Current state Write recovery
57. not cause bodily injury fire or other consequential damage due to the operation of the Elpida Memory Inc product Usage environment This product is not designed to be resistant to electromagnetic waves or radiation This product must be used in a non condensing environment If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan Also if you export products technology controlled by U S export control regulations or another country s export control laws or regulations you must follow the necessary procedures in accordance with such laws or regulations If these products technology are sold leased or transferred to a third party or a third party is granted license to use these products that third party must be made aware that they are responsible for compliance with the relevant laws and regulations 01 0107
58. omer s equipment shall be done under the full responsibility of the customer Elpida Memory Inc assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information Product applications Elpida Memory Inc makes every attempt to ensure that its products are of high quality and reliability However users are instructed to contact Elpida Memory s sales office before using the product in aerospace aeronautics nuclear power combustion control transportation traffic safety equipment medical equipment for life support or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury Product usage Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory Inc including the maximum ratings operating supply voltage range heat radiation characteristics installation conditions and other related characteristics Elpida Memory Inc bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions Even within the guaranteed ranges and conditions consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Elpida Memory Inc products does
59. on Refer to 6 1 Simplified State Diagram of DDR SDRAM and 7 2 Command Execution Conditions User s Manual E0234E30 Ver 3 0 31 CHAPTER 3 PRODUCT FEATURES 3 3 MultiBank Operation Similar to SDR SDRAM DDR SDRAM has multiple banks each bank consisting of address decoders memory cell arrays and sense amplifiers Each bank can be controlled independently Such a configuration is referred to as multibank operation By using the interleave operation of the bank even while one bank is being precharged other bank s can be accessed to achieve better efficiency 3 3 1 Four bank configuration DDR SDRAM has four banks A B C and D which are selected by bank addresses 0 1 For details refer to 2 2 6 Bank Address input BAO 1 This four bank configuration is outlined below using a comparison with EDO DRAM 1 EDO DRAM To achieve four banks four devices are necessary These banks are selected by RAS signals 2 DDR SDRAM SDR SDRAM Because DDR SDRAM SDR SDRAM has four banks internally four banks can be configured with one device Figure 3 4 Four Bank Configuration IRAS1 52 BAO Data In Data In BA1 Data Out Data Out RAS3 RAS4 DDR SDRAM EDO DRAM SDR SDRAM 32 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES 3 3 2 Multibank operations There are various multibank operations depending on the current state and operations that follow 1 Burst read burst
60. operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when once it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity MOS devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap MOS devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor MOS devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin The unused pins must be handled in accordance with the related specifications STATUS BEFORE INITIALIZATION OF MOS DEVICES Power on does not necessarily define initial status of MOS devices Production p
61. or 2 5V interface to eliminate the signal degradation caused by noise and reflection produced as a result of a high operating frequency SSTL 2 is a low voltage 2 5V small amplitude and high speed interface that reduces the effect of reflection by connecting series resistance between the signal branch point from the bus stub and the memory 1 Stub resistance A stub resistance of approximately 250 220 is generally used for DIMMs Dual In Line Memory Modules is connected in series to the output pin Vout providing impedance matching between the transmission line and device output 2 Termination voltage The line is terminated with a resistance of approximately 250 27Q is generally used for DIMMs This termination suppresses signal reflection in the transmission line and also reduces voltage spikes enabling high speed data transmission 3 Reference voltage The SSTL 2 interface is symmetrical with respect to high level and low level output Vrer is used as a reference voltage to detect high and low levels 4 Interface specification DDR SDRAM generally uses the SSTL_2 interface with termination at one end Figure 1 3 SSTL_2 Interface case of DIMM DDR Vout Vout DDR DDR Module Module R1 Termination resistance 27Q R2 Stub resistance 220 Mounted on DIMM R3 220 Vit 1 2 VDDQ 14 User s Manual E0234E30 Ver 3 0 CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM Table 1 2 SSTL_2 Interfac
62. ow in power down mode 2 Exiting power down mode The power down mode is exited at T9 when CKE is changed from low to high T8 T9 and the next command can be input starting from T10 The clock must toggle at least one cycle before CKE goes high Figure 11 3 Power Down Mode Power down mode entry Power down mode exit Remarks 1 Commands cannot be input in the power down mode 2 Make sure that tner is satisfied 78 User s Manual E0234E30 Ver 3 0 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION 11 2 2 Self refresh mode Self refresh is the operation mode used to reduce power consumption of the device by deactivating the internal clock while at the same time executing refresh operations automatically This mode is useful when it s necessary to keep memory cell data but a write read operation is not necessary Figure 11 4 shows the timing of self refresh mode 1 Starting self refresh mode The self refresh mode is started at T2 by changing the clock enable signal CKE from high to low T1 T2 when the self refresh entry command SELF is input In self refresh mode all the input signals except CKE are in the don t care state high or low level and the data bus becomes high impedance must be kept low in self refresh mode 2 Exiting self refresh mode The self refresh mode is exited by changing from low to high T101 T102 The clock must toggle at least one cycle before CKE goes high In addi
63. rocess of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the MOS devices with reset function have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers MOS devices are not initialized until the reset signal is received Reset operation must be executed immediately after power on for MOS devices having reset function CME0107 The information in this document is subject to change without notice Before using this document confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory Inc Elpida Memory Inc does not assume any liability for infringement of any intellectual property rights including but not limited to patents copyrights and circuit layout licenses of Elpida Memory Inc or third parties by or arising from the use of the products or information listed in this document No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of Elpida Memory Inc or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the cust
64. state Bank active Nop S C wamwem J ee mtm mee E Notes 1 lllegal for the same bank these commands may be valid depending on the state of the bank specified by the bank addresses BAO 1 2 Illegal if tras is not satisfied Remark Illegal Device operation and or data integrity are not guaranteed User s Manual E0234E30 Ver 3 0 53 CHAPTER 7 COMMAND OPERATIONS Current state Read xs Nooperaion Gancacieaterburiend No operation ark acne READREADA r sop Sar eadand ano poaae oet amm ma jm e Prepa Burst sap gt Precrargo feoeo vanatoare oet LL Notes 1 Must satisfy command interval and or burst interrupt condition 2 Illegal for the same bank these commands may be valid depending on the state of the bank specified by the bank addresses BAO BA1 Remark Illegal Device operation and or data integrity are not guaranteed Current state Write xs Nowpwaion ankaaioatorm i or hr wa REKDREROA Bue sop gt Sanveadied wih avo pechage Susrsep Sar now wiene wih ao rece Notes cde E Notes 1 Must satisfy command interval and or burst interrupt condition
65. t 64 User s Manual 0234 30 Ver 3 0 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION This chapter describes the data strobe signal DQS newly introduced in DDR SDRAM This signal is used to control the I O buffer 9 1 Data Strobe Signal DQS Since DDR SDRAM performs data input output at twice the frequency of the external clock the valid data window is narrower than for SDR SDRAM If the wiring length between the memory and the controller is different the time required for data to reach the receiver flight time is different This makes it difficult for the receiver to determine the data acceptance timing DDR SDRAM employs a data strobe signal DQS to notify the receiver of the data transfer timing DQS is a bi directional strobe signal and functions as the basic operating clock for DQ during read write operations Note Data is edge aligned to DQS for read data and center aligned for write data This means that when controller receives read data from DDR SDRAM it will internally delay the received strobe to the center of the received data window Figure 9 1 Relationship between Data Strobe Signal and Data Input Output DQS Read operation DQ Write operation DQ User s Manual E0234E30 Ver 3 0 65 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 1 1 Data strobe signal DQS in read cycle In the read cycle DDR SDRAM drives the data strobe signal DQS which is in synchronization with the clo
66. t data DQS changes back to high impedance 4 in figure Figure 9 3 shows the operation timing of DQS for the write cycle Figure 9 3 Data Strobe Signal in Write Cycle Command DOS DQ Remark BL Burst length User s Manual E0234E30 Ver 3 0 67 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 2 Relationship between Data Strobe Signal DQS Output Data DQ and Clock CK CK during Read Cycle During the read cycle the rising and falling edges of the data strobe signal DQS and the valid data window edges of DQ almost coincide with the rising and falling edges of the clock CK CK through the use of the DLL circuit or similar internal control Timing specifications and examples for DQ and DQS as related to CK are shown below Table 9 1 AC Characteristics of Data Strobe Signal and Output Data in Read Cycle DQS output access time from CK CK DDR266A DDR266B ns DQ output access time from CK CK Cr ns Figure 9 4 Data Strobe Signal and Output Data Timing as Related to Clock in Read Cycle toasck MIN tac MIN m i tac MAX peek i EE IM 8 77 tac 68 User s Manual E0234E30 Ver 3 0 CHAPTER 9 DATA STROBE SIGNAL 005 CONTROL OPERATION 9 3 Relationship between Data Strobe Signal DQS and Output Data DQ in Read Cycle In the read cycle the valid data window edge nearly coincides
67. the read cycle as an example In this architecture 2n bits of data are transferred from the memory cell array to the I O buffer every clock Data transferred to the I O buffer is output n bits at a time every half clock both rising and falling edges of the clock As the internal bus width is twice the external bus width DDR SDRAM achieves a data output rate that is twice the data rate of the internal bus Because data is accessed in 2 bit pairs only burst lengths of 2 4 and 8 are supported for DDR SDRAM Figure 1 1 2 Bit Prefetch Architecture ICK set CK 1 clock 1 2 clock Buffer 2 c c 7 SN Latch Circuit 12 Users Manual 0234 30 Ver 3 0 CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM 1 1 2 Clock input Due to the influence of various factors the high level period and low level period of the clock input may not be the same the duty ratio may not be 50 In the case of SDR SDRAM for which data input output is only synchronized with the rising edges of the clock there is some margin in the timing However in the case of DDR SDRAM for which data input output is synchronized with both the rising and falling edges of the clock it is difficult to accurately control the data input output timing based on the conventional single clock Therefore DDR SDRAM adopts a differential clock scheme that ena
68. the register Figure 5 1 Mode Register Extended Mode Register Set Cycle PALL 5 2 Parameters The mode register has the following 5 functions 1 AO through A2 2 3 A4 to A6 4 S Burst length Burst sequence CAS latency A7and A9 through Ax Option DLL reset The extended mode register has the following 2 functions 6 0 7 A1 through 11 DLL enable disable Option User s Manual E0234E30 Ver 3 0 41 CHAPTER 5 MODE REGISTER SET 1 Burst length The burst length is the number of data that can be successively input or output DDR SDRAM supports burst lengths of 2 4 and 8 Example 1 Burst length of 8 Data of eight columns can be successively input or output by a single read command READ or write command WRIT When the burst operation has been completed the data bus becomes high impedance Figure 5 2 Read Write Cycle with Burst Length of 8 512 Columns 0 511 4095 4096 Rows 0 Eight successive data synchronized with are input output Command i Hi Z Remark CL CAS latency 42 User s Manual E0234E30 Ver 3 0 CHAPTER 5 MODE REGISTER SET 2 Burst sequence The burst sequence specifies the order in which the burst data address is incremented Similarly to SDR SDRAM DDR SDRAM supports the sequential type and interleave type When address 0 the sequential type is select
69. tion txsnr must be satisfied before the next command is input Figure 11 4 Self Refresh Mode TO T1 T2 T3 T100 17101 T102 17103 T104 T105 T106 Self refresh mode entry Self refresh mode exit Caution For customers using concentrated CBR auto refresh non average periodic refresh to make sure memory cell data is not lost concentrated CBR auto refresh for all the row is required just before and after a self refresh operation User s Manual E0234E30 Ver 3 0 79 CHAPTER 11 CLOCK ENABLE SIGNAL CONTROL OPERATION 11 2 3 Clock enable signal command truth table 128M bit DDR SDRAM EDD1216ALTA The clock enable signal CKE command truth table is shown below Current state Self refresh CS RAS CAS Address Command Action Note ilegal Impossible Impossible H e cbc SREX Exit self refresh Self refresh recovery al Note low to high transition will re enable the clock n and other inputs asynchronously A minimum setup time must be satisfied before any command other than exit is input Remark H High level L Low level x High or low level Don t care Illegal Device operation and or data integrity are not guaranteed Current state Self refresh recovery ics RAS CAS WE Address Command Action Note C p D D o oL Dep pe peo so nor oopen cestero Remark
70. when it s a successive data access SDR SDRAM and DDR SDRAM can achieve a faster data transfer rate than EDO DRAM due to the pipelined operation DDR SDRAM which uses 2 bit prefetch architecture achieves an even faster data transfer rate than SDR SDRAM 34 User s Manual E0234E30 Ver 3 0 CHAPTER 3 PRODUCT FEATURES Figure 3 5 Burst Operation EDO DRAM Y Decoder Address 1 Address 2 Data amplifer Output buffer Output data 1 4 gt gt gt gt gt gt gt gt gt Time for each data to be output Output data 2 ni o 2 o o Data amplifer Output buffer T T2 T3 T4 T5 T6 Output data 1 4 Time for each data to be output Output data 2 qg Output data 3 Output data 4 tO Data out penne Data 1 X Data X Data X Data DDR SDRAM Data amplifer Output buffer Output data 1 Output data 2 Output data 3 Output data 4 Data out i Data 2X Data d User s Manual E0234E30 Ver 3 0 35 CHAPTER 3 PRODUCT FEATURES 3 5 Access Time This section compares the access time of EDO DRAM SDR SDRAM and DDR SDRAM using the read cycle as an example Figure 3 6 shows the burst read cycle of EDO DRAM SDR SDRAM and DDR SDRAM with a burst length of 8 and a clock frequen

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