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1. lflags The libraries to link 1 linkerscript Linker script used W1 T Wl linker script file mode Compile the ELF file in xMDStub mode MicroBlaze only or executable mode procinst Processor instance associated with this software application progccflags All other compiler options that cannot be set using the above options progstart Program start address searchlibs Library search path option L searchincl Include search path option I stacksize Stack size Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 67 7 XILINX Settings on Special Software Applications Settings on Special Software Applications Restrictions For every processor instance there is a bootloop application provided by default in XPS For MicroBlaze instances there is also an XMDStub application provided by XPS The only setting available on these special software applications is to Mark for BRAM Initialization When you use the xset_swapp_prop_value XPS no window mode will recognize lt procinst gt _bootloop and lt procinst gt _xmdstub as special software application names For example if the processor instance is mymblaze then XPS recognizes mymblaze_bootloop and mymblaze_xmdstub as software applications You can set the init_bram option on this application XPS xset swapp prop value mymblaze bootloop init bram true XPS xset swapp prop v
2. Option Name Description arch Set the target device architecture dev Set the target part name enable par timing error 0 1 When set to 1 enables PAR timing error fpga imp mode 0 1 Specify implementation tool to be used 0 xflow 1 ISE Xplorer gen sim tb true false Generate test bench for simulation models hdl vhdl verilog Set the HDL language to be used hier top sub Set the design hierarchy Embedded System Tools Reference Manual www xilinx com 63 UG111 EDK 11 3 1 XILINX Executing Flow Commands Table 4 1 xset and xget Command Options Cont d Option Name mix lang sim true false Description Specify if the available simulator tool can support both VHDL and Verilog package Set the package of the target device searchpath directories Set the search path as a semicolon separated list of directories speedgrade Set the speedgrade of the target device swapps Get a list of software applications This option can not be used with xset command sim model structural behavioral timing simulator mti ncsim none Set the current simulation mode Set the simulator for which you want simulation scripts generated sim x lib sim edk lib Set the simulation library paths These paths are not stored in XMP but in the registry that you specify For details refer to Chapter 6 Simulation Model Generator Simgen topinst instance
3. Instruction Register information can be found in the device BSDL file idcode device idcode gt JTAG ID code of the device jtagport cpu Specifies if the PowerPC processor JTAG pins are connected directly to FPGA user IO pins partname device name The name of the device Embedded System Tools Reference Manual www xilinx com 169 UG111 EDK 11 3 1 XILINX 170 Connect Command Options PowerPC Processor Options The following options allow you to specify the FPGA device to debug and the processor number in the device You can also map special PowerPC processor features such as ISOCM Caches TLB and DCR registers to unused memory addresses and then access them from the debugger as memory addresses This is helpful for reading and writing to these registers and memory from GDB or XMD Note These options do not create any real memory mapping in hardware Table 9 10 PowerPC Processor Options Option Description cpunr lt CPU Number gt PowerPC processor number to be debugged in a Virtex device containing multiple PowerPC processors The Processor number starts from 1 dcachestartadr Start address for reading or writing the data lt D Cache start address gt cache contents dcrstartadr Start address for reading and writing the lt DCR start address gt Device Control Registers DCR Using this option the entire DCR address space 210 addresses can be mapped to addresses starting
4. 233 qn 233 POCOV ta elit Seite ack Sas dues ted apte deret indie erede date needs 233 Utilities Specific to MicroBlaze and PowerPC usuuuuuuueue 233 mb addr2line mii aree tede a e eed eb Edd ebd ede a baked 233 nir MD XT DE 233 DAS iere re hU eed ba hace ende ee e eae a Fede aee eg 233 Ib EE E a tasso due Puede vise eoque E E ter dissitis uns 234 mb iota Erebi reed det ed aha a ii 234 PADES E uie tede ard faeta pe ed paite edet s desde e deno donned du EE 234 nec T dd AA a Ri A 234 O OS 234 nep PET 234 TDS EOE se ede det E rede reb S E MN otra aNobii EE diede eh aisle ied 234 dnm N 234 AU P mmm 234 mb obicOpy echar bebe P A E OCT eG e NE Eee ae tees 234 mb objdump i es rl delas 234 mb ranlib dieere bed eged dd 235 AUP CA SU res nt insta tein th toad a ita tete olde petes ade ee 235 MDI A ai 235 hax cc RT 235 nerd M EE 235 Other Programs and Files isse suhe doeet ad b dac abaco FCR Rod 235 Appendix B Interrupt Management Additional Resources ere 237 Hardware Setup iria aU pe dc E ts Rd ior ab ad 238 Software Setup and Interrupt Flow tous 239 Interrupt Flow for MicroBlaze Systems 666 cece eee eee eee 239 Interrupt Flow for PowerPC Systems 6 6 cece nee eee 241 Software APIs iaa 243 Interrupt Controller Driver 2 0 6 6 eee 243 API Descriptions Pm 244 Standalone Software Platform APIs for MicroBlaze 6 cee eee 246 MicroBlaze In
5. Exception_id Trap Exception_Name 9 Yes APU non available exception 10 No Time out exception on programmable interval timer 11 No Time out exception on fixed interval timer 12 No Time out exception on watchdog timer 13 No Data TLB miss exception 14 No Instruction TLB miss exception 15 No Debug event exception 16 Yes Assertion failure 17 Yes Program exit Table 9 6 MicroBlaze Exception Settings Exception_id Trap Exception_Name 0 Yes Fast Simplex Link exception 1 No Unaligned data access exception 2 Yes Illegal op code exception 3 Yes Instruction bus error exception 4 Yes Data bus error exception 5 Yes Divide by zero exception 6 Yes Floating point unit exception 7 Yes Privileged instruction exception 8 Yes Data storage exception 9 Yes Instruction storage exception 10 Yes Data TLB miss exception 11 Yes Instruction TLB miss exception 12 Yes Assertion failure 13 Yes Program exit 166 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Overwriting Exception Settings There are two methods to overwrite the default exception settings 1 Use the command xmdconfig mb trap mask ppc trap mask MASK This sets the mask for all targets in the current XMD session To define your own default setting for all XMD sessions you can write that command in the
6. Master BEM Component 1 Master BEM gt Component 2 Arbiter X10849 Figure 5 3 Speed Up Simulation Use Case Bus Functional Simulation Methods There are two software packages that allow you to perform Bus Functional Simulation and each applies its own methodology e IBM CoreConnect Toolkit e Xilinx EDK BFM Package Neither software package is included with EDK but they are required if you intend to perform bus functional simulation You can download them free of charge once you obtain a license for the IBM CoreConnect Bus Architecture Licensing CoreConnect provides access to a wealth of documentation Bus Functional Models and the Bus Functional Compiler Xilinx provides a Web based licensing mechanism that enables you to obtain CoreConnect from the Xilinx web site To license CoreConnect use an internet browser to access http www xilinx com products ipcenter dr_pcentral_coreconnect htm Once the request has been approved typically within 24 hours you will receive an E mail granting you access to the protected web site from which to download the toolkit For further documentation on the CoreConnect Bus Architecture refer to the IBM CoreComnect web site http www 01 ibm com chips techlib techlib nsf products CoreConnect Bus Architecture Note There are some differences between IBM CoreConnect and the Xilinx implementation of CoreConnect These are described in the Processor IP Referenc
7. xget sw array element handle handle element name Description Arguments Example Returns the handle to the array element associated with the handle handle is of specified type Valid handle types are array or array instance element name is array element required If specified as an asterisk the API returns a list of element handles To access an individual element handle iterate over the list in Tcl set elem handle xget sw array element handle array handle myelement www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Software Tcl Commands x XILINX xget_sw_driver_handle lt mss_handle gt lt driver_name gt Description Returns the handle to the driver with the lt driver_name gt associated with the specified lt mss_handle gt Arguments lt driver_name gt is the name of the required driver mss handle is the handle to the MSS file Example set drv handle xget sw driver handle mss handle driver name xget sw driver handle for ipinst merged processor handle ipinst name Description Returns a handle to the merged driver object assigned to the IP instance specified by ipinst name A merged driver object is a driver that has an associated list of peripherals and parameter values that use the merged driver The merged driver contains connectivity information that is provided by the merged processor object Arguments merged processor hand
8. Add the c DEBUG ENABLED parameter to a MicroBlaze instance and set its value to 1 xadd hw ipinst parameter mb handle C DEBUG ENABLED 1 xadd hw subproperty prop handle subprop name subprop value Description Arguments Example Adds a subproperty to a property parameter port or bus interface prop handle is a handle to the parameter port or bus interface lt subprop_name gt is the name of the sub property lt subprop_value gt is the value of the sub property For a list of sub properties refer to Microprocessor Peripheral Definition MPD in the Platform Specification Format Reference Manual and Additional Keywords in the Merged Hardware Datastructure on page 290 Add DIR to a port xadd hw subproperty port handle DIR I xadd hw toplevel port mhs handle port name connector name direction Description Arguments Example Adds a new top level port to the MHS specified by mhs handle Returns a handle to the newly created port if successful and NULL otherwise mhs handle is the handle to the MHS in which this top level port has to be added port name is the name of the port that needs to be added connector name is the name of the connector direction is the direction of the port I 0 or IO Add a top level input port sys clk pin with connector dcm clk s xadd hw toplevel port mhs handle sys clk pin v dc
9. To generate an SVF file for hardware configuration for all FPGAs 1 Create a SCR file impact download scr with the following contents and invoke the impact batch impact download scr command setMode cf setPreference pref KeepSVF True addCollection name Temp addDesign version 0 name config0 addDeviceChain index 0 setCurrentDeviceChain index 0 setCurrentCollection collection Temp setCurrentDesign version 0 Embedded System Tools Reference Manual www xilinx com 213 UG111 EDK 11 3 1 7 XILINX Generating ACE Files addDevice position 1 file ML561 FPGA1 Download bit addDevice position 2 file ML561 FPGA2 Download bit addDevice position 3 file ML561 FPGA3 Download bit generate quit This generates the SVF file config0 svf 2 Generate an SVF file for the software on the first FPGA device The options file contains the following jprog ace fpgal_sw ace board user configdevice devicenr 1 idcode 0x22a96093 irlength 10 partname xc5v1lx50t configdevice devicenr 2 idcode 0x22a96093 irlength 10 partname xc5vlx50t configdevice devicenr 3 idcode 0x22a96093 irlength 10 partname xc5vlx50t debugdevice devicenr 1 cpunr 1 target mdm elf executablel elf This generates the SVF file fpga1_sw svf 3 Generate an SVF file for the software on the second FPGA device The options file contains the following jprog ace fpga2_sw ace board user configdevice devicenr 1
10. X xlib directory Path to the Xilinx simulation libraries unisim simprim XilinCoreLib directory This is the output directory of the Compxlib tool 92 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 6 Simulation Model Generator Simgen XILINX Output Files Simgen produces all simulation files in the simulation directory which is located inside the output_directory In the simulation directory there is a subdirectory for each simulation model such as output_directory simulation lt sim_model gt Where sim model is one of behavioral structural or timing After a successful Simgen execution the simulation directory contains the following files peripheral wrapper vhd v Modular simulation files for each component Not applicable for timing models system name vhd v The top level HDL file of the design system name sdf The SDF file with the appropriate block and net delays from the place and route process used only for timing simulation xilinxsim ini Initialization file for the ISim system prj Project file specifying HDL source files and libraries to compile for the ISim system name fuse sh Helper script to create a simulation executable ISim only when Simgen does not create a test harness system name setup do sh tcl Script to compile the HDL files and load the compiled simulation models in the simulator test har
11. Creating a New Empty Project Creating a New Project With an Existing MHS Opening an Existing Project Reading an MSS File Saving Your Project Files Setting Project Options Executing Flow Commands Reloading an MHS File Adding a Software Application Deleting a Software Application Adding a Program File to a Software Application Deleting a Program File from a Software Application Archiving Your Project Files Setting Options on a Software Application Settings on Special Software Applications Restrictions Embedded System Tools Reference Manual www xilinx com 61 UG111 EDK 11 3 1 XILINX Invoking XPS Command Line Mode Invoking XPS Command Line Mode To invoke the XPS command line or no window mode type the command xps nw at the prompt in the Xilinx Bash Shell This is the EDK Cygwin shell for a Windows platform or LINUX shell with appropriate environment variables set up for LINUX based platforms XPS performs the specified operation then presents a command prompt From the command line you can e Generate the Microprocessor Software Specification MSS file and make files e Runthe complete project flow in batch mode Create an XMP project file e Load a Xilinx Microprocessor Project XMP file created by the XPS GUI e Read and reload project files e Add and delete software applications or program files e Ex
12. set addrTypeValue xget hw subproperty value param ADDR TYPE Found tag Add MhsInst to list and break to go to next MhsInst if string compare nocase addrTypeValue MEMORY 0 lappend ret list mhsinst break return ret list Embedded System Tools Reference Manual www xilinx com 267 UG111 EDK 11 3 1 XILINX 268 Appendix C EDK Tcl Interface Advanced Write Access APIs Advance Write Access APIs modify the MHS object in memory These commands operate on the original MHS handle and handles obtained from the MHS handle The Write Access APIs can be used to create the project only They are disabled during the Platgen flow Advance Write Access Hardware API Summary The following table provides a summary of the Advance Write Access APIs To go to the API descriptions which are provided in the following section click on a summary link Table C 2 Hardware Advanced Write Access APIs Add Commands xadd hw hdl srcfile xipinst handle fileuse filename lt hdllang gt xadd hw ipinst busif ipinst handle busif name busif value xadd hw ipinst port ipinst handle port name connector name xadd hw ipinst mhs handle inst name ip name hw ver xadd hw ipinst parameter ipinst handle param name param value xadd hw subproperty prop handle subprop name subprop value xadd hw toplevel port mhs handle port name connector name direction
13. Creating Simulation Models Using XPS Batch Mode 1 Open your project by loading your XMP file XPS load xmp lt filename gt xmp 2 Set the following simulation values at the XPS prompt a Select the simulator of your choice using the following command XPS xset simulator mti ncs none b Specify the path to the Xilinx and EDK precompiled libraries using the following commands XPS xset sim x lib path XPS xset sim edk lib lt path gt c Select the Simulation Model using the following command XPS xset sim model behavioral structural timing 3 To generate the simulation model type the following XPS run simmodel When the process finishes HDL models are saved in the simulation directory 4 Toopen the simulator type the following XPS run sim 90 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 6 Simulation Model Generator Simgen XILINX Simgen Syntax At the prompt run Simgen with the MHS file and appropriate options as inputs For example simgen lt system_name gt mhs options Requirements Verify that your system is properly configured to run the Xilinx ISE tools Consult the release notes and installation notes that came with your software package for more information Options The following Simgen options are supported Table 6 1 Simgen Syntax Options Option Command Description EDK Library Directory E edklib dir Deprecated
14. GNU Compiler Tools GCC GNU compiler tools are called for compiling and linking application executables for each processor in the system Processor specific compilers are e The mb gcc compiler for the MicroBlaze processor e The powerpc eabi gcc compiler for the PowerPC processor As shown in the embedded tools architectural overview Figure 1 2 page 20 e The compiler reads a set of C code source and header files or assembler source files for the targeted processor e The linker combines the compiled applications with selected libraries and produces the executable file in ELF format The linker also reads a linker script which is either the default linker script generated by the tools or one that you have provided Refer to Chapter 8 GNU Compiler Tools Chapter 10 GNU Debugger GDB and Appendix A GNU Utilities for more information about GNU compiler tools and utilities 26 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX EDK Overview Xilinx Microprocessor Debugger XMD You can debug your program in software using an Instruction Set Simulator ISS or ona board that has a Xilinx FPGA loaded with your hardware bitstream As shown in Figure 1 2 page 20 the debugger utility XMD reads the application executable ELF file For debugging on a physical FPGA XMD communicates over the same download cable as used to configure the FPGA with a bitstream Refer to Chapter 9 Xili
15. The Newlib math libraries have alternate versions that implement these math functions using single precision arithmetic These single precision libraries might be able to make direct use of the MicroBlaze hardware floating point unit and could therefore perform better If you are sure that your application does not require standard precision and you would like to implement enhanced performance you can change the version of the linked in library manually By default the CPU driver copies the double precision version libm fpd a ofthe library into your XPS project To get the single precision version you can create a custom CPU driver that copies the corresponding 1ibm_ _fps a library instead Simply copy the corresponding 1ibm fps a file into your processor library folder such as microblaze_0 1ib as libm a When you have copied the library that you want to use rebuild your application software project Thread Safety The MicroBlaze C and math libraries distributed with EDK are not built to be used in a multi threaded environment Common C library functions such as printf scanf malloc and free are not thread safe and will cause unrecoverable errors in the system at run time Use appropriate mutual exclusion mechanisms when using the EDK libraries in a multi threaded environment Command Line Arguments MicroBlaze programs cannot take command line arguments The command line arguments argc and argv are initialized to 0 by
16. These components may be instantiated in an MHS design file for the Platform Studio tools to create the simulation HDL files Note Xilinx has written an adaptation layer to connect the IBM CoreConnect Bus Functional Models to the Xilinx implementation of CoreConnect Some of these BFM devices have different data instruction bus widths OPB BFM Component Instantiation The following is an example MHS file that instantiates OPB BFM components and the BFM synchronization bus Parameters PARAMETER VERSION Il N 1 0 Ports PORT rx rx DIR IN PORT tx tx DIR OUT PORT leds leds VEC 0 7 DIR INOUT PORT sys_reset sys_reset DIR IN PORT sys clk sys clk DIR IN SIGIS Components BEGIN opb_device_bfm PARAMETER INSTANCE my_device PARAMETER HW_VER 1 00 a PARAMETER SLAVE ADDR LO 0 0x00000000 PARAMETER SLAVE ADDR HI 0 0x0000ffff PORT SYNCH IN synch PORT SYNCH OUT synchO0 BUS INTERFACE MSOPB opb bus END BEGIN opb monitor bfm PARAMETER INSTANCE my monitor PARAMETER HW VER 1 00 a PORT OPB_Clk sys clk PORT SYNCH IN synch PORT SYNCH OUT synch1 BUS INTERFACE MON OPB opb bus ND E BEGIN bfm synch PARAMETER INSTANCE my synch PARAMETER HW VER 1 00 a PARAMETER C NUM SYNCH 2 PORT FROM SYNCH OUT synch0 synchl PORT TO SYNCH IN sy
17. Writes a 32 bit value into register number reg xstack check target id Gives the stack usage information of the program running on the current target The most recent ELF file downloaded on the target is taken into account for stack check Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 193 7 XILINX XMD Internal Tcl Commands Program Control Options Table 9 21 Program Control Options Option xbreakpoint lt target id addr function name sw hw Description Sets a breakpoint at the given address or start of function Note Breakpoints on instructions immediately following an IMM instruction can lead to undefined results for an XMDStub target xcontinue target id Execute Start Address gt block Continues from current PC or optionally specified Execute Start Address If block option is specified the command returns when the Processor stops on breakpoint or watchpoint The block option is useful in scripting xcycle step target id cycles Cycle steps through one clock cycle of PowerPC processor ISS If cycles is specified then step cycles number of clock cycles xlist target id Lists all of the breakpoint addresses xremove target id lt addr gt function name gt bp id all Removes one or more breakpoints or watchpoints xreset target id reset type Resets targ
18. XILINX Appendix B Interrupt Management void XIntc Stop XIntc InstancePtr Description Stops the interrupt controller by disabling the output from the controller so that no interrupts are caused by the interrupt controller Parameters InstancePtr is a pointer to the XIntc instance Standalone Software Platform APIs for MicroBlaze The following are the relevant functions for handling interrupts on a MicroBlaze processor using the Standalone software platform void microblaze register handler XInterruptHandler Handler void DataPtr Description This function registers a handler that is invoked from the Standalone software platform interrupt handler when an interrupt occurs in the system When no interrupt controller is present this function is used to directly register the final interrupt handler for the application When an interrupt controller is present this function would be used to register the handler for the interrupt controller driver XIntc_DevicelnterruptHandler thus enabling vectoring of interrupts by the interrupt controller driver Parameters Handler is the handler function to be invoked DataPtris the callback value that is passed to the function when it is invoked void microblaze enable interrupts void Description This function enables external interrupts on the MicroBlaze processor void microblaze disable interrupts void Description This function disables external interrupts on the
19. Mn BE out std logic vector 0 to C BI OPB DWIDTH 8 1 BI Mn busLock out std logic BI Mn DBus out std logic vector 0 to C BI OPB DWIDTH 1 BI Mn request out std logic BI Mn RNW out std logic BI Mn select out std logic BI Mn segAddr out std logic Examples IM request out std logic Bridge request out std logic O20b request out std logic OPB Master Inputs For interconnection to the OPB all masters must provide the following inputs BI nOPB Clk in std logic BI nOPB DBus in std logic vector 0 to C_ lt BI gt OPB_DWIDTH 1 BI nOPB errAck in std logic BI nOPB MGrant in std logic BI nOPB retry in std logic BI nOPB Rst in std logic BI nOPB timeout in std logic BI nOPB xferAck in std logic Examples IOPB DBus in std logic vector 0 to C IOPB DWIDTH 1 1 Deprecated in this release 44 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility XILINX OPB_DBus in Busl1 OPB DBus in Slave OPB Ports std logic vector 0 to C OPB DWIDTH 1 std logic vector 0 to C Busi OPB DWIDTH 1 H The signal list shown below applies to slave OPB ports that are independent of master OPB ports For the signal list for peripherals that use a combined master and slave bus interface refer to Mast
20. On the PowerPC 405 processor the critical and non critical interrupt ports are named EICC405CRITINPUTIRQ and EICC405EXTINPUTIRQ respectively On the PowerPC 440 processor the critical and non critical interrupt ports are named EICCAAOCRITIRQ and EICC440EXTIRQ respectively There are two ways to wire interrupts to a processor e The interrupt signal from the interrupting peripheral is directly connected to the processor interrupt port In this configuration only one peripheral can interrupt the processor e The interrupt signal from the interrupting peripheral is connected to an interrupt controller core which in turn generates an interrupt on a signal connected to the interrupt port on the processor This allows multiple peripherals to send interrupt signals to a processor This is the more common method as there are usually more than one peripheral on embedded systems that require access to the interrupt function The following figure illustrates the interrupt configurations Processor Processor Programmable Timer Interrupt Port Interrupt Port Interrupt Controller Programmable Timer Interrupts without an Interrupts with an Interrupt Controller Interrupt Controller Ethernet MAC X11017 Figure B 1 Interrupt Configurations www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software Setup and Interrupt Flow
21. configuration options xilinx parallel For additional information refer to Connect debugdevice device name Command Options on page 168 mrd mrd 0x400 Reads num memory locations starting at mrd address lt number of words half words bytes gt w h b mrd lt Global Variable Name gt mrd 0x400 10 mrd 0x400 10 h address Defaults to a word w read If Global Variable Name name is specified reads memory corresponding to global variable in the previously downloaded ELF file 156 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD 7 XILINX Table 9 2 XMD User Commands Cont d command options mrd_var mrd_var lt Global Variable Name lt filename elf gt Example Usage mrd global vari executable elf Description Reads memory corresponding to global variable in the ilename elf orina previously downloaded ELF file mwr mwr lt address gt values number of words half words bytes w h b mwr lt Global Variable Name values number of words half words bytes w h b mwr 0x400 0x12345678 mwr 0x400 0x1234 1 h mwr 0x400 0x12345678 0x87654321 2 Writes to num memory locations starting at address or lt Global Variable Name Defaults to a word w write profile profile o GMON Output filename profile o gproff out
22. www xilinx com 101 7 XILINX Load Paths Load Paths The following figure and Figure 7 2 on page 103 are diagrams of the directory structure for drivers libraries and Operating Systems OSs Ip library path Library Name boards drivers pcores SW Services X10133 Figure 7 1 Directory Structure of Peripherals Drivers Libraries and OSs PC System Load Paths On a PC the drivers and libraries reside in the following locations e Drivers SXILINX_EDK sw lib XilinxProcessorIPLib drivers e Libraries SXILINX EDKNswN library name Nsw services e OSs XILINX_EDK sw bsp lt library_name gt Additional Directories To specify additional directories use one of the following options e Use the current working directory from which Libgen was launched e Set the EDK tool option lp Libgen checks for drivers OSs and libraries under each of the subdirectories of the path specified in the lp option 102 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 7 Library Generator Libgen XILINX Search Priority Mechanism Libgen uses a search priority mechanism to locate drivers and libraries as follows 1 drivers lt my_driver gt Search the current working directory a Drivers Search for drivers inside the drivers or pcores directory in the current working directory in which you run Libgen Libraries Search for libraries inside the sw servic
23. Clock and Reset PLB Clk PLB Rst PLBV46 Slave Clock and Reset SPLB Clk SPLB Rst PLBV46 Master Clock and Reset MPLB Clk MPLB Rst Slave DCR Ports Slave DCR ports must follow the naming conventions shown in the following table Table 2 5 Slave DCR Port Naming Conventions lt S1n gt A meaningful name or acronym for the slave output S1n must not contain the string DCR upper lower or mixed case so that slave outputs are not confused with bus outputs nDCR A meaningful name or acronym for the slave input The last three characters of nDCR must contain the string DCR upper lower or mixed case BI A bus identifier Optional for peripherals with a single slave DCR port and required for peripherals with multiple slave DCR ports Br must not contain the string DCR upper lower or mixed case For peripherals with multiple slave DCR ports the B1 strings must be unique for each bus interface Note f Br is present S1n is optional 1 Deprecated in this release 40 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility XILINX DCR Slave Outputs For interconnection to the DCR all slaves must provide the following outputs lt BI gt lt S1n gt _dcrDBus out std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 lt BI gt lt S1n gt _dcrAck out std logic Examples Ua
24. Delete Commands xdel hw ipinst mhs handle inst name xdel hw ipinst busif ipinst handle busif name xdel hw ipinst port ipinst handle port name xdel hw ipinst parameter ipinst handle param name xdel hw subproperty prop handle subprop name xdel hw toplevel port mhs handle port name Modify Commands xset hw parameter value busif handle busif value xset hw port value port handle port value xset hw busif value busif handle busif value www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Example Procedures XILINX Advance Write Access Hardware API Descriptions Add Commands xadd hw hdl srcfile lt ipinst_handle gt lt fileuse gt filename lt hdllang gt Description Adds HDL files on the fly to the PAO This API should only be used in batch tools like platgen simgen and not in xps batch as a design entry mechanism When adding VHDL files those files are expected to be an instance specific customization and consequently are added to a logical library called instname wrapper hwver VHDL files must be generated in the projdir hdl elaborate instname wrapper hwver directory While Verilog does not use libraries the files must still be generated in the specified directory structure and location Arguments lt ipinst_handle gt is the handle of the IP instance lt fileuse gt is lib synlib
25. For more information about SDK see the Software Development ToolKit SDK Help Library Generator Libgen Libgen configures libraries device drivers file systems and interrupt handlers for the embedded processor system creating a software platform The software platform defines for each processor the drivers associated with the peripherals you include in your hardware platform selected libraries standard input and output devices interrupt handler routines and other related software features Your SDK projects further define software applications to run on each processor which are based on the software platform Taking libraries and drivers from the installation along with any custom libraries and drivers for custom peripherals you provide SDK is able to compile your applications including libraries and drivers into Executable Linked Format ELF files that are ready to run on your processor hardware platform Libgen reads selected libraries and processor core pcore software description files Microprocessor Driver Definition MDD and driver code from the EDK library and any user IP repository Refer to Chapter 7 Library Generator Libgen and the Xilinx Platform Studio Help for more information For more information on libraries and device drivers refer to the Xilinx software components documented in the OS and Libraries Document Collection Links to the documentation are supplied in the Additional Resources page 18
26. Invoke language cleanup functions such as C destructors De initialize the hardware sub system For example if the program is being profiled clean up the profiling sub system Embedded System Tools Reference Manual www xilinx com 135 UG111 EDK 11 3 1 XILINX 136 MicroBlaze Compiler Usage and Options Table 8 8 Register initialization in the C Runtime files Register Value Description rl _stack 16 The stack pointer register is initialized to point to the bottom of the stack area with an initial negative offset of 16 bytes The 16 bytes can be used for passing in arguments r2 SDA2 BASE SDA2 BASE is the read only small data anchor address r13 SDA BASE _SDA_BASE is the read write small data anchor address Other Undefined Other registers do not have defined values registers The following subsections describe the initialization files used for various application modes This information is for advanced users who want to change or understand the startup code of their application For MicroBlaze there are two distinct stages of C runtime initialization The first stage is primarily responsible for setting up vectors after which it invokes the second stage initialization It also provides exit stubs based on the different application modes First Stage Initialization Files crt0 o This initialization file is used for programs which are to be executed in standalone mode wi
27. e Chapter 5 Bus Functional Model Simulation e Chapter 6 Simulation Model Generator Simgen e Chapter 7 Library Generator Libgen e Chapter 8 GNU Compiler Tools e Chapter 9 Xilinx Microprocessor Debugger XMD e Chapter 10 GNU Debugger GDB e Chapter 11 Bitstream Initializer BitInit e Chapter 12 System ACE File Generator GenACE e Chapter 13 Flash Memory Programming e Chapter 14 Version Management Tools revup e Chapter 15 Xilinx Bash Shell e Appendix A GNU Utilities e Appendix B Interrupt Management e Appendix C EDK Tcl Interface e Appendix D Glossary Embedded System Tools Reference Manual www xilinx com 3 UG111 EDK 11 3 1 Preface About This Guide XILINX Additional Resources e Xilinx website http www xilinx com e Xilinx Answer Browser and technical support WebCase website http www xilinx com support e Xilinx Platform Studio and EDK website http www xilinx com ise embedded design prod platform studio htm e Xilinx Platform Studio and EDK Document website http www xilinx com ise embedded edk docs htm e Xilinx XPS EDK Supported IP website http www xilinx com ise embedded edk ip htm e Xilinx EDK Example website http www xilinx com ise embedded edk examples htm e Xilinx Tutorial website http www xilinx com support techsup tutorials index htm e Xilinx Data Sheets
28. Program Control Options 0c ene eens Program Trace and Profile Options 6 cece ccc eee Miscellaneous Commands oooooococncccor een eee es Chapter 10 GNU Debugger GDB Tool Usage suorrrtaneay rra rbd ad ai TOO ODDS a iaa Debug Flow using GDB a cae eee a ry re I e a a Additional Resources us esee Rn MicroBlaze GDB Targets iii PELUCHE eas CU UC RARA Simulator Target inicia del dd bi Hardware Tagget iii A Tu pe eret Compiling for Debugging on MicroBlaze Targets 0 0 eee eee eee ee PowerPC 405 Vance 5 525 ios icr AA Hadi EE eO AAA AIDA PowerPC 440 Targets scsi RA ee ada RR Console Mode epa eren pube tees aces gh hee eae RE dae Rea eet GDB Command Reference na n nananana naaar raaraa rarer Chapter 11 Bitstream initializer Bitlnit VervieW toria ONG AAA A Ke ICE A A Tool Usage iia ria id da Tool ODUODE vii ia A RARAS Chapter 12 System ACE File Generator GenACE ASSUIMPUONS ra AAA AAA AAA TA AAA AAA Tool Requirements cios rok REX RR E an Gen ACE Fealifes oesdesd eod gd pat Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 13 EZ XILINX USES M 209 Supported Target Boards in Genace tcl Script oo ooooocoomoocmmmmmmo o 210 Generating ACE Files ooo a E a ed 211 For Custom Boards koe re epe HE er pe e e Ie ib 211 Single FPGA Device rsss oeseso s deeeetebrb a 211 Hardware an
29. RO sub Rd Ra Rb Replace by instruction rsub Rd Rb Ra www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX MicroBlaze Linker Options The mb 1d linker for the MicroBlaze soft processor provides additional options to those supported by the GNU compiler tools The options are summarized in this section defsym TEXT START ADDR value By default the text section of the output code starts with the base address 0x28 0x800 in XMDStub mode This can be overridden by using the defsym TEXT START ADDR option If this is supplied to mb gcc compiler the text section of the output code starts from the given value You do not have to use defsym TEXT START ADDR if you want to use the default start address set by the compiler This is a linker option and should be used when you invoke the linker separately If the linker is being invoked as a part of the mb gcc flow you must use the following option Wl defsym W1 TEXT START ADDR value relax This is a linker option that removes all unwanted imm instructions generated by the assembler The assembler generates an imm instruction for every instruction where the value of the immediate cannot be calculated during the assembler phase Most of these instructions do not need an imm instruction These are removed by the linker when the relax command line option is provided This option is required only when linker is in
30. Write and read 1 mem update addr f ff write addr ffff8020 be 1100 0000 write addr ffff8022 be 0011 0000 write addr ffff8024 be 0000 1100 write addr ffff8026 be 0000 0011 read addr fff read addr fff read addr fff read addr fff Write and read 8 mem update addr fff 8020 be 1100 0000 F 8022 be 0011 0000 F 8024 5be 0000 1100 F 8026 be 0000 0011 write addr ffff8030 be 1000 0000 write addr ffff8031 be 0100 0000 write addr ffff8032 be 0010 0000 write addr ffff8033 be 0001 0000 write addr ffff8034 be 0000 1000 write addr ffff8035 be 0000 0100 write addr ffff8036 be 0000 0010 write addr ffff8037 be 0000 0001 read addr ffff8030 be 1000 0000 read addr ffff8031 be 0100 0000 read addr ffff8032 be 0010 0000 read addr ffff8033 be 0001 0000 8014 size 0000 be z00001111 F8010 data 11111111 22222222 6 bit data using byte enable architecture 8020 data 33334444 55556666 bit data using byte enable architecture 8030 data 778899aa bbccadee Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 81 Chapter 5 Bus Functional Model Simulation XILINX read read read read addr ffff8034 be 0000 1000 addr ffff8035 be 0000 0100 addr ffff8036 be 0000 0010 addr ffff8037 be 0000 0001 Write and read a 16 word line mem update mem update mem update mem update mem update mem update mem update addr fff addr fff addr
31. XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION Embedded System Tools Reference Manual www xilinx com UG111 September 16 2009 XILINX Preface About This Guide Welcome to the Embedded Development Kit EDK This product provides you with a full set of design tools and a wide selection of standard peripherals required to build embedded processor systems based on the MicroBlaze soft processor and PowerPC hard processor This guide contains information about the embedded system tools included in EDK These tools consisting of processor platform tailoring utilities software application development tools a full featured debug tool chain and device drivers and libraries allow you to fully exploit the power of MicroBlaze and PowerPC processors along with their corresponding peripherals Guide Contents This guide contains the following chapters e Chapter 1 Embedded System and Tools Architecture Overview e Chapter 2 Platform Specification Utility PsfUtility e Chapter 3 Platform Generator Platgen e Chapter 4 Command Line no window Mode
32. XMD stp fffffc70 XMD stp fffffc 74 XMD mrd OxFFFFCOO00 5 FFFFCOO00 00000000 FFFFCOO04A 00000000 FFFFCO008 00000000 FFFFCOOC 00000000 FFFFCO10 00000000 id 0 51c6832a a2c94315 00000003 00000003 51c6832a a2c94315 45401007 8a80200b 00000000 00000000 c000007f ffffe204 a06ea671 00000000 00000000 81000000 ffffe204 00000000 00000000 ffffe204 ffffe204 51c6832a a2c94315 00000003 00000003 51c6832a a2c94315 45401007 8a80200b 00000000 XMD mwr OxFFFFCO04 Oxabcd1234 2 XMD mwr OxFFFFCO10 0xa5a50000 XMD mrd OxFFFFCOO0 5 FFFFCOO0 00000000 FFFFCO04 ABCD1234 FFFFCOO08 ABCD1234 FFFFCOOC 00000000 FFFFCO10 A5A50000 XMD XMD id r16 bag ris 19 r20 e215 r22 r23 cr pvr sprg3 tbu evpr srr2 iacl deer sgr dvcl sler sprg7 r16 r17 rig r19 r20 x21 r22 r23 0 at TCP port no 00000804 00000408 f7c7dfcd fbcbefce 0040080d 0080040e c1200004 c2100008 00000000 20010820 ffffe204 00000010 ffff0000 00000000 ffffe204 00000000 Eftttftf ffffe204 00000000 ffffe204 00000804 00000408 f7c7dfcd fbcbefce 0040080d 0080040e c1200004 c2100008 r24 x25 r26 x27 r28 r29 r30 EST Ir sprg0 srr0 icdbdr ESES srr3 iac2 icer dcwr dvc2 sprg4 suOr r24 r25 r26 x27 r28 r29 r30 x31 1234 32a08800 31504400 82020922 41010611 fe0006f0 fd0009f0 00000003 00000003 ef0009f8 ffff
33. etnia ee etek eee a a a aie Nee o 154 XMD Command Reference ssssseeee rreraren 154 XMD User Command Summary 6666s 154 XMD User Commands sess 155 Special Purpose Register Names ssss en 160 MicroBlaze Special Purpose Register Names o ooooooccocccoococccr eee 160 PowerPC 405 Processor Special Purpose Register Names oooooooooooooo 161 PowerPC 440 Processor Special Purpose Register Names oooooooooooooo 162 XMD Reset Sequence oooooooooorrr nne 162 PowerPC 405 Processors eddie em ede RD esee oe etate EEE Recent d 163 PowerPC 440Processors sees eee ehh hrs 163 Mi CKO BLAZE i e eade ee entes go di ecd s die eee rd ne aes Me e CR e n 163 Recommended XMD Flows ssseeeeeee an 164 Debug eine a Program ntc iia onere eee rep de eek data 164 Debugging Programs in a Multi processor Environment oooocococococc o 164 Running a Program in a Debug Session 6 00 ccc eee ees 165 Using Safemode for Automatic Exception Trapping 00 00 eee 165 Processor Default Exception Settings 0 c eee ccc 165 Overwriting Exception Settings nne 167 Viewing Safemode Settings 0 0 6 c ccc eee eens 167 Connect Command Options suus eese 168 D A A A ai 168 PowerPC Processor Targets oooooooocooororrronrra arar 168 PowerPC Processor Hardware Connection 00 ccc eee eee eee reel 168 PowerP
34. handle contains MLD information also Software Read Access APIs This section lists the software Read Access APIs The following is a summary of the APIs which you can click on to go to the API description The descriptions follow the summary list Software Read Access API Summary Table C 4 Software Read Access APIs xget_sw_array_handle lt handle gt lt array_name gt xget_libgen_proc_handle xget_sw_array_element_handle lt handle gt lt element_name gt xget_sw_driver_handle lt mss_handle gt lt driver_name gt xget_sw_driver_handle_for_ipinst lt merged_processor_handle gt lt ipinst_name gt xget_sw_function_handle lt handle gt lt function_name gt xget_sw_ipinst_handle lt handle gt lt ipinst_name gt xget_sw_ipinst_handle_from_processor lt ipinst_name gt lt merged_processor_handle gt xget_sw_iplist_for_driver lt merged_driver_handle gt xget_sw_interface_handle lt handle gt lt interface_name gt xget_sw_library_handle lt mss_handle gt lt library_name gt xget_sw_mdd_handle lt handle gt xget sw mld handle lt handle gt xget sw name handle xget sw parameter handle handle parameter name xget sw parameter value handle parameter name xget sw os handle mss handle os name xget sw option handle handle option name xget sw option value handle option name xget sw parent handle handle xget sw processor handle mss handle processor name xget sw
35. http www xilinx com support documentation data sheets htm e Xilinx Problem Solvers http www xilinx com support troubleshoot psolvers htm e Xilinx ISE Manuals http www xilinx com support software manuals htm e Additional Xilinx Documentation http www xilinx com support library htm e GNU Manuals http www gnu org manual Conventions This document uses the following conventions An example illustrates each convention Typographical Conventions The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and program files that i f arene FORE the system displays speed grade 100 Literal commands that you enter in a Courier bold syntactical statement Descriptive text will ngdbuild design name also reflect this convention Commands that you select from a menu File Open Helvetica bold Keyboard shortcuts Ctrl C 4 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Conventions Convention Italic font Meaning or Use Variables in a code syntax statement for which you must supply values Text within descriptions will also reflect this convention Example ngdbuild design name References to other manuals Refer To the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it ov
36. memory allocation routines allocate memory from this section This section must be mapped to RAM Stack This section contains uninitialized data that is used as the program stack This section must be mapped to RAM This section is typically laid out right after the heap section In some versions of the linker the stack and heap sections might appear merged together into a section named bss stack init This section contains language initialization code and has the same flags as text It must be mapped to initialized ROM Embedded System Tools Reference Manual www xilinx com 123 UG111 EDK 11 3 1 XILINX 124 Common Compiler Usage and Options fini This section contains language cleanup code and has the same flags as text It must be mapped to initialized ROM ctors This section contains a list of functions that must be invoked at program startup and the same flags as data and must be mapped to initialized RAM dtors This section contains a list of functions that must be invoked at program end the same flags as data and it must be mapped to initialized RAM got2 got This section contains pointers to program data the same flags as data and it must be mapped to initialized RAM eh frame This section contains frame unwind information for exception handling It contains the same flags as rodata and can be mapped to initialized ROM tbss This section holds uninitialized thread lo
37. nPLB rdPrim in std logic BI nPLB SAValid in std logic BI nPLB wrPrim in std logic BI nPLB wrBurst in std logic BI nPLB wrDBus in std logic vector 0 to C BI PLB DWIDTH 1 BI nPLB rdBurst in std logic PLB size in std logic vector 0 to 3 IPLB size in std logic vector 0 to 3 DPLB size in std logic vector 0 to 3 Master PLBV4 6 ports Master PLBV4 6 ports must use the naming conventions shown in the following table Table 2 14 Master PLBV46 Port Naming Conventions M Prefix for the master output PLB M Prefix for the master input BI A bus identifier Optional for peripherals with a single master PLBV46 port and required for peripherals with multiple master PLBV46 ports For peripherals with multiple master PLBV46 ports the BI strings must be unique for each bus interface Trailing underline character in the BI string are ignored 50 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility 7 XILINX PLB v4 For interconnection to the PLB v4 6 masters must provide the following outputs PLB v4 6 Master Outputs lt BI gt M_abort ou lt BI gt M_ABus ou BI M UABus ou BI M BE ou lt BI gt M_busLock ou lt BI gt M_lockErr ou lt BI gt M_MSize ou lt BI gt M_priority ou lt BI gt M_rdBurst ou lt BI gt M_request ou lt BI
38. out std logic lt BI gt lt S1n gt _wrBTerm out std logic lt BI gt lt S1n gt _wrComp out std logic lt BI gt lt S1n gt _wrDAck out std logic Examples Tmr addrAck out std logic Uart addrAck out std logic Intc addrAck out std logic 1 Deprecated in this release ERS 1 ERS 1 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 49 EZ XILINX Conventions for Defining HDL Peripherals PLB Slave Inputs For interconnection to the PLB slaves must provide the following inputs Examples BI nPLB Clk in std logic BI nPLB Rst in std logic BI nPLB ABus in std logic vector 0 to C BI PLB AWIDTH 1 BI nPLB BE in std logic vector 0 to C BI PLB DWIDTH 8 1 BI nPLB PAValid in std logic BI nPLB RNW in std logic BI nPLB abort in std logic BI nPLB busLock in std logic BI nPLB compress in std logic BI nPLB guarded in std logic BI nPLB lockErr in std logic BI nPLB masterID in std logic vector 0 to C BI PLB MID WIDTH 1 BI nPLB MSize in std logic vector 0 to 1 BI nPLB ordered in std logic BI nPLB pendPri in std logic vector 0 to 1 BI nPLB pendReq in std logic BI regpri in std logic vector 0 to 1 BI nPLB size in std logic vector 0 to 3 BI nPLB type in std logic vector 0 to 2 BI
39. priority out std logic vector 0 to 1 BI Mn rdBurst out std logic BI Mn request out std logic BI Mn size out std logic vector 0 to 3 BI Mn type out std logic vector 0 to 2 BI Mn wrBurst out std logic BI Mn wrDBus out std logic vector 0 to C BI PLB DWIDTH 1 Examples IM request out std logic Bridge request out std logic O20b request out std logic PLB Master Inputs For interconnection to the PLB masters must provide the following inputs BI nPLB Clk in std logic BI nPLB Rst in std logic BI nPLB AddrAck in std logic BI nPLB Busy in std logic BI nPLB Err in std logic BI nPLB RdBTerm in std logic BI nPLB RdDAck in std logic BI nPLB RdDBus in std logic vector 0 to C BI PLB DWIDTH 1 BI nPLB RdWdAddr in std logic vector 0 to 3 BI nPLB Rearbitrate in std logic BI nPLB SSize in std logic vector 0 to 1 BI nPLB WrBTerm in std logic lt BI gt lt nPLB gt _WrDAck in std logic Examples IPLB MBusy in std logic Bus1_PLB MBusy in std logic 48 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility 7 XILINX Slave PLB 1 Ports Slave PLB ports must follow the naming conventions shown in the following table Table 2 13 Slave PLB Port Nami
40. std_logic std_logic std_logic std_logic_vector 0 to 3 std_logic std_logic_vector 0 to 1 std_logic in std_logic in std_logic Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 51 EZ XILINX Conventions for Defining HDL Peripherals Slave PLBV46 ports The following table shows the required naming conventions for Slave PLBV4 6 ports Table 2 15 Slave PLBV46 Port Naming Conventions S1 Prefix for the slave output PLB Prefix for the slave input BI A bus identifier Optional for peripherals with a single slave PLBV46 port and required for peripherals with multiple slave PLBV46 ports For peripherals with multiple PLBV46 ports the BI strings must be unique for each bus interface Trailing underline character in the Br string are ignored PLBV46 Slave Outputs For interconnection to the PLBV4 6 slaves must provide the following outputs lt BI gt S1_addrAck out std_logic lt BI gt S1_MBusy out std_logic_vector 0 to C_ lt BI SPLB gt _NUM_MASTERS 1 lt BI gt S1_MRdErr out std_logic_vector 0 to C_ lt BI SPLB gt _NUM_MASTERS 1 lt BI gt S1_MWrErr out std_logic_vector 0 to C BI SPLB NUM MASTERS 1 lt BI gt S1_MIRO out std logic lt BI gt S1_rdBTerm out std logic lt BI gt S1_rdComp out std_logic lt BI gt S1_rdDAck out std logic lt BI gt S1_rdDBus out std logic vector 0 to C
41. void XIntc Disable Xintc InstancePtr u8 Id Description Parameters Disables the interrupt source provided as the argument Id such that the interrupt controller will not cause interrupts for the specified Id The interrupt controller will continue to hold an interrupt condition for the Id but does not cause an interrupt InstancePtris a pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR INTC MAX NUM INTR INPUTS 1 with 0 being the highest priority interrupt int XIntc Start XIntc InstancePtr u8 Mode Description Parameters Starts the interrupt controller by enabling the output from the controller to the processor Interrupts can be generated by the interrupt controller after this function is called InstancePtris a pointer to the XIntc instance Mode determines if software is allowed to simulate interrupts or if real interrupts are allowed to occur Modes are mutually exclusive The interrupt controller hardware resets in a mode that allows software to simulate interrupts until this mode is exited It cannot be re entered once it has been exited Mode is one of the following valued XIN SIMULATION MODE enables simulation of interrupts only XIN REAL MODE enables hardware interrupts only This function must be called after Xintc initialization is completed Embedded System Tools Reference Manual UG 111 EDK 11 3 1 www xilinx com 245
42. xm rc file which is located at your home directory Use the command safemode config mode MASK This sets the mask for current target only While debugging a program this is a convenient way to change the trap settings Note The current target is destroyed when you disconnect from the target Viewing Safemode Settings You can view the current safemode setting at any time with the following command safemode info In sa emode XMD sets the breakpoint at the exception handlers that you want to trap For MicroBlaze all exceptions take PC to 0x20 For PowerPC processors XMD needs to detect the exception handler locations from the ELF file The detection works on most Standalone or Xilkernal projects If another software platform is used the detection might fail In such cases set the exception handler address with the command safemode config exception id exception handler addr Embedded System Tools Reference Manual www xilinx com 167 UG111 EDK 11 3 1 7 XILINX Connect Command Options Connect Command Options XMD can debug programs on different targets processor or peripheral e When communicating with a target XMD connects to the target and a unique target ID is assigned to each target after connection e When connecting to a processor the gdbserver starts enabling communication with GDB or SDK Usage connect mb ppc mdm Connection Type Options Table 9 7 Connect Command Option
43. 0 and store the value in an internal sub property called RESOLVED ISVALID on that property e RESOLVED BUS If a port or parameter in an IP has a colon separated list of buses specified in the Bus tag that it can be associated with in the MPD file the tools analyze the connectivity of that IP and determine to which of those buses the IP is connected and store the name of that bus interface in the RESOLVED BUS tag 290 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Flow During Software Platform Generation XILINX Tcl Flow During Software Platform Generation Driver and library configuration occurs via a data definition file MDD or MLD and a corresponding data generation Tcl file The Tcl file has procedures defined within Each of these procedures can use both software and hardware access commands The Tcl procedures run as part of the Libgen automated software generation The following sections explain the interaction of Libgen and the various Tcl procedures for a driver or library The Tcl procedures can access the system data structure through handles For more information refer to Understanding Handles on page 256 Input Files Libgen works with the input files MSS or MHS and the data files MPD MDD MLD or Tcl of IPs drivers OSs processors and libraries It creates the system view based on these files Each of the drivers OSs processors and librari
44. 0x400 dow data system dat 0x400 elf verify executable elf Downloads the given ELF or data file with the data option onto the memory of the current target e Ifno address is provided along with the ELF file the download address is determined from the ELF file by reading its headers Note Only those segments of the ELF file that are marked LOAD are written to memory If an address is provided with the ELF file on MicroBlaze targets only itis treated as Position Independent Code PIC code and downloaded at the specified address Also the R20 Register is set to the start address according to the PIC code semantics When an ELF file is downloaded the command does a reset stops the processor at the reset location by using breakpoints and loads the ELF program to the memory The reset is done to ensure the system is in a known good state The reset behavior can be configured using debugconfig reset_on run system enable processor enable disable Refer to the Configure Debug Session on page 189 Verify if the executable elf is downloaded correctly to the target If ELF file is not specified it uses the most recent ELF file downloaded on the target fpga f lt bitstream gt cable cable options fpga f download bit fpga f download bit Loads the FPGA device bitstream Optionally specify the cable JTAG configuration and debug device options configdevice cable type
45. 0x70020000 0x70023fff Connected to ppc target id 0 Starting GDB server for ppc target id 0 at TCP port no 1234 XMD targets System 0 Hardware System on FPGA Device 5 Targets Target 0 PowerPC440 1 Hardware Debug Target XMDS 174 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Example with a Program Running in ISOCM Memory and Accessing DCR Registers This example demonstrates a simple debug session with a program running on ISOCM memory of the PowerPC 405 processor target The ISOCM address parameters can be specified during the connect command If the XMP file is loaded XMD infers the ISOCM address parameters of the system from the MHS file Note In a Virtex 4 device ISOCM memory is readable This enables better debugging of a program running from ISOCM memory XMD connect ppc hw debugdevice isocmstartadr OxFFFFE000 isocmsize 8192 isocmdcrstartadr 0x15 dcrstartadr 0xab000000 JTAG chain configuration Device ID Code IR Length Part Name 1 0a001093 8 System_ACE 2 5059093 16 XCF32P 3 01e58093 10 XC4VFX12 4 49608093 8 xc95144xl PowerPC405 Processor Configuration VES TON edee see kom a aa 0x20011430 User IDe iia eb 0x00000000 No of PC Breakpoints 4 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 TSOCM veu ur uen Meee ee Ea Oxffffe000 Oxffffffff Us
46. 1 page 21 e Ability to generate and view a system block diagram and or design report e Project management support e Process and tool flow dependency management e Ability to export hardware specification files for import into SDK For more information on files and their formats see the Platform Specification Format Reference Manual which is linked in Additional Resources page 18 Refer to the Xilinx Platform Studio Help for details on using the XPS GUI The following subsections describe the tool and utility components of XPS 22 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX EDK Overview The Base System Builder BSB Wizard The BSB wizard helps you quickly build a working system Some embedded design projects can be completed using the BSB wizard alone For more complex projects the BSB wizard provides a baseline system that you can then customize to complete your embedded design BSB wizard can generate a single processor design for the supported processor types and dual processor designs for MicroBlaze For efficiency in project creation Xilinx recommends using the BSB wizard in every scenario Based on the board you choose the BSB wizard allows you to select and configure basic system elements such as processor type debug interface cache configuration memory type and size and peripheral selection BSB provides functional default values pre selected in the wizard that c
47. 91 XILINX Simgen Syntax Table 6 1 Simgen Syntax Options Cont d Option Processor ELF Files Command pe proc instance elf file elf file Description Specifies a list of ELF files to be associated with the processor with instance name as defined in the MHS Simulator s mti ncs Generates compile script and helper scripts for vendor simulators ModelSim and NcSim The option are ModelSim mti ncs NcSim Source Directory sd source dir Specifies the source directory to search for netlist files Testbench Template tb Creates a testbench template file Use ti and tm to define the design under test name and the testbench name respectively Top Level Instance ti top instance When a testbench template is requested use top instance to define the instance name of the design under test When design represents a sub module use top instance forthe top levelinstance name Top Level Module tm top module When a testbench template is requested use top module to define the name of the testbench When the design represents a sub module use top module for the top level entity module name Top Level toplevel yes no yes Design represents a whole design no Design represents a level of hierarchy sub module Default yes Version v Displays the version and then quits Xilinx Library Directory
48. BreakpointS ses 4 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 User Defined Address Map to access Special PowerPC Features using XMD I Cache Data 0x70000000 0x70003fff I Cache TAG 0x70004000 0x70007fff D Cache Data 0x78000000 0x78003fff D Cache TAG 0x78004000 0x78007fff DOR aesensbeneseemees 0x78004000 0x78004fff MiB 0x70004000 0x70007 f 172 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD 7 XILINX Connected to ppc target Starting GDB server for ppc target XMD rrd r0 ef0009f8 r8 r1 00000003 r9 r2 fe008380 r os r3 fd004340 rii r4 0007a120 x12 r5 000b5210 r13 r6 51c6832a x14 r7 a2c94315 ribs pc ffff0700 msr XMD srrd pc ffff0700 msr Gtr fffffftf xer sprgl ffffe204 sprg2 srr1 00000000 tbi esr 88000000 dear tcr 00000000 pit dbsr 00000300 dbcr0 dacl ffffe204 dac2 zpr 00000000 pid ccr0 00700000 dberi iac3 ffffe204 iac4 sprg5 ffffe204 sprg6 usprg0 ffffe204 XMD rst Sending System Reset Target reset successfully XMD rwr 0 OxAAAAAAAA XMD rwr 1 0x0 XMD rwr 2 0x0 XMD rrd r0 aaaaaaaa r8 r1 00000000 x91 r2 00000000 r10 r3 fd004340 ril r4 0007a120 r12 r5 000b5210 r13 r6 51c6832a rl4 r7 a2c94315 153 pe fffffffe msr XMD mrd OxFFFFFFFC FFFFFFFC ABFFFC74
49. Command Options Cont d Option Name Description clean Delete the all tool generated files and directories download Download the bitstream onto the FPGA hwclean Delete the implementation directory init_bram Update the bitstream with block RAM initialization information libs Generate the software libraries libsclean Delete the software libraries netlist Generate the netlist netlistclean Delete the NGC or EDN netlist program Compile your program into Executable Linked Format ELF files programclean Delete the ELF files resync Update any MHS file changes into the memory sim Generate the simulation models and run the simulator simmodel Generate the simulation models without running the simulator swclean Calls 1ibsclean and programclean simclean Delete the simulation directory Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 65 7 XILINX Reloading an MHS File Reloading an MHS File All EDK design files refer to MHS files Any changes in MHS files have impact on other design files If there are any changes in the MHS file after you loaded the design use the command run resync This causes XPS to re read MHS MSS and XMP files Adding a Software Application You can add new software application projects in an XPS batch using the xadd_swapp command When adding a new software application you must specify a name for t
50. Components BEGIN plb_v34 PARAMETER HW_VE PARAMETER C DCR PORT PLB Clk PORT SYS Rst END Sys reset DIR PARAMETER INSTANCE myplb R 1 01 a _INTFCE 0 sys_clk sys reset 76 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX PLB BFM Component Instantiation BEGIN plb bram if cntlr PARAMETER INSTANCE myplb bram cntlr PARAMETER HW VER 1 00 a PARAMETER C BASEADDR OxFFFF8000 PARAMETER C HIGHADDR OxFFFFFFFF BUS INTERFACE PORTA porta BUS INTERFACE SPLB myplb END BEGIN bram block PARAMETER INSTANCE braml PARAMETER HW VER 1 00 a BUS INTERFACE PORTA porta END BEGIN plb master bfm PARAMETER INSTANCE my master PARAMETER HW VER 1 00 a PARAMETER PLB MASTER ADDR LO 0 OxFFFF0000 PARAMETER PLB MASTER ADDR HI 0 OxFFFFFFFF BUS INTERFACE MPLB myplb PORT SYNCH OUT synch0 PORT SYNCH IN synch ND E BEGIN plb slave bfm PARAMETER INSTANCE my slave PARAMETER HW VER 1 00 a PARAMETER PLB SLAVE ADDR LO O0 OxFFFFO0000 PARAMETER PLB SLAVE ADDR HI 0 OxFFFF7FFF BUS INTERFACE SPLB myplb PORT SYNCH OUT synch1 PORT SYNCH IN synch ND E BEGIN plb monitor bfm
51. For more details about linker options refer to Linker Options page 120 If the start address is defined to be less than 0x800 XMD issues an address overlap error e crtl oisusedas the initialization file The crt1 o file returns the control back to the XMDStub when your program execution is complete Note Use x1 mode xmdstub for designs when XMDStub is part of the bitstream Do not use this mode when the system is complied for No Debug or when Hardware Debugging is turned ON For more details on debugging with XMD refer to Chapter 10 GNU Debugger GDB xl mode bootstrap This option is used for applications that are loaded using a bootloader Typically the bootloader resides in non volatile memory mapped to the processor reset vector If a normal executable is loaded by this bootloader the application reset vector overwrites the reset vector of the bootloader In such a scenario on a processor reset the bootloader does not execute first it is typically required to do so to reload this application and do other initialization as necessary To prevent this you must compile the bootloaded application with this compiler flag On a processor reset control then reaches the bootloader instead of the application www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Using this switch on an application that is deployed in a scenario different from the one
52. Manual www xilinx com 241 UG 111 EDK 11 3 1 XILINX 242 Appendix B Interrupt Management 5 Onsystems with an interrupt controller the next level handler is the handler provided by the interrupt controller driver This handler queries the interrupt controller for all active interrupts in the system For each active interrupt it consults its internal vector table which contains the user registered handler for each interrupt line If no handler is registered a default do nothing handler is registered The registered handler for each interrupt gets invoked in turn in interrupt priority order 6 On systems without an interrupt controller the next handler is the final interrupt handler that is executed by the application 7 The final interrupt handler for a particular interrupt typically queries the interrupting peripheral and determines the cause for the interrupt It usually does a series of actions that are appropriate for the given peripheral and the cause for the interrupt The handler is also responsible for acknowledging the interrupt at the interrupting peripheral When the interrupt handler completes its activity it returns back and the interrupt stack gets unwound back to the software platform level interrupt handler The platform level interrupt handler restores the registers that it saved on the stack and returns control back to the Program Counter PC location where the interrupt occurred The return instruction als
53. MicroBlaze processor 246 www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software APIs 7 XILINX MicroBlaze Interrupt Setup Example The following program provides an example of how interrupts are initialized on MicroBlaze when an interrupt controller is present The software example assumes that e There is an xps_timer peripheral named xps_timer_0 present in the system e The interrupt signal from the timer is connected to an xps_intc interrupt controller named xps_intc_0 that is present in the system e The interrupt signal from the interrupt controller is connected to the MicroBlaze external interrupt port include include include include mb interface h xparameters h xtmrctr h xintc h XIntc sys intc XTmrCtr sys tmrctr void my timer handler XUint32 ControlStatusReg Read the new Control Status Register content 7 ControlStatusReg XTimerCtr mReadReg sys tmrctr BaseAddress 0 XTC TCSR OFFSET Acknowledge the interrupt by clearing the interrupt bit in the timer control status register XTmrCtr mWriteReg sys tmrctr BaseAddress O0 XTC TCSR OFFSET ControlStatusReg XTC CSR INT OCCURED MASK print Timer interrupt occurred r n int main XStatus Status Initialize the interrupt controller driver so that it is ready to use specify the device ID that is generated in xparame
54. OUT C NUM SYNCH 3 BFM Synch TO SYNCH IN X10850 Figure 5 4 BFM Synchronization Bus Usage Embedded System Tools Reference Manual www xilinx com 79 UG111 EDK 11 3 1 Chapter 5 Bus Functional Model Simulation XILINX Note OPB Bus Functional Language Usage FILE sample bfl This example initializes an OPB master Initialize my device Note The instance name for my device is duplicated in the path due to the wrapper level inserted by the tools set device path system my device my device device device type opb device The following is a sample BFL file written for the OPB BFM Component Instantiation page 75 which instantiates OPB BFM components Write and read 32 bit data using byte enable architecture Note The CoreConnect opb device is a 64 bit device hence the 8 bit byte enables are aligned accordingly 100 be 11110000 da 104 be 00001111 da 100 be 11110000 da 104 be 00001111 da write addr ffff0 write addr ffff0 read addr ffff0 read addr ffff0 Write and read write addr ffff0 read addr ffff0 write addr ffff0 read addr ffff01 Write and read write addr ffff01 read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 r
55. PARAMETER INSTANCE my monitor PARAMETER HW VER 1 00 a BUS INTERFACE MON PLB myplb PORT SYNCH OUT synch2 PORT SYNCH IN synch END BEGIN bfm synch PARAMETER INSTANCE my synch PARAMETER HW VER 1 00 a PARAMETER C NUM SYNCH 3 PORT TO SYNCH IN synch END PORT FROM SYNCH OUT synch0 amp synchl synch2 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 77 Chapter 5 Bus Functional Model Simulation XILINX PLB v4 6 BFM Component Instantiation The following is an example MHS file that instantiates PLB v4 6 BFM components and the BFM synchronization bus Parameters PARAMETER VERSION 2 1 0 Ports PORT sys clk sys clk DIR I SIGIS CLK PORT sys reset sys reset DIR IN Components BEGIN plb v46 PARAMETER INSTANCE myplb PARAMETER HW VER 1 01 a PARAMETER C DCR INTFCE 0 PORT PLB_C1k sys clk PORT SYS Rst sys reset END BEGIN plb bram if cntlr PARAMETER INSTANCE myplbbram cntlr PARAMETER HW VER 1 00 a PARAMETER C BASEADDR OxFFFF8000 PARAMETER C HIGHADDR OxFFFFFFFF BUS INTERFACE PORTA porta BUS INTERFACE SPLB myplb BEGIN bram block PARAMETER INSTANCE braml PARAMETER HW VER 1 00 a BUS INTERFACE PORTA porta END BEGIN plbv46 master bfm PARAMETER INSTANCE my master PARAMETER HW V
56. Reference Manual www xilinx com 249 UG 111 EDK 11 3 1 XILINX Appendix B Interrupt Management void XExc RegisterHandler Xuint8 Exceptionld XExceptionHandler Handler void DataPtr Description Parameters This function registers a handler invoked from the Standalone software platform exception handler when an exception occurs in the system Interrupts are one kind of exception that the processor can handle Hence this function can be used to register interrupt handlers When no interrupt controller is present this function would be used to directly register the final interrupt handler for the application When an interrupt controller is present this function registers the interrupt handler for the controller driver XIntc DeviceInterruptHandler thus enabling vectoring of interrupts by the interrupt controller driver ExceptionIdis the identifier for the exception for which a handler is being registered The two exception identifiers that correspond to critical and non critical external input interrupts on the PowerPC processors are XEXC ID CRITICAL INT and XEXC ID NON CRITICAL INT Handler is the handler function to be invoked DataPtris the callback value that will be passed to the function when it is invoked void XExc mEnableExceptions EnableMask Description Parameters This function enables the specified set of exception categories on the PowerPC processor EnableMaskis the set of exception categori
57. Section Small Read Only Data Section Small Read Only Uninitialized Data Section Read Write Data Section Small Read Write Data Section Small Uninitialized Data Section Uninitialized Data Section Program Heap Memory Section Program Stack Memory Section Figure 8 1 Sectional Layout of an Object or Executable File X11005 The reserved sections that you would not typically modify include init fini ctors dtors got got2 and eh frame text This section of the object file contains executable program instructions This section has the x executable r read only and i initialized flags This means that this section can be assigned to an initialized read only memory ROM that is addressable from the processor instruction bus rodata This section contains read only data This section has the r read only and the i initialized flags Like the text section this section can also be assigned to an initialized read only memory that is addressable from the processor data bus 122 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Sdata2 This section is similar to the rodata section It contains small read only data of size less than 8 bytes AII data in this section is accessed with reference to the read only small data anchor This ensures that all the contents of this section are accessed using a single instruction You can change the size of
58. The EDK GNU tools support both the C and C languages The MicroBlaze GNU tools include mb gcc and mb g compilers mb as assembler and mb 1d linker The PowerPC processor tools include powerpc eabi gcc and powerpc eabi g compilers powerpc eabi as assembler and the powerpc eabi 1d linker The toolchains also include the C Math GCC and C standard libraries The PowerPC and MicroBlaze processor GCC tools are constructed using open source GCC 4 1 1 sources The compiler also uses the common binary utilities referred to as binutils such as an assembler a linker and object dump The PowerPC and MicroBlaze compiler tools use the GNU binutils based on GNU version 2 16 of the sources The concepts options usage and exceptions to language and library support are described Appendix A GNU Utilities Additional Resources GNU Information GCC 4 1 1 release feature references http gcc gnu org onlinedocs gcc 4 1 1 gcc Invoking the compiler for different languages http gcc gnu org onlinedocs gcc 4 1 1 gcc Invoking G 002b 002b html Invoking G 002b 002b Embedded System Tools Reference Manual www xilinx com 109 UG111 EDK 11 3 1 7 XILINX Compiler Framework e GCC online manual http www gnu org manual manual html e GNU C standard library http gcc gnu org onlinedocs libstdc documentation html e GNU linker scripts http www gnu org software binutils PowerPC Informa
59. The default memory size is 64 KB Simulator Target Requirements To debug programs on the Cycle Accurate Instruction Set Simulator using XMD you must compile programs for debugging and link them with the startup code in crt0 o The mb gcc can compile programs with debugging information when it is run with the option g and by default mb gcc links crt0 o with all programs The option is x1 mode executable The program memory size must not exceed 64 K and must begin at address 0 The program must be stored in the first 64KB of memory Note XMD with a simulator target does not support the simulation of OPB peripherals MDM Peripheral Target You can connect to the mdm peripheral and use the UART interface for debugging and collecting information from the system Usage connect mdm uart MDM Target Requirements To use the UART functionality in the MDM target you must set the C USE UART parameter while instantiating the mdm in a system UART input can also be provided from the host to the program running on MicroBlaze using the xuart w byte command You can use the terminal command to open a hyperteminal like interface to read and write from the UART interface The read uart command provides interface to write to STDIO or to file 188 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Configure Debug Session Configure t
60. This option executes the compiler and all the tools underneath the compiler in verbose mode This option gives complete description of the options passed to all the tools This description is helpful in discovering the default options for each tool save temps The GNU compiler provides a mechanism to save the intermediate files generated during the compilation process The compiler stores the following files Preprocessor output input_file_name i for C code and input file name ii for C code Compiler cc1 output in assembly format input file name s Assembler output in ELF format input file name s The compiler saves the default output of the entire compilation as a out o filename The compiler stores the default output of the compilation process in an ELF file named a out You can change the default name using o output file name The output file is created in ELF format Wp option Wa option Wl option The compiler mb gcc or powerpc eabi gcc is a wrapper around other executables such as the preprocessor compiler cc1 assembler and the linker You can run these components of the compiler individually or through the top level compiler www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX There are certain options that are required by tools but might not be necessary for the top level compiler To run these commands use the options listed in th
61. Writes a Profile output file which can be interpreted by mb gprof or powerpc eabi gprof to generate profiling information Specify the profile configuration sampling frequency in Hz histogram bin size and memory address for collecting profile data For details about Profiling using XPS search on Profiling in the Platform Studio Online Help read uart read uart start stop lt TCL Channel ID gt read uart start read uart stop read uart start channel id Theread uart start command redirects the output from the mdm UART interface to an optionally specified TCL channel TCL Channel ID The read uart stop command stops redirection A TCL channel represents an open file or a socket connection The TCL channel should be opened prior to using the read uart command using appropriate TCL commands rrd rrd Reads all registers or reads reg num register rrd reg num rrd r1 or rrd R1 rrd 1 rst rst Resets the system rst processor rst processor If the processor option is specified the current processor target is reset If the processor is not in a Running state use the state command then the processor will be stopped at the processor reset location on reset rwr rwr register number register name Hex value rwr pc 0x400 Registers writes from a register number register name or hex value Embedded System Tools Reference Manua
62. XILINX Software Setup and Interrupt Flow Interrupts are typically vectored through multiple levels in the software platform before the application interrupt handlers are executed The Xilinx software platforms Standalone and Xilkernel follow the interrupt flow shown in the following figure Final peripheral level or application level interrupt handling happens here Application Interrupt Handler Vectoring of individual interrupts to final handlers happens here Acknowledges to the interrupt controller and statistics collection are also options Save and restore of register context happens here Software Platform OS Level Interrupt Vector Located at an address that is either fixed statically or fixed at run time Usually just a branch to the next level vectoring code Lowest Level Interrupt Vector X11018 Figure B 2 Interrupt Flow Interrupt Flow for MicroBlaze Systems MicroBlaze interrupts go through the following flow 1 Interrupts have to be enabled on MicroBlaze by setting appropriate bits in the Machine Status Registers MSR Upon an external interrupt signal being raised the processor first disables further interrupts Then the processor jumps to an absolute fixed address 0x0000 0010 The software platform or OS provides vectoring code at this address which transfers control to the main platform interrupt handler The platform interrupt handler saves all of the process
63. be in a specific directory under YOUR PROJECT bsp or library name bsp as shown in Figure 7 1 on page 102 e The OS_NAME attribute allows you to specify any name for your OS which is also the name of the OS directory e The source files and make file for the OS must be in the src subdirectory under the os name directory e The make file should have the targets include and libs e Each OS must contain an MLD file and a Tcl file in the data subdirectory Look at the existing EDK OSs to understand the structures Refer to the Microprocessor Library Definition MLD chapter in the Platform Specification Format Reference Manual for details on how to write an MLD and its corresponding Tcl file A link to the document is supplied in the Additional Resources page 100 Embedded System Tools Reference Manual www xilinx com 107 UG111 EDK 11 3 1 XILINX OS Block 108 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 8 GNU Compiler Tools This chapter describes the GNU compiler tools and is organized as follows Overview Overview Additional Resources Compiler Framework Common Compiler Usage and Options MicroBlaze Compiler Usage and Options PowerPC Compiler Usage and Options Other Notes EDK includes the GNU compiler collection GCC for both the PowerPC 405 and 440 processors and the MicroBlaze processor
64. by XPS By referring to the examples in the template file and using various auxiliary design support files that are output by the wizard you can start quickly on designing your custom logic In the Import mode this tool creates the interface files and directory structures that are necessary to make your peripheral visible to the various tools in XPS For the Import operation mode it is assumed that you have followed the required XPS naming conventions Once imported your peripheral is available in the XPS peripherals library When you create or import a peripheral XPS generates the Microprocessor Peripheral Definition MPD and Peripheral Analyze Order PAO files automatically e The MPD file defines the interface for the peripheral e The PAO file specifies to Platgen and Simgen what HDL files are required for compilation synthesis or simulation for the peripheral and in the order of those files For more information about MPD and PAO files see the Platform Specification Format Reference Manual A link to the document is available in Additional Resources page 18 For detailed information on using the features provided in the CIP wizard see the Xilinx Platform Studio Help Embedded System Tools Reference Manual www xilinx com 23 UG111 EDK 11 3 1 Chapter 1 Embedded System and Tools Architecture Overview XILINX Platform Specification Utility PsfUtility The PsfUtility enables automatic generation of Microprocessor
65. code segments across multiple smaller memories Remapping frequently executed sections to fast memories Mapping read only segments to non volatile flash memories No restrictions apply to how you can partition your executable The partitioning can be done at the output section level or even at the individual function and data level The resulting ELF can be non contiguous that is there can be holes in the memory map Ensure that you do not use documented reserved locations Alternatively if you are an advanced user who wants to modify the default binary data provided by the tools for the reserved memory locations you can always do so In this case you must replace the default startup files and the memory mappings provided by the linker Embedded System Tools Reference Manual www xilinx com 121 UG111 EDK 11 3 1 7 XILINX Common Compiler Usage and Options Object File Sections An executable file is created by concatenating input sections from the object files o files being linked together The compiler by default creates code across standard and well defined sections Each section is named based on its associated meaning and purpose The various standard sections of the object file are displayed in the following figure In addition to these sections you can also create your own custom sections and assign them to memories of your choice Sectional Layout of an object or an Executable File Text Section Read Only Data
66. debugging tool to control the target processor e You can use an Instruction Set Simulator ISS running on the host computer to debug your code e You can gauge the performance of your system by profiling the execution of your code Device Configuration When your hardware and software platforms are complete you then create a configuration bitstream for the target FPGA device e For prototyping download the bitstream along with any software you require to run on your embedded platform while connected to your host computer e For production store your configuration bitstream and software in a non volatile memory connected to the FPGA Embedded System Tools Reference Manual www xilinx com 19 UG111 EDK 11 3 1 Chapter 1 Embedded System and Tools Architecture Overview XILINX EDK Overview An embedded hardware platform typically consists of one or more processors peripherals and memory blocks interconnected via processor buses It also has port connections to the outside world Each of the processor cores also referred to as pcores or processor IPs has a number of parameters that you can adjust to customize its behavior These parameters also define the address map of your peripherals and memories XPS lets you select from various optional features consequently the FPGA needs only implement the subset of functionality required by your application The following figure provides an overview of the EDK architecture struc
67. described above will not work This mode uses crt2 o as a startup file xl mode novectors This option is used for applications that do not require any of the MicroBlaze vectors This is typically used in standalone applications that do not use any of the processor s reset interrupt or exception features Using this switch leads to smaller code size due to the elimination of the instructions for the vectors This mode uses crt3 o as a startup file Caution Do not use more than one mode of execution on the command line You will receive link errors due to multiple definition of symbols if you do so Position Independent Code The GNU compiler for MicroBlaze supports the fPIC and fpic switches These switches enable Position Independent Code PIC generation in the compiler This feature is used by the Linux operating system only for MicroBlaze to implement shared libraries and relocatable executables The scheme uses a Global Offset Table GOT to relocate all data accesses in the generated code and a Procedure Linkage Table PLT for making function calls into shared libraries This is the standard convention in GNU based platforms for generating relocatable code and for dynamically linking against shared libraries MicroBlaze Application Binary Interface The GNU compiler for MicroBlaze uses the Application Binary Interface ABI defined in the MicroBlaze Processor Reference Guide Refer to the ABI documentation for register and stack us
68. ee EA A A eg 91 Output Files PP LT 93 Memory Initialization sss ee 94 O mara ET Med Um ese REM E 94 Verilog renet ete pae ete a t a bra A eoe RU Eee i op eR depo ren 94 Test Bencles etarra uc bebe bis bens bei ees tap SLE a 94 VHDL Test Bench Example isc e Seba shee dere pee E wae 95 Verilog Test Bench Example 0 006 esie eh n e ah tees 96 Simulating Your Design 5ioracssis gus kke DE EE HERRERA ARIA RETI RE 98 RESTEICHOD S coo Seo ERE rete beet mess aid e ER aw BAe vos dtes 98 Chapter 7 Library Generator Libgen OVERVIEW GET FPEM di ed aa ei did id 99 Additional Resources AM A A 100 SERI rm 100 Tool OpUODS oc i or e Y PE HE PERRO Pape oe edid bea do idu oae 100 Load PANS il cR RO cn UR OUR ree A RE S Mad od 102 PC System Load Paths 66 en 102 Additional Directories iii eee p o g a saddens 102 Search Priority Mechanism 2 066 ccc eee eens 103 OQutp t Files qe PT 104 include Directory i ae eee di Rr Ee b ete i S be e ee t 104 lib Dite CHORY verroes Roe npe ee Tes n Mie sane eg a ected eie d Ha en edes 104 labsre Director ceo eee ere da 104 code Directory 232 s eerte kie ee e an be hace eon et a de Rita 104 Generating Libraries and Drivers 0 000 0 cece cece eee eee 105 OVervieW issses eso kk EAR A pete a ciate creates reek se erede de 105 MDD MED and Tcl sais to a ah ade Shana Y UE PE Rae au 105 MSS Paramelefs casside sse rese d obe e d enee oe aded add dor kde
69. exceptions and or the fno rtti switches This is recommended only for advanced users who know the requirements of their application and understand these language features Refer to the GCC manual for more specific information on available compiler options and their impact C programs might have more intensive dynamic memory requirements stack and heap size due to more complex language features and library routines Many of the C library routines can request memory to be allocated from the heap Review your heap and stack size requirements for C programs to ensure that they are satisfied C Standard Library The C standard defines the C standard library A few of these platform features are unavailable on the default Xilinx EDK software platform For example file I O is supported in only a few well defined STDIN STDOUT streams Similarly locale functions thread safety and other such features may not be supported Note The C standard library is not built for a multi threaded environment Common C features such as new and delete are not thread safe Please use caution when using the C standard library in an operating system environment For more information on the GNU C standard library refer to the documentation available on the GNU website A link to the documentation is provided in Additional Resources page 109 Position Independent Code Relocatable Code The MicroBlaze and PowerPC processor compilers s
70. fff addr fff addr fff addr fff addr fff mem update addr f ff write read addr ffff8080 size 0011 be 1111_ 1111 addr fff F8080 data 01010101 01010101 F8088 data 02020202 02020202 8090 data 03030303 03030303 F8098 data 04040404 04040404 F 80a0 data 05050505 05050505 F80a8 data 06060606 06060606 F80b0 data 07070707 07070707 F80b8 data 08080808 08080808 F 8080 size 0011 be 1111 1111 More information about the PLB Bus Functional Language may be found in the PlbToolkit pdf document in the XILINX EDK third party doc directory Bus Functional Compiler Usage The Bus Functional Compiler provided with the CoreConnect toolkit is a Perl script called BFC The script uses a b crc configuration file which specifies to the script which simulator is used and the paths to the BFMs Xilinx EDK includes a helper executable called xilbfc which enables this configuration for you The helper application has been previously used to verify the correct installation on the BFM Package To compile a BFL file type the following at a command prompt xilbfc sample bfl This creates a script targeted for the selected simulator that initializes the BFM devices In the case of ModelSim it creates a file called sample do 82 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX PLB BFM Component Instantiation Running BFM Simulations To
71. for main and invokes main Invokes destructor functions fini Invokes profile clean to cleanup the profiling library PIDAN Invokes _program_clean and then returns Embedded System Tools Reference Manual www xilinx com 137 UG111 EDK 11 3 1 EZ XILINX MicroBlaze Compiler Usage and Options sim crtinit o This second stage startup file is used when the mno clearbss switch is used in the compiler This startup file performs the following steps 1 Invokes program init Invokes constructor functions init Sets up the arguments for main and invokes main Invokes destructor functions fini me OI Invokes program clean and then returns sim pgcrtinit o This second stage startup file is used during profiling in conjunction with the mno clearbss switch This startup files performs the following steps in order Invokes _program_init Invokes profile init to initialize the profiling library Invokes constructor functions _init Sets up the arguments for main and invokes main Invokes destructor functions fini Invokes profile clean to cleanup the profiling library NO gPROIHML Invokes program clean and then returns Other files The compiler also uses certain standard start and end files for C language support These are crti o crtbegin o crtend o and crtn o These files are standard compiler files that provide the content for the init fini ctors and dtors sect
72. for the current interrupt type and jump to it user or peripheral interrupt handler others function For each active interrupt call the registered interrupt handler t HandlerTable XExc_VectorTable XIntc_DevicelnterruptHandler registered with the OS layer User or peripheral interrupt handlers a registered with the interrupt controller driver X11022 Figure B 6 PowerPC Processor Interrupt Flow with Interrupt Controller This section provides an overview of the software APIs involved in handling and managing interrupts lists the available Software APIs by processor type and provides examples of interrupt management code Note This chapter is not meant to cover the APIs comprehensively Refer to the interrupt controller device driver documentation as well as the Standalone platform s reference documentation to know all the details of the APIs Interrupt Controller Driver The Xilinx interrupt controller supports the following features Enabling and disabling specific individual interrupts Acknowledging specific individual interrupts Attaching specific callback function to handle interrupt source Enabling and disabling the master Sending a single callback per interrupt or handling all pending interrupts for each interrupt of the processor The acknowledgement of the interrupt within the interrupt controller is selectable either prior to calling the device handler or af
73. get a list of IPs of a particular IPTYPE proc xget ipinst handle list for iptype merged mhs handle iptype Get a list of all IPs set ipinst list xget hw ipinst handle merged mhs handle set ret list foreach ipinst ipinst list Get the value of the IPTYPE Option set curiptype xget hw option value ipinst IPTYPE i1 curiptype matches the given iptype then add it to the list that this proc returns if string compare nocase curiptype Siptype O f lappend ret list Sipinst j return ret list www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Example Procedures XILINX Example 2 The following procedure explains how to get the list of cores that are memory controllers in a design Memory controller cores have the tag ADDR_TYPE MEMORY in their address parameter HH Procedure to get a list of memory controllers in a design proc xget hw memory controller handles merged mhs set ret list Gets all MhsInsts in the system set mhsinsts xget hw ipinst handle merged mhs Loop through each MhsInst and determine if it has ADDR_TYPE MEMORY in the parameters foreach mhsinst mhsinsts Gets all parameters of the IP set params xget hw parameter handle mhsinst Loop through each param and find tag ADDR TYPE MEMORY foreach param params if Sparam 0 continue elseif param continue
74. handle For example a Tcl file for a driver would have the following construct defining the generate procedure procedure generate driver_handle e post_generate During the post generate Tcl procedure Libgen calls for all drivers OSs processors and libraries present in the MSS file after the generate Tcl procedure is called Each driver OS processor and library defines this procedure in its Tcl file The procedure is called from Libgen with the corresponding driver OS processor or library handle Embedded System Tools Reference Manual www xilinx com 291 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface For example a Tcl file for a driver has the following construct defining the post generate procedure procedure post generate driver handle y e execs_generate A Tcl procedure that Libgen calls for all drivers OSs processors and libraries present in the MSS file after the post generate Tcl procedure is called Each driver OS processor and library defines this procedure in its Tcl file The procedure is called from Libgen with the corresponding driver processor or library handle For example a Tcl file for a driver would have the following construct defining the execs generate procedure procedure execs generate driver handle A driver OS or library writer can use the read only software access commands and the hardware access commands in any of the Tcl procedures drc generate
75. hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE XFPU SP LITE when this option is given sp full Produces code targeted to the Single precision Full FPU coprocessor This version supports only single precision hardware floating point and uses hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE XFPU SP FULL when this option is given 142 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX dp_lite Produces code targeted to the Double precision Lite FPU coprocessor This version supports both single and double precision hardware floating point and does not use hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE XFPU DP LITE when this option is given dp full Produces code targeted to the Double precision Full FPU coprocessor This version supports both single and double precision hardware floating point and uses hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE XFPU DP FULL when this option is given Caution Do not link code compiled with one variant of the mfpu switch with code compiled with other variants or without the mfpu switch You must use the switch even when you are only linking object files toget
76. idcode 0x22a96093 irlength 10 partname xc5vlx50t configdevice devicenr 2 idcode 0x22a96093 irlength 10 partname xc5vlx50t configdevice devicenr 3 idcode 0x22a96093 irlength 10 partname xc5vlx50t debugdevice devicenr 2 cpunr 1 target mdm elf executable2 elf This generates the SVF file pga2 sw svf 4 Generate an SVF file for the software on the third FPGA device The options file contains the following jprog ace fpga3_sw ace board user configdevice devicenr 1 idcode 0x22a96093 irlength 10 partname xc5vl1x50t configdevice devicenr 2 idcode 0x22a96093 irlength 10 partname xc5vlx50t configdevice devicenr 3 idcode 0x22a96093 irlength 10 partname xc5vlx50t debugdevice devicenr 3 cpunr 1 target mdm elf executable3 elf This generates the SVF file pga3 sw svf 214 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 12 System ACE File Generator GenACE XILINX Concatenate the files in the following order con ig0 svf fpgal sw svf fpga2_sw svf and fpga3_sw svf to final system svf Generate the ACE file by calling impact batch svf2ace scr Use the following SCR file svf2ace wtck d i final system svf o final system ace quit Related Information CF Device Format To have the System ACE controller read the CF device do the following 1 Format the CF device as FAT16 2 Createa Xilinx sys file in the root directory This file contains the directory s
77. in bytes XMD CONNECT The connect command used in XMD to connect to the processor PROC INSTANCE The instance name of the processor used for programming TARGET TYPE The type of the processor instance used for programming MicroBlaze or PowerPC 405 or 440 processor FLASH BOOT CONFIG Refer to Handling Flash Devices with Conflicting Sector Layouts on page 222 EXTRA COMPILER FLAGS For MicroBlaze specify any compiler flags required to turn on support for hardware features For example if you have the hardware multiplier enabled add mno x1 soft mul here Do not set this variable for the PowerPC processors Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 221 XILINX Customizing Flash Programming Manual Conversion of ELF Files to SREC for Bootloader Applications If you want to create SREC images of your ELF file manually instead of using the auto convert feature in XPS or SDK you can use the command line tools For example to create a final software application image named myexecutable elf navigate in the console of your operating system Cygwin on Windows platforms to the folder containing this ELF file and type the following platform objcopy O srec myexecutable elf myexecutable srec where platform is powerpc eabi if your processor is a PowerPC 405 or 440 processor or mb if your processor is a MicroBlaze This creates an SREC file that
78. instance of that IP PARAMETER C_MYPARAM 5 SYSLEVEL_DRC_PROC sysdrc_myparam DRC Procedure for the IP After System Level Analysis Use the OPTION SYSLEVEL_DRC_PROC to specify the Tcl procedure that performs DRC after Platgen updates system level information The input handle is a handle to an instance of the IP For example if this particular IP has been instantiated the procedure can check to limit the number of instances of this IP check that this IP is always used in conjunction with another IP or check that this IP is never used along with another IP MPD Snippet OPTION SYSLEVEL_DRC_PROC syslevel_drc BUS_INTERFACE BUS SPLB BUS_STD PLB BUS_TYPE SLAVE PORT MYPORT DIR O Tcl snippet proc syslevel_drc ipinst_handle set myport conn xget hw port value ipinst handle MYPORT set mhs handle xget hw parent handle ipinst handle set sink ports xget hw connected ports handle mhs handle myport conn SINK if llength sink ports gt 5 error MYPORT should not drive more than 5 signals return 1 else return 0 Platgen specific Call The OPTION PLATGEN SYSLEVEL UPDATE PROC is called after all the common Tcl procedures have been invoked If you want certain actions to occur only when Platgen runs and not when other tools run this procedure can be used MPD Snippet OPTION PLATGEN SYSLEVEL UPDATE PROC platgen syslevel update
79. is inferred for all global ports tagged srGrs RST in the MHS file The polarity of the reset signal is given by the RST_POLARITY tag The length of the reset is given by the RST LENGTH tag For more information about the clock and reset tags refer to the Platform Studio Online Help www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 6 Simulation Model Generator Simgen XILINX VHDL Test Bench Example library IEEE use IEEE STD LOGIC 1164 ALL library UNISIM use UNISIM VCOMPONENTS ALL entity system tb is end system tb architecture STRUCTURE of system tb is constant sys clk PERIOD time 10 ns constant sys reset LENGTH time 160 ns constant sys clk PHASE time 2 5 ns component system is port Sys clk in std logic sys reset in std logic rx in std logic tx out std logic leds inout std logic vector 0 to 3 Jor end component Internal signals signal leds std logic vector 0 to 3 signal rx std logic signal sys clk std logic signal sys reset std logic signal tx std logic begin dut system port map Sys Clk gt sys clk Sys reset sys reset LX gt rx tx gt tx leds gt leds n Clock generator for sys clk process begin sys clk lt 0 wait for sys clk PHASE loop wait for sys clk PERIOD 2 sys_clk lt not sys clk end loop end process Embedded System Tool
80. made to XMD and debugging is done from the GDB GUI gt XMD Accepted a new GDB connection from 127 0 0 1 on port 3791 XMDS XMD GDB Closed connection XMD stp Embedded System Tools Reference Manual www xilinx com 183 UG111 EDK 11 3 1 7 XILINX Connect Command Options BREAKPOINT at 114 F1440003 sbi rio r4 3 XMD dis 0x114 10 114 F1440003 sbi r10 r4 3 118 E0E30004 lbui r7 r3 4 DLES E1030005 lbui r8 r3 5 120 FOEA40004 sbi rd E4 4 124 F1040005 sbi r8 r4 b 128 B800FFCC bri 52 12C B6110000 rtsd r17 0 130 80000000 Or r0 r0 r0 134 B62E0000 rtid rid 0 138 80000000 Or r0 r ro XMD dow microblaze 0 code executable elf XMD con Info Processor started Type stop to stop processor RUNNING stop XMD Info User Interrupt Processor Stopped at 0x0000010c XMD con Info Processor started Type stop to stop processor RUNNING rrd pc pc 0x000000f4 With the MDM the current PC of MicroBlaze can be read while the program is running RUNNING rrd pc pc 0x00000110 Note the PC is constantly changing as the program is running RUNNING stop Info Processor started Type stop to stop processor XMD rrd r0 00000000 r8 00000065 r16 00000000 r24 00000000 r1 00000548 r9 0000006c r17 00000000 r25 00000000 r2 00000190 r10 0000006c r18 00000000 r26 00000000 r3 0000014c r11 00000000 r19 00000000 r27 00000000 r4 00000500 r12 00000000 r20 00000000
81. master output Mri must not contain the string PLB upper lower or mixed case so that master outputs are not confused with bus outputs lt nPLB gt A meaningful name or acronym for the master input The last three characters of lt nPLB gt must contain the string PLB upper lower or mixed case lt BI gt A bus identifier Optional for peripherals with a single master PLB port and required for peripherals with multiple master PLB ports BI must not contain the string PLB upper lower or mixed case For peripherals with multiple master PLB ports the BI strings must be unique for each bus interface Note If Bl is present Mn is optional 1 Deprecated in this release Embedded System Tools Reference Manual www xilinx com 47 UG111 EDK 11 3 1 XILINX Conventions for Defining HDL Peripherals PLB Master Outputs For interconnection to the PLB masters must provide the following outputs lt BI gt lt Mn gt _ABus out std_logic_vector 0 to C_ lt BI gt PLB_AWIDTH 1 lt BI gt lt Mn gt _BE out std_logic_vector 0 to C_ lt BI gt PLB_DWIDTH 8 1 lt BI gt lt Mn gt _RNW out std logic BI Mn abort out std logic BI Mn busLock out std logic BI Mn compress out std logic BI Mn guarded out std logic BI Mn lockErr out std logic BI Mn MSize out std logic BI Mn ordered out std logic BI Mn
82. models is only supported when the netlist file has hierarchy preserved For VHDL simulation models run Simgen with the pe option to generate a VHDL file This file contains a configuration for the system with all initialization values For example simgen system mhs pe mblaze executable elf 1 vhdl This command generates the VHDL system configuration in the file system init vhd This file is used along with your system to initialize memory The BRAM blocks connected to the mblaze processor contain the data in executable elf For Verilog simulation models run Simgen with the pe option to generate a Verilog file This file contains defparam constructs that initialize memory For example simgen system mhs pe mblaze executable elf 1 verilog This command generates the Verilog memory initialization file system init v This file is used along with your system to initialize memory The BRAM blocks connected to the processor mblaze contains the data in executable elf Simgen is capable of creating test bench templates If you use the tb switch simgen will create a test bench which will instantiate the top level design and will create default stimulus for clock and reset signals Clock stimulus is inferred from any global port which is tagged SIGIS CLK in the MHS file The frequency of the clock is given by the CLK_FREQ tag The phase of the clock is given by the CLK PHASE tag which takes values from 0 to 360 Reset stimulus
83. modify only the starting address of your program by defining the linker symbol _TEXT_START_ADDR on MicroBlaze or START ADDR on PowerPC as displayed in this example mb gcc lt input files and flags Wl defsym Wl TEXT START ADDR 0x100 powerpc eabi gcc lt input files and flags W1 defsym Wl TEXT START ADDR 0x2000 mb ld lt o files defsym TEXT START ADDR 0x100 The choices of the default script that will be used by the linker from the SXILINX EDK gnu processor name platform processor name 1lib ldscripts area are described as follows e elf32 procname xis used by default when none of the following cases apply e elf32 procname xnis used when the linker is invoked with the n option e el 32 procname xbn is used when the linker is invoked with the N option e elf32 procname xr is used when the linker is invoked with the r option e elf 32 procname xu is used when the linker is invoked with the ur option where procname ppc or microblaze processor name powerpc eabi or microblaze and platform linor nt To use a linker script provide it on the GCC command line Use the command line option T script for the compiler as described below compiler T linker script Other Options and Input Files If the linker is executed on its own include the linker script as follows linker T linker script Other Options and Input Files This tells GCC to use yo
84. name Set the name by which the processor design is instantiated if submodule ucf file Specify a path to the User Constraints File UCF to be used for implementation tools usercmdl Set the user command 1 usercmd2 Set the user command 2 user make file directory path Specify a path to the make file This file should not be same as the make file generated by XPS Executing Flow Commands You can run various flow tools using the run command with appropriate options XPS creates a make file for the project and runs that make file with the appropriate target XPS generates the make file every time the run command is executed The following table lists the valid options for the run command run lt option gt Table 4 2 run Command Options Option Name ace Description Generate the System ACE technology file after the BIT file is updated with block RAM information assign default drivers Assign default drivers to all peripherals in the MHS file and save to MSS file bits Run the Xilinx implementation tools flow and generate the bitstream bitsclean Delete the BIT NCD and BMM files in the implementation directory bsp Generate the VxWorks Board Support Package BSP for the given PowerPC processor system 64 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 4 Command Line no window Mode XILINX Table 4 2 run
85. names for MicroBlaze and PowerPC processors refer to Special Purpose Register Names on page 160 For connect command options refer to Connect Command Options on page 168 Table 9 2 XMD User Commands command options Example Usage Description block timeout lt Seconds gt bpl bp1 Lists breakpoints and watchpoints bpr bpr 0x400 Removes breakpoints and watchpoints bpr all lt bp id gt bpr main lt address gt lt function gt bpr all bps bps 0x400 Sets a software or hardware breakpoint at bps lt address gt bps main hw address orstart of function name The function name gt sw hw last downloaded ELF file is used for function lookup Defaults to software breakpoint con con Continues from current PC or optionally con lt Execute Start Address gt con 0x400 specified Execute Start Address e f block option is specified the command returns when the Processor stops on breakpoint or watchpoint e A timeout value can be specified to prevent indefinite blocking of the command e The block option is useful in scripting connect connect lt target_type s gt connect mb mdm connect ppc Connects to target type Valid target types are mb ppc and mdm For additional information refer to Connect Command Options on page 168 cstp cstp number of cycles cstp cstp 10 Steps through the specified number of cycles Note This is
86. object e PORT the parent is the MPD IP instance the merged IP instance or the MHS object e BUS INTERFACE the parent is the MPD IP instance or the merged IP instance object e IO INTERFACE the parent is the MPD or the merged IP instance object e OPTION the parent is the MPD or the merged IP instance object e IPINST the parent is the MHS or the merged MHS object For MHS or MPD the parent is a NULL handle xget hw pcore dir from mpd mpd handle Description Returns the pcore directory path for the MPD Arguments mpd handle is the handle to the MPD xget hw pcore dir ipinst handle Description Returns the pcore directory for the given IP instance Arguments ipinst handle is the handle to the IP instance Embedded System Tools Reference Manual www xilinx com 263 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface xget hw port connectors list ipinst handle portName Description Arguments If the value connector of the port is within an amp separated list this API splits that list and returns a list of strings connector names ipinst handle is the handle to the IP instance merged or original lt portName gt is the name of the port whose connectors are needed xget hw port handle handle port name Description Arguments Returns the handle to a port associated with the handle If a handle is of type MES the returned handle p
87. post_generate or execs_generate to access the system data structure 292 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 gt XILINX Glossary Appendix D Terms Used in EDK B BBD file BFL BFM BIT File Bitlnit block RAM BMM file Embedded System Tools Reference Manual UG111 EDK 11 3 1 Black Box Definition file The BBD file lists the netlist files used by a peripheral Bus Functional Language Bus Functional Model Xilinx Integrated Software Environment ISE Bitstream file The Bitstream Initializer tool It initializes the instruction memory of processors on the FPGA and stores the instruction memory in BlockRAMs in the FPGA A block of random access memory built into a device as distinguished from distributed LUT based random access memory Block Memory Map file A Block Memory Map fileis a text file that has syntactic descriptions of how individual Block RAMs constitute a contiguous logical data space Data2MEM uses BMM files to direct the translation of data into the proper initialization form Since a BMM file is a text file it is directly editable www xilinx com 293 7 XILINX 294 BSB BSP CFI DCM DCR DLMB DMA DOPB DRC EDIF file EDK ELF file Appendix D Glossary Base System Builder A wizard for creating a complete EDK design BSB is also the file type used in the BSB Wizard Board Support Package Com
88. ppc sim to connect to a PowerPC 405 processor ISS running on localhost or other machine When XMD is connected to the PowerPC 405 processor target powerpc eabi gdb can connect to the target through XMD and debugging can proceed www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD Running PowerPC Processor ISS XMD starts the ISS with a default configuration The ISS executable file is located in the S XILINX_EDK third_party bin lt platform gt directory The PowerPC 405 processor configuration file used is DK third_party data iss405 icf XILINX El XILINX You can run ISS with different configuration options and XMD can connect to the ISS target Refer to the IBM Instruction Set Simulator User Guide for more details A link to the document is supplied in Additional Resources on page 152 The following are the default configurations for ISS Two local memory banks Connect to XMD Debugger Debugger port at 6470 6490 Data cache size of 16 K Instruction cache size of 16 K Non deterministic multiply cycles Processor clock period and timer clock period of 5 ns 200 MHZ The following table lists the Local Memory Banks Table 9 11 Local Memory Banks Name Start Address Length Speed Mem0 0x0 0x80000 0 Mem1 Oxfff80000 0x80000 0 The following figure illustrates a PowerPC processor ISS target Embedded Sy
89. profile init routine before invoking main This initializes the software profiling library before your code executes Similarly upon exit from main it invokes the profile cleanroutine which cleans up the profiling library Other files The compiler also uses standard start and end files for C language support ecrti o crtbegin o crtend o and crtn o These files are standard compiler files that provide the content for the init fini ctors and dtors sections The PowerPC default and generated linker scripts also make boot o a startup file This file is present in the standalone package for PowerPC 405 and 440 processors Embedded System Tools Reference Manual www xilinx com 147 UG111 EDK 11 3 1 XILINX PowerPC Compiler Usage and Options Modifying Startup Files The initialization files are distributed in both pre compiled and source form with EDK The pre compiled object files are found in the compiler library directory Sources for the initialization files for the PowerPC compiler can be found in the XILINX EDK Sw lib ppc405 src directory where lt XILINX_EDK gt is the EDK installation area Any time you need a custom startup file requirement you can take the files from the source area and include them as a part of your application sources Alternatively they can be assembled into o files and placed in a common area To refer to the newly created object files instead of the standard files use the B directory nam
90. property handle handle property name xget sw subproperty handle property handle subprop name xget sw property value handle property name xget sw subproperty value property handle subprop name Embedded System Tools Reference Manual www xilinx com 275 UG111 EDK 11 3 1 7 XILINX 276 Appendix C EDK Tcl Interface Software Read Access API Descriptions xget libgen proc handle Description Arguments Example Returns the handle to the merged processor for which Libgen is currently being run This API is available only when Libgen is run none In a driver Tcl file get the merged processor instance for which the Libgen algorithm is run set proc handle xget libgen proc handle xget sw array handle lt handle gt array name Description Arguments Example Returns the handle to the array associated with the handle handle is of specified type Valid handle types are MDD MLD MSS merged MSS original driver instance merged driver original processor instance merged processor original OS instance merged OS original library instance or merged library array name is the name of the array required If specified as an asterisk 5 the API returns a list of array handles To access an individual array handle iterate over the list in Tcl To get a list of array handles associated with an MSS handle set array handle xget sw array handle mss handle
91. r28 00000000 r5 24242424 r13 00000190 r21 00000000 r29 00000000 r6 0000c204 r14 00000000 r22 00000000 r30 00000000 r7 00000068 r15 0000005c r23 00000000 r31 00000000 pc 0000010c msr 00000000 XMD bps 0x100 Setting breakpoint at 0x00000100 XMD bps Oxllc hw Setting breakpoint at 0x0000011c XMD bpl SW BP addr 0x00000100 instr 0xe1230002 lt Software Breakpoint HW BP BP ID 0 addr 0x0000011c Hardware Breakpoint XMD con Info Processor started Type stop to stop processor RUNNING Processor stopped at PC 0x00000100 Info Processor stopped Type start to start processor XMD con Info Processor started Type stop to stop processor RUNNING Info Processor started Type stop to stop processor 184 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD 7 XILINX MicroBlaze Stub Hardware Target To connect to a MicroBlaze target use the XMDStub a ROM monitor running on the target and start a GDB server for the target XMD connects to XMDStub through a JTAG or serial interface The default option connects using a JTAG interface MicroBlaze Stub JTAG Target Options Usage connect mb stub comm jtag cable JTAG Cable options gt configdevice lt JTAG chain options gt debugdevice lt MicroBlaze options gt JTAG Cable Options and JTAG Chain Options For JTAG cable and chain option descri
92. run the BFM simulation you must ov unge SN e Compile the simulation HDL files Load the system into the simulator Initialize the Bus Functional Models Optionally create a waveform list or load a previously created one Provide the clock and reset stimulus to the system Run the simulation The following is an example script called run do that you can write to perform the BFM simulation steps do system do vsim system do sample do do wave do force freeze sim system sys clk 1 0 0 10 ns r 20 ns force freeze sim system sys reset 0 1 200 ns run 2 us Note f your design has an input reset that is active high replace the reset line with force freeze sim system sys reset 1 0 200 ns At the ModelSim prompt type do run do Embedded System Tools Reference Manual www xilinx com 83 UG111 EDK 11 3 1 Chapter 5 Bus Functional Model Simulation 84 www xilinx com XILINX Embedded System Tools Reference Manual UG111 EDK 11 3 1 gt XILINX Chapter 6 Simulation Model Generator Simgen This chapter introduces the basics of Hardware Description Language HDL simulation and describes the Simulation Model Generator tool Simgen and usage of the Compxlib utility tool It contains the following sections e Simgen Overview e Additional Resources e Simulation Libraries e Compxlib Utility e Simulation Models e Simgen Syntax e Output File
93. supported only on ISS targets data verify data verify binary filename load address data verify system dat 0x400 Verify if the Binary filename is downloaded correctly at Load Address to the target debugconfig debugconfig step mode disable interrupt enable interrupt debugconfig memory datawidth matching disable enable debugconfig reset on run options debugconfig Step mode enable interrupt debugconfig memory datawidth mat ching enable Configures the debug session for the target For additional information refer to Configure Debug Session on page 189 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 155 XMD User Commands XILINX Table 9 2 XMD User Commands Cont d command options dis dis lt address in hex gt lt number of words gt Example Usage dis 0x400 10 Description Disassemble instruction Note Supported on the MicroBlaze target only disconnect disconnect lt target id gt disconnect 0 Disconnects from the current processor target closes the corresponding GDB server and reverts to the previous processor target if any dow dow lt filename elf gt dow lt PIC filename elf gt lt load_address gt dow data lt binary_filename gt lt load_address gt elf verify elf verify lt filename el gt dow executable elf dow executable elf
94. the 11 1 release e OPB Device BFM opb device bfm The OPB device model can act as a master slave or both The master contains logic to initiate transactions on the bus automatically The slave contains logic to respond to bus transactions based on an address decode operation The model maintains an internal memory that can be initialized through the Bus Functional Language and can be checked dynamically during simulation or when all bus transactions are complete e OPB Monitor BFM opb monitor bfm The OPB monitor is a model that connects to the OPB and continuously samples the bus signals It checks for bus compliance or violations of the OPB architectural specifications and reports warnings and errors e PLB Master BFM p1b master bfm The PLB master model contains logic to initiate transactions on the bus automatically The model maintains an internal memory that can be initialized through the Bus Functional Language and can be checked dynamically during simulation or when all bus transactions are complete e PLB Slave BFM plb slave bfm The PLB slave contains logic to respond to bus transactions based on an address decode operation The model maintains an internal memory that can be initialized through the Bus Functional Language and may be dynamically checked during simulation or when all bus transactions have completed e PLB Monitor plb monitor bfm The PLB monitor is a model that connects to the PLB and continuously samp
95. the C runtime routines 140 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Interrupt Handlers Interrupt handlers must be compiled in a different manner than normal sub routine calls In addition to saving non volatiles interrupt handlers must save the volatile registers that are being used Interrupt handlers should also store the value of the machine status register RMSR when an interrupt occurs interrupt_handler attribute To distinguish an interrupt handler from a sub routine mb gcc looks for an attribute interrupt_handler in the declaration of the code This attribute is defined as follows void function name __attribute__ interrupt handler Note The attribute for the interrupt handler is to be given only in the prototype and not in the definition Interrupt handlers might also call other functions which might use volatile registers To maintain the correct values in the volatile registers the interrupt handler saves all the volatiles if the handler is a non leaf function Note Functions that have calls to other sub routines are called non leaf functions Interrupt handlers are defined in the MicroBlaze Hardware Specification MHS and the MicroBlaze Software Specification MSS files These definitions automatically add the attributes to the interrupt handler functions For more information refer to Appendix B Interrupt Management The
96. the data going into this section with the G option to the compiler This section has the r read only and the i initialized flags data This section contains read write data and has the w read write and the i initialized flags It must be mapped to initialized random access memory RAM It cannot be mapped to a ROM Sdata This section contains small read write data of a size less than 8 bytes You can change the size of the data going into this section with the G option All data in this section is accessed with reference to the read write small data anchor This ensures that all contents of the section can be accessed using a single instruction This section has the w read write and the i initialized flags and must be mapped to initialized RAM Sbss2 This section contains small read only un initialized data of a size less than 8 bytes You can change the size of the data going into this section with the G option This section has ther read flag and can be mapped to ROM Sbss This section contains small un initialized data of a size less than 8 bytes You can change the size of the data going into this section with the G option This section has the w read write flag and must be mapped to RAM bss This section contains un initialized data This section has the w read write flag and must be mapped to RAM heap This section contains uninitialized data that is used as the global program heap Dynamic
97. to processor2 Use the debugcon ig command to configure the reset behavior which depends on your system architecture Refer to the Configure Debug Session on page 189 Download the ELF file Set the required Breakpoints and Watchpoints Start the processor execution using the con command or step through the program using the stp command Use the targets command to list the targets in the system Each target is associated witha target id an asterisk marks the active target Use targets target id to switch between targets Use the state command to check the processor status Use the stop command to stop the processor When the processor is stopped read and write the registers and memory To re run the program use the run command www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Running a Program in a Debug Session Connect to the processor Download the ELF file Set the Breakpoint at the exit function Start the processor execution using the con command Use the state command to check the processor status Use the stop command to stop the processor When the processor is stopped read and write the registers and memory 9o LO COT JE GO Nes To re run the program use the run command Using Safemode for Automatic Exception Trapping XMD allows you to trap exceptions in your program when errors occur Such errors in
98. top level HDL design file for the embedded system that stitches together all the instances of parameterized pcores contained in the system In the process it resolves the high level bus connections in the MHS into the actual signals required to interconnect the processors peripherals and on chip memories The system level HDL netlist produced by Platgen is used as part of the FPGA implementation process e Invokes the XST Xilinx Synthesis Technology compiler to synthesize each of the instantiated pcores e Generates the block RAM Memory Map BMM file which contains addresses and configuration of on chip block RAM memories This file is used later for initializing the block RAMs with software Chapter 3 Platform Generator Platgen provides a detailed description of the Platgen tool FXPS Command Line or no window Mode XPS includes a no window mode that allows you to run from an operating system command line Chapter 4 Command Line no window Mode provides information on the command line feature in XPS 24 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX EDK Overview Bus Functional Model BFM Bus Functional Model simulation simplifies the verification of hardware components that attach to a bus For more information on bus functional models see the BFM Simulation document A link to the document is available in Additional Resources page 18 Debug Configuration Wiza
99. xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Appendix A GNU Utilities This appendix describes the GNU utilities available for use with EDK It contains the following sections e General Purpose Utility for MicroBlaze and PowerPC e Utilities Specific to MicroBlaze and PowerPC e Other Programs and Files General Purpose Utility for MicroBlaze and PowerPC cpp Pre processor for C and C utilities The preprocessor is invoked automatically by GNU Compiler Collection GCC and implements directives such as file include and define gcov This is a program used in conjunction with GCC to profile and analyze test coverage of programs It can also be used with the gprof profiling program Utilities Specific to MicroBlaze and PowerPC Utilities specific to MicroBlaze have the prefix mb as shown in the following program names The PowerPC processor versions of the programs are prefixed with powerpc eabi mb addr2line This program uses debugging information in the executable to translate a program address into a corresponding line number and file name mb ar This program creates modifies and extracts files from archives An archive is a file that contains one or more other files typically object files for libraries mb as This is the assembler program Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 233 XILIN
100. 0 std logic std logic std logic vector 0 std logic std logic vector 0 std logic vector 0 std logic std logic std logic std logic std logic vector 0 std logic std logic std logic vector std logic vector std logic vector std logic vector std logic std logic vector 0 std logic std logic vector 0 std logic vector 0 std logic vector 0 CO CO CO CO CO to to to C_ lt BI SPLB gt _AWIDTH 1 C_ lt BI SPLB gt _AWIDTH 1 C_ lt BI gt PLB_DWIDTH 8 1 C_ lt BI SPLB gt _MID_WIDTH 1 1 1 1 1 3 15 2 C_ lt BI SPLB gt _DWIDTH 1 3 4 3 3 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 53 XILINX Conventions for Defining HDL Peripherals 54 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 3 Platform Generator Platgen The Hardware Platform Generation tool Platgen customizes and generates the embedded processor system in the form of hardware netlists HDL files and Electronic Data Interchange Format EDIF files By default Platgen synthesizes each processor IP core instance found in your embedded hardware design using the XST compiler Platgen also generates the system level HDL file that interconnects all the IP cores to be synthesized later as part of the overall Xilinx Integrated Software Environment ISE9 implementation flow This chapter covers
101. 0 00 cc ccc cent ence ent n 275 Software Read Access API Summary 0 6 0 c ec cee eee eee 275 Software Read Access API Descriptions 6 0 0 0 c ec cece eee eee 276 Tcl Flow During Hardware Platform Generation 6 284 Input FiOS eR 284 Tcl Procedures Called During Hardware Platform Generation 284 Additional Keywords in the Merged Hardware Datastructure 290 Tcl Flow During Software Platform Generation 005 291 Input Eles precesio e eps er REPRE eras 291 Tcl Procedure Calls from Libgen 06 66 291 Appendix D Glossary Terms Used in EDK ccoooiicciiccorcic e e he dba aa dd p Les d uad 293 16 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 1 Embedded System and Tools Architecture Overview About EDK This chapter describes the architecture of the embedded system tools and flows provided in the Xilinx Embedded Development Kit EDK for developing systems based on the PowerPC 405 and 440 processors and MicroBlaze embedded processors The following sections are included e About EDK e Additional Resources e Design Process Overview e EDK Overview The Xilinx Embedded Development Kit EDK system tools enable you to design a complete embedded processor system for implementation in a Xilinx FPGA device EDK includes e The Xilinx Platform Studio XPS sy
102. 11 EDK 11 3 1 Table of Contents Preface About This Guide Guide Contents a RE QE 3 Additional Resources sess RR e e 4 Conventions ccc ccc cece ee 4 Typographical Conventions 0 2 e 4 Online Doct ment it Reate d a QR Bud 5 Chapter 1 Embedded System and Tools Architecture Overview AbOULEDK te detis eli ue REUS REO eT MU dad 17 Additional Resources ssssssssssssssssss n 18 Design Process Overview i so laa c RR XP EXE QRE LEER E qa av dare ga 18 Hardware Development ceci aii CERDO a eR reet eR 18 Software Development cree h ker acere ae 19 cgi MEMO 19 Hardware Verification Using Simulation lees 19 Software Verification Using Debugging 0 cece ee 19 Device Configuration 22e kem Rem Re RR RR r9 cree e e eqs 19 EDK OVetvIew dp eet Aba Ru tod 20 EDK Tools and Utilities cp LeRRERR cseanettds RP EENG REN ELES T EFENO 21 Xilinx Platform Studio XPS sssssseeeeeeee nett eens 22 The Base System Builder BSB Wizard 0 0 ccc eens 23 The Create and Import Peripheral CIP Wizard sssusa nasan eee eee 23 Platform Specification Utility PsfUtility 0 0 cee ee ee eee 24 Coprocessor Wizard ios iesus dns a qubd ed atat e dn a 24 Platform Generator Platgen 0 rr 24 FXPS Command Line or no window Mode 0 02 eee eee eee eee eee 24 Bus Functional Model BFM 0 cece eee eee eee nents 25 Debug C
103. 11019 Figure B 3 MicroBlaze Interrupt Flow without Interrupt Controller www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software Setup and Interrupt Flow XILINX User Program INTR 0x000_0008 e 0x000_00 10 microblaze_interrupt_handler c interrupt handler Branch to OS xintc c INTR handler XIntc_DevicelnterruptHandler user or peripheral interrupt handler function Lookup the interrupt handler registered with the OS and jump to it 0x000 00 18 For each active interrupt call the registered interrupt handler 0x000_00 20 MB InterruptVector Table XIntc_DevicelnterruptHandler registered with the OS Layer HandlerTable t User or peripheral interrupt handlers registered with the interrupt controller driver k X11020 Figure B 4 MicroBlaze interrupt Flow with Interrupt Controller Interrupt Flow for PowerPC Systems Interrupts on the PowerPC processors go through the following flow 1 Interrupts must be enabled on the PowerPC processor by setting appropriate bits in the Machine Status Registers MSR Depending on whether critical or non critical or both interrupts are being used appropriate bits must be set 2 Upon the external interrupt signal being raised the processor first disables further interrupts The processor then calculates an address for the interrupt type and ju
104. 288 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Flow During Hardware Platform Generation XILINX Simgen specific Call The OPTION SIMGEN_SYSLEVEL_UPDATE_PROC is called after all the common Tel procedures have been invoked If you want certain actions to occur when Simgen runs and not when other tools run this procedure can be used MPD Snippet OPTION SIMGEN_SYSLEVEL_UPDATE_PROC simgen_syslevel_update FORMAT PROC The FORMAT_PROC keyword defines the Tcl entry point that allows you to provide a specialized formatting procedure to format the value of the parameter The EDK tools deliver output files of two HDL types Verilog and VHDL Each format semantic requires that the parameter values be normalized to adhere to a stylized representation suitable for processing For example Verilog is case sensitive and does not have string manipulation functions When developing an IP you can use this Tcl entry point to specify procedures to format string values based on the HDL requirements Refer to the Plaform Specification Format Reference Manual for further details and examples Additional Resources page 255 contains a link to the document Helper Core Tcl Procedures All the illustrated Tcl procedures must be specified in the top level cores If a top level core is using helper or library cores you can execute Tcl procedures specific to those helper cores by using one
105. 4 Note Following these naming conventions enables the PsfUtility to create a correct and complete MPD file Create an XST Xilinx Synthesis Technology project file or a PAO file that lists the HDL sources required to implement the IP Invoke the PsfUtility by providing the XST project file or the PAO file with additional options For more information on invoking the PsfUtility with different options see the following section Use Models for Automatic MPD Creation Use Models for Automatic MPD Creation You can run the PsfUtility in a variety of ways depending on the bus standard and bus interface types used with the peripheral and the number of bus interfaces a peripheral contains Bus standards and types can be one of the following OPB on chip peripheral bus SLAVE OPB MASTER OPB MASTER SLAVE PLB processor local bus SLAVE PLB UMASTER PLB MASTER SLAVE PLBV46 processor local bus version 4 6 SLAVE PLBV46 MASTER DCR design control register SLAVE LMB local memory bus SLAVE FSL fast simplex link SLAVE FSL MASTER POINT TO POINT BUS special case 1 Deprecated in this release Embedded System Tools Reference Manual www xilinx com 31 UG111 EDK 11 3 1 XILINX Use Models for Automatic MPD Creation Peripherals with a Single Bus Interface Most processor peripherals have a single bus interface This is the simplest model for the PsfUtility For most such peripherals complete MPD specific
106. 501 This board has the following device in the JTAG chain XC5vLX50 e ML505 Board type is m1505 This board has the following device in the JTAG chain XC5vLX50T e ML506 Board type is m1506 This board has the following device in the JTAG chain XC5vSX50T e ML507 Board type is m1507 This board has the following device in the JTAG chain XC5VFX70T For a custom board use the configdevice option to specify the JTAG chain and use an OPT file 210 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 12 System ACE File Generator GenACE XILINX Generating ACE Files System ACE files can be generated for the scenarios in the following subsections An example OPT file is given for each Specify the use of the OPT file as follows xmd tcl genace tcl opt genace opt For Custom Boards If your board is not listed in the Supported Target Boards in Genace tcl Script page 210 the JTAG Chain configuration of the board can be specified using the configdevice option The options file in this case would be jprog hw implementation download bit ace system ace board user lt Note The Board type is user configdevice devicenr 1 idcode 0x1266093 irlength 14 partname XC2VP20 devicenr 2 idcode 0x1266093 irlength 14 partname XC2VP20 lt Note The JTAG Chain is specified here target ppc_hw elf executable elf Single FPGA Device Hardware and Software Configuration jprog hw imp
107. 6 XCF32P 3 01e58093 10 XC4VFX12 4 49608093 8 xc95144x1 MicroBlaze Processor Configuration VOLS LOM epg aci dad 7 00 a Optimisation Z esg bk RA a Performance INtercomebtE aiii as a 3e sacs da PLBv46 No of PC Breakpoints 3 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 Exceptions Support off FPU SuppOEXtt izcsesecdao Au vm Gee EAM UU off Hard Divider Support off Hard Multiplier Support on Mul32 Barrel Shifter Support off MSR clr set Instruction Support on Compare Instruction Support on PVR SuppO Zted i sde seo ha a Co OR Ce on PVR Configuration Type Base Connected to MDM UART Target Connected to mb target id 0 Starting GDB server for mb target id 0 at TCP port no 1234 XMD rrd r0 00000000 r8 00000000 r16 00000000 r24 00000000 r1 00000510 r9 00000000 r17 00000000 r25 00000000 r2 00000140 r10 00000000 r18 00000000 r26 00000000 r3 aba5aba5 r11 00000000 r19 00000000 r27 00000000 r4 00000000 r12 00000000 r20 00000000 r28 00000000 r5 00000000 r13 00000140 r21 00000000 r29 00000000 r6 00000000 r14 00000000 r22 00000000 r30 00000000 r7 00000000 r15 00000064 r23 00000000 r31 00000000 pc 00000070 msr 00000004 lt Launching GDB from XMD console gt XMD start mb gdb microblaze 0 code executable elf XMDS lt From GDB a connection is
108. B ABus in std logic vector 0 to C LMB AWIDTH 1 DLMB ABus in std logic vector 0 to C DLMB AWIDTH 1 Embedded System Tools Reference Manual www xilinx com 43 UG111 EDK 11 3 1 XILINX Conventions for Defining HDL Peripherals Master OPB Ports The signal list in the following table applies to master OPB ports that are independent of slave OPB ports Master OPB ports must follow the naming conventions shown in the following table Table 2 9 Master OPB Port Naming Conventions Mn A meaningful name or acronym for the master output Mr must not contain the string OPB upper lower or mixed case so that master outputs will not be confused with bus outputs nOPB A meaningful name or acronym for the master input The last three characters of lt nOPB gt must contain the string OPB upper lower or mixed case BI A bus identifier Optional for peripherals with a single OPB port of any type and required for peripherals with multiple OPB ports of any type or mix of types BI must not contain the string OPB upper lower or mixed case For peripherals with multiple OPB ports the BI strings must be unique for each bus interface Note If BI is present Mn is optional OPB Master Outputs For interconnection to the OPB masters must provide the following outputs BI Mn ABus out std logic vector 0 to C BI OPB AWIDTH 1 BI
109. BI SPLB DWIDTH 1 lt BI gt S1_rdwdAddr out std_logic_vector 0 to 3 lt BI gt Sl_rearbitrate out std_logic lt BI gt S1_SSize out std logic 0 to 1 BI S1 wait out std logic lt BI gt S1_wrBTerm out std logic lt BI gt S1_wrComp out std_logic lt BI gt S1_wrDAck out std logic Examples Tmr S1 addrAck out std logic Uart S1 addrAck out std logic IntcSl addrAck out std logic 52 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility 7 XILINX PLBV4 6 Slave Inputs For interconnection to the PLBV4 6 slaves must provide the following inputs lt BI gt SPLB_C1k lt BI gt SPLB_Rst lt BI gt PLB_ABus lt BI gt PLB_UABus lt BI gt PLB_BE lt BI gt PLB_busLock lt BI gt PLB_lockErr lt BI gt PLB_masterID lt BI gt PLB_PAValid lt BI gt PLB_rdPendPri lt BI gt PLB_wrPendPri lt BI gt PLB_rdPendReq lt BI gt PLB_wrPendReq lt BI gt PLB_rdBurst lt BI gt PLB_rdPrim lt BI gt PLB_reqPri lt BI gt PLB_RNW lt BI gt PLB_SAValid lt BI gt PLB_MSize lt BI gt PLB_size lt BI gt PLB_TAttribute lt BI gt PLB_type lt BI gt PLB_wrBurst lt BI gt PLB_wrDBus lt BI gt PLB_wrPrim Examples PLB size IPLB_size DPORTO PLB size in in in in in in in in in in in in in in in in in in in in in in in in in in in in std logic std logic std logic vector 0 std logic vector 0 std logic vector
110. C Compiler Options Quick Reference 0 00 0 esses 142 PowerPC Compiler Options sssssseseeee ee 142 PowerPC Processor Linker ssiri sireisas diiidan ee 144 PowerPC Processor Linker Script Sections oooococooroccccnrrrrrcannnr oo 144 Embedded System Tools Reference Manual www xilinx com 11 UG111 EDK 11 3 1 EZ XILINX Tips for Writing or Customizing Linker Scripts 0 60 cece eee ee eee 145 Startup Piles micres postas pe RU aer Red 146 Initialization File Description 6 6 eects 147 Start up File Descriptions ri iiss ii hei 8 4p RR CAD A DE eee 147 Other files bd RR dios RR bode cade dps ee tpa eee res 147 Modifying Startup Files sssr peeps nin s era E E E E E 148 Reducing the Startup Code Size for C Programs ooococcooococcoococcco 148 Modifying Startup Files for Bootstrapping an Applicati0N oo ooooooo o 149 Compiler Librati S cien orcas cra e ee dn eeu iee esa ea 149 Thread Safety vicios I ee eR Re REST EES pER RI EC ET Er 149 Command Line Arguments 06666 149 Other Notes nanunua enan aeneae naeeua raaraa ruarena rennara 150 O 150 C Standard AA Re qe nb pera ed a stand 150 Position Independent Code Relocatable Code nonn nn eee ec eee 150 Other Switches and Features 0 0 cece cee eee eens 150 Chapter 9 Xilinx Microprocessor Debugger XMD Additional Resources 0 000 cece eee n eee 152 XMD Usage 152 XMD Console
111. C Processor Target Requirements csse 171 Example Debug Sessions 21 06 ccc cece ehh nn 172 Example Connecting to PowerPC440 Processor Target ooooocoocoommmo mo 174 PowerPC Processor Simulator Target 0 6 ccc eee ro 176 Running PowerPC Processor ISS oocoocoocoocooccorcror een 177 Example Debug Session for PowerPC Processor ISS Target ooooommmmooo 178 DCR TLB and Cache Address Space and Access 6 0 00 cece cece eee eee 179 12 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 7 XILINX Advanced PowerPC Processor Debugging Tips llle MicroBlaze Processor Target sssssseessseees ee MicroBlaze MDM Hardware Target liess MicroBlaze MDM Target Requirements sese Example Debug Sessions 0 6 6 c ec een nn MicroBlaze Stub Hardware Target lee MicroBlaze Stub JTAG Target Options l l MicroBlaze Stub Serial Target Options llle Stub Target Requirements rp ek RA ERR too ERA MEAE EACH a MicroBlaze Simulator Target oooooocororcrcrrarnr nr Simulator Target Requirements 0 ccc eee ee eee MDM Peripheral Target 0 6 6 rr Configure Debug Session 66 icis nne Configuring Reset for Multiprocessing Systems 1 6 6 cece eee eee XMD Internal Tcl Commands s sees Program Initialization Options 6 66 Register Memory Options 2 0 0 ccc eee eens
112. Collection Concepts Tools and Techniques http www xilinx com ise embedded edk_docs htm e PowerPC 405 and 440 Processor Reference Guides http www xilinx com support documentation user guides ug018 pdf http www xilinx com support documentation user guides ug011 pdf e MicroBlaze Processor User Guide http www xilinx com support documentation sw manuals mb ref guide pdf Design Process Overview The tools provided with EDK are designed to assist in all phases of the embedded design process as illustrated in the following figure ISE Integrated Software Environment SDK Software Development Kit Also included in the Embedded Edition XPS Xilinx Platform Studio I I I I I I Processor Hardware Software Development I l 22a pi i i I Verification File i Generation Software Debug l l l l l l l l l l ili Planahead Design Implementation Sonware Proning I l l ee ee Device Configuration Device Configuraian X11124 Figure 1 1 Basic Embedded Design Process Flow Hardware Development Xilinx FPGA technology allows you to customize the hardware logic in your processor subsystem Such customization is not possible using standard off the shelf microprocessor or controller chips The term Hardware platform describes the flexible embedded processing subsystem you are creating with Xilinx technology for your application needs 18 www xilinx com Embedded System Tools Reference M
113. D file contains the bus interface label shown in the following table Table 2 2 Recognized Bus Interfaces Description Bus Label in MPD Slave DCR interface SDCR Slave LMB interface SLMB Master OPB interface MOPB Master Slave OPB interface MSOPB Slave OPB 2 interface SOPB Master PLB interface MPLB Master Slave PLB interface MSPLB Slave PLB interface SPLB Master PLBV46 interface MPLB Slave PLBV46 interface SPLB Master FSL interface MFSL Slave FSL interface SFSL a Deprecated in this release For components that have more than one bus interface of the same type naming conventions must be followed so the automation tools can group the bus interfaces www xilinx com 35 7 XILINX 36 Conventions for Defining HDL Peripherals Naming Conventions for VHDL Generics For peripherals that contain more than one of the same bus interface a bus identifier must be used The bus identifier must be attached to all associated signals and generics Generic names must be VHDL compliant Additional conventions for IP peripherals are e The generic must start with C_ e If more than one instance of a particular bus interface type is used on a peripheral a bus identifier Br must be used in the signal e Ifa bus identifier is used for the signals associated with a port the generics associated with that port can optionally use BI e If no BI string is used i
114. DATA START SDATA END SDATA2 START SDATA2 END SBSS2 START SBSS2 END bss start bss end _sbss_start and sbss end are defined to the beginning and end of the sections sdata sdata2 sbss2 bss and sbss respectively ANSI C requires that all uninitialized memory be initialized to startup not required for stack and heap The standard CRT that is provided assumes a single bss section that is initialized to zero If there are multiple bss sections this CRT will not work You should write your own CRT that initializes all the bss sections Startup Files The compiler includes pre compiled startup and end files in the final link command when forming an executable Startup files set up the language and the platform environment before your application code executes The following actions are typically performed by startup files Set up any reset interrupt and exception vectors as required Set up stack pointer small data anchors and other registers Refer to Table 8 8 page 136 for details Clear the BSS memory regions to zero Invoke language initialization functions such as C constructors Initialize the hardware sub system For example if the program is to be profiled initialize the profiling timers Set up arguments for the main procedure and invoke it Similarly end files are used to include code that must execute after your program ends The following actions are typically performed by end files
115. DK IP components library is provided for VHDL only and can be encrypted The Xilinx Compxlib utility deploys compiled models for EDK IP components into a common location Unencrypted EDK IP components can be compiled using Compxlib Precompiled libraries are provided for encrypted components EDK Libraries Search Order Simgen searches for pre compiled libraries in the sim1ib directory for the current project For Simgen to find and use a pre compiled library in the current project the directory structure must conform to the following example project directory gt simlib mti mycore vi 00 a ncsim mycore vi 00 a Compxlib Utility Xilinx provides the Compxlib utility to compile the HDL libraries for Xilinx supported simulators Compxlib compiles the UNISIM SIMPRIM and XilinxCoreLib libraries for supported device architectures using the tools provided by the simulator vendor You must have an installation of the Xilinx implementation tools to compile your HDL libraries using Compxlib Run Compxlib with the help option if you need to display a brief description for the available options compxlib help Each simulator uses certain environment variables that you must set before invoking Compxlib Consult your simulator documentation to ensure that the environment is properly set up to run your simulator Note Make sure you use the p simulator path option to point to the directory where the ModelSim executable is if it
116. ER 1 00 a PARAMETER PLB MASTER ADDR LO O0 OxFFFF0000 PARAMETER PLB MASTER ADDR HI 0 OxFFFFFFFF BUS INTERFACE MPLB myplb PORT SYNCH OUT synchO0 P ORT SYNCH IN synch tJ EGIN plbv46 slave bfm PARAMETER INSTANCE my slave PARAMETER HW VER 1 00 a PARAMETER PLB SLAVE ADDR LO 0 OxFFFF0000 PARAMETER PLB SLAVE ADDR HI 0 OxFFFF7FFF BUS INTERFACE SPLB myplb PORT SYNCH OUT synch1 PORT SYNCH IN synch END 78 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX PLB BFM Component Instantiation BEGIN plbv46 monitor bfm PARAMETER INSTANCE my monitor PARAMETER HW VER 1 00 a BUS INTERFACE MON PLB myplb P P E ORT SYNCH OUT synch2 ORT SYNCH IN synch ND tJ EGIN bfm synch PARAMETER INSTANCE my synch PARAMETER HW VER 1 00 a PARAMETER C NUM SYNCH 3 PORT FROM SYNCH OUT synch0 amp synchl amp synch2 PORT TO SYNCH IN synch END BFM Synchronization Bus Usage The BFM synchronization bus collects the SYNCH OUT outputs of each BFM component in the design The bus output is then connected to the SYNCH IN of each BFM component The following figure depicts an example for three BFMs and the MHS examples above show their instantiation for OPB PLB and PLB v4 6 BFMs SYNCH OUT SYNCH IN SYNCH OUT SYNCH IN SYNCH OUT SYNCH IN FROM SYNCH
117. Embedded System Tools Reference Guide EDK 11 3 1 UG111 September 16 2009 XILINX XILINX O Copyright 2002 2009 Xilinx Inc All Rights Reserved XILINX the Xilinx logo the Brand Window and other designated brands included herein are trademarks of Xilinx Inc The PowerPC name and logo are registered trademarks of IBM Corp and used under license All other trademarks are the property of their respective owners Disclaimer Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND
118. From the pcores directory the root directory is the peripheral name Embedded System Tools Reference Manual www xilinx com 57 UG111 EDK 11 3 1 Chapter 3 Platform Generator Platgen XILINX From the root directory the underlying directory structure is as follows data hal netlist Output Files Platgen produces directories and files from the project directory in the following underlying directory structure hdl implementation synthesis HDL Directory The hal directory contains the following files e system vhd v is the HDL file of the embedded processor system as defined in the MHS and the toplevel file for your project e system_stub vhd v is the toplevel template HDL file of the instantiation of the system Use this file as a starting point for your own toplevel HDL file e inst wrapper vhd v is the HDL wrapper file for the of individual IP components defined in the MHS Implementation Directory The implementation directory contains the peripheral file peripheral_wrapper ngc an implementation netlist file Synthesis Directory The synthesis directory contains the following synthesis project file system prj scr 58 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Synthesis Netlist Cache BMM Flow Platgen generates the system bmm and the system stub Lbmmin the Project Name implementation directory e The lt system
119. Generates a o file g This option adds DWARF2 based debugging information to the output file The debugging information is required by the GNU debugger mb gdb or powerpc eabi gdb The debugger provides debugging at the source and the assembly level This option adds debugging information only when the input is a C C source file gstabs Use this option for adding STABS based debugging information on assembly S files and assembly file symbols at the source level This is an assembler option that is provided directly to the GNU assembler mb as or powerpc eabi as If an assembly file is compiled using the compiler mb gcc or powerpc eabi gcc prefix the option with Wa Embedded System Tools Reference Manual www xilinx com 115 UG111 EDK 11 3 1 EZ XILINX 116 Common Compiler Usage and Options On The GNU compiler provides optimizations at different levels The optimization levels in the following table apply only to the C and C source files Table 8 3 Optimizations for Values of n n Optimization 0 No optimization 1 Medium optimization 2 Full optimization 3 Full optimization Attempt automatic inlining of small subprograms S Optimize for size Note Optimization levels 1 and above cause code re arrangement While debugging your code use of no optimization level is recommended When an optimized program is debugged through gdb the displayed results might seem inconsistent V
120. I must not contain the string FSL_M upper lower or mixed case For peripherals with multiple master FSL ports the BI strings must be unique for each bus interface FSL Master Outputs For interconnection to the FSL masters must provide the following outputs BI nFSL M Full out std logic Examples FSL M Full out std logic Memcon FSL M Full out std logic FSL Master Inputs For interconnection to the FSL masters must provide the following inputs BI nFSL Clk in std logic BI nFSL Rst in std logic BI nFSL M Clk in std logic BI nFSL M Data in std logic vector 0 to C BI FSL DWIDTH 1 BI nFSL M Control in std_logic BI nFSL M Write in std logic Examples FSL M Write in std logic Busi1 FSL M Write in std logic Busi1 timer FSL M Control out std logic Busl1 timer FSL M Data out std logic vector 0 to C BI FSL DWIDTH 1 Bus2 timer FSL M Control out std logic Bus2 timer FSL M Data out std logic vector 0 to C BI FSL DWIDTH 1 42 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility XILINX Slave LMB Ports Slave LMB ports must follow the naming conventions shown in the table below Table 2 8 Slave LMB Port Naming Conventions lt S1n gt A meaningful name or acronym for the slave output lt S1n gt must not co
121. ILINX Connect Command Options RS 232 Serial Cable Uartlite OPB PLBv46 Bus Local Memory OPB PLBv46 Bus Local Memory X10844 MicroBlaze Figure 9 4 MicroBlaze Stub Target with MDM UART and UARTlite 186 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Stub Target Requirements To debug programs on the hardware board using XMD the following requirements must be met XMD uses a JTAG or serial connection to communicate with xMDStub on the board Therefore an mdm or a UART designated as XMDSTUB PERIPHERAL in the MSS file is necessary on the target MicroBlaze system Platform Generator can create a system that includes a mdm or a UART if specified in its MHS file The JTAG cables supported with the xmpstub mode are Xilinx parallel cable Platform USB cable XMDStub on the board uses the MDM or UART to communicate with the host computer therefore it must be configured to use the MDM or UART in the MicroBlaze system The Library Generator Libgen can configure the xMDStub to use the XMDSTUB PERIPHERAL inthe system Libgen generates an XMDStub configured for the XMDSTUB PERIPHERAL and puts it in code xmdstub e1f as specified by the XMDStub attribute in the MSS file For more information refer to Chapter 7 Library Generator Libgen The xmpStub executable must be included in th
122. Include this section definition only when your program uses interrupts and or exceptions Each physical region of memory must use a separate program header Two discontinuous regions of memory cannot share a program header ANSI C requires that all uninitialized memory be initialized to startup not required for stack and heap The standard CRT provided assumes a single bss section that is initialized to zero If there are multiple bss sections this CRT will not work You must write your own CRT that initializes the bss sections Embedded System Tools Reference Manual www xilinx com 145 UG111 EDK 11 3 1 7 XILINX PowerPC Compiler Usage and Options Startup Files When the compiler forms an executable it includes pre compiled startup and end files in the final link command Startup files set up the language and the platform environment before your application code can execute The following actions are typically performed by startup files e Setup any reset interrupt and exception vectors as required e Setup stack pointer small data anchors and other registers as required e Clear the BSS memory regions to zero e Invoke language initialization functions such as C constructors e Initialize the hardware sub system For example if the program is to be profiled initialize the profiling timers e Setup arguments for and invoke the main procedure End files are used to include code that must execute after your program i
123. Internally these variables cause the flash programmer to rearrange the sector map according to the boot topology Data Polling Algorithm for AMD Fujitsu Command Set The DQ7 data polling algorithm is used during erasure and programming operations on flash hardware that supports the AMD Fujitsu command set Certain flash devices are known to use a configuration register to control the behavior of the data polling DQ7 bit Some known flash devices that offer this configuration register feature are AT49BV322A T AT49BV162A T and AT49BV163A T It is required that DQ7 output 0 during an erase operation and 1 at the end of the operation Similarly DO7 must output inverted data during programming and the actual data after programming is done If your flash hardware has a different configuration when using the Program Flash Memory dialog box then the programming could fail Refer to your flash hardware datasheet for information about how to reset the configuration so that DQ7 has the appropriate outputs upon erasure and ending Embedded System Tools Reference Manual www xilinx com 223 UG111 EDK 11 3 1 XILINX Customizing Flash Programming 224 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 14 Version Management Tools revup This chapter introduces the version management tools in XPS It contains the following sections e Overview e Format Revision Tool Backup and Updat
124. L slaves must provide the following outputs BI nFSL S Data out std logic vector 0 to C BI FSL DWIDTH 1 BI nFSL S Control out std logic BI nFSL S Exists out std logic Examples FSL S Control out std logic Memcon FSL S Control out std logic Busl1 timer FSL S Control out std logic Busi1 timer FSL S Data out std logic vector 0 to C BI FSL DWIDTH 1 Bus2 timer FSL Control out std logic REN Bus2 timer FSL S Data out std logic vector 0 to C BI FSL DWIDTH 1 Embedded System Tools Reference Manual www xilinx com 41 UG111 EDK 11 3 1 XILINX Conventions for Defining HDL Peripherals FSL Slave Inputs For interconnection to the FSL slaves must provide the following inputs BI nFSL Clk in std logic BI nFSL Rst in std logic BI nFSL S Clk in std logic BI nFSL S Read in std logic Examples FSL S Read in std logic Busl1 FSL S Read in std logic Master FSL Ports The following table lists the required Master FSL ports naming conventions Table 2 7 Master FSL Port Naming Conventions nFSL or A meaningful name or acronym for the master I O The last five characters of nFSL M nFSL M must contain the string FSL M upper lower or mixed case BI A bus identifier Optional for peripherals with a single master FSL port and required for peripherals with multiple master FSL ports B
125. L Scripts External debugger GDB Remote XMD Socket protocol Interface GDB Remote Protocol Interface XMD Tcl Interface XMD Socket Interface Xilinx Microprocessor Debug XMD MicroBlaze ISS TCP Socket du unc p Interface l l l l l MicroBlaze XMDSTUB using PowerPC MicroBlaze on board Serial Interface PowerPC ISS MicroBlaze UP l l l l Hardware on Board iro UR e UE UG111 13 01 091905 Figure 9 1 XMD Targets Additional Resources e PowerPC 405 Processor Documents PowerPC 440 Processor Documents MicroBlaze Processor Reference Guide IBM PowerPC ISS Reference Guide http www xilinx com ise embedded edk docs htm XMD Usage xmd h help hw hardware specification file ipcport portnum nx opt optfile v xmp xmpfile tel tcl file args gt Table 9 1 XMD Options Option Command Description Help h help Displays the usage menu and then quits Hardware hw hw spec file Specifies the XML file that describes Specification the hardware components File 152 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD Table 9 1 XMD Options Cont d XILINX Option Port Number Command ipcport port number Description Starts the XMD server at lt portnum gt Internal XMD commands can be issued over this TCP Port If lt port_number gt is not specified a default v
126. LIBRARY NAME attribute allows you to specify any name for your libraries which is also the name of the library directory e The source files and make file for the library must be in the src subdirectory under the 1ibrary name directory e The make file must have the targets include and libs e Each library must also contain an MLD file and a Tcl file in the data subdirectory Refer to the existing EDK libraries for more information about the structure of the libraries Refer to the Microprocessor Library Definition MLD chapter in the Platform Specification Format Reference Manual for details on how to write an MLD and its corresponding Tcl file A link to the document is supplied in the Additional Resources page 100 The MSS file includes an OS block for each processor instance The OS block contains a reference to the OS name OS_NAME parameter and the OS version OS VER There is no default value for these parameters The bsp directory contains C source and header files and a make file for the OS The MLD file for each OS specifies all configurable options for the OS Each MLD file has a corresponding Tcl file associated with it Refer to the Microprocessor Library Definition MLD and Microprocessor Software Specification MSS chapters in the Platform Specification Format Reference Manual A link to the document is supplied in the Additional Resources page 100 You can write your own OSs These OSs must
127. MSS format and all the parameters that MSS supports refer to the Microprocessor Software Specification MSS chapter in the Platform Specification Format Reference Manual A link to the document is supplied in the Additional Resources page 100 Most peripherals require software drivers The EDK peripherals are shipped with associated drivers libraries and BSPs Refer to the Device Driver Programmer Guide for more information on driver functions A link to the guide is supplied in the Additional Resources page 100 The MSS file includes a driver block for each peripheral instance The block contains a reference to the driver by name DRIVER NAME parameter and the driver version DRIVER VER There is no default value for these parameters A driver has an associated MDD file and a Tcl file e The driver MDD file is the data definition file and specifies all configurable parameters for the drivers e Each MDD file has a corresponding Tcl file which generates data that includes generation of header files generation of C files running DRCS for the driver and generating executables You can write your own drivers These drivers must be in a specific directory under YOUR PROJECT driver name or library name drivers as shown in Figure 7 1 on page 102 e The DRIVER NAME attribute allows you to specify any name for your drivers which is also the name of the driver directory e The source files and make file for t
128. Peripheral Definition MPD files required to create an IP core compliant with EDK Features provided by this tool can be used with the help of the CIP wizard For more information see Chapter 2 Platform Specification Utility PsfUtility Coprocessor Wizard The Coprocessor wizard helps add and connect a coprocessor to a CPU A coprocessor is a hardware module that implements a user defined function in the FPGA fabric and connects to the processor through the Fast Simplex Link FSL interface FSL channels are dedicated point to point communication interfaces implemented using FIFOs This feature is applicable for MicroBlaze processor designs only or details on the Fast Simplex Link FSL refer to the MicroBlaze Processor Reference Guide and the PowerPC 405 and 440 processor guides Additionally the Xilinx data sheet for the FSL Bus can provide more information Links to document locations are available in the Additional Resources page 18 For instructions on using the Coprocessor wizard refer to the Xilinx Platform Studio Help Platform Generator Platgen Platform Generator Platgen compiles the high level description of your embedded processor system into HDL netlists that can be implemented in a target FPGA device Platgen e Reads the MHS file as its primary design input e Reads various processor core pcore hardware description files MPD PAO from the XPS project and any user IP repository e Produces the
129. Reference Manual UG111 EDK 11 3 1 Terms Used in EDK Embedded System Tools Reference Manual UG111 EDK 11 3 1 ISOCM ISS JTAG Libgen LMB MDD file MDM MFS file MHS file MLD file XILINX Instruction side On Chip Memory Instruction Set Simulator Joint Test Action Group Library Generator sub component of the Xilinx Platform Studio technology Local Memory Bus A low latency synchronous bus primarily used to access on chip block RAM The MicroBlaze processor contains an instruction LMB bus and a data LMB bus Microprocessor Driver Description file Microprocessor Debug Module LibXil Memory File System The MFS provides user capability to manage program memory in the form of file handles Microprocessor Hardware Specification file The MHS file defines the configuration of the embedded processor system including buses peripherals processors connectivity and address space Microprocessor Library Definition file www xilinx com 297 XILINX 298 MOST MPD file MSS file MVS file NGC file NGD file NCF file NGO File NPI NPL File OCM Appendix D Glossary Media Oriented Systems Transport A developing standard in automotive network devices Microprocessor Peripheral Definition file The MPD file contains all of the available ports and hardware parameters for a peripheral Microprocessor Software Specification file Microprocessor Verific
130. SIZE The default value of HEAP SIZE is zero Dynamic memory allocation routines use the heap If your program uses the heap in this fashion then you must provide a reasonable value for HEAP SIZE For advanced users you can generate linker scripts directly from XPS Memory Layout The MicroBlaze and PowerPC processors use 32 bit logical addresses and can address any memory in the system in the range 0x0 to OxFFFFFFFF This address range can be categorized into the following types e Reserved memory e O memory Reserved Memory Reserved memory has been defined by the hardware and software programming environment for privileged use This is typically true for memory containing interrupt vector locations and operating system level routines Table 8 5 page 121 lists the reserved memory locations for MicroBlaze and PowerPC as defined by the processor hardware For more information on these memory locations refer to the corresponding processor reference manuals 120 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Note In addition to these memories that are reserved for hardware use your software environment can reserve other memories Refer to the manual of the particular software platform that you are using to find out if any memory locations are deemed reserved Table 8 5 Hardware Reserved Memory Locations t Default Text Processor Family Reserved Me
131. Simulation XILINX Bus Functional Models BFMs BFMs are hardware components that include and model a bus interface There are different BFMs for different buses For example there are OPB BFM components and PLB BFM components Each is used to connect to its own respective bus For each bus there are different model types For example the OPB bus has OPB Master OPB Slave and OPB Monitor BFM components The same set of components and more could exist for other busses or the functionality of BFM components could be combined into a single model Bus Functional Language BFL The BFL describes the behavior of the BFM components You can specify how to initiate or respond to bus transactions using commands in a BFL file Bus Functional Compiler BFC The BFC translates a BFL file into the commands that actually program the selected Bus Functional Model Bus Functional Model Use Cases There are two main use cases for Bus Functional Models e IP verification e Speed Up simulation IP Verification When verifying a single piece of IP that includes a bus interface you concern yourself with the internal details of the IP design and the bus interactions It is inefficient to attach the IP to a large system only to verify that it is functioning properly The following figure shows an example in which a master BFM generates bus transactions to which the device under test responds The monitor BFM reports any errors regarding the bu
132. Specification Format Reference Manual and Additional Keywords in the Merged Hardware Datastructure on page 290 xget hw value handle Description Arguments Gets the value associated with the specified handle handle is of specified type If handle is of type IP instance its value is the IP module name For example if the handle refers to the MicroBlaze instance in the MHS file the value the API returns is the name of the IP that is microblaze Similarly to get the value of a parameter from a parameter handle you can use the same command Embedded System Tools Reference Manual www xilinx com 265 UG111 EDK 11 3 1 7 XILINX Appendix C EDK Tcl Interface Tcl Example Procedures The following are example Tcl procedures that use some of the hardware API Tcl commands 266 Example 1 This procedure explains how to get a list of IPs of a particular IPTYPE Each IP provided in the EDK repository has a corresponding IP type specified by the IPTYPE option in the MPD file The merged mhs instance has the information from both the MHS file and the MPD file The process for getting a list of IPs of a particular IPTYPE is 1 2 Using the merged mhs handle get a list of all IPs Iterate over this list and for each ID get the value of the OPTION IPTYPE and compare it with the given IP type The following code snippet illustrates how to get the IPTYPE of specific IPs HH Procedure to
133. System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX JTAG Cable Options The following options allow you to specify the Xilinx JTAG cable used to connect to target Table 9 8 JTAG Cable Options Option Description fname lt filename svf gt Filename for creating the Serial Vector Format SVF file frequency Specify the cable clock speed in Hertz lt cable speed in Hz gt Valid Cables speeds are e For Parallel 4 5000000 default 2500000 200000 e For Platform USB 24000000 12000000 6000000 default 3000000 1500000 750000 port port name Specify the port Valid arguments for port are Ipt1 Ipt2 usb21 usb22 type cable type Specify the cable type Valid cable types are e xilinx parallel3 e xilinx parallel4 e xilinx platformusb e xilinx svffile In the case of xilinx_svffile the JTAG commands are written into a file specified by the name option JTAG Chain Options The following options allow you to specify device information of non Xilinx devices in the JTAG chain Refer to Example Showing Special JTAG Chain Setup for Non Xilinx Devices on page 176 Table 9 9 JTAG Chain Options Option Description devicenr device position The position of the device in the JTAG chain The device position number starts from 1 irlength length of the JTAG The length of the IR register of the device This
134. The compiler prefixes 1ib to the library name that you provide The compiler is sensitive to the order in which you provide options particularly the 1 command line switch Provide this switch only after all of the sources in the command line For example if you create your own library called libproject a you can include functions from this library using the following command Compiler Source Files L LIBDIR 1 project Caution f you supply the library flag 1 1ibrary name before the source files the compiler does not find the functions called from any of the sources This is because the compiler search is only done in one direction and it does not keep a list of available libraries L Lib Directory This option indicates the directories in which to search for the libraries The compiler has a default library search path where it looks for the standard library Using the L option you can include some additional directories in the compiler search path Header File Search Option I Directory Name This option searches for header files in the dir name directory before searching the header files in the standard path Default Search Paths The compilers mb gcc and powerpc eabi gcc search certain paths for libraries and header files The search paths on the various platforms are described below The compilers search libraries in the following order 1 Directories are passed to the compiler with the L dir name optio
135. To use the GNU compiler type lt Compiler_Name gt options files where lt Compiler_Name gt is powerpc eabi gcc ormb gcc To compile C programs you can use either the powerpc eabi g or the mb g command Input Files The compilers take one or more of the following files as input e C source files e C source files e Assembly files e Object files e Linker scripts Note These files are optional If they are not specified the default linker script embedded in the linker mb 1d or powerpc eabi 1d is used The default extensions for each of these types are listed in Table 8 1 In addition to the files mentioned above the compiler implicitly refers to the libraries files 1ibc a libgcc a libm a and libxil a The default location for these files is the EDK installation directory When using the G compiler the Libsupc aand libstdc a files are also referenced These are the C language support and C platform libraries respectively Output Files The compiler generates the following files as output e AnELF file The default output file name is a out on Solaris and a exe on Windows e Assembly file if save temps or S option is used e Object file if save temps or c option is used e Preprocessor output i or ii file if save temps option is used 112 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX File Types and Extensions The GNU co
136. X Appendix A GNU Utilities mb c This is the same cross compiler as mb gcc invoked with the programming language set to C This is the same as mb g mb c filt This program performs name demangling for C and Java function names in assembly listings mb g This is the same cross compiler as mb gcc invoked with the programming language set to C This is the same as mb c mb gasp This is the macro preprocessor for the assembler program mb gcc This is the cross compiler for C and C programs It automatically identifies the programming language used based on the file extension mb gdb This is the debugger for programs mb gprof This is a profiling program that allows you to analyze how much time is spent in each part of your program It is useful for optimizing run time mb ld This is the linker program It combines library and object files performing any relocation necessary and generates an executable file mb nm This program lists the symbols in an object file mb objcopy This program translates the contents of an object file from one format to another mb objdump This program displays information about an object file This is very useful in debugging programs and is typically used to verify that the correct utilities and data are in the correct memory location 234 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Other Programs and Files XILINX mb ranlib This program c
137. ach way has 16 sets then 0x70000000 0x700001FF is mapped to I Cache way 0 and 0x70000200 0x700003FF is mapped to I Cache way 1 Cache Tag and Parity Access The cache tag address space contains the tag status and parity information of the cache entries for the corresponding cache address space In the provided example the tag information for I Cache entry at 0x70000100 is available at 0x70008100 and the tag information for the D Cache entry at 0x78000600 is available at 0x78008600 The PowerPC 405 processor uses one word to store the tag and status of one cache line and one word to store parities The PowerPC 440 processor also uses two words first word is tag low and second word is tag high to store the tag of one cache line For more information on how to translate the tag bits refer to the icread and dcread instructions in the respective PowerPC405 User Manual or PowerPC440 User Manual A link to these documents can be found in Additional Resources on page 152 Because the cacheline size is 32 bytes the tag values repeat within the same cacheline Embedded System Tools Reference Manual www xilinx com 179 UG111 EDK 11 3 1 XILINX 180 Connect Command Options DCR Address Spaces Although the DCR bus is not in the same address domain as the PLB bus you can access the DCR bus in XMD through the PLB address map Each DCR address corresponds to one DCR register which has 4 bytes When it is mapped to the PLB address it need
138. ad the program into the target b main Set a breakpoint in function main c Continue after a breakpoint Note Do not use the run command 1 View a listing of the program at the current point n Steps one line stepping over function calls s Step one line stepping into function calls stepi Step one assembly line info reg View register values info target View the number of instructions and cycles executed for the built in simulator only p lt xyz gt Print the value of xyz data hbreak main Set hardware breakpoint in function main watch gvari Set Watchpoint on Global Variable gvar1 rwatch gvari Set Read Watchpoint on Global Variable gvar1 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 201 XILINX GDB Command Reference 202 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 11 Bitstream Initializer BitInit Overview Tool Usage Tool Options This Bitstream Initializer BitInit utility chapter contains the following sections e Overview e Tool Usage e Tool Options BitInit initializes the instruction memory of processors on the FPGA which is stored in block RAMs in the FPGA This utility reads an Microprocessor Hardware Specification MHS file and invokes the Data2MEM utility provided in ISE to initialize the FPGA block RA Ms To invo
139. age conventions as well as a description of the standard memory model used by the compiler A link to the document is provided in the Additional Resources on page 109 MicroBlaze Assembler The mb as assembler for the Xilinx MicroBlaze soft processor supports the same set of options supported by the standard GNU compiler tools It also supports the same set of assembler directives supported by the standard GNU assembler The mb as assembler supports all the opcodes in the MicroBlaze machine instruction set with the exception of the imm instruction The mb as assembler generates imm instructions when large immediate values are used The assembly language programmer is never required to write code with imm instructions For more information on the MicroBlaze instruction set refer to the MicroBlaze Processor Reference Guide A link to the document is provided in the Additional Resources on page 109 The mb as assembler requires all MicroBlaze instructions with an immediate operand to be specified as a constant or a label If the instruction requires a PC relative operand then the mb as assembler computes it and includes an imm instruction if necessary For example the Branch Immediate if Equal beqi instruction requires a PC relative operand The assembly programmer should use this instruction as follows begi r3 mytargetlabel where mytargetlabel is the label of the target instruction The mb as assembler computes the immediate value o
140. al UG111 EDK 11 3 1 Chapter 7 Library Generator Libgen Table 7 1 7 XILINX Libgen Syntax Options Cont d Option Library path for user peripherals and driver repositories Command lp Library Path Description Specifies a library containing repositories of user peripherals drivers OSs and libraries Libgen looks for the following e Drivers in the directory lt Library_Path gt sub_dir drivers e Libraries in the directory lt Library_Path gt sub_dir sw_services e OSs in the directory lt Library_Path gt sub_dir bsp Hardware Specification File hw lt hwspecfile xml gt Specifies the hardware specification file XML to be used for Libgen The hardware specification file describes the complete hardware system to LibGen MHS file mhs lt mhsfile mhs gt Specifies the Microprocessor Hardware Specification MHS file to be used for Libgen The following is the order Libgen uses to search and locate mhsfile mhs 1 Current working directory YOUR PROJECT 2 Ifthere is no mhs option specified the filename used is the MHS file which has the same name as the MSS file Libraries lib Use this option to copy libraries and drivers but not to compile them Processor instance specific Libgen run pe mblaze_0 This command runs Libgen for a specific processor instance Embedded System Tools Reference Manual UG111 EDK 11 3 1
141. alue 1234 is used No Initialization file Does not source xmd ini file on startup Option File opt connect option file Specifies the option file to use to connect to target The option file contains the XMD connect command to target Tcl File tcl tclfile tclarg Specifies the XMD Tcl script to run The lt tclargs gt are arguments to the Tcl script This Tcl file is sourced from XMD XMD quits after executing the Script No other option can follow tc1 Version TV Displays the version then quits XMP File xmp lt xmpfile gt Specifies the XMP file to load Upon startup XMD does the following e fan XMD Td script is specified XMD executes the script then quits e Ifan XMD Tcl script is not specified XMD starts in interactive mode In this case XMD does the following 1 Creates source HOMI Tcl commands using XMD commands If hw option is given loads the XML file E xmdrc file You can use this configuration file to form custom If nx option is not given sources the xmd ini file if present in the current directory If opt option is given uses Connect option file to connect to processor target f ipcport option is given opens XMD socket server If xmp option is given loads system XMP file 2 Displays the XMD prompt From the XMD Tc1 prompt you can use XMD commands for debugging as described in the ne
142. alue mymblaze xmdstub init bram false This assumes that there is no software application by the same name If there is an application with same name you will not be able to change the settings using the XPS Tcl interface Therefore in XPS no window mode you should not create an application with name procinst bootloopOr procinst xmdstub This limitation is valid only for XPS no window mode and does not apply if you are using the GUI interface MSS Changes XPS batch supports limited MSS editing If you want to make any changes in the MSS file you must hand edit the file make the changes and then run the xload mss command to load the changes into XPS You do not have to close the project You can save the MSS file edit it and then re load it into the project with the xload mss command XMP Changes 68 Xilinx recommends that you do not edit the XMP file manually The XPS batch mode supports changing project options through commands It also supports adding source and header files to a processor and setting any compiler options Any other changes must be done from XPS www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 5 Bus Functional Model Simulation This chapter describes Bus Functional Model BFM simulation within Xilinx Platform Studio The following topics are included Introduction Bus Functional Simulation Basics Bus Functional Model Use Case
143. an be modified as desired If your target development board is not available or not currently supported by the BSB wizard you can select the Custom Board option instead of selecting a target board Using this option you can specify the individual hardware devices that you expect to have on your custom board To run the generated system on a custom board you enter the FPGA pin location constraints into the User Constraints File UCF If a supported target board is selected the BSB wizard inserts these constraints into the UCF automatically The BSB wizard can generate one or more optional software projects Each project contains a sample application and linker script that can be compiled and run on the hardware for the target development board Each application is designed to illustrate system aliveness and perform simple and basic testing of some of the hardware The contents of each test application varies depending on the components in your system For detailed information on using the features provided in the BSB wizard see the Xilinx Platform Studio Help The Create and Import Peripheral CIP Wizard The CIP wizard helps you create your own peripherals and import them into XPS compliant repositories or projects In the Create mode the CIP wizard creates templates that help you implement your peripheral without requiring detailed understanding of the bus protocols naming conventions or the formats of special interface files required
144. andle associates with the parameter object of a particular instance of that IP MPD snippet PARAMETER C_PARAM1 ES PARAMETER C PARAM2 0 IPLEVEL UPDATE VALUE PROC update param2 I A Tcl computes value based on other parameters on the IP Argument param handle points to C PARAM2 because the Tcl is associated with C PARAM2 proc update param2 param handle set retval 0 set mhsinst xget hw parent handle param handle set paramlval xget hw param value mhsinst C PARAM if Sparamlval gt 4 set retval 1 return retval DRC Procedure for a Parameter Before System Level Analysis You can use the parameter subproperty IPLEVEL_DRC_PROC to specify the Tcl procedure that performs DRCs specific to that parameter These DRCs should be independent of other PARAMETER values on that IP For example this DRC can be used to ensure that only valid values are specified for that parameter The input handle is a handle to the parameter object for a particular instance of that IP MPD snippet PARAMETER C_PARAM1 0 IPLEVEL_DRC_PROC drc_paraml Tcl snippet Argument param_handle points to C_PARAM1 since the Tcl is associated with C_PARAM1 proc drc_paraml param_handle set paramlval xget hw value param handle if Sparamlval gt 5 error C_PARAM1 value should be less 5 return 1 else return 0 286 www xilinx com Embedded Sy
145. andle only and not the original IP instance handle Consequently the various property handles the parameter and port handles for example are merged handles and not the original handles 258 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 EDK Hardware Tcl Commands XILINX Hardware Read Access APls The following sections contain a summary table and descriptions of defined hardware read access APIs To go to the API descriptions which are provided in the following section click on a summary link API Summary Table C 1 Hardware API Summary xget_hw_busif_value lt handle gt lt busif_name gt xget_hw_bus_slave_addrpairs lt merged_bus_handle gt xget_hw_busif_handle lt handle gt lt busif_name gt xget_hw_connected_busifs_handle lt merged_mhs_handle gt lt businst_name gt lt busif_type gt xget_hw_connected_ports_handle lt merged_mhs_handle gt lt connector_name gt lt port_type gt xget_hw_ioif_handle lt handle gt lt ioif_name gt xget hw ioif value handle lt ioif_name gt xget hw ipinst handle mhs handle ipinst name xget hw mpd handle ipinst handle xget hw name handle xget hw option handle handle option name xget hw option value handle option name xget hw parameter handle handle parameter name xget hw parameter value handle parameter name xget hw pcore dir from mpd mpd handle xget hw pcore dir ipinst handle xget hw port
146. anual UG111 EDK 11 3 1 XILINX Design Process Overview The hardware platform consists of one or more processors and peripherals connected to the processor buses XPS captures the hardware platform in the Microprocessor Hardware Specification MHS file The MHS file is the principal source file that maintains the hardware platform description and represents in ASCII text the hardware components of your embedded system Software Development A software platform is a collection of software drivers and optionally the operating system on which to build your application The created software image contains only the portions of the Xilinx library you use in your embedded design You can create multiple applications to run on the software platform Verification EDK provides both hardware and software verification tools The following subsections describe the verification tools available for hardware and software Hardware Verification Using Simulation To verify the correct functionality of your hardware platform you can create a simulation model and run it on an Hardware Design Language HDL simulator When simulating your system the processor s execute your software programs You can choose to create a behavioral structural or timing accurate simulation model Software Verification Using Debugging The following options are available for software verification e You can load your design on a supported development board and use a
147. arget id state system system id state target id state system system id elf file srrd srrd Reads special purpose registers or reads srrd register name srrd pc reg name register stackcheck stackcheck Gives the stack usage information of the program running on the current target The most recent ELF file downloaded on the target is taken into account for stack check state state When no target id is specified the command displays the current state of all targets When a target id is specified state of that target is displayed When system system id is specified the current state of all the targets in the system is displayed stats stats lt filename gt stats trace txt stats Displays execution statistics for the ISS target The ilename is the trace output from trace collection 158 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Table 9 2 XMD User Commands Cont d command options Example Usage Description stop stop Stops the target For MicroBlaze if the program is stalled at memory or FSL access it is stopped forcibly stp stp Steps through the specified number of stp number of instructions stp 10 instructions targets targets Lists information about all current targets or targets target id targets 0 changes
148. ary directory contain customized versions of the libraries for a particular configuration For instance the double directory contains the version of libraries for use with a double precision FPU whereas the 440 subdirectory contains the version of libraries suited for use with PowerPC 440 processor Thread Safety The C and math libraries for the PowerPC processor distributed with EDK are not built to be used in a multi threaded environment Common C library functions such as printf scanf malloc and free are not thread safe and will cause unrecoverable errors in the system at run time Use appropriate mutual exclusion mechanisms when using the EDK libraries in a multi threaded environment Command Line Arguments PowerPC processor programs cannot take in command line arguments The command line arguments argc and argy are initialized to zero by the C runtime routines Embedded System Tools Reference Manual www xilinx com 149 UG111 EDK 11 3 1 7 XILINX Other Notes C Code Size 150 Other Notes The GCC toolchain combined with the latest open source C standard library libstdc v3 might be found to generate large code and data fragments as compared to an equivalent C program A significant portion of this overhead comes from code and data for exception handling and runtime type information Some C applications do not require these features To remove the overhead and optimize for size use the no
149. ated with these parameters To have the PsfUtility infer this information automatically all specified conventions must be followed for reserved generics as well This can help prevent errors when your peripheral requires information on the platform that is generated Table 2 3 page 37 lists the reserved generic names www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility Embedded System Tools Reference Manual UG111 EDK 11 3 1 Table 2 3 Automatically Expanded Reserved Generics 7 XILINX Parameter C_FAMILY Description FPGA device family C_INSTANCE Instance name of component C_ lt BI gt OPB_NUM_MASTERS Number of OPB masters C_ lt BI gt OPB_NUM_SLAVES Number of OPB slaves C_ lt BI gt DCR_AWIDTH DCR address width C_ lt BI gt DCR_DWIDTH DCR data width C_ lt BI gt DCR_NUM_SLAVES Number of DCR slaves C BI FSL DWIDTH FSL data width C_ lt BI gt LMB_AWIDTH LMB address width C_ lt BI gt LMB_DWIDTH LMB data width C_ lt BI gt LMB_NUM_SLAVES Number of LMB slaves C_ lt BI gt OPB_AWIDTH OPB address width C_ lt BI gt OPB_DWIDTH OPB data width C_ lt BI gt PLB_AWIDTH PLB address width C_ lt BI gt PLB_DWIDTH PLB data width C_ lt BI gt PLB_MID_WIDTH PLB master ID width C_ lt BI gt PLB_NUM_MASTERS Number of PLB masters C_ lt BI gt PLB_NUM_SLAVES Number of PLB sla
150. ation Specification file The NGC file is a netlist file that contains both logical design data and constraints This file replaces both EDIF and NCF files Native Generic Database file The NGD file is a netlist file that represents the entire design Netlist Constraints file A Xilinx specific format binary file containing a logical description of the design in terms of its original components and hierarchy Native Port Interface Xilinx Integrated Software Environment ISE Project Navigator project file On Chip Memory www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Terms Used in EDK OPB PACE PAO file PBD file Platgen PLB PROM PSF SDF file SDK SDMA Simgen Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX On chip Peripheral Bus Pinout and Area Constraints Editor Peripheral Analyze Order file The PAO file defines the ordered list of HDL files needed for synthesis and simulation Processor Block Diagram file Hardware Platform Generator sub component of the Platform Studio technology Processor Local Bus Programmable ROM Platform Specification Format The specification for the set of data files that drive the EDK tools Standard Data Format file A data format that uses fields of fixed length to transfer data between multiple programs Software Development Kit Soft Direct Memory Access The Simulation Generator s
151. ations can be obtained without any additional attributes added to the source code Signal Naming Conventions The signal names must follow the conventions specified in Conventions for Defining HDL Peripherals on page 34 When there is only one bus interface no bus identifier need be specified for the bus signals Invoking the PsfUtility The command line for invoking PsfUtility is as follows psfutil hdl2mpd hdlfile lang vhdl ver top top entity bus lt busstd gt lt bustype gt o lt mpdfile gt For example to create an MPD specification for an PLB slave peripheral such as UART the command is psfutil hdl2mpd uart prj lang vhdl top uart bus plb s o uart mpd Peripherals with Multiple Bus Interfaces Some peripherals might have multiple associated bus interfaces These interfaces can be exclusive bus interfaces non exclusive bus interfaces or a combination of both All bus interfaces on the peripheral that can be connected to the peripheral simultaneously are exclusive interfaces For example an OPB Slave bus interface and a DCR Slave bus interface are exclusive because they can be connected simultaneously Note On a peripheral containing exclusive bus interfaces a port can be connected to only one of the exclusive bus interfaces Non exclusive bus interfaces cannot be connected simultaneously Note Peripherals with non exclusive bus interfaces have ports that can be connected to more than one of th
152. ator Specify one or more point to point connections for the peripheral o outfile Specify output filename default is stdout PAO file to MPD pao2mpd paofile Generate MPD from Peripheral Analyze Order PAO file Suboptions are lang ver vhd1 Specify language top design Specify top level entity or module name bus opb p1b plbv46 dcr lmb fsl m s ms mb lt busif_name gt Specify one or more peripherals and optional interface name s p2pbus busif name bus std target initiator Specify one or more point to point connections of the peripheral o outfile Specify output filename default is stdout Display version v Displays the version number information Note 1 Bus type mb master that generates burst transactions is valid for bus standard PLBv46 only 2 Deprecated in this release 30 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility XILINX MPD Creation Process Overview You can use the PsfUtility to create MPD specifications from the HDL specification of the core automatically To create a peripheral and deliver it through EDK 1 Code the IP in VHDL or Verilog using the required naming conventions for Bus Clock Reset and Interrupt signals These naming conventions are described in detail in Conventions for Defining HDL Peripherals on page 3
153. attes pepe nde n diia 125 MicroBlaze Compiler Usage and Opti0MS oooocoocccococcccccccccno 126 MicroBlaze Compiler ie cbe caged etane eR ye Ee E oe E 126 MicroBlaze Compiler Options Quick Reference 0 00000 ee eee 126 Processor Feature Selection Options as as 6 6 cece eee eens 126 General Program OPti0NS ooooooocconnccrononncrnrr eens 129 Application Execution Modes 0 0 ccc ccc nn 130 Position Independent Code 2592 gate siecle A e m abd 131 MicroBlaze Application Binary Interface 6 666 131 MicroBlaze Assembler 0 0 0000s 131 MicroBlaze Linker Options 0 0 0 06 c ccc ene eens 133 MicroBlaze Linker Script Sections 666 nee 134 Tips for Writing or Customizing Linker Scripts 600 c cece eee eee eee 135 Startup Piles uni pots pi RAR ies Reread 135 First Stage Initialization Files 6 cee eens 136 Second Stage Initialization Files 6 6 e 137 Otherfil sz sso scien edes dae rs eb SEE EE eee wet d repe et 138 Modifying Startup Piles sc sae ieee nga ide RESI e Db Re ea geras 138 Reducing the Startup Code Size for C Programs 6 2 0 66sec ee eee 139 Compiler Libraries scott etr o aote s UE 139 Thread Safety a coronas ek b eek ek AR steed cree Pi da e ped xa 140 Command Line Arguments osiers Kerri eE oa nn 140 Interrupt Handler ii Ye EXPERS EXP Vae ee vac exea CROP 141 PowerPC Compiler Usage and Options 00 0 e eee eee 142 PowerP
154. atures and options that are unique to the MicroBlaze compiler are described in the sections that follow When compiling with the MicroBlaze compiler the pre processor provides the definition MICROBLAZE automatically You can use this definition in any conditional code MicroBlaze Compiler The mb gcc compiler for the Xilinx MicroBlaze soft processor introduces new options as well as modifications to certain options supported by the GNU compiler tools The new and modified options are summarized in this chapter MicroBlaze Compiler Options Quick Reference Click an option name below to view its description Processor Feature Selection Options mcpuzvX YY Z General Program Options mno xl soft mul msmall divides mxl multiply high mxl gp opt mno xl multiply high mno clearbss mxl soft mul mxl stack check mno xl soft div Application Execution Modes mxl soft div xl mode executable mxl barrel shift xl mode xmdstub mno xl barrel shift xl mode bootstrap mxl pattern compare xl mode novectors mno xl pattern compare MicroBlaze Linker Options mhard float defsym TEXT START ADDR value msoft float relax mxl float convert N mxl float sqrt Processor Feature Selection Options mcpu vX YY Z This option directs the compiler to generate code suited to MicroBlaze hardware version v X YY Z To get the most optimized and correct code for a given processor use this switch with the hardware version of the processor T
155. bi gcc is built out of the sources for the PowerPC processor port as distributed by GNU foundation The compiler is customized for Xilinx purposes The features and options that are unique to the version distributed with EDK are described in the following sections When compiling with the PowerPC processor compiler the pre processor automatically provides the definition PPC Youcanuse this definition in any conditional code that you have mcpu 440 Target code for the 440 processor This includes instruction scheduling optimizations enable or disable instruction workarounds as well as usage of libraries targeted for the 440 processor mfpu sp lite sp full dp lite dp full none Generate hardware floating point instructions to use with the Xilinx PowerPC processor APU FPU coprocessor hardware The instructions and code output follow the floating point specification in the PowerPC Book E with some exceptions tailored to the APU FPU hardware Book E is available from the IBM web page Refer to the FPU hardware documentation for more information on the architecture Links to Book E and to the FPU documentation are available in the Additional Resources on page 109 The option given to mfpu determines which variant of the FPU hardware to target The variants are as follows sp lite Produces code targeted to the Single precision Lite FPU coprocessor This version supports only single precision hardware floating point and does not use
156. ble automatically and chains the FPGA device containing the MicroBlaze MDM system If XMD is unable to detect the JTAG chain or the FPGA device automatically you can explicitly specify them using the following options Usage connect mb hw cable JTAG Cable options gt configdevice JTAG chain options debugdevice MicroBlaze options gt JTAG Cable Options and JTAG Chain Options For JTAG cable and chain option descriptions refer to Table 9 8 JTAG Cable Options on page 169 and Table 9 9 JTAG Chain Options on page 169 respectively MicroBlaze Options The following table describes MicroBlaze options Table 9 14 MicroBlaze Options Option Description cpunr CPU Number Specific MicroBlaze processor number to be debugged in an FPGA containing multiple MicroBlaze processors connected to MDM The processor number starts from 1 devicenr Position in the JTAG chain of the FPGA device MicroBlaze device position containing the MicroBlaze processor The device position number starts from 1 Embedded System Tools Reference Manual www xilinx com 181 UG111 EDK 11 3 1 7 XILINX Connect Command Options Table 9 14 MicroBlaze Options Cont d Option Description romemstartadr Start address of Read Only Memory lt ROM start address gt Use this to specify flash memory range XMD sets hardware breakpoints instead of software breakpoints romemsize Size of Read On
157. bprop name is the name of the subproperty Example set subprop handle xget sw subproperty handle prop handle lt subprop_name gt xget sw subproperty value property handle subprop name Description Returns the value of a specified subproperty Arguments property handle is the name of the property subprop name is the name of the subproperty Example set subprop value xget sw subproperty handle prop handle lt subprop_name gt Embedded System Tools Reference Manual www xilinx com 283 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface xget sw value handle Description Returns the value associated with the specified handle a handle of type PARAMETER has a value of that parameter Arguments handle is of specified type Example Get the value of a PARAMETER called stdin in the MSS file of an OS instance that is assigned UART 0 the value returned by the API of uart0 set stdin value xget sw value stdin param handle Tcl Flow During Hardware Platform Generation Input Files Platgen Simgen Libgen and other tools that create the hardware platform work with the MHS design file and the IP data files MPD Internally the tools create the system view based on these files Each of the IP in the design has an MPD associated with it Optionally it can have an associated Tcl file Tcl files can contain DRC procedures procedures to automate calculation of paramete
158. c a libm a and libxil a libraries The 1ibxi1 library contains driver functions that the particular processor can access For more information about the libraries refer to the introductory section of the OS and Libraries Document Collection A link to the document is supplied in the Additional Resources page 100 libsrc Directory The 1ibsrc directory contains intermediate files and make files needed to compile the OSs libraries and drivers The directory contains peripheral specific driver files BSP files for the OS and library files that are copied from the EDK and your driver OS and library directories Refer to the Drivers page 106 OS Block page 107 and Libraries page 107 sections of this chapter for more information code Directory 104 The code directory is a repository for EDK executables Libgen creates an xmdstub elf file for MicroBlaze on board debug in this directory Note Libgen removes these directories every time you run the tool You must put your sources executables and any other files in an area that you create www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 7 Library Generator Libgen XILINX Generating Libraries and Drivers Overview This section provides and overview of generating libraries and drivers The MHS and the MSS files define a system For each processor in the system Libgen finds the list of addressable peripherals For each process
159. cal data that contribute to the program memory image This section has the same flags as bss and it must be mapped to RAM tdata This section holds initialized thread local data that contribute to the program memory image This section must be mapped to initialized RAM gcc except table This section holds language specific data This section must be mapped to initialized RAM jcr This section contains information necessary for registering compiled Java classes The contents are compiler specific and used by compiler initialization functions This section must be mapped to initialized RAM fixup This section contains information necessary for doing fixup such as the fixup page table and the fixup record table This section must be mapped to initialized RAM www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Linker Scripts The linker utility uses commands specified in linker scripts to divide your program on different blocks of memories It describes the mapping between all of the sections in all of the input object files to output sections in the executable file The output sections are mapped to memories in the system You do not need a linker script if you do not want to change the default contiguous assignment of program contents to memory There is a default linker script provided with the linker that places section contents contiguously You can selectively
160. cds 106 Drivers PN NM C prr IPTE 106 lj a 107 10 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 7 XILINX OS Block 107 Chapter 8 GNU Compiler Tools COVORVIEW MD LEE 109 Additional Resources 17e ia Orb ds eO tien UE Ro ORI eR 109 Compiler Framework ooooococccccccoconccccn crono 110 Common Compiler Usage and Options utu 112 Us BE iaces erar tte eei deese e ee id ee ie een pee de ee 112 Tnput Bes P ww 0 lili 112 Output Files tte p eben A epa ee bee e desees 112 File Types and Extensions sssssssssssse eee 113 Libraries C A dee id 113 Language Dialect esee pep ePRRES ern EORR ER EE Ne Reese Roe Fr e paa 114 Commonly Used Compiler Options Quick Reference oooooooommmmmmoo 115 General Options eer eda mte eee paste egent eee i tede ade d 115 Library Search Options oieri iere cee nee eee 118 Header File Search Option 0 2 6 ccc eee eee eee 118 Default Search Paths 5 os ete re eye qu me ea ee rd e aor ds 118 Linker Options cese eee vage noni eese ees eandem i oed desdted E 120 Memory Layout Eie Cet ERI Edere P der e eoe do Pob eee gd 120 Reserved Memory ew tasted ed e peek rcp OFEN ees ER ud 120 VO MeMO ayee Ea a AA AS ES AAA A dete ios 121 User and Program Memory oooococcooccocnn rr 121 Object File SCCHONS e decirte aed dei C OE o da o PE da aed 122 Linker Scripts eoe ede etie p
161. ce and a DCR Slave interface the command is psfutil hdl2mpd mem prj lang vhdl top mem bus plb s bus dcr s o mem prj Peripherals with Point to Point Connections Some peripherals such as multi channel memory controllers might have point to point connections BUS STD XIL MEMORY CHANNEL BUS TYPE TARGET Signal Naming Conventions The signal names must follow conventions such that all signals belonging to the point to point connection start with the same bus interface name prefix such as MCHO_ Invoking the PsfUtility with Point to Point Connections Specified in the Command Line You can specify point to point connections in the command line using the bus interface name as a prefix to the bus signals The command line for invoking PsfUtil is psfutil hdl2mpd hdlfile lang vhdl ver top top entity p2pbus busif name bus std target initiator o lt mpdfile gt For example to create an MPD specification for a peripheral with an MCH0 connection the command is psfutil hdl2mpd mch mem prj lang vhdl top mch mem p2pbus MCHO XIL MEMORY CHANNEL TARGET o mch mem mpd Embedded System Tools Reference Manual www xilinx com 33 UG111 EDK 11 3 1 7 XILINX DRC Checks in PsfUtility DRC Checks in PsfUtility To enable generation of correct and complete MPD files from HDL sources the PsfUtility reports DRC errors The DRC checks are listed in the following subsections in the order they are performe
162. cessor System Configuration The assumed configuration is with two PowerPC processors and a MicroBlaze processor each loaded with a single ELF file The board configuration is specified in the options file jprog hw implementation download bit ace system ace board user configdevice devicenr 1 idcode 0x1266093 irlength 14 partname XC2VP20 Options for PowerPC Processor 1 Target Type ELF files amp debugdevice devicenr 1 cpunr 1 target ppc_hw elf executablel elf Data files Options for PowerPC Processor 2 Target Type ELF files amp Data files debugdevice devicenr 1 cpunr 2 target ppc_hw elf executable2 elf Options for MicroBlaze Processor Target Type ELF files amp Data files debugdevice devicenr 1 cpunr 1 target mdm elf executable3 elf Note When multi processors are specified in an OPT file processor specific options such as target type ELF data files should follow debugdevice option for that processor The cpunr of the processor is inferred from debugdevice option 212 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 12 System ACE File Generator GenACE XILINX Multiple FPGA Devices The assumed configuration is with two FPGA devices each with a single processor and a single ELF file The configuration of the board is specified in the options file This configuration requires multiple steps to generate the ACE file 1 Genera
163. clude the execution of illegal instructions and bus errors Use the following steps 1 Download the program 2 Runthe safemode on command 3 Startthe program with the con command The program stops when an exception occurs This feature is more useful when working with the GUI debugger either Insight GDB or SDK e When using SDK check the Enable Sa emode checkbox box in the Initialization tab before running the program e When using GDB download the program and run the safemode on command in XMD console before running the program in GDB When the exception occurs the program stops and the GUI shows the line of code that triggered the exception Processor Default Exception Settings The following tables show the factory default settings for exception trapping settings by processor types Table 9 5 PowerPC Processor Exception Settings Exception id Trap Exception Name 0 No External critical interrupt exception 1 Yes External bus error exception 2 Yes Data storage exception 3 Yes Instruction storage exception 4 No External noncritical interrupt exception 5 No Unaligned data access exception 6 Yes Illegal op code exception 7 Yes FPU non available exception 8 No System call instruction Embedded System Tools Reference Manual www xilinx com 165 UG111 EDK 11 3 1 7 XILINX XMD User Commands Table 9 5 PowerPC Processor Exception Settings Cont d
164. connectors list ipinst handle lt portName gt xget hw parent handle handle xget hw port connectors list ipinst handle lt portName gt xget hw port handle handle port name xget hw port value handle port name xget hw proj setting prop name xget hw proc slave periphs merged proc handle xget hw subproperty handle property handle subprop name xget hw subproperty value property handle subprop name xget hw value handle Hardware API Descriptions xget hw busif handle handle busif name Description Returns a handle to the associated bus interface Arguments handle is the handle to the MPD original IP instance or merged IP instance busif name isthename of the bus interface whose handle is required If busif name is specified as an asterisk the API returns a list of bus interface handles To access an individual bus interface handle you can iterate over the list in Tcl Embedded System Tools Reference Manual www xilinx com 259 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface xget_hw_busif_value lt handle gt lt busif_name gt Description Returns the value of the specified bus interface The value is typically the instance name of the bus to which the bus interface is connected For a transparent bus interface the value is the connector which is not a bus instance name Arguments lt handle gt the handle to the MPD original IP i
165. d HDL Source Errors The PsfUtility returns a failure status if errors are found in the HDL source files Bus Interface Checks Depending on what bus interface is associated with which cores the PsfUtility does the following for every specified bus interface e Checks and reports any missing bus signals e Checks and reports any repeated bus signals The PsfUtility generates an MPD file when all bus interface checks are completed Conventions for Defining HDL Peripherals The top level HDL source file for an IP peripheral defines the interface for the design and has the following characteristics e Lists ports and default connectivity for bus interfaces e Lists parameters generics and default values e Parameters defined in the MHS overwrite corresponding HDL source parameters Individual peripheral documentation contains information on source file options 34 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility Naming Conventions for Bus Interfaces Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX A bus interface is a grouping of related interface signals For the automation tools to function properly you must adhere to the signal naming conventions and parameters associated with a bus interface When the signal naming conventions are correctly specified the following interface types are recognized automatically and the MP
166. d Software Configuration cesses ees 211 Hardware and Software Partial Reconfiguration oooocooocooroommm o 211 Hardware Only Configuration oocoocoocooccooccoacco eee ens 211 Hardware Only Partial Reconfiguration cesse ee 211 Software Only Configuration oooocoococccooconoco enn 212 Generating ACE for a Single Processor in Multi Processor SysteM 212 Multi Processor System Configuration 0 0 6 6 cece eee 212 Multiple FPGA Devices 6 ro 213 Related Information 0 0 0 0 0 000 I e 215 CF Device Format 2 22 eoe ia isla eee 215 Chapter 13 Flash Memory Programming Overview iia did dd a o a PLE REPE MEE 217 Flash Programming from XPS and SDK 00 00 e eee eee ee 218 Supported Flash Hardware 0 uisus esee 218 Flash Programmer Performance 00 00 cor 219 Customizing Flash Programming 0 60 00 e cece eee eee ees 220 Manual Conversion of ELF Files to SREC for Bootloader Applications 222 Operational Characteristics and Workarounds 0000 c cece eens 222 Handling Xilinx Platform Flash Modes 0 2 6 600 c cece cee eee eee 222 Handling Flash Devices with OxFO as the Read Reset Command 222 Handling Flash Devices with Conflicting Sector Layouts 0 0000 cues 222 Data Polling Algorithm for AMD Fujitsu Command Set 0000 eae 223 Chapter 14 Version Manage
167. data Loading section boot0 Loading section boot Start address Oxfffffffc Transfer rate 41344 bits sec gdb c Continuing size Oxfcc lma Oxffff8000 size 0x118 lma Oxffff8fdO0 size 0x2f8 lma Oxffff90e8 size 0x14 lma Oxffff93e0 size 0x20 lma Oxffff93f4 size Oxc lma Oxffff9414 size 0x10 lma Oxffffa430 size 0x4 lma Oxfffffffc load size 5168 323 bytes write For the console mode these two commands can also be placed in the GDB startup file gdb ini in the current working directory 200 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 10 GNU Debugger GDB GDB Command Reference XILINX For help on using mb gdb select Help gt Help Topics in the XPS main dialog box or type help in the console mode To open a console window from the GBD main dialog box select View Console For comprehensive online documentation on using GDB refer to the GNU web site For information about the mb gdb Insight GUI refer to the Red Hat Insight webpage Links to these documents are provided in the Additional Resources page 198 The following table describes the commonly used mb gdb console commands The equivalent GUI versions can be identified in the mb gdb GUI window icons Some of the commands such as info target and monitor info might be available only in the console mode Table 10 1 Commonly Used GDB Console Commands Command load program Description Lo
168. dded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com Chapter 9 Xilinx Microprocessor Debugger XMD 7 XILINX Register Memory Options Table 9 20 Register Memory Options Option xdata_verify lt target id lt Binary filename gt lt load address gt Description Verifies if the lt Binary filename gt was downloaded correctly at load address gt memory xdisassemble inst Disassembles and displays one 32 bit instruction xelf verify lt target id lt filename gt elf Verifies if the ilename elf is downloaded correctly to memory If ilename elf is not specified verifies the last downloaded ELF file to target xrmem lt target id gt lt address gt lt number of bytes half word gt b h w xrmem lt target id gt var lt Global Variable Name gt Reads lt number of bytes gt of memory locations from the specified memory address Defaults to byte b read Returns a list of data values The data type depends on the data width of memory access xwmem lt target id gt lt address gt lt number of bytes gt half word b h w lt value list gt xwmem lt target id gt var lt Global Variable Name gt lt value list gt Writes lt number of bytes gt data value from the specified memory address Defaults to byte b write xrreg target id reg Reads all registers or only register number reg xwreg target id reg value
169. design The Base System Builder BSB Wizard Allows you to quickly create a working embedded design using any features of a supported development board or using basic functionality common to most embedded systems For initial project creation it is recommended to use the BSB wizard The Create and Import Peripheral CIP Wizard Assists you in adding your own peripheral s to a design The CIP creates associated directories and data files required by XPS the Platform Specification Utility PsfUtility tool enables automatic generation of Microprocessor Peripheral Definition MPD files which are required to create IP peripherals that are compliant with the Embedded Development Kit EDK The CIP wizard in XPS supports features provided by the PsfUtility for MPD file creation recommended Coprocessor Wizard Helps you add a coprocessor to a CPU This applies to MicroBlaze based designs only Platform Generator Platgen Constructs the programmable system on a chip in the form of HDL and synthesized netlist files FXPS Command Line or no window Mode Allows you to run embedded design flows or change tool options from a command line Bus Functional Model BFM Helps simplify the verification of custom peripherals by creating a model of the bus environment to use in place of the actual embedded system Simulation Model Generator Simgen Generates the hardware simulation model and the compilatio
170. e Generating Libraries and Drivers e MSS Parameters e Drivers e Libraries e OS Block Overview Libgen is the first Embedded Design Kit EDK tool that you run to configure libraries and device drivers Libgen takes an XML file or a Microprocessor Software Specification MSS file that you create The XML file defines hardware system to Libgen and the MSS file describes the drivers associated with peripherals standard input and output devices interrupt handler routines and other related software features Libgen configures libraries and drivers with this information For further description on generating the XML file refer to the Software Development Kit SDK documentation in the SDK Online Help For further description of the MSS file format refer to the Microprocessor Software Specification MSS chapter in the Platform Specification Format Reference Manual A link to the document is supplied in Additional Resources page 100 Note EDK includes a Format Revision tool to convert older MSS file formats to a new MSS format Refer to Chapter 14 Version Management Tools revup for more information Embedded System Tools Reference Manual www xilinx com 99 UG111 EDK 11 3 1 7 XILINX Additional Resources Additional Resources e Platform Specification Format Reference Manual http www xilinx com ise embedded edk_docs htm e OS and Libraries Document Collection http
171. e List of ELF files to download If an SVF file is specified it is used hw bitstream file none The bitstream file for the system If an SVF file is specified it is used jprog true false false Clear the existing FPGA configuration This option should not be specified if performing runtime configuration opt genace options file none GenACE options are read from the options file target target type ppc hw mdm ppc hw Target to use in the system for downloading ELF or Data file Target types are e ppc hw to connect to a PowerPC 405 and 440 processor system e mdm to connects to a MicroBlaze processor system This assumes the presence of mdm in the system Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 207 7 XILINX The Genace tcl Script The options can be specified in an options file and passed to the GenACE script The options syntax is described in the following table Table 12 2 Genace File Options Options Default Description Some Text none The line starting with is treated as a comment ace ACE file none The output ACE file The file prefix should not match any input file bitstream elf data files prefix board board type none This identifies the JTAG chain on the board Devices user supported board list IR length Debug device and so on The options are given with resp
172. e These instructions are natively decoded and executed by MicroBlaze when the FPU is enabled in hardware The compiler automatically defines the C pre processor definition HAVE HW FPU when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the use of the hardware floating point unit option in MicroBlaze A link to the document is provided in the Additional Resources page 109 msoft float This option tells the compiler to use software emulation for floating point arithmetic This option is the default www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX mxl float convert This option turns on the usage of single precision floating point conversion instructions int and 1t in the compiler These instructions are natively decoded and executed by MicroBlaze when the FPU is enabled in hardware and these optional instructions are enabled Refer to the MicroBlaze Processor Reference Guide for more details about the use of the hardware floating point unit option in MicroBlaze A link to the document is provided in the Additional Resources page 109 mxl float sqrt This option turns on the usage of single precision floating point square root instructions sqrt in the compiler These instructio
173. e amp sys intc XPAR XPS INTC 0 XPS TIMER 0 INTERRUPT INTR Initialize the timer counter so that it s ready to use specify the device ID that is generated in xparameters h El Status XTmrCtr Initialize amp sys tmrctr XPAR XPS TIMER 0 DEVICE ID if Status XST SUCCESS LE return XST FAILURI Enable the interrupt of the timer counter so interrupts will occur and use auto reload mode such that the timer counter will reload itself automatically and continue repeatedly without this option it would expire once only T XTmrCtr SetOptions amp sys tmrctr 0 XTC INT MODE OPTION XTC AUTO RELOAD OPTION Set a reset value for the timer counter such that it will expire earlier than letting it roll over from 0 the reset value is loaded 252 www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software APIs 7 XILINX into the timer counter when it is started XTmrCtr SetResetValue amp sys tmrctr 0 OxDEADBEEF Start the timer counter such that it s incrementing by default then wait for it to timeout a number of times ef XTmrCtr Start amp sys tmrctr 0 Initialize the Standalone software platform exception system XExc Init Register the interrupt controller handler with the Standalone software platform s exception table zJ XExc RegisterHandler XEXC ID NON CRITICAL INT XExcep
174. e is source sink orall This API returns a list of handles to ports based on the port type where e source is a list of ports that are driving the given signal e sinkisa list of ports that are being driven by the given signal allisa list of all ports connected to the given signal xget hw ioif handle handle ioif name Description Arguments Returns the handle to an I O interface associated with the handle handle is the handle to an MPD or a merged IP instance Note If an original IP instance handle is provided this API returns a NULL lt ioif_name gt is the name of the I O interface whose handle is required If lt ioif_name gt is specified as an asterisk the API returns a list of I O interface handles To access an individual I O interface handle you can iterate over the list in Tcl xget hw ioif value handle ioif name Description Arguments Returns the value of the I O interface The value is specified in the MPD file and cannot be overwritten in MHS handle is the handle to an MPD or a merged IP instance ioif name is the name of the I O interface whose value is required xget hw ipinst handle mhs handle ipinst name Description Arguments Embedded System Tools Reference Manual UG111 EDK 11 3 1 Returns the handle of the specified IP instance mhs handle is the handle to either an original MHS or a merged MHS lt ipinst_name gt is the
175. e Guide available in your XILINX EDK doc usenglish directory Refer to the following sections On Chip Peripheral Bus V2 0 with OPB Arbiter for differences in the OPB bus Processor Local Bus PLB V3 4 for differences in the PLB bus and Device Control Register Bus DCR V2 9 for differences in the DCR bus 72 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Getting and Installing the Platform Studio BFM Package IBM CoreComnect Toolkit The IBM CoreConnect Toolkit is a collection of three toolkits e OPB Toolkit e PLB Toolkit e DCR Toolkit Each toolkit includes a collection of HDL files that represents predefined systems including a bus bus masters bus slaves and bus monitors You can modify the predefined systems included in the toolkits manually to connect the hardware components you want to test This is a labor intensive process because you must describe all the connections to the bus and ensure there are no errors in setting up the test environment Refer to the CoreConnect Toolkit documentation for more information on how to verify your hardware module Platform Studio BFM Package The Platform Studio BFM package includes a set of CoreConnect BFMs the Bus Functional Compiler and CoreConnect documents tailored for use within Platform Studio The BFM package lets you specify bus connections from a high level description such as an MHS file By allowing the Platform Studio
176. e MicroBlaze local memory at system startup Data2MEM can populate the MicroBlaze memory with XMDStub Libgen generates a Data2MEM script file that can be used to populate the block RAM contents of a bitstream containing a MicroBlaze system It uses the executable specified in DEFAULT INIT For any program that must be downloaded on the board for debugging the program start address must be higher than 0x800 and the program must be linked with the startup code in crt1 o mb gcc can compile programs satisfying the above two conditions when it is run with the option x1 mode xmdstub Note For source level debugging programs should also be compiled with the g option While initially verifying the functional correctness of a C program it is advisable to not use any mb gcc optimization option such as 02 or 03 as mb gcc performs aggressive code motion optimizations which might make debugging difficult to follow Embedded System Tools Reference Manual www xilinx com 187 UG111 EDK 11 3 1 7 XILINX Connect Command Options MicroBlaze Simulator Target You can use mb gdb and XMD to debug programs on the cycle accurate simulator built in to XMD Usage connect mb sim memsize lt size gt MicroBlaze Simulator Option Table 9 17 MicroBlaze Simulator Option Option Description memsize size The width of the memory address bus allocated in the simulator Programs can access the memory range from 0 to 2517 1
177. e OPB Bus Functional Language is available in the OpbToolkit pdf document in the SXILINX_El DK third_party doc directory 80 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX PLB BFM Component Instantiation PLB Bus Functional Language Usage The following is a sample BFL file written for the PLB BFM Component Instantiation page 76 and PLB v4 6 BFM Component Instantiation page 78 which instantiate the PLB BFM or PLB v4 6 BFM components FILE sample bfl This test case initializes a PLB master Initialize my_ma Note The instance name for plb_master is duplicated in the ster path due to the wrapper level inserted by the tools set device path system my master my master master device type plb mas ter Configure as 64 bit master configure msize 01 Write and read 64 bit data using byte enable architecture mem update addr ffff8000 data 00112233 44556677 mem update addr ffff8008 data z8899aabb ccddeeff write addr ffff8000 size 0000 be 11111111 write addr ffff8008 size 0000 be 11111111 read addr ffff8000 size 0000 be 11111111 read addr ffff8008 size 0000 be 11111111 Write and read 32 bit data using byte enable architecture mem_update addr f ff write addr ffff8010 size 0000 be 11110000 write addr ffff8014 size 0000 be z00001111 read addr ffff8010 size 0000 be 11110000 read addr fff
178. e Processes e Command Line Option for the Format Revision Tool e The Version Management Wizard Overview When you open an older project with the current version of EDK the Format Revision Tool automatically performs format changes to an existing EDK project and makes that project compatible with the current version Backups of existing files such as Xilinx Microprocessor Project XMP Microprocessor Hardware Specification MHS and Microprocessor Software Specification MSS are performed before the format changes are applied These backup files are stored in the revup folder in the project directory Updates to IP and drivers if any are handled by the Version Management wizard which launches after the format revision tool runs The format revision tool does not modify the IPs used in the MHS design it only updates the syntax so the project can be opened with the new tools Embedded System Tools Reference Manual www xilinx com 225 UG111 EDK 11 3 1 XILINX Format Revision Tool Backup and Update Processes Format Revision Tool Backup and Update Processes The Format Revision tool creates a backup of your files and a file name extension that specifies the EDK release number For example EDK 10 1 files are saved witha 101 extension and then modified for EDK 11 x tools 11 3 Changes Tools are updated to reflect revision 11 3 e Updates GenACE A microblaze_v72 option was added to the cpu_version XMD deb
179. e command line option while invoking powerpc eabi gcc To prevent the default startup files being used add nostartfiles on final compile line Note that the compiler standard CRT files for C support such as ecrti oand crtbegin o are not provided with source code They are available in the installation to be used as is You might need to bring them in on your final link command if your code uses constructors and destructors Reducing the Startup Code Size for C Programs If your application has stringent requirements on code size for C programs you can eliminate all sources of overhead This section documents how to remove the overhead of invoking the C constructor or destructor code in a C program that does not need them You might be able to save approximately 500 bytes of code space by making these modifications 1 Follow the instructions for creating a custom copy of the startup files from the installation area as described in the preceding sections Specifically you need to copy over the particular version of xil crt s that suits your application For example if your application is being profiled copy xil pgcrt0 s from the installation area Modify the CRT file to remove the following lines Call init bl init and Invoke the language cleanup functions bl fini This avoids referencing the extra code that is usually pulled in for constructor and destructor handling and reducing code size 2 Either compile t
180. e following table Table 8 4 Tool Specific Options Passed to the Top Level GCC Compiler Option Tool Example Wp option Preprocessor mb gcc Wp D Wp MYDEFINE Signal the pre processor to define the symbol MYDEFINE with the D MYDEFINE option Wa option Assembler powerpc eabi gcc Wa m405 Signal the assembler to target the PowerPC405 processor with the m405 option W1 option Linker mb gcc W1 M Signal the linker to produce a map file with the M option help Use this option with any GNU compiler to get more information about the available options You can also consult the GCC manual A link to the manual is supplied in the Additional Resources on page 109 B directory Add directory to the C run time library search paths L directory Add directory to library search path I directory Add directory to header search path 1 library Search library for undefined symbols Note The compiler prefixes lib to the library name indicated in this command line switch Embedded System Tools Reference Manual www xilinx com 117 UG111 EDK 11 3 1 XILINX Common Compiler Usage and Options Library Search Options 1 libraryname By default the compiler searches only the standard libraries such as libc libm and libxil You can also create your own libraries You can specify the name of the library and where the compiler can find the definition of these functions
181. e non exclusive interfaces Further non exclusive interfaces have the same bus interface standard Non Exclusive and Exclusive Bus Interfaces Signal Naming Conventions Signal names must adhere to the conventions specified in Conventions for Defining HDL Peripherals on page 34 e For non exclusive bus interfaces bus identifiers need not be specified e For exclusive bus interfaces identifiers must be specified only when the peripheral has more than one bus interface of the same bus standard and type Invoking the PsfUtility With Buses Specified in the Command Line You can specify buses on the command line when the bus signals do not have bus identifier prefixes The command line for invoking the PsfUtility is as follows psfutil hdl2mpd hdlfile lang vhdl ver top top entity bus busstd bustype o mpdfile 32 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility XILINX Exclusive and Non exclusive Bus Interface Command Line Examples For an example of a non exclusive bus interface to create an MPD specification for a peripheral with a PLB slave interface and a PLB Master Slave interface such as gemac the command is psfutil hdl2mpd gemac prj lang vhdl top gemac bus plb s bus plb ms o gemac mpd For an example of an exclusive bus identifier to create an MPD specification for a peripheral with a PLB slave interfa
182. e or not Refer to the MicroBlaze Processor Reference Guide for more details about the usage of the hardware divide option in MicroBlaze A link to the document is provided in the Additional Resources section of this chapter mxl soft div This option tells the compiler that there is no hardware divide unit on the target MicroBlaze hardware This option is the default The compiler replaces all 32 bit divisions with a call to the corresponding software emulation routines divsi3 udivsi3 Embedded System Tools Reference Manual www xilinx com 127 UG111 EDK 11 3 1 7 XILINX 128 MicroBlaze Compiler Usage and Options mxl barrel shift The MicroBlaze processor can be configured to be built with a barrel shifter In order to use the barrel shift feature of the processor use the option mx1 barrel shift The default option assumes that no barrel shifter is present and the compiler uses add and multiply operations to shift the operands Enabling barrel shifts can speed up your application significantly especially while using a floating point library The compiler automatically defines the C pre processor definition HAVE HW BSHIFT when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether or not this feature is specified as available Refer to the MicroBlaze Processor Reference Guide for more details about the use of the barrel shifter option in MicroBlaze A link to the doc
183. e overwritten in MHS Arguments handle the handle to an MPD or a merged IP instance option name is the name of the option whose value is required xget hw parameter handle handle parameter name Description Returns the handle to an associated parameter Arguments handle is the handle to the MPD original IP instance or merged IP instance parameter name is the name of the associated parameter whose handle is required If parameter name is specified as an asterisk a list of parameter handles is returned To access an individual parameter handle you can iterate over the list in Tcl 262 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 EDK Hardware Tcl Commands XILINX xget_hw parameter value lt handle gt lt parameter_name gt Description Returns the value of the specified parameter Arguments handle is the handle to the MPD original IP instance or merged IP instance parameter name is the name of the associated parameter whose value is required xget hw parent handle handle Description Returns the handle to the parent of the specified handle The type of parent handle is determined by the specified handle type If the specified handle is a merged handle the parent obtained through this API will also be a merged handle Arguments lt handle gt is one of the following e PARAMETER the parent is the MPD IP instance or the merged IP instance
184. e204 ffff0700 55000000 fc000000 00000000 ffffe204 00000000 00000000 ffffe204 ffffe204 00000000 32a08800 31504400 82020922 41010611 fe0006f0 fd0009f0 00000003 00000003 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 173 XILINX Connect Command Options Example Connecting to PowerPC440 Processor Target To connect to the PowerPC 440 processor target use the connect ppc hw command XMD automatically detects the processor type and connects to the PowerPC 440 processor Use powerpc eabi gdb to debug software program remotely Refer to Chapter 10 GNU Debugger GDB for more information about connecting the GNU Debugger to XMD XMD connect ppc hw JTAG chain configuration Device ID Code IR Length Part Name 1 5059093 16 XCF32P 2 5059093 16 XCF32P 3 59608093 8 xc95144x1 4 0a001093 8 System_ACE 5 032c6093 10 XC5VFX70T_U PowerPC440 Processor Configuration Versin arretea Gee ar ee eee aca wa dus 0x7ff21910 USE TD ica a rea 0x00 00000 No of PC Breakpoints 4 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 User Defined Address Map to access Special PowerPC Features using XMD I Cache Data 0x70000000 0x70007fff I Cach TAG n 0x70008000 0x7000ffff D Cache Data 0x78000000 0x78007fff D Cache TAG 0x78008000 0x7800ffff DER raa nas e ie 0x78020000 0x78020fff TUB resina a eh Rc gn
185. ead addr ffff01 16 bit data using 100 be 11000000 da 100 be 11000000 da 102 be 00110000 da read addr ffff01 write addr ffff01 read addr ffff01 write addr ffff01 02 be 00110000 da 04 be 00001100 da 04 be 00001100 da 06 be 00000011 da 06 be 00000011 da 8 bit data using byte enable architecture 00 be 10000000 da 00 be 10000000 da 01 be 01000000 da 01 be 01000000 da 02 be 00100000 da 02 be 00100000 da 03 be 00010000 da 03 be 00010000 da 04 be 00001000 da 04 be 00001000 da 05 be 00000100 da 05 be 00000100 da 06 be 00000010 da 06 be 00000010 da 07 be 00000001 da 07 be 00000001 da shifted by 0 s ta 00112233 ta 44556677 ta 00000033 ta 00000000 ta 00040004 ta 00040004 ta 00400040 ta 00400040 ta 04000400 ta 04000400 ta 40004000 ta 40004000 ta 01010101 ta 01010101 ta 02020202 ta 02020202 ta 03030303 ta 03030303 ta 04040404 ta 04040404 ta 05050505 ta 05050505 ta 06060606 ta 06060606 ta 07070707 ta 07070707 ta 08080808 ta 08080808 byte enable architecture The CoreConnect BFM devices differ in certain bus widths In this example the opb_device is a 64 bit device so the byte enable signals are shifted accordingly to match the address alignment Also the data mirroring required by the CoreConnect bus specifications are performed on the data field The adaptation layer translates this into a 32 bit bus width More information about th
186. ebugconfig Debug Configuration for Target 0 Step M rt rerea ERU RE Interrupt Enabled Memory Data Width Matching Disabled Configuring Memory Access XMD supports handling different memory data width accesses The supported data widths are word 32 bits half word 16 bits and Byte 8 bits By default XMD uses appropriate data width accesses when performing memory read and write operations You can use the debugconfig command for configuring XMD to match the data width of the memory operation This is usually necessary for accessing flash devices of different data widths XMD debugconfig Debug Configuration for Target 0 Step Moderar EUR Ss Interrupt Disabled Memory Data Width Matching Enabled XMD debugconfig memory datawidth matching disable XMD debugconfig Debug Configuration for Target 0 Step Mode cine ecc Interrupt Disabled Memory Data Width Matching Disabled 190 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Configuring Reset for Multiprocessing Systems By default XMD performs a system reset upon download of a program to a processor This behavior ensures a clean processor state before running the program However in multiprocessing systems downloading and running programs to the various processors happens in sequence Depending upon the system architecture a system reset performed during download of a progra
187. ect to the System ACE controller The script contains the options for some pre defined boards Board type options are e user for user specific board You must also specify the configdevice and debugdevice option in the OPT file Refer to the genace opt file for details e Fora list of supported board types refer to Supported Target Boards in Genace tcl Script on page 210 configdevice none Configuration parameters for the device on the JTAG only for user board type chain e devicenr Device position on the JTAG chain e idcode ID code e irlength Instruction Register IR length e partname Name of the device The device position is relative to the System ACE device and these JTAG devices must be specified in the order in which they are connected in the JTAG chain on the board Note This option is not available on the command line Use in OPT file only data data file load address none List of data binary file and its load address The load address can be in decimal or hex format 0x prefix needed If an SVF file is specified it is used 208 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 12 System ACE File Generator GenACE XILINX Table 12 2 Genace File Options Cont d Options Default Description debugdevice XMD debug device MB v7 The device containing either PowerPC 405 or 440 options cpu version lt version gt MDM v1 proc
188. ecute flow commands e Archive your project XPS batch provides the ability to query the EDK design database Tcl commands are available for this purpose In batch mode for XPS you can specify a Tcl script by using the scr option You can also provide an existing XMP file as input to XPS Creating a New Empty Project To create a new project with no components use the command xload new lt basename gt xmp XPS creates a project with an empty Microprocessor Hardware Specification MHS file and also creates the corresponding MSS file All of the files have same base name as the XMP file If XPS finds an existing project in the directory with same base name then the XMP file is overwritten However if an MHS or MSS file with same name is found then they are read in as part of the new project Creating a New Project With an Existing MHS 62 To create a new project use the command xload mhs lt basename gt mhs XPS reads in the MHS file and creates the new project The project name is the same as the MHS base name All of the files generated have the same name as MHS After reading in the MHS file XPS also assigns various default drivers to each of the peripheral instances if a driver is known and available to XPS www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 4 Command Line no window Mode XILINX Opening an Existing Project If you already have an XMP project file you can load that fi
189. ed for an IP instance Note The MPD tag name that specifies the Tcl procedure name indicates the category to which the Tcl procedure belongs Each of the following tags is a name value pair in the MPD file where the value specifies the Tcl procedure associated with that tag You must ensure that such a Tcl procedure exists in the Tcl file for that IP Tool specific Tcl calls You can specify calls specific to either Platgen or Simgen Order of Execution for Tcl Procedures in the MPD The Tcl procedures specified in the MPD are executed in the following order during hardware platform generation CON Dor ON IPLI IPLI IPLE SYS SYS SYS SYS EVEL UPDATE VALUE PROC on parameters EVEL DRC PROC on parameters VEL DRC PRCC on the IP specified on options EVEL UPDATE VALUE PROC on parameters EVEL UPDATE PROC on the IP specified on options EVEL DRC PROC on parameters ports EVEL_DRC_PROC on the IP specified on options FORMAT PROC on parameters Helper core Tcl Procecdures Embedded System Tools Reference Manual www xilinx com 285 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface UPDATE Procedure for a Parameter Before System Level Analysis You can use the parameter subproperty IPLEVEL UPDATE VALUE PROC to specify the Tcl procedure that computes the parameter value based on other parameters on the same IP The input h
190. em Such customization is not possible using standard off the shelf microprocessor or controller chips Hardware platform is a term that describes the flexible embedded processing subsystem you are creating with Xilinx technology for your application needs www xilinx com 295 7 XILINX Appendix D Glossary HDL Hardware Description Language Hierarchical View This is the default view for both the IP Catalog and System Assembly panel grouped by IP instance The IP instance ordering is based on classification from top to bottom processor bus bus bridge peripheral and general IP IP instances of the same classification are ordered alphabetically by instance name When grouped by IP it is easier to identify all data relevant to an IP instance This is especially useful when you add IP instances to your hardware platform IBA Integrated Bus Analyzer IDE Integrated Design Environment ILA Integrated Logic Analyzer ILMB Instruction side Local Memory Bus See also LMB IOPB Instruction side On chip Peripheral Bus See also OPB IPIC Intellectual Property Interconnect IPIF Intellectual Property Interface ISA Instruction Set Architecture The ISA describes how aspects of the processor including the instruction set registers interrupts exceptions and addresses are visible to the programmer ISC Interrupt Source Controller ISE File Xilinx ISE Project Navigator project file 296 www xilinx com Embedded System Tools
191. en to generate structural simulation models Timing Models To create a timing simulation model as displayed in Figure 6 4 page 90 Simgen requires an MHS file as input and an associated implemented netlist file From this netlist file Simgen creates an HDL file that models the design and a Standard Data Format SDF file with the appropriate timing information Optionally Simgen can generate a compile script for a specified vendor simulator If specified Simgen can generate HDL files with data to initialize block RAMs associated with any processor that exists in the design This data is obtained from an existing ELF file Embedded System Tools Reference Manual www xilinx com 89 UG111 EDK 11 3 1 7 XILINX Simulation Models C ELF ON UG111_04_101705 Figure 6 4 Timing Simulation Model Generation Single and Mixed Language Models Simgen allows the use of mixed language components in behavioral files for simulation By default Simgen takes the native language in which each component is written Individual components cannot be mixed language To use this feature a mixed language simulator is required Xilinx IP components are written in VHDL If a mixed language simulator is not available Simgen can generate single language models by translating the HDL files that are not in the HDL language The resulting translated HDL files are structural files Structural and Timing simulation models are always single language
192. enerates directories and files in the YOUR_PROJECT directory For every processor instance in the MSS file Libgen generates a directory with the name of the processor instance Within each processor instance directory Libgen generates the following directories and files which are described in the following subsections e include Directory e lib Directory e libsrc Directory e code Directory include Directory The include directory contains C header files needed by drivers The include file xparameters h is also created through Libgen in this directory This file defines base addresses of the peripherals in the system defines needed by drivers OSs libraries and user programs as well as function prototypes The Microprocessor Driver Definition MDD file for each driver specifies the definitions that must be customized for each peripheral that uses the driver Refer to the Microprocessor Driver Definition MDD chapter in the Platform Specification Format Reference Manual for more information The Microprocessor Library Definition MLD file for each OS and library specifies the definitions that you must customize Refer to the Microprocessor Library Definition MLD chapter in the Platform Specification Format Reference Manual for more information A link to the Platform Specification Format Reference Manual is supplied in the Additional Resources page 100 lib Directory The 1ib directory contains lib
193. er Defined Address Map to access Special PowerPC Features using XMD I Cache Data 0x70000000 0x70003fff I Cache TAG 0x70004000 0x70007fff D Cache Data 0x78000000 0x78003fff D Cache TAG 0x78004000 0x78007fff DB s Bice Se ri xS 0xab000000 Oxab000fff PUB A eee 0x70004000 0x70007fff XMD stp ffffe21c XMD stp ffffe220 XMD bps OxFFFFE218 Setting breakpoint at Oxffffe218 XMD con Processor started Type stop to stop processor RUNNING 8 Processor stopped at PC Oxffffe218 XMDS XMD mrd 0xab000060 8 AB000060 00000000 AB000064 00000000 AB000068 FF000000 DCR register ISARC AB00006c 81000000 DCR register ISCNTL AB000070 00000000 AB000074 00000000 AB000078 FE000000 DCR register DSARC AB00007c 81000000 DCR register DSCNTL XMDS Embedded System Tools Reference Manual www xilinx com 175 UG111 EDK 11 3 1 XILINX 176 Connect Command Options Example Showing Special JTAG Chain Setup for Non Xilinx Devices This example demonstrates the use of the configdevice option to specify the JTAG chain on the board in the event that XMD is unable to detect the JTAG chain automatically Automatic detection in XMD can fail for non Xilinx devices on the board for which the JTAG IRLengths are not known The JTAG Boundary Scan IRLength information is usually available in Boundary Scan Description Language BSDL files provided by device
194. er Slave OPB Ports on page 46 Slave OPB ports must follow the naming conventions shown in the table below Table 2 10 Slave OPB Port Naming Conventions Sin A meaningful name or acronym for the slave output lt S n gt must not contain the string OPB upper lower or mixed case to ensure that slave outputs are not confused with bus outputs nOPB A meaningful name or acronym for the slave input The last three characters of nOPB must contain the string OPB upper lower or mixed case BI A Bus Identifier Optional for peripherals with a single OPB port and required for peripherals with multiple OPB ports of any type BI must not contain the string OPB upper lower or mixed case For peripherals with multiple OPB ports of any type or mix of types the BI strings must be unique for each bus interface Note If Bl is present lt Sin gt is optional OPB Slave Outputs For interconnection to the OPB all slaves must provide the following outputs BI Sln DBus out std logic vector 0 to C_ lt BI gt OPB_DWIDTH 1 BI Sln errAck out std logic BI Sln retry out std logic lt BI gt lt S1n gt _toutSup out std_logic lt BI gt lt S1n gt _xferAck out std_logic Examples Tmr_xferAck out std_logic Uart xferAck out std logic Intc xferAck out std logic OPB Slave Inputs For interconnection to the OPB all slaves must provide the following inpu
195. erlaps the pin of a symbol the two nets are not connected Courier Italic in angle brackets Variable in a syntax statement for which you must supply values within a Tcl file ngdbuild design name An optional entry or parameter However in ngdbuild option name Square brackets bus specifications such as bus 7 0 they design name are required A list of items f hich h Braces T ist of items from which you must choose imper ton GEE one or more Vertical bar Separates items in a list of choices lowpwr on off Boo ois ees IOB 1 N QOUT Vertical ellipsis Repetitive material that has been omitted i aude IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block name loci loc2 locn Online Document The following conventions are used in this document Blue text Convention Meaning or Use in the current document Cross reference link to a location Example Refer to the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com Preface About This Guide XILINX 6 www xilinx com Embedded System Tools Reference Manual UG1
196. es 56 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Load Path Load Path Table 3 1 Platgen Syntax Options Cont d Option Command Description Output od output dir Specifies the output directory path dS Default The current directory Part name p partname Uses the specified part type to implement the design Instance name ti lt instname gt Specifies the top level instance name Top level tm lt top_module gt Specifies the top level module name module Top level toplevel yes no Specifies if the input design represents a whole design or a level of hierarchy Default yes Refer to the following figure for a depiction of the peripheral directory structure To specify additional directories use one of the following options e Use the current directory from which Platgen was launched e Set the EDK tool lp option Platgen uses a search priority mechanism to locate peripherals in the following order 1 The pcores directory in the project directory 2 The lt Library_Path gt lt Library_Name gt pcores as specified by the Ip option 3 The xiLINX EDK hw Library Name pcores Note Directory path names are case sensitive in Linux Ensure that you are using pcore and not Ip library path Pcore Library Name Figure 3 1 Peripheral Directory Structure boards sw_services X10066
197. es defined in the MSS file have an MDD or MLD file and a Tcl file associated with them The Tcl file contains procedures for generating the right configuration of drivers and libraries based on input in the MSS file The Tcl files that are used during the software platform generation are present in the individual drivers directory along with the MDD files For Xilinx supplied cores the files are located in the EDK install area gt sw XilinxProcessorlPLib drivers lt driver_name gt data directory Tcl Procedure Calls from Libgen When the Libgen tool runs it calls the following Tcl procedures for each of the drivers OSs processors and libraries in the MSS file in the following order e prc The name of the DRC procedure is given as an OPTION in the MDD or MLD file This is the procedure that Libgen invokes for a driver OS processor or library For example for a driver the MDD and Tcl have the following constructs defining the DRC procedure MDD MLD OPTION DRC mydrc Tcl procedure mydrc driver handle e generate During the generate Tcl procedure Libgen calls for all drivers OSs processors and libraries present in the MSS file after the relevant driver OS processor and library files are copied and their corresponding DRC procedures have been run Each driver OS processor and library defines this procedure in its Tcl file The procedure is called from Libgen with the corresponding driver OS processor or library
198. es directory in the current working directory in which you run Libgen OS Search for OSs inside the bsp directory in the current working directory from which you run Libgen Search the repositories under the library path directory specified using the 1p option a Drivers Search one of the following Library Path N Library Name Vdrivers or Library Path N Library Name Npcores Libraries Search one of the following as specified by the 1p option Here Library Path isthe directory argument to 1p option and Library Name is a subdirectory under Library Path Library Path N Library Name Nsw services OSs Search the following as specified by the 1p option In this case Library Path is the directory argument to the 1p option and OS Name gt is a subdirectory under Library Path Library Path N OS Name Mbsp Search the EDK install area a Drivers Search the following as specified by the 1p option SXILINX_EDK sw lt Library_Name gt drivers Libraries Search XILINX_EDK sw lt Library_Name gt sw_services OSs Search XILINX_EDK sw lt Library_Name gt bsp lt Library Name gt pcores lt my_driver gt sw_services lt my_library gt X10134 Figure 7 2 Directory Structure of Drivers OSs and Libraries Embedded System Tools Reference Manual www xilinx com 103 UG111 EDK 11 3 1 7 XILINX Output Files Output Files Libgen g
199. es to be enabled XEXC CRITICAL specifies external critical input interrupts XEXC NON CRITICAL specifies external non critical input interrupts belong to the category void XExc mDisableExceptions DisableMask Description Parameters This function disables the specified set of exceptions or categories on the PowerPC processor DisableMaskis the set of exception categories to be disabled XEXC CRITICAL specifies the external critical input interrupts XEXC NON CRITICAL specifies the external non critical input interrupts 250 www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software APIs 7 XILINX PowerPC Processor Interrupt Setup Example The following program provides an example of how interrupts are initialized on either a PowerPC 405 or 440 processor when an interrupt controller is present The software example assumes these conditions e There is an xps_timer peripheral in the system named xps timer 0 e The interrupt signal from the timer is connected to an xps_intc interrupt controller named xps intc 0 e The interrupt signal from the interrupt controller is connected to the PowerPC processor external non critical interrupt input include include include include xexception_1 h xparameters h xtmrctr h xainto a XIntc sys intc XTmrCtr sys tmrctr void my timer handler XUint32 ControlStatusReg Read the new Co
200. ess If the value compares to data stop the processor e Address and Data can be specified in hex 0x format or binary 0b format e Don t care values are specified using X e Addresses can be of contiguous range only e Default value of data is OxXXXXXXXX Thatis it matches any value Note For the PowerPC processor only absolute values are supported verbose verbose level verbose Toggles verbose mode on and off In verbose mode XMD prints debug information Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 159 XILINX Table 9 2 XMD User Commands Cont d XMD User Commands xload xload XMP lt XMP_filename gt command options Example Usage xload xmp system xmp Description Loads XMP system files XMD reads the XMP files to gather instruction and data memory address maps of the processor This information is used to verify the program and data downloaded to processor memory 160 Special Purpose Register Names MicroBlaze Special Purpose Register Names The following special register names are valid for MicroBlaze processors pc msr ear fer btr pvr0 pvr2 pvr3 pvr4 pvr6 pvr7 pvr8 pvr10 pvr11 edr esr zpr pvri zpr pvr5 zpr pvr9 pid For additional information descriptions and usage of MicroBlaze special register names refer to the Special Purpose Registers section of the MicroBlaze Architecture cha
201. essor or MicroBlaze to debug or configure in the mdm_version lt version gt JTAG chain Specify the XMD debug device options suchas e position on the chain devicenr e number of processors cpunr e processor options such as OCM Cache addresses For a MicroBlaze system the script assumes the MicroBlaze v7 processor and MDM v1 versions The additional options for MicroBlaze versions are cpu version microblaze v5 microblaze v6 microblaze v7 microblaze v72 The additional MDM versions are mdm version mdm v1 mdm v2 mdm v3 elf list of Elf or SVF files none List of ELF files to download If an SVF file is specified itis used hw bitstream file none The bitstream file for the system If an SVF file is specified it is used jprog false Clear the existing FPGA configuration This option should not be specified if performing runtime configuration start address Start Address Specify the address at which to start processor processor run address gt of the last ELF execution This is useful when a data file is being file if ELF file loaded and processor should execute from load is specified address else none target lt target type gt ppc_hw Target to use in the system for downloading ELF Data file Target types are e ppc_hw to connect to a PowerPC 405 or 440 processor system e mdm to connect to a MicroBlaze system This assumes the presence of mdm in the sys
202. et port value is the value to be set Example Set the value of a port to my connection xset hw port value port handle my connection Embedded System Tools Reference Manual www xilinx com 273 UG111 EDK 11 3 1 EZ XILINX Appendix C EDK Tcl Interface xset hw busif value busif handle busif value Description Sets the value of the bus interface to the given value Arguments lt busif_handle gt is the handle to the bus interface whose value must be set lt busif_value gt is the value to be set Example Set the value of a bus interface to my_bus xset_hw_busif_value busif handle my bus Software Tcl Commands This section provides an overview of the terms used in EDK software Tcl APIs and lists the Tcl software APIs that are available Software API Terminology Overview The following table contains brief descriptions of the terms used in the software Tcl APIs Table C 3 Software API Terms Original MSS The handle that points to the MSS information only This handle does not contain any information about the MDD or MLD information If a driver or library parameter has not been overwritten in the MSS this handle will not contain that parameter Merged MSS The handle that points to the information containing both the MSS and MDD or MLD This data structure object is formed by merging the MDD or MLD information with the MSS information Original Processor Instance The processo
203. et Optionally provide target specific reset types such as the signals mentioned in Table 9 22 on page 194 xrun lt target id Runs program from the program start address xstate target id Returns the processor target state running or stopped xstep target id Single steps one MicroBlaze instruction If the PC is at an IMM instruction the next instruction also runs During a single step interrupts are disabled by keeping the BIP flag set Use xcontinue with breakpoints to enable interrupts while debugging xstop target id Stops the program execution xwatch target id r w address lt data value Sets read write watchpoints at a given address and optionally check for data value gt lf data value is not specified watchpoints match any value The address and value can be specified in hex or binary format a This command is for Simulator targets only Table 9 22 XMD MicroBlaze Hardware Target Signals Signal Name Value Non maskable Break 0x10 Similar to the Break signal but works even while the BIP flag is already set Refer the MicroBlaze Processor Reference Guide for more information about the BIP flag A link to the document is supplied in the Additional Resources page 152 Description Processor Break 0x20 Raises the Brk signal on MicroBlaze using the JTAG UART Ext Brk signal It sets the Break in Progress BIP flag
204. f dut conf Clock generator for sys clk initial begin sys clk 1 b0 sys_clk_PHASE forever sys_clk_PERIOD 2 sys_clk sys_clk end Reset Generator for sys_reset initial begin sys reset 1 b0 dsys clk LENGTH sys reset sys reset end START USER CODE Do not remove this line User Put your stimulus here Code in this section will be not be overwritten END USER CODE Do not remove this line endmodule You can add your own Verilog code between the lines tagged BEGIN USER CODE and END USER CODE The code between these lines is maintained if simulation files are created again Any code outside these lines will be lost if a new test bench is created Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 97 XILINX Simulating Your Design Simulating Your Design Restrictions 98 When simulating your design there are some special considerations to keep in mind such as the global reset and tristate nets Xilinx ISE tools provide detailed information on how to simulate your VHDL or Verilog design Refer to the Simulating Your Design chapter in the ISE Synthesis and Simulation Design Guide for more information Additional Resources page 85 contains a link to the document website Helper scripts generated at the test harness or testbench level are simulator setup scripts When run the setup script perfor
205. f the instruction as mytargetlabel PC Embedded System Tools Reference Manual www xilinx com 131 UG111 EDK 11 3 1 XILINX 132 MicroBlaze Compiler Usage and Options If this immediate value is greater than 16 bits the mb as assembler automatically inserts an imminstruction If the value of mnytargetlabelis not known at the time of compilation the mb as assembler always inserts an imm instruction Use the relax option of the linker remove any unnecessary imm instructions Similarly if an instruction needs a large constant as an operand the assembly language programmer should use the operand as is without using an imm instruction For example the following code adds the constant 200 000 to the contents of register r3 and stores the results in register r4 addi r4 r3 200000 The mb as assembler recognizes that this operand needs an imm instruction and inserts one automatically In addition to the standard MicroBlaze instruction set the mb as assembler also supports some pseudo op codes to ease the task of assembly programming The following table lists the supported pseudo opcodes Table 8 6 Pseudo Opcodes Supported by the GNU Assembler Pseudo Opcodes Explanation nop No operation Replaced by instruction or RO RO RO la Rd Ra Imm Replaced by instruction addik Rd Ra imm Rd Ra Imm not Rd Ra Replace by instruction xori Rd Ra 1 neg Rd Ra Replace by instruction rsub Rd Ra
206. file headers Otherwise it is treated as Position Independent Code PIC code and downloaded at the specified address and Register R20 is set to the start address according to the PIC code semantics XMD does not perform bounds checking with the exception of preventing writes into the XMDSTUB area address 0x0 to 0x800 xfpga f lt bitstream gt cable lt cable_options gt configdevice configuration options debugdevice device name Loads the FPGA device bitstream and optionally the cable configuration and debug device options xload sysfile lt XMP System File Loads the XMP file xrut Session ID Authenticates the XMD session when communicating over XMD sockets interface The session ID is first assigned and subsequent calls return the session ID xtargets listSysID xtargets system lt system_ID gt print listTgtID xtargets target lt target_ID gt print prop Provides system and target information in the current XMD session e listSysID returns a list of existing systems e system lt system_ID gt provides information on the specified system print prints the different targets in the system listTgtID returns a list of existing targets in the system e target lt target_ID gt provides information on the specified target The options print prints the target information prop returns the target properties 192 Embe
207. from the lt DCR start address gt for debugging from XMD and GDB devicenr Position in the JTAG chain of the Virtex lt PowerPC device position gt device containing the PowerPC processor The device position number starts from 1 dtagstartadr Start address for reading or writing the data lt D Cache start address gt cache tags fputype sp dp XMD does not automatically look for a Floating Point Unit FPU in the PowerPC processor system To force XMD to detect a FPU specify this option with the FPU type in the system The options are sp Single Precision dp Double Precision icachestartadr Start address for reading or writing the lt I Cache start address gt instruction cache contents isocmdcrstartadr DCR address corresponding to the ISOCM lt ISOCM in Bytes DCR address gt interface specified using the C_ISOCM_DCR_BASEADDR parameter on PowerPC 405 processors isocmstartadr Start address for the Instruction Side On lt ISOCM start address gt Chip Memory ISOCM Only for PowerPC 405 processor isocmsize Size of the ISBRAM memory connected to lt ISOCM size in Bytes gt the ISOCM interface Only for PowerPC 405 processor www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Table 9 10 PowerPC Processor Options Cont d Option Description itagstartadr Start address for reading or writ
208. gdb and XMD through the GDB Remote TCP protocol XMD supports two remote targets Instruction Set Simulator ISS PowerPC 440 Hardware and Cycle Accurate PowerPC To connect to a PowerPC440 target 1 Start XMD and connect to the board using the connect ppc command as described in Chapter 9 Xilinx Microprocessor Debugger XMD From GDB select Run gt Connect to target In the GDB target selection dialog box specify the following Target Remote TCP Hostname localhost Port 1234 Click OK The debugger powerpc eabi gdb attempts to make a connection to XMD If successful a message is printed in the shell window where XMD started Select View gt Console to open the console window On the console type set arch powerpc 440 to set the architecture to a PowerPC 440 processor At this point the debugger is connected to XMD in PowerPC440 mode and controls the debugging The user interface can be used to debug the program and read and write memory and registers Console Mode To start powerpc eabi gdb in the console mode type the following xilinx gt powerpc eabi gdb nw executable elf In the console mode type the following two commands to connect to the board through XMD gdb target remote localhost 1234 gdb load The following text displays Loading section text Loading section rodata Loading section data Loading section fixup Loading section got2 Loading section s
209. gions to zero Set up registers Refer to Table 8 12 page 146 for details Initialize the timer base register to zero Optionally enable the floating point unit bit in the MSR Invoke the C language and constructor initialization function _init Invoke main Invoke C language destructors ini A dE O9 I2 Transfer control to exi t Start up File Descriptions xil crt0 o This is the default initialization file used for programs that are to be executed in standalone mode with no other special requirements This performs all the common actions described above xil pgcrt0 o This initialization file is used when the application is to be profiled in a software intrusive manner In addition to all the common CRT actions described it also invokes the profile init routine before invoking main This initializes the software profiling library before your code executes Similarly upon exit from main it invokes the profile clean routine which cleans up the profiling library xil sim crt0 o This initialization file is used when the application is compiled with the mno clearbss switch It performs all the common CRT setup actions except that it does not clear the bss section to zero xil sim pgcrt0 o This initialization file is used when the application is compiled with the mno clearbss switch It performs all the common CRT setup actions except that it does not clear the bss section to zero It also invokes the
210. gt bmn is used by the implementation tools when EDK is the top level system e The lt system gt _stub is used by the implementation when EDK is a sub module of the top level system The EDK tools implementation tools flow using Data2MEM is as follows ngdbuild bm lt system gt bmm lt system gt ngc map par bitgen bd lt system gt elf Bitgen outputs system bd bmm which contains the physical location of block RAMs A block RAM Memory Map BMM file contains a syntactic description of how individual block RAMs constitute a contiguous logical data space The system bd bmm and system bit files are input to Data2MEM Data2MEM translates contiguous fragments of data into the proper initialization records for the Virtex series block RAMs Synthesis Netlist Cache An IP rebuild is triggered when one of the following changes occur e Instance name change e Parameter value change e Core version change e Core is specified with the MPD CORE STATE DEVELOPMENT option e Core license change Embedded System Tools Reference Manual www xilinx com 59 UG111 EDK 11 3 1 Chapter 3 Platform Generator Platgen 60 www xilinx com XILINX Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 4 Command Line no window Mode This chapter describes the XPS command line no window mode and includes the following sections Invoking XPS Command Line Mode
211. gt M_RNW ou lt BI gt M_size ou lt BI gt M_TAttribute ou lt BI gt M_type ou lt BI gt M_wrBurst ou lt BI gt M_wrDBus ou Examples IPLBM_request out Bridge_M_request out O20b M request out 6 Master Inputs ct ct vv ounouoouoodoocdcocZdocuuocu uu ct ct ct ct td_logic td_logic_vector 0 td_logic_vector 0 td_logic_vector 0 td_logic td_logic td_logic td_logic_vector 0 td_logic td_logic td_logic td_logic_vector 0 td_logic_vector 0 td_logic_vector 0 td_logic td_logic_vector 0 td_logic td_logic td_logic to to to to to to to to C_ lt BI MPLB gt _AWIDTH 1 C_ lt BI MPLB gt _AWIDTH 1 3 15 2 C BI MPLB C BI MPLB DWIDTH 8 1 DWIDTH 1 For interconnection to the PLBV4 6 masters must provide the following inputs lt BI gt MPLB_C1k lt BI gt MPLB_Rst lt BI gt PLB_MBusy lt BI gt PLB_MRdErr lt BI gt PLB_MWrErr lt BI gt PLB_MIRQ lt BI gt PLB_MWrBTerm lt BI gt PLB_MWrDAck lt BI gt PLB_MAddrAck lt BI gt PLB_MRdBTerm lt BI gt PLB_MRdDAck lt BI gt PLB_MRdDBus lt BI gt PLB_MRdWdAddr lt BI gt PLB_MRearbitrate lt BI gt PLB_MSSize lt BI gt PLB_MTimeout Examples IPLBO_PLB_MBusy Busl_PLB_MBusy in in in in in in in in in in in in in in in in std_logic_vector 0 to C_ lt BI MPLB gt _DWIDTH 1 std_logic std_logic std_logic std_logic std_logic std_logic std_logic std_logic
212. h Point to Point Connections 0 0 0c e eee eee 33 DRC Checks in PsfUtility ao yum E pe ed 34 HIDE So rce Errors ea eo eee ere bte P e ee e eU eio aue s 34 Bus Interface Checks ccc cc ee eee ren 34 Conventions for Defining HDL Peripherals 34 Naming Conventions for Bus Interfaces isses eee 35 Naming Conventions for VHDL Generics oooooocccococcocccnnrrrrra 36 Reserved Parameters o 38 Naming Conventions for Bus Interface Signals 2 0 6 6 eee 39 Global POTS e i arce de qud 40 Slave DER POESIE A vede ve eee Vete e he E dace P Regn 40 Slave ESEPOPSS auto ds UE teer dence hos A A ies 41 Master ESE Ports 5i ete bec ete dace cues p T V epe p reer quiae 42 Slave LMB Ports ti e eine tbe a eee adds 43 Master OPB Potts Eois eR EL een eee te dda HP CEP IE Poen Rege 44 Slave OPBAPORIS uote ti Tuve Meet ra Te a Le e cece 45 Master Slave OPB Potts od Pete d oe ce Rd aeta ce ds 46 Master PLBPORS ni ace e dern gd 47 PLB Master Outputs baee Iac da 48 PLB Master Inputs net Ad eta end es 48 Slave PEB POtts 5 id dice Vb e Pd edet Td a Ad esu c oae 49 PEB Slave OBtputs esie e a eee ient cds 49 PLB Slave Inputs iae decet id ded eee erede eren 50 Master PLBV4 6 ports esce e er ee Rh reete ew Rea heus 50 PLB v4 6 Master Outputs 1 esae aene o de 51 PEB v4 6 Master Inputs sequo Pep ebbe QU ERE He qur d bra reds 51 Slave PLBV46 ports dee e een een tete ote e
213. hat application and a processor instance on which that application runs By default XPS assumes that the ELF file related to a new software application is created at lt swapp_name gt bin lt swapp_name gt elf You can change the directory after the application has been created xadd swapp lt swapp_name gt proc inst Deleting a Software Application An existing software application can be deleted from project in the XPS batch using the xdel swapp command You must specify the name of the software application that you want to delete xdel swapp swapp name Adding a Program File to a Software Application You can add any program file C source or header files to an existing software application using the xadd swapp progfile command The name of the software application to which the file must be added and the location of the program file must be specified XPS automatically adds it as a source or header based on the extension of the file xadd swapp progfile swapp name filename Deleting a Program File from a Software Application You can delete any program file C source or header file associated with an existing software application using the xdel swapp progfile command The name of the software application and the program file location needs to be specified xdel swapp progfile swapp name filename Archiving Your Project Files To archive a project use the command xps archiver The xps archiver tool c
214. he edk install data xmd flashwriter directory to the sw services directory 4 Change the following line in the flashwriter tcl file copy 220 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 13 Flash Memory Programming set flashwriter_src sre to 7 XILINX file join xilinx edk data xmd flashwriter set flashwriter_src file join sw_services flashwriter src From this point when you use the Program Flash Memory dialog box in XPS or the Flash Programmer dialog box in SDK the flash programming tools use the script and the sources you copied into the sw services directory You can customize these as required If you prefer to not have the GUI overwrite the etc flash_params tcl file you must run the command xmd tcl flashwriter tcl on the command line to use only the values that you specify in the etc flash_params tcl file The following table lists the available parameters in the etc flash_params tcl file Table 13 3 Flash Programming Parameters Variable FLASH FILE Function A string containing the full path of the file to be programmed FLASH BASEADDR The base address of the flash memory bank FLASH PROG OFFSET The offset within the flash memory bank at which the programming should be done SCRATCH BASEADDR The base address of the scratch memory used during programming SCRATCH LEN The length of the scratch memory
215. he mcpu switch behaves differently for different versions as described below e Pr v3 00 a Uses 3 stage processor pipeline mode Does not inhibit exception causing instructions being moved into delay slots e v3 00 a and v4 00 a Uses 3 stage processor pipeline model Inhibits exception causing instructions from being moved into delay slots e v5 00 aand later Uses 5 stage processor pipeline model Does not inhibit exception causing instructions from being moved into delay slots 126 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX mno xl soft mul This option permits use of hardware multiply instructions for 32 bit multiplications The MicroBlaze processor has an option to turn the use of hardware multiplier resources on or off This option should be used when the hardware multiplier option is enabled on MicroBlaze Using the hardware multiplier can improve the performance of your application The compiler automatically defines the C pre processor definition HAVE HW MUL when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the usage of the multiplier option in MicroBlaze A link to the document is provided in the Additional Resources page 109 mxl multiply high MicroBlaze has an option to e
216. he C DEBUG ENABLED parameter from a MicroBlaze instance xdel hw ipinst parameter mb handle C DEBUG ENABLED 272 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Example Procedures 7 XILINX xdel hw subproperty prop handle lt subprop_name gt Description Deletes a specified subproperty from a property handle Arguments prop handle is a handle to a parameter port or bus interface subprop name is the name of the subproperty Example Delete SIGIS subproperty from a given port xdel hw subproperty port handle SIGIS xdel hw toplevel port mhs handle port name Description Deletes a top level port with the specified name Arguments mhs handle is the handle to the original MHS port name is the name of the port to be deleted Example Delete a top level port called sys_c1k_pin xdel hw toplevel port mhs handle sys clk pin Modify Commands xset hw parameter value busif handle busif value Description Sets the value of the parameter to the given value Arguments port handle is the handle to the port whose value must be set port value is the value to be set Example Set the value of a parameter to 2 xset hw parameter value param handle 2 xset hw port value port handle port value Description Sets the value of the port to the given value Arguments port handle is the handle to the port whose value must be s
217. he UNISIM library have zero delay Synchronous components have a unit delay to avoid race conditions The clock to out delay for these synchronous components is 100 ps SIMPRIM Library The SIMPRIM Library is used for timing simulation It includes all the Xilinx primitives library components used by Xilinx implementation tools Timing simulation models generated by Simgen instantiate SIMPRIM library components 86 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 6 Simulation Model Generator Simgen XILINX XilinxCoreLib Library The Xilinx CORE Generator software is a graphical Intellectual Property IP design tool for creating high level modules like FIR Filters FIFOs CAMs and other advanced IP You can customize and pre optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices such as block multipliers SRLs fast carry logic and on chip single or dual port RAM The CORE Generator software HDL library models are used for behavioral simulation You can select the appropriate HDL model to integrate into your HDL design The models do not use library components for global signals Xilinx EDK Library The EDK library is used for behavioral simulation It contains all the EDK IP components precompiled for ModelSim SE and PE or NcSim This library eliminates the need to recompile EDK components on a per project basis minimizing overall compile time The E
218. he arguments passed in and can return different return values To support this C compilers encode the type of the function to be invoked in the function name avoiding multiple definitions of a function with the same name Be careful about name mangling if you decide to follow a mixed compilation mode with some source files containing C code and some others containing C code or using GCC for compiling certain files and G for compiling others To prevent name mangling of a C symbol you can use the following construct in the symbol declaration ifdef _ cplusplus extern C fendif int foo int morefoo ifdef _ cplusplus fendif Make these declarations available in a header file and use them in all source files This causes the compiler to use the C dialect when compiling definitions or references to these symbols Note All the EDK drivers and libraries follow the conventions listed above in all the header files they provide You must include the necessary headers as documented in each driver and library when you compile with G This ensures that the compiler recognizes library symbols as belonging to C type When compiling with either variant of the compiler to force a file to a particular dialect use the x lang switch Refer to the GCC manual on the GNU website for more information on this switch A link to the document is provided in the Additional Resources on page 109 When using the GCC com
219. he debug session for a target using the debugconfig command You can configure the behavior of instruction stepping and memory access method of the debugger Usage debugconfig step mode disable interrupt enable interrupt memory datawidth matching disable enable reset on run system enable processor enable disable Table 9 18 Debug Config Options Option No Option Description Lists the current debug configuration for the current session step mode disable interrupt enable interrupt Configures how XMD handles Instruction Stepping e disable interrupt is the default mode The interrupts are disabled during Step e enable interrupt enables interrupts during Step If an interrupt occurs during Step the interrupt is handled by the registered interrupt handler of the program memory datawidth matching disable enable Configures how XMD handles Memory Read and Write By default the data width matching is set to enable All data width byte half and word accesses are handled using the appropriate data width access method This method is especially useful for memory controllers and flash memory where the datawidth access should be strictly followed When data width matching is set to di sable XMD uses the best possible method such as word access reset on run system enable processor enable disable Configures how XMD handles Reset on program executio
220. he driver must be in the src subdirectory under the driver name directory e The make file must have the targets include and libs e Each driver must also contain an MDD file and a Tcl file in the data subdirectory Open the existing EDK driver files to get an understanding of the required structure Refer to the Microprocessor Driver Definition MDD chapter in the Platform Specification Format Reference Manual for details on how to write an MDD and its corresponding Tcl file A link to the document is supplied in the Additional Resources page 100 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 7 Library Generator Libgen XILINX Libraries OS Block The MSS file includes a library block for each library The library block contains a reference to the library name LIBRARY_NAME parameter and the library version LIBRARY_VER There is no default value for these parameters Each library is associated with a processor instance specified using the PROCESSOR_INSTANCE parameter The library directory contains C source and header files and a make file for the library The MLD file for each library specifies all configurable options for the libraries and each MLD file has a corresponding Tcl file You can write your own libraries These libraries must be in a specific directory under YOUR PROJECT sw services Or library name sw services as shown in Figure 7 1 on page 102 e The
221. her This allows the compiler to use the correct set of libraries and prevent incompatibilities none This option tells the compiler to use software emulation for floating point arithmetic This option is the default Refer to the latest APU FPU user guide for detailed information on how to optimize use of the hardware floating point co processor A link to the guide is provided in the Additional Resources on page 109 mppcperflib Use PowerPC processor performance libraries for low level integer and floating emulation and some simple string routines These libraries are used in the place of the default emulation routines provided by GCC and simple string routines provided by Newlib The performance libraries show an average of three times increase in speed on applications that heavily use these routines The SourceForge project web page contains more information and detailed documentation A link to that page is provided in the Additional Resources section of this chapter Caution You cannot use the performance libraries in conjunction with the mfpu switch They are incompatible mno clearbss This option is useful for compiling programs used in simulation According to the C language standard uninitialized global variables are allocated in the bss section and are guaranteed to have the value 0 when the program starts execution Typically this is achieved by the C startup files running a loop to fill the bss section with
222. hese files into o files and place them in a directory of your choice or include them as a part of your application sources 3 Add the nostartfiles switch to the compiler Add the B directory switch if you have chosen to assemble the files in a particular folder 4 Compile your application 148 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Modifying Startup Files for Bootstrapping an Application If your application is going to be loaded from a bootloader you might not want to overwrite the processor reset vector of the bootloader with that of your application This re executes the bootloader on a processor reset instead of your application To achieve this your application must not bring in boot o as a startup file Unlike other compiler startup files boot o is not explicitly linked in by the compiler Instead the default linker scripts and the tools for generating the linker scripts specify boot o as a startup file You must remove the STARTUP directive in such linker scripts You must also modify the ENTRY directive to be start instead of _boot Compiler Libraries The powerpc eabi gcc compiler requires the GNU C standard library and the GNU math library Precompiled versions of these libraries are shipped with EDK These libraries are located in SXILINX EDK gnu powerpc eabi platform powerpc eabi lib Various subdirectories under this top level libr
223. icular instance of that IP Note that when this procedure is called system level parameters computed by Platgen for example C NUM MASTERS on a bus are already updated with the correct values MPD snippet PARAMETER C_PARAM1 5 SYSLEVEL_UPDATE_VALUE_PROC sysupdate_paraml Tcl snippet proc sysupdate_paraml param handle set retval somehow compute paraml return reetval Embedded System Tools Reference Manual www xilinx com 287 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface UPDATE Procedure for the IP Instance After System Level Analysis You can use the OPTION SYSLEVEL_UPDATE_PROC to perform certain actions associated with a specific IP This procedure is associated with the complete IP and not with a specific parameter so it cannot be used to update the value of a specific parameter For example you can use this procedure to copy certain files associated with the IP in a particular directory The input handle is a handle to an instance of the IP MPD Snippet OPTION SYSLEVEL_UPDATE_PROC syslevel_update_proc Tcl snippet Proc myip syslevel update proc ipinst handle do something return 0 DRC Procedure for a Parameter After System Level Analysis Use the tag SYSLEVEL_DRC_PROC to specify Tcl procedure that performs DRC on the complete IP based on how the IP has been used in the system Input is a handle to the parameter object of a particular
224. ile This file defines the configurable parameters for the driver OS or library Data Generation File Tcl This file uses the parameters configured in the MSS file for a driver OS or library to generate data Data generated includes but is not limited to generation of header files C files running DRCs for the driver OS or library and generating executables The Tcl file includes procedures that Libgen calls at various stages of its execution Various procedures in a Tcl file include DRC The name of DRC given in the MDD or MLD file generate A Libgen defined procedure that is called after files are copied gt post_generate A Libgen defined procedure that is called after generate has been called on all drivers OSs and libraries execs_generate A Libgen defined procedure that is called after the BSPs libraries and drivers have been generated Note The data generation Tcl file is not necessary for a driver OS or library Embedded System Tools Reference Manual www xilinx com 105 UG111 EDK 11 3 1 XILINX MSS Parameters For more information about the Tcl procedures and MDD MLD related parameters refer to the Microprocessor Driver Definition MDD and Microprocessor Library Definition MLD chapters in the Platform Specification Format Reference Manual A link to the document is supplied in the Additional Resources page 100 MSS Parameters Drivers 106 For a complete description of the
225. in this release Simgen infers the location of the EDK simulation libraries from the X switch Help h help Displays the usage menu and then quits Options File f filename Reads command line arguments and options from file HDL Language lang vhdl verilog Specifies the HDL language VHDL or Verilog Default vhd1 Log Output log logfile log Specifies the log file Default simgen 1og Library Directories lp Library Path Allows you to specify library directory paths This option can be specified more than once for multiple library directories Simulation Model Type m beh str tim Allows you to select the type of simulation models to be used The supported simulation model types are behavioral beh structural str and timing tim Default beh Mixed Language mixed yes no Allows or disallows the use of mixed language behavioral files yes Use native language for peripherals and allow mixed language systems no Use structural files for peripherals not available in selected language Note Only valid when m beh is used Default yes Output Directory od output dir Specifies the project directory path The default is the current directory Target Part or Family p lt partname gt Allows you to target a specific part or family This option must be specified Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com
226. inal driver instance merged driver original processor instance merged processor original OS instance merged OS original library instance or merged library lt interface_name gt is the required interface If specified as an asterisk the API returns a list of interface handles To access an individual interface handle you can iterate over the list in Tcl Example set swif handle xget sw interface handle mld handle interface name xget sw library handle mss handle library name Description Returns the handle to the library with the lt 1ibrary_name gt associated with the specified mss handle Arguments library name is the name of the required library mss handle is the handle to the MSS file Example set lib handle xget sw library handle mss handle library name xget sw mdd handle handle Description Returns a handle to the MDD object associated with the given driver or processor instance Arguments handle is of specified type Types can be original driver instance original processor instance merged driver or merged processor Example set mdd handle xget sw mdd handle drv handle xget sw mld handle handle Description Returns a handle to the MLD object associated with the given OS or library instance Arguments handle is of specified type Valid types are original OS instance original library instance merged OS or merged library Example set
227. ing figure Simgen requires an MHS file as input Simgen creates a set of HDL files that model the functionality of the design Optionally Simgen can generate a compile script for a specified vendor simulator If specified Simgen can generate HDL files with data to initialize block RAMs associated with any processor that exists in the design This data is obtained from an existing Executable Linked Format ELF file UG111 02 101705 Figure 6 2 Behavioral Simulation Model Generation www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 6 Simulation Model Generator Simgen XILINX Structural Models To create a structural simulation model as shown in the following figure Simgen requires an MHS file as input and associated synthesized netlist files From these netlist files Simgen creates a set of HDL files that structurally model the functionality of the design Optionally Simgen can generate a compile script for a specified vendor simulator If specified Simgen can generate HDL files with data to initialize block RAMs associated with any processor that exists in the design This data is obtained from an existing ELF file The following figure illustrates the structural simulation model simulation generation sorot UG111_03_101705 Figure 6 3 Structural Simulation Model Generation Note The EDK design flow is modular Platgen generates a set of netlist files that are used by Simg
228. ing the lt I Cache start address gt instruction cache tags romemstartadr Start address of Read Only Memory This lt ROM start address gt can be used to specify flash memory range XMD sets hardware breakpoints instead of software breakpoints romemsize Size of Read Only Memory ROM lt ROM size in bytes gt tlbstartadr Start address for reading and writing the lt TLB start address gt Translation Look aside Buffer TLB PowerPC Processor Target Requirements There are two possible methods for XMD to connect to the PowerPC processors over a JTAG connection The requirements for each of these methods are described in the following subsections Debug connection using the JTAG port of a Virtex FPGA If the JTAG ports of the PowerPC processors are connected to the JTAG port of the FPGA internally using the JTAGPPC primitive then XMD can connect to any of the PowerPC processors inside the FPGA as shown in the following figure Refer to the PowerPC 405 Processor Block Reference Guide and the PowerPC 440 Processor Block Reference Guide for more information A link to the document is supplied in the Additional Resources on page 152 Debug connection using I O pins connected to the JTAG port of the PowerPC Processor If the JTAG ports of the PowerPC processors are brought out of the FPGA using I O pins then XMD can directly connect to the PowerPC processor for debugging In this mode XMD can only communicate with one Powe
229. interrupt handler uses the instruction rtid for returning to the interrupted function save volatiles attribute The MicroBlaze compiler provides the attribute save volatiles which is similar to the interrupt handler attribute but returns using rtsd instead of rtid This attribute saves all the volatiles for non leaf functions and only the used volatiles in the case of leaf functions void function name attribute save volatiles The following table lists the attributes with their functions Table 8 10 Use of Attributes Attributes Functions interrupt handler This attribute saves the machine status register and all the volatiles in addition to the non volatile registers rt id returns from the interrupt handler If the interrupt handler function is a leaf function only those volatiles which are used by the function are saved save volatiles This attribute is similar to interrupt handler but it uses rtsd to return to the interrupted function instead of rt id Embedded System Tools Reference Manual www xilinx com 141 UG111 EDK 11 3 1 7 XILINX PowerPC Compiler Usage and Options PowerPC Compiler Usage and Options PowerPC Compiler Options Quick Reference PowerPC Compiler Options mcpu 440 mfpu sp lite sp full dp lite dp full none mppcperflib mno clearbss Linker Options defsym START ADDR value PowerPC Compiler Options The PowerPC processor GNU compiler powerpc ea
230. ion can be repeated once for each processor instance in the design Only one ELF per processor can be initialized into block RAM Quiet mode quiet Runs the tool in quiet mode In this mode it does not print status warning or informational messages while running It prints only error messages on the console Display version v Displays the version and then quits Note Bitlnit also produces a file named data2mem dmr which is the log file generated during invocation of the Data2MEM utility www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 12 System ACE File Generator GenACE This chapter describes the steps to generate Xilinx System ACE technology configuration files from an FPGA bitstream and Executable Linked Format ELF data files The generated ACE file can be used to e Configure the FPGA e Initialize block RAM e Initialize external memory with valid program or data e Bootup the processor in a production system EDK provides a Tool Command Language Tcl script genace tcl which uses Xilinx Microprocessor Debug XMD commands to generate ACE files ACE files can be generated for PowerPC 405 and 440 processors and the MicroBlaze processor with Microprocessor Debug Module MDM systems This chapter contains the following sections e Assumptions e Tool Requirements e GenACE Features e GenACE Model e The Genace tcl Sc
231. ions Modifying Startup Files 138 The initialization files are distributed in both pre compiled and source form with EDK The pre compiled object files are found in the compiler library directory Sources for the initialization files for the MicroBlaze GNU compiler can be found in the XILINX EDK sw lib microblaze src directory where lt XILINX_EDK gt is the EDK installation area To fulfill a custom startup file requirement you can take the files from the source area and include them as a part of your application sources Alternatively you can assemble the files into o files and place them in a common area To refer to the newly created object files instead of the standard files use the B directory name command line option while invoking mb gcc To prevent the default startup files from being used use the nostartfiles on the final compile line Note The miscellaneous compiler standard CRT files such as crti o and crtbegin o are not provided with source code They are available in the installation to be used as is You might need to bring them in on your final link command www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Reducing the Startup Code Size for C Programs If your application has stringent requirements on code size for C programs you might want to eliminate all sources of overhead This section describes how to reduce the overhead of invoki
232. ipheral has more than one slave LMB port The peripheral has more than one slave DCR port The peripheral has more than one master DCR port The peripheral has more than one slave FSL port The peripheral has more than one master FSL port The peripheral has more than one slave PLBV46 port The peripheral has more than one master PLBV46 port The peripheral has more than one OPB port of any type master slave or master slave The peripheral has more than one port of any type and the choice of un or S1n causes ambiguity in the signal names For example a peripheral with both a master OPB port and master PLB port and the same lt mn gt string for both ports requires a BI string to differentiate the ports because the address bus signal would be ambiguous without Br For peripherals that have only a single bus interface which is the case for most peripherals the use of the bus identifier string in the signal names is optional and the bus identifier is typically not included 1 Deprecated in this release Embedded System Tools Reference Manual www xilinx com 39 UG111 EDK 11 3 1 XILINX Conventions for Defining HDL Peripherals Global Ports The names for the global ports of a peripheral such as clock and reset signals are standardized You can use any name for other global ports such as the interrupt signal LMB Clock and Reset LMB Clk LMB Rst OPB Clock and Reset OPB_C1k OPB_Rst PLB
233. ipherals used with Linux and VxWorks operating systems are specified using a CONNECTED PERIPHS parameter which replaces the CONNECT TO parameter used in earlier versions When the Format Revision Tool runs it collects old CONNECT TO driver parameter peripherals and collates them in the CONNECTED PERIPHS parameter of the OS block Inthe MSS file PROCESSOR block the following parameters are removed LEVEL EXECUTABLE SHIFTER and DEFAULT INIT Inthe PROCESSOR block the DEBUG PERIPHERAL is renamed XMDSTUB PERIPHERAL Command Line Option for the Format Revision Tool Run the Format Revision tool from the command line as follows revup system xmp The following option is supported h Help Displays the usage menu and then quits 228 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 14 Version Management Tools revup XILINX The Version Management Wizard When an older projectis opened for the first time with the new version of EDK the Format Revision Tool runs and the Version Management Wizard opens Some IP cores might have been obsoleted or updated in the repository since the project was last processed so the wizard outlines the modifications provides the option to automatically upgrade to the latest backward compatible revision or provides more information on how to upgrade to the latest version of the core The wizard also gives you the option to make similar updates for dri
234. is being used it must be provided to both the compile and the link commands of the build process for your program Using the switch inconsistently can lead to compile link or run time errors mno clearbss This option is useful for compiling programs used in simulation According to the C language standard uninitialized global variables are allocated in the bss section and are guaranteed to have the value 0 when the program starts execution Typically this is achieved by the C startup files running a loop to fill the bss section with zero when the program starts execution Optimizing compilers also allocates global variables that are assigned zero in C code to the bss section Embedded System Tools Reference Manual www xilinx com 129 UG111 EDK 11 3 1 XILINX 130 MicroBlaze Compiler Usage and Options In a simulation environment the above two language features can be unwanted overhead Some simulators automatically zero the entire memory Even in a normal environment you can write C code that does not rely on global variables being zero initially This switch is useful for these scenarios It causes the C startup files to not initialize the bss section with zeroes It also internally forces the compiler to not allocate zero initialized global variables in the bss and instead move them to the data section This option might improve startup times for your application Use this option with care and ensure either that you do no
235. is not in your path The following is an example of a command for compiling Xilinx libraries for MTI SE Compxlib s mti se f all 1 vhdl w o Embedded System Tools Reference Manual www xilinx com 87 UG111 EDK 11 3 1 7 XILINX Simulation Models This command compiles the necessary Xilinx libraries into the current working directory Refer to the Command Line Tools User Guide for information Compxlib Refer to the Simulating Your Design chapter of the Synthesis and Simulation Design Guide to learn more about compiling and using Xilinx ISE simulation libraries A link to the documentation website is provided in Additional Resources page 85 Simulation Models This section describes how and when each of three FPGA simulation models are implemented and provides instructions for creating simulation models using XPS batch mode At specific points in the design process Simgen creates an appropriate simulation model as shown in the following figure The following figure illustrates the FPGA design simulation stages Design Entry Behavioral Simulation Design Implementation Design Synthesis Implemented Design Netlist Timing Simulation UG111 01 111903 Design Netlist Structural Simulation Functional Simulation ecu ceu Figure 6 1 FPGA Design Simulation Stages Behavioral Models 88 To create a behavioral simulation model as displayed in the follow
236. ities flash command set incompatibilities or memory size constraints are considerations when programming flash This section briefly describes the the flash programming algorithm so that if necessary you can plug in and replace elements of the flow to customize it for your particular setup When you click on the Program Flash button in XPS or SDK the following sequence of events occurs 1 A flash_params tcl file is written out to the etc folder This contains parameters that describe the flash programming session and is used by the flash programmer Tel file 2 XPS or SDK launches XMD with the flash programmer Tcl script executing it with a command such as xmd tcl flashwriter tcl nx This flash programmer host Tcl comes from the installation You can replace the default 1ashwriter tcl with your own driver Tcl to run when you click the Program Flash button by placing a copy of the flashwriter tcl file in your project root directory XMD searches for the specified file in your project directory before looking for it in the installation 3 The flash programmer Tcl script copies the flash programmer application source files from the installation to the etc flashwriter folder It compiles the application locally to execute from the scratch memory address you specified in the dialog box You can compile your own flash writer sources by modifying your local copy of the flashwriter tcl script to compile your own sources instead of those from
237. ives the in system flash programming stub with commands and data and completes the flash programming The flash programming tools do not process or interpret the image file to be programmed and the tools routinely program the file as is onto flash memory Your software and hardware application setup must infer the contents of the file being programmed Supported Flash Hardware The flash programmer uses the Common Flash Interface CFI to query the flash devices so it requires that the flash device be CFI compliant The layout of the flash devices to form the total memory interface width is also important The following table lists the supported flash layouts and configurations If your flash layout does not match a configuration in the table you must then customize the flash programming session Refer to Customizing Flash Programming on page 220 Table 13 1 Supported Flash Configurations x8 only capable device forming an 8 bit data bus x16 x8 capable device in x8 mode forming an 8 bit data bus x32 x8 capable device in x8 mode forming an 8 bit data bus x16 x8 capable device in x16 mode forming a 16 bit data bus Paired x8 only capable devices forming a 16 bit data bus Quad x8 only capable devices forming a 32 bit data bus Paired x16 only capable devices in x16 mode forming a 32 bit data bus x32 x8 capable device in x32 mode forming a 32 bit data bus x32 only capable device forming a 32 bit da
238. ke the BitInit tool type the following bitinit lt mhsfile gt options Note You must specify lt mhsfile gt before specifying other tool options The following options are supported in the current version of BitInit Table 11 1 Bitlnit Syntax Options Option Command Description Input BMM file bm Specifies the input BMM file which contains the address map and the location of the instruction memory of the processor Default implementation lt sysname gt _bd bmm Bitstream file bt Specifies the input bitstream file that does not have its memory initialized Default implementation lt sysname gt bit Display Help h Displays the usage menu and then quits Log file name log Specifies the name of the log file to capture the log Default bitinit log Embedded System Tools Reference Manual www xilinx com 203 UG111 EDK 11 3 1 XILINX 204 Tool Options Table 11 1 Bitlnit Syntax Options Cont d Option Command Description Libraries path lp Specifies the path to repository libraries This option can be repeated to specify multiple libraries Output bitstream file 0 Specifies the name of the output file to generate the bitstream with initialized memory Default implementation download bit Specify the Processor pe Specifies the name of the processor instance in Instance name and list associated ELF file that forms its instruction of ELF files memory This opt
239. l UG111 EDK 11 3 1 www xilinx com 157 XILINX XMD User Commands Table 9 2 XMD User Commands Cont d command options run Example Usage run Description Runs program from the program start address The command does a reset stops the processor at the reset location by using breakpoints and loads the ELF program data sections to the memory Loading the ELF program data sections ensures that the static variables are properly initialized and reset is done so the system is in a known good state The reset behavior can be configured using the following command debugconfig reset_on run system enable processor enable disable Refer to Configure Debug Session on page 189 safemode safemode options safemode config lt mode gt lt exception_mask gt safemode on of f safemode config lt exception_id gt lt exception_addr gt safemode info safemode elf elf file safemode config mode exception mask safemode on safemode off safemode config exception id exception addr safemode info safemode elf Enables disables configures and specifies files to be read in safemode Changes the current safemode configuration Enables and disables safemode Changes exception handler ID and or addresses Displays the safemode information Specifies the ELF file to be debugged state t
240. lash into external memory The bootloader then transfers control to the software application to continue execution The software application you build from your project is in Executable Linked Format ELF When bootloading a software application from flash ELF images should be converted to one of the common bootloadable image formats such as Motorola S record SREC This keeps the bootloader smaller and more simple EDK provides interface and command line options for creating bootloaders in SREC format See the Xilinx Platform Studio Help for instructions on creating a flash bootloader and on converting ELF images to SREC Embedded System Tools Reference Manual www xilinx com 217 UG111 EDK 11 3 1 XILINX Supported Flash Hardware Flash Programming from XPS and SDK The Xilinx Platform Studio XPS and the Software Development Kit SDK interfaces include dialog boxes from which you can program external Common Flash Interface CFI compliant parallel flash devices on your board connected through the external memory controller EMC IP cores The programming solution is designed to be generic and targets a wide variety of flash hardware and layouts The programming is achieved through the debugger connection to a processor in your design XPS or SDK downloads and executes a small in system flash programming stub on the target processor The in system programming stub requires a minimum of 8 KB of memory to operate A host Tcl script dr
241. le xget sw parameter value handle parameter name Description Arguments Example Returns the value of the specified parameter handle is of specified type parameter name is the specified parameter PARAMETER named stdin in the MSS file of an OS instance that is assigned uart0 the value returned by the API is VART 0 as specified in the MSS file set stdin value xget sw parameter value os handle www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Software Tcl Commands i XILINX xget_sw_option_handle lt handle gt lt option_name gt Description Returns the handle to an option associated with the handle Arguments handle is of specified type Valid handle types are MDD MLD original driver instance merged driver original processor instance merged processor original OS instance merged OS original library instance or merged library option name is the name of the option required If specified as an asterisk the API returns a list of option handles To access an individual option handle iterate over the list in Tcl Example Get a handle on an option named prc in the MLD file of an OS instance which is assigned standalone drc where the option handle is obtained from the os handle set drc handle xget sw option handle os handle xget sw option value lt handle gt option name Description Returns the value of a specified option name
242. le is a merged processor object that is available only when Libgen is run and is obtained by using the xget libgen proc handle API ipinst name is the IP instance whose merged driver information is required Example Obtain a driver for the IP of a particular IP source connected to the Interrupt controller set sw proc handle xget libgen proc handle set ip driver xget sw driver handle for ipinst sw proc handle ip name Note This example is from the intc driver Tcl file xget sw function handle handle function name Description Returns the handle to the function associated with the handle specified by function name Arguments handle is an interface handle function name is the name of the required function If specified as an asterisk the API returns a list of function handles To access an individual function handle iterate over the list in Tcl Example set func handle xget sw function handle swif handle lt function_name gt Embedded System Tools Reference Manual www xilinx com 277 UG111 EDK 11 3 1 7 XILINX Appendix C EDK Tcl Interface xget sw ipinst handle lt handle gt ipinst name Description API returns the handle to the IP instance specified by the ipinst name Arguments handle is a merged processor instance ipinst name is the name of the IP instance Example set ipinst xget sw ipinst handle mpi handle lt ipname gt xget sw ip
243. le using the command xload xmp lt basename gt xmp XPS reads in the XMP file XPS takes the name of the MSS file from the XMP file if specified Otherwise it assumes that these files are based on the XMP file name Ifthe XMP file does not refer to an MSS file but the file exists in the project directory XPS reads that MSS file If the file does not exist then XPS creates a new MSS file Reading an MSS File To read an MSS file use the command xload mss lt filename gt If you do not specify lt filename gt it is assumed to be the MSS file associated with this project Loading an MSS file overrides any earlier settings For example if you specify a new driver for a peripheral instance in the MSS file the old driver for that peripheral is overridden Saving Your Project Files To save MSS XMP and make files for your project use the command save mss xmp make proj Command save proj saves the XMP and MSS files To save the make file use the save make command explicitly Setting Project Options You can set project options and other fields in XPS using the xset command You can also display the current value of those fields by using xget commands The xget command also returns the result as a Tel string result which can be saved into a Tel variable The following table shows the options you can use with the xget and xset commands xset option lt value gt xget option Table 4 1 xset and xget Command Options
244. led versions of these libraries are shipped with EDK The CPU driver for MicroBlaze copies over the correct version based on the hardware configuration of MicroBlaze during the execution of Libgen To manually select the library version that you would like to use look in the following folder SXILINX EDK gnu microblaze platform microblaze xilinx elf lib The filenames are encoded based on the compiler flags and configurations used to compile the library For example 1ibc m bs aisthe C library compiled with hardware multiplier and barrel shifter enabled in the compiler Embedded System Tools Reference Manual www xilinx com 139 UG111 EDK 11 3 1 7 XILINX MicroBlaze Compiler Usage and Options The following table shows the current encodings used and the configuration of the library specified by the encodings Table 8 9 Encoded Library Filenames on Compiler Flags Encoding Description _bs Configured for barrel shifter _m Configured for hardware multiplier _p Configured for pattern comparator _mh Configured for extended hardware multiplier Of special interest are the math library files Libm a The C standard requires the common math library functions sin andcos forexample to use double precision floating point arithmetic However double precision floating point arithmetic may not be able to make full use of the optional single precision floating point capabilities in available for MicroBlaze
245. lementation download bit ace system ace board m1501 target mdm elf executablel elf executable2 elf Hardware and Software Partial Reconfiguration hw implementation download bit ace system ace board m1501 target mdm elf executablel elf executable2 elf Hardware Only Configuration jprog hw implementation download bit ace system ace board m1401 Hardware Only Partial Reconfiguration hw implementation download bit ace system ace board m1501 Embedded System Tools Reference Manual www xilinx com 211 UG111 EDK 11 3 1 7 XILINX Generating ACE Files Software Only Configuration jprog ace system ace board m1501 target mdm elf executablel elf Generating ACE for a Single Processor in Multi Processor System Many of the Virtex family designs contain two PowerPC processors 405 and 440 or the system might contain multiple MicroBlaze processors To generate an ACE file for a single processor use debugdevice option Use cpunr to specify the processor instance In the example we assume a configuration with two PowerPC processors and ACE file is generated for processor number two The options file for this configuration is jprog hw implementation download bit ace system ace board user configdevice devicenr 1 idcode 0x1266093 irlength 14 partname XC2VP20 debugdevice devicenr 1 cpunr 2 lt Note The cpunr is 2 target ppc_hw elf executablel elf executable2 elf Multi Pro
246. les the bus signals It checks for bus compliance or violations of the PLB architectural specifications and reports warnings and errors e PLB v4 6 Master BFM plbv46 master bfm The PLB v4 6 master model contains logic to initiate bus transactions on the PLB v4 6 bus automatically The model maintains an internal memory that can be initialized through the Bus Functional Language and may be dynamically checked during simulation or when all bus transactions have completed e PLB v4 6 Slave BFM plbv46_slave_bfm The PLB v4 6 slave contains logic to respond to PLB v4 6 bus transactions based on an address decode operation The model maintains an internal memory that can be initialized through the Bus Functional Language and may be dynamically checked during simulation or when all bus transactions have completed e PLB v4 6 Monitor plbv46 monitor bfm The PLB v4 6 monitor is a model that connects to the PLB v4 6 and continuously samples the bus signals It checks for bus compliance or violations of the PLB v4 6 architectural specifications and reports warnings and errors 74 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Using the Platform Studio BFM Package e BFM Synchronization Bus b m synch The BFM Synchronization Bus is not a bus BFM but a simple bus that connects BFMs in a design and allows communication between them The BFM Synchronization Bus is required whenever BFM devices are used
247. list for driver merged driver handle Description Returns a list of handles to peripherals that are assigned to the driver associated with the merged driver handle Arguments merged driver handle is available only when Libgen is run and obtained by using the xget sw driver handle for ipinst API Example Get the list of all peripherals that use the driver uartlite using the uart driver handle set periphs xget sw iplist for driver S uart driver handle xget sw ipinst handle from processor ipinst name merged processor handle Description Returns the handle to an IP instance associated with a merged processor handle Arguments ipinst name is the IP instance associated with the merged processor handle merged processor handle isthename ofthe merged processor and is obtained by the xget libgen proc handle API Example Get the handle to an instance named my p1lb ethernet set sw proc handle xget libgen proc handle set inst handle xget sw ipinst handle from processor sw proc handle my plb ethernet 278 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Software Tcl Commands XILINX xget_sw_interface handle lt handle gt lt interface_name gt Description Returns the handle to the interface associated with the handle specified by lt interface_name gt Arguments handle is an interface handle Valid handle types are MDD MLD orig
248. ll read only static and global variables with initial values rodata Read only variables text Program instructions from code in functions and global assembly statements got2 Global Offset Table GOT The GOT is to define a place where position independent code can access global data got1 Global Offset Table GOT The GOT defines a place where position independent code can access global data fixup Fixup information such as fixup record table jer Compiler specific Used by compiler initialization functions 144 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Table 8 11 Section Names and Descriptions Cont d gcc except table Language specific data Section Description tdata Initialized thread local data tbss Unititialized thread local data Tips for Writing or Customizing Linker Scripts The following points must be kept in mind when writing or customizing your own linker script e The PowerPC processor linker is built with default linker scripts This script assumes a contiguous memory starting at address OxFFFF0000 The script defines boot o as the first file to be linked The boot o file is present in the 1ibxil a library which is created by the Libgen tool The script defines the start address to be OxFFFF0000 To specify a different start address you can convey it to the linker using either a command line a
249. ly EJ XTmrCtr SetOptions amp sys tmrctr 0 XTC INT MODE OPTION XTC AUTO RELOAD OPTION Set a reset value for the timer counter such that it will expire eariler than letting it roll over from 0 the reset value is loaded 248 www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software APIs XILINX into the timer counter when it is started XTmrCtr SetResetValue amp sys tmrctr 0 OxDEADBEEF Start the timer counter such that it s incrementing by default then wait for it to timeout a number of times 4 XTmrCtr Start amp sys tmrctr 0 Register the intc device driver s handler with the Standalone software platform s interrupt table e microblaze register handler XInterruptHandler XIntc DeviceInterruptHa ndler void XPAR XPS INTC 0 DEVICE ID Enable interrupts on MicroBlaze El microblaze enable interrupts At this point the system is ready to respond to interrupts from the timer uA while 1 Standalone Software API for PowerPC 405 and 440 Processors The following are the relevant functions for handling interrupts on a PowerPC processor using the Standalone software platform void XExc Init void Description Tnitialize exception interrupt handling for the PowerPC processor system The interrupt and exception vector table is setup with a stub handler for all exceptions Embedded System Tools
250. ly Memory lt ROM Size in Bytes gt tlbstartadr Start address for reading and writing the lt TLB start address gt Translation Look aside Buffer TLB MicroBlaze MDM Target Requirements 1 To use the hardware debug features on MicroBlaze such as hardware breakpoints and hardware debug control functions like stopping and stepping the hardware debug port must be connected to the MDM 2 To use the UART functionality in the MDM target you must set the C USE UART parameter while instantiating the MDM core in a system Note Unlike the MicroBlaze stub target programs should be compiled in executable mode and NOT in XMDSTUB mode while using the MDM target Consequently you do not need to specify an XMDSTUB PERIPHERAL for compiling the XMDStub 182 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Example Debug Sessions Example Using a MicroBlaze MDM Target This example demonstrates a simple debug session with a MicroBlaze MDM target Basic XMD based commands are used after connecting to the MDM target using the connect mb mdm command At the end of the session mb gdb connects to XMD using the GDB remote target Refer to Chapter 9 Xilinx Microprocessor Debugger XMD for more information about connecting GDB to XMD XMD connect mb mdm JTAG chain configuration Device ID Code IR Length Part Name T 0a001093 8 System_ACE 2 5059093 1
251. m Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 161 XILINX XMD User Commands PowerPC 440 Processor Special Purpose Register Names The following table lists the special register names that are valid for PowerPC 440 processors Table 9 4 pc fpscr srr0 dear csrrl dac2 dbdr iac4 decar ivor4 ivor10 invO itv2 dtv0 dcdbtrl mcsrr1 f5 f11 f17 f23 f29 PowerPC 440 Processor Special Purpose REgister Names msr pvr srr1 ivpr dbsr pir ccr0 dbcr2 uspre0 ivor5 ivor11 inv1 itv3 dtv1 dcdbtrh f0 f6 f12 f18 124 30 cr sprg0 tbl tsr dbcr0 rstcfg dbcr1 sprg4 ivor0 ivor6 ivor12 inv2 dnv0 dtv2 icdbtrl fl f7 f13 f19 f25 f31 lr sprg1 tbu tcr lacl mmucr dvcl sprg5 ivorl ivor7 ivor13 inv3 dnv1 dtv3 icdbtrh f2 f8 f14 20 26 ctr sprg2 s icdbdr dec lac2 pid dvc2 sprg6 ivor2 ivor8 ivorl4 itvO dnv2 dvlim mcsr f3 f9 f15 21 27 xer prg3 esr csrr0 dacl ccrl iac3 sprg7 ivor3 ivor9 ivor15 itv1 dnv3 ivlim mcsrr f4 f10 f16 f22 f28 Note XMD always uses 64 bit notation to represent the Floating Point Registers f0 f31 In the case of a Single Precision floating point unit the 32 bit Single Precision value is extended to a 64 bit value For additional information about PowerPC440 processor special register names refer to the Register Set Summary section of the PowerPC 440 Processor Block Refere
252. m c lk s uo Ni Embedded System Tools Reference Manual www xilinx com 271 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface Delete Commands xdel_hw_ipinst lt mhs_handle gt lt inst_name gt Description deletes the IP instance with a specified instance name Arguments lt mhs_hand1e gt is the handle to the original MHS inst name is the name of the instance to be deleted Example Delete an instance called mymb xdel_hw_ipinst mhs handle mymb xdel hw ipinst busif ipinst handle busif name Description Deletes a specified bus interface on an IP instance handle Arguments ipinst handle is the handle of the IP instance busif name is the name of the bus interface that is to be deleted Example Delete the ILMB bus interface from a MicroBlaze instance xdel hw ipinst busif mb handle ILMB xdel hw ipinst port ipinst handle port name Description Deletes a specified port on an IP instance handle Arguments ipinst handle is the handle of the IP instance port name is the name of the port to be deleted Example Delete a C1k port on a given MicroBlaze instance xdel hw ipinst port mb handle Clk xdel hw ipinst parameter ipinst handle param name Description Deletes a specified parameter on an IP instance handle Arguments ipinst handle is a handle to the IP instance param name is the name of the parameter to be deleted Example Delete t
253. m could cause programs downloaded to other processors earlier in the sequence to get reset This may or may not be desirable consequently use the debugconfig command to disable system reset and or enable processor reset only on the various processors The following are example use cases Example 1 One Master Processor and Multiple Slave Processors In this scenario the program on the master processor gets downloaded and run first followed by the other processors In this case the user wants to enable system reset on download to the master processor and only a processor reset or no reset on the other processors Example 2 Peer Processors In this case the download sequence could be arbitrary and the user wants to enable only processor reset or no reset at both the processors This will ensure that downloading a program to one of the peer processors does not affect the system state for the other peers Refer the proc_sys_reset IP module documentation for more information on how the reset connectivity and sequencing works through this module XMD Internal Tcl Commands In the Tcl interface mode XMD starts a Tcl shell augmented with XMD commands All XMD Tel commands start with x and you can list them from XMD by typing x Xilinx recommends using the Tcl wrappers for these internal commands as described in Table 9 1 on page 152 The Tcl wrappers print the output of most of these commands and provide more options While the Tcl
254. ment Tools revup As ok heed ok whol hn bok vad he A A 225 Format Revision Tool Backup and Update Processes 226 WDB Ch ngess o fae sid seg eee cheer tee ati s dip qp diodes eedem ena a desiqed sacas 226 IUGERA 226 MACAO C Oda ty ae ac 226 10 1 Chan ges ici A i da qae Qm d wai eds 227 LIC SOS nm 227 Changes T 97i educi ieget UR ERE aree terr aree ga ra eet dec dei aides 227 Changes 10 821 esseer eere erp rh baute Roe rd eer x nee eh oie close ra 227 Changes in 8 1 4 ties ete EET A PETERE en ER heri a ed 227 Changes 17 di EE 228 Changes 1m 6 81 Loo eset Ee eae dere steeds edat Cedere de ed 228 Changes 1n 6 21 3 ete eergexe eret e aile dup e het 228 Command Line Option for the Format Revision Tool 228 The Version Management Wizard usuiussssssssssese esse 229 Chapter 15 Xilinx Bash Shell SUMMATY MERERI EM 281 The EDK Installed Cygwin Environment ooooocccccoococccccnnrrrra eens 231 14 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 7 XILINX Requirements for Using an Existing Cygwin Environment ooooooomomoo 231 Xilinx Bash Shell sese adc dad whe O 23 Using XDa8D e tede rte HG HI EC e HE IH de trie Eae a eed 232 The override and undo Options oooocccocccooccnnncrrrnannn nrnrnnn 232 Cygwin on Windows Vista platform seeeeee ee 232 Appendix A GNU Utilities General Purpose Utility for MicroBlaze and PowerPC
255. mld handle xget sw mld handle os handle Embedded System Tools Reference Manual www xilinx com 279 UG111 EDK 11 3 1 XILINX 280 Appendix C EDK Tcl Interface xget sw name handle Description Arguments Example Returns the name of the specified handle For an OS instance named standalone in the MSS file the name returned by the API is standalone Similarly to get the name of a parameter from a parameter handle you can use the same command handle is of specified type Get the OS instance and its name set os name xget sw name os handle xget sw parameter handle lt handle gt parameter name Description Arguments Example Returns the handle to a parameter associated with the handle handle is of specified type Valid handle types are MDD MLD MSS merged MSS original driver instance merged driver original processor instance merged processor original OS instance merged OS original library instance or merged library Note Based on the handle type the returned parameter is either original or merged parameter name is the required parameter If specified as an asterisk the API returns a list of parameter handles To access an individual parameter handle you can iterate over the list in Tcl Get the handle for a PARAMETER named stdin in the MSS file of an OS instance obtained from the os handle set stdin handle xget sw parameter handle os hand
256. mon Flash Interface Digital Clock Manager Device Control Register Data side Local Memory Bus See also LMB Direct Memory Access Data side On chip Peripheral Bus See also OPB Design Rule Check Electronic Data Interchange Format file An industry standard file format for specifying a design netlist Embedded Development Kit Executable Linked Format file www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Terms Used in EDK EMC EST XILINX Enclosure Management Controller Embedded System Tools FATfs XilFATfs Flat View FPGA FSL GDB GPIO LibXil FATFile System The XilFATfs file system access library provides read write access to files stored on a Xilinx SystemACE CompactFlash or IBM microdrive device Flat view provides information in the Name column of the IP Catalog and System Assembly Panel as directly visible and not organized in expandable lists Field Programmable Gate Array MicroBlaze Fast Simplex Link Unidirectional point to point data streaming interfaces ideal for hardware acceleration The MicroBlaze processor has FSL interfaces directly to the processor GNU Debugger General Purpose Input and Output A 32 bit peripheral that attaches to the on chip peripheral bus Hardware Platform Embedded System Tools Reference Manual UG111 EDK 11 3 1 Xilinx FPGA technology allows you to customize the hardware logic in your processor subsyst
257. mories Reserved Purpose Start Address MicroBlaze 0x0 0x4F Reset Interrupt 0x50 Exception and other reserved vector locations PowerPC OxFFFFFFFC Reset vector location OxFFFF0000 OxFFFFFFFF I O Memory I O memory refers to addresses used by your program to communicate with memory mapped peripherals on the processor buses These addresses are defined as a part of your hardware platform specification User and Program Memory User and Program memory refers to all the memory that is required for your compiled executable to run By convention this includes memories for storing instructions read only data read write data program stack and program heap These sections can be stored in any addressable memory in your system By default the compiler generates code and data starting from the address listed in Table 8 5 and occupying contiguous memory locations This is the most common memory layout for programs You can modify the starting location of your program by defining in the linker the symbol _TEXT_START_ADDR for MicroBlaze and _START_ADDR for PowerPC processors In special cases you might want to partition the various sections of your ELF file across different memories This is done using the linker command language refer to the Linker Scripts page 125 for details The following are some situations in which you might want to change the memory map of your executable When partitioning large
258. moved from the project Simulation library paths are now applied across all the XPS projects for the machine e Updates XMP Stack and Heap size for custom linker scripts can no longer be provided in the compiler settings dialog These have to be specified in the custom linker script Stack and Heap size can be provided through the compiler settings dialog for default linker scripts Changes in 8 2i e Updates MHS For submodule designs the Format Revision Tool expands any I O ports into individual I O and _T ports This aligns with changes to Platgen any buffers in the generated stub HDL are not instantiated and the interface of the generated HDL stays the same as that in the MHS file e Updates MHS The Format Revision Tool changes the value of SIGIS for top level ports from DCMCLK to CLK The value DCMCLK has been deprecated e The preprocessor assembler and linker specific options for a software application are moved and included among the Advanced Compiler Options settings individual options have been eliminated e Updates XMP The synthesis tool setting is removed Changes in 8 1i e Update MSS The PROCINST PARAMETER is added to LIBRARY blocks which ensures that a given library can be configured differently across different processor instances in the system Embedded System Tools Reference Manual www xilinx com 227 UG111 EDK 11 3 1 XILINX Command Line Option for the Format Revision Tool e Updates Linkerscri
259. mpiler determines the type of your file from the file extension Table 8 1 illustrates the valid extensions and the corresponding file types The GCC wrapper calls the appropriate lower level tools by recognizing these file types Table 8 1 File Extensions Extension File type Dialect ue C file E C file CXX C file Cpp C file C C file Moro C file 8 Assembly file but might have preprocessor directives 8 Assembly file with no preprocessor directives Libraries Table 8 2 lists the libraries necessary for the powerpc eabi gccandmb gcc compilers as follows Table 8 2 Libraries Used by the Compilers Library Particular libxil a Contain drivers software services such as XilMFS and initialization files developed for the EDK tools libc a Standard C libraries including functions like strcmp and strlen libgcc a GCC low level library containing emulation routines for floating point and 64 bit arithmetic libm a Math Library containing functions like cos and sine libsupc a C support library with routines for exception handling RTTI and others libstdc a C standard platform library Contains standard language classes such as those for stream I O file I O string manipulation and others Libraries are linked in automatically by both compilers If the standard libraries are overridden the search path for these libraries mu
260. mps to that address The calculation varies between the PowerPC 405 processor and the PowerPC 440 processor The PowerPC 405 processor consults the software set value of the Exception Vector Prefix Register EVPR and adds a constant offset to this value depending on the interrupt type to determine the final physical address where the vector code is placed The PowerPC 440 processor has independent offset registers for each interrupt type labeled IVORO IVOR15 Each offset register contains a value that is appended to the Interrupt Vector Prefix register IVPR to obtain the final physical address of the interrupt vector code 3 The processor jumps to the calculated interrupt vector code address Each interrupt vector location contains a platform interrupt handler that is appropriate for the interrupt type For external critical and non critical interrupts the handler saves all of the processor registers that could be clobbered further down onto the current application stack The handler then transfers control to the next level handler Because this can be dependent on whether there is an interrupt controller in the system the handler consults an internal interrupt vectoring table to determine the function address of the next level handler The handler also consults the vectoring table for a callback value that it must pass to the next level handler Then the handler makes the actual call Embedded System Tools Reference
261. ms initialization functions and displays usage instructions for creating waveform and list ModelSim only windows using the waveform and list scripts The top level scripts invoke instance specific scripts You might need to edit hierarchical path names in the helper scripts for test harnesses not created by Simgen Commands in the scripts are commented or not commented to define the displayed set of signals Editing the top level waveform or list scripts allows you to include or exclude signals for an instance editing the instance level scripts allows you to include or exclude individual port signals For timing simulations only top level ports are displayed Simgen does not provide simulation models for external memories and does not have automated support for simulation models External memory models must be instantiated and connected in the simulation testbench and initialized according to the model specifications www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 7 Library Generator Libgen This chapter describes the Library Generator utility Libgen which is required for the generation of libraries and drivers for embedded soft processors It also describes how you can customize peripherals and associated drivers This chapter contains the following sections e Overview e Additional Resources e Tool Usage e Tool Options e Load Paths e Output Files
262. n 2 Directories are passed to the compiler with the B dir name option 3 The compilers search the following libraries a S XILINX EDK gnu processor platform processor lib lib b S XILINX EDK lib processor Note Processor indicates powerpc eabi for the PowerPC processor and microblaze for MicroBlaze Header files are searched in the following order 1 Directories are passed to the compiler with the I dir name option 2 The compilers search the following header files a S XILINX EDK gnu processor platform lib gcc processor 4 1 1 include b S XILINX EDK gnu processor platform processor lib include 118 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX The compilers search initialization files in the following order 1 2 Directories are passed to the compiler with the B dir name option The compilers search XILINX EDK gnu processor platform processor lib lib The compilers search the following libraries a XILINX_EDK gnu lt processor gt platform lt processor lib gt lib b SXILINX_EDK 1ib processor Where processor is powerpc eabi for PowerPC and microblaze for MicroBlaze processor lib is powerpc eabi for PowerPC and microblaze xilinx elf for MicroBlaze Note platform indicates sol for Solaris lin for Linux lin64 for Linux 64 bit and nt for Windows Cygwin The compilers sea
263. n A reset brings the system to a known consistent state for program execution This ensures correct program execution without any side effects from a previous program run By default XMD performs system reset on run on program download or program run e To enable different reset types specify debugconfig reset_on_run processor enable debugconfig reset_on_run system enable e To disable reset specify debugconfig reset_on_run disable Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 189 7 XILINX Connect Command Options Configuring Instruction Step Modes XMD supports two Instruction Step modes You can use the debugconfig command to select between the modes The two modes are e Instruction step with interrupts disabled This is the default mode In this mode the interrupts are disabled e Instruction step with interrupts enabled In this mode the interrupts are enabled during step operation XMD sets a hardware breakpoint at the next instruction and executes the processor If an interrupt occurs itis handled by the registered interrupt handler The program stops at the next instruction Note The instruction memory of the program should be connected to the processor d side interface XMD debugconfig Debug Configuration for Target 0 Step Modest arasi a bel Interrupt Disabled Memory Data Width Matching Disabled XMD debugconfig step mode enable interrupt XMD d
264. n environment does not conform to these standards you must use the Xilinx Bash Shell Error messages and warnings may be displayed based on state of the existing Cygwin installation Xilinx Bash Shell The Xilinx Bash shell is a Linux environment emulation mechanism based on Cygwin It is used to run EDK tools and other bin utilities with a Linux look and feel on the Windows platform To invoke the shell from the Windows Start menu select Start Programs gt Xilinx ISE Design Suite 11 gt EDK gt Accessories gt Launch Xilinx Bash Shell This launches the xbash utility which is located at k ILINX_EDK bin nt xbash exe Embedded System Tools Reference Manual www xilinx com 231 UG111 EDK 11 3 1 7 XILINX Xilinx Bash Shell Using xbash To find usage information about xbash use the xbash help command Usage xbash c lt COMMAND gt override undo c lt COMMAND gt Run lt COMMAND gt on the Xilinx Bash Shell override Override local Cygwin installation and use the EDK Cygwin version undo Undo the effect of the override option help Print this help menu When using an existing Cygwin installation on the computer the specifications in the Cygwin Requirements section need to be met If not you will be prompted to upgrade to a newer version of Cygwin or to install the required tools In the event that a Cygwin version upgrade is necessary you may choose to use the EDK Cygwin by using the override and undo
265. n or providing a linker script that lists the value for the start address You are not required to use de sym _START_ADDR if you want to use the default start address set by the compiler This is a linker option Use this option when you invoke the linker separately If the linker is being invoked as a part of the powerpc eabi gcc flow use the option W1 defsym Wl START ADDR value The PowerPC linker uses linker scripts to assign sections to memory The following subsection lists the script sections PowerPC Processor Linker Script Sections The following table lists the input sections that are assigned by the PowerPC processor linker scripts Table 8 11 Section Names and Descriptions Section Description boot Processor reset vector code with initial branch to boot0 boot0 Boot code heap Section of memory defined for the heap Stack Section of memory defined for the stack bss Static and global variables without initial values Is initialized to 0 by the boot code Sbss Small static and global variables without initial values Initialized to 0 by the boot code Sbss2 Small read only static and global variables with initial values Initialized to zero by the boot code Sdata Small static and global variables with initial values data Static and global variables with initial values These variables are initialized to zero by the boot code Sdata2 Sma
266. n returning from _crtinit it ends the program by infinitely looping atthe _exit label Because the other vectors are not populated the GNU linking mechanism does not pull in any of the interrupt and exception handling related routines thus saving code space Second Stage Initialization Files According to the C standard specification all global and static variables must be initialized to 0 This is a common functionality required by all the CRTs above Another routine _crtinit is invoked The crtinit routine initializes memory in the bss section of the program The _crtinit routine is also the wrapper that invokes the main procedure Before invoking the main procedure it may invoke other initialization functions The _crtinit routine is supplied by the startup files described below crtinit o This is the default second stage C startup file This startup file performs the following steps 1 Clears the bss section to zero 2 Invokes program init 3 Invokes constructor functions init 4 Setsup the arguments for main and invokes main 5 Invokes destructor functions fini 6 Invokes program clean and returns pgcrtinit o This second stage startup file is used during profiling This startup files performs the following steps Clears the bss section to zero Invokes program init Invokes profile init to initialize the profiling library Invokes constructor functions init Sets up the arguments
267. n script files for simulating the complete system Simulation Library Compiler Compxlib Compiles the EDK simulation libraries for the target simulator as required before starting behavioral simulation of the design Software Development and Verification Software Development Kit SDK An integrated design environment GUI that helps you with the development of software application projects Library Generator Libgen Constructs a software platform comprising a customized collection of software libraries drivers and OS GNU Compiler Tools GCC Builds a software application based on the platforms created by the Libgen Xilinx Microprocessor Debugger XMD Used for software download and debugging Also provides a channel through which the GNU debugger accesses the device Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 21 Chapter 1 Embedded System and Tools Architecture Overview XILINX Table 1 1 EDK Tools and Utilities Cont d GNU Debugger GDB GUI for debugging software on either a simulation model or target device Bitstream Initializer Bitinit Updates an FPGA configuration bitstream to initialize the on chip instruction memory with the software executable Debug Configuration Wizard Automates hardware and software platform debug configuration tasks common to most designs System ACE File Generator GenACE Generate
268. n the name the generics associated with bus parameters are assumed to be global For example C_DOPB_DWIDTH has a bus identifier of D and is associated with the bus signals that also have a bus identifier of D If only C OPB DWIDTH is present it is associated with all OPB buses regardless of the bus identifier on the port signals Note For the PLBV46 bus interface the bus identifier BI is treated as the bus tag bus interface name For example C SPLBO DWIDTH has a bus identifier tag SPLBO and is associated with the bus signals that also have a bus identifier of SPLBO as the prefix e For peripherals that have only a single bus interface which is the case for most peripherals the use of the bus identifier string in the signal and generic names is optional and the bus identifier is typically not included e All generics that specify a base address must end with _BASEADDR and all generics that specify a high address must end with _HIGHADDR Further to tie these addresses with buses they must also follow the conventions for parameters as listed above e For peripherals with more than one bus interface type the parameters must have the bus standard type specified in the name For example parameters for an address on the PLB bus must be specified as C PLB BASEADDR and C PLB HIGHADDR The Platform Generator Platgen expands and populates certain reserved generics automatically For correct operation a bus tag must be associ
269. n understanding of hardware interrupts and their usefulness The sections in this document are Additional Resources Hardware Setup Software Setup and Interrupt Flow Software APIs Additional Resources Platform Specification Format Reference Manual http www xilinx com ise embedded edk_docs htm PowerPC Processor Reference Guide http www xilinx com ise embedded edk_docs htm OS and Libraries Document Collection http www xilinx com ise embedded edk_docs htm Using and Creating Interrupt Based Systems Application Note http direct xilinx com bvdocs appnotes xapp778 pdf Xilinx device drivers document in the EDK installation doc usenglish xilinx drivers htm Embedded System Tools Reference Manual www xilinx com 237 UG 111 EDK 11 3 1 XILINX Appendix B Interrupt Management Hardware Setup 238 You must first wire the interrupts in your hardware so the processor receives interrupts The MicroBlaze processor has a single external interrupt port called Interrupt The PowerPC 405 processor and the PowerPC 440 processor each have two ports for handling interrupts One port generates a critical category external interrupt and the other port generates a non critical category external interrupt the difference between the two categories being the priority level over other competing interrupts and exceptions in the system The critical category has the highest priority
270. nable instructions that can compute the higher 32 bits of a 32x32 bit multiplication This option tells the compiler to use these multiply high instructions The compiler automatically defines the C pre processor definition HAVE HW MUL HIGH when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is available or not Refer to the MicroBlaze Processor Reference Guide for more details about the usage of the multiply high instructions in MicroBlaze A link to the document is provided in the Additional Resources page 109 mno xl multiply high Do not use multiply high instructions This option is the default mxl soft mul This option tells the compiler that there is no hardware multiplier unit on MicroBlaze so every 32 bit multiply operation is replaced by a call to the software emulation routine mulsi3 This option is the default mno xl soft div You can instantiate a hardware divide unit in MicroBlaze When the divide unit is present this option tells the compiler that hardware divide instructions can be used in the program being compiled This option can improve the performance of your program if it has a significant amount of division operations The compiler automatically defines the C pre processor definition HAVE HW DIV when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as availabl
271. name of the IP instance whose handle is required If ipinstf name is specified as an asterisk the API returns a list of IP instance handles To access an individual IP instance handle you can iterate over the list in Tcl www xilinx com 261 XILINX Appendix C EDK Tcl Interface xget hw mpd handle lt ipinst_handle gt Description Returns a handle to the MPD object associated with the specified IP instance Arguments ipinst handle isa handle to the merged IP instance xget hw name lt handle gt Description Returns the name of the specified handle Arguments handle is of specified type If handle is of type IP instance its name is the instance name of that IP For example if the handle refers to an instance of MicroBlaze called mymb in the MHS file the value the API returns is mymb Similarly to get the name of a parameter from a parameter handle you can use the same command xget hw option handle handle option name Description Returns a handle to the associated option Arguments handle is the associated option lt option_name gt is the name of the option whose value is required If specified as an asterisk the API returns a list of option handles To access an individual option handle you can iterate over the list in Tel xget hw option value handle option name Description Returns the value of the option The value is specified in the MPD file and cannot b
272. nce Guide A link to the document is supplied in the Additional Resources page 152 XMD Reset Sequence When the rst command is issued XMD resets the processor or system to bring them back to known states Following are the sequences of operation that rst does for each type of processors www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX PowerPC 405 Processors Disable virtual addressing If reset address 0xFFFFFFFC is writable and not on OCM write a branch to self instruction at the reset location Set DBCRO to 0x81000000 Issue reset signal either system reset or processor reset through JTAG Debug Control Register DCR The processor starts running Stop the processor Restore the original instruction at reset address PowerPC 440 Processors 1 Set DBCRO to 0x81000000 2 Set register MMUCR to 0 3 Set DBCR1 and DBCR2 to 0 4 Set up TLB so that virtual addresses are the same as real addresses 5 Synchronize with the shadow TLB 6 If reset address 0xFFFFFFFC is writable write a branch to self instruction at the reset location 7 Issue reset signal either system reset or processor reset through JTAG DCR The processor starts running 8 Stop the processor 9 Restore the original instruction at reset address MicroBlaze 1 Set a hardware breakpoint at reset location 0x0 2 Issue reset signal system
273. nch END Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 75 Chapter 5 Bus Functional Model Simulation XILINX BEGIN opb v20 PARAMETER INSTANCE opb bus PARAMETER HW VER 1 10 b PARAMETER C EXT RESET HIGH O0 PORT SYS Rst PORT OPB_C1k END BEGIN opb uartli sys reset sys clk ce ETER INSTANCE my uart R 1 00 b ETER C DATA BITS 8 FREQ 100000000 PARAM PARAMETER HW_VE PARAM PARAMETER C_CLK_ PARAMETER C_BAU PARAMETER C_USE PARAMETER C_BAS PARAMETER C_HIG BUS_INTERFACE S PORT RX rx PORT TX tx ND E BEGIN opb gpio PARAMETER C GPI PARAMETER C AL PARAMETER C BAS PARAMETER C HIG BUS INTERFACE S PORT GPIO IO END DRATE 19200 PARITY 0 EADDR Oxffff0200 HADDR OxffffO2ff OPB opb bus PARAMETER INSTANCE my gpio PARAMETER HW VER 1 00 a O WIDTH 8 INPUTS 0 EADDR Oxffff0100 HADDR OxffffOl1ff OPB opb_bus leds PLB BFM Component Instantiation The following is an example MHS file that instantiates PLB BFM components and the BFM synchronization bus Parameters PARAMETER VERSION 2 1 0 Ports PORT sys_clk sys_clk DIR I SIGIS PORT sys_reset
274. nent Instantiation suse PLB v4 6 BFM Component Instantiation 6 666 BFM Synchronization Bus Usage OPB Bus Functional Language Usage 0 6 6 0 c cece eee PLB Bus Functional Language Usage oocooccccccccccccccccc Bus Functional Compiler Usage 0 6 66 c cece e eee eens Running BFM Simulations 0 0 0 ee eens Chapter 6 Simulation Model Generator Simgen Simg n Overview paisa id dines eek et Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 XILINX 7 XILINX Additional Resources 00 0 000 ccc e as 85 Simulation Libraries 00 0 0 0 0000 ccc cece ee 86 Xilinx ISE Libraries ai it ce dee e acere e i 86 UNISIM Tabi ary 33202 tr DOR renes e p Ple quiete beue hee eate teen 86 SIMPBRIM Library vs 5532 pt a Pace educ a ete es o 86 XilinxCoreLib Eibrary z 24s de Pete eat edes p ee UE Pe me eere udin ake 87 Xilinx EDK Library idco a ir bec beta id cb e dias 87 EDK Libraries Search Order 87 Compxlib Uy cirios dd di br din 87 Simulation Models 88 Behavioral Models 2 ck ex Ebr a Bee areca alee pia 88 Structural Models ii a AS DXSu ly T EE an pU REY 89 Timing Models dead eu UM IAS EE E 89 Single and Mixed Language Models sse 90 Creating Simulation Models Using XPS Batch Mode ooooooococccccccccnoo 90 Simpen Syntax usesed oves d ecsetoxeedamo v ed persa 91 ISequiremetits ou cio dco das a a is 91 Opos a ee
275. ness name prj Project file specifying HDL source and libraries to compile for the ISim when Simgen creates a test harness test harness fuse sh Helper script to create a simulation executable ISim only when Simgen creates a test harness test harness setup do sh tcl Helper script to set up the simulator and specify signals to display in a waveform window or tabular list window ModelSim only test harness wave do sv tcl Helper script to set up simulation waveform display test harness list do Helper script to set up simulation tabular list display ModelSim only instance wave do sv tcl Helper script to set up simulation waveform display for the specified instance instance list do Helper script to set up simulation tabular list display for the specified instance ModelSim only Embedded System Tools Reference Manual www xilinx com 93 UG111 EDK 11 3 1 XILINX Memory Initialization Memory Initialization VHDL Verilog Test Benches 94 If a design contains banks of memory for a system the corresponding memory simulation models can be initialized with data You can specify a list of ELF files to associate to a given processor instance using the pe switch The compiled executable files are generated with the appropriate GNU Compiler Collection GCC compiler or assembler from corresponding C or assembly source code Note Memory initialization of structural simulation
276. ng Conventions Sln A meaningful name or acronym for the slave output S1n must rot contain the string PLB upper lower or mixed case so that slave outputs are not confused with bus outputs lt nPLB gt A meaningful name or acronym for the slave input The last three characters of lt nPLB gt must contain the string PLB upper lower or mixed case lt BI gt A bus identifier Optional for peripherals with a single slave PLB port and required for peripherals with multiple slave PLB ports lt BI gt must not contain the string PLB upper lower or mixed case For peripherals with multiple PLB ports the BI strings must be unique for each bus interface Note f Bl is present lt Sin gt is optional PLB Slave Outputs For interconnection to the PLB slaves must provide the following outputs lt BI gt lt S1n gt _addrAck out lt BI gt lt S1n gt _MErr out BI Sln MBusy out BI Sln rdBTerm out lt BI gt lt S1n gt _rdComp out lt BI gt lt Sln gt _rdDAck out BI Sln rdDBus out lt BI gt lt S1n gt _rdWdAddr lt BI gt lt S1n gt _rearbitrate lt BI gt lt S1n gt _SSize std_logic std_logic_vector 0 to C BI PLB NUM MAS std logic vector 0 to C BI PLB NUM MAS std logic std logic std logic std logic vector 0 to C BI PLB DWIDTH 1 out std logic vector 0 to 3 out std logic out std logic 0 to 1 BI Sln wait
277. ng the C constructor or destructor code in a C program that does not require that code You might be able to save approximately 220 bytes of code space by making the following modifications 1 Follow the instructions for creating a custom copy of the startup files from the installation area as described in the preceding sections Specifically copy over the particular versions of crtn s and xcrtinit s that suit your application For example if your application is being bootstrapped and profiled copy crt2 s and pg crtinit s from the installation area 2 Modify pg crtinit s to remove the following lines brlid r15 init Invoke language initialization functions nop and brlid r15 fini Invoke language cleanup functions nop This avoids referencing the extra code usually pulled in for constructor and destructor handling reducing code size 3 Compile these files into o files and place them in a directory of your choice or include them as a part of your application sources 4 Addthe nostartfiles switch to the compiler Add the B directory switch if you have chosen to assemble the files in a particular folder 5 Compile your application If your application is executing in a different mode then you must pick the appropriate CRT files based on the description in Startup Files page 135 Compiler Libraries The mb gcc compiler requires the GNU C standard library and the GNU math library Precompi
278. ns are natively decoded and executed by MicroBlaze when the FPU is enabled in hardware and these optional instructions are enabled Refer to the MicroBlaze Processor Reference Guide for more details about the use of the hardware floating point unit option in MicroBlaze A link to the document is provided in the Additional Resources page 109 General Program Options msmall divides This option generates code optimized for small divides when no hardware divider exists For signed integer divisions where the numerator and denominator are between 0 and 15 inclusive this switch provides very fast table lookup based divisions This switch has no effect when the hardware divider is enabled mxl gp opt If your program contains addresses that have non zero bits in the most significant half top 16 bits then load or store operations to that address require two instructions MicroBlaze ABI offers two global small data areas that can each contain up to 64 K bytes of data Any memory location within these areas can be accessed using the small data area anchors and a 16 bit immediate value needing only one instruction for a load or store to the small data area This optimization can be turned on with the mx1 gp opt command line parameter Variables of size lesser than a certain threshold value are stored in these areas and can be addressed with fewer instructions The addresses are calculated during the linking stage Caution If this option
279. nstance or merged IP instance lt busif_name gt is the name of the bus interface whose value is required xget hw bus slave addrpairs merged bus handle Description Returns a list of slave addresses associated with the specified bus handle The returned value is a list of integers where e The first value is the base address of any connected peripherals e The second value is the associated high address e The following values are paired base and high addresses of other peripherals Arguments merged bus handle isahandle to a merged IP instance pointing to a bus instance xget hw connected busifs handle merged mhs handle businst name busif type Description Returns a list of handles to bus interfaces that are connected to a specified bus Arguments merged mhs handle is a handle to the merged MHS businst name is the name of the connected bus instance busif type is one of the following MASTER SLAVE TARGET INITIATOR ALL 260 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 EDK Hardware Tcl Commands 7 XILINX xget hw connected ports handle merged mhs handle connector name port type Description Arguments Returns a list of handles to ports associated with a specified connector The valid handle type is the merged MHS merged mhs handle is the handle to the merged MHS connector name is the name of the connector port typ
280. ntain the string LMB upper lower or mixed case so that slave outputs will not be confused with bus outputs lt nLMB gt A meaningful name or acronym for the slave input The last three characters of lt nLMB gt must contain the string LMB upper lower or mixed case lt BI gt Optional for peripherals with a single slave LMB port and required for peripherals with multiple slave LMB ports lt BI gt must not contain the string LMB upper lower or mixed case For peripherals with multiple slave LMB ports the BI strings must be unique for each bus interface Note f Bl is present lt Sin gt is optional LMB Slave Outputs For interconnection to the LMB slaves must provide the following outputs lt BI gt lt S1n gt _DBus out std logic vector 0 to C_ lt BI gt LMB_DWIDTH 1 BI Sln Ready out std logic Examples D Ready out std logic I Ready out std logic LMB Slave Inputs For interconnection to the LMB slaves must provide the following inputs BI nLMB ABus in std logic vector 0 to C_ lt BI gt LMB_AWIDTH 1 BI nLMB AddrStrobe in std logic BI nLMB BE in std logic vector 0 to C BI LMB DWIDTH 8 1 BI nLMB Clk in std logic BI nLMB ReadStrobe in std logic BI nLMB Rst in std logic BI nLMB WriteDBus in std logic vector 0 to C BI LMB DWIDTH 1 BI nLMB WriteStrobe in std logic Examples LM
281. nterrupt occurs The argument provided in this call as the Ca11BackRef is used as the argument for the handler when it is called InstancePtris a pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR INTC MAX NUM INTR INPUTS 1 with 0 being the highest priority interrupt Handler is the handler for that interrupt CallBackRef is the callback reference usually the instance pointer of the connecting driver Warning The handler provided as an argument overwrites any handler that was previously connected void XIntc Disconnect XIntc InstancePtr u8 Id Description Parameters Disconnects the XIntc instance InstancePtris a pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR INTC MAX NUM INTR INPUTS 1 with 0 being the highest priority interrupt 244 www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software APIs XILINX Void XIntc Enable XIntc InstancePtr u8 Id Description Parameters Enables the interrupt source provided as the argument Id Any pending interrupt condition for the specified Id occurs after this function is called InstancePtris a pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR INTC MAX NUM INTR INPUTS 1 with 0 being the highest priority interrupt
282. ntrol Status Register content el ControlStatusReg XTimerCtr mReadReg sys tmrctr BaseAddress 0 XTC TCSR OFFSET Acknowledge the interrupt by clearing the interrupt bit in the timer control status register E XTmrCtr mWriteReg sys tmrctr BaseAddress 0 XTC TCSR OFFSET ControlStatusReg XTC CSR INT OCCURED MASK print Timer interrupt occurred r n int main XStatus Status Initialize the interrupt controller driver so that it is ready to use specify the device ID that is generated in xparameters h y Status XIntc Initialize amp sys intc XPAR XPS INTC 0 DEVICE ID if Status XST SUCCESS return XST_FAILURE Embedded System Tools Reference Manual www xilinx com 251 UG 111 EDK 11 3 1 XILINX Appendix B Interrupt Management Connect the application handler that will be called when an interrupt for the timer occurs y Status XIntc_Connect amp sys_intc XPAR XPS INTC 0 XPS TIMER 0 INTERRUPT INTR XInterruptHandler my timer handler void 0 if Status XST SUCCESS return XST_FAILURE Start the interrupt controller such that interrupts are enabled for all devices that cause interrupts z7 Status XIntc_Start amp sys_intc XIN REAL MODE if Status XST_SUCCESS return XST_FAILUR B Enable the interrupt for the timer counter i XIntc Enabl
283. nvironment in which you can develop your embedded design Xilinx Synthesis Technology Zero Bus Turnaround M www xilinx com 301 XILINX Appendix D Glossary 302 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1
284. nx Microprocessor Debugger XMD for more information GNU Debugger GDB The GNU Debugger GDB is a powerful yet flexible tool that provides a unified interface for debugging and verifying MicroBlaze and PowerPC processor systems during various development phases GDB uses Xilinx Microprocessor Debugger XMD as the underlying engine to communicate to processor targets Refer to Chapter 10 GNU Debugger GDB for more information Simulation Library Compiler Compxlib The Compxlib utility compiles the EDK HDL based simulation libraries using the tools provided by various simulator vendors The Compxlib operates in both the GUl and batch modes In the GUI mode it allows you to compile the Xilinx libraries in your ISE installation using the libraries available in EDK For more information about Compxlib see Simulation Models in Chapter 6 and the ISE Command Line Tools User Guide For instructions on compiling simulation libraries refer to the Xilinx Platform Studio Help Bitstream Initializer Bitinit The Bitinit tool initializes the on chip block RAM memory connected to a processor with its software information This utility reads hardware only bitstream produced by the ISE tools system bit and outputs a new bitstream download bit which includes the embedded application executable ELF for each processor The utility uses the BMM file originally generated by Platgen and updated by the ISE tools with ph
285. o enables interrupts again on the PowerPC processor The application resumes normal execution at this point It is recommended that interrupt handlers be of a short duration and that the bulk of the interrupt work be done by application This prevents long lockouts of other possibly higher priority interrupts and is considered good system design The following figures illustrate the interrupt flow for a PowerPC processor system without and with an interrupt controller User Program xvectors S section vectors Branch to vectoring code INTR critical intr Interrupt Vectoring Code others P i Branch to user or peripheral external intr vectoring code interrupt handler Lookup the function interrupt handler registered with the OS for the current interrupt type and jump to it others User or peripheral interrupt handlers registered directly with the OS layer XExc VectorTable X11021 Figure B 5 PowerPC Processor Interrupt Flow without Interrupt Controller www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 Software APIs 7 XILINX Software APIs xvectors S section vectors Branch to vectoring code Branch to vectoring code User Program critical intr Interrupt Vectoring Code others P 9 xintc c external intr XIntc_DevicelnterruptHandler Lookup the interrupt handler registered with the OS
286. o improve timing InsertNoPads TopInst NPL File These settings are removed from the XMP LockAddr ICacheAddr DCacheAddr These settings for Address Generator in the GUI were removed Simulator MixLangSim Simulator settings are now applied across all the XPS projects The simulator settings can be set using Edit gt Preferences in the XPS GUI e Updates Simgen The CompEDKLib was removed and replaced by Compx1ib 226 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 14 Version Management Tools revup XILINX E switch was deprecated e Updates Command Line enable reset optimization option is obsoleted e Updates PsfUtility The tbus suboption was obsoleted the KIND OF reserved generics were obsoleted 10 1 Changes Tools are updated to reflect revision 10 1 The following tags were removed from the XMP file in 10 1 e UseProjNav PnImportBitFile PnimportBmmFile These settings were removed from the XMP in 10 1 9 2i Changes e Updates XMP The XMP tag EnableResetOptimization was added and its value is set to 0 false If it is set to true it will improve timing on the reset signal e Updates XMP The XMP tag EnableParTimingError was added and its value is set to 0 false If it set to 1 true the tools will error out if timing conditions are not met after Place and Route Changes in 9 1i e Updates XMP Simulation libraries path are re
287. ode El cie iH oen 52 PLBV46 Slave Outputs mc A hederae 52 PEBVA 6 Slave InpU ts euet e e a eee ass Rda iii 53 Chapter 3 Platform Generator Platgen Features oor eR et o quendi Prev dug exe nere d sins 55 Additional Resources ceiedsses rhe Ehe eR be ERE RR RE dd dra Rd edd 56 TOOL Requiremgebis i etra dE Rd Aa rd be AAA ARAS ATO Ae addc e Ce 56 Tool Usage cs 56 TO OPI eiiie di RA ia EE EEE E EE E 56 Load Path oor bo Rr Eure E A ate dia 57 O tput AJI T C 58 HDL Directory cis ci ii Rete a odere ates erue be didi es Sas neta 58 Implementation Directory sssssesseee III e 58 Synthesis Directory 2er dee rye ron ee rp a shed een nes 58 ludo NEC 59 Synthesis Netlist Cache pira E Rape ER pu let pee d e ciun 59 8 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 4 Command Line no window Mode Invoking XPS Command Line Mode Creating a New Empty Project ooooooocooccccccccccoccoccoo Creating a New Project With an Existing MHS Opening an Existing PPOJEt Ls rs tr EE e aet geh Reading an MSS Pile cs eas cero Ere Che KC RH C4 ed CC TRO dod Saving Your Project Files a asi oda eroe Ce op e eed Setting Project Options iaces das ehe eoe o Rec e Rode a nt net nn Executing Flow Commands o utuSStt tiisisssssssssss Reloading an MHS File soos tarda et ede
288. of two procedures SYSLEVEL_GENERIC_PROC and SYSLEVEL_ARCHSUPPORT_PROC These tcl procedures must be specified in the data directory of the helper core and must follow the same naming conventions as the other PSF files For example a Tcl file for the proc_common_v1_00_a core must be named ina corresponding nomenclature proc_common_v2_1_0 tc1 e The SYSLEVEL_GENERIC_PROC procedure is a generic procedure used to print any message e The SYSLEVEL_ARCHSUPPORT_PROC procedure is used to notify users of deprecated helper cores For example if the proc_common_v1_00_a core is deprecated the core developer can print a message in the tools every time this core is used within a non deprecated top level core by including this procedure in the tcl file of the helper core in the proc_common_v2_1_0 tc1 file of the proc_common_v1_00_a core as follows proc syslevel_archsupport_proc mhsinst print_deprecated_helper_core message mhsinst proc_common_v1_00_a The PRINT_DEPRECATED_HELPER_CORE_MESSAGE procedure is provided by EDK tools to generate a standard message for deprecated cores It takes the handle to the top level core and the name of deprecated helper core as arguments Embedded System Tools Reference Manual www xilinx com 289 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface Additional Keywords in the Merged Hardware Datastructure Some key
289. oints to a global port of the given name handle is the handle to the MPD original IP instance merged IP instance original MHS or merged MHS port name is the name of the port whose handle is required If port name is specified as an asterisk a list of port handles is returned To access an individual port handle you can iterate over the list in Tcl If a handle is of type MHS original or merged the returned handle points to a global port with the given name xget hw port value lt handle gt port name Description Arguments Returns the value of the specified port The value of a port is the signal name connected to that port handle is the handle to the MPD original IP instance merged IP instance original MHS or merged MHS port name is the name of the port whose value is required xget hw proj setting prop name Description Arguments 264 Returns the value of the property specified by prop name prop name is the name of the property whose value is needed Options are f pga family fpga subfamily fpga partname fpga device fpga package fpga speedgrade www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 EDK Hardware Tcl Commands 7 XILINX xget hw proc slave periphs merged proc handle Description Arguments Returns a list of handles to slaves that can be addressed by the specified processor merged proc handle i
290. ompacts the files into a zip file Refer to the XPS Online Help for the list of files that are archived 66 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 4 Command Line no window Mode XILINX Setting Options on a Software Application You can set various software application options and other fields in XPS using the xset swapp prop value command You can also display the current value of those fields using the xget_swapp_prop_value command The xget_swapp_prop_value command also returns the result as a Tel string result The following table lists the options available for setting or displaying with these commands Table 4 3 xset swapp prop value swapp name option name value xget swapp prop value swapp name option name xset_ and xget Command Options Option Name Description compileroptlevel Compiler optimization level Values are 0 to 3 debugsym Debug symbol setting Value can be from none to two corresponding none g and gstabs options executable Path to the executable ELF file sources List of sources For adding sources use the xadd_swapp_progfile command globptropt true false Specify whether to perform global pointer optimization headers List of headers For adding header files use the xadd_swapp_progfile command heapsize Heap size init bram If ELF file should be used for block RAM initialization
291. on MicroBlaze and jumps to address 0x18 194 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX Table 9 22 XMD MicroBlaze Hardware Target Signals Cont d Signal Name Value Description Processor Reset 0x80 Resets MicroBlaze using the JTAG UART Debug Rst signal System Reset 0x40 Resets the entire system by sending an OPB Rst using the JTAG UART Debug SYS Rst signal Program Trace and Profile Options Table 9 23 Program Trace Profile Options Option Description xprofile target id o GMON Output File gt Generates profile output that can be read by xprofile lt target id mb gprof or powerpc eabi gprof config sampling freq hw value binsize Specify the profile configuration sampling frequency in value profile mem start addr gt Hz Histogram binary size and memory address for collecting profile data xstats target id options Displays the simulation statistics for the current session Use the reset option to reset the simulation statistics xtracestart lt target id gt Starts collecting trace information xtracestop lt target id gt Stops collecting trace information a This command is for ISS targets only Miscellaneous Commands Table 9 24 Miscellaneous Commands Command Description xhelp Lists the XMD commands xuart r w s lt data gt Perform
292. on of the IP that needs to be added Example Add a Microblaze v7 00 a IP with the instance name mblaze to the MHS xadd_hw_ipinst mhs handle mblaze microblaze 7 00 a xadd hw ipinst port ipinst handle port name connector name Description Creates and adds a port specified by port name and connector name to the IP instance specified by the ipinst handle This API returns a handle to the newly created port if successful and NULL otherwise Arguments inst handle isthe handle to the IP instance to which the port has to be added port name is the name of the port connector name is the name of the connector Example Add a clock port on a MicroBlaze instance and connect it to the sys clk s signal xadd hw ipinst port mb handle Clk sys clk s 270 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Example Procedures XILINX xadd hw ipinst parameter lt ipinst_handle gt param name param value Description Arguments Example Creates and adds a parameter specified by param name and param value to the IP instance specified by the ipinst handle This API returns a handle to the newly created parameter if successful and NULL otherwise ipinst handle is the handle to the IP instance to which the parameter is to be added param name is the name of the parameter param value is the parameter value
293. onfiguration Wizard petite sitai cence eens 25 Simulation Model Generator Simgen 66 6 cece eens 25 Software Development Kit SDK 0 000 e eee 25 Library Generator Libgen reusi css c epa cece enn 26 GNU Compiler Tools GCC cc5 ss cis sche cede acts Ke ERE E n eee eee 26 Xilinx Microprocessor Debugger XMD ssssseee ee eee 27 GNU Debugger GOB siii A Pet a AE eee pet ed are ale 27 Simulation Library Compiler Compxlib 0 0 eee eee ene 27 Bitstream Initializer Bitinit 2 0 eee eee eee 27 System ACE File Generator GenACE 0 6 6 nee 27 Flash Memory Programmer esses hn 28 Format Revision Tool and Version Management Wizard llle 28 Xilinx Bash Shell 00 3 222 2 A e EHE Rd E E a 28 Chapter 2 Platform Specification Utility PsfUtility Tool CODHOBS sica dr deed eU QC RO CER GE e ANITA VC Do C o 30 MPD Creation Process Overview 0 0 0000 00 ccc ccc ees 31 Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 EZ XILINX Use Models for Automatic MPD Creati0M ooooooooooooooooommmooo 31 Peripherals with a Single Bus Interface ooooccccoccccccconorrrrac 32 Signal Naming Conventions sisas isses hn 32 Invoking the PstUtlity 10 pit A ePS VU A RE E E s 32 Peripherals with Multiple Bus Interfaces oooooooooororocccororrracc 32 Non Exclusive and Exclusive Bus Interfaces 0 0c cece cece een eee oo 32 Peripherals wit
294. onfiguration data to perform JTAG operations XMD and iMPACT generate SVF files for software and hardware system files respectively The set of JTAG instructions and data used to communicate with the JTAG chain on board is an SVF file It includes the instructions and data to perform operations such as e Configuring an FPGA using iMPACT e Connecting to the processor target Downloading the program and running the program from XMD These actions are captured in an SVF file format The SVF file is then converted to an ACE file and written to the storage medium These operations are performed by the System ACE controller to achieve the determined operation The following is the sequence of operations using iMPACT and XMD for a simple hardware and software configuration that gets translated into an ACE file 1 Download the bitstream using iMPACT The bitstream download bit contains system configuration and bootloop code 2 Bring the device out of reset causing the Done pin to go high This starts the processor system Connect to the processor using XMD Download multiple data files to block RAM or external memory Download multiple executable files to block RAM or external memory The PC points to the start location of the last downloaded ELF file 6 Continue execution from the PC instruction address The flow for generating System ACE files is BIT to SVE ELF to SVE binary data to SVF SVF to ACE file The following section de
295. onsible for most of the optimizations done on the input C code and for generating assembly code Assembler mb as for MicroBlaze and powerpc eabi as for PowerPC processors The assembly code has mnemonics in assembly language The assembler converts these to machine language The assembler also resolves some of the labels generated by the compiler It creates an object file which is passed on to the linker Linker mb 1d for MicroBlaze and powerpc eabi 1d for PowerPC processors Links all the object files generated by the assembler If libraries are provided on the command line the linker resolves some of the undefined references in the code by linking in some of the functions from the assembler Executable options are described in Commonly Used Compiler Options Quick Reference page 115 Linker Options page 120 MicroBlaze Compiler Options Quick Reference page 126 MicroBlaze Linker Options page 133 PowerPC Compiler Options Quick Reference page 142 Note From this point forward the references to GCC in this chapter refer to both the MicroBlaze compiler mb gcc and the PowerPC processor compiler powerpc eabi gcc and references to G refer to both the MicroBlaze C compiler mb g and the PowerPC processor C compiler powerpc eabi g Embedded System Tools Reference Manual www xilinx com 111 UG111 EDK 11 3 1 XILINX Common Compiler Usage and Options Common Compiler Usage and Options Usage
296. ool performs format changes only it does not update your design Backups of existing files such as the project file XMP the MHS and MSS files are performed before the format changes are applied The Version Management wizard appears automatically when an older project is opened in a newer version of EDK for example when a project created in EDK 10 1 is opened in version 11 3 The Version Management wizard is invoked after format revision has been performed The wizard provides information about any changes in Xilinx Processor IPs used in the design If a new compatible version of an IP is available then the wizard also prompts you to update to the new version For instructions on using the Version Management wizard see Chapter 14 Version Management Tools revup and the Xilinx Platform Studio Help Xilinx Bash Shell Because GNU based tools on the NT platform require a LINUX emulation shell the Red Hat Cygwin shell and utilities are provided as part of the EDK installation Refer to Chapter 15 Xilinx Bash Shell for more information about Cygwin and the requirements to comply with the EDK tool suite www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 2 Platform Specification Utility PsfUtility This chapter describes the various features and the usage of the Platform Specification Utility PsfUtility tool that enables automatic generation of Microprocessor Pe
297. oprocessor Software Specification MSS or library data files such as Microprocessor Peripheral Definition MPD Microprocessor Driver Definition MDD and Microprocessor library Definition MLD Access to the data structure is given as Tcl APIs Based on design requirements IP driver library and OS writers that provide the corresponding data files can access the data structure information to add some extra steps in the tools processing EDK tools also use Tool Command Language Tcl to perform various Design Rule Checks DRCs and to update the design data structure in a limited manner Additional Resources e Platform Specification Format Reference Manual http www xilinx com ise embedded edk docs htm Embedded System Tools Reference Manual www xilinx com 255 UG111 EDK 11 3 1 7 XILINX Appendix C EDK Tcl Interface Understanding Handles The tools provide access points into the data structure through a set of API functions Each API function requires an argument in the form of system information which is called a handle For example an IP defined in the Microprocessor Hardware Specification MHS file or a driver defined in the Microprocessor Software Specification MSS file could serve as a handle Handles can be of various types based on the kind of data to which they are providing access Data types include instance names driver names hardware parameters or hardware ports From a given handle you can ge
298. options The override and undo Options If Cygwin version on your machine is older than the minimum requirement of 1 5 17 you can use the xbash override option If the installed Cygwin version is at the minimum required version this option has no effect Note This option is intended to be used once only and must be executed from the Windows DOS command prompt Subsequent invocations of the xbash command or the Xilinx Bash Shell do not require this option Note Use this option with caution because it changes the existing Cygwin setup on your computer Using this option upgrades only essential Cygwin tools and DLLs on your computer it does not upgrade all the tools If you prefer to revert this change and restore the original state of the Cygwin setup use xbash undo Cygwin on Windows Vista platform For EDK to work correctly on the Windows Vista platform it is necessary for any existing Cygwin installations to be valid and to be installed with the right permissions Be aware of the following permission requirements e Any existing Cygwin installations must allow execute permissions for all users on the machine e If Cygwin is installed on the local machine by a user with Administrator privileges and if this Cygwin installation is invalid it will be necessary for a user with Administrator privileges to correct the Cygwin installation it will not be possible for a user with lesser privileges to correct the situation 232 www
299. or a unique list of drivers and libraries are built Libgen does the following for each processor Builds the directory structure as defined in the Output Files page 104 Copies the necessary source files for the drivers OSs and libraries into the processor instance specific area OUTPUT DIR processor instance name libsrc Calls the Design Rule Check DCR procedure which is defined as an option in the MDD or MLD file for each of the drivers OSs and libraries visible to the processor Calls the generate Tcl procedure if defined in the Tcl file associated with an MDD or MLD file for each of the drivers OSs and libraries visible to the processor This generates the necessary configuration files for each of the drivers OSs and libraries in the include directory of the processor Calls the post generate Tcl procedure if defined in the Tcl file associated with an MDD or MLD file for each of the drivers OSs and libraries visible to the processor Runs make with targets include and libs for the OSs drivers and libraries specific to the processor On the Linux platform the gmake utility is used while on NT platforms make is used for compilation Calls the execs generate Tcl procedure if defined in the Tcl file associated with an MDD or MLD file for each of the drivers OSs and libraries visible to the processor MDD MLD and Tcl A driver or library has two associated data files Data Definition File MDD or MLD f
300. or instance OS instance library instance or one of the merged instances processor instance OS instance library instance driver instance or the MSS object e ELEMENT the parent is the array object INTERFACE the parent could be the MDD MLD driver instance processor instance OS instance library instance or one of the merged instances processor instance OS instance library instance driver instance e FUNCTION the parent is the interface object e OPTION the parent could be one of the following the MDD or MLD driver instance the processor instance the OS instance the library instance or one of the merged instances processor instance OS instance library instance driver instance e DRVINST the parent is either the MSS or the merged MSS object e PROCINST the parent is either the MSS or the merged MSS object e OSINST the parent is either the MSS or the merged MSS object e LIBINST the parent is either the MSS or the merged MSS object e MSS MDD or MLD the parent is a NULL handle Example To get the parent of a parameter set parent handle xget sw parent handle param handle xget sw processor handle mss handle processor name Description Returns the handle to the processor with the processor name associated with the specified mss handle Arguments processor name is the name of the processor associated with the specified mss handle mss handle is
301. or registers that could be clobbered further down onto the current application stack The handler then transfers control to the next level handler Because the next level handler can be dependent on whether there is an interrupt controller in the system or not the handler consults an internal interrupt vectoring table to figure out the function address of the next level handler It also consults the vectoring table for a callback value that it must pass to the next level handler Finally the actual call is made On systems with an interrupt controller the next level handler is the handler provided by the interrupt controller driver This handler queries the interrupt controller for all active interrupts in the system For each active interrupt it consults its internal vector table which contains the user registered handler for each interrupt line If the user has not registered any handler a default do nothing handler is registered The registered handler for each interrupt gets invoked in turn in interrupt priority order On systems without an interrupt controller the next handler is the final interrupt handler that the application wishes to execute Embedded System Tools Reference Manual www xilinx com 239 UG 111 EDK 11 3 1 7 XILINX 240 7 Appendix B Interrupt Management The final interrupt handler for a particular interrupt typically queries the interrupting peripheral and figures out the cause for the interrupt I
302. outSup out std logic lt BI gt lt S1n gt _xferAck out std logic Examples IM request out std logic 1 Deprecated in this release 46 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utility PsfUtility XILINX Bridge_request out std_logic O20b request out std logic OPB Master Slave Inputs For interconnection to the OPB masters and slaves must provide the following inputs lt BI gt lt nOPB gt _ABus in std logic vector 0 to C_ lt BI gt OPB_AWIDTH 1 BI nOPB BE in std logic vector 0 to C BI OPB DWIDTH 8 1 BI nOPB Clk in std logic BI nOPB DBus in std logic vector 0 to C_ lt BI gt OPB_DWIDTH 1 BI nOPB errAck in std logic lt BI gt lt nOPB gt _MGrant in std logic BI nOPB retry in std logic BI nOPB RNW in std logic BI nOPB Rst in std logic BI nOPB select in std logic BI nOPB segAddr in std logic BI nOPB timeout in std logic BI nOPB xferAck in std logic Examples IOPB DBus in std logic vector 0 to C IOPB DWIDTH 1 OPB DBus in std logic vector 0 to C OPB DWIDTH 1 Bus1_OPB_DBus in std logic vector 0 to C Bus1 OPB DWIDTH 1 Master PLB Ports Master PLB ports must follow the naming conventions shown in the following table Table 2 12 Master PLB Port Naming Conventions Mn A meaningful name or acronym for the
303. pecification Format Reference Manual http www xilinx com ise embedded edk docs htm Tool Requirements Set up your system to use the Xilinx Integrated Development System Verify that your system is properly configured Consult the release notes and installation notes for more information Tool Usage Run Platgen as follows platgen p partname system mhs where platgen is the executable name pis the option to specify a part partname is the partname system mhs is the output file Tool Options The following table lists the supported Platgen syntax options Table 3 1 Platgen Syntax Options Option Command Description Help h help Displays the usage menu and then exits without running the Platgen flow Version v Displays the version number of Platgen and then exits without running the Platgen flow Filename f lt filename gt Reads command line arguments and options from file Integration intstyle Indicates contextual information when Style ise default invoking Xilinx applications within a flow or project environment Language lang verilog vhdl Specifies the HDL language output Default vhd1 Log output log lt logfile log gt Specifies the log file Default platgen log Library pathfor 1p lt Library_Path gt Adds Library Path to the list of IP user peripherals search directories A library is a collection and driver of repository areas repositori
304. piler libstdc a and libsupc a are not automatically linked in When compiling C programs use the G variant of the compiler to make sure all the required support libraries are linked in automatically Adding 1stdc and 1supc to the GCC command are also possible options www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX For more information about how to invoke the compiler for different languages refer to the GNU online documentation A link to the documentation is provided in the Additional Resources on page 109 Commonly Used Compiler Options Quick Reference The summary below lists compiler options that are common to the compilers for MicroBlaze and PowerPC Note The compiler options are case sensitive To jump to a detailed description for a given option click on its name General Options Library Search Options E Wp option libraryname 8 Wa option L Lib Directory C WI option g help Header File Search Option gstabs B directory I Directory Name On L directory y I directory Linker Options save temps I library defsym STACK SIZE value o filename defsym HEAP SIZE value General Options E Preprocess only do not compile assemble and link The preprocessed output displays on the standard out device S Compile only do not assemble and link Generates a s file C Compile and Assemble only do not link
305. pt MicroBlaze based application linker script updates are provided to allow the addition of new vector sections that support CRT changes e Updates Linkerscript MicroBlaze based application linker script updates are provided to allow the addition of new sections that support C e Updates Linkerscript PowerPC based application linker script updates are provided to allow the addition of new sections that support C e No Project Updates For MicroBlaze applications the program start address is changed from 0x0 to 0x50 to accommodate the change in size of xmdstub elf e No Project Updates For projects that use the Spartan 3 FPGA architecture there is a change to bitgen ut Changes in 7 1i Updates Linkerscript PowerPC based application linker script updates are provided to allow for the addition of new sections that support GCC 3 4 1 changes Changes in 6 3i Updates MHS The EDGE and LEVEL subproperties on top level interrupt ports are consolidated into the SENSITIVITY subproperty in the MHS file Changes in 6 2i e No Project Updates The mb gcc compiler option related to the hard multiplier is removed This is based only on FPGA architecture e Updates MSS In the MSS file the PROCESSOR block is split into two blocks PROCESSOR and OS In conjunction with this change TheLinux and VxWorks LIBRARY blocks are renamed to reflect their new status as OS blocks With the introduction of the OS block all per
306. pter in the MicroBlaze Processor Reference Guide A link to the document is supplied in the Additional Resources on page 152 Note When MicroBlaze is debugged in XMDSTUB mode only PC and MSR registers are accessible www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD PowerPC 405 Processor Special Purpose Register Names XILINX The following table lists the special register names that are valid for PowerPC 405 processors Table 9 3 Special Register Names for PowerPC 405 Processors ccrO Cr ctr dacl dac2 dbcr0 dbcr1 dbsr decr dcwr dear dvcl dvc2 esr evpr f0 fl f2 f3 f11 22 f12 23 f13 24 f14 25 f15 26 f16 27 f17 28 f18 29 f19 30 20 f21 iacl lac2 iac4 iccr icdbdr Ir msr pe pid pit iacl iac2 pvr sgr sler sprg0 sprgl sprg2 sprg3 sprg4 sprg5 sprg6 sprg7 srr0 srr1 srr2 srr3 suOr tbl tbu tcr tsr usprg0 xer zpr suOr tbl tbu Note XMD always uses 64 bit notation to represent the Floating Point Registers f0 f31 In the case of a Single Precision floating point unit the 32 bit Single Precision value is extended to a 64 bit value For additional information about PowerPC 405 processor special register names refer to the PowerPC 405 Processor Block Reference Guide A link to the document is supplied in the Additional Resources section Embedded Syste
307. ption like 02 or 03 as mb gcc does aggressive code motion optimizations which might make debugging difficult to follow Note For debugging with XMD in hardware mode using XMDSTUB specify the mb gcc option x1 mode xmdstub Refer to Chapter 9 Xilinx Microprocessor Debugger XMD for more information about compiling for specific targets PowerPC 405 Targets Debugging for the PowerPC 405 processor is supported by powerpc eabi gdb and XMD through the GDB Remote TCP protocol XMD supports two remote targets PowerPC 405 Hardware and Cycle Accurate PowerPC Instruction Set Simulator ISS To connect to a PowerPC 405 target 1 Start XMD and connect to the board using the connect ppc command as described in Chapter 9 Xilinx Microprocessor Debugger XMD Select Run Connect to target from GDB In the GDB target selection dialog box specify the following Target Remote TCP Hostname localhost Port 1234 4 Click OK The debugger powerpc eabi gdb attempts to make a connection to XMD If successful a message is printed in the shell window where XMD started At this point the debugger is connected to XMD and controls the debugging The GUI can be used to debug the program and read and write memory and registers Embedded System Tools Reference Manual www xilinx com 199 UG111 EDK 11 3 1 XILINX PowerPC 440 Targets PowerPC 440 Targets Debugging for the PowerPC 440 processor is supported by powerpc eabi
308. ptions refer to Table 9 8 JTAG Cable Options on page 169 and Table 9 9 JTAG Chain Options on page 169 respectively MicroBlaze Option Table 9 15 MicroBlaze Option Option Description devicenr The position in the JTAG chain of the FPGA lt MicroBlaze device position gt device containing MicroBlaze MicroBlaze Stub Serial Target Options Usage connect mb stub comm serial lt Serial Communication options gt Serial Communication Options The following options can be used to specify the MicroBlaze stub serial target Table 9 16 MicroBlaze Stub Serial Target Options Option Description baud Specifies the serial port baud rate in bits per second lt serial port baud rate gt bps The default value is 19200 bps port serial port Specifies the serial port to which the remote hardware is connected when XMD communication is over the serial cable The default serial ports are e dev ttyS0 on Linux e Com1 on Windows timeout Timeout period while waiting for a reply from timeout in secs XMDStub for XMD commands Note If the program has any I O functions such as print or putnum that write output onto the UART or MDM UART it is printed on the console or terminal in which XMD was started Refer to Chapter 7 Library Generator Libgen for more information about libraries and I O functions Embedded System Tools Reference Manual www xilinx com 185 UG111 EDK 11 3 1 7 X
309. r handle obtained from the original MSS This handle contains information present only in the MSS Merged Processor The processor handle obtained from merged MSS This handle contains MDD information and other connectivity information such as the list of merged drivers accessible from the processor the list of merged libraries accessible from the processor and the merged OS instance assigned to this processor This handle is available after Libgen is run Original Driver Instance Handle The driver handle obtained from the original MSS This handle contains information present only in the MSS Merged Driver A driver that has an associated list of peripherals that use it and all the parameter values merged The merged driver has connectivity information that is provided by the merged processor object Original OS Instance Handle The OS handle obtained from the original MSS This handle contains information present only in the MSS Merged OS Handle The OS handle obtained from the merged MSS This handle contains MLD information also 274 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Software Tcl Commands XILINX Table C 3 Software API Terms Continued Original Library Instance The library handle obtained from the original MSS This handle contains information present only in the MSS Merged Library The library handle obtained from the merged MSS This
310. rPC 405 processors running on a hardware board cycle accurate Instruction Set Simulator ISS XMD provides a Tool Command Language Tcl interface This interface can be used for command line control and debugging of the target as well as for running complex verification test scripts to test a complete system XMD supports GNU Debugger GDB remote TCP protocol to control debugging of a target Some graphical debuggers use this interface for debugging including the PowerPC processor GDB and the MicroBlaze GDB powerpc eabi gdb and mb gdb and the Software Development Kit SDK the EDK Eclipse based software tool In either case the debugger connects to XMD running on the same computer or on a remote computer on the network XMD reads Xilinx Microprocessor Project the XMP system file to gather information about the hardware system on which the program is debugged The information is used to perform memory range tests determine MicroBlaze to Microprocessor Debug Module MDM connectivity for faster download speeds and perform other system actions This chapter contains the following sections e Additional Resources e XMD Usage e XMD Command Reference e Connect Command Options e XMD Internal Tcl Commands Figure 9 1 page 152 shows the XMD targets Embedded System Tools Reference Manual www xilinx com 151 UG111 EDK 11 3 1 7 XILINX Additional Resources GDB and Platform Studio SDK Manual debugger TC
311. rPC processor If there are two PowerPC processors in your system you cannot chain them and the JTAG ports to each processor should be brought out to use FPGA I O pins Refer to the PowerPC 405 Processor Block Reference Guide and the PowerPC 440 Processor Block Reference Guide for more information about this debug setup A link to the document is supplied in the Additional Resources on page 152 Embedded System Tools Reference Manual www xilinx com 171 UG111 EDK 11 3 1 7 XILINX Connect Command Options The following figure illustrates the PowerPC processor target XMD JTAG FPGA JTAG PPC l l I PowerPC JTAG signals I l I UG111 13 02 072407 Figure 9 2 PowerPC Processor Target Example Debug Sessions Example Using a PowerPC 405 Processor Target The following example demonstrates a simple debug session with a PowerPC 405 processor target Basic XMD based commands are used after connecting to the PowerPC processor target using the connect ppc hw command At the end of the session powerpc eabi gdb is connected to XMD using the GDB remote target Refer to Chapter 10 GNU Debugger GDB for more information about connecting GDB to XMD XMD connect ppc hw JTAG chain configuration Device ID Code IR Length Part Name 1 0a001093 8 System ACE 2 5059093 16 XCF32P 3 01e58093 10 XC4VFX12 4 49608093 8 xc95144x1 PowerPC405 Processor Configuration poo s AAA A AA 0x20011430 User IS A 0x00000000 No of PC
312. rch header files in the following order 1 Directories are passed to the compiler with the I directory name option 2 The compilers search the following header files a SXILINX EDK gnu processor platform lib gcc processor 4 1 1 i nclude b SXILINX_EDK gnu lt processor gt platform lt processor 1ib gt include Embedded System Tools Reference Manual www xilinx com 119 UG111 EDK 11 3 1 XILINX Common Compiler Usage and Options Linker Options Linker options are as follows defsym _STACK_SIZE value The total memory allocated for the stack can be modified using this linker option The variable _STACK_SIZEis the total space allocated for the stack The STACK SIZE variable is given the default value of 100 words or 400 bytes If your program is expected to need more than 400 bytes for stack and heap combined it is recommended that you increase the value of STACK SIZE using this option The value is in bytes In certain cases a program might need a bigger stack If the stack size required by the program is greater than the stack size available the program tries to write in other incorrect sections of the program leading to incorrect execution of the code Note A minimum stack size of 16 bytes 0x0010 is required for programs linked with the Xilinx provided C runtime CRT files defsym HEAP SIZE value The total memory allocated for the heap can be controlled by the value given to the variable HEAP
313. rd The Debug Configuration wizard automates hardware and software platform debug configuration tasks common to most designs You can instantiate a ChipScope core to monitor the Processor Local Bus PLB or any other system level signals In addition you can configure the parameters of an existing ChipScope core for hardware debugging You can also provide Joint Team Action Group JTAG based virtual input and output To configure the software for debugging you can set the processor debug parameters When co debugging is enabled for a ChipScope core you can set up mutual triggering between the software debugger and the hardware signals The JTAG interface can be configured to transport UART signals to the Xilinx Microprocessor Debugger XMD For detailed information on using the features provided in the Debug Configuration wizard see the Xilinx Platform Studio Help Simulation Model Generator Simgen Software The Simulation Platform Generation tool Simgen generates and configures various simulation models for the hardware To generate a behavioral model Simgen takes an MHS file as its primary design input For generating structural or timing models Simgen takes its primary design input from the post synthesis or post place and route design database respectively Simgen also reads the embedded application executable ELF file for each processor to initialize on chip memory thus allowing the modeled processor s to execute their
314. reates an index for an archive file and adds this index to the archive file itself This allows the linker to speed up the process of linking to the library represented by the archive mb readelf This program displays information about an Executable Linked Format ELF file mb size This program lists the size of each section in the object file This is useful to determine the static memory requirements for utilities and data mb strings This is a useful program for determining the contents of binary files It lists the strings of printable characters in an object file mb strip This program removes all symbols from object files It can be used to reduce the size of the file and to prevent others from viewing the symbolic information in the file Other Programs and Files The following Tcl and Tk shells are invoked by various front end programs e cygitclsh30 e cygitkwish30 e cygtclsh80 e cygwish8s0 e tix4180 Embedded System Tools Reference Manual www xilinx com 235 UG111 EDK 11 3 1 XILINX Appendix A GNU Utilities 236 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 gt XILINX Appendix B Interrupt Management This appendix describes how to setup interrupts in a Xilinx embedded hardware system Also this appendix describes the software flow of control during interrupts and the software APIs for managing interrupts To benefit from this description you need to have a
315. reset or processor reset The processor starts running 3 After processor is stopped at reset location remove the breakpoint Embedded System Tools Reference Manual www xilinx com 163 UG111 EDK 11 3 1 XILINX 164 XMD User Commands Recommended XMD Flows The following are the recommended steps in XMD for debugging a program and debugging programs in a multi processor environment and running a program in a debug session Debugging a Program To debug a program 1 Pe p m 9o ves us Connect to the processor Download the ELF file Set the required breakpoints and watchpoints Start the processor execution using the con command or step through the program using the stp command Use the state command to check the processor status Use stop command to stop the processor if needed When the processor is stopped read and write registers and memory To re run the program use the run command Debugging Programs in a Multi processor Environment For debugging programs in a multi processor environment 1 2 10 11 12 13 14 15 16 Connect to processorl Use the debugconfig command to configure the reset behavior which depends on your system architecture Refer to the Configure Debug Session on page 189 Download the ELF file Set the required breakpoints and watchpoints Start the processor execution using the con command or step through the program using the stp command Connect
316. rget The XMD simulator is a cycle accurate ISS of the MicroBlaze system which presents the simulated MicroBlaze system state to GDB 198 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 10 GNU Debugger GDB XILINX Hardware Target With the hardware target XMD communicates with Microprocessor Debug Module mdm debug core or an xMDSTUB program running on a hardware board through the serial cable or JTAG cable and presents the running MicroBlaze system state to GDB For more information about XMD refer to Chapter 9 Xilinx Microprocessor Debugger XMD Compiling for Debugging on MicroBlaze Targets To debug a program you must generate debugging information when you compile the program This debugging information is stored in the object file it describes the data type of each variable or function and the correspondence between source line numbers and addresses in the executable code The mb gcc compiler for the Xilinx MicroBlaze soft processor includes this information when the appropriate modifier is specified The g option in mb gcc allows you to perform debugging at the source level The debugger mb gcc adds appropriate information to the executable file which helps in debugging the code The debugger mb gdb provides debugging at source assembly and mixed source and assembly Note While initially verifying the functional correctness of a C program do not use any mb gcc optimization o
317. ripheral Definition MPD files MPD files are required to create IP peripherals that are compliant with the Embedded Development Kit EDK The Create and Import Peripheral CIP wizard in the Xilinx Platform Studio XPS interface supports features provided by the PsfUtility for MPD file creation recommended This chapter contains the following sections Tool Options MPD Creation Process Overview Use Models for Automatic MPD Creation DRC Checks in PsfUtility Conventions for Defining HDL Peripherals Embedded System Tools Reference Manual www xilinx com 29 UG111 EDK 11 3 1 7 XILINX Tool Options Tool Options Table 2 1 PsfUtility Syntax Options Option Command Description Single IP MHS deploy core Generate MHS Template that instantiates a single peripheral template corename Suboptions are lt coreversion gt lp lt Library_Path gt Add one or more additional IP library search paths o outfile Specify output filename default is stdout Help h help Displays the usage menu then exits HDL file to MPD hdl2mpd hdlfile Generate MPD from the VHDL Ver src prj file Suboptions are lang ver vhdl Specify language top design Specify top level entity or module name bus opb p1b 2 plbv46 dcr lmb fs1 m s ms mb busif name Specify one or more bus interfaces for the peripheral p2pbus busif name bus std target initi
318. ript e Generating ACE Files e Related Information Assumptions This chapter assumes that you e Are familiar with debugging programs using XMD and with using XMD commands e Are familiar with general hardware and software system models in EDK e Have a basic understanding of Tcl scripts Tool Requirements Generating an ACE file requires the following tools e agenace tcl file e XMD e iMPACT from ISE Embedded System Tools Reference Manual www xilinx com 205 UG111 EDK 11 3 1 7 XILINX GenACE Features GenACE Features GenACE e Supports PowerPC 405 and 440 processor and the MicroBlaze processor with MDM targets e Generates ACE files from hardware Bitstream and software ELF and data files e Initializes external memories on PowerPC 405 and 440 processors and MicroBlaze systems e Supports multi processor systems e Supports single and multiple FPGA device systems GenACE Model System ACE CF is a two chip solution that requires the System ACE CF controller and either a CompactFlash card or one inch Microdrive disk drive technology as the storage medium System ACE CF configures devices using Boundary Scan JTAG instructions and a Boundary Scan Chain The generated System ACE files support the System ACE CF family of configuration solutions The System ACE file is generated from a Serial Vector Format SVF file which is a text file that contains both programming instructions and c
319. rs or they can perform other tasks The Tcl files that are used during the hardware platform generation are present in the individual cores directory along with the MPD files For Xilinx supplied cores the Tcl files are in the lt EDK install area hw XilinxProcessorIPLib pcores corename data directory Tcl Procedures Called During Hardware Platform Generation 284 Platgen and many EDK batch tools such as Libgen Simgen and Bitinit run a few predefined Tcl procedures related to each IP to perform DRCs and to compute values of certain parameters on the IP For information on the Tcl file for a given IP see the Platform Format Specification Reference Manual A link to the document is supplied in Additional Resources page 255 This section lists the Tcl procedures and describes how they can be called for user IP Tcl procedures can be classified based on e The action performed in that Tcl procedure DRC These procedures perform DRCs on the system but do not modify the state of the system itself The return code provided by these procedures is captured by Platgen Hence if there is any error status returned by a DRC procedure Platgen captures the error and stops execution at an appropriate time UPDATE These procedures assume the system to be in a correct state and query the design data structure using Tcl APIs to compute the values of certain parameters The tool uses the string these procedures return to update the de
320. rt dcrAck out std logic Intc dcrAck out std logic Memcon dcrAck out std logic Busl1 timer dcrAck out std logic Busl1 timer dcrDBus out std logic vector 0 to C BI DCR DWIDTH 1 Bus2 timer dcrAck out std logic Bus2 timer dcrDBus out std logic vector 0 to C BI DCR DWIDTH 1 DCR Slave Inputs For interconnection to the DCR all slaves must provide the following inputs BI nDCR ABus in std logic vector 0 to C BI DCR AWIDTH 1 BI nDCR DBus in std logic vector 0 to C BI DCR DWIDTH 1 BI nDCR Read in std logic BI nDCR Write in std logic Examples DCR DBus in std logic vector 0 to C BI DCR DWIDTH 1 Bus1_DCR_DBus in std logic vector 0 to C BI DCR DWIDTH 1 Slave FSL Ports The following table contains the required Slave FSL port naming conventions Table 2 6 Slave FSL Port Naming Conventions nFSL or A meaningful name or acronym for the slave I O The last five characters of nFSL S nFSL S must contain the string FSL S upper lower or mixed case BI A bus identifier Optional for peripherals with a single slave FSL port and required for peripherals with multiple slave FSL ports Br must rot contain the string FSL_S upper lower or mixed case For peripherals with multiple slave FSL ports the BI strings must be unique for each bus interface FSL Slave Outputs For interconnection to the FS
321. s Option Description ppc Connects to PowerPC processor mb Connects to MicroBlaze processor mdm Connects to MDM peripheral Connection Type Connection method target dependent Options Connection options The following sections describe connect options for different targets PowerPC Processor Targets Xilinx Virtex devices can contain one or two PowerPC 405 and 440 processor cores XMD can connect to these PowerPC processor targets over a JTAG connection on the board XMD also communicates over a TCP socket interface to an IBM PowerPC 405 Processor Instruction Set Simulator ISS Use the connect ppc command to connect to the PowerPC processor target and start a remote GDB server When XMD is connected to the PowerPC processor target powerpc eabi gdb or SDK can connect to the processor target through XMD and debugging can proceed Note XMD does not support Virtual Addressing Debugging is only supported for Programs running in Real Mode PowerPC Processor Hardware Connection When connecting to a PowerPC processor hardware target XMD detects the JTAG chain automatically and the PowerPC processor type and processors in the system and connects to the first processor You can override or provide information using the following options Usage connect ppc hw cable JTAG Cable options configdevice JTAG chain options gt debugdevice PowerPC options gt 168 www xilinx com Embedded
322. s Bus Functional Simulation Methods Getting and Installing the Platform Studio BFM Package Using the Platform Studio BFM Package Note BFM simulation can be run with ModelSim only Introduction Bus Functional Simulation provides the ability to generate bus stimulus and thereby simplifies the verification of hardware components that attach to a bus Bus Functional Simulation circumvents the drawbacks to the two typical validation methods which are Creating a test bench This is time consuming because it involves describing the connections and test vectors for all combinations of bus transactions Creating a larger system with other known good components that create or respond to bus transactions This is time consuming because it requires that you describe the established connections to the device under test program the added components to generate the bus transactions to which the device will respond and potentially respond to bus transactions that the device is generating Such a system usually involves creating and compiling code storing that code in memory for the components to read and generating the correct bus transactions Bus Functional Simulation Basics Bus Functional Simulation usually involves the following components A Bus Functional Model A Bus Functional Language A Bus Functional Compiler Embedded System Tools Reference Manual www xilinx com 69 UG111 EDK 11 3 1 Chapter 5 Bus Functional Model
323. s e Memory Initialization e Test Benches e Simulating Your Design e Restrictions Simgen Overview Simgen creates and configures various VHDL and Verilog simulation models for a specified hardware Simgen takes as the input file the Microprocessor Hardware Specification MHS file which describes the instantiations and connections of hardware components Simgen is also capable of creating scripts for a specified vendor simulation tool The scripts compile the generated simulation models The hardware component is defined by the MHS file Refer to the Microprocessor Hardware Specification MHS chapter in the Platform Specification Format Reference Manual for more information The Additional Resources page 85 section contains a link to the document web site For more information about simulation basics and for discussions of behavioral structural and timing simulation methods refer to the Platform Studio Online Help Additional Resources e Platform Specification Format Reference Manual http www xilinx com ise embedded edk docs htm e Command Line Tools User Guide and ISE Synthesis and Simulation Design User Guide http www xilinx com support software manuals htm Embedded System Tools Reference Manual www xilinx com 85 UG111 EDK 11 3 1 XILINX Simulation Libraries Simulation Libraries EDK simulation netlists use low level hardware primitives available in Xilinx FPGAs Xilin
324. s 4 bytes of address range In the example shown in Example Debug Session for PowerPC Processor ISS Target page 178 the address mappings are DCR Address Mapped Address 0x0 0x78020000 0x1 0x78020004 0x2 0x78020008 0x10 0x78020040 Advanced PowerPC Processor Debugging Tips Support for Running Programs from ISOCM and ICACHE There are restrictions on debugging programs from PowerPC 405 processor ISOCM memory and instruction caches ICACHEs One such restriction is that you cannot use software breakpoints In such cases XMD can set hardware breakpoints automatically if the address ranges for the ISOCM or ICACHEs are provided as options to the connect command in XMD In this case of ICACHE this is only necessary if you try to run programs completely from the ICACHE by locking its contents in ICACHE For more information refer to the Xilinx Platform Studio Help The special features of the PowerPC processor can be accessed from XMD by specifying the appropriate options to the connect command in the XMD console Debugging Setup for Third Party Debug Tools To use third party debug tools such as Wind River SingleStep and Green Hills Multi Xilinx recommends that you bring the JTAG signals of the PowerPC processor TCK TMS TDI and TDO out of the FPGA as User IO to appropriate debug connectors on the hardware board You must also bring the DBGC405DEBUGHALT and C405JTGTDOEN signals out of the FPGA as User IO In the ca
325. s Reference Manual www xilinx com 95 UG111 EDK 11 3 1 7 XILINX Test Benches Reset Generator for sys_reset process begin Sys reset lt 0 wait for sys reset LENGTH Sys reset not sys reset wait end process START USER CODE Do not remove this line User Put your stimulus here Code in this section will not be overwritten END USER CODE Do not remove this line Lj end architecture STRUCTUR configuration system tb conf of system tb is for STRUCTURE for all system use configuration work system conf end for end for end system tb conf You can add your own VHDL code between the lines tagged BEGIN USER CODE and END USER CODE The code between these lines is maintained if simulation files are created again Any code outside these lines will be lost if a new test bench is created Verilog Test Bench Example timescale 1 ns 10 ps uselib lib unisims ver module system tb E real sys clk PERIOD 10 real sys clk PHASE 2 5 real sys reset LENGTH 160 Internal signals reg 0 3 leds reg rx reg Sys clk reg sys reset reg tx system dut SysS clk sys clk Sys reset sys reset EX re tx tx leds leds 96 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 6 Simulation Model Generator Simgen XILINX Data initialization system_con
326. s a Xilinx System ACE configuration file based on the FPGA configuration bitstream and software executable to be stored in a compact flash device in a production system Flash Memory Programmer Allows you to use your target processor to program on board Common Flash Interface CFI compliant parallel flash devices with software and data Format Revision Tool and Version Management Wizard Updates the project files to the latest format The Version Management wizard helps migrate IPs and drivers created with an earlier EDK release to the latest version Xilinx Platform Studio XPS XPS provides an integrated environment for creating embedded processor systems based on MicroBlaze and PowerPC processors XPS also provides an editor and a project management interface to create and edit source code XPS offers customization of tool flow configuration options and provides a graphical system editor for connection of processors peripherals and buses There is also a batch mode invocation of XPS available From XPS you can run all embedded system tools needed to process hardware system components You can also perform system verification within the XPS environment XPS offers the following features e Ability to add processor and peripheral cores edit core parameters and make bus and signal connections to generate an MHS file e Ability to generate and modify the MSS file e Support for tools described in Table 1
327. s a handle to the merged IP instance pointing to a processor instance This returned list includes slaves that are not directly connected to the processor but are accessed across a bus to bus bridge for example opb2plb bridge The input handle must be an IP instance handle to a processor instance which can be obtained from the merged MHS only not from the original MHS xget hw subproperty handle property handle subprop name Description Arguments Returns the handle to a subproperty associated with the specified property handle property handle is a handle to one of the following PARAMETER PORT BUS INTERFACE IO INTERFACE Or OPTION subprop name is the name of the subproperty whose handle is required For a list of sub properties please refer to Microprocessor Peripheral Definition Microprocessor Peripheral Definition MPD in the Platform Specification Format Reference Manual and Additional Keywords in the Merged Hardware Datastructure on page 290 xget hw subproperty value property handle subprop name Description Arguments Returns the value of a specified subproperty property handle is one of the following PARAMETER PORT BUS INTERFACE IO INTERFACE Or OPTION lt subprop_name gt is the name of the subproperty whose value is required For a list of sub properties please refer to Microprocessor Peripheral Definition MPD in the Platform
328. s are assumed to be in an unprotected state The flash programming stub will not attempt to unlock or initialize the flash and will report an error if the flash hardware is not in a ready and unlocked state Note The flash programmer does not currently support dual die flash devices which require every flash command to be offset with a Device Base Address DBA value Examples of such dual die devices are the 512 Mbit density devices in the Intel StrataFlash Embedded Memory P30 family of flash memory Flash Programmer Performance The following factors determine the speed at which an image can be programmed e The flash programmer communicates with the in system programming stub using JTAG Consequently the inherent bandwidth of the JTAG cable is in most cases the bottleneck in programming flash e When it is available on the system it is best to use external memory as scratch memory This will allow the debugger to download the flash image data without having to stream it in multiple iterations e Itis desirable to implement the fastest configuration possible when using the MicroBlaze soft processor You can improve programming speed by turning on features such as the barrel shifter and multiplier and by using the fast download feature on MicroBlaze Embedded System Tools Reference Manual www xilinx com 219 UG111 EDK 11 3 1 7 XILINX Customizing Flash Programming Customizing Flash Programming Hardware incompatibil
329. s compliance of the device under test 70 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Bus Functional Model Use Cases Monitor BFM Slave Device Master BFM Under Test X10847 Figure 5 1 Slave IP Verification Use Case The following figure shows an example in which a slave BFM responds to bus transactions that the device under test generates The monitor BFM reports any errors regarding the bus compliance of the device under test Monitor BFM Master Device Slave BFM Arbiter X10848 Figure 5 2 Master IP Verification Use Case Under Test Speed Up Simulation When verifying a large system design it can be time consuming to simulate the internal details of each IP component that attaches to a bus There are certain complex pieces of IP that take a long time to simulate and could be replaced by a Bus Functional Model especially when the internal details of the IP are not of interest Additionally some IP components are not easy to program to generate the desired bus transactions The following figure shows how two different IP components that are bus masters have been replaced by BFM master modules These modules are simple to program and can provide a shorter simulation time because no internal details are modeled Embedded System Tools Reference Manual www xilinx com 71 UG111 EDK 11 3 1 Chapter 5 Bus Functional Model Simulation XILINX Monitor BFM
330. s finished The following actions are typically performed by end files e Invoke language cleanup functions such as C destructors e Clean up the hardware subsystem For example if the program is being profiled clean up the profiling subsystem Table 8 12 Register initialization in the C Runtime files Register Value Description r1 _stack 8 Stack pointer register initializes the bottom of the allocated stack offset by 16 bytes The 16 bytes can be used for passing in arguments r2 _SDA2_BASE _SDA2_BASE_ is the read only small data anchor address r13 SDA BASE SDA BASE is the read write small data anchor address Other Undefined Other registers do not have defined values registers The following subsection describes the initialization files This information is for advanced users who want to change or understand the startup code of their application 146 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Initialization File Description The PowerPC processor compiler uses four different CRT files xil crt0 o xil pgcrt0 o xil sim crt0 o and xil sim pgcrt0 o The various CRT files perform the following steps with exceptions as described 1 Invoke the function cpu init This function is provided by the board support package library and contains processor architecture specific initialization Clear the bss memory re
331. s one of three UART operations on the MDM UART if it is enabled This command is valid only for the MDM target xuart r reads byte from the MDM UART xuart w data writes byte onto the MDM UART xuart s reads the status of MDM UART xverbose Toggles verbose mode on and off Dumps debugging information from XMD Embedded System Tools Reference Manual www xilinx com 195 UG111 EDK 11 3 1 XILINX XMD Internal Tcl Commands 196 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 10 GNU Debugger GDB This chapter describes the general usage of the Xilinx GNU debugger GDB for the MicroBlaze processor and the PowerPC 405 and 440 processors This chapter contains the following sections e Overview e Additional Resources e MicroBlaze GDB Targets e PowerPC 405 Targets e PowerPC 440 Targets e Console Mode e GDB Command Reference Overview GDB is a powerful and flexible tool that provides a unified interface for debugging and verifying MicroBlaze and PowerPC 405 and 440 systems during various development phases It uses Xilinx Microprocessor Debugger XMD as the underlying engine to communicate to processor targets Tool Usage MicroBlaze GDB usage mb gdb lt options gt executable file PowerPC GDB usage powerpc eabi gdb lt options gt executable file Embedded System Tools Reference Manual www xilin
332. s with initial values data Static and global variables with initial values Initialized to zero by the boot code Sdata Small static and global variables with initial values Sbss2 Small read only static and global variables without initial values Initialized to zero by boot code Sbss Small static and global variable without initial values Initialized to zero by the boot code bss Static and global variables without initial values Initialized to zero by the boot code heap Section of memory defined for the heap Stack Section of memory defined for the stack www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX Tips for Writing or Customizing Linker Scripts The following points must be kept in mind when writing or customizing your own linker script Ensure that the different vector sections are assigned to the appropriate memories as defined by the MicroBlaze hardware Allocate space in the bss section for stack and heap Set the _stack variable to the location after STACK SIZE locations of this area and the heap start variable to the next location after the STACK SIZE location Because the stack and heap need not be initialized for hardware as well as simulation define the bss end variable after the bss and COMMON definitions Note however that the bss section boundary does not include either stack or heap Ensure that the variables S
333. scribes the options available in the genace tcl script 206 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 12 System ACE File Generator GenACE The Genace tcl Script Syntax xmd tcl genace tcl XILINX ace ACE file board board type data data files load address elf elf files hw bitstream file jprog true false opt genace options file target target type ppc hw mdm Table 12 1 genace tcl Script Command Options Options ace ACE file Default none Description The output ACE file The file prefix should not match any of input files bitstream elf data files prefix board board type supported board list none This identifies the JTAG chain on the board Devices IR length Debug device and so on The options are given with respect to the System ACE controller The script contains the options for some pre defined boards You must specify the configdevice and debugdevice option in the OPT file Refer to the genace opt file for details e For Supported board type refer to Supported Target Boards in Genace tcl Script on page 210 data lt data_file gt lt load_address gt none List of data binary file and its load address The load address can be in decimal or hex format 0x prefix needed If an SVF file is specified it is used elf list of Elf Files non
334. se of multiple PowerPC processors Xilinx recommends that you chain the PowerPC processor JTAG signals inside the FPGA For more information about connecting the PowerPC processor JTAG port to FPGA User IO refer to the JTAG port sections of the PowerPC 405 Processor Block Reference Guide and the PowerPC 440 Processor Block Reference Guide A link to the document is supplied in the Additional Resources on page 152 Note DO NOT use the JTAGPowerPC module while bringing the PowerPC processor JTAG signals out as User IO www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX MicroBlaze Processor Target XMD can connect through JTAG to one or more MicroBlaze processors using the MDM peripheral XMD can communicate with a ROM monitor such as XMDStub through a JTAG or serial interface You can also debug programs using built in cycle accurate MicroBlaze ISS The following sections describe the options for these targets MicroBlaze MDM Hardware Target Use the command connect mb mdm to connect to the MDM target and start the remote GDB server The MDM target supports non intrusive debugging using hardware breakpoints and hardware single step without the need for a ROM monitor Ip library path Library Name Figure 9 3 MicroBlaze MDM Target drivers SW Services X10066 When no option is specified to the connect mb mdm XMD detects the JTAG ca
335. sign with the Tel computed value e The stage during hardware platform creation at which they are invoked IPLEVEL These procedures are invoked early in processing performed within the tools These procedures assume that no design analysis has been performed and therefore none of the system level information is available www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Flow During Hardware Platform Generation XILINX SYSLEVEL These procedures are invoked later in processing when the tool has performed some system level analysis of the design and has updated certain parameters For a list of such parameters refer to the Reserved Parameters section of Chapter 2 Platform Specification Utility PsfUtility Also note that some parameters may be updated by Tcl procedures of IPs Such parameters are governed solely by IP Tcl and are therefore not listed in the MPD documentation Each Tcl procedure takes one argument The argument is a handle of a certain type in the data structure The handle type depends on the object type with which the Tcl procedure is associated Tcl procedures associated with parameters are provided with a handle to that parameter as an argument Tcl procedures associated with the IP itself are provided with a handle to a particular instance of the IP used in the design as an argument The following is a list of the Tcl procedures that can be call
336. simlib filename is the specified filename lt hdllang gt is vh 1 veri1og Example xadd hw hdl srcfile ipinst handle lib xps central dma vhd vhdl xadd hw ipinst busif ipinst handle busif name busif value Description Creates and adds a bus interface specified by busif name and busif value to the IP instance specified by the ipinst handle This API returns a handle to the newly created bus interface if successful and NULL otherwise Arguments ipinst handle is the handle to the IP instance to which the bus interface has to be added busif name is the name of the bus interface busif value is the value of the bus interface Example Connect the ILMB bus interface from MicroBlaze to the ilmb 0 bus xadd hw ipinst busif mb handle ILMB ilmb 0 Embedded System Tools Reference Manual www xilinx com 269 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface xadd_hw_ipinst lt mhs_handle gt lt inst_name gt lt ip_name gt lt hw_ver gt Description Adds a new MHS instance to the MHS specified by lt mhs_hand1e gt Returns a handle to the newly created instance if successful and NULL otherwise Arguments lt mhs_handle gt is the handle to the MHS in which this mhs instance has to be added lt inst_name gt is the instance name of the IP instance that needs to be added lt ip_name gt is the name of the IP that needs to be added lt hw_ver gt is the versi
337. software code during simulation Refer to Chapter 6 Simulation Model Generator Simgen for more information Development Kit SDK The SDK provides a development environment for software application projects SDK is based on the Eclipse open source standard SDK has the following features e Can be installed independent of ISE and XPS with a small disk footprint e Supports development of software applications on single processor or multi processor systems e Imports the XPS generated hardware platform definition e Supports development of software applications in a team environment e Supports source code revision control based on CVS e Has the ability to create and configure software platforms and Board Support Packages BSPs for third party OS e Provides off the shelf sample software projects to test the hardware and software functionality e Hasan easy GUI interface to generate linker scripts for software applications program FPGA devices and program parallel flash memory e Has feature rich C C code editor and compilation environment e Provides project management Embedded System Tools Reference Manual www xilinx com 25 UG111 EDK 11 3 1 Chapter 1 Embedded System and Tools Architecture Overview XILINX e Configures application builds and automates the make file generation e Supplies error navigation e Provides a well integrated environment for seamless debugging and profiling of embedded targets
338. ssignment or an adjustment to the linker script e When writing or customizing your own linker script Ensure that the boot section starts at OxFFFFFFFC Upon power up the PowerPC processor starts execution from the location OxFFFFFFFC The _end variable is defined after the boot0 section definition This section is a jump to the start of the boot0 section The jump is defined to be 24 bits hence the boot and boot0 sections should not be more than 24 bits apart On the PowerPC 440 processor the boot0 section has a fixed location of 0xFFFFFF00 Allocate space in the bss section for stack and heap Set the stack variable to the location after STACK SIZE locations of this area and the heap start variable to the next location after the STACK SIZE location Because the stack and heap need not be initialized for hardware as well as simulation define the bss end variable after the bss and COMMON definitions Note that the bss section boundary does not include either stack or heap Ensure that the variables SDATA START SDATA END SDATA2 START SDATA2 END SBSS2 START SBSS2 END bss start bss end Sbss start and sbss end are defined to the beginning and end of the sections sdata sdata2 sbss2 bss and sbss respectively For the PowerPC 405 processor ensure that the vectors section is aligned on a 64K boundary The PowerPC 440 processor does not require any special alignment on the vectors section
339. st be given to the compiler The libxil a is modified by the Library Generator tool Libgen to add driver and library routines Embedded System Tools Reference Manual www xilinx com 113 UG111 EDK 11 3 1 7 XILINX 114 Common Compiler Usage and Options Language Dialect The GCC compiler recognizes both C and C dialects and generates code accordingly By GCC convention it is possible to use either the GCC or the G compilers equivalently on a source file The compiler that you use and the extension of your source file determines the dialect used on the input and output files When using the GCC compiler the dialect of a program is always determined by the file extension as listed in Table 8 1 page 113 If a file extension shows that it is a C source file the language is set to C This means that if you have compile C code contained in a CC file even if you use the GCC compiler it automatically mangles function names The primary difference between GCC and G is that G automatically sets the default language dialect to C irrespective of the file extension and if linking automatically pulls in the C support libraries This means that even if you compile C code in a c file with the G compiler it will mangle names Name mangling is a concept unique to C and other languages that support overloading of symbols A function is said to be overloaded if the same function can perform different actions based on t
340. stem Tools Reference Manual UG111 EDK 11 3 1 Figure 9 2 PowerPC Processor ISS Target www xilinx com 177 XILINX Connect Command Options Usage connect ppc sim debugdevice proctype lt ppc440 ppc405 gt icf Configuration File ipcport IP lt port gt Table 9 12 PowerPC Processor ISS Options Option debugdevice proctype Description Specifies the options for PowerPC processor types configuration file ppc405 ppc405 PowerPC 405 processor The processor type defaults to ppc405 icf Uses the given ISS configuration file instead of the default configuration file You can customize the PowerPC ISS features such as cache size memory address map and memory latency ipcport port Specifies the IP address and debug port of a PowerPC processor ISS that you have started XMD does not spawn a ISS you must start the ISS Example Debug Session for PowerPC Processor ISS Target XMD connect ppc sim Instruction Set Simulator ISS PPC405 Version 1 9 1 76 c 1998 2005 IBM Corporation Waiting to connect to controlling interface port 6470 protocol tcp XMD Connected to PowerPC Sim Controling interface connected Connected to PowerPC target id 0 Starting GDB server for target id 0 at TCP port no 1234 XMD dow dhry2 elf XMD bps Oxffff09dO XMD con Processor started Type stop to stop processor RUNNING 178 ww
341. stem Tools Reference Manual UG111 EDK 11 3 1 Tcl Flow During Hardware Platform Generation XILINX DRC Procedure for the IP Before System Level Analysis You can use the OPTION IPLEVEL_DRC_PROC to specify the Tcl procedure that performs this DRC The procedure should be used to perform DRCs at IPLEVEL for example consistency between two parameter values The DRCs performed here should be independent of how that IP has been used in the system MHS and should only use parameter bus interface and port settings used on that IP The input handle is a handle to an instance of the IP MPD Snippet OPTION IPLEVEL DRC PROC iplevel drc BUS INTERFACE BUS SPLB BUS STD PLB BUS TYPE SLAVE PORT MYPORT DIR I Tcl snippet proc iplevel drc ipinst handle set splb handle xget hw busif handle ipinst handle SPLB set splb conn xget hw value splb handle set myport handle xget hw port handle MYPORT set myport conn xget hw value myport handle if splb conn myport conn error Either busif SPLB or port MYPORT must be connected in the design return 1 else return 0 UPDATE Procedure for a Parameter After System Level Analysis You can use the parameter subproperty SYSLEVEL_UPDATE_VALUE_PROC to specify the Tel procedure that computes the parameter value based on other parameters of the same IP The input handle is a handle to the parameter object of a part
342. stem tools suite with which you can develop your embedded processor hardware e The Software Development Kit SDK based on the Eclipse open source framework which you can use to develop your embedded software application SDK is also available as a standalone program e Embedded processing Intellectual Property IP cores including processors and peripherals EDK is a component of the Integrated Software Environment ISE a Xilinx development system product that is required to implement designs into Xilinx programmable logic devices EDK is installed when you select it as an option during the ISE install SDK can be installed as a separate executable without installing ISE or EDK While the EDK environment supports creating and implementing designs the recommended flow is to begin with an ISE project then add an embedded processor source to the ISE project EDK depends on ISE components to start synthesize the microprocessor hardware design to map that design to an FPGA target and to generate and download the bitstream For information about ISE refer to the ISE software documentation For links to ISE documentation and other useful information see Additional Resources page 4 Embedded System Tools Reference Manual www xilinx com 17 UG111 EDK 11 3 1 Chapter 1 Embedded System and Tools Architecture Overview g XILINX Additional Resources e Platform Specification Format Reference Manual OS and Libraries Document
343. t does a series of actions that are appropriate for the given peripheral and the cause for the interrupt The handleris also responsible for acknowledging the interrupt at the interrupting peripheral Once the interrupt handler is done it returns back and the interrupt stack gets unwound all the way back to the software platform level interrupt handler The platform level interrupt handler restores the registers it saved on the stack and returns control back to the Program Counter PC location where the interrupt occurred The return instruction also enables interrupts again on the MicroBlaze processor The application resumes normal execution at this point It is recommended that interrupt handlers be kept to a short duration and the bulk of the work be left to the application to handle This prevents long lockouts of other possibly higher priority interrupts and is considered good system design The following figures illustrate the interrupt flow for MicroBlaze system without and with an interrupt controller User Program microblaze_interrupt_handler c interrupt handler INTR 0x000 0008 Branch to OS INTR handler user or peripheral interrupt handler function 0x000 00 10 Lookup the interrupt handler registered with the OS and jump to it 0x000 00 18 0x000 00 20 MB InterruptVector Table User or peripheral interrupt handler registered directly with h the OS layer X
344. t iar och n Adding a Software Applicati0M oooooooccocccncoccocccccc Deleting a Software Application 0 00 0000s Adding a Program File to a Software Application Deleting a Program File from a Software Application Archiving Your Project FileS ooooooocoococcoccocco co Setting Options on a Software Application Settings on Special Software Applications Restrictions vv civic ra a ee es MSS Changes oce terere a des XMP Cian OS Tr Chapter 5 Bus Functional Model Simulation Introduction 0 0 00 ccc cc cece cee hh hh Bus Functional Simulation Basics 00 e eee eee eee Bus Functional Models BFMs 0 eee eee eee eee ene Bus Functional Language BFL 0666s Bus Functional Compiler BFC 0 00000 c eee eee eee Bus Functional Model Use Cases 0 00 00 ccc sees IP Verifications s coectetuer Ree tC CEPR DER Leg Speed p Simulation isa ud e RR hh Rat i ak eR da Bus Functional Simulation Methods s suse IBM CoreConnect Toolkit eeeeeeeeee RR Platform Studio BFM Package 0 00 e eee eee eee eee Getting and Installing the Platform Studio BFM Package Using the Platform Studio BFM Package OPB BFM Component Instantiation 6 PLB BFM Compo
345. t information associated with that handle or you can get other associated handles Data Structure Creation EDK tools provide access to two basic types of run time information 256 e The original design and library datafile data structure The original data structure provides access only to the information present in various data files You can get a handle to such files as the MHS MSS MPD MDD and MLD These handles allow you to query the contents of the files with which they are associated e The merged data structure When EDK tools run the information in the design files MHS or MSS is combined with the corresponding information from library files MPD or MDD MLD to create merged data structures hardware merged datastructure also referred to as the hardware merged object and software merged datastructure also referred to as the software merged object During the process of creating the merged data structure the tools also analyze various design characteristics such as connectivity or address mapping and that information is also stored in the merged data structures A merged data structure provides an easy way to access this analyzed information For example an instance of an IP in the MHS file is merged with its corresponding MPD Using the merged instances complete information can be obtained from one handle it is not necessary to access the IP instance and MPD handles separately MHS Ce Merged DataStruct
346. t use code that relies on global variables being initialized to zero or that your simulation platform performs the zeroing of memory mxl stack check With this option you can check whether the stack overflows during the execution of the program The compiler inserts code in the prologue of the every function comparing the stack pointer value with the available memory If the stack pointer exceeds the available free memory the program jumps to a the subroutine stack overflow exit This subroutine sets the value of the variable stack overflow error to 1 You can override the standard stack overflow handler by providing the function Stack overflow exit in the source code which acts as the stack overflow handler Application Execution Modes xl mode executable This is the default mode used for compiling programs with mb gcc This option need not be provided on the command line for mb gcc This uses the startup file crto o xl mode zzmdstub The Xilinx Microprocessor Debugger XMD allows debugging of applications in a software intrusive manner This mode is known as XMDSTUB mode Compile programs being debugged in such a manner with this switch In such programs the address locations 0x0 to 0x800 are reserved for use by XMDSTUB Using x1 mode xmdstub has two effects e The start address of your program is set to 0x800 You can change this address by overriding the TEXT START ADDR in the linker script or through linker options
347. ta bus 218 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 13 Flash Memory Programming XILINX The physical layout geometry information and other logical information such as command sets are determined using the CFI The flash programmer can be used on flash devices that use the CFI defined command sets only The CFI defined command sets are listed in the following table Table 13 2 CFI Defined Command Sets edd ID OEM Sponsor Interface Name 1 Intel Sharp Intel Sharp Extended Command Set 2 AMD Fujitsu AMD Fujitsu Standard Command Set 3 Intel Intel Standard Command Set 4 AMD Fujitsu AMD Fujitsu Extended Command Set By default the flash programmer supports only flash devices which have a sector map that matches what is stored in the CFI table Some flash vendors have top boot and bottom boot flash devices the same common CFI table is used for both The field that identifies the boot topology of the current device is not part of the CFI standard Consequently the flash programmer encounters issues with such flash devices Refer to Customizing Flash Programming on page 220 for more information about how to work around the boot topology identification field The following assumptions and behaviors apply to programming flash hardware e Flash hardware is assumed to be in a reset state when programming is attempted by the flash programming stub e Flash sector
348. te an SVF file for the first FPGA device The options file contains the following jprog target ppc_hw hw implementation download bit elf executablel elf ace fpgal ace board user configdevice devicenr 1 idcode 0x123e093 irlength 10 partname XC2VP4 configdevice devicenr 2 idcode 0x123e093 irlength 10 partname XC2VP4 debugdevice devicenr 1 cpunr 1 This generates the file pga1 svf 2 Generate an SVF file for the second FPGA device The options file contains the following jprog target ppc hw hw implementation download bit elf executable2 elf ace fpga2 ace board user configdevice devicenr 1 idcode 0x123e093 irlength 10 partname XC2VP4 configdevice devicenr 2 idcode 0x123e093 irlength 10 partname XC2VP4 debugdevice devicenr 2 cpunr 1 Note The change in Devicenr This generates the file pga2 svf 3 Concatenate the files in the following order fpgal svf and fpga2 svf to final system svf 4 Generate the ACE file by calling impact batch svf2ace scr Use the following SCR file svf2ace wtck d i final system svf o final system ace quit On some boards for example the ML561 the FPGA DONE pins are all connected together For these boards the FPGAs on the board must be configured with the hardware bitstream at the same time followed by software configuration The following are the steps to generate the ACE file for such an configuration This procedure uses an ML561 board as an example only
349. tem Usage xmd tcl genace tcl jprog target mdm hw implementation download bit elf executablel elf executable2 svf data image bin Oxfe000000 board m1507 ace system ace Preferred genace opt file jprog hw implementation download bit ace system ace board m1507 target mdm Embedded System Tools Reference Manual www xilinx com 209 UG111 EDK 11 3 1 7 XILINX The Genace tcl Script elf executablel elf executable2 svf data image bin 0xfe000000 Supported Target Boards in Genace tcl Script The Tcl script supports the following boards e ML401 Board type is m1401 This board has the following devices in the JTAG chain XCF32P gt XC4VLX25 gt XC95144XL e ML401 with V4LX25 ES Board type is m1401 es This board has the following devices in the JTAG chain XCF32P gt XC4VLX25 ES gt XC95144XL e M1402 Board type is m1402 This board has the following devices in the JTAG chain XCF32P gt XC4VSX35 gt XC95144XL e ML403 Board type is m1403 This board has the following devices in the JTAG chain XCF32P gt XC4VFX12 gt XC95144XL e ML405 Board type is m1405 This board has the following devices in the JTAG chain XCF32P gt XC4VFX20 gt XC95144XL e M1410 Board type is m1 410 This board has the following device in the JTAG chain XC4FX60 e M1411 Board type is m1411 This board has the following device in the JTAG chain XC4FX100 e ML501 Board type is m1
350. ter the handler is called Interrupt signal inputs are either edge or level signal consequently support for those inputs is required Edge driven interrupt signals require that the interrupt is acknowledged prior to the interrupt being serviced to prevent the loss of interrupts which are occurring close together Level driven interrupt input signals require the interrupt to be acknowledged after servicing the interrupt to ensure that the interrupt only generates a single interrupt condition Embedded System Tools Reference Manual UG 111 EDK 11 3 1 www xilinx com 243 XILINX Appendix B Interrupt Management API Descriptions int XIntc Initialize XIntc InstancePtr ul6 Deviceld Description Parameters Initializes a specific interrupt controller instance or driver All the fields of the XIntc structure and the internal vectoring tables are initialized All interrupt sources are disabled InstancePtris a pointer to the XIntc instance Deviceldis the unique id of the device controlled by this XIntc instance obtained from xparameters h Passing ina DeviceId associates the generic XIntc instance to a specific device as chosen by the caller or application developer int XIntc Connect XIntc InstancePtr u8 Id XInterruptHandler Handler void CallBackRef Description Parameters Makes the connection between the Id of the interrupt source and the associated handler that is to be run when the i
351. terrupt Setup Example 06 eee eee 247 Standalone Software API for PowerPC 405 and 440 Processors ooooooooo 249 PowerPC Processor Interrupt Setup Example 0 0 0 0 0 nrnna annn 251 Appendix C EDK Tcl Interface Introduction occ ec lc ee eee cea 255 Additional Resources 0 cc cee ccc RR Rn 255 Embedded System Tools Reference Manual www xilinx com UG111 EDK 11 3 1 15 EZ XILINX Understanding Handles ssis ssesssssi sisus e ear addo a doro 256 Data Structure Creation usus ee 256 Tel Command Usage civ divert ee e RR EROR E e e n 257 General Conventions liess hr es 257 Before You Begin viii RU E Eee HC ATH Ie Hee Pede Ped 257 EDK Hardware Tcl Commands usssssss ee 258 OOVCIVI Wind dada Lada eG be eL ORIG Riu E RR RA DECEM X ee ERR 258 Hardware Read Access APIs 0 00 c ccc cece RR RR Re 259 API Summary do eidem EP OCC p EU Ee It Cd t a oeil 259 Hardware API Descriptions c nn 259 Tel Example Procedures oy cci Le err Dre AAA PE COR RA 266 lcu UT 266 Example 2 ucc Se RR RP a m 267 Advanced Write Access APIS 0 0 00 c ccc ce eee cece es 268 Advance Write Access Hardware API Summary 2 0 0 c cece eee eee 268 Advance Write Access Hardware API Descriptions 269 Software Tcl Commands 00 cc ccc cece n 274 Software API Terminology Overview 0000 c cece cece cee ees 274 Software Read Access APIs
352. ters h Status XIntc Initialize amp sys intc XPAR XPS INTC 0 DEVICE ID if Status XST SUCCESS return XST_FAILURE Embedded System Tools Reference Manual www xilinx com 247 UG 111 EDK 11 3 1 XILINX Appendix B Interrupt Management Connect the application handler that will be called when an interrupt for the timer occurs 7 Status XIntc_Connect amp sys_intc XPAR XPS INTC 0 XPS TIMER 0 INTERRUPT INTR XInterruptHandler my timer handler void 0 if Status XST SUCCESS return XST_FAILURE Start the interrupt controller such that interrupts are enabled for all devices that cause interrupts EJ Status XIntc_Start amp sys_intc XIN REAL MODE if Status XST_SUCCESS return XST_FAILURE Enable the interrupt for the timer counter A XIntc Enable amp sys intc XPAR XPS INTC 0 XPS TIMER 0 INTERRUPT INTR Initialize the timer counter so that it s ready to use specify the device ID that is generated in xparameters h 2 Status XTmrCtr Initialize amp sys tmrctr XPAR XPS TIMER 0 DEVICE ID if Status XST SUCCESS return XST_FAILUR Lj Enable the interrupt of the timer counter so interrupts will occur and use auto reload mode such that the timer counter will reload itself automatically and continue repeatedly without this option it would expire once on
353. th bus outputs lt S1n gt A meaningful name or acronym for the slave output To avoid confusion between slave and bus outputs lt S1n gt must not contain the string OPB upper lower or mixed case nOPB A meaningful name or acronym for the slave input The last three characters of lt nOPB gt must contain the string OPB upper lower or mixed case BI A bus identifier Optional for peripherals with a single OPB port and required for peripherals with multiple OPB ports of any type BI must not contain the string OPB upper lower or mixed case For peripherals with multiple OPB ports of any type or mix of types the BI strings must be unique for each bus interface Note lf BI is present S1n and Mn are optional OPB Master Slave Outputs For interconnection to the OPB all master and slaves must provide the following outputs lt BI gt lt S1n gt _ABus out std_logic_vector 0 to C_ lt BI gt OPB_AWIDTH 1 BI Sin BE out std logic vector 0 to C BI OPB DWIDTH 8 1 lt BI gt lt Sln gt _busLock out std logic BI Sln request out std logic lt BI gt lt S1n gt _RNW out std logic BI Slin select out std logic lt BI gt lt S1n gt _segAddr out std logic lt BI gt lt S1n gt _DBus out std_logic_vector 0 to C_ lt BI gt OPB_DWIDTH 1 lt BI gt lt S1n gt _errAck out std logic BI Sln retry out std logic lt BI gt lt S1n gt _t
354. that is associated to the handle Arguments handle is of specified type option name is a specified software option Example Get the value of a drc option in the MLD file of an OS instance that is assigned standalone drc The value is obtained from the os handle set drc value xget sw option value os handle xget sw os handle mss handie os name Description Returns the handle to the OS with the os name associated with the specified mss handle Arguments os name is the name of the required OS mss handle is the handle to the MSS file Example Set os handle xget sw os handle mss handle os name Embedded System Tools Reference Manual www xilinx com 281 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface xget_sw_parent_handle lt handle gt Description Returns the handle for the parent of the specified handle Arguments handle is of specified type The parent handle type depends on the type of the handle specified If the specified handle is a merged handle the parent obtained through this API will also be a merged handle The option per handle type are e PARAMETER the parent is one of the following MDD MLD processor instance driver instance OS instance library instance or the merged processor instance merged driver instance merged OS instance or merged library instance object e ARRAY the parent is one of the following MDD MLD driver instance process
355. the installation 4 The script downloads the flash programmer to the processor and communicates with the flash programmer through mailboxes in memory In other words it writes parameters to the memory locations corresponding to variables in the flash programmer address space and lets the flash programmer execute 5 The script waits for the flash programmer to invoke a callback function at the end of each operation and stops the application at the callback function by setting a breakpoint at the beginning of the function When the flash programmer stops the host Tcl processes the results and continues with more commands as required 6 While running the flash programmer erases only as many flash blocks as required in which to store the image 7 The flashwriter allocates a streaming buffer based on the amount of scratch pad memory available and iteratively stream programs the image file The stream buffer is allocated within the flashwriter If there is enough scratch memory to hold the entire image the programming can be completed quickly 8 When the programming is done the flash programmer Tel sends an exit command to the flash programmer and terminates the XMD session The following is an example set of steps to perform for a custom flow 1 Copy flashwriter tcl from edk install data xmd flashwriter tcl to your EDK project folder 2 Create a sw services directory within your EDK project if it does not exist 3 Copyt
356. the current target targets system sytem id targets system 1 terminal terminal jtag uart server port number terminal terminal jtag uart server 4321 JTAG based hyperterminal to communicate with mdm UART interface The UART interface should be enabled in the mdm Ifthe jtag uart server option is specified a TCP server is opened at port no Use any hyperterminal utility to communicate with opb mdm UART interface over TCP sockets The port number default value is 4321 tracestart tracestart xpc trace filename function name func trace filename tracestart pctrace txt tracestart pctrace txt function name fntrace txt tracestart Starts collecting instruction and function trace information to lt filename gt e Trace collection can be stopped and started any time the program runs e filename is specified on first tracestart only e pc trace filename defaults to isstrace out e func trace filename defaults to fntrace out Note This is supported on ISS targets only tracestop tracestop done tracestop tracestop done Stops collecting trace information The done option signifies the end of tracing Note Supported on ISS targets only watch watch r w address data watch r 0x400 0x1234 watch r 0x40X 0x12X4 watch r 0b01000000XXXX 0b00010010XXXX0100 watch r 0x40X Sets a read or write watchpoint at addr
357. the following topics e Features e Tool Requirements e Tool Usage e Tool Options e Load Path e Output Files e Synthesis Netlist Cache Features The features of Platgen includes the creation of e The programmable system on a chip in the form of hardware netlists HDL and implementation netlist files e A hardware platform using the Microprocessor Hardware Specification MHS file as input e Netlist files in various formats such as NGC and EDIF e Support files for downstream tools and top level HDL wrappers to allow you to add other components to the automatically generated hardware platform After running Platgen XPS spawns the Project Navigator interface for the FPGA implementation tools to complete the hardware implementation allowing you full control over the implementation At the end of the ISE flow a bitstream is generated to configure the FPGA This bitstream includes initialization information for block RAM memories on the FPGA chip If your code or data must be placed on these memories at startup the Data2MEM tool in the ISE tool set updates the bitstream with code and data information obtained from your executable files which are generated at the end of the software application creation and verification flow Embedded System Tools Reference Manual www xilinx com 55 UG111 EDK 11 3 1 Chapter 3 Platform Generator Platgen Additional Resources XILINX The Platform S
358. the name of the MSS file Example set proc handle xget sw processor handle mss handle processor name 282 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Software Tcl Commands x XILINX xget_sw_property_handle lt handle gt lt property_name gt Description Returns the handle to a property specified by the lt property_name gt associated with the handle Valid handle types are interface array or function Arguments lt handle gt is of specified type Valid handle types are interface array or function lt property_name gt is the name of the property If specified as an asterisk the API returns a list of property handles To access an individual property handle iterate over the list in Tel Example set prop_handle xget_sw_property_handle swif_handle HEADER xget sw property value lt handle gt property name Description Returns the value of the specified property Arguments handle is of specified type property name is of specified property Example set prop val xget sw property value swif handle HEADER xget sw subproperty handle lt property_handle gt subprop name Description Returns the handle to a subproperty associated with the specified property handle Arguments property handle is the name of the property Valid options are PARAMETER ARRAY ELEMENT FUNCTION PROPERTY INTERFACE or OPTION su
359. thout the use of any bootloader or debugging stub such as xmdstub This CRT populates the reset interrupt exception and hardware exception vectors and invokes the second stage startup routine crtinit On returning from crtinit it ends the program by infinitely looping in the exit label crtl o This initialization file is used when the application is debugged in a software intrusive manner It populates all the vectors except the breakpoint and reset vectors and transfers control to the second stage _crtinit startup routine On returning from _crtinit it returns program control back to the XMDStub which signals to the debugger that the program has finished crt2 o This initialization file is used when the executable is loaded using a bootloader It populates all the vectors except the reset vector and transfers control to the second stage _crtinit startup routine On returning from _crtinit it ends the program by infinitely looping at the _exit label Because the reset vector is not populated on a processor reset control is transferred to the bootloader which can reload and restart the program www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX crt3 o This initialization file is employed when the executable does not use any vectors and wishes to reduce code size It populates only the reset vector and transfers control to the second stage crtinit startup routine O
360. tion e BM Book E http www ibm com e IBM PowerPC performance library http sourceforge net projects ppcpertlib e APU FPU documentation http www xilinx com ise embedded edk ip htm MicroBlaze Information e The MicroBlaze Processor Reference Guide http www xilinx com ise embedded edk_docs htm Compiler Framework This section discusses the common features of both the MicroBlaze and PowerPC processor compilers The following figure displays the GNU tool flow Input C C Files as mb as or powerpc eabi as Libraries mb Id or powerpc eabi ld Output ELF File UG111 05 101905 Figure 8 1 GNU Tool Flow 110 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 8 GNU Compiler Tools XILINX The GNU compiler is named mb gcc for MicroBlaze and powerpc eabi gcc for PowerPC The GNU compiler is a wrapper that calls the following executables Pre processor cpp0 This is the first pass invoked by the compiler The pre processor replaces all macros with definitions as defined in the source and header files Machine and language specific compiler This compiler works on the pre processed code which is the output of the first stage The language specific compiler is one of the following C Compiler cc1 The compiler responsible for most of the optimizations done on the input C code and for generating assembly code C Compiler cc1plus The compiler resp
361. tionHandler XIntc DeviceInterruptHandler void XPAR XPS INTC 0 DEVICE ID Enable non critical exceptions on PowerPC T XExc mEnableExceptions XEXC NON CRITICAL At this point the system is ready to respond to interrupts from the timer p while 1 Embedded System Tools Reference Manual www xilinx com 253 UG 111 EDK 11 3 1 XILINX Appendix B Interrupt Management 254 www xilinx com Embedded System Tools Reference Manual UG 111 EDK 11 3 1 gt XILINX Appendix C EDK Tcl Interface Introduction This appendix describes the various Tool Command Language Icl Application Program Interfaces APIs available in EDK tools and methods for accessing information from EDK tools using Tcl APIs This appendix contains the following sections e Introduction e Additional Resources e Understanding Handles e Data Structure Creation e Tcl Command Usage e EDK Hardware Tcl Commands e Tcl Example Procedures e Advanced Write Access APIs e Software Tcl Commands e Tcl Flow During Hardware Platform Generation e Additional Keywords in the Merged Hardware Datastructure e Tcl Flow During Software Platform Generation Each time EDK tools run they build a runtime data structure of your design The data structure contains information about user design files such as Microprocessor Hardware Specification MHS and Micr
362. tools to write the HDL files that describe the connections the time and effort required to set up the test environment are reduced The following sections describe how to perform BFM simulation using the Platform Studio BFM Package Getting and Installing the Platform Studio BFM Package The use of the CoreConnect BFM components requires the acceptance of a license agreement For this reason the BFM components are not installed along with EDK Xilinx provides a separate installer for these called the Xilinx EDK BFM Package To use the Xilinx EDK BFM Package you must register and obtain a license to use the IBM CoreConnect Toolkit at http www xilinx com products ipcenter dr_pcentral_coreconnect htm After you register you receive instructions and a link to download the CoreConnect Toolkit files You can then install the files using the registration key provided After running the installer you can verify that the files were installed by typing the following command xilbfc check A Success message indicates you are ready to continue otherwise you will receive instructions on the error Embedded System Tools Reference Manual www xilinx com 73 UG111 EDK 11 3 1 Chapter 5 Bus Functional Model Simulation XILINX Using the Platform Studio BFM Package After successfully downloading and installing the Platform Studio BFM Package you can launch Platform Studio Note OPB and PLB components are deprecated in
363. tructure to use by the ACE controller 3 Copy the generated ACE file to the appropriate directory For more information refer to the iMPACT section of the ISE Help Embedded System Tools Reference Manual www xilinx com 215 UG111 EDK 11 3 1 x XILINX Related Information 216 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 13 Flash Memory Programming This chapter describes the flash memory programming tools in EDK and includes the following sections e Overview e Supported Flash Hardware e Flash Programmer Performance e Customizing Flash Programming Overview You can program the following in flash e Executable or bootable images of applications e Hardware bitstreams for your FPGA e File system images data files such as sample data and algorithmic tables The executable or bootable images of applications is the most common use case When the processor in your design comes out of reset it starts executing code stored in block RAM at the processor reset location Typically block RAM size is only a few kilobytes or so and is too small to accommodate your entire software application image You can store your software application image typically a few megabytes worth of data in flash memory A small bootloader is then designed to fit in block RAM The processor executes the bootloader on reset which then copies the software application image from f
364. ts lt BI gt lt nOPB gt _ABus in std logic vector 0 to C_ lt BI gt OPB_AWIDTH 1 BI nOPB BE in std logic vector 0 to C BI OPB DWIDTH 8 1 BI nOPB Clk in std logic BI nOPB DBus in std logic vector 0 to C BI OPB DWIDTH 1 BI nOPB Rst in std logic BI nOPB RNW in std logic BI nOPB select in std logic BI nOPB segAddr in std logic 1 Deprecated in this release Embedded System Tools Reference Manual www xilinx com 45 UG111 EDK 11 3 1 XILINX Conventions for Defining HDL Peripherals Examples OPB_DBus in std_logic_vector 0 to C_OPB_DWIDTH 1 IOPB_DBus in std_logic_vector 0 to C_IOPB_DWIDTH 1 Bus1_OPB_DBus in std_logic_vector 0 to C Bus1 OPB DWIDTH 1 Master Slave OPB Ports The following table shows the signal list that applies to master and slave type OPB ports that attach to the same OPB bus and share the input and output data buses This bus interface type is typically used when a peripheral has both master and slave functionality and when DMA is included with the peripheral It is useful for the master and slave to share the input and output data buses Master and slave OPB ports must follow these naming conventions Table 2 11 Master Slave OPB Port Naming Conventions Mn A meaningful name or acronym for the master output Mn must rot contain the string OPB upper lower or mixed case so that master outputs are not confused wi
365. ture of how the tools operate together to create an embedded system Processor Hardware Platform MHS IP Library or User Repository Drivers Platform Simulation Libraries Seas System and HDL Model Wrapper HDL system BMM E Synthesis XST l NGC Implementation NM s NGDBuild Simulation CompXLib IP Models Processor Software Platform MSS EDK Software Libraries BSP MLD Library Generator Application Source C h S Compiler GCC Constraint File Generator Structural HDL Model MAP PAR NCD UCF Simulation Generator Timing HDL SDF Model ELF system_BD BMM a Bitstream Generator Bitstream Initializer a system BIT download BIT iMPACT JTAG Cable FPGA Device X10310 Simulation Debugger XMD GDB download CMD Figure 1 2 Embedded Development Kit EDK Tools Architecture 20 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX EDK Tools and Utilities EDK Overview The following table describes the tools and utilities supported in EDK and the subsections that follow provide an overview of each tool with references to the chapters that contain additional information Table 1 1 EDK Tools and Utilities Hardware Development and Verification Xilinx Platform Studio XPS An integrated design environment GUI in which you can create your embedded hardware
366. ub component of the Platform Studio technology www xilinx com 299 XILINX 300 Appendix D Glossary Software Platform SPI A software platform is a collection of software drivers and optionally the operating system on which to build your application Because of the fluid nature of the hardware platform and the rich Xilinx and Xilinx third party partner support you may create several software platforms for each of your hardware platforms Serial Peripheral Interface Standalone Library SVF File UART UCF VHDL XBD File XCL Xilkernel Standalone library A set of software modules that access processor specific functions Serial Vector Format file Universal Asynchronous Receiver Transmitter User Constraints File VHSIC Hardware Description Language Xilinx Board Definition file Xilinx CacheLink A high performance external memory cache interface available on the MicroBlaze processor The Xilinx Embedded Kernel shipped with EDK A small extremely modular and configurable RTOS for the Xilinx embedded software platform www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Terms Used in EDK Embedded System Tools Reference Manual UG111 EDK 11 3 1 XMD XMP File XPS XST ZBT 7 XILINX Xilinx Microprocessor Debugger Xilinx Microprocessor Project file This is the top level project file for an EDK design Xilinx Platform Studio The GUI e
367. ug device command in the Genace File Options in Table 12 2 page 208 e Updates XMD An option to specify the fpga device was added to the Program Control Options in Table 9 21 page 194 Anote was added to the dow command to clarify that only those segments of an ELF file that are marked as LOAD are executed References to ppc440 mode for ISS were removed e Update BFM The Bus Functional Model was added as a chapter of this document e Update Flash Programmer A work around was added to allow the user to change a flash program from synchronous to asynchronous in the TCL file 11 2 Changes Tools are updated to reflect revision 11 2 e Updates Flash Memory The set reset command documentation was updated to include information regarding new flash devices that require that the cfi c file be modified e Updates configdevice option The configdevice option documentation changed to reflect that the option is available in the OPT file only configdevice is not available as a command line option 11 1 Changes Tools are updated to reflect revision 11 1 e Updates XMP The following tags were removed from the XMP in 11 1 FpgaImpMode Used to select between Xplorer and xflow flows Beginning with release 11 1 Xplorer is no longer supported in EDK Instead instantiate the project in the ISE Project Navigator to use Xplorer flow EnableResetOptimization ISE tools no longer require this setting t
368. ument is provided in the Additional Resources page 109 mno xl barrel shift This option tells the compiler not to use hardware barrel shift instructions This option is the default mxl pattern compare This option activates the use of pattern compare instructions in the compiler Using pattern compare instructions can speed up boolean operations in your program Pattern compare operations also permit operating on word length data as opposed to byte length data on string manipulation routines such as strcpy strlen and strcmp On a program heavily dependent on string manipulation routines the speed increase obtained will be significant The compiler automatically defines the C pre processor definition HAVE HW PCMP when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the use of the pattern compare option in MicroBlaze A link to the document is provided in the Additional Resources page 109 mno xl pattern compare This option tells the compiler not to use pattern compare instructions This option is the default mhard float This option turns on the usage of single precision floating point instructions fadd rsub fmul and fdiv in the compiler Italso uses cmp p instructions where p is a predicate condition such as 1e ge 1t gt eg n
369. upport the fPIC switch to generate position independent code The PowerPC compiler supports the mrelocatable switches to generate a slightly different form of relocatable code While both these features are supported in the Xilinx compiler they are not supported by the rest of the libraries and tools because EDK only provides a standalone platform No loader or debugger can interpret relocatable code and perform the correct relocations at runtime These independent code features are not supported by the Xilinx libraries startup files or other tools Third party OS vendors could use these features as a standard in their distribution and tools Other Switches and Features Other switches and features might not be supported by the Xilinx EDK compilers and or platform such as fprofile arcs Some features might also be experimental in nature as defined by open source GCC and could produce incorrect code if used inappropriately Refer to the GCC manual for more information on specific features A link to the document is provided in Additional Resources page 109 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 9 Xilinx Microprocessor Debugger XMD The Xilinx Microprocessor Debugger XMD is a tool that facilitates debugging programs and verifying systems using the PowerPC 405 or 440 processor or the MicroBlaze processor You can use it to debug programs on MicroBlaze or Powe
370. ur linker script in the place of the default built in linker script Linker scripts can be generated for your program from within XPS and SDK In XPS or SDK select Tools gt Generate Linker Script This opens up the linker script generator utility Mapping sections to memory is done here Stack and Heap size can be set as well as the memory mapping for Stack and Heap When the linker script is generated it is given as input to GCC automatically when the corresponding application is compiled within XPS or SDK Linker scripts can be used to assign specific variables or functions to specific memories This is done through section attributes in the C code Linker scripts can also be used to assign specific object files to sections in memory These and other features of GNU linker scripts are explained in the GNU linker documentation which is a part of the online binutils manual A link to the GNU manuals is supplied in the Additional Resources on page 109 For a specific list of input sections that are assigned by MicroBlaze and PowerPC linker scripts see MicroBlaze Linker Script Sections on page 134 and PowerPC Processor Linker Script Sections on page 144 Embedded System Tools Reference Manual www xilinx com 125 UG111 EDK 11 3 1 7 XILINX MicroBlaze Compiler Usage and Options MicroBlaze Compiler Usage and Options The MicroBlaze GNU compiler is derived from the standard GNU sources as the Xilinx port of the compiler The fe
371. ure X10582 Figure C 1 Merged Hardware Data Structure Creation www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Tcl Command Usage XILINX Tcl Command Usage General Conventions There are two kinds of Tcl APIs which differ based on the type of data they return Tcl APIs return either e A handle or a list of handles to some objects e A value or a list of values The common rules followed in all Tcl APIs are e AnAPIreturns a NULL handle when an expected handle to another object is not found e An API returns an empty string when a value is either empty or that value cannot be determined Before You Begin When you use XPS in non GUI mode xps nw you must first initialize the internal tool database the runtime datastructure by loading the project with the xload command xload lt filetype gt lt filename gt MHS MSS XMP Refer to Chapter 4 Command Line no window Mode for more detail regarding xload To gain access to either the MHS Handle or the merged MHS Handle use one of the following commands after loading the project XPS set original mhs handle xget handle mhs Or XPS set merged mhs handle xget handle merged mhs The following section provides the nomenclature of the EDK Hardware Tcl commands in more detail Embedded System Tools Reference Manual www xilinx com 257 UG111 EDK 11 3 1 XILINX Appendix C EDK Tcl Interface EDK Hardware Tcl Commands O
372. vendors For these unknown devices IRLength is the only critical information the other fields such as partname and idcode are optional The options used in the following example are e Xilinx Parallel cable III or IV connection is done over the LPT1 parallel port e The two devices in the JTAG chain are explicitly specified e The IRLength partname and idcode of the PROM are specified e The debugdevice option explicitly specifies to XMD that the FPGA device of interest is the second device in the JTAG chain In Virtex devices it is also explicitly specified that the connection is for the first PowerPC processor if there is more than one XMD connect ppc hw cable type xilinx parallel port LPT1 configdevice devicenr 1 partname PROM XC18V04 irlength 8 idcode 0x05026093 configdevice devicenr 2 partname XC2VP4 irlength 10 idcode 0x0123e093 debugdevice devicenr 2 cpunr 1 Adding Non Xilinx Devices You can add a non Xilinx device either on the command line using the connect command using the JTAF Chain options or by specifying it in the GUI See Connect Command Options page 168 and JTAG Chain Options page 169 and for more information PowerPC Processor Simulator Target XMD can connect to one or more PowerPC 405 processor ISS targets through socket connection Use the connect ppc sim command to start the PowerPC 405 processor ISS on a local host connect to that host and start a remote GDB server You can also use connect
373. vers if required Backup copies of the MHS and MSS files are created before the project is modified You may choose to cancel the wizard at any time without modifying the files but as a result it may not be possible to run the project with the current version of XPS Embedded System Tools Reference Manual www xilinx com 229 UG111 EDK 11 3 1 XILINX The Version Management Wizard 230 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 XILINX Chapter 15 Xilinx Bash Shell This chapter introduces the Xilinx Cygwin based Bash shell It contains the following sections e Summary e Xilinx Bash Shell Summary The Xilinx Embedded Development Kit EDK includes some GNU based tools such as the compiler the debugger and the make utility For the NT platform these require a LINUX emulation shell the Red Hat Cygwin shell and utilities are provided as part of the EDK installation The EDK Installed Cygwin Environment Xilinx EDK installs a Cygwin environment under XILINX_EDK cygwin Requirements for Using an Existing Cygwin Environment You can also use your existing Cygwin environment Pre existing Cygwin environments must conform to the following requirements e The Cygwin revision level must be 1 5 17 May 2005 or later e The make utility make exe must be available If your pre existing Cygwin environment meets these requirements it is used If your existing Cygwi
374. verview This section provides a list of Tcl APIs available in the EDK hardware data structure The description of these commands uses certain terms which are defined in the following subsections Original MHS Handle original_mhs_handle The handle that points to the MHS information only This handle does not contain any MPD information If an IP parameter has not been specified in the MHS this handle does not contain that parameter Merged MHS Handle merged_mhs_handle The handle that points to both the MHS and MPD information A hardware datastructure merged object is formed when the tools merge the MHS and MPD information Note Various Tcl procedures are also called within batch tools such as Platgen Libgen and Simgen Handles provided through batch tools always refer to the merged MHS handle You do not have access to the original MHS handle from the batch tools The original MHS handle is needed only when you must modify the design using the provided APIs so that the generated MHS design file can be updated Original IP Instance Handle original IP handle A handle to an IP instance obtained from the original MHS handle that contains information present only in the MHS file Merged IP Instance Handle merged rP handle Refers to the IP handle obtained from the merged MHS handle The merged IP instance handle contains both MHS and MPD information Note Batch tools such as Platgen provide access to the merged IP instance h
375. ves www xilinx com 37 XILINX Conventions for Defining HDL Peripherals Reserved Parameters The following table lists the parameters that Platgen populates automatically Table 2 4 Reserved Parameters Parameter Description C_BUS_CONFIG Defines the bus configuration of the MicroBlaze processor C_FAMILY Defines the FPGA device family C_INSTANCE Defines the instance name of the component C_DCR_AWIDTH Defines the DCR address width C_DCR_DWIDTH Defines the DCR data width C_DCR_NUM_SLAVES Defines the number of DCR slaves on the bus C_LMB_AWIDTH Defines the LMB address width C_LMB_DWIDTH Defines the LMB data width C_LMB_NUM_SLAVES Defines the number of LMB slaves on the bus C_OPB_AWIDTH Defines the OPB address width C_OPB_DWIDTH Defines the OPB data width C_OPB_NUM_MASTERS Defines the number of OPB 2 masters on the bus C_OPB_NUM_SLAVES Defines the number of OPB slaves on the bus C PLB AWIDTH Defines the PLB address width C PLB DWIDTH Defines the PLB data width C PLB MID WIDTH Defines the PLB master ID width This is set to log2 S C PLB NUM MASTERS Defines the number of PLB masters on the bus C PLB NUM SLAVES Defines the number of PLB slaves on the bus a Deprecated in this release 38 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 2 Platform Specification Utilit
376. voked on its own When linker is invoked through the mb gcc compiler this option is automatically provided to the linker N This option sets the text and data section as readable and writable It also does not page align the data segment This option is required only for MicroBlaze programs The top level GCC compiler automatically includes this option while invoking the linker but if you intend to invoke the linker without using GCC use this option For more details on this option refer to the GNU manuals online A link to the manuals is provided in the Additional Resources page 109 The MicroBlaze linker uses linker scripts to assign sections to memory These are listed in the following section Embedded System Tools Reference Manual www xilinx com 133 UG111 EDK 11 3 1 XILINX 134 MicroBlaze Linker Script Sections MicroBlaze Compiler Usage and Options The following table lists the input sections that are assigned by MicroBlaze linker scripts Table 8 7 Section Names and Descriptions Section Description vectors reset Reset vector code vectors sw exception Software exception vector code vectors interrupt Hardware Interrupt vector code vectors hw exception Hardware exception vector code text Program instructions from code in functions and global assembly statements rodata Read only variables Sdata2 Small read only static and global variable
377. w xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD XILINX DCR TLB and Cache Address Space and Access The XMD sets up address space for you to access TLB entries and Cache entries These address spaces can be specified with tlbstartadr icachestartadr and dcachestartadr as options to the connection command If the TLB and Cache address space is not specified XMD uses a default unused address space for this purpose When connected these address spaces are displayed in the XMD console For example I Cache Data 0x70000000 0x70007 f I Cache TAG 0x70008000 0x7000 ffff D Cache Data 0x78000000 0x78007 f D Cache TAG 0x78008000 0x7800 ffff DOR ucc qad oues 0x78020000 0x78020fff REB de eu EE LS 0x70020000 0x70023fff TLB Access Each TLB entry is represented by a 4 word entry The following table shows the 4 word entries available for PPC405 and PPC440 Table 9 13 PPC405 and PPC440 TLB Entries Word PPC405 PPC440 1 PID PID 2 TLBHI TLB Word0 excluding PID 3 TLBLO TLB Word1 4 Padded with 0 s TLB Word2 The total 64 TLB entries can be read from or written to the 256 words starting from the TLB starting address Cache Word Access The cache entries are mapped to the address space in a way by way manner Using the provided example if the cache line size is 32 byte and e
378. words sub properties that are created optionally on parameters ports and bus interfaces in the merged hardware datastructure These are used internally by tools and can also be used by Tcl for DRCs These additional keywords are e MHS_VALUE When the merged object is created it combines information from both MHS and MPD The default value is present in the MPD However these properties can be overridden in the MHS The tools have conditions when some values are auto computed and that auto computed value will override the values in MHS also The original value specified in MHS is consequently stored in the MHS_VALUE sub property e MPD_VALUE When the merged object is created it combines information from both MHS and MPD The default value is present in the MPD However these properties can be overridden in the MHS The tools have conditions when some values are auto computed and that auto computed value will override the values in MHS also The value specified in MPD is consequently stored in the MPD_VALUE sub property e CLK_FREQ_HZ The frequency of every clock port in the merged hardware datastructure if available is stored in a sub property called CLK_FREQ_Hz on that port This is an internal sub property and the frequency value is always in Hz e RESOLVED ISVALID fa parameter port or bus interface has the sub property ISVALID defined in the MPD then the tools evaluate the expression to true 1 or false
379. wrappers are backward compatible the x name commands will be deprecated in a future EDK release The following Tcl command subsections are e Program Initialization Options e Register Memory Options e Program Control Options e Program Trace and Profile Options e Miscellaneous Commands Embedded System Tools Reference Manual www xilinx com 191 UG111 EDK 11 3 1 XILINX XMD Internal Tcl Commands Program Initialization Options Table 9 19 Program Initialization Option Option xconnect target mb ppc mdm connect type loptions Description Connects to a processor or a peripheral target Valid target types are mb ppc and mdm Refer to Connect Command Options page 168 for more information on options xdebugconfig target id step mode Step Type gt memory datawidth matching disable enable reset on run system enable processor enable disable Configures the debug session for the target For additional information refer to the Configure Debug Session page 189 xdisconnect target id Disconnects from the target xdownload target id filename load address xdownload target id data filename load address Downloads the given ELF or data file using the data option onto the memory of the current target If no address is provided along with ELF file the download address is determined from the ELF
380. www xilinx com ise embedded edk_docs htm e Device Driver Programmer Guide is located in the doc usenglish folder of your EDK installation file name xilinx_drivers_guide paf Tool Usage To run Libgen type the following libgen options lt filename gt mss Tool Options The following options are supported in this version Table 7 1 Libgen Syntax Options Option Command Description Help h help Displays the usage menu and quits Version v Displays the version number of Libgen and quits Log output log lt logfile log gt Specifies the log file Default Libgen log Architecture p lt partname gt Defines the target device defined either as family architecture family or partname Use h to view a list of values for the target family Output directory od lt output_dir gt Specifies the output directory output_dir The default is the current directory All output files and directories are generated in the output directory The input file filename mss is taken from the current working directory This output directory is also called OUTPUT_DIR and the directory from which Libgen is invoked is called YOUR PROJECT for convenience in the documentation Source directory sd source dir Specifies the source directory source dir for searching the input files The default is the current working directory 100 www xilinx com Embedded System Tools Reference Manu
381. x com 197 UG111 EDK 11 3 1 XILINX Additional Resources Tool Options The following options are the most common in the GNU debugger command FILE Execute GDB commands from the specified file Used for debugging in batch and script mode batch Exit after processing options Used for debugging in batch and script mode nx Do not read initialization file gdbinit If you have issues connecting to XMD GDB connects and disconnects from XMD target launch GDB with this option or remove the gdbinit file nw Do not use a GUI interface W Use a GUI interface Default Debug Flow using GDB 1 Start XMD from XPS Connect to the Processor target This action opens a GDB server for the target Start GDB from XPS Connect to Remote GDB Server on XMD Download the Program and Debug application a PF YN Additional Resources e GNU website http www gnu org e Red Hat Insight webpage http sources redhat com insight MicroBlaze GDB Targets The MicroBlaze GNU Debugger and XMD tools support remote targets Remote debugging is done through XMD The XMD server program can be started on a host computer with the Simulator target or the Hardware target The Cycle Accurate Instruction Set Simulator ISS and the hardware interface provide powerful debugging tools for verifying a complete MicroBlaze system The debugger mb gdb connects to XMD using the GDB remote protocol over TCP IP socket connection Simulator Ta
382. x provides simulation models for these primitives in the libraries listed in this section The libraries described in the following sections are available for the Xilinx simulation flow The HDL code must refer to the appropriate compiled library The HDL simulator must map the logical library to the physical location of the compiled library Xilinx ISE Libraries Xilinx ISE libraries can be compiled using the Compxlib utility Refer to the Command Line Tools User Guide to learn more about Compxlib Refer to the Simulating Your Design chapter of the Synthesis and Simulation Design Guide to learn more about compiling and using Xilinx ISE simulation libraries A link to the documentation web site is provided in Additional Resources page 85 Xilinx ISE provides the following libraries for simulation e UNISIM Library e SIMPRIM Library e XilinxCoreLib Library UNISIM Library The UNISIM Library is a library of functional models used for behavioral and structural simulation It includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools The UNISIM library also includes components that are commonly instantiated such as I Os and memory cells You can instantiate the UNISIM library components in your design VHDL or Verilog and simulate them during behavioral simulation Structural simulation models generated by Simgen instantiate UNISIM library components Asynchronous components in t
383. xt section MD Command Reference page 154 Embedded System Tools Reference Manual UG111 EDK 11 3 1 www xilinx com 153 7 XILINX XMD Console XMD Console The XMD console is a standard Tcl console where you can run any available Tcl commands Additionally the XMD console provides command editing convenience such as file and command name auto fill and command history The available Tcl commands on which you can use auto fill are defined in the EDK Install Area data xmd cmdlist file The command history is stored in HOME xmdcmdhi story To use different files for available command names and command history you can use environment variables XILINX XMD CMD LIST and XILINX XMD CMD HISTORY to overwrite the defaults XMD Command Reference XMD User Command Summary The following is a summary of XMD commands To go to a description for a given command click on its name bpl rst bpr rwr bps run con safemode connect state cstp srrd data verify Stackcheck debugconfig state dis stats disconnect stop dow stp elf verify targets fpga f terminal lt bitstream gt mrd tracestart mwr tracestop profile watch read_uart verbose rrd xload www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 9 Xilinx Microprocessor Debugger XMD 7 XILINX XMD User Commands The following table displays XMD user commands and options For a list of special register
384. y PsfUtility XILINX Naming Conventions for Bus Interface Signals This section provides naming conventions for bus interface signal names The conventions are flexible to accommodate embedded processor systems that have more than one bus interface and more than one bus interface port per component When peripherals with more than one bus interface port are included in a design it is important to understand how to use a bus identifier As explained previously a bus identifier must be used for peripherals that contain more than one of the same bus interface The bus identifier must be attached to all associated signals and generics The names must be HDL compliant Additional conventions for IP peripherals are e The first character in the name must be alphabetic and uppercase e The fixed part of the identifier for each signal must appear exactly as shown in the applicable section below Each section describes the required signal set for one bus interface type e If more than one instance of a particular bus interface type is used on a peripheral the bus identifier BI must be included in the signal identifier The bus identifier can be as simple as a single letter or as complex as a descriptive string with a trailing underscore peripheral BI must be included in the port signal identifiers in the following cases The peripheral has more than one slave PLB port The peripheral has more than one master PLB port The per
385. y the define FRR CMD OxFF in the cfi c file to define FRR CMD OxFO Handling Flash Devices with Conflicting Sector Layouts Some flash vendors store a different sector map in the CFI table and another based on the boot topology of the flash device in hardware Because the boot topology information is not standardized in CFI the flash programmer cannot determine the layout of your particular flash device If your flash hardware has a sector layout that is different from the one specified in the CFI table for the device then you must create a custom flash programming flow You must determine whether the device is a top boot or a bottom boot flash device 222 www xilinx com Embedded System Tools Reference Manual UG111 EDK 11 3 1 Chapter 13 Flash Memory Programming XILINX In a top boot flash device the smallest sectors are the last sectors in the flash In a bottom boot flash device the smallest sectors are the first sectors in the flash layout After you determine the flash device type you must copy over the files to create a custom programming flow e If you have a bottom boot flash add the following line in your etc flash_params tcl file set FLASH BOOT CONFIG BOTTOM BOOT FLASH e Ifyou have a top boot flash add the following line in your etc flash_params tcl file set FLASH BOOT CONFIG TOP BOOT FLASH Next run the flash programming from the command line with the following command umd tcl flashwriter tcl
386. you can then use as appropriate The utilities mb objcopy and powerpc eabi objcopy are GNU binaries that ship with EDK For information about creating a bootloader from within a GUI see the Xilinx Platform Studio Help or the SDK Help Operational Characteristics and Workarounds Handling Xilinx Platform Flash Modes The Xilinx Platform Flash memory devices initialize in synchronous mode You must set such devices to asynhcronous mode before performing device operations This capability is provided as an internally enabled workaround in the flash programmer flow because not all devices require a mode switch and the flash programmer does not contain such device specifics To enable this workaround use a custom flash programming flow Add the following line in your etc flash_params tcl file set XILINX_PLATFORM_FLASH 1 Next run the flash programming from the command line with the following command xmd tcl flashwriter tcl Handling Flash Devices with OxFO as the Read Reset Command The CFI specification defines the read reset command as 0xFF 0xF0 By default the flash programmer uses the 0xFF read reset command Certain devices require 0xF0 as the read reset command however the flash programmer is unable to determine this automatically Consequently you might encounter issues when programming newer devices In that event of an error occurring follow the documented steps in Customizing Flash Programming page 220 then modif
387. ysical placement information on each block RAM in the FPGA Internally the Bitstream Initializer tool uses the Data2MEM utility to update the bitstream file See Figure 1 2 page 20 to see how the Bitinit tool fits into the overall system architecture Refer to Chapter 11 Bitstream Initializer BitInit for more information System ACE File Generator GenACE XPS generates Xilinx System ACE configuration files from an FPGA bitstream ELF and data files The generated ACE file can be used to configure the FPGA initialize block RAM initialize external memory with valid program or data and bootup the processor in a production system EDK provides a Tool Command Language Tcl script genace tc1 that uses XMD commands to generate ACE files ACE files can be generated for PowerPC processors and MicroBlaze processors with Microprocessor Debug Module MDM systems For more information see Chapter 12 System ACE File Generator GenACE Embedded System Tools Reference Manual www xilinx com 27 UG111 EDK 11 3 1 28 Chapter 1 Embedded System and Tools Architecture Overview XILINX Flash Memory Programmer The Flash Memory Programming solution is designed to be generic and targets a wide variety of flash hardware and layouts See Chapter 13 Flash Memory Programming Format Revision Tool and Version Management Wizard The Format Revision Tool revup updates an existing EDK project to the current version The revup t
388. zero when the program starts execution Additionally optimizing compilers will also allocate global variables that are assigned zero in C code to the bss section In a simulation environment the two language features above can be unwanted overhead Some simulators automatically zero the whole memory Even in a normal environment you can write C code that does not rely on global variables being zero initially This switch is useful for these scenarios It causes the C startup files to not initialize the bss section with zeroes It also internally forces the compiler not to allocate zero initialized global variables in the bss and instead move them to the data section This option may improve startup times for your application Use this option with care Do not use code that relies on global variables being initialized to zero or ensure that your simulation platform performs the zeroing of memory Embedded System Tools Reference Manual www xilinx com 143 UG111 EDK 11 3 1 7 XILINX PowerPC Compiler Usage and Options PowerPC Processor Linker The powerpc eabi 1d linker for the PowerPC processor introduces a new option in addition to those supported by the GNU compiler tools The option is described below defsym START ADDR value By default the text section of the output code starts with the base address 0xff 0000 because this is the start address listed in the default linker script This can be overridden by using the above optio

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