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1. ELECTRONICS SAM47 INSTRUCTION SET KS57C3316 P3316 Table 5 16 Program Control Instructions Binary Code Summary Continued Name operand Binary Code Operation Notation PC13 8 SP 1 SP PC7 0 lt SP 3 SP 2 lt SP 4 1 ERB lt SP 4 0 SP SP 6 PC13 8 lt SP 1 SP PC7 0 lt SP 3 SP 2 PSW lt SP 5 SP 4 SP SP 6 PC13 8 lt SP 1 SP PC7 0 lt SP 3 SP 2 lt SP 4 1 ERB lt SP 4 0 SP lt SP 6 then skip Table 5 17 Data Transfer Instructions Binary Code Summary XCH A DA Tar os Tor els o i i jio nno EA DA 1 1 AG DAEGDA 1 rar Tos os oe os oe ar oo EA RRb HL lt gt HL 1 XCHI A HL 1 1 1 A HL then L lt 1 1 skip if L XCHD A HL 1 1 e HL then L 1 1 skip if L OFH ewm ies s e e s 5 acm sonra 1 v Ges Fer os os s ma ppp pbi ela 5 16 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET Table 5 17 Data Transfer Instructions Binary Code Summary Continued Binary Code Operation Notation wm pp D e oo pe mam e
2. 17 12 A C Timing Measurement Points Except for Xy and 17 13 Clock Timing Measurement at Xy eia Tiene Neh ovi etre gera dea ee Koes ee 17 13 Clock Timing Measurement at XT I 17 13 Input Timing for RESET Silgrial er Dd etie re Eod Ee eta 17 14 Input Timing for External Interrupts and Quasi Interrupts ppp 17 14 80 QFP 1420C Package Dimensions 18 1 KS57P3316 Pin Assignments 80 19 2 Standard Operating Voltage 19 12 Stop Mode Release Timing When Initiated by 19 13 Stop Mode Release Timing When Initiated by an Interrupt 19 13 Timing Measurement Points Except for Xy and 19 14 Glock Timing Measurement at Xy ehe fcrt esi ond ee 19 14 Clock Timing Measurement at III Immer 19 14 Input Timing for RESET 19 15 Input Timing for External Interrupts and 19 15 SMDS Product Configuration SMDS2 sese nnne 20 2 TB573316A Target Board een 20 3 40 Pin Connectors for
3. 10 10 Port 5 Circuit cope eger A 10 11 Forts Circuit Diagrams oe oce roe epe 10 12 Chapter 11 Timers and Timer Counter e n 11 1 BT ie ese e epe TEES 11 2 ecu 11 2 Basic Timer Mode Register 11 4 Basic Timer Counter BCN Theis da Idea eva i ec au du dus 11 5 Timer Output Enable Register 11 5 Basic Timer Operation 11 5 Watchdog Timer Mode Register 11 7 Watchdog Timer Counter 11 7 Watchdog Timer Counter Clear mener 11 7 8 Bit Timer Counter TCO 11 9 QU C Em 11 9 TCO Furiction Summa cadet eee nk lag ER dee Va opea 11 9 TOO Component E 11 10 TCO Programmable Timer Counter 11 12 TCO Operation Sequerice 1 epe Te A eee ia PIRE QR DE 11 12 TCO Event Counter FUnction tonirana E ni
4. IRQB 1 KS57C3316 P3316 If no INT4 interrupt if yes INTB interrupt is processed INT4 is processed ELECTRONICS KS57C3316 P3316 POWER DOWN POWER DOWN OVERVIEW The KS57C3316 microcontroller has four power down modes to reduce power consumption idle stop1 stop2 and CE low modes Idle mode is initiated by the IDLE instruction and stop1 mode by the instruction STOP Several NOP instructions must always follow an IDLE or STOP instruction in a program In idle mode the CPU clock stops while peripherals and the oscillation source continue to operate normally When RESET occurs during normal operation or during a power down mode a reset operation is initiated and the CPU enters idle mode When the standard oscillation stabilization time interval 29 1 ms at 4 5 MHz has elapsed normal CPU operation resumes In stop1 mode main system clock oscillation is halted assuming it is currently operating and peripheral hard ware components are powered down Stop2 mode is entered by bit SCMOD 2 setting In stop2 mode both main and sub system clock are stopped Only PLL is disabled in CE low mode while other peripherals operate normally The effect of power down mode on specific peripheral hardware components is detailed in Table 8 1 NOTE Do not use stop mode if you are using an external clock source because Xp input must be restricted internally to Vgs to reduce current leakage Idle or main sto
5. 1 skipon cary ELECTRONICS 5 19 SAM47 INSTRUCTION SET KS57C3316 P3316 Table 5 20 Bit Manipulation Instructions Binary Code Summary Name oporana Binary Code Operation Notation 5 20 e DA b pt ft for 1 JSkpitDAb i a6 a5 a4 at m pM aes Skip if memb 7 2 L 3 2 1 1 _ mema b m PTT Tete Skip if mema b 0 well ces memb L Skip if memb 7 2 L 3 2 L 1 0 0 Fe o ss a Skip if DA 3 0 b 0 o bt bo as a2 m Skip if mema b 1 and clear memb L Skip if memb 7 2 L 3 2 L 1 0 1 and clear H DA b ipm Skip if H DA 3 0 b 1 and clear o o bt bo at a0 Far ss ar mema b lt 1 o o ao ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET Table 5 20 Bit Manipulation Instructions Binary Code Summary Continued Binary Code Operation Notation 2 Pace m PEE ETT memb L 14111 1111 11 1 1 o Imemb7 2 L3 2 1 0 0 EXER ER SET Ea H
6. deck sete system dock esitare NEN EN R Read only Description of the W Write only effect of specific bit R W Read write settings Bit identifier used for bit addressing Type of addressing Bit value immediately Bit number in that must be used to following aRESET MSB to LSB order address the bit 1 bit 4 bit or 8 bit Figure 4 1 Register Description Format ELECTRONICS 4 7 MEMORY KS57C3316 P3316 ADMOD Apc Mode Register FDAH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W Bit Addressing 1 4 1 4 3 2 Bits 3 2 Always logic zero 1 0 ADC Analog Input Pin Selection Bits Select ADCO P5 0 as input channel Select ADC1 P5 1 as input channel ESEJ Select ADC2 P5 2 as input channel Select ADC3 P5 3 as input channel ELECTRONICS KS57C3316 P3316 MEMORY MAP AFLAG Flag Register FDBH Bit 3 2 1 0 Identifier ADSTR EOC ADCLK RESET Value 0 0 0 0 Read Write W R Bit Addressing 1 4 1 4 1 4 ADSTR ADC Conversion Start Control Flag 1 Enable ADC when the ADSTR bit is set to 1 the ADC starts operating and the ADSTR bit is cleared automatically EOC End of Conversion Bit Read only A D conversion operation is in progress 1 A D conversion operation is complete 4 Bit 1 Always logic zero ADCLK ADC Clock Source Selection Conversion clock fxx 2
7. Code direct addressing 0020H 007FH Select bank register 8 bits Logical exclusive OR Logical OR Logical AND Contents addressed by RR ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET OPCODE DEFINITIONS Table 5 7 Opcode Definitions Direct Table 5 8 Opcode Definitions Indirect amp n 0 HL WX WL i Immediate data for indirect addressing 0 0 0 0 1 1 1 1 0 0 1 1 ee e seco m Immediate data for register CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock Three different clock rates can be selected using the PCON register In this document the letter S is used in tables when describing the number of additional machine cycles required for an instruction to execute given that the instruction has a skip function S skip The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped whether it is a 1 byte 2 byte or 3 byte instruction A skip is also executed for SMB and SRB instructions The values in additional machine cycles for S for the three cases in which skip conditions occur are as follows Case 1 No skip S Ocycles Case 2 Skip is 1 byte or 2 byte instruction S 1 cycle Case 3 Skip is 3 byte instruction 2 cycles NOTE REF instructions are skipped in one machi
8. 6 5 6 2 Instruction Cycle Times for CPU Clock 6 6 6 3 System Clock Mode Register SCMOD 6 7 6 4 Main or Sub Oscillation Stop 6 8 6 5 System Operating Mode 6 9 6 6 Elapsed Machine Cycles During CPU Clock Switch 6 11 6 7 Clock Output Mode Register CLMOD 6 12 7 1 Interrupt Types and Corresponding Port 7 1 7 2 151 and 150 Bit Manipulation for Multi Level Interrupt 7 6 7 3 Standard Interrupt Priorities nnne 7 7 7 4 Interrupt Priority Register 05 7 7 7 5 IMODO 1 and 2 Register 7 8 7 6 IMOD2 Register Bit 0 0 7 10 7 7 Interrupt Enable and Interrupt Request Flag Addresses 7 12 7 8 Interrupt Request Flag Conditions and Priorities 7 13 8 1 Hardware Operation During Power Down 0 8 2 8 2 Unused Pin Connections for Reducing Power 8 7 9 1 Hardware Register Values After a System
9. 1 5 2 5 1 SCO The PSW can be manipulated by 1 bit or 4 bit read write and by 8 bit read instructions depending on the specific bit or bits being addressed The PSW can be addressed during program execution regardless of the current value of the enable memory bank EMB flag Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt After the interrupt has been processed the PSW values are popped from the stack back to the PSW address When a system reset is generated the EMB and ERB values are set according to the reset vector address and the carry flag is left undefined or the current value is retained PSW bits ISO 151 SCO SC1 and SC2 are all cleared to logical zero Table 2 5 Program Status Word Bit Descriptions PSW Bit Identifier Bit Addressing Read Write 2 16 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES INTERRUPT STATUS FLAGS 150 151 PSW bits 150 and 151 contain the current interrupt execution status values You can manipulate ISO and IS1 flags directly using 1 bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register IPR you can process multiple interrupts by anticipating the next interrupt in an execution sequence The interrupt priority control circuit determines the ISO and 151 settings in order to control multiple interrupt processing When both interrupt status flags are set to O all
10. aD 5 36 Bit Test and Skip on 5 37 Bit Test and Skip on False crecen teet ee ee PER de 5 38 Bit Test and Skip on True inei nette reset td Les pcd o tudo e th id Lena e E Pd OR 5 39 Bit Test arid Skip Thue aden tees 5 40 Bit Test and Skip on True Clear Bit 5 41 Bit Test and Skip on True Clear 5 42 Bit Exclusive QBs roin re liceat eb c ii reatus PERRA ER TERI res 5 43 Bit Exclusive OR eee er buena uidi MEE 5 44 Gall Proced te xe n aU e ater UD UI e HM ebd 5 45 Call Procedure Short ERI XR AAT ees dees 5 46 Gomplemeht Carty Flag xu e ea AXIS 5 47 Complement Accumulator nente nsa ear ene p 5 48 Compare and Skip if 5 49 Decrement and Skip on menm ene nnne 5 50 Disable Interrupts det tenella Nive 5 51 Enable Interrupts 5 52 Idle Operation 5 53 Increment and Skip on 20 5 54 Return From Interrupt Nive Hive 5 55 DUM 5 56 xxiii JPS JUMP
11. as es ae ar a 1 Far os as ue us ar oo eps men mo Dor p p heo Eon Far as ae us oo nude po pep eua Jiji mk po Far as as us we po o mecum ms Phere it pete ACA He E 991419441 A HL oo HL then L L 1 L 0H A HL then L L 1 ins i iis uc mew lt Eee v RRC A 1 1 C A 0 C 1 lt n21 2 3 PUSH r2 SP 1 SP 2 lt RR lt 5 1 lt SMB SP 2 SRB lt pats ELECTRONICS 5 17 SAM47 INSTRUCTION SET KS57C3316 P3316 Table 5 17 Data Transfer Instructions Binary Code Summary Concluded Lm Bia Operation Notation r2 rt RR lt SP RRy lt SP 1 SP SP 2 SRB lt SP SMB lt SP 1 SP SP 2 11 Table 5 18 Logic Instructions Binary Code Summary Name Operand Binary Code Operation Notation eM ke o fos acne 1 RRb EA A im A HL XOR i fas ae or oo Pols 4 E
12. 12 17 KS57C3316 P3316 MICROCONTROLLER Figure Number 13 1 13 2 14 1 14 2 14 3 15 1 15 2 15 3 16 1 16 2 16 3 16 4 16 5 17 1 17 2 17 3 17 4 17 5 17 6 17 7 17 8 18 1 19 1 19 2 19 3 19 4 19 5 19 6 19 7 19 8 19 9 20 1 20 2 20 3 20 4 List of Figures Concluded Title Page Number A D Converter Circuit Diagram 20000 0 13 2 A D Converter Timing mme n enn n 13 5 Serial I O Interface Circuit 14 2 SIO Timing in Transmit Receive 14 4 SIO Timing in Receive Only Mode Hee Herm nnne nnne 14 4 Block Diagram of the PLL Frequency e 15 1 PLE Register ConflguratlOn 15 3 Reference Frequency 15 4 IF Counter Block Diagram ee ene ee HS ERE ene He 16 1 Gate Timing 1 4 01 8 18 LS 16 3 16 4 Gate Timing Terris ED 16 5 and EMIF Pin 16 7 Standard Operating Voltage 17 11 Stop Mode Release Timing When Initiated by 17 12 Stop Mode Release Timing When Initiated by an Interrupt
13. 9 3 10 1 ROGER 10 2 10 2 Port Pin Status During Instruction 10 2 10 3 Port Mode Group conet Poi hi te Abre nb RR 10 3 10 4 Pull Up Resistor Mode Register PUMOD 10 4 10 5 N Channel Open Drain Mode Register PNE Setting 10 5 10 6 LPOT Setting for Port 7 13 Output e 10 6 11 1 Basic Timer Register 1 1 nnne nnne 11 3 11 2 Basic Timer Mode Register BMOD Organization 11 4 11 3 Watchdog Timer Interval 0 22 11 7 11 4 TOO Register Overvigw i kd Merk eie Re 11 11 11 5 TMODO Setting for TOLO Edge Detection esses 11 13 11 6 Timer 0 Mode Register 11 16 11 7 TMODO 6 TMODO 5 and TMODO 4 Bit 11 17 11 8 Watch Timer Mode Register WMOD 11 24 12 1 Common Signal Pins Used per Duty 12 3 12 2 LCD Control Register LCON 12 4 12 3 LCON 0 and LMOD 3 Bit 12 4 12 4 LCD Mode Register LMOD eem 12 5
14. lt INCS HL Skip INCS HL lt 1 leaves the register pair HL with the value and RAM location with the value Since a carry occurred the second instruction is skipped The carry flag value remains unchanged 5 54 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET IRET Return From Interrupt IRET Operation Description Example a IRET is used at the end of an interrupt service routine It pops the PC values successively from the stack and restores them to the program counter The stack pointer is incremented by six and the PSW enable memory bank EMB bit and enable register bank ERB bit are also automatically restored to their pre interrupt values Program execution continues from the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower level or same level interrupt was pending when the IRET was executed IRET will be executed before the pending interrupt is processed 1 1 1 1 1 PC13 8 SP 1 SP PC7 0 SP 2 SP 3 PSW lt SP 4 SP 5 6 The stack pointer contains the value An interrupt is detected the instruction at location 0122H RAM locations OFDH OFCH and OFAH contain the values 2H 3H and 1H respectively The instruction IRET leaves the stack pointer with the value OOH and the program returns to continue exec
15. SEG1 P7 1 SEG3 P7 3 SEG5 P8 1 SEG7 P8 3 SEG9Q P9 1 SEG11 P9 3 2 5 5 5 e 10199uu0 U d 0p P4 2 SI P5 0 ADCO P5 2 ADC2 6 0 50 6 2 52 VDDO XouT TEST XT OUT BIAS VLC1 COMO COM2 SEGO P7 0 SEG2 P7 2 SEG4 P8 0 SEG6 P8 2 SEG8 P9 0 SEG10 P9 2 SEG12 P10 0 SEG13 P10 1 SEG15 P10 3 SEG17 P11 1 SEG19 P11 3 SEG21 P12 1 SEG23 P 12 3 SEG25 P13 1 SEG27 P13 3 P2 1 P2 3 VCOAM AMIF VDD1 CE P3 1 P3 3 PO 1 TCLOO P0 3 BUZ P1 1 INT1 P1 3 INT4 10199uu0o U d 0p Figure 20 3 40 Pin Connectors for TB573316A Target Board J101 J102 39 40 79 80 Target Cable for 40 Pin Connector Part Name AS40D A Order Code SM6306 Target System 4102 J101 12 39 40 Figure 20 4 TB573316A Adapter Cable for 80 QFP Package 557 3316 KS57C3316 P3316 SEG14 P10 2 SEG16 P11 0 SEG18 P11 2 SEG20 P12 0 SEG22 P 12 2 SEG24 P13 0 SEG26 P13 2 2 0 2 2 VCOFM VSS1 FMIF EO P3 0 P3 2 PO 0 BTCO P0 2 TCLO P1 0 INTO P1 2 INT2 P4 0 SCK ELECTRONICS
16. 11 4 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER BASIC TIMER COUNTER BCNT BONT is an 8 bit counter for the basic timer It can be addressed by 8 bit read instructions A chip reset leaves the BCNT counter value undetermined BCNT is automatically cleared to logic zero whenever the BMOD register control bit BMOD 3 is set to 1 to restart the basic timer It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected When has incremented to hexadecimal OFFH 255 clock pulses it is cleared to and an overflow is generated The overflow causes the interrupt request flag IRQB to be set to logic one When the interrupt request is generated BCNT immediately resumes counting with incoming clock signal NOTE Always execute a BONT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing If after two consecutive reads the BCNT values match you can select the latter value as valid data Until the results of the consecutive reads match however the read operation must be repeated until the validation condition is met TIMER OUTPUT ENABLE REGISTER TOE Disable timer counter 0 output Enable timer counter O output Disable basic timer overflow output Enable basic timer overflow output The basic timer s sequence of operations may be summarized as follows BASIC TIMER OPERA
17. EN CPSE EA HL RET is not skipped That is the subroutine returns since the result of the comparison is not equal ELECTRONICS 5 49 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec DECS Decrement and Skip on Borrow DECS dst Ro Decrement register R skip on borrow RR Decrement register pair RR skip on borrow Description destination is decremented by one An original value of will underflow to OFFH If a borrow occurs a skip is executed The carry flag value is unaffected Ro skip on borrow a alo oe RR lt RR 1 skip on borrow Pea Os ae a Examples 1 Register pair HL contains the value 7FH 01111111B The following instruction leaves the value 7EH in register pair HL DECS HL 2 Register A contains the value OH The following instruction sequence leaves the value OFFH in register A Since a borrow occurs the CALL PLAY1 instruction is skipped and the CALL PLAY2 instruction is executed DECS A Borrow occurs CALL PLAY1 Skipped CALL PLAY2 Executed 5 50 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET DI Disable Interrupts DI Operation Operation Summary Bytes Cycles Description Bit 3 of the interrupt priority register IPR IME is cleared to logic zero disabling all interrupts Interrupts can still set their respective interrupt status latches but the CPU will not dir
18. Vpp voltage below Vip P0 2 P1 P4 0 P4 2 P amp CE 0 8 RESET IH3 Input low All input pins except those specified 0 3 d voltage below Vio 2 P1 P4 0 P4 2 P5 P6 CE and 0 2 Vpp RESET XTour Output high Vpp 4 5 V to 5 5 V EO Vpp 2 0 voltage 1mA Other output ports 1mA Output low Vout Vpp 4 5 to 5 5 V EO 2 0 voltage lg 1 Vpp 45V to 5 5 V Other output ports 10 mA leakage All input pins currentnote Input low luL 0 leakage All input pins current te Output high ILOH Vout leakage All output pins currentnote NOTE Except for Xin 2 Xour XTIN and XTour ELECTRONES 17 3 ELECTRICAL DATA KS57C3316 P3316 Table 17 2 D C Electrical Characteristics Continued 25 C to 85 C 1 8V to 5 5V voltage 0 2 voltage 0 2 voltage 0 2 COM output Vpp 5V Vico COM 1 0 3 lO 15pA 1 0 3 SEG output Vpp 5V Vigo 0 3 voltage IO 15 12 0 3 deviation 120 IN LCD output voltage deviation Oscillator Vpp 5 0 V Ta 25 C feed back X V 0V resistors Vpp 5 0 V Ta 25 C 1500 3000 XI XT our 0 V Pull down Vpp 5 0 V Von resistor VCOFM VCOAM AMIF and FMIF Pll up Resistor 0 V
19. interrupt to jump incorrectly to the INTS address and causes a CPU malfunction to occur ELECTRONICS ADDRESS SPACES KS57C3316 P3316 INSTRUCTION REFERENCE AREA Using 1 byte REF instructions you can easily reference instructions with larger byte sizes that are stored in addresses 0020 007 of program memory This 96 byte area is called the REF instruction reference area or look up table Locations in the REF look up table may contain two 1 byte instructions one 2 byte instruction or one 3 byte instruction such as a JP jump or CALL The starting address of the instruction you are referencing must always be an even number To reference a JP or CALL instruction it must be written to the reference area in a two byte format for JP this format is for CALL it is TCALL By using REF instructions you can execute instructions larger than one byte you can save program code size In summary there are three ways you can use the REF instruction Using the 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch instruction stored in the look up table Calling subroutines at any location by referencing a call instruction stored in the look up table 59 PROGRAMMING TIP Using the REF Look Up Table Here is one example of how to use the REF instruction look up table ORG 0020H JMAIN TJP MAIN 0 MAIN KEYCK BTSF KEYFG 1 KEYFG CHECK WATCH TC
20. leakage All output pins current note Output low Vour OV leakage All output pins current note NOTE Except for Xin Xour XT np and 19 4 ELECTRONICS 53 7335 7335 Parameter Vico output voltage Output voltage Vice output voltage COM output voltage deviation SEG output voltage deviation LCD output voltage deviation Oscillator feed back resistors Pull down resistor Pull up resistor ELECTRONICS S3P7335 OTP Table 19 4 D C Electrical Characteristics Continued 40 to 85 Vpp 1 8V to 5 5V 0 6 Vpp Vico 25 0 2 Vice 25 0 2Vpp 0 2 0 2 Vpp 0 2 45 Vee Mass BU Wien OMS 120 Vos 5V Vigo 0 m i Rosc1 Vpp 5 0 V 25 Xn Xoyr 0 V Rosc2 Vpp 5 0 V TA 25 XTn XT gut 0 V i vot TN VCOFM VCOAM AMIF and FMIF 1500 3000 4500 Ports 1 2 3 4 5 and 6 0 2 0 2 70 300 15 25 50 R5 Vy 0V Vpp 5 RESET 200 53 7335 53 7335 7335 Table 19 4 D C Electrical Characteristics Concluded TA 407 to 85 C 18 to 5 5 V Symbol Conditions Supply Ipp 2 Main operating Current 1 PCON 0011B SCMOD 0000B CE Vpp Crystal oscillator C1 C2 22 pF Vpp 5 V 10 2 CE Low mate PCON 0011 SCMOD 00
21. 64 ELECTRONES PRODUCT OVERVIEW Instruction Execution Times 0 9 1 8 14 2 us at 4 5 MHz e 122 us at 32 768 kHz subsystem Operating Temperature e 25 C to 85 Operating Voltage Range e 1 8V to 5 5 V at 3MHz e operation 2 5V to 3 5V or 4 0V to 5 5V Package Type e 80 pin QFP 1 3 PRODUCT OVERVIEW 3C7335 P7335 BLOCK DIAGRAM PO 2 TCLO RESET XTIN Imer Timer Timer PO SIBUZ CE Xour XTour PINTI imer Pt 2 INT2 1 3 4 Interrupt Instruction i 2 0 Control Register VO Port 2 Block Counter 2 2 Program 5 VCOFM Internal Counter y EO P2 3 P3 1 D 5 VO Port 3 Interrupts BIAS P3 0 P3 3 LOD Driver VLCO VLC2 Controller Serial Instruction Decoder Program VO Port Status Word P13 0 P13 3 Arithmetic SEG24 SEG27 Output Port P12 0 P12 3 P4 0 SCK and 11 12 13 SEG20 SEG23 P4 1 SO VO Port 4 Logic Unit Stack P11 0 P11 3 d Pointer SEG16 SEG19 10 0 10 3 P5 0 ADCO SEG12 SEG15 PS2 ADE2 5 Output Port gt sede P5 3 ADC3 7 8 9 10 P8 0 P8 3 512 x 4 Bit 16K Byte 4 A D Data Memory Program Memory SEGO SEG3 Converter VO Port 6 P6 0 P6 3 KS0 KS3 e 4 Figure 1 1 S3C7335 Simplified Block Diagram 1 4 ELECTRONES KS57C3316 P3316 Preliminary Spec PRODUCT OVERVIEW PIN ASSIGNMENTS 08 3 MOS 0 vd 62 vINI E Ld L E3 LI
22. ht rt E rots To fas or Fe po oo fas Lar Second Byte Bit Addresses ee 1 1 bt Examples 1 Bit location 30H 2 the RAM has a current value of logic one The following instruction clears the third bit in RAM location 30H bit 2 to logic zero 30H 2 30H 2 lt 0 2 You can use BITR in the same way to manipulate a port address bit P1 0 1 0 lt 0 ELECTRONICS 5 31 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BITR Bit Reset BITR Continued Examples 3 Assuming that P2 2 P2 3 and P3 0 P3 3 are cleared to 0 LD L 0AH BP2 BITR P1 L First 1 P2 2 111100B 10B 10B OF2H 2 INCS L JR BP2 4 If bank 0 location 0 is cleared and regardless of whether the EMB value is logic zero BITR has the following effect FLAG EQU 0 LD H 0AH BITR H FLAG Bank 0 OAOH 0 lt 0 NOTE Since the BITR instruction is used for output functions the pin names used in the examples above may change for different devices in the SAM47 product family 5 32 ELECTRONICS 557 3316 3316 SAM47 INSTRUCTION SET BITS Bit Set BITS dst b H DA b Description This instruction sets the specified bit within the destination without affecting any other bits in the destination BITS can manipulat
23. ELECTRONICS 12 7 LCD CONTROLLER DRIVER KS57C3316 P3316 Static and 1 3 Bais V 3V at V DD 5V 1 2 Bais VLCD 2 5V at V 5V BIAS Pin VLCD Static and 1 3 Bais V 5V at V 5V Voltage Dividing Registor Adjustment VLCD 5V VLC2 R Option Votage Dividing Resistor By setting LMOD 7 R External Resistor Figure 12 4 Voltage Dividing Resistor Circuit Diagrams 12 8 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER Figure 12 5 LCD Signal Waveforms in Static Mode ELECTRONICS 12 9 LCD CONTROLLER DRIVER KS57C3316 P3316 2 Eris COM Possible 2 55 Figure 12 6 LCD Connection Example Static Mode 12 10 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER 4 1 2VLCD 0 1 2VLCD VLCD VLCD 1 2VLCD SSSR 1 2VLCD E VLCD Figure 12 7 LCD Signal Waveforms at 1 2 Duty 1 2 Bias ELECTRONICS 12 11 LCD CONTROLLER DRIVER KS57C3316 P3316 Timing Strobe x SR skor SE 26 Er Figure 12 8 LCD Connection Example at 1 2 Duty 1 2 Bias 12 12 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER Vss VLCo VLC1 2 Vss VLCO VLC1 2 VSS VLCO VLC1 2 Vss VLCD 41 2VLCD 0 1 2VLCD VLCD VLCD 1 2V LCD 0 1 2VLCD VLCD VLCD 4
24. ERR eu SERERE 5 13 Instruction Descriptions ee ionic ettet eod bete iu nete EE e td etate Pete Da aL e abet 5 23 vi KS57C3316 P3316 MICROCONTROLLER Table of Contents Continued Part Il Hardware Descriptions Chapter 6 Oscillator Circuits QU M EE 6 1 Main System Oscillator 4 6 4 Subsystem Oscillator CitCults tto tea ter ED ee er Rod Do debe eed e Rd ela Rl Perak a ede auos 6 4 Power Gontrol Register PGON tens eai tee itera eire tra El eX eei see D ERE rea ec ee Xo ua etu xe Bie dua e ee 6 5 TGS 6 6 System Clock Mode Register 5 6 7 Switching the CPU GIOCK 6 10 Clock Output Mode Register ene en eene hene n nnne tren nnns 6 12 Clock Output GIL CUL ea rec e te teet hg tee 6 13 Clock Output Procedures gees c ARA 6 13 Chapter 7 Interrupts VGN 7 1 pe ER ROI rait cr tet 7 5 Interrapt Priority Register ted tete EE idee x ber uua Ripe Deer ERR HE nn OUS 7 7 External Interrupt 0 and 1 Mode Registers IMODO
25. KS57C3316 P3316 MICROCONTROLLER List of Register Descriptions Register Full Register Name Page Identifier Number ADMOD ADG Mode utet pt Po secant uus 4 8 AFLAG ADG FLAG Register iioi itane eo e LR ODE HERE nU MOL EM 4 9 APCON ADC and Port Control Fegister citet rr e Code e eb eO eda dus 4 10 BMOD Basic Timer Mode Register 3 3 4 11 CLMOD Clock Output Mode nnne nnns enne nnn 4 12 IE0 1 IRQO 1 INTO 1 Interrupt Enable Request 5 4 13 IE2 IRQ2 INT2 Interrupt Enable Request 0 4 14 1 4 IRQ4 INT4 Interrupt Enable Request Flags 4 15 IEB IRQB Interrupt Enable Request 0 4 15 IRQCE Interrupt Enable Request 0 4 16 IRQIF INTIF Interrupt Enable Request 4 16 IES IRQS INTS Interrupt Enable Request 0 4 17 IETO IRQTO INTTO Interrupt Enable Request 0 4 18 IEW IRQW INTW Interrupt Enable Request 0 4 19 IFMOD IF Counter Mode 4 20 IMODO External Interrupt 0 INTO Mode 4 21 IMOD1 External Inte
26. IE1 2 lt X 49 7 7 ELECTRONICS 4 3 MEMORY KS57C3316 P3316 Table 4 1 Map for Memory Bank 15 Continued Memory Bank 15 oe Mode FCAH PLLREG ULFG CEFG IFCFG Yes The Address FCBH FCFH are not mapped FDOH CLMOD The Address FD2H FD5H not mapped FD6H PNE10 PNE7 W No Yes Lv pem rons The Address FDEH FDFH not mapped The Address FE2H FE3H are not mapped FE4H SBUF R W FESH a PUMO 2 FE6H PMGO PUMO 3 PUMO 2 PUMO 1 PUMO 0 FE7H 1 PM2 3 PM2 0 9 BN PM3 3 PM3 0 FEAH PMG2 4 3 4 0 Bol PM5 3 5 0 PMG3 PM6 3 FEDH v The Address FEEH FEFH are not mapped 2 2 A Yes 4 4 ELECTRONICS 557 3316 3316 MEMORY Table 4 1 for Memory Bank 15 Continued Memory Bank 15 Addressing Mode Yes Yes NOTES 1 WMOD register is read only 2 Thecarry flag can be read or written by specific bit manipulation instructions only 3 The ADSTR bit of the AFLAG register is 1 or 4 bit write only but the EOC bit is 1 or 4 bit read only Yes Yes The Address FFEH FFFH are not mapped ELECTRONICS 4 5
27. clear frequency dividing circuits able watch timer 1 En 4 Watch Timer Speed Control Bit High speed operation set IRQW to 3 91 ms Normal speed set IRQW to 0 5 seconds fel 0 Watch Timer Clock Selection Bit Select system clock fxx 128 as the watch timer clock 1 Select a subsystem clock as the watch timer clock NOTE system reset sets WMOD 3 to the current input level of the subsystem clock XT If the input level is high WMOD 3 is set to logic one if low WMOD 3 is cleared to zero along with all the other bits in the WMOD register 4 46 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set includes 1 bit 4 bit and 8 bit instructions for data manipulation logical and arithmetic operations program control and CPU control I O instructions for peripheral hardware devices are flexible and easy to use Symbolic hardware names can be substituted as the instruction operand in place of the actual address Other important features of the SAM47 instruction set include 1 byte referencing of long instructions REF instruction Redundant instruction reduction string effect Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction Several instructions have multiple operand formats Predefined values or labels can be used as instruction operands when addressing immediate data
28. ey ey oe ae 0000 PLL Enable Pulse Swallow Method In the above example each time NF bit value LSB is inverted the VCO oscillation frequency varies by 25 kHz To simplify programming it is therefore better not to use the NF bit In the next example the reference frequency is calculated in multiples of 25 KHz and the NF bit is not used Example fV 6 _ _ 100 0 10 7 x 10 2214 decimal fg 2 x 25 x 109 8A6H hexadecimal ELECTRONICS 15 9 PLL FREQUENCY SYNTHESIZER KS57C3316 P3316 ENERO EXE EXER PLMOD NF PLL Enable Pulse Swallow Method Don t care As this example shows all 16 bits the 16 PLLD bits except for the NF bit are used for the pulse swallow method When you use the direct method only the most significant 12 bits of the PLLD value PLLD3 PLLD2 and PLLD1 are evaluated 15 10 ELECTRONICS KS57C3316 P3316 INTERMEDIATE FREQUENCY COUNTER INTERMEDIATE FREQUENCY COUNTER OVERVIEW The KS57C3316 uses an intermediate frequency counter IFC to counter the frequency of the AM or FM signal at FMIF or AMIF pin The IFC block consists of a 1 2 divider gate control circuit IFC mode register IFMOD and a 16 bit binary counter The gate control circuit which controls the frequency counting time is programmed using the IFMOD register Four different gate times can be selected using IFMOD register settings During gate time the 16 bit IFC counts the input frequency at the FMIF or
29. falling signal edge 1 Interrupt requests are triggered by both rising and falling signal edges Interrupt request flag IRQO cannot be set to logic one 4 21 MEMORY KS57C3316 P3316 IMOD1 External Interrupt 1 INT1 Mode Register FB5H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 3 1 Bits 3 1 Always logic zero 0 External Interrupt 1 Edge Detection Control Bit ES Rising edge detection Falling edge detection 4 22 ELECTRONICS KS57C3316 P3316 MEMORY MAP IMOD2 External Interrupt 2 INT2 Mode Register FB6H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 4 4 3 and 2 Bit 3 2 Always logic zero 1 0 External Interrupt Mode Control Bits Interrupt requests at 2 triggered by rising edge 1 Interrupt requests at KS2 KS3 triggered by falling edge Interrupt requests at KSO KS3 triggered by falling edges ELECTRONICS 4 23 MEMORY KS57C3316 P3316 IPR Interrupt Priority Register FB2H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 1 4 4 4 4 IME Interrupt Master Enable Bit ES Disable all interrupt processing Enable processing for all interrupt service requests 2 0 External Interrupt Mode Control Bits Normal interrupt handling according to default priority settings DEJES Process INTB and INT4 interrupt at highest priority Process INTO interrupt at highes
30. this bit is cleared to 0 automatically Instruction that clear the watchdog timer BITS WDTCF should be executed at proper points in a program within a given period If not executed within a given period and watchdog timer overflows A system reset is generated internally and system is restarted with reset status 4 44 ELECTRONICS KS57C3316 P3316 MEMORY MAP WDMOD watchdog Timer Mode Register F99H F98H Bit 7 6 5 4 3 2 1 0 RESET Value 1 0 1 0 0 1 0 1 Read Write W W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 WDMOD Watchdog Timer Enable Disable Control 5AH Disable watchdog timer function Any other value Enable watchdog timer function ELECTRONICS 4 45 MEMORY KS57C3316 P3316 WMOD watch Timer Mode Register F89H F88H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 note 0 0 0 Read Write W R W Bit Addressing 8 8 8 1 8 8 8 7 Enable Disable Buzzer Output Bit Disable buzzer BUZ signal output Enable buzzer BUZ signal output 6 Bit 6 Always logic zero 5 4 Output Buzzer Frequency Selection Bits 2 kHz buzzer BUZ signal output ES 4 kHz buzzer BUZ signal output 1 8 kHz buzzer BUZ signal output 1 16 kHz buzzer BUZ signal output 3 XTiN Input Level Control Bit Input level to XTjn pin is low 1 bit read only addressable for tests Input level to XTin pin is high 1 bit read only addressable for tests 2 Enable Disable Watch Timer Bit Disable watch timer
31. 1 ELECTRONICS 4 29 MEMORY KS57C3316 P3316 PLLREG PLL status Register FCAH Bit 3 2 1 0 Identifier ULFG cEFG o RESET Value note note note note Read Write R R R Bit Addressing 1 4 1 4 1 4 ULFG PLL Frequency Synthesizer Locked Unlocked Status Flag PLL is currently in locked state fel PLL is currently in unlocked state CEFG CE Pin Level Status Flag CE pin is currently Low level fe CE pin is currently High level IFCFG IF Counter Gate Open Close Status Flag Gate is currently open Gate is currently close 0 Not used Always logic zero NOTE When a system reset occurs during operation mode the value of ULFG is undefined CEFG is current state of CE is the current state of the CE pin and IFCFG is 0 When a system reset occurs after power on the value of ULFG is undefined CEFG is the current state of the CE pin and IFCFG is undefined 4 30 ELECTRONICS KS57C3316 P3316 MEMORY MAP PLMOD PLL Mode Register FC8H Bit 3 2 1 0 RESET Value note note note note Read Write W W Bit Addressing 4 4 4 4 3 Frequency Division Method Selection Flag Direct method for Pulse swallow method for FM 2 PLL Enable Disable Bit Disable PLL Enable PLL 4 Bit Value Loaded into PLLDO Register NF bit is loaded into the LSB of swallow counter 0 Select the PLL Operation Voltage Select the PLL operation voltage as 4 0 V to 5 5 V
32. 1 Conversion clock fxx 4 NOTE stands for the system clock ELECTRONICS 4 KS57C3316 P3316 APCON ADC and Port Control Register FAEH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 4 4 4 4 3 Pin P5 3 input Selection Bit ADC input or Normal Port Input Connect to a normal input block digital signal input Connect to a ADC block analog signal input 2 Pin P5 2 input Selection Bit ADC input or Normal Port Input Connect to a normal input block digital signal input Connect to a ADC block analog signal input 1 Pin P5 1 input Selection Bit ADC input or Normal Port Input EZ Connect to a normal input block digital signal input Connect to a ADC block analog signal input 0 Pin P5 0 input Selection Bit ADC input or Normal Port Input Connect to a normal input block digital signal input 1 Connect to a ADC block analog signal input NOTE If the specific ports were set as a normal input mode don t connect an analog signals ELECTRONICS KS57C3316 P3316 MEMORY MAP Basic Timer Mode Register F85H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 1 4 4 4 3 Basic Timer Restart Bit Restart basic timer then clear IRQB flag BCNT BMOD 3 to logic zero 2 1 Input Clock Frequency and Signal Stabilization Interval Control Bits Input clock frequency 212 1 098 kHz Signal stabilization interval 220
33. 4 bit mode register BMOD 8 bit counter register BCNT Output enable flag BOE 8 bit watchdog timer mode register WDMOD Watchdog timer counter clear flag WDTCF The basic timer generates interrupt requests at precise intervals based on the frequency of the system clock Basic timer s counter register BCNT outputs timer pulses to the watchdog timer s counter register WDTCNT when an overflow occurs in BCNT You can use the basic timer as a watchdog timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following chip reset Bit settings in the basic timer mode register BMOD turns the BT on and off selects the input clock frequency and controls interrupt or stabilization intervals Interval Timer Function The measurement of elapsed time intervals is the basic timer s primary function The standard interval is 256 BT clock pulses To restart the basic timer set bit 3 of the mode register BMOD to logic one The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD 2 BMOD 0 The 8 bit counter register BCNT is incremented each time a clock signal is detected that corresponds to the frequency selected BMOD continues incrementing as it counts BT clocks until an overflow occurs An overflow causes the BT interrupt request flag IRQB to be set to logic one to
34. 557 3316 3316 SAM47 INSTRUCTION SET XCHD Exchange and Decrement XCHD dst src A HL Exchange A and data memory contents decrement 1 2 5 contents of register L and skip borrow Description instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L If the content of register L is OFH the next instruction is skipped The value of the carry flag is not affected A HL 1 a 1 1 A e HL thenL e L 1 skip if L OFH Example Register pair HL contains the address 20H and internal RAM location 20H contains the value OFH LD HL 20H LD A 0H XCHD A HL A lt OFHandL lt L 1 HL lt 0 JPS XXX Skipped since a borrow occurred JPS YYY H lt 2H L lt 0 YYY XCHD A HL 2FH lt lt 2FH L L 1 JPS YYY instruction is executed since skip occurs after the XCHD instruction ELECTRONICS 5 91 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec Exchange and Increment XCHI dst src A HL Exchange A and data memory contents increment 1 2 5 contents of register L and skip on overflow Description instruction exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L If the content of register L is OH a skip is executed The value
35. H DAb 1 1 1 1 1 o 1 Skip if H DA 3 0 b 1 and clear bt a2 at Second Byte Bit Addresses Seine Bt lhe ies ee et 1 1 Examples 1 Port pin P2 0 is toggled by checking the P2 0 value level BISTZ P2 0 If P2 0 1 then P2 0 lt 0 and skip BITS P2 0 If P2 0 0 then P2 0 lt 1 JP LABEL3 2 Assume that port pins P2 2 P2 3 and 0 are toggled LD L 0AH BP2 BTSTZ P1 L First P1 90AH P2 2 111100B 10B 10B 2 2 RET INCS L JR BP2 ELECTRONICS 5 41 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BTSTZ Test and Skip on True Clear Bit BTSTZ Continued Examples 3 Bank 0 location 0 is tested and EMB 0 FLAG EQU 0 BITR EMB LD H 0AH BISTZ H FLAG If bank 0 AH OH 0 OAOH O 1 clear and skip BITS H FLAG IfOAOH 0 0 then 1 NOTE Since the BTSTZ instruction is used for input output functions pin names used in the examples above may change for different devices in the SAM47 product family 5 42 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET BXOR Bit Exclusive OR BXOR C src b Exclusive OR carry with memory bit SS C memb L C H DA b Description specified bit of the source is logically XORed with the carry bit value The resultant bit is written to the carry f
36. LCD controller operates All external interrupts are acknowledged All CPU operations All CPU operations All CPU operations CPU operates are disabled are disabled are disabled normally IFC stops IFC stops IFC operates IFC stops PLL stops PLL stops PLL operates PLL stops A D converter A D converter is A D converter is A D converter operates A D converter operates disabled disabled Mode release signal Interrupt request signals except INTO CE or RESET input NOTES Interrupt request signals except INTO CE or RESET input Interrupt request signals CE or RESET input CE pin high 1 mode is not controlled by an instruction but rather by directly modifying the state of the external CE pin 2 INTO can release Idle mode only when fxx 64 is selected as a sampling clock 8 2 ELECTRONICS KS57C3316 P3316 POWER DOWN IDLE MODE TIMING DIAGRAMS Oscillation Idle Stabilization Instruction 29 1 ms 4 5 MHz Idle Mode Normal Mode Normal Oscillation Figure 8 1 Timing When ldle Mode is Released by RESET Idle Instruction Mode v Release Signal Normal Mode Idle Mode Normal Mode Normal Oscillation Figure 8 2 Timing When Idle Mode is Released by an Interrupt ELECTRONICS 8 3 POWER DOWN KS57C3316 P3316 STOP MODE TIMING DIAGRAMS Oscillation Stabilization 29 1 ms 4 5 MHz 1 Stop Instruction Normal Mode S
37. Logical OR OR dst src Logical OR immediate data to A HL Logical OR indirect data memory contents to RRb EA Logical OR EA to double register Description The source operand is logically ORed with the destination operand The result is stored in the destination The contents of the source are unaffected Operand Binary Code Operation Notation A im 1 OR im a2 ao eqno IHE RN 1 1 110 RRb EA Example If the accumulator contains the value 1100001 1B and register pair HL the value 55H 01010101B the instruction OR EA leaves the value 0D7H 11010111B in the accumulator ELECTRONICS 5 71 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec POP Pop From Stack POP dst Pop SMB and SRB values from stack Description contents of the RAM location addressed by the stack pointer is read and the SP is incremented by two The value read is then transferred to the variable indicated by the destination operand RRL lt SP lt SP 1 SP lt 2 SRB lt SP SMB lt SP 1 SP lt 2 Example The SP value is equal to OEDH and RAM locations OEFH through OEDH contain the values 2H 3H and 4H respectively The instruction POP HL leaves the stack pointer set to OEFH and
38. MEMORY KS57C3316 P3316 REGISTER DESCRIPTIONS In this section register descriptions are presented in a consistent format to familiarize you with the memory mapped locations in bank 15 of the RAM Figure 4 1 describes features of the register description format Register descriptions are arranged in alphabetical order Programmers can use this section as a quick reference source when writing application programs Counter registers and reference registers as well as the stack pointer and port I O latches are not included in these descriptions More detailed information about how these registers are used is included in Part II of this manual Hardware Descriptions in the context of the corresponding peripheral hardware module descriptions 4 6 ELECTRONICS KS57C3316 P3316 MEMORY MAP Register and bit IDs Name of individual used for bit addressing bit or related bit Associated Register location Register ID Register name hardware module in RAM bank 15 CLMOD Clock Output Control Register CPU Bit 3 2 1 0 Identifi cene Read Write WwW Bit Addressing 4 T 4 4 4 CLMOD 3 Enable Disable Clock Output Control Bit 0 Disable clock output 1 Enablectockoutput CLMOD 2 Bit 2 GETTE CLMOD 1 0 Clock Source and Frequency Selection Control 1 dock tove
39. ORG 0100H 20 REF Al LD HL 00H 21 REF A2 LD HL 03H 22 REF A3 LD HL 05H 23 REF A4 LD HL 10H 24 REF A5 LD HL 26H 25 REF A6 LD HL 08H 26 REF A7 LD 27 8 LD HL 0FOH 30 REF 9 LD HL 67H 31 REF A10 CALL SUB1 32 REF 11 JP SUB2 ELECTRONICS 5 77 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec RET Return From Subroutine RET Description RET pops the PC values successively from the stack incrementing the stack pointer by six Program execution continues from the resulting address generally the instruction immediately following a CALL or CALLS p lt SP 1 SP 7 0 SP 3 SP 2 lt SP 4 1 ERB lt SP 4 0 SP SP 6 Example The stack pointer contains the value RAM locations OFCH and OFDH contain 1H 0H 5H and 2H respectively The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H During a return from subroutine PC values are popped from stack locations as follows 5 78 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET RRC Rotate Accumulator Right Through Carry RRC A Operation Operation Summary Bytes Cycles Description four bits in the accumulator and the carry flag are together rotated one bit to the right Bit 0 moves into the carry flag and the original carry v
40. 1 Select the PLL operation voltage as 2 5 V to 3 5 V NOTE If a system reset occurs during operation mode the current value contained is retained If a system reset occurs after power on the value is undefined ELECTRONICS 4 3 MEMORY KS57C3316 P3316 Port 1 0 Mode Control Register Port 0 FE7H FE6H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Bit Addressing 8 8 8 8 7 4 Not used Always logic zero PMO 3 Mode Selection Bit Set P0 3 to input mode Set P0 3 to output mode 2 0 2 Mode Selection Bit Set P0 2 to input mode fel Set P0 2 to output mode 1 0 1 Mode Selection Bit Set P0 1 to input mode je Set P0 1 to output mode PM0 0 P0 0 Mode Selection Bit Set P0 0 to input mode 1 Set P0 0to output mode 4 32 ELECTRONICS KS57C3316 P3316 MEMORY MAP 1 Port yo Mode Control Register Port 2 and Port 3 FE8H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W Bit Addressing 8 8 8 8 8 8 8 8 PM3 3 P3 3 Mode Selection Bit Set P3 3 to input mode 1 Set P3 3 to output mode PM3 2 P3 2 Mode Selection Bit Set P3 2 to input mode 1 Set P3 2 to output mode PM3 1 P3 1 Mode Selection Bit Set P3 1 to input mode 1 Set P3 1 to output mode PM3 0 P3 0 Mode Selection Bit Set P3 0 to input mode 1 Set P3 0 to output mode PM2 3 P2 3 Mode Selection Bit Set
41. 1 and assuming the carry flag is already set to 1 SMB 15 BAND C P1 0 If P1 0 1 1 If P1 0 0 lt 0 2 Assume the P1 address is FF1H and the value for register L is 1001 The address memb 7 2 is 111100B L 3 2 is 10B The resulting address is 11110010B or FF2H specifying P2 The bit value for the BAND instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD L 9H BAND C P1 L P1 L is specified as P2 1 AND P2 1 ELECTRONICS 5 29 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BAND Bit Logical And BAND Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BAND instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BAND C H FLAG AND FLAG 20H 3 5 30 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET BITR Bit Reset BITR dst b Operation Operan Operation Summary Bytes Clear specified memory bit to logic zero 2 2 memwa H DA b Description A BITR instruction clears to logic zero resets the specified bit within the destination operand No other bits in the destination are affected operand Binary ode Operation Notation DA b 1 4 DAb O
42. 1 8V to 5 5V Clock Parameter Test Condition Typ Configuration Ceramic Oscillation frequency 2 7 V to 5 5 V Oscillator 1 Stabilization time 2 Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Crystal Oscillation frequency Vpp 2 7 V to 5 5 V Oscillator 1 Stabilization time 2 4 5 V to 5 5 V External Xy input frequency 1 0 4 Clock Xy input high and low 83 3 level width bj tx 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only NOTES 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs or when stop mode is terminated 17 6 ELECTRONES KS57C3316 P3316 ELECTRICAL DATA Table 17 4 Subsystem Clock Oscillator Characteristics 25 C 85 Vg 1 8V to 5 5 V Crystal Oscillator External XTN Clock input high and low level width txTH NOTES 1 Oscillation frequency and XTINinput frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs ELECTRONES 17 7 ELECTRICAL DATA KS57C3316 P3316 Table 17 5 Input Output Capacitance 25 C Vpp 0 V Input 1 MHz Unmeasured capacitance pins are returned to Ves Output Cour capacitance capacitance Table 17 6 A C Electrical Character
43. 12 5 LCD Clock Signal LCDCK and Frame 12 6 12 6 LCD Port Control Register nennen 12 6 12 7 12 7 xvi KS57C3316 P3316 MICROCONTROLLER List of Tables Concluded Table Title Page Number Number 13 1 A D Converter Component 13 2 13 2 A D Converter Mode Register 13 3 13 3 A D Converter Control Flag 0 13 4 14 1 SIO Mode Register SMOD 14 3 15 1 PEMOD Organization ege rode E E 15 5 15 2 PLLREF Register Organization 15 6 16 1 FMOD Organization OE e EE ERU es 16 2 16 2 IF Counter Frequency m eem eee enn 16 6 17 1 Absolute Maximum mme mme 17 2 17 2 Electrical Characteristics ciet re 17 3 17 3 Main System Clock Oscillator 17 6 17 4 Subsystem Clock Oscillator Characteristics 17 7 17 5 Input Output Capacitarice iis ny eene 17 8 17 6 A
44. 15 2 ELECTRONICS 557 3316 3316 PLL FREQUENCY SYNTHESIZER PLL DATA REGISTER PLLD The frequency division value of the swallow counter and programmable counter is set in the PLL data register PLLDO PLLD3 Figure 15 2 shows the PLL data register configuration The PLLD register can be manipulated using 4 bit and 8 bit RAM control instructions Programmable Counter Swallow Counter Upper 12 bits Lower 5 bits 16 15 14 13 12 11 10 9 8 7 6 5 PLMOD PLLREF 1 21 Address FC7H Figure 15 2 PLL Register Configuration Direct Frequency Division and Pulse Swallow Formulas In the direct frequency division method the upper 12 bits are valid In the pulse swallow method all 16 bits are valid The upper 12 bit are set in the programmable counter and the lower 4 bits and the NF bit are set in the swallow counter The frequency division formulas for both methods as set in the PLL data register are shown below Direct frequency division AM is fVcoAM R N Where the frequency division value is 12 bits fV coap input frequency at the Pulse swallow system FM is R N where the frequency division value is 16 bits fV coFM input frequency at the pin ELECTRONICS 15 3 PLL FREQUENCY SYNTHESIZER KS57C3316 P3316 REFERENCE FREQUENCY GENERATOR The reference frequency generator produce reference frequency which are then compared by the phase comparator
45. As shown in Figure 15 3 the reference frequency generator divides a crystal oscillation frequency of 4 5 MHz and generates the reference frequency fp for the PLL frequency synthesizer Using the PLLREF register you can select from ten different reference frequencies Data Bus 3 kHz 5 kHz Frequency 6 25 kHz Divider To Phase Detector 4 5 MHz gt 100 kHz Figure 15 3 Reference Frequency Generator 15 4 ELECTRONICS KS57C3316 P3316 PLL FREQUENCY SYNTHESIZER PLL MODE REGISTER PLMOD The PLL mode register PLMOD is used to start and stop PLL operation PLMOD values also determine the frequency dividing method PLMOD 3 selects the frequency dividing method The basic configuration for the two frequency dividing methods are as follows Direct Method Used for AM mode Swallow counter is not used VcoamPin is selected for input Pulse Swallow Method Used for FM mode Swallow counter is used Vcoew is selected for input The input frequency at the pin is divided by the programmable divider The frequency division value of the programmable divider is written to the PLL data register When the pulse swallow method is selected by setting PLMOD 3 the input signal is first divided by a 1 32 or 1 33 prescaler and the divided frequency is input to the programmable divider PLMOD can be written using 4 bit RAM control instructions Table 15 1 shows P
46. Call Procedure CALL dst operation Operation Summary ADR14 Call direct address 14 bits Description CALL calls a subroutine located at the destination address The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack decreasing the stack pointer by six and ERB are also pushed to the stack Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16K bytes program memory address space operand Binary Code operation Notation 1 1 1 1 1 1 SP 1 SP 2 EMB ERB SP 3 SP 4 PC7 0 1 13 12 a11 a10 SP 5 SP 6 lt PC13 8 SP SP 6 sr as e ss 19 0 Example The stack pointer value is and the label PLAY is assigned to program memory location OE3FH Executing the instruction CALL PLAY at location 0123H will generate the following values SP OH OFEH EMB ERB OFDH 2H 6H OFBH OH OFAH 1H PC Data is written to stack locations OFFH OFAH as follows OFAH OFBH OFCH OFDH o J o ewe Ene 0 ELECTRONICS 5 45 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec CALLS Procedure Short CALLS dst Description Example 5 46 ADR11 Call direct address wi
47. Clock Output Mode Register CLMOD Organization CPU clock fx 4 fx 64 fxt 4 1 125 2 562 5 kHz 70 3 KHz 8 19 KHZ fens CLMOD 3 Result of CLMOD 3 Setting Clock output is disable Clock output is enable NOTE Frequencies assume that fxx 4 5 MHz 6 12 ELECTRONICS 557 3316 3316 OSCILLATOR CIRCUITS CLOCK OUTPUT CIRCUIT The clock output circuit which is used to output clock pulses to the CLO pin has the following components see Figure 6 6 4 bit clock output mode register CLMOD Clock selector output latch Port mode flag CLO output pin P4 3 CLMOD 3 CLMOD 2 CLMOD 1 CLOCK SELECTOR p CLOCKS CPU clock fxx 8 fxx 16 fxx 64 CLMOD 0 Figure 6 6 CLO Output Pin Circuit Diagram CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the CLO pin may be summarized as follows Disable clock output by clearing CLMOD 3 to logic zero Set the clock output frequency CLMOD 1 CLMOD 0 Load a 0 to the output latch of the CLO pin P4 3 Set the P4 3 mode flag PM 4 3 to output mode Enable clock output by setting CLMOD 3 to logic one amp PROGRAMMING TIP CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin BITS EMB SMB 15 LD EA 08H LD PMG2 EA 4 3 lt Output mode BITR P4 3 Clear P4 3 output latch LD A 9H LD CLMOD A ELECTRONICS 6 13 OSCILLATOR
48. EMB and the enable ERB 0 1 register bank flag ERB and program counter to vector ADR address then branch to the corresponding location Table 5 10 Program Control Instructions High Level Summary CPSE R im Compare and el if equals im 2 EA HL Compare and skip FEA equals indirect data memoy 2 2 5 gt emu rect address 9 ump arectin a page Tabi 2 wx Bren ow regs 3 serrate Tef 020 3 omis omn Cal rect access 2 9 3 L3 2 wvv AIJU N d ELECTRONICS 5 9 SAM47 INSTRUCTION SET KS57C3316 P3316 LDI DD LDC RRC Table 5 11 Data Transfer Instructions High Level Summary 2 Exchange EA and register pair RRb contents A HL Exchange A and indirect data memory contents increment contents of register L and skip on carry Exchange A and indirect data memory contents decrement contents of register L and skip on carry Load 4 bit immediate data to A N 42 2 2 42 A RRa Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 8 bit immediate data to register Load contents of A to direct data memory HL EA Load contents of EA to indirect data memory A HL Load indirect data memory
49. IRET you do not need to set the EMB and ERB values again Instead use BITR and BITS to clear these values in your program routine The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction These addresses must be stored ROM locations 0000 Generally the VENTn instructions are coded starting at location 0000H The format for VENT instructions is as follows VENTn di d2 ADDR EMB lt d1 0 or 1 ERB lt d2 0 or 1 ADDR address to branch device specific module address code 0 Operand BiarCode 000 Code Operation Notation EMB 0 1 a13 12 11 a10 EMB ERB lt ROM 2x n 7 6 ERB 0 1 PC13 12 ROM 2 x n 5 4 ADDR 11 8 lt ROM 2 x n 3 0 PC7 0 ROM 2 x n 1 7 0 n 0 1 2 3 4 5 6 7 Fer as e so a0 5 88 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET VENT Load EMB ERB and Vector Address VENTn Continued Example The instruction sequence ORG 0000H VENTO 1 0 VENT1 0 1 INTB VENT2 0 1 0 VENT3 VENTA _ 0 1 INTS VENT5 0 1 INTTO causes the program sequence to branch to the RESET routine labeled RESET setting EMB to 1 and ERB to 0 when a system reset is activated When a basic timer interrupt is generated VENT1 causes the program to branch to the basic timer s interrupt service routine and to set the EMB
50. Input Output Output 4 bit I O ports 1 bit 4 bit or 8 bit read write and test are possible Pull up resistors can be configured by software Ports 4 and 5 can be paired to support 8 bit data transfer 4 bit I O port 1 bit 4 bit or 8 bit read write and test are possible Pull up resistors can be configured by software 2 2 3 4 5 6 7 8 9 10 11 1 bit or 4 bit output port Alternatively used for LCD segment output CO 1 bit or 4 bit output port Alternatively used for LCD segment output 3 1 bit 4 bit output Alternatively used for LCD segment output Co CO ON 1 bit or 4 bit output port Alternatively used for LCD segment output 28 5 1 6 ELECTRONES KS57C3316 P3316 Preliminary Spec PRODUCT OVERVIEW Table 1 1 S3C7335 Pin Descriptions Continued Pin Description Reset Circuit Type Value Type 1 bit or 4 bit output port 44 Output 28 Alternatively used for LCD segment output 1 bit or 4 bit output port Output 28 Alternatively used for LCD segment output 1 bit or 4 bit output port Output 28 Alternatively used for LCD segment output Common signal output for LCD display 24 27 Emme mI LCD power supply Input Voltage dividing resistors are assignable by software MainGround 113 er eset pn SS Crystal or ceramic oscillator
51. Memory addressing area 00H 7FH 2 12 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES PUSH OPERATIONS Three kinds of push operations reference the stack pointer SP to write data from the source register to the stack PUSH instructions CALL instructions and interrupts In each case the SP is decreased by a number determined by the type of push operation and then points to the next available stack location PUSH Instructions A PUSH instruction references the SP to write two 4 bit data nibbles to the stack Two 4 bit stack addresses are referenced by the stack pointer one for the upper register value and another for the lower register After the PUSH has executed the SP is decreased by two and points to the next available stack location CALL Instructions When subroutine call is issued the CALL instruction references the SP to write the PC s contents to six 4 bit stack locations Current values for the enable memory bank EMB flag and the enable register bank ERB flag are also pushed to the stack Since six 4 bit stack locations are used per CALL you may nest subroutine calls up to the number of levels permitted in the stack Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word PSW to the stack Six 4 bit stack locations are used to store this data After the interrupt has executed the SP is decreased by six and points to the next available sta
52. Ports 7 13 pin addresses are in bank 1 of the RAM The contents of I O port pin latches can be read written or tested at the corresponding address using bit manipulation instructions Port Mode Flags Port mode flags PM are used to configure ports to input or output mode by setting or clearing the corresponding buffer PM flags are stored in five 8 bit registers and are addressable by 8 bit write instructions only Output Ports 7 13 Output ports 7 13 consists of 28 pins that can be used either for LCD segment data output or for normal output Bit settings in the LPOT determine the port output mode LCD or normal output mode for specific ports 7 13 pins Pull Up Resistor Mode Register PUMOD The pull up mode registers PUMOD is a 8 bit register used to assign internal pull up resistors by software to specific ports When a configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting PUMOD are addressable by 8 bit write instructions only A system reset clears PUMOD register values to logic zero automatically disconnecting all software assignable port pull up resistors ELECTRONICS 10 1 PORTS KS57C3316 P3316 Table 10 1 Port Overview Pin Names Address Function Description P0 0 P0 3 FFOH 4 bit I O port 1 bit and 4 bit read write and test are possible 4 bit pull up re
53. Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IE4 Bit 3 Disable INT4 interrupt requests 1 Enable INT4 interrupt requests IRQ4 Bits 2 Generate INT4 interrupt This bit is set and cleared automatically by hardware when the rising and falling edge detected at external INT4 pin Interrupt Enable Flag Disable INTB interrupt requests 1 Enable INTB interrupt requests IRQB INTB Interrupt Request Flag Generate INTB interrupt This bit is set and cleared automatically by hardware when reference interval signal received from basic timer ELECTRONICS 4 1 557 3316 3316 Interrupt Enable Request Flags FBBH IEIF IRQIF interrupt Enable Request Flags FBBH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IEIF IRQIF IRQCE IEIF Interrupt Enable Flag Disable INTIF interrupt Enable INTIF interrupt 1 IRQIF interrupt Request Flag Generate INTIF interrupt This bit is set and cleared by hardware whenever the specified gate time has elapsed INTCE Interrupt Enable Flag Disable INTCE interrupt requests at the CE pin 1 Enable INTCE interrupt requests at the CE pin INTCE Interrupt Request Flag Generate INTCE interrupt This bit is set and cleared by hardware where a falling edge is detected at the CE pin ELECTRONICS KS57C3316 P3316 MEMORY MAP IES IRQ
54. System is operating with sub clock NOTES 1 This mode must not be used STOP instruction Only main oscillator stops CPU is in idle mode Sub oscillator still runs or stops Set SCMOD 3 to 1 1 Only main oscillator stops CPU is in idle mode Sub oscillator still runs or stops STOP instruction 1 Only main oscillator stops CPU is in idle mode Sub oscillator still runs Set SCMOD 3 to 1 Only main oscillator stops CPU still operates Sub oscillator still runs Set SCMOD 2 to 1 Main oscillator still runs CPU operates Only sub oscillator stops Set SCMOD 2 to 1 Main oscillator still runs or stops CPU is in idle mode Only sub oscillator stops Interrupts CE or RESET signal After stop mode released main oscillation starts and oscillation stabilization time is elapsed And then the CPU operates Oscillation stabilization time is 1 256 x BT clock CE or RESET signal Interrupts can t start the main oscillation Therefore the CPU operation can never be restarted Basic timer overflow CE or RESET signal After the overflow of basic timer 1 256 x BT clock fxt CPU operation and main oscillation automatically start Set SCMOD 3 to 0 CE or a system reset Set SCMOD 3 to 0 CE or a system reset RESET signal 2 Oscillation stabilization time by interrupt is 1 256 x BT clocks Oscillation stabilization tim
55. and the carry flag is set to 1 SCF 1 SBC EA HL EA lt 1H lt 0 5 Jump to no skip after SBC 2 If the extended accumulator contains the value register pair HL the value OAAH and the carry flag is cleared to 0 RCF 0 SBC EA HL EA 19H C lt 0 JPS XXX Jump to XXX no skip after SBC 5 80 ELECTRONICS KS57C3316 P3316 SBC subtract With Carry SBC Continued SAM47 INSTRUCTION SET Examples 3 If SBC A HL is followed by an ADS A im the SBC skips on borrow to the instruction immediately after the ADS An ADS A im instruction immediately after the A HL instruction does not skip even if an overflow occurs This function is useful for decimal adjustment operations 8 6 decimal addition the contents of the address specified by the HL register is 6H A 8H SBC A HL ADS A 0AH JPS XXX C lt 0 lt 8H A lt 8H 6H 0 2H C lt 0 Skip this instruction because no borrow after SBC result b 3 4 decimal addition the contents of the address specified by the HL register is RCF LD A 3H SBC A HL ADS A 0AH JPS XXX ELECTRONICS C lt 0 A lt A C 0 OFH lt 1 No skip lt OAH 9H The skip function of ADS A im is inhibited after a SBC A HL i
56. and very high frequency VHF signals to a fixed frequency using a phase difference comparison system As shown in Figure 15 1 the PLL frequency synthesizer consists of an input selection circuit programmable divider phase detector reference frequency generator and a charge pump Swallow Counter Input Circuit Hh Figure 15 1 Block Diagram of the PLL Frequency Synthesizer ELECTRONICS 15 1 PLL FREQUENCY SYNTHESIZER KS57C3316 P3316 PLL FREQUENCY SYNTHESIZER FUNCTION The PLL frequency synthesizer divides the signal frequency at the pin using the problemmable divider It then outputs the phase difference between the divided frequency and reference frequency at the EO pin NOTE The PLL frequency synthesizer operates only when the CE pin is High level When the CE pin is Low level the synthesizer is disable Input Selection Circuit The input selection circuit consists of the VcoAM pin and VcoFM pins FM AM selector and two amplifiers The input selection circuit selects the frequency division method and the input pin of the PLL frequency You can choose one of two frequency division methods using the PLL mode register 1 direct frequency division method 2 pulse swallow method The PLL mode register is also used to select the pin as the frequency input pin Programmable Divider The programmable divider divides the frequency of the signal from the Vcoam
57. for main system 14 clock For external clock input use and input 15 XN S reverse phase to Crystal oscillator pin for subsystem clock For 18 external clock input use XT jy and input XT ys reverse 17 phase to XT Test signal input must be connected to V gg for 16 normal operation Input pin for checking device power 67 Input B 5 Normal operation is high level and PLL IFC operation is stopped at low level VCOFM External VCOFM AM signal inputs 60 Input C 61 PLU sphaseerroroutput 5 PLL sphaseemorouput error output 66 Output m intermediate frequency signal inputs 64 Input B 4 EN power supply power supply a ELECTRONES 1 7 PRODUCT OVERVIEW 3C7335 P7335 Table 1 1 S3C7335 Pin Descriptions Concluded Pin Description Reset Circuit Type Value Type BTCO Basic timer overflow output signal 72 Poo Input D2 TCLOO Timer counter 0 clock output signal TCLO External clock input for timer counter 0 Pree BUZ 2 4 8 or 16 kHz frequency output for buzzer sound for Input D 2 4 19 MHz main system clock or 32 768 kHz subsystem clock INTO External interrupt The triggering edges rising falling P1 0 Input INT1 are selectable Only INTO is synchronized with B P1 1 system clock INT2 Quasi interrupt with detection of rising edge signal 78 P1 2 INT4 External interrupt input with detec
58. lt P4 046 047 lt lt E lt E Non essential instruction since 0 lt 046 E lt 047H lt 146 E 147H ADDRESSING MODES KS57C3316 P3316 NOTES 3 12 ELECTRONICS 557 3316 3316 MEMORY OVERVIEW To support program control of peripheral hardware I O addresses for peripherals are memory mapped to bank 15 of the RAM Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location Access to bank 15 is controlled by the select memory bank SMB instruction and by the enable memory bank flag EMB setting If the EMB flag is 0 bank 15 can be addressed using direct addressing regardless of the current SMB value 1 bit direct and indirect addressing can be used for specific locations in bank 15 regardless of the current EMB value MAP FOR HARDWARE REGISTERS Table 4 1 contains detailed information about I O mapping for peripheral hardware in bank 15 register locations F80H FFFH Use the I O map as a quick reference source when writing application programs The I O map gives you the following information Register address Register name mnemonic for program addressing Bit values both addressable and non addressable Read only write only or read and write addressability 1 bit 4 bit or 8 bit data manipulation characteristi
59. lt 00H WX WX WX Current PC13 8 01H WX 0100H Jump to address 0100H and execute JPS AAA Address lt A EA lt Jump to address 0200H Address 30H lt 0H If LD EA 01H were to be executed in place of LD EA 00H the program would jump to 0101H and address 30H would contain the value 1H If LD EA 02H were to be executed the jump would be to 0102H and address 30H would contain the value 2H ELECTRONICS 5 59 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec LD Load LD dst src ADA Load drect data memory conenstoa Am 2 Load ata 2 mmm Load Bt immediate daa register 2 Daa Load contents ot A to dct datamemoy 2 maa oed comens orato reser 2 EAGHL data memory conons o EA tADA Load drect data memory coments toaa regster Load contents ot Ato irdrectr data memoy Daea owes m rnmj rnmj rnm DA EA Load contents of EA to data memory RRb EA Load contents of EA to register HL EA Load contents of EA to indirect data memory Description contents of the source are loaded into the destination The source s contents are unaffected If an instruction such as LD A im LD EA imm or LD HL imm is written more than two times
60. 1 2VLCD 1 2VLCD VLCD Figure 12 9 LCD Signal Waveforms at 1 3 Duty 1 2 Bias ELECTRONICS 12 13 LCD CONTROLLER DRIVER 12 14 Figure 12 10 LCD Signal Waveforms at 1 3 Duty 1 3 Bias KS57C3316 P3316 1 3VLCD J 3V LCD VLCD VLCD 1 3VLCD P 3VLCD VLCD VLCD D HS VERD 1 3VLCD VLCD ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER Timing Strobe SEG8 SEG9 SEG10 num xm atta oH to ar seat SEG19 Hun a SEG21 efef see olol E2 xx 1011 5507 Figure 12 11 LCD Connection Example at 1 3 Duty 1 3 Bias ELECTRONICS 12 15 LCD CONTROLLER DRIVER 12 16 Figure 12 12 LCD Signal Waveforms at 1 4 Duty 1 3 Bias KS57C3316 P3316 1 0 1 VLCD VLCD 1 0 1 3VLCD ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER Timing mongo sees SEM AHHH secas sEG2s Figure 12 13 LCD Connection Example at 1 4 Duty 1 3 Bias ELECTRONICS 12 17 LCD CONTROLLER DRIVER KS57C3316 P3316 NOTES 12 18 ELECTRONICS 557 3316 3316 A D CONVERTER ANALOG TO DIGITAL CONVERTER OVERVIEW The 8 bit A D converter ADC module uses a successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 8 bit digital values The analog input level mus
61. 20H 3 FLAG EQU 20H 3 LD H 2H BOR C H FLAG OR FLAG 20H 3 5 36 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET BTSF Bit Test and Skip on False BTSF dst b Operation Operand Operation Summary cycles Test specified memory bit and skip if bit equals 0 memas memwa H DA b Description specified bit within the destination operand is tested If it is 0 the BTSF instruction skips the instruction which immediately follows it otherwise the instruction following the BTSF is executed The destination bit value is not affected operand Binay Code Operation notation DA b 1 4 1 O skipitDAb 0 rar as Tos as uz at 1 skpitmemab 0 memb L Skip if memb 7 2 L 3 2 L 1 0 0 La aa H DAb 1 1 1 1 0 5 010 0 bo at Second Byte Bit Addresses 0 bt eo a2 jar Farr 1 4 bt bo a2 at Examples 1 If RAM bit location 30H 2 is set to logic zero the following instruction sequence will cause the program to continue execution from the instruction identified as LABEL2 BTSF 30H 2 If 30H 2 0 then skip RET If 30H 2 1 return JP LABEL2 2 You can use BTSF in the same way to manipulate a port pin address bit BTSF P2 0 I
62. 5 5 V Data retention supply current Vpppr 1 8 V 0 1 1 ELECTRONES 17 11 ELECTRICAL DATA KS57C3316 P3316 TIMING WAVEFORMS Internal RESET Operation Stop Mode gt gt Idle Mode lt gt 4 Operating Mode Data Retention Mode VDD Execution of STOP Instruction RESET Figure 17 2 Stop Mode Release Timing When Initiated by RESET Idle Mode lt tr Stop Mode 77 Bist lt Normal Operating Data Retention gt Mode VDDDR Execution of STOP Instruction Power down Mode Terminating Signal Interrupt Request Figure 17 3 Stop Mode Release Timing When Initiated by an Interrupt Request 17 12 ELECTRONES KS57C3316 P3316 ELECTRICAL DATA 0 8 VDD 08 VDD Measurement Points 0 2 VDD 0 2 VDD Figure 17 4 A C Timing Measurement Points Except for VDD 0 1 V 0 1 V Figure 17 5 Clock Timing Measurement at XIN 1 fxt gt VDD 0 1 V 0 1 V Figure 17 6 Clock Timing Measurement at XTIN ELECTRONES 17 13 ELECTRICAL DATA KS57C3316 P3316 Figure 17 7 Input Timing for RESET Signal INTO 1 2 4 KSO to KS2 Figure 17 8 Input Timing for External Interrupts and Quasi Interrupts 17 14 ELECTRONES KS57C3316 P3316 MECHANICAL DATA MECHANICAL DATA OVERVIEW This section contains the following information about the device package
63. 5 5 V 0 67 time 1 TCLO input fi Vpp 27V to 5 5V 1 5 frequency Vpp 1 8 V to 5 5V low width Vo 18V to 55V SCK cycle time m ERU 27V to 55V E ns External SCK source Internal SCK source SCK Internal SCK source Vpp 1 8 V to 5 5 V 3200 External SCK source width External SCK source RH extemal SCK source SI setup time to External SCK source SCK high Internal SCK source SI hold time to External SCK source SCK high Internal SCK source Output delay for Vpp 2 7 to 5 5 SCK to SO External source Internal SCK source SCK source Co 1 8 V to 5 5V ESTE SCK source Internal source SCK source NOTE Unless otherwise specified Instruction Cycle Time condition values assume amain system clock 4 fx 4 source 17 10 ELECTRONES KS57C3316 P3316 ELECTRICAL DATA CPU Clock Main Oscillator Frequency 15MHz eco T T 1 0475 MHz L1 419 MHz NEN Ss T 1 3 4 Supply Voltage V CPU Clock 1 x oscillator frequency 4 8 or 64 When operation operating voltage range is 2 5 V to 3 5 V or 4 0 V to 5 5 V Figure 17 1 Standard Operating Voltage Range Table 17 7 RAM Data Retention Supply Voltage in Stop Mode TA 25 85 Conditions Tw Unit Data retention supply voltage Normal operation 1 8
64. 573316 20 6 TB573316A Adapter Cable for 80 QFP Package 53 7335 20 6 KS57C3316 P3316 MICROCONTROLLER xiii Table Number 1 1 2 1 2 3 2 4 2 5 2 6 2 7 3 1 3 2 3 4 5 1 5 2 5 3 5 4 5 5 5 7 5 8 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 20 List of Tables Title Page Number S3C7335 P3316 Pin Descriptions 20 0001 ener nnne nnne 1 6 Program Memory Address 2 1 Data Memory Organization and Addressing 2 7 Working Register Organization and Addressing pp 2 9 BSG Register Organization ect or cete enr e ca oe er Pao elie Od X ROCHE ODE 2 15 Program Status Word Bit Descriptions 2 16 Interrupt Status Flag Bit 0 2 17 Valid Carry Flag Manipulation Instructions mm 2 20 RAM Addressing Not Affected by the EMB 3 4 1 Bit Direct and Indirect RAM 3 6 4 Bit Direct and Indirect RAM 00 3 8 8 Bit Direct and Indirect RAM Addressing 3 10 Map for Memory Bank AE R E 4 2 Valid 1 Byte Instruction Combinations for REF Look Ups
65. 8 ms 4 gt 4 Counting Period 5 Gate open here Counting ends IFMOD is written IFCFG flag is set to 1 and IFCFG flag is cleared to 0 IRQIF is set to 1 9 Figure 16 2 Gate Timing 1 4 or 8 ms ELECTRONICS 16 3 INTERMEDIATE FREQUENCY COUNTER KS57C3316 P3316 Selecting Gate Remains Open If you select gate remain open IFMOD 0 and IFMOD 1 1 the IFC counts the input signal during the open period of the gate The gate closes the next time a value is written to IFMOD Clock 1 kHz n e Gate Time q Counting Period The gate closes when IFMOD is rewritten Gate is opened by writing IFMOD Figure 16 3 Gate Timing When Open When you select gate remains open as the gating time you can control the opening and closing of the gate in one of two ways Set the gate time to a specific interval 1 ms 4 ms or 8 ms by setting bits IFMOD 1 and IFMOD 0 Gate Time gt Set IFMOD 1 IFMOD 0 1 Set non open gate time 1 4 8 ms by bit IFMOD 1 and IFMOD O Disable IFC operation by clearing bits IFMOD 3 and IFMOD 2 to 0 This method lets the gate remain open and stops the counting operation Gate Time gt 6 Set IFMOD 1 IFMOD 0 1 Set IFMOD 3 IFMOD 2 0 IFC counting operation is sto
66. C Electrical Characteristics aeoaea ae e 17 8 17 7 RAM Data Retention Supply Voltage in Stop 17 11 19 1 Pin Descriptions Used to Read Write the 19 3 19 2 Comparison of KS57P3316 and S3C7335 Features 19 3 19 3 Operating Mode Selection eee 19 3 19 4 D C Electrical 19 4 19 5 Main System Clock Oscillator 19 7 19 6 Subsystem Clock Oscillator Characteristics e 19 8 19 7 Input Output 19 9 19 8 Electrical 19 9 19 9 RAM Data Retention Supply Voltage in Stop 19 12 20 1 Power Selection Settings for 573316 20 4 20 2 Pin Selection Settings for 573316 20 4 20 3 Sub clock Selection Settings for TB573316A 20 5 KS57C3316 P3316 MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2 Address Spaces Defining Vectored AE nennen nnne 2 3 Using the REF L
67. DAb 1 1 1 1 1 o H DA3 0b ES Exc MN C mema b ELL fet tet C amp C AND ee eee C memb L AND memb 7 2 L 3 2 L 1 0 Pro o s os C H DA b spree C C AND H DA 3 0 b o o bt bo aa at a0 C mema b fee C C OR memab C memb L OR memb 7 2 1 3 2 L 1 0 a o as a 2 C H DA b C C H DA 3 0 b Madii ee ae C mema b C amp C C memb L 1 C XOR memb 7 2 L 3 2 L 1 0 es a C H DAb 1 1 1 1 1 C C XOR H DA3 0 b bt bo Second Byte BitAddresses Addresses 1 1 ae at FFonFF ELECTRONICS 5 21 SAM47 INSTRUCTION SET KS57C3316 P3316 Table 5 20 Bit Manipulation Instructions Binary Code Summary Concluded omne ETE Te mn 0 a5 at a2 GH DAbC 1 1 1 1 1 o H DA3 01b lt 2 poe lt memb7 L 3 2 L 1 0 2242 7 C H DAb 1 1 1 1 0 0 CcIH DA3 0 b Second Byte Bit Addresses DOCO 7000 fos ae at ao ORR 5 22 ELECTRONICS 557 3316 3316 SAM47 INSTRUCTION SET INSTRUCTION DESC
68. Flag SCF Description SCF instruction sets the carry flag to logic one regardless of its previous value Eee If the carry flag is cleared to logic zero the instruction SCF sets the carry flag to logic one ELECTRONICS 5 83 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec SMB select Memory Bank SMB n Description SMB instruction sets the upper four bits of a 12 bit data memory address to select a specific memory bank The constants 0 and 15 are usually used as the SMB operand to select the corresponding memory bank All references to data memory addresses fall within the following address ranges Please note that since data memory spaces differ for various devices in the SAM47 product family the n value of the SMB instruction will also vary 000H 01FH Working registers 020H 0FFH Stack and general purpose registers OEAH OFFH Display registers F80H FFFH hardware registers The enable memory bank EMB flag must always be set to 1 in order for the SMB instruction to execute successfully for memory banks 0 and 15 Format Binary Code Operation Notation o os e ar Example If the EMB flag is set the instruction SMB 0 selects the data memory address range for bank 0 000 as the working memory bank 5 84 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET SRB
69. Flags SC2 SC1 5 0 2 20 Carry Flag eti ite e oe pe e eo be E HE Tode Eb c oH e 2 20 KS57C3316 P3316 MICROCONTROLLER Table of Contents Continued Chapter 3 Addressing Modes 91 21 3 1 and ERB Initialization 3 3 Enable Memory Bank Settings nnne tern nnne nnns 3 4 Select Bank Register SEN 3 5 Direct and Indirect Addressing pp 3 6 T Bit Addressitg cicero et Lap ctt e 3 6 4 Bit Addressing eS 3 8 8 te eat ee A ee eet ete 3 10 Chapter 4 Memory Map 4 1 for Hardware Registers 4 1 Register Descriptions 7 rice re cepe er eei ed ee 4 6 Chapter 5 SAM47 Instruction Set e LET 5 1 Instruction Set e tea e Eno 5 1 Symbols and Goriventions ie leis OaE ANAE iba e 22 5 6 Opcode Defiriitioris gh E COLE n REOR RO LIA Co du EA 5 7 Calculating Additional Machine Cycles for 5 7 HighisEevel Summary 5 8 Binary Gode Sutmimaly 2 3 tea
70. H DA b Load carry bit to a specified indirect memory bit Load specified memory bit to carry bit C memb QL Load specified indirect memory bit to carry bit _ b 5 12 a KS57C3316 P3316 SAM47 INSTRUCTION SET BINARY CODE SUMMARY This Chapter contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy to read tabular format It is intended to be used as a quick reference source for programmers who are experienced with the SAM47 instruction set The same binary values and notation are also included in the detailed descriptions of individual instructions later in Chapter 5 If you are reading this user s manual for the first time please just scan this very detailed information briefly Most of the general information you will need to write application programs can be found in the high level summary tables in the previous Chapter The following information is provided for each instruction Instruction name Operand s Binary values Operation notation The tables in this Chapter are arranged according to the following instruction categories CPU control instructions Program control instructions transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions ELECTRONICS 5 13 SAM47 INSTRUCTION SET KS57C3316 P3316 Table 5 15 CPU Control Instructions Binary Code S
71. LD 90H A 090H lt A bank 0 is selected LD 34H A 034H lt A bank 0 is selected SMB 15 Select memory bank 15 LD 20H A Program error but assembler does not detect it LD 90H A F90H lt A bank 15 is selected 2 18 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES ERB FLAG ERB The 1 bit register bank enable flag ERB determines the range of addressable working register area When the ERB flag is 1 the working register area from register banks 0 to 3 is selected according to the register bank selection register SRB When the ERB flag is register bank 0 is the selected working register area regardless of the current value of the register bank selection register SRB When an internal reset is generated bit 6 of program memory address 0000H is written to the ERB flag This automatically initializes the flag When a vectored interrupt is generated bit 6 of the respective address table in program memory is written to the ERB flag setting the correct flag status before the interrupt service routine is executed During the interrupt routine the ERB value is automatically pushed to the stack area along with the other PSW bits Afterwards it is popped back to the 0 bit location The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions PROGRAMMING Using the ERB Flag to Select Register Banks ERB flag settings for register bank selection 1 When ER
72. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA mema memb b and so on Using instruction labels can greatly simplify program writing and debugging tasks INSTRUCTION SET FEATURES In this Chapter the following SAM47 instruction set features are described in detail Instruction reference area Instruction redundancy reduction Flexible bit manipulation ADC and SBC instruction skip condition ELECTRONICS 5 1 SAM47 INSTRUCTION SET KS57C3316 P3316 Instruction Reference Area Using the 1 byte REF Reference instruction you can reference instructions stored in addresses 0020H 007FH of program memory the REF instruction look up table The location referenced by REF may contain either two 1 byte instructions or a single 2 byte instruction The starting address of the instruction being referenced must always be an even number 3 byte instructions such as JP or CALL may also be referenced using REF To reference these 3 byte instructions the 2 byte pseudo commands TJP and TCALL must be written in the reference The PC is not incremented when a REF instruction is executed After it executes the program s instruction execution sequence resumes at the address immediately following the REF instruction By using REF instructions to execute instructions larger than one byte as well as branches and subroutines you can reduce the program size To summarize the REF in
73. Package dimensions in millimeters Pad diagram Pad pin coordinate data table 23 90 0 30 gt 80 1420 e o N 0 80 0 20 0 05 MIN 2 65 0 10 3 00 MAX 0 80 0 20 Figure 18 1 80 QFP 1420C Package Dimensions NOTE Dimensions are in millimeters ELECTRONICS MECHANICAL DATA KS57C3316 P3316 NOTES 18 2 ELECTRONICS 53 7335 7335 53 7335 S3P7335 OVERVIEW The S3P7335 single chip CMOS microcontroller is the One Time Programmable version of the 53 7335 microcontroller It has an on chip EPROM instead of masked ROM The EPROM is accessed by a serial data format S3P7335 is fully compatible with the 3 7335 both in function and in pin configuration Because of its simple programming requirements the S3P7335 is ideal for use as an evaluation chip for the 8307335 ELECTRONICS 19 1 53 7335 P4 1 SO P4 2 SI P4 3 CLO P5 0 ADCO P5 1 ADC1 P5 2 ADC2 P5 3 ADC3 P6 0 KSO P6 1 KS1 SDAT P6 2 KS2 SCLK P6 3 KS3 0 Vss Vss0O XOUT XIN VPP TEST XT IN XT OUT RESETRESET BIAS VLCO VLC1 VLC2 COMO 6 82 E3 cLNI C kd ZZ E3 92 L3 Ld GZ L3 Zn8 8 0d vL 0701 04 4 00 19L H 0d 61 OOL8 0 0d KS57P3316 80 QFP Top View 0 4 0945 Cj 8c 44 1995 C4 6c cZ4d cOdS 0 8 d 55
74. SHON eec eae el en ele 5 57 JR Jump Relative Very 5 56 KS57C3316 P3316 MICROCONTROLLER List of Instruction Descriptions Continued Instruction Full Instruction Name Page Mnemonic Number JR Jump Relative Very SOM RR COR PHAR RIED RE CE eta bu 5 59 LD HP 5 60 LD 5 61 LD LOA 5 62 LD 5 63 LDB EE 5 64 LDB LO AG 5 65 LDC Coad Gode Byte ince ee pascunt eta eec bas ne Eee Len be CO ED ARTE 5 66 LDC EDU OU Ba 5 67 LDD Load Data Memory and Decrement pp 5 68 NOP INGO peration eic etie ettet sates M RR EE 5 70 OR Logical Em 5 71 POP Pop From en N 5 72 PUSH Push Onto Stack ne ised PV dete uu naue eue den RUE Eee Hi 5 73 RCF Reset Carry e 5 74 REF Reference 5 75 Reference amp sc 5 76 REF Reference P feb re 5 77 Return Erom SubfoU
75. TCO output enable flag TOEO must be set to 2 mode flag for PO 1 PMO 1 must be set to output mode 1 Output latch value for PO 1 must be cleared to 0 Each time overflow and an interrupt request is generated the state of the output latch TOLO is inverted and the TCO generated clock signal is output to the TCLOO pin 59 PROGRAMMING TCO Signal Output to the TCLOO Pin Output a 30 ms pulse width signal to the TCLOO pin BITS EMB SMB 15 LD EA 79H LD TREFO EA LD EA 4CH LD TMODO EA LD EA 01H LD 1 lt output mode BITR PO 1 Clear 1 BITS TOEO 11 14 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER TCO SERIAL I O CLOCK GENERATION Timer counter 0 can supply a clock signal to the clock selector circuit of the serial interface for data shifter and clock counter operations These internal SIO operations are controlled in turn by the SIO mode register SMOD This clock generation function enables you to adjust data transmission rates across the serial interface Use TMODO and TREFO register setting to select the frequency and interval of the TCO clock signal to be used as SCK input to the serial interface The generated clock signal is then sent directly to the serial I O clock selector circuit not through the port 0 1 latch TCLOO pin the flag may be disabled TCO EXTERNAL INPUT SIGNAL DIVIDER By selection an ext
76. VO Mode Register ce ERA DE noth 4 41 TMODO Timer Mode Register ent Ede e opus 4 42 TOE Timer Output Enable 0 4 43 WDFLAG Watchdog Timer Counter Clear Flag Register esse 4 44 WDMOD Watchdog Timer Mode 4 45 WMOD Watch Timer Mode 4 46 xxii KS57C3316 P3316 MICROCONTROLLER Instruction Mnemonic ADC ADS ADS AND BAND BAND BITR BITR BITS BITS BOR BOR BTSF BTSF BTST BTST BTSTZ BTSTZ BXOR BXOR CALL CALLS CCF COM CPSE DECS D E IDLE INCS IRET JP KS57C3316 P3316 MICROCONTROLLER List of Instruction Descriptions Full Instruction Name Page Number Add WIR Garry inito tette bea et pt Po REC PH OL Pea ut E E COE HR RIED E CE eda but 5 24 Add And Skip On Overthow ss tote co HH EH E COLE HR IE Pe HORN Cd Ped eae 5 26 Add And Skip On Overflow oot tese fen a Oe e Cod ud 5 27 LO 5 28 Bit 5 29 LOgiCal 5 30 Er T OPER 5 81 I PERETES 5 32 zl E 5 33 5 34 5 35
77. and pins in accordance with the values contained in the swallow counter and programmable counter The programmable divider consists of prescalers a swallow counter and a programmable counter When the PLL operation starts the contents of the PLL data registers PLLDO PLLD3 and the NF bit in the PLMOD register are automatically loaded into the 12 bit programmable counter and the 5 bit swallow counter When the 12 bit programmable down counter reaches zero the contents of the data register are automatically reloaded into the programmable counter and the swallow counter for the next counting operation If you modify the data register value while the PLL is operating the new values are not immediately loaded into the two counters the new data are loaded into the two counters when the current count operation has been completed The contents of the data register undetermined after initial power on However the data register retains its current value when the reset operation is initiated by an external reset or a change in level at the CE pin The swallow counter is a 5 bit binary down counter the programmable counter is a 12 bit binary down counter The swallow counter is for FM mode only The swallow counter and programmable counter start counting down simultaneously When the swallow counter starts counting down the 1 33 prescaler is selected When the swallow counter reaches zero it stop operation and selects the 1 32 prescaler
78. and 1 He 7 8 External Interrupt 2 Mode Register IMOD2 aasssssesesssesnessernrreerrtieerrrieerrtteentrrecatteetnttecnntnenttteenntecennnne 7 10 7 12 Chapter 8 Power Down NI 8 1 Idle Mode Timitig Diagramss aee eid 8 3 Stop Mode Timing Diagraims tiui to eter CL peti P Rod Pre RR eod ea Reese 8 4 Port Pin Configuration for Power Down 8 6 Recommended Connections for Unused 8 7 Chapter 9 RESET TELE 9 1 Hardware Register Values after a System RESET eene n ener nnne nnns 9 3 KS57C3316 P3316 MICROCONTROLLER vii Table of Contents Continued Chapter 10 Ports OE 10 1 Port Mode Flags PM 5 10 3 Pull Up Resistor Mode Register 10 4 ADC and Port Control Register 10 5 N Channel Open Drain Mode Register 10 5 Pin Addressing for Output 7 13 10 6 Port 0 Gircuit DIagram ay Le an ee ec 10 7 10 8 2 3 Diagrams iere itin i ee tse 10 9 Port 4 Circuit Diag
79. and FMIF AMIF s feed back resistor Enable IFC operation AMIF pin is selected FMIF is pulled down and FMIF s feed back resistor is off Enable IFC operation FMIF is selected AMIF is pulled down and AMIF s feed back resistor is off Enable IFC operation Both AMIF and FMIF are selected PLL FLAG REGISTER PLLREG The PLL flag register PLLREG is a 4 bit read only register When IFC operation is started by setting IFMOD the IFC gate flag IFCFG is cleared to 0 After a specified gate time has elapsed the IFCFG bit is automatically set to 1 This lets you check whether a IFC counting operation has been completed or not The IFC interrupt can also be used to check whether or not a IFC counting operation is complete The reset value of IFCFG is O 16 2 ELECTRONICS KS57C3316 P3316 INTERMEDIATE FREQUENCY COUNTER GATE TIMES When you write a value to IFMOD the IFC gate is opened for a 1 millisecond 4 millisecond or 8 millisecond interval setting with a rising clock edge When the gate is open the frequency at the AMIF or FMIF pin is counted by the 16 bit counter When the gate closes the IFC gate flag IFCFG is set to 1 An interrupt is then generated and the IFC interrupt request flag IRQIF is set Figure 16 2 shows gate timings with a 1 kHz internal clock ceu ILE LE LEU UU UU UU LL LG 1 1 ims i 4 ms 1 1 1 1 1 1 1 1 1
80. carry flag after a system reset occurs during normal operation is undefined If a system reset occurs during power down mode IDLE or STOP the current value of the carry flag is retained 2 carry flag can only be addressed by a specific set of 1 bit manipulation instructions See Section 2 for detailed information 4 38 ELECTRONICS KS57C3316 P3316 MEMORY MAP PUMOD Pull Up Resistor Mode Register FDDH FDCH Bit 7 6 5 4 3 2 1 0 Identifier 7 6 5 4 3 2 o RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W Bit Addressing 8 8 8 8 8 8 8 7 Bit 7 Always logic zero 6 Connect Disconnect Port 6 Pull up Resistor Control Bit Disconnect port 6 pull up resistor 1 Connect port 6 pull up resistor 5 Connect Disconnect Port 5 Pull up Resistor Control Bit isconnect port 5 pull up resistor onnect port 5 pull up resistor 4 Connect Disconnect Port 4 Pull up Resistor Control Bit isconnect port 4 pull up resistor onnect port 4 pull up resistor 3 Connect Disconnect Port 3 Pull up Resistor Control Bit isconnect port 3 pull up resistor onnect port 3 pull up resistor 2 Connect Disconnect Port 2 Pull up Resistor Control Bit isconnect port 2 pull up resistor onnect port 2 pull up resistor 4 Connect Disconnect Port 1 Pull up Resistor Control Bit isconnect port 1 pull up resistor onnect port 1 pull up resistor 0 5 ect Disconnect Port 0 Pull up Resistor Contro
81. each falling edge of the SIO clock Receive data is simultaneously input from the SI pin P4 2 to SBUF at the rate of one bit for each rising edge of the SIO clock When receive only mode is used incoming data is input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock PROGRAMMING Setting Transmit Receive Modes for Serial I O 1 Transmit the data value 48H through the serial interface using an internal clock frequency of fx 24 and in MSB first mode BITS EMB SMB 15 LD EA 03H LD PMG2 EA P4 0 SCK and P4 1 SO lt Output LD EA 0E6H LD SMOD EA LD EA 48H LD SBUF EA BITS SMOD 3 SIO data transfer SCK P4 0 External 5 4 Device KS57C3316 2 Use CPU clock to transfer and receive serial data at high speed BITR EMB LD EA 03H LD PMG2 EA P4 0 SCK and P4 1 SO lt Output P4 2 SI lt Input LD EA 47H TDATA address 20 7 LD SMOD EA LD EA TDATA LD SBUF EA BITS SMOD 3 SIO start BITR IES SIO Interrupt Disable STEST BTSTZ IRQS JR STEST LD EA SBUF LD RDATA EA RDATA address 20H 7FH ELECTRONICS 14 5 SERIAL I O INTERFACE KS57C3316 P3316 52 PROGRAMMING Setting Transmit Receive Modes for Serial Continued 3 Transmit and receive an internal clock frequency of 4 39 kHz at 4 5 MHz in LSB first mode INTS 14 6 XCH LD BITS POP POP IRET EMB EA 03H PMG2 EA EA 87H SMOD EA
82. execution of a requested service routine the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines The flags are stored at the beginning of the program with the VENT instruction The initial flag values determine the vectors for resets and interrupts Enable flag values are saved during the main routine as well as during service routines Any changes that are made to enable flag values during a service routine are not stored in the vector address When an interrupt occurs the enable flag values before the interrupt is initiated are saved along with the program status word PSW and the enable flag values for the interrupt is fetched from the respective vector address Then if necessary you can modify the enable flags during the interrupt service routine When the interrupt service routine is returned to the main routine by the IRET instruction the original values saved in the stack are restored and the main program continues program execution with these values Software Generated Interrupts To generate an interrupt request from software the program manipulates the appropriate IRQx flag When the interrupt request flag value is set it is retained until all other conditions for the vectored interrupt have been met and the servi
83. flag initializing it automatically When a vectored interrupt is generated bit 7 of the respective vector address table is written to the EMB This automatically sets the EMB flag status for the interrupt service routine When the interrupt is serviced the EMB value is automatically saved to stack and then restored when the interrupt routine has completed At the beginning of a program the initial EMB and ERB flag values for each vectored interrupt must be set by using VENTR instruction The and ERB can be set or reset by bit manipulation instructions BITS BITR despite the current SMB setting 59 PROGRAMMING Initializing the EMB and ERB Flags The following assembly instructions show how to initialize the EMB and ERB flag settings ORG 0000H ROM address assignment VENTO 1 0 RESET lt 1 ERB lt 0 branch RESET VENT1 0 1 INTB lt 0 ERB lt 1 branch INTB VENT2 0 1 INTO lt 0 ERB lt 1 branch INTO VENT3 0 1 INT1 lt 0 ERB lt 1 branch INT1 VENT4 0 1 INTS lt 0 ERB lt 1 branch INTS VENT5 0 1 INTTO lt 0 ERB lt 1 branch INTTO VENT6 0 1 INTCE lt 0 ERB lt 1 branch INTCE VENT7 0 1 INTIF lt 0 ERB lt 1 branch INTIF RESET BITR EMB ELECTRONICS 3 3 ADDRESSING MODES KS57C3316 P3316 ENABLE MEMORY BANK SETTINGS 1 When the enable memory bank flag is set to logic one you can address the data memory
84. for the corresponding service routines The 16 byte area can be used alternately as general purpose ROM REF Instructions Locations 0020H 007FH are used as a reference area look up table for 1 byte REF instructions The REF instruction reduces the byte size of instruction operands REF can reference one 2 byte instruction two 1 byte instructions and 3 byte instructions which are stored in the look up table Unused look up table addresses can be used as general purpose ROM Table 2 1 Program Memory Address Ranges ROM Area Function Address Ranges Area Size in Bytes General purpose program memory 0010H 001FH REF instruction look up table area 0020H 007FH General purpose program memory 0080H 3FFFH 16 256 ELECTRONICS 2 1 ADDRESS SPACES KS57C3316 P3316 GENERAL PURPOSE MEMORY AREAS The 16 byte area at ROM locations 0010 001 and the 16 256 byte area at ROM locations 0080H 3FFFH are used as general purpose program memory Unused locations in the vector address area and REF instruction look up table areas can be used as general purpose program memory However care must be taken not to overwrite live data when writing programs that use special purpose areas of the ROM VECTOR ADDRESS AREA The 16 byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts The starting addresses of interrupt service routines are stored in this area along with the ena
85. free stack location IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET IRET references the SP to locate the six 4 bit stack addresses used for the interrupt and to write this data back to the PC and the PSW After the IRET has executed the SP is incremented by six and points to the next free stack location POP RET or SRET IRET SP 4 SP 2 SP 4 5 6 SP 4 SP 6 Upper Register PC13 PC12 PC3 PCO PC7 PC4 0 0 Figure 2 8 Pop Type Stack Operations 2 14 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES BIT SEQUENTIAL CARRIER BSC BUFFER The bit sequential carrier BSC is a 16 bit general register that can be manipulated using 1 4 and 8 bit RAM control instructions A system reset clears all BSC bit values to logic zero Using the BSC you can specify sequential addresses and bit locations using 1 bit indirect addressing nemb L Bit addressing is independent of the current EMB value In this way programs can process 16 bit data by moving the bit location sequentially and then incrementing or decreasing the value of the L register BSC data can also be manipulated using direct addressing For 8 bit manipulations the 4 bit register names BSCO and BSC2 must be specified and the upper and lower 8 bits manipulated separately If the values of the L register are at BSCO L the address and bit location assignment is FCOH O If the L register content is FH at BSCO L the add
86. in succession only the first LD will be executed the other similar instructions that immediately follow the first LD will be treated like a NOP This is called the redundancy effect see examples below 5 60 ELECTRONICS 557 3316 3316 LD Load LD Continued SAM47 INSTRUCTION SET Description Binary Gode maw mum i ioli eua i oaea irpo po 7 9 oacaparice Far as as s ue ur 20 owe Examples 1 RAM location 30H contains the value 4H The RAM location values are 40H 41H and OAH 3H respectively The following instruction sequence leaves the value 40H in point pair HL OAH in the accumulator and in RAM location 40H and 3H in register E LD HL 30H LD A HL LD HL 40H LD EA HL LD HL A ELECTRONICS HL lt 30H lt 4H lt 40H lt OAH E lt 40H lt OAH 5 61 SAM47 INSTRUCTION SET LD Load LD Continued KS57C3316 P3316 Preliminary Spec Examples 2 If an instruction such as LD A im LD EA imm or LD HL imm is written more than two times in succession only the first LD is executed the next instructions are treated as NOPs Here are two examples of this redunda
87. instruction is used in an interrupt service routine a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values as shown in Example 2 below 2 When ERB 1 VENT2 1 1 INTO lt 1 ERB lt 1 Jump to INTO address INTO PUSH SB Store current SMB SRB SRB 2 Select register bank 2 because of ERB 1 SMB 0 LD EA 00H LD 80H EA LD HL 40H INCS HL LD WX EA LD YZ EA POP SB Restore SMB SRB IRET ELECTRONICS 2 11 ADDRESS SPACES KS57C3316 P3316 STACK OPERATIONS STACK POINTER SP The stack pointer SP is an 8 bit register that stores the address used to access the stack an area of data memory set aside for temporary storage of data and addresses The SP can be read or written by 8 bit control instructions When addressing the SP bit 0 must always remain cleared to logic zero F80H SP3 SP2 se ow F81H SP7 SP6 SP5 SP4 There are two basic stack operations writing to the top of the stack push and reading from the top of the stack pop A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack The program counter contents and program status word PSW are stored in the stack area prior to the execution of a CALL or a PUSH instruction or during interrupt service routines Stack operation is a LIFO Last In First Out type The stack area is located in general purpose data memory
88. interrupts and subroutine calls A system reset clears the 4 bit SRB value to logic zero Select Memory Bank SMB Instruction To select one of the four available data memory banks you must execute an SMB n instruction specifying the number of the memory bank you want 0 1 or 15 For example the instruction SMB 1 selects bank 1 and SMB 15 selects bank 15 And remember to enable the selected memory bank by making the appropriate EMB flag setting The upper four bits of the 12 bit data memory address are stored in the SMB register If the SMB value is not specified by software or if a system reset does not occur the current value is retained A system reset clears the 4 bit SMB value to logic zero The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls ELECTRONICS 3 5 ADDRESSING MODES KS57C3316 P3316 DIRECT AND INDIRECT ADDRESSING 1 bit 4 bit and 8 bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand Indirect addressing specifies a memory location that contains the required direct address The KS57 instruction set supports 1 bit 4 bit and 8 bit indirect addressing For 8 bit indirect addressing an even numbered RAM address must always be used as the instruction operand 1 BIT ADDRESSING Table 3 2 1 Bit Direct and Indirect RAM Addressing N
89. interrupts are allowed The priority with which interrupts are processed is then determined by the IPR When an interrupt occurs 150 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level Then when the interrupt service routine ends with an IRET instruction ISO and 161 values are restored to the PSW Table 2 6 shows the effects of ISO and 151 flag settings Table 2 6 Interrupt Status Flag Bit Settings Status of Currently Effect of ISO and IS1 Settings Malus Executing Process on Interrupt Request Control All interrupt requests are serviced Only high priority interrupt s as determined in the interrupt priority register IPR are serviced more interrupt requests serviced Not applicable these bit settings are undefined Since interrupt status flags can be addressed by write instructions programs can exert direct control over interrupt processing status Before interrupt status flags can be addressed however you must first execute a DI instruction to inhibit additional interrupt routines When the bit manipulation has been completed execute an El instruction to re enable interrupt processing 59 PROGRAMMING Setting ISx Flags for Interrupt Processing The following instruction sequence shows how to use the ISO and 151 flags to control interrupt processing INTB DI Disable interrupt BITR 151 151
90. mode LD EA 40H LD PUMOD EA Enable P6 pull up resistors 7 10 ELECTRONICS KS57C3316 P3316 INTERRUPTS Rising Edge Detection P6 3 KS3 P6 2 KS2 P6 1 KS1 P6 0 KSO Falling Edge Detection Circuit Clock Selector NOTE To generate a key interrupt on a falling edge at KSO KS3 KSO KS3 pins must be configured to input mode Figure 7 6 Circuit Diagram for INT2 ELECTRONICS 7 11 INTERRUPTS KS57C3316 P3316 INTERRUPT FLAGS There are three types of interrupt flags interrupt request and interrupt enable flags that correspond to each interrupt the interrupt master enable flag which enables or disables all interrupt processing Interrupt Master Enable Flag IME The interrupt master enable flag IME enables or disables all interrupt processing Therefore even when an IRQx flag is set and its corresponding IEx flag is enabled the interrupt service routine is not executed until the IME flag is set to logic one The IME flag is located in the IPR register IPR 3 It can be directly be manipulated by El and DI instructions regardless of the current value of the enable memory bank flag EMB Inhibit all interrupts Enable all interrupts Interrupt Enable Flags IEx IEx flags when set to logical one enable specific interrupt requests to be serviced When the interrupt request flag is set to logical one an interrupt will not be serviced until its corresponding IEx flag is also enabled Int
91. not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Example The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one stopping the CPU clock The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 53 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec INCS Increment and Skip on Carry INCS dst Ro Increment register R skip on carry Increment indirect data memory skip on carry RR Increment register pair RRb skip on carry tas Description instruction INCS increments the value of the destination operand by An original value of OFH will for example overflow to OOH If a carry occurs the next instruction is skipped The carry flag value is unaffected Binary Code Operation Notation lo 1 1 skip on carry lt DA 1 skip carry a2 at 20 ES ESESES HL HL 1 skip on carry ofifo 2 r o 1 skip on cary Example Register pair HL contains the value 7EH 01111110B RAM location 7EH contains OFH The instruction sequence Increment direct data memory skip on carry 1 1 Lo o 67 ES INCS HL
92. of the carry flag is not affected A HL 114141134 1 HL then L L skip if L 0H Example Register pair HL contains the address 2FH and internal RAM location 2FH contains OFH LD HL 2FH LD A 0H A HL lt OFHandL 1 0 HL JPS XXX Skipped since an overflow occurred JPS YYY H lt 2H L 0H YYY A HL 20H lt A lt 20 e 1 1H JPS YYY instruction is executed since skip occurs after the XCHI instruction 5 92 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET Logical Exclusive OR XOR dst src Exclusive OR immediate data to A A HL Exclusive OR indirect data memory to A Exclusive OR register pair RRb to EA Description performs a bit wise logical operation between the source and destination variables and stores the result in the destination The source contents are unaffected Operand Binary Code Operation Notation 11 0 1 im 2 ao of ofa t fes eee o o i fifofeln o 0 RRb EA 1 o lt EA If the extended accumulator contains 11000011 and register pair HL contains 55H 01010101 the instruction XOR leaves the value 96H 10010110 in the extended accumulator ELECTRONICS 5 93 SAM47 INSTRUCTION S
93. pin is selected as a IFC input pin SMB 15 Time delay Built in AC amplifier stabilization time LD A 0AH LD IFMOD pin is selected and gate time is set to 8 ms Start IFC operation LOOP BTSF IFCG Check gate open close status JPS READ Jump to READ if gate closes JPS LOOP READ Read IFCNT1 IFCNTO ELECTRONICS 16 7 INTERMEDIATE FREQUENCY COUNTER KS57C3316 P3316 IFC DATA CALCULATION Selecting the FMIF pin for IFC Input First divide the signal at the FMIF pin by 2 and then apply this value to the IF counter This means that the IF counter value is equal to one half of the input signal frequency input frequency femp 10 7 MHz Gate time 8 ms IFC counter value N FMIP2 x 10 7 x 106 2 x 8x 10 3 42800 A730H sn IFCNT1 IFCNTO Selecting the AMIF Pin for IFC Input The signal at AMIF pin is directly input to the IF counter input frequency 450 kHz Gate time 8 ms IFC counter value N famir X 450 x 103 8x 10 3 3600 Dc 0 FE dTt J IFCNT IFCNT1 IFCNTO 16 8 ELECTRONICS KS57C3316 P3316 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section information on KS57C3316 electrical characteristics is presented as tables and
94. select Register Bank SRB n Operation Operation Summary Bytes Cycles Description SRB instruction selects one of four register banks in the working register memory area The constant value used with SRB is 0 1 2 or 3 The following table shows the effect of SRB settings ERB Setting SRB Settings Selected Register Bank Always set to bank 0 NOTE x applicable The enable register bank flag ERB must always be set for the SRB instruction to execute successfully for register banks 0 1 2 and 3 In addition if the ERB value is logic zero register bank 0 is always selected regardless of the SRB value Binary Code Operation Notation ieee 7 rots Tots ole ar ao Example If the ERB flag is set the instruction SRB 3 selects register bank 018H 01FH as the working memory register bank ELECTRONICS 5 85 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec SRET Return From Subroutine and Skip SRET Operation Description Example 5 86 fF Return from subroutine and then skip SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL or CALLS instruction SRET skips the resulting address which is generally the instruction immediately after the point at which the subroutine was called Then program execution continues from the resulting address and the contents of the location addressed by the stac
95. set to logic zero the following instruction sequence will execute the RET instruction BTST 30H 2 If 30H 2 1 then skip RET If 830H 2 0 return JP LABEL2 ELECTRONICS 5 39 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BTST Bit Test and Skip on True BTST Examples 5 40 Continued 2 You can use BTST in the same way to manipulate a port pin address bit BTST P2 0 If P2 0 1 then skip RET If P2 0 0 then return JP LABEL3 Assume that P2 2 P2 3 and P3 0 P3 3 are cleared to 0 LD L 0AH BP2 BTST P1 L First 1 P2 2 111100B 10B 10B 2 2 RET INCS L JR BP2 Bank 0 location is tested and regardless of the current EMB value BTST has the following effect FLAG EQU 0 LD H 0AH BTST H FLAG If bank 0 AH 0 OAOH O 1 then skip RET ELECTRONICS 557 3316 3316 SAM47 INSTRUCTION SET BTSTZ Bit Test and Skip on True Clear Bit BTSTZ dst b Test specified bit skip and clear if memory bit is set Description specified bit within the destination operand is tested If it is a 1 the instruction immediately following the BTSTZ instruction is skipped otherwise the instruction following the BTSTZ is executed The destination bit value is cleared ww rte el a a memb L ee Skip if memb 7 2 L 3 2 L 1 0 1 and clear
96. signal that the designated time interval has elapsed An interrupt request is then generated BCNT is cleared to logic zero and counting continues from 00H Oscillation Stabilization Interval Control Bits 2 0 of the BMOD register are used to select the input clock frequency for the basic timer This setting also determines the time interval also referred to as wait time required to stabilize clock signal oscillation when power down mode is released by an interrupt When a chip reset is generated the standard stabilization interval for system clock oscillation is 29 1 ms at 4 5 MHz Watchdog Timer Function The basic timer can also be used as a watchdog timer to detect an inadvertent program loop that is system or program operation error For this purpose instruction that clears the watchdog timer BITS WDTCF within a given period should be executed at proper points in a program If an instruction that clears the watchdog timer is not done within the period and the watchdog timer overflows a reset signal is generated and system is restarted with reset status An operation of watchdog timer is as follows Write some value except to Watchdog Timer Mode register WDMOD Each time BCNT overflows an overflow signal is sent to the watchdog timer counter WDONT If WDTONT overflows system reset will be generated 11 2 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER Table 11 1 Basic Timer Registe
97. skip function when an overflow or borrow occurs XCHI INCS XCHD DECS LDI ADS LDD SBS If there is an overflow or borrow from the result of an increment or decrement a skip signal is generated and a skip is executed However the carry flag value is unaffected The instructions BTST BTSF and CPSE also generate a skip signal and execute a skip when they meet a skip condition and the carry flag value is also unaffected Instructions Which Affect the Carry Flag The only instructions which do not generate a skip signal but which do affect the carry flag are as follows ADC LDB C operand SBC BAND C operand SCF BOR C operand RCF BXOR C operand CCF 5 4 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET ADC and SBC Instruction Skip Conditions The instructions ADC A HL and SBC A HL can generate a skip signal and set or clear the carry flag when they are executed in combination with the instruction ADS A im If an ADS A im instruction immediately follows an ADC A HL or A HL instruction a program sequence the ADS instruction does not skip the instruction following ADS even if it has a skip function If however an ADC A HL SBC A HL instruction is immediately followed by an ADS A im instruction the ADC or SBC skips on overflow or if there is no borrow to the instruction immediately following the ADS and program execution continues Table 5 3 contains additional information and e
98. the data pointer pair HL set to 34H 5 72 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET PUSH Push Onto Stack PUSH src RR o Push register pair onto stack 1 Push SMB and SRB values onto stack 2 Description SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer thereby adding a new element to the top of the stack 2 1 SP 1 lt SP 2 lt RRL SP SP 2 pt 1 6 1 SMB SP 2 lt SRB SP lt SP 2 Example As an interrupt service routine begins the stack pointer contains the value OFAH and the data pointer register pair HL contains the value 20H The instruction PUSH HL leaves the stack pointer set to OF8H and stores the values 2H and OH RAM locations OF9H and OF8H respectively ELECTRONICS 5 73 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec RCF Reset Carry Flag RCF Description flag is cleared to logic zero regardless of its previous value Assuming the carry flag is set to logic one the instruction RCF resets clears the carry flag to logic zero 5 74 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET REF Reference Instruction REF Operation Description dst Operation Summary Cycles REF instruction f
99. to the main system clock First clear SCMOD 3 to 0 to enable main system clock oscillation Until main osc is stabilized system clock must not be changed Then after a certain number of machine cycles has elapsed select the main system clock by clearing all SCMOD values to logic zero Following a system reset CPU operation starts with the lowest main system clock frequency of 14 2 usec at 4 5 MHz after the standard oscillation stabilization interval of 29 1 ms has elapsed Table 6 6 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect 6 10 ELECTRONICS 557 3316 3316 OSCILLATOR CIRCUITS Table 6 6 Elapsed Machine Cycles During CPU Clock Switch AFTER SCMOD 0 0 SCMOD 0 1 BEFORE 0 1 PCON A 1 1 1 0 1 1 MACHINE CYCLE 1 MACHINE CYCLE SCMOD 0 0 8 MACHINE CYCLES 8 MACHINE CYCLES 16 MACHINE CYCLES 16 MACHINE CYCLES fx Afxt MACHINE CYCLE NOTES 1 Even if oscillation is stopped by setting SCMOD 3 during main system clock operation the stop mode is not entered 2 Since the Xy input is connected internally to Vos to avoid current leakage due to the crystal oscillator in stop mode do not set SCMOD 3 to 1 or STOP instruction when an external clock is used as the main system clock 3 When the system clock is switched to the subsystem clock it is necessary to disable any interrupts which may occur during the time intervals shown in Tab
100. using SP PUSH EA POP EA FBOH FBFH 1 bit direct addressing PSW SCMOD BITS EMB FFOH FFFH IRQx I O 1 4 1 bit indirect addressing using the BSC I O BTST OFC3H L L register BAND C P3 L 3 4 ELECTRONICS KS57C3316 P3316 ADDRESSING MODES SELECT BANK REGISTER SB The select bank register SB is used to assign the memory bank and register bank The 8 bit SB register consists of the 4 bit select register bank register SRB and the 4 bit select memory bank register SMB as shown in Figure 3 2 During interrupts and subroutine calls SB register contents can be saved to stack in 8 bit units by the PUSH SB instruction You later restore the value to the SB using the POP SB instruction 4 sme F83H 4 sr F82H M CM SMB3 5 2 5 1 SMB 0 SRB 1 SRB 0 Figure 3 2 SMB and SRB Values the SB Register Select Register Bank SRB Instruction The select register bank SRB value specifies which register bank is to be used as a working register bank The SRB value is set by the SRB instruction where 0 1 2 and 3 One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the SRB instruction The current SRB value is retained until another register is requested by program software PUSH SB and POP SB instructions are used to save and restore the contents of SRB during
101. value to 0 and the ERB value to 1 VENT2 then branches to INTO to INT1 and so setting the appropriate EMB and ERB values ELECTRONICS 5 89 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec Exchange or EA with Nibble or Byte XCH dst src Exchange A and data memory contents 2 Exchange A and register Ra contents A RRa Exchange A and indirect data memory 1 EA DA Exchange EA and direct data memory contents EA RRb Exchange EA and register pair RRb contents EA HL Exchange EA and indirect data memory contents Description instruction loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source Binary Code Operation Notation 1 a2 at a0 0 lt gt 1 1 Double register HL contains the address 20H The accumulator contains the value 00111111B and internal RAM location 20H the value 75H 01110101B The instruction EA RRb EA HL 25 a4 ekle a7 5 a4 as EA HL leaves RAM location 20H with the value 00111111B and the extended accumulator with the value 75H 01110101 5 90 ELECTRONICS
102. voltage VA Description analog reference voltage V that is generated by the DAC and writes the corresponding digital value to the ADATA register Compares the applied external analog input voltage VAIN to the Digital data register ADATA Stores digital values as analog to digital conversion is completed ADC mode register ADMOD Used to select one of four analog channels as the input source for the analog data to be converted ADC control register AFLAG Contains the control flags used to start A D converter operation and to monitor operational status Successive approxima Control blocks in the A D converter contain the successive tion logic approximation logic required to generate the analog reference voltage 13 2 ELECTRONICS KS57C3316 P3316 A D CONVERTER ADC DATA REGISTER ADATA The A D converter data register ADATA is an 8 bit register in which digital data values are stored as an A D conversion operation is completed Digital values stored in ADATA are retained until another conversion operation is initiated ADATA is addressable by 8 bit read instructions only ADC MODE REGISTER ADMOD The analog to digital converter mode register ADMOD is a 4 bit register that is used to select one of four analog channels as the analog data input source ADMOD is addressable by 1 bit or 4 bit read or write instructions FDAH ADMOD 1 ADMOD O to ADMOD4 ApMopo Input channels ADCO ADC3 corres
103. your programs 1 Disable all interrupts with a DI instruction Modify the IMODO or IMOD 1 register Clear all relevant interrupt request flags Enable the interrupt by setting the appropriate IEx flag Enable interrupts with an El instructions ELECTRONICS 7 9 INTERRUPTS KS57C3316 P3316 EXTERNAL INTERRUPT 2 MODE REGISTER IMOD2 The mode register for external interrupts at the KSO KS3 and INT2 IMOD2 is addressable only by 4 bit write instructions A system reset clears all IMOD 2 bits to logic zero FB6H IMOD2 1 IMOD2 0 co If a rising edge is detected at the 2 pin or when a falling edge is detected at any one of the pins KS0 KS3 the IRQ2 flag is set to logic one and a release signal for power down mode is generated Since INT2 is a quasi interrupt the interrupt request flag IRQ2 must be cleared by software Table 7 6 IMOD2 Register Bit Settings mona fect of MOD Setings pn ww 3 sea ating wage a SKS PROGRAMMING Using the INT2 as Key Input Interrupt IMOD2 When you use the INT2 interrupt as a key entry interrupt the selected key interrupt source pin must be set to input mode 1 When KSO KS3 are selected four pins BITS EMB SMB 15 LD A 3H LD IMOD2A IMOD2 lt KS0 KS3 falling edge select LD EA 00H LD PMG3 EA P6 lt input
104. 0 3 Port Mode Group Flags Bulz Xm mum FE9H PM3 3 PM3 2 PM3 1 PMG2 FEAH PM4 3 PM4 2 PM4 1 FEBH PM5 3 5 2 NOTE If a PMGn bit 0 the corresponding pin is set to input mode If the PMGn 1 the pin is set to output mode All flags are cleared to 0 following a system reset PROGRAMMING Configuring I O Ports to Input or Output Configure port 0 as an output port BITS EMB SMB 15 LD EA 0FH LD PMGO EA PO lt Output ELECTRONICS 10 3 PORTS KS57C3316 P3316 PULL UP RESISTOR MODE REGISTER PUMOD The pull up resistor mode register PUMOD is used to assign internal pull up resistors by software to specific ports When configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting PUMOD is addressable by 8 bit write instructions only A system reset clears PUMOD register values to logic zero automatically disconnecting all software assignable port pull up resistors Table 10 4 Pull Up Resistor Mode Register PUMOD Organization PUMOD FDCH PUR3 PUR2 PUR1 PURO FDDH PUR6 PURS PUR4 NOTE When a PURn bit 1 a pull up resistor is assigned to the corresponding I O port is for port 3 PUR2 for port 2 and so on 59 PROGRAMMING Enabling and Disabling I O Port Pull Up Resistors P6 is enabled to ha
105. 0 and 1 Clear banks 0 and 1 of the data memory area RAMCLR SMB 1 RAM 100H 1FFH clear LD HL 00H LD A 0H RMCL1 LD HL A INCS HL JR RMCL1 SMB 0 RAM 010H 0FFH clear LD RMCLO LD HL A INCS HL JR RMCLO ELECTRONICS 2 7 ADDRESS SPACES KS57C3316 P3316 WORKING REGISTERS Working registers mapped to RAM address 000H 01FH data memory bank 0 are used to temporarily store intermediate results during program execution as well as pointer values used for indirect addressing Unused registers may be used as general purpose memory Working register data can be manipulated as 1 bit units 4 bit units or using paired registers as 8 bit units Working Register Register Bank 1 Register Bank 2 Register Bank 3 Figure 2 4 Working Register Map 2 8 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES Working Register Banks For addressing purposes the working register area is divided into four register banks bank 0 bank 1 bank 2 and bank 3 Any one of these banks can be selected as the working register bank by the register bank selection instruction SRB n and by setting the status of the register bank enable flag ERB Generally working register bank 0 is used for the main program and banks 1 2 and 3 for interrupt service routines Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing Table 2 3 Working Registe
106. 008 0 Crystal oscillator C1 C2 22 pF Vpp 5 Vt m 10 3 V 10 6 0 MHz 4 5 MHz ii gt 2 N Sub operating mode PCON 0011B SCMOD 1001B 0 3 V 10 32 kHz crystal oscillator Sub idle mode PCON 0111B SCMOD 1001B CE 0V 3 V 10 32 kHz crystal oscillator Stop mode CPU fxt 4 SCMOD 1101B CE 0 V 5 V 10 Stop mode CPU fx 4 SCMOD 0100B Vpp 5 V 10 Ippa Main idle mode 6 0 MHz PCON 0111B SCMOD 0000B 4 5 MHz Crystal oscillator C1 C2 22 pF Vpp 5 V 10 3 V 10 6 0 MHz 4 5MHz Ipp4 Oc ol c gt NOTES 1 Supply current does not include current drawn through internal pull up resistors and LCD voltage dividing resistors 2 Data includes the power consumption for sub system clock oscillation 19 6 ELECTRONICS 53 7335 7335 53 7335 Table 19 5 Main System Clock Oscillator Characteristics 40 85 C 1 8V to 5 5V Ceramic Oscillator Stabilization time 2 Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Crystal Oscillation frequency Vpp 2 7 V to 5 5 V Oscillator 1 Stabilization time 2 4 5 V to 55V 1 8V to 4 5V External Xy input frequency 1 Clock Xn input high and low level width typ tx NOTES 1 Oscillation frequency an
107. 00H 66H RET If the instruction LD EA 01H is executed in place of LD EA 00H The content of 0501H 77H is loaded to the EA register If LD EA 02H is executed the content of address 0502H 88H is loaded to EA 5 66 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET LDC Load Code Byte LDC Continued Examples 2 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator ORG 0500 DB 66H DB 77H DB 88H DB 99H DISPLAY LD WX 00H LDC EA WX EA lt address 0500H 66H RET If the instruction LD WX 01H is executed in place of LD WX 00H then EA lt address 0501H 77H If the instruction LD WX 02H is executed in place of LD WX 00H then EA lt address 0502H 88H 3 Normally the LDC EA EA and the LDC EA WX instructions reference the table data on the page on which the instruction is located If however the instruction is located at address xxFFH it will reference table data on the next page In this example the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A ORG 01FDH 01FDH LD WX 00H 01FFH LDC EA OWX lt upper 4 bits of 0200H address A lt lower 4 bits of 0200H address 4 Here is another example of page referencing with the LDC instruction ORG 0100 DB 67H SMBO LD HL 30H Even number LD WX 00H LDC EA WX lt upper 4 bits of
108. 0100H address lt lower 4 bits of 0100H address LD HL EA RAM 30H 7 RAM 6 ELECTRONICS 5 67 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec LDD Load Data Memory and Decrement LDD dst A HL Load indirect data memory contents to A decrement 1 2 5 register L contents and skip on borrow Description contents of a data memory location are loaded into the accumulator and the contents of the register L are decreased by one If a borrow occurs e g if the resulting value in register L is OFH the next instruction is skipped The contents of data memory and the carry flag value are not affected A HL 1 1 1 1 A lt HL then L 1 skip if L OFH Example In this example assume that register pair HL contains 20H and internal RAM location 20H contains the value LD HL 20H LDD A e HL and lt L 1 JPS Skip JPS YYY H lt 2H and L lt OFH The instruction 5 is skipped since a borrow occurred after the LDD A HL and instruction JPS YYY is executed 5 68 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET LDI Load Data Memory and Increment LDI Operation Description Example ELECTRONICS dst src A HL Load indirect data memory to A increment register L 1 2 5 contents and skip overflow The contents of a data memory location are loaded into the accumulator and the contents of the register L
109. 16 P3316 SAM47 INSTRUCTION SET Reducing Instruction Redundancy When redundant instructions such as LD A im and LD EA imm are used consecutively in a program sequence only the first instruction is executed The redundant instructions which follow are ignored that is they are handled like a NOP instruction When LD HL imm instructions are used consecutively redundant instructions are also ignored In the following example only the LD A im instruction will be executed The 8 bit load instruction which follows it is interpreted as redundant and is ignored LD Load 4 bit immediate data im to accumulator LD EA imm Load 8 bit immediate data imm to extended accumulator In this example the statements LD A 2H and A 3H are ignored BITR EMB LD Execute instruction LD A 2H Ignore redundant instruction LD A 3H Ignore redundant instruction LD 23H A Execute instruction 023H lt 1H If consecutive LD HL imm instructions load 8 bit immediate data to the 8 bit memory pointer pair HL are detected only the first LD is executed and the LDs which immediately follow are ignored For example LD HL 10H HL lt 10H LD HL 20H Ignore redundant instruction LD A 3H LD EA 35H Ignore redundant instruction LD HL A 10H 3H If an instruction reference with a REF instruction has a redundancy effect the following conditions apply Ifthe instruction preceding th
110. 21 S3 C7335 P7335 1199 USER S MANUAL 3C7335 P7335 4 Bit CMOS Microcontroller Revision 1 ELECTRONICS 53 7335 7335 4 5 MICROCONTROLLER USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Typical parameters can and do vary in different 3C7335 P7335 4 Bit CMOS Microcontroller User s Manual Revision 0 Publication Number 21 S3 C7335 P7335 1199 1999 Samsung Electronics applicati
111. 256 byte block Normally the JR WX JR EA instructions jump to the address in the page in which the instruction is located However if the first byte of the instruction code is located at address or OxFFH the instruction will jump to the next page POIAR 15 Pone EA First Byte Condition First Byte 23 PC PC 1 245 ELECTRONICS 557 3316 3316 JR Jump Relative Very Short SAM47 INSTRUCTION SET JR Continued Examples 1 A short form for a relative jump to label KK is the instruction JR KK where must be within the allowed range of current PC 15 to current PC 16 The JR instruction has in this case the effect of an unconditional JP instruction 2 In the following instruction sequence if the instruction LD WX 02H were to be executed in place of LD WX 00H the program would jump to 0102H and 5 would be executed If EA Z04H were to be executed the jump would be to 0104H and 5 would be executed ORG JPS JPS JPS JPS LD LD ADS JR 0100H AAA BBB CCC DDD WX 00H EA WX WX EA WX 3 Here is another example ORG 0200H A 0H 30H A YYY EA 00H EA WX
112. 2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code file by HEX2ROM the value is filled into the unused ROM area upto the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all KS57 series microcontrollers All required target system cables and adapters are included with the device specific target board OTPs One time programmable microcontroller OTP for the KS57C3316 microcontroller and OTP programmer Gang are ELECTRONICS 20 1 DEVELOPMENT TOOLS KS57C3316 P3316 now available IBM PC AT or Compatible RS 232C SMDS2 Target PROM OTP Writer Unit Application System lt _ gt RAM Break Display Unit 5 lt Trace Timer Unit TB573316A SAM4 Base Unit Target Board Eva lt gt Power Supply Unit Chip Figure 20 1 SMDS Product Configuration SMDS2 20 2 ELECTRONICS KS57C3316 P3316 DEVELOPMENT TOOLS TB573204A TARGET BOARD The TB573316A target board is used for the KS57C3316 P3316 microcontroller It is supported by the SMDS2 development system 573316 User Vcc Stop Idle Off On 74HC11 22 o EVA Chip 160 QFP KS57E3300 40 40 Pin Connector SM1268A Figure 20 2 TB573316A Target Board C
113. 3S C4 1 O 8d VOAS 8d 553S 66 c 8 9945 C4 ve 8d OdS Ge 0 6d 8DAS 96 6d 653S C4 Z 01945 6 936 C4 66 0014 21946 C4 OV Figure 19 1 S3P7335 Pin Assignments 80 QFP FMIF AMIF Vss1 VCOAM VCOFM P2 3 P2 2 P2 1 P2 0 SEG27 P13 3 SEG26 P13 2 SEG25 P 13 1 SEG24 P 13 0 SEG23 P12 3 SEG22 P 12 2 SEG21 P12 1 SEG20 P 12 0 SEG19 11 3 SEG18 P11 2 SEG17 P11 1 SEG16 P11 0 SEG15 P10 3 SEG14 P10 2 SEG13 P10 3 53 7335 7335 ELECTRONICS 53 7335 7335 53 7335 Table 19 1 Pin Descriptions Used to Read Write the EPROM During Programming Serial data pin Output port when reading and input port when writing Can be assigned as a Input or push pull output port Serial clock pin Input only pin Power supply pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Vpp TEST RESET RESET Chip initialization Vpp Vss Vop Vss 12 13 Logic power supply pin Vpp should be tied to 5 V during programming Table 19 2 Comparison of S3P7335 and S3C7335 Features Program Memory 16K bytes EPROM 16K bytes mask ROM Operating Voltage 1 8V to 5 5 V 1 8V to 5 5 V 2 5 V to 3 5 Vor 4 0 V to 5 5 V 2 5 V to 3 5 Vor 4 0 V to 5 5 V at PLL IFC operation at PLL IFC operation OTP Programming Mode 5 V TEST 12 5 V
114. 4 Table 6 2 shows corresponding cycle times in microseconds Table 6 2 Instruction Cycle Times for CPU Clock Rates Oscillation Source Selected CPU Clock Resulting Frequency Cycle Time usec k 4 5 MHz 70 3 kHz UE 1220 6 6 ELECTRONICS 557 3316 3316 OSCILLATOR CIRCUITS SYSTEM CLOCK MODE REGISTER SCMOD The system clock mode register SCMOD is a 4 bit register that is used to select the CPU clock and to control main and sub system clock oscillation SCMOD is mapped to the RAM address FB7H When main system clock is used as clock source main system clock oscillation can be stopped by STOP instruction or setting SCMOD 3 not recommended When the clock source is subsystem clock main system clock oscillation is stopped by setting SCMOD 3 SCMOD 0 SCMOD2 and SCMOD 3 cannot be simultaneously modified Sub oscillation goes into stop mode only by SCMOD 2 PCON which revokes stop mode cannot stop the sub oscillation The stop of sub oscillation is released only by a system reset A system reset clears all SCMOD values to logic zero selecting the main system clock fx as the CPU clock and starting clock oscillation The reset value of the SCMOD is 0 SCMOD 3 SCMOD 2 SCMOD 0 bits can be manipulated by 1 bit write instructions In other words SCMOD 0 SCMOD 2 and SCMOD 3 cannot be modified simultaneously by a 4 bit write Bit 1 is always logic zero A subsystem clock fxt can be selected as the system cloc
115. 5 2 Bit Addressing Modes and 5 4 Skip Conditions for ADC and SBC 5 5 Data Type Symbols oett ter ds 5 6 Identifiers s iets Ante te TE er Ie eec bee D ber Lese bee DRE 5 6 Instruction Operand IO 5 6 Opcode Definitions READERS 5 7 Opcode Definitions 5 7 CPU Control Instructions High Level Summary pp 5 9 Program Control Instructions High Level 5 9 Data Transfer Instructions High Level 5 10 Logic Instructions High Level Summary 5 11 Arithmetic Instructions High Level Summary 5 11 Bit Manipulation Instructions High Level Summary 5 12 CPU Control Instructions Binary Code 5 14 Program Control Instructions Binary Code 5 15 Data Transfer Instructions Binary Code Summary pp 5 16 Logic Instructions Binary Code menn mener 5 18 Arithmetic Instructions Binary Code Summary 5 19 Bit Manipulation Instructions Binary Code 5 20 XV KS57C3316 P3316 MICROCONTROLLER List of Tables Continued Table Title Page Number Number 6 1 Power Control Register PCON
116. 7C3316 P3316 ELECTRONICS KS57C3316 P3316 RESET RESET OVERVIEW A system reset operation can be initiated by RESET or by changing the state of the external CE pin When a reset operation occurs the system is initialized and the program is executed starting from the reset vector address A CE reset occurs when the CE pin is forced from Low to High level You can use a CE reset for normal system initialization When a power on occurs the power on flag POF is automatically set to 1 Please note that the RESET signal is not generated automatically The POF bit in the power on flag register POFR 0 is read initially to check whether not power has been turned on You can tested or clear this flag using the BITR instruction Whenever a RESET signal is input during normal operation or during power down mode the CPU enters idle mode When the standard oscillation stabilization interval of 29 1 ms at 4 5 MHz has elapsed normal system operation resumes When reset operation occurs during normal operating or after a power down mode has been entered most hardware register values are set to the reset values described in Table 9 1 Some reset values may vary for different types of reset operations However during idle or stop mode the current values contained in the following status register are always retained flag Data memory values General purpose registers E A L H X W Z and Y General purpose r
117. 8 8 7 4 Not used Always logic zero PM6 3 P6 3 Mode Selection Bit Set P6 3 to input mode 1 Set P6 3 to output mode PM6 2 P6 2 Mode Selection Bit Set P6 2 to input mode Set P6 2 to output mode 1 P6 1 Mode Selection Bit Set P6 1 to input mode Set P6 1 to output mode fe PM6 0 P6 0 Mode Selection Bit Set P6 0 to input mode 1 Set P6 0 to output mode ELECTRONICS 4 3 MEMORY KS57C3316 P3316 PNE Port Open Drain Enable Register FD7H FD6H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W Bit Addressing 8 8 8 8 8 8 8 7 Not used Always logic zero PNE13 Port 13 N Channel Open Drain Configurable Bit ush pull output channel open drain output PNE12 Port 12 N Channel Open Drain Configurable Bit ush pull output channel open drain output 11 Port 11 N Channel Open Drain Configurable Bit ush pull output channel open drain output PNE10 Por 10 N Channel Open Drain Configurable Bit ush pull output channel open drain output 9 Port 9 N Channel Open Drain Configurable Bit Push pull output gt N channel open drain output PNE8 Port 8 N Channel Open Drain Configurable Bit Push pull output gt N channel open drain output PNE7 Por 7 N Channel Configurable Bit Push pull output gt N channel open drain output 4 36 ELECTRONICS KS57C3316 P3316
118. ALL CLOCK 2 CALL CLOCK INCHL LD HL A 3 HL lt A INCS HL ABC LD EA 00H 47 lt ORG 0080H MAIN NOP NOP REF KEYCK BTSF KEYFG 1 byte instruction REF JMAIN KEYFG 1 jump to MAIN 1 byte instruction REF WATCH KEYFG 0 CALL CLOCK 1 byte instruction REF INCHL LD HL A INCS HL REF ABC LD 1 byte instruction 2 4 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES DATA MEMORY RAM OVERVIEW In its standard configuration the data memory has five areas 32 4 bit working register area 224 x 4 bit general purpose area in bank 0 also used as the stack area 228 x 4 bit general purpose area in bank 1 28 x 4 bit area for LCD data in bank 1 128 x 4 bit area in bank 15 for memory mapped address To make it easier to reference the data memory area has three memory banks bank 0 bank 1 and bank 15 The select memory bank instruction SMB is used to select the bank you want to select as working data memory Data stored in RAM locations are 1 4 and 8 bit addressable One exception is the LCD data register area which is 1 bit and 4 bit addressable only Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset However when a system reset signal is generated in power down mode the data memory contents are held Working Registers 32 x 4 Bits General purpose Regi
119. AM SEG27 P13 3 SEG1 P7 1 SEGO P7 0 P R T 5 G M E N T D R V E R Timing COM Controller Control LCD Voltage Control Figure 12 2 LCD Circuit Diagram 12 2 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses 1E4H 1FFH are used as LCD data memory These locations can be addressed by 1 bit 4 bit instructions When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG27 using a direct memory access DMA method that is synchronized with the f signal RAM addresses in this location that not used for LCD display can be allocated to general purpose use 1 2 1 Figure 12 3 LCD Display Data RAM Organization Table 12 1 Common Signal Pins Used per Duty Cycle NOTE NC connection is required ELECTRONICS 12 3 LCD CONTROLLER DRIVER KS57C3316 P3316 LCD CONTROL REGISTER LCON LCON is a 4 bit write only register The LCON register can be used to turn the LCD display on or off and to control the current to dividing resistors in the LCD circuit A reset operation clears all 1 values to 0 This turns the LCD display off and stops the current to the dividing resistors and LCON 1 used for P6 When LCON 1 is 0 P6 is connected an exter
120. AMIF pins The FMIF or AMOIF pin input signal for the 16 bit counter is selected using IFMOD register settings The 16 bit binary counter IFCNT1 IFCNTO can be read by 8 bit RAM control instructions only When the FMIF input signal is selected the signal is divided by two When the AMIF pin input signal is directly connected to the IFC it is not divided By setting IFMOD register the gate is opened for 1 ms 4 ms or 8 ms periods During the open period of the gate input frequency is counted by the 16 bit counter When the gate is closed the counting operation is complete and an interrupt is generated T is Selector IF Counter vider 16 bit ir Data Bus 1KHz Internal Signal Figure 16 1 IF Counter Block Diagram ELECTRONICS 16 1 INTERMEDIATE FREQUENCY COUNTER KS57C3316 P3316 IFC MODE REGISTER IFMOD The IFC mode register IFMOD is a 4 bit register that is used to select the input pin and gate time Setting IFMOD register reset IFC value and IFC gate flag value and starts IFC operation You use the IFMOD register to select the AMIF or FMIF input pin and the gate time IFC operation starts when you select AMIF or FMIF as the IFC input pin The IFMOD register can be read or written by 4 bit RAM control instructions A reset operation clears all IFMOD values to 0 Table 16 1 IFMOD Organization Pin Selection Bits iFMOD3 IFMOD 2 Effect of Control Setting IFC is disable FMIF AMIF are pulled down
121. B 0 SRB 1 Register bank 0 is selected since ERB 0 the SRBis configured to bank 0 LD EA 34H Bank 0 EA lt 34 LD HL EA BankOHL lt EA SRB 2 Register bank 0 is selected LD YZ EA BankO YZ EA SRB 3 Register bank 0 is selected LD WX EA Bank 0 lt EA 2 When ERB 1 SRB 1 Register bank 1 is selected LD EA 34H Bank1EA lt LD HL EA Bank1 HL lt Bank 1 SRB 2 Register bank 2 is selected LD YZ EA Bank2 YZ lt BANK2 EA SRB 3 Register bank 3 is selected LD WX EA Bank3WX lt Bank3EA ELECTRONICS 2 19 ADDRESS SPACES KS57C3316 P3316 SKIP CONDITION FLAGS SC2 SC1 SCO The skip condition flags SC2 SC1 and SCO in the PSW indicate the current program skip conditions and are set and reset automatically during program execution Skip condition flags can only be addressed by 8 bit read instructions Direct manipulation of the SC2 SC1 and SCO bits is not allowed CARRY FLAG C The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry ADC SBC The carry flag can also be used as a 1 bit accumulator for performing Boolean operations involving bit addressed data memory If an overflow or borrow condition occurs when executing arithmetic instructions with carry ADC SBC the carry flag is set to 1 Otherwise its value is 0 When a system reset occurs the current value of the carry flag is retained du
122. CHD A HL Bank 1 160 166 o JR TRANS ELECTRONICS 3 9 ADDRESSING MODES KS57C3316 P3316 8 BIT ADDRESSING Table 3 4 8 Bit Direct and Indirect RAM Addressing Instruction Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description DA irect 8 bi indi Direct 8 bit address indicated by the RAM address DA FFFH Bank 15 15 a 8 bit even number and memory SMB 0 1 15 addressable bank selection peripherals Indirect the 8 bit address 4bit 0 OOOH OFFH Banko indicated by the memory bank 1 000H FFFH SMB 0 1 15 All 8 bit selection and register HL the addressable L register value must be an peripherals even number SMB 15 3 10 ELECTRONICS KS57C3316 P3316 PROGRAMMING 8 Bit Addressing Modes 8 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 4 SMB 0 LD ADATA EA 2 BDATA EA 2 If EMB 1 ADATA EQU 46H BDATA EQU SMB 15 LD EA P4 SMB 0 LD ADATA EA LD BDATA EA 8 Bit Indirect Addressing 1 If EMB 0 ADATA EQU 46H SMB 1 HL ADATA LD EA HL 2 If EMB 1 ADATA EQU 46H SMB 1 LD HL ZADATA LD EA HL ELECTRONICS ADDRESSING MODES Non essential instruction because EMB 0 lt P5 A lt P4 046 lt 047 lt E FBEH F8FH E lt P5 A
123. CIRCUITS 557 3316 3316 5 6 14 ELECTRONICS KS57C3316 P3316 INTERRUPTS INTERRUPTS OVERVIEW The KS57C3316 interrupt control circuit has five functional components Interrupt enable flags Interrupt request flags IRQx Interrupt master enable register IME Interrupt priority register IPR Power down release signal circuit Three kinds of interrupts are supported Internal interrupts generated by on chip processes External interrupts generated by external peripheral devices Quasi interrupts used for edge detection and as clock sources Table 7 1 Interrupt Types and Corresponding Port Pin s Interrupt Type Corresponding Port Pins External interrupts INTO INT1 INT4 INTCE P1 0 P1 1 1 3 CE Internal interrupts INTB INTTO INTIF INTS Not applicable Quasi interrupts INT2 KSO KS3 P1 2 KSO KS3 P6 0 P6 3 ELECTRONICS 7 1 INTERRUPTS KS57C3316 P3316 Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware or they can be generated by program software A vectored interrupt is generated when the following flags and register settings corresponding to the specific interrupt INTn are set to logic one Interrupt enable flag Interrupt master enable flag IME Interrupt request flag IRQx Interrupt status flags ISO 151 Interrupt priority register IPR If all conditions are satisfied for the
124. CLO pin on falling edge 1 Internal system clock fxx of 4 5 2 219 4 39 kHz Select clock 26 70 3 kHz at 4 5 MHz 1 Select clock fxx 24 281 kHz at 4 5 MHz Select clock fxx 4 5 MHz 3 Clear Counter and Resume Counting Control Bit 1 Clear TCNTO IRQTO TOLO resume counting immediately This bit is cleared automatically when counting starts 2 Timer Counter 0 Enable Disable Bit Disable timer counter 0 retain TCNTO contents Enable timer counter 0 1 0 Not used ES Always logic zero 4 42 ELECTRONICS KS57C3316 P3316 MEMORY MAP TOE Timer Output Enable Flag Register F92H Bit 8 2 1 0 RESET Value 0 0 0 0 Read Write R W R W Bit Addressing 1 4 1 4 3 Not used Always logic zero 0 zi er Counter 0 Output Enable Flag Disable timer counter 0 output at the TCLOO pin Enable timer counter 0 output at the TCLOO pin 1 BOE Basic Timer Output Enable Flag Disable basic timer output at the BTCO pin 1 Enable basic timer output at the BTCO pin 0 Not used Always logic zero ELECTRONICS 4 4 MEMORY KS57C3316 P3316 WDFLAG Watchdog Timer Counter Clear Flag Register F9AH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 1 4 WDTCF Watchdog Timer Counter Clear Flag Clears the watchdog timer counter 2 0 Bits 2 0 EN Always logic zero NOTE After watchdog timer is cleared by writing 1
125. DMOD The watchdog timer mode register WDMOD is 8 bit write only register located at RAM address F98H F99H WDMOD register controls to enable or disable the watchdog function WDMOD values are set to logic 5 following a chip reset and this value enables the watchdog timer and watchdog timer is set to the longest interval because BT overflow signal is generated with the longest interval Watchdog Timer Enable Disable Control 5AH Disable watchdog timer function Any other value Enable watchdog timer function WATCHDOG TIMER COUNTER WDCNT The watchdog timer counter WDCNT is a 3 bit counter WDCNT is automatically cleared to logic zero and restarts whenever the WDTCF register control bit is set to 1 RESET stop and wait signal clears the WDCNT to logic zero also WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated When WDCNT has incremented to hexadecimal 07H it is cleared to OOH and an overflow is generated The overflow causes the system reset When the interrupt request is generated BCNT immediately resumes counting incoming clock signals WATCHDOG TIMER COUNTER CLEAR FLAG WDTCF The watchdog timer counter clear WDTCF is a 1 bit write instruction When WDTCF is set to one it clears the WDONT to zero and restarts the WDCNT WDTCF register bits 2 0 are always logic zero Table 11 3 Watchdog Timer Interval Ti
126. E a ene 5 18 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET Table 5 19 Arithmetic Instructions Binary Code Summary Name Operand BinayCode Operation Notation Jojo 1 1 1 1 t 0 JGBAcA HO C EARR 1 1 0 11 1 11 01 0 C EACEA RR C RRbEA 1 1 1 o RRb lt 0 da ao skip on cary EA imm ENEREZEZXEREEXESEN EA lt EA imm skip on carry 47 as a4 a3 a2 at do 1 Ac HL skip on EA RR EA EA on carry 1 9 0 41 11 1 410 RRbEA 1 1 1 skip CAcA H C EARR 1 1 ola 1 1 0 c EAcEA RR C ENEEEKSEZERESEZES wee 8 0 1 A A HL skip on borrow EA lt EA RR skip borrow RRb EA RRb lt RRb EA skip on borrow R 1 R lt 1 skip on borrow Lat poe o eoe RR lt RR 1 skip on borrow ESESESESERERESRES DA DA 1 skip on carry a6 a5 a4 as a2 at Qn HL lt HL 1 skip carry Ro 1
127. EA RRb EA HL EA ELECTRONICS SAM47 INSTRUCTION SET Operation Description and Guidelines Load data memory contents pointed to by 8 bit register HL to the A register and the contents of HL 1 to the E register The contents of register L must be an even number If the number is odd the LSB of register L is recognized as a logic zero an even number and it is not replaced with the true value For example LD HL 36H loads immediate 36H to HL and the next instruction LD EA HL loads the contents of 36H to register A and the contents of 37H to register E Load direct data memory contents of DA to the A register and the next direct data memory contents of DA 1 to the E register The DA value must be an even number If it is an odd number the LSB of DA is recognized as a logic zero an even number and it is not replaced with the true value For example LD EA 37H loads the contents of 36H to the A register and the contents of 37H to the E register Load 8 bit RRb register HL WX YZ to the EA register H W and Y register values are loaded into the E register and the L X and Z values into the A register Load A register contents to data memory location pointed to by the 8 bit HL register value Load the A register contents to direct data memory and the E register contents to the next direct data memory location The DA value must be an even number If it odd number the LSB of the DA value is recognized as logi
128. EA TDATA SBUF EA SMOD 3 IES SB EA EMB EA TDATA EA SBUF RDATA EA SCK P4 0 50 4 1 SI P4 2 KS57C3316 P4 0 SCK and P4 1 SO lt Output 4 2 51 lt Input TDATA address 20H 7FH SIO start SIO Interrupt Enable Store SMB SRB Store EA EA Receive data TDATA address 20H 7FH Transmit data lt gt Receive data address 20H 7FH SIO start External Device ELECTRONICS KS57C3316 P3316 SERIAL I O INTERFACE 52 PROGRAMMING Setting Transmit Receive Modes for Serial Concluded 4 Transmit and receive an external clock in LSB first mode INTS XCH BITS POP POP IRET ELECTRONICS EMB EA 02H PMG2 EA EA 07H SMOD EA EA TDATA SBUF EA SMOD 3 IES SB EA EMB EA TDATA EA SBUF RDATA EA KS57C3316 High Speed SIO Transmission 4 1 SO lt Output P4 0 SCK and P4 2 SI lt Input SIO start TDATA address 20H 7FH SIO Interrupt Enable Store SMB SRB Store EA EA lt Transmit data TDATA address 20H 7FH Transmit data lt gt Receive data address 20H 7FH SIO start External Device SERIAL I O INTERFACE KS57C3316 P3316 NOTES 14 8 ELECTRONICS KS57C3316 P3316 PLL FREQUENCY SYNTHESIZER PLL FREQUENCY SYNTHESIZER OVERVIEW The phase locked loop PLL frequency synthesizer locks medium frequency MF high frequency HF
129. ECTRONES 557 3316 3316 Preliminary Spec PRODUCT OVERVIEW Pull up Enable Data Circuit Output Type C Disable SEG ADCEN Output Disable ADC Select Data Figure1 13 Pin Circuit Type 10 P5 Figure 1 15 Pin Circuit Type H 4 Output Disable Circuit Type H 4 Figure 1 14 Pin Circuit COMO COM3 Figure 1 16 Pin Circuit Type H 28 P7 P13 ELECTRONES 1 11 PRODUCT OVERVIEW 3C7335 P7335 NOTES 1 12 ELECTRONES KS57C3316 P3316 ADDRESS SPACES ADDRESS SPACES PROGRAM MEMORY ROM OVERVIEW ROM maps for KS57C3316 devices are mask programmable at the factory KS57C3316 has 16K x 8 bit program memory In its standard configuration the device s 16K x 8 bit program memory has four areas that are directly addressable by the program counter PC 16 byte area for vector addresses 16 general purpose area 96 byte instruction reference area 16 256 byte general purpose area General Purpose Program Memory Two program memory areas are allocated for general purpose use One area is 16 bytes in size and the other is 16 256 bytes Vector Addresses A 16 byte vector address area is used to store the vector addresses required to execute system resets and interrupts Start addresses for interrupt service routines are stored in this area along with the values of the enable memory bank EMB and enable register bank ERB flags that are used to set their initial value
130. ERFIESEJES A ee Fo eror faz foo Operation operara Operation Summary Byes dc E e L LLL uL 1 1 1 1 0 1 0 C cmemb7 L 3 2 L 1 0 0 1 00 as a4 c H DAb 1 1 1 1 0 o 0 bt bo a2 at Second Byte Bit Addresses menat ei pa ea an 1 bt 2 1 0 5 64 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET LDB Load Bit LDB Continued Examples 1 The carry flag is set and the data value at input pin P1 0 is logic zero The following instruction clears the carry flag to logic zero LDB C P1 0 2 The P1 address is FF1H and the L register contains the value 9H 1001B The address memb 7 2 is 111100B and L 3 2 is 10B The resulting address is 11110010B or FF2H and P2 is addressed The bit value L 1 0 is specified as 01B bit 1 LD L 9H LDB C P1 L P1 L specifies P2 1 and lt P2 1 3 The H register contains the value 2H and FLAG 20H 3 The address for H is 0010B and for FLAG 3 0 the address is 0000B The resulting address is 00100000B or 20H The bit value is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H LDB C H FLAG FLAG 20H 3 4 The following instruction sequence sets the carry flag and the loads the 1 data value to the output pin P1 0 setting i
131. ET KS57C3316 P3316 Preliminary Spec NOTES 5 94 ELECTRONICS 557 3316 3316 OSCILLATOR CIRCUITS OSCILLATOR CIRCUITS OVERVIEW The KS57C3316 microcontroller has two oscillator circuits a main system clock circuit and a subsystem clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits Specifically a clock pulse is required by the following peripheral modules LCD controller Basic timer Timer counter 0 Watch timer A D converter Clock output circuit Serial I O interface PLL frequency synthesizer IF counter CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx fxt Main system clock Subsystem clock fxx Selected system clock ELECTRONICS 6 1 OSCILLATOR CIRCUITS 557 3316 3316 Clock Control Registers When the system clock mode control register SCMOD and the power control register PCON are both cleared to zero after a system reset the normal CPU operating mode is enabled a main system clock of fx 64 is selected and main system clock oscillation is initiated PCON is used to select normal CPU operating mode or one of two power down modes stop or idle Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power down mode The system clock mode control register SCMOD lets you select the main system clock fx ora subsystem c
132. EW The serial I O interface SIO has the following functional components 8 bit mode register SMOD Clock selector circuit 8 bit buffer register SBUF 3 serial clock counter Using the serial interface you can exchange 8 bit data with an external device You control the transmission frequency by the appropriate bit settings to the SMOD register The serial interface can run off an internal or an external clock source or the TOLO signal that is generated by the 8 bit timer counter 0 TCO If you use the TOLO clock signal you can modify its frequency to adjust the serial data transmission rate SIO OPERATION SEQUENCE The general sequence of operations for the serial I O interface may be summarized as follows 1 Set SIO mode to transmit and receive or to receive only Select MSB first or LSB first transmission mode Set the SCK clock signal in the mode register SMOD Set SIO interrupt enable flag IES to 1 Initiate SIO transmission by setting bit 3 of the SMOD to 1 wo When the SIO operation is complete IRQS flag is set and an interrupt is generated ELECTRONICS 14 1 SERIAL I O INTERFACE KS57C3316 P3316 Internal Bus LSB or MSB first Wb SO SBUF 8 Bit i Over Flow IRQS 405 a Clear 7 SMOD 6 Svons SMOD 3 SMOD 2 SMOD 1 SMOD O 8 BITS note Internal Bus TOLO gt CPU CLK Clock 3 Bit Counter RAT Sel
133. H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IE1 INT1 Interrupt Enable Flag Disable interrupt requests at the INT1 Enable interrupt requests at the INT1 pin IRQ1 INT1 Interrupt Request Flag Generate INT1 interrupt This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin IEO INTO Interrupt Enable Flag Disable interrupt requests at the INTO Enable interrupt requests at the INTO pin IRQO INTO Interrupt Request Flag Generate INTO interrupt This bit is set and cleared automatically by hardware when rising or falling edge detected at INTO pin ELECTRONICS 4 13 MEMORY KS57C3316 P3316 IE2 IRQ2 2 Interrupt Enable Request Flags FBFH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W Bit Addressing 1 4 1 4 3 2 Bits 3 2 Always logic zero IE2 INT2 Interrupt Enable Flag ES Disable INT2 interrupt requests at the INT2 pin or KSO KS3 pins Enable INT2 interrupt requests at the INT2 pin or KSO KS3 pins IRQ2 INT2 Interrupt Request Flag Generate INT2 quasi interrupt This bit is set and is not cleared automatically by hardware when a rising edge is detected at INT2 or when a rising edge is detected at KSO KS3 pins 4 14 ELECTRONICS KS57C3316 P3316 MEMORY MAP 4 IRQ4 INT4 Interrupt Enable Request Flags FB8H IEB IRQB intB Interrupt Enable Request Flags FB8H Bit 3 2 1 0 RESET Value 0 0 0 0
134. HING THE CPU CLOCK Together bit settings in the power control register PCON and the system clock mode register SCMOD determine whether a main system or a subsystem clock is selected as the CPU clock and also how this frequency is to be divided This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies SCMOD 3 SCMOD 2 and SCMOD 0 select the main system clock fx or a subsystem clock fxt and start or stop main or sub system clock oscillation PCON 1 and 0 control the frequency divider circuit and divide the selected fx clock by 4 8 64 or fxt clock by 4 NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications the previously selected clock continues to run for a certain number of machine cycles For example you are using the default CPU clock normal operating mode and a main system clock of fx 64 and you want to switch from the fx clock to a subsystem clock and to stop the main system clock To do this you first need to set SCMOD 0 to 1 This switches the clock from fx to fxt but allows main system clock oscillation to continue Before the switch actually goes into effect a certain number of machine cycles must elapse After this time interval you can then disable main system clock oscillation by setting SCMOD 3 to 1 This same stepped approach must be taken to switch from a subsystem clock
135. IRQTO Interrupt enable flag IETO 11 10 KS57C3316 P3316 Activates the timer counter and selects the internal clock frequency or the external clock source at the TCLO pin Stores the reference value for the desired number of clock pulses between interrupt requests Counts internal or external clock pulses based on the bit settings in TMODO and TREFO Together with the mode register TMODO lets you select one of four internal clock frequencies or an external clock Determines when to generate an interrupt by comparing the current value of the counter register TCNTO with the reference value previously programmed into the reference register TREFO Where a clock pulse is stored pending output to the serial circuit or to the TCLO output pin TCLOO When the contents of the TCNTO and TREFO registers coincide the timer counter interrupt request flag IRQTO is set to 1 the status of TCLO is inverted and an interrupt is generated Must be set to 1 before the contents of the TOLO latch can be output to TCLOO Cleared when TCO operation starts and the TCO interrupt service routine is executed and enable whenever the counter value and reference value coincide Must be set to 1 before the interrupt requests generated by timer counter 0 can be processed ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER Table 11 4 TCO Register Overview Register Type Description RAM Addressing Reset Name Add
136. If EMB 0 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 LD H 0BH BTSTZ H CFLAG 1 0 lt 0 and skip BITS CFLAG Else if OBAH O 0 lt 1 2 1f EMB 1 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 LD H 0BH 0BH BTSTZ H CFLAG 1 lt 0 skip BITS CFLAG Else if OBAH 0 0 lt 1 ELECTRONICS 3 7 ADDRESSING MODES KS57C3316 P3316 4 BIT ADDRESSING Table 3 3 4 Bit Direct and Indirect RAM Addressing Operand Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank Mapping DA Direct 4 bit address indicated OOOH O7FH by the RAM address DA and All 4 bit the memory bank selection 1 000H FFFH SMB 0 1 15 addressable peripherals DD indicated by the memory bank 1 000H FFFH SMB 0 1 15 All 4 bit selection and register HL addressable peripherals SMB 15 WX Indirect 4 bit address indicated 000H 0FFH Bank 0 by register WX WL Indirect 4 bit address indicated X 000H 0FFH Bank 0 by register WL NOTE x means don t care 52 PROGRAMMING 4 Bit Addressing Modes 4 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 Non essential instruction since EMB 0 LD A P3 lt SMB 0 Non essential instruction since EMB 0 LD ADA
137. LMOD organization Table 15 1 PLMOD Organization disable PLL enable PLMOD 0 Select the PLL operating voltage as 4 0 V to 5 5 V PLL Enable Bit PLMOD 2 Select the PLL operating voltage as 2 5 V to 3 5 V Frequency Division Method Selection Bit PLMOD 3 Frequency Division Selected Pin Input Voltage Input Division Value Method Frequency Direct method for AM VcoAM Selected 300mVpp 0 5 30 MHz 16 to 212 1 pulled Low 2 1 Pulse swallow method for selected 300mVpp 30 150 MHz 210 to 217 2 FM VcoAM Pulled Low NOTE The NF bit a one bit frequency division value is written to bit 0 in the swallow counter um ELECTRONICS 15 5 PLL FREQUENCY SYNTHESIZER KS57C3316 P3316 PLL REFERENCE FREQUENCY SELECTION REGISTER PLLREF The PLL reference frequency selection register PLLREF used to determine the reference frequency You can select one of ten reference frequencies by setting bits PLLREF 3 PLLREF 0 to the appropriate value You can select one of the reference frequencies by setting bits PLLREF 3 PLLREF 0 Table 15 2 PLLREF Register Organization 0 o 5 kHz as 770 seect 125 ke as reference 779 PHASE DETECTOR CHARGE PUMP AND UNLOCK DETECTOR oo o o _ o o oo Los cpm
138. LOCK BTSTZ RET e e ELECTRONICS IRQW PO 3 lt output mode 0 5 second check No return Yes 0 5 second interrupt generation Increment HOUR MINUTE SECOND 11 25 TIMERS and TIMER COUNTER KS57C3316 P3316 NOTES 11 26 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The KS57C3316 microcontroller can directly drive an up to 28 SEG x 4 COM LCD panel Its LCD block has the following components LCD controller driver Display RAM for storing display data 28 segment output pins SEGO SEG27 4 common output pins COMO COM3 Internal resistor circuit for LCD bias The frame frequency duty and bias and the segment pins used for display output are determined by bit settings in the LCON LMOD The LCD control register LCON is used to turn the LCD display on and off to switch current to the dividing resistors for the LCD display Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during main clock stop and idle modes if the clock source is activated o BIAS LCD VLCo VLC2 Controller Driver D 9 00 c a SEGO SEG27 P7 0 P13 3 Figure 12 1 LCD Function Diagram ELECTRONICS 12 1 LCD CONTROLLER DRIVER KS57C3316 P3316 LCD CIRCUIT DIAGR
139. Logical OR carry with specified memory bit SS C memb L C H DA b Description specified bit of the source is logically ORed with the carry flag bit value The value of the source is unaffected Binary Code Operation Notation C amp C memab C memb L poe OR memb 7 2 L 3 2 L 1 0 0 1 00 a4 cC H DAb 1 1 1 14 1 1 Cec OR H DA3 0 b o bt a2 at Second Byte BitAddesses Addresses enee ee ee 1 ao FFonFF Examples 1 The carry flag is logically ORed with the P1 0 value RCF C 0 BOR C P1 0 IfP1 0 1 thenC lt 1 if P1 0 then C lt 0 2 The P1 address is FF1H and register L contains the value 9H 1001B The address memb 7 2 is 111100B and L 3 2 10B The resulting address is 11110010B or FF2H specifying P2 The bit value for the BOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD L 9H BOR C P1 L P1 L is specified as P2 1 C OR P2 1 ELECTRONICS 5 35 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BOR Bit Logical OR BOR Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000 The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG
140. ME 4 39 30 ms TREFO value 84H 1 83H 3 Load the value 83H to the TREFO register BITS EMB SMB 15 LD EA 83H LD TREFO EA LD EA 4CH LD TMODO EA 11 20 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER WATCH TIMER OVERVIEW The watch timer is a multi purpose timer which consists of three basic components 8 bit watch timer mode register WMOD Clock selector Frequency divider circuit Watch timer functions include real time and watch time measurement and interval timing for the main and subsystem clock It is also used as a clock source for the LCD controller and for generating buzzer BUZ output Real Time and Watch Time Measurement To start watch timer operation set bit 2 of the watch timer mode register WMOD 2 to logic one The watch timer starts the interrupt request flag IRQW is automatically set to logic one and interrupt requests commence in 0 5 second intervals Since the watch timer functions as a quasi interrupt instead of a vectored interrupt the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed Using a System or Subsystem Clock Source The watch timer can generate interrupts based on the system clock frequency or on the subsystem clock When the zero bit of the WMOD register is set to 1 the watch timer uses the subsystem clock signal fxt as its source if WMOD 0 0 the system clock fxx
141. MEMORY MAP Power Flag Register FD1H Bit 3 2 1 0 RESET Value 0 0 0 1 Read Write R W Bit Addressing 1 4 3 1 Bit 3 1 Always logic zero POF Power On Flag Set automatically when a power on occurs NOTES 1 power on the value is 1 2 The POF bit is read initially to check whether or not power has been turned on It can be cleared by using BITR instruction ELECTRONICS If a system reset occurs during operation mode the current value contained is retained If a system reset occurs after MEMORY KS57C3316 P3316 PSW Program Status Word FB1H Bit 7 6 5 4 3 2 1 0 RESET Value 1 0 0 0 0 0 0 0 Read Write R W R R R R W R W R W R W Bit Addressing 2 8 8 8 1 4 1 4 1 1 C Carry Flag No overflow or borrow condition exists An overflow or borrow condition exists 5 2 5 0 Skip Condition Flags 151 150 Interrupt Status Flags Service only the highest priority interrupt s as determined in the interrupt priority register IPR EMB Enable Data Memory Bank Flag Restrict program access to data memory to bank 15 and to the locations 000H 07FH in the bank 0 only Enable full access to data memory banks 0 1 and 15 ERB Enable Register Bank Flag Select register bank 0 as working register area Select register banks 0 1 2 or 3 as working register area in accordance with the select register bank SRB instruction operand NOTES 1 The value of the
142. NI E Ld 94 3 OLNI O ld 94 Zng8 e od MOLZ 0d Z 3 OOTOL 1 0d cL E3 OOLE 0 0d P4 1 SO 4 2 5 P4 3 CLO P5 0 ADCO P5 1 ADC1 P5 2 ADC2 P5 3 ADC3 P6 0 KSO P2 1 P6 1 KS1 P2 0 P6 2 KS2 SEG27 P13 3 P6 3 KS3 SEG26 P132 KS57C3316 SEG25 P13 1 FMIF AMIF Vss1 VCOAM VCOFM 2 3 P2 2 O OONOOARWD Vss0 80 QFP Top View SEG24 P13 0 XOUT SEG23 P12 3 XIN SEG22 P12 2 TEST SEG21 P12 1 XTIN SEG20 P12 0 XT OUT SEG19 P11 3 RESET SEG18 P11 2 BIAS SEG17 P11 1 VLCO SEG16 P11 0 VLC1 SEG15 P10 3 VLC2 SEG14 P10 2 COMO SEG13 P10 1 07 4 0035 Cj 82 44 995 C3 6c 24 2095 06 5 14 593 cj IE 0 8d VO3S C3 89 6995 C 89 9995 cj 76 684 046 0 6d e03S Cj 96 L ed eo3s C ZE c 6d 0LO3S 88 6d LLO3S 9 66 0 0Ld ero3S C3 0 Figure 1 2 53 7335 80 QFP Pin Assignment ELECTRONES 1 5 PRODUCT OVERVIEW 3C7335 P7335 PIN DESCRIPTIONS Table 1 1 S3C7335 Pin Descriptions Description Reset Circuit Value Type 4 bit port Input 1 bit or 4 bit read write and test are possible Pull up resistors can be configured by software 4 bit input port Input A 4 1 bit 4 bit read and test are possible Pull up resistors can be configured by software P2 0 P2 3 4 bit I O ports Input D 2 P3 0 P3 3 1 bit 4 bit or 8 bit read write and test are possible Pull up resistors can be configured by software Ports 2 and 3 can be paired to support 8 bit data D 4 transfer
143. OH 2 respectively are both logic zero program execution mode is normal and all interrupt requests are serviced see Figure 7 3 Whenever an interrupt request is accepted 151 and ISO are incremented by and the values are stored in the stack along with the other PSW bits After the interrupt routine has been serviced the modified 151 and ISO values are automatically restored from the stack by an IRET instruction 150 151 can be manipulated directly by 1 bit write instructions regardless of the current value of the enable memory bank flag EMB Before you modify an interrupt service flag however you must first disable interrupt processing with a DI instruction When 151 0 and ISO 1 all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register IPR Normal Program High or Low Level Processing Interrupt Processing Status 0 Status 1 High Level Interrupt INT Disable Processing Set IPR gt Status 2 INT Enable gt Low or High Level Interrupt Generated High Level Interrupt Generated Figure 7 3 Two Level Interrupt Handling ELECTRONICS 7 5 INTERRUPTS KS57C3316 P3316 Multi Level Interrupt Handling With multi level interrupt handling a lower priority interrupt request can be executed by manipulating the interrupt status flags 150 and IS1 while a high priority interrupt is being serviced see Ta
144. OLO are cleared counting starts from 00H and TMODO 3 is automatically reset to 0 for normal TCO operation When TCO operation stops TMODO 2 0 the contents of the TCO counter register TCNTO are retained until TCO is re enabled TMODO 6 TMODO 5 and TMODO 4 bit settings are used together to select the TCO clock source This selection involves two variables Synchronization of timer counter operation with either the rising edge or the falling edge of the clock signal input at the TCLO pin Choosing of one of four frequencies based on division of the incoming system clock frequency for use in internal TCO operation Table 11 6 Timer 0 Mode Register Organization Resulting TCO Function Always logic zero F91H TMODO 7 Specify input clock edge and internal frequency Disable timer counter 0 retain TCNTO contents TMODO 2 TMODO 1 TMODO 0 Enable timer counter 0 Always 0 Always 0 TMODO 3 1 Clear TCNTO IRQTO and TOLO and resume counting immediately This bit is automatically cleared to 0 after counting resumes 11 16 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER Table 11 7 TMODO 6 TMODO 5 and TMODO 4 Bit Settings TMODO 6 TMODO 5 TMODO 4 Resulting Counter Source and Clock Frequency External Clock input TCLO on rising edges 1 External Clock input TCLO on falling edges 1 Eu d 3 NOTE selected system
145. P2 3 to input mode 1 Set P2 3 to output mode PM2 2 P2 2 Mode Selection Bit Set P2 2 to input mode 1 Set P2 2 to output mode 2 1 2 1 Mode Selection Bit Set P2 1 to input mode 1 Set P2 1 to output mode PM2 0 0 0 Mode Selection Bit Set P2 0 to input mode 1 Set P2 0 to output mode ELECTRONICS 4 3 MEMORY KS57C3316 P3316 2 Port yo Mode Selection Register Port 4 and Port 5 FEBH FEAH Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Bit Addressing 8 8 8 8 8 8 8 8 PM5 3 P5 3 Mode Selection Bit Set P5 3 to input mode 1 Set P5 3 to output mode PM5 2 P5 2 Mode Selection Bit Set P5 2 to input mode 1 Set P5 2 to output mode PM5 1 P5 1 Mode Selection Bit Set P5 1 to input mode fel Set P5 1 to output mode PM5 0 P5 0 Mode Selection Bit Set P5 0 to input mode fe Set P5 0 to output mode PM4 3 P4 3 Mode Selection Bit Set P4 3 to input mode Set 4 3 to output mode PM4 2 P4 2 Mode Selection Bit Set P4 2 to input mode fel Set P4 2 to output mode PM4 1 P4 1 Mode Selection Bit Set P4 1 to input mode fe Set P4 1 to output mode PM4 0 P0 0 Mode Selection Bit Set P4 0 to input mode 1 Set P4 0 to output mode 4 34 ELECTRONICS KS57C3316 P3316 MEMORY MAP PMG3 Port yo Mode Selection Register Port 6 FEDH FECH Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W Bit Addressing 8 8
146. Pin Configuration 80 QFP 80 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the 3 7335 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 17 3 below Table 19 3 Operating Mode Selection Criteria 5V 0000H EPROM read 12 5 V 0000H NOTE 0 means low level 1 means high level um ELECTRONICS 19 3 EPROM verify EPROM read protection 53 7335 53 7335 7335 Table 19 4 D C Electrical Characteristics 40 to 85 C Vpp 1 8 V to 5 5 Input high All input pins except those specified 0 7 Vpp voltage below Vino 0 2 1 4 0 4 2 5 P6 CE and 0 8 Vpp RESET Typ Max Units XT and XTour Input low Vi 4 All input pins except those specified voltage below Vito 0 2 P1 4 0 P4 2 P5 P6 CE and RESET Xn and Output high Vout 4 5 to 5 5 EO Vpp 2 0 4 5 to 5 5 V Vpp 1 0 Other output ports lon 1 mA Output low Vout VDD 4 5V to 5 5 V EO voltage lo 1 mA Vpp 4 5V to 5 5V Other output ports 10 mA leakage All input pins current note Input low lu OV leakage All input pins current note Output high lou Vour
147. R can be modified all interrupts must first be disabled by a DI instruction By manipulating the IPR settings you can choose to process all interrupt requests with the same priority level or you can select one type of interrupt for high priority processing A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source Table 7 3 Standard Interrupt Priorities Interrupt Default Priority INTB INT4 INTO INTS INTTO INTCE INTIF The MSB of the IPR the interrupt master enable flag IME enables and disables all interrupt processing Even if an interrupt request flag and its corresponding enable flag are set a service routine cannot be executed until the IME flag is set to logic one The IME flag mapped FB2H 3 can be directly manipulated by El and DI instructions regardless of the current enable memory bank EMB value Table 7 4 Interrupt Priority Register Settings wm Sting o Normal menu handing acorn 10 default PeeeNTBamiWT tempssthigespiody 3 9 Press INTO highest pony o 3 cess IT trust highest pony a o o 0 pony 3 3 9 T Process INTE imerupis at hignest priory Process INTIF interrupts at highest priority NOTE During norm
148. RIPTIONS The following section contains detailed information and programming examples for each instruction of the SAM47 instruction set Information is arranged in a consistent format to improve readability and for use as a quick reference resource for application programmers If you are reading this user s manual for the first time please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set The information elements of the instruction description format are as follows Instruction name mnemonic Full instruction name Source destination format of the instruction operand Operation overview from the High Level Summary table Textual description of the instruction s effect Binary code overview from the Binary Code Summary table Programming example s to show how the instruction is used ELECTRONICS 5 23 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec ADC Add With Carry ADC dst src A HL Add indirect data memory to A with carry 2 EA RR Add register pair RR to EA with carry RRb EA Add EA to register pair RRb with carry Description source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the carry flag is
149. S ints Interrupt Enable Request Flags FBDH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W Bit Addressing 1 4 1 4 3 and 2 Not used E Always logic zero IES INTS Interrupt Enable Flag Disable INTS interrupt requests Enable INTS interrupt requests IRQS INTS Interrupt Request Flag Generate INTS interrupt This bit is set and cleared by hardware whenever a serial data transfer completion signal is received from the serial interface ELECTRONICS 4 17 MEMORY IETO IRQTO Interrupt Enable Request Flags Bit Identifier RESET Value Read Write Bit Addressing 3 2 IETO IROTO n Bits 2 1 0 772 m 0 0 0 R W R W 1 4 1 4 3 2 Always logic zero INTTO Interrupt Enable Flag Disable INTTO interrupt requests KS57C3316 P3316 FBCH Enable INTTO interrupt requests INTTO Interrupt Request Flag Generate INTTO interrupt This bit is set and cleared automatically by hardware when contents of TCNTO and TREFO registers match KS57C3316 P3316 MEMORY MAP IEW IRQW intw Interrupt Enable Request Flags FBAH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W Bit Addressing 1 4 1 4 3 2 Bits 3 2 Always logic zero IEW INTW Interrupt Enable Flag E Disable INTW interrupt requests Enable INTW interrupt requests IROW INTW Interrupt Request Flag Generate INTW interrupt This bit is set when the timer interval is
150. Serial I O interface clock generator 1 2 3C7335 P7335 Watch Timer e Time interval generation 0 5 s 3 9 ms at 32 768 kHz e Frequency outputs to BUZ e Clock source generation for LCD 8 Serial Interface e 8 bittransmit receive mode e 8 bit receive mode e Data direction selectable LSB first or MSB first e Internal or external clock source A D Converter e 4 channels with 8 bit resolution Bit Sequential Carrier Buffer e Support 16 bit serial data transfer in arbitrary format PLL Frequency Synthesizer e Level 300 mVpp min e AMVCO range 0 5 MHz to 30 MHz e FMVCO range 30 MHz to 150 MHz 16 Bit Intermediate Frequency IF Counter e Level 300 mVpp min e AMIF range 100 kHz to 1 MHz FMIF range 5 MHz to 15 MHz ELECTRONES KS57C3316 P3316 Preliminary Spec FEATURES Continued Interrupts e Four internal vectored interrupts e Four external vectored interrupts e Two quasi interrupts Memory Mapped I O Structure e Data memory bank 15 Three Power Down Modes e Idle Only CPU clock stops e Main system or subsystem clock stops e 2 Main system and subsystem clock stop e CE low PLL and IFC stop Oscillation Sources e Crystal or ceramic oscillator for main system clock e Crystal for subsystem clock e Main system clock frequency 4 5 MHz e Subsystem clock frequency 32 768 kHz Typ e clock divider circuit by 4 8
151. T FMIF x2 when TG gate time 1 ms 4 ms 8 ms pin input frequency is N DEC when TG gate time 1 ms 4 ms 8 ms Table 16 2 shows the range of frequency that you can apply to the AMIF and FMIF pins Table 16 2 IF Counter Frequency Characteristics Pn Voltage Level Frequency Range AMIF 300 m Vpp 0 1 MHz to 1 MHz in FMIF 300 m Vpp min 5 MHz to 15 MHz 16 6 ELECTRONICS 557 3316 3316 INTERMEDIATE FREQUENCY COUNTER INPUT PIN CONFIGURATION The AMIF and FMIF pins have built in AC amplifiers see Figure 16 5 The DC component of the input signal must be stripped off by the external capacitor When the AMIF or FMIF pin is selected for the IFC function and the switch is turned on voltage of each pin increases to approximately 1 2 Vpp after a sufficiently long time If the pin voltage does not increase to approximately 1 2 Vpp the AC amplifier exceeds its operating range possibly causing an IFC malfunction To prevent this from occurring you should program a sufficiently long time delay interval before starting the count operation External To Internal Frequency Counter Figure 16 5 AMIF and FMIF Pin Configuration PROGRAMMING Counting the Frequency at the FMIF pin 8 ms Gate Time You must insert a time delay before starting an IF counter operation This time delay ensures the normal operation of the built in AC amplifier when each
152. T4 NOTE INTO N R is indicated to Noise Reduction circuit Figure 10 2 Port 1 Circuit Diagram INT1 INT2 INT4 KS57C3316 P3316 ELECTRONICS KS57C3316 P3316 PORTS PORTS 2 3 CIRCUIT DIAGRAM port number 2 3 When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 3 Ports 2 3 Circuit Diagram ELECTRONICS 10 9 PORTS KS57C3316 P3316 PORT 4 CIRCUIT DIAGRAM P4 0 SCK P4 1 SO P4 2 SI P4 3 CLO SCK 51 When port acts as output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 4 Port 4 Circuit Diagram 10 10 ELECTRONICS KS57C3316 P3316 PORTS PORT 5 CIRCUIT DIAGRAM ADCO ADC1 ADC2 ADC3 TE pe De 0 0 U 70 P5 0 ADCO P5 1 ADC1 P5 2 ADC2 P5 3 ADC3 Pn D DD NOTE When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 5 Port 5 Circuit Diagram ELECTRONICS 10 11 PORTS KS57C3316 P3316 PORT 6 CIRCUIT DIAGRAM lll TIU Output Latch Br NOTE Whe
153. TA A 046H lt A LD BDATA A LCON lt 2 1 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD A P3 lt SMB 0 LD ADATA A 046H lt A LD BDATA A 3 8 ELECTRONICS KS57C3316 P3316 ADDRESSING MODES 52 PROGRAMMING TIP 4 Bit Addressing Modes Continued 4 Bit Indirect Addressing Example 1 1 If EMB 0 compare bank 0 locations 040H 046H with bank 0 locations 060H 066H ADATA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL BDATA LD WX ADATA COMP LD A WL A lt bank 0 040H 046H CPSE A HL If bank 0 060H 066H A skip SRET DECS L JR COMP RET 2 If EMB 1 compare bank 0 locations 040H 046H to bank 1 locations 160H 166H ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL ZBDATA LD WX ADATA COMP LD A WL A bank 0 040 046 CPSE A HL If bank 1 160H 166H A skip SRET DECS L JR COMP RET 4 Bit Indirect Addressing Example 2 1 If EMB 0 compare bank 0 locations 040H 046H with bank 0 locations 060H 066H ADATA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL BDATA LD WX ADATA TRANS LD A WL A lt bank 0 040H 046H XCHD A HL Bank 0 060H 066H lt gt JR TRANS 2 If EMB 1 exchange bank 0 locations 040H 046H to bank 1 locations 160H 166H ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL ZBDATA LD WX ADATA TRANS LD A WL lt bank 0 040H 046H X
154. TER TCO REFERENCE REGISTER TREFO The TCO reference register TREFO is an 8 bit write only register It is addressable by 8 bit RAM control instructions A system reset initializes the TREFO value to FFH TREFO is used to store a reference value to be compared to the incrementing TCNTO register in order to identify an elapsed time interval Reference values will differ depending upon the specific function that TCO is being used to perform as a programmable timer counter event counter clock signal divider or arbitrary frequency output source During timer counter operation the value loaded into the reference register is compared to the TCNTO value When TCNTO TREFO an interrupt request is generated to signal the interval or event The TREFO value together with the TMODO clock frequency selection determines the specific TCO timer interval Use the following formula to calculate the correct value to load to the TREFO reference register 1 TMODO frequency setting TCO timer interval TREFO value 1 x TREFO value 0 ELECTRONICS 11 19 TIMERS TIMER COUNTER KS57C3316 P3316 PROGRAMMING Setting a TCO Timer Interval To set 30 ms timer interval for TCO given 4 5 MHz follow these steps 1 Select the timer mode register with a maximum setup time of 58 3 ms assume the TCO counter clock 219 and TREFO is set FFH 2 Calculate the TREFO value TREFO value 1 SO
155. TION SEQUENCE 1 Set counter buffer bit BMOD 3 to logic one to restart the basic timer BONT is then incremented by one per each clock pulse corresponding to BMOD selection BCNT overflows if BCNT 255 BCNT When an overflow occurs the IRQB flag is set by hardware to logic one The interrupt request is generated BCNT is then cleared by hardware to logic zero N ogg LD Basic timer resumes counting clock pulses ELECTRONICS 11 5 TIMERS TIMER COUNTER KS57C3316 P3316 PROGRAMMING Using the Basic Timer 1 To read the basic timer count register BCNT BITS EMB SMB 15 BONTR LD YZ EA LD CPSE EA YZ JR BCNTR 2 When stop mode is released by an interrupt set the oscillation stabilization interval to 29 1 ms BITS EMB SMB 15 LD A 0AH LD BMOD A Wait time is 29 1 ms NOP STOP Set stop power down mode NOP NOP NOP Normal Normal CPU Operating Mode Stop Mode Idle Mode Operating Mode Operation 29 1 ms EN Stop Stop Mode is Instruction Released by Interrupt 3 To set the basic timer interrupt interval time to 1 82 ms at 4 5 MHz BITS EMB SMB 15 LD A 0EH LD BMOD A EI BITS IEB Basic timer interrupt enable flag is set to 1 4 Clear BCNT and the IRQB flag and restart the basic timer BITS EMB SMB 15 BITS BMOD 3 11 6 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER WATCHDOG TIMER MODE REGISTER W
156. a Register ADATA ii ae ete e ete Ret RE UR ADC Mode Register 0 ADC and Port Control Register Control Register Gne une day uen rey uei a a dne Fede Digital to Analog Converter DAC Conversion eL Procedure Description rode tegere pire cet enata Chapter 14 Serial 1 0 Interface QN EE 9SIO Operation Sequerice corr tite E tret teta ee Senai V Modo Register SMOD cti etes re teed ch ate e eee Eu ee eae doa c dee utere Enn Setial l O Liming Diagrams eee Eee a EBENE EHE ERE piven aes Serial VO Buffer Register SBUF J eter ib eod et REO RE CORE PAR RE DE ES RR Ed EAR Eds Chapter 15 PLL Frequency Synthesizer OVEIVIOW secet PLL Frequency Synthesizer FUMCION coo n de iut adage ena PLL Data Register uiti MEE RES Reference Frequency PLL Mode Register RD PLL Reference Frequency Selec
157. al interrupt processing interrupts are processed in the order in which they occur If two or more interrupt requests are received simultaneously the priority level is determined according to the standard interrupt priorities in Table 7 3 the default priority assigned by hardware when the lower three IPR bits 0 In this case the high priority interrupt request is serviced and the other interrupt is inhibited Then when the high priority interrupt is returned from its service routine by an IRET instruction the inhibited service routine is started um ELECTRONICS 7 7 INTERRUPTS KS57C3316 P3316 52 PROGRAMMING Setting the INT Interrupt Priority The following instruction sequence sets the INT1 interrupt to high priority BITS EMB SMB 15 DI PR 3 IME 0 LD A 3H LD IPR A EI PR3 IME lt 1 EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS IMODO and IMOD1 The following components are used to process external interrupts at the INTO and INT1 pins Noise filtering circuit for INTO Edge detection circuit Two mode registers IMODO and IMOD1 The mode registers are used to control the triggering edge of the input signal IMODO and IMOD1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger The INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges IMODO and IMOD1 are addre
158. alue moves into the bit 3 accumulator position 3 0 Binary Code Operation Notation A 1 1 C A 0 A3 C A n 1 1 2 3 The accumulator contains the value 5H 0101 and the carry flag is cleared to logic zero The instruction RRC A leaves the accumulator with the value 2H 0010B and the carry flag set to logic one ELECTRONICS 5 79 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec SBC subtract with Carry SBC dst src A HL Subtract indirect data memory from A with carry 1 EA RR Subtract register pair RR from EA with carry ee RRb EA Subtract EA from register pair RRb with carry Description SBC subtracts the source and carry flag value from the destination operand leaving the result in the destination SBC sets the carry flag if a borrow is needed for the most significant bit otherwise it clears the carry flag The contents of the source are unaffected If the carry flag was set before the SBC instruction was executed a borrow was needed for the previous step in multiple precision subtraction In this case the carry bit is subtracted from the destination along with the source operand sy core prt ttn __ 1 s foan o o t 1 1 1 P peee Er r ojo sje mo RRb EA o lt RRb EA C Examples 1 The extended accumulator contains the value OC3H register pair HL the value OAAH
159. are incremented by one If an overflow occurs e g if the resulting value in register L is OH the next instruction is skipped The contents of data memory and the carry flag value are not affected A HL 1 1 1 lt HL thenL lt 1 1 skip if L 0H Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value OFH LD HL 2FH LDI A HL lt HL and L lt 1 JPS XXX Skip JPS YYY 2H and L 0H The instruction JPS is skipped since an overflow occurred after the LDI A HL and the instruction JPS YYY is executed 5 69 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec NOP No Operation NOP Operation Operation Summary Bytes Cycles Description operation is performed NOP instruction It is typically used for timing delays One NOP causes a 1 cycle delay with a 1 us cycle time five NOPs would therefore cause a 5 us delay Program execution continues with the instruction immediately following the NOP Only the PC is affected At least three NOP instructions should follow a STOP or IDLE instruction Binary Code Operation Notation tt fod Nooperation Example Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power down mode is initiated STOP NOP NOP NOP 5 70 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET OR
160. arry RRb EA Add EA to register pair RRb and skip on carry Subtract indirect data memory from A with carry Subtract register pair RR from EA with carry Subtract EA from register pair RRb with carry Subtract indirect data memory from A skip on borrow Subtract register pair RR from EA skip on borrow Subtract EA from register pair RRb skip on borrow SBC SBS Decrement register R skip on borrow Decrement register pair RR skip on borrow R Increment register R skip on carry Increment direct data memory skip on carry Increment indirect data memory skip on carry Increment register pair RRb skip on carry umm ELECTRONICS 5 11 SAM47 INSTRUCTION SET KS57C3316 P3316 Table 5 14 Bit Manipulation Instructions High Level Summary ee Operation Description Test specified bit and skip if carry flag is set DA b Test specified bit and skip if memory bit is set 2 5 mema b memb L H DA b DA b Test specified memory bit and skip if bit equals 0 mema b memb L H DA b mema b Test specified bit skip and clear if memory bit is set memb L H DA b DA b Set specified memory bit mema b memb L H DA b DA b Clear specified memory bit to logic zero mema b memb L H DA b C mema b Logical AND carry flag with specified memory bit C memb L C H DA b C mema b Logical OR carry with specified memory bit C memb L C H DA b C mema b Exclusive OR carry with specified memory bit C memb L C
161. ate transmission and then reset this bit to logic zero Bit not used value is always 0 SMOD Clock Selection R W Status of SBUF External clock at SCK pin SBUF is enabled when SIO operation is halted or when SCK goes high Use TOLO clock from TCO 1 x CPUclck fxx 4 fxx 8 fxx 64 Enable SBUF read write 1 4 39 kHz clock fxx 210 SBUF is enabled when SIO operation is halted or when SCK goes high 281 kHz clock NOTES 1 system clock x means don t care 2 kHzfrequency ratings assume a system clock fxx running at 4 5 MHz 3 The SIO clock selector circuit cannot select a fxx 24 clock if the CPU clock is fxx 64 ELECTRONICS 14 3 SERIAL I O INTERFACE KS57C3316 P3316 SERIAL 1 TIMING DIAGRAMS Transmit IR 85 Complete 4 SET SMOD 3 Figure 14 2 SIO Timing in Transmit Receive Mode High Impendence Transmit IR os Complete E SET SMOD 3 1 1 1 1 1 1 1 1 1 1 L 1 1 1 1 1 Figure 14 3 SIO Timing in Receive Only Mode 14 4 ELECTRONICS KS57C3316 P3316 SERIAL INTERFACE SERIAL I O BUFFER REGISTER SBUF The serial I O buffer register SBUF can be read or written using 8 bit RAM control instructions After a reset operation the value of SBUF is undetermined When the serial interface operates in transmit and receive mode SMOD 1 1 transmit data in the SIO buffer register are output to the SO pin P4 1 at the rate of one bit for
162. atically so that a check can be made to verify that the conversion was successful 8 Converted digital values that have been stored in the 8 bit ADATA register can now be read Conversion values are retained until the next A D conversion operation starts ELECTRONICS 13 5 A D CONVERTER KS57C3316 P3316 PROGRAMMING Configuring A D Converter Input Pins In this A D converter program sample the ADCO ADC1 and ADC2 pins are used as A D input pins and the P5 3 ADC3 is used as normal input pin ADOCK AD1CK AD2CK 13 6 EMB ADCLK A 7H APCON A A 0H ADMOD A ADSTR EOC ADOCK EA ADATA ADCOBUF EA ADMOD A ADSTR EOC AD1CK EA ADATA ADC1BUF EA ADMOD A ADSTR EOC AD2CK EA ADATA ADC2BUF EA Selects fxx 4 clock for conversion Setting ADCO ADC1 and ADC2 as ADC input and P5 3 as normal input ADCO pin select for A D conversion A D conversion start A D conversion end check A D conversion not completed A D conversion end ADCOBUF lt ADCO conversion data ADC1 pin select for A D conversion A D conversion start A D conversion end check A D conversion not completed A D conversion end ADC1BUF lt ADC1 conversion data ADC2 pin select for A D conversion A D conversion start A D conversion end check A D conversion not completed A D conversion end ADC2BUF lt ADC2 conversion data ELECTRONICS 557 3316 3316 SERIAL I O INTERFACE SERIAL MO INTERFACE OVERVI
163. ator Figure 2 6 1 Bit 4 Bit and 8 Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction 2 10 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES PROGRAMMING Selecting the Working Register Area The following examples show the correct programming method for selecting working register area 1 When ERB 0 VENT2 1 0 INTO lt 1 ERB lt 0 Jump to INTO address INTO PUSH SB PUSH current SMB SRB SRB 2 Instruction does not execute because ERB 0 PUSH HL PUSH HL register contents to stack PUSH WX PUSH WX register contents to stack PUSH YZ PUSH YZ register contents to stack PUSH EA PUSH EA register contents to stack SMB 0 LD EA 00H LD 80H EA LD HL 40H INCS HL LD WX EA LD YZ EA POP EA POP EA register contents from stack POP YZ POP YZ register contents from stack POP WX POP WX register contents from stack POP HL POPHL register contents from stack POP SB POP current SMB SRB IRET The POP instructions execute alternately with the PUSH instructions If an SMB n
164. bank 0 During an interrupt or a subroutine the PC value and the PSW are saved to the stack area When the routine has completed the stack pointer is referenced to restore the PC and PSW and the next instruction is executed SP can address stack registers in bank 0 addresses 000 regardless of the current value of the enable memory bank EMB flag and the select memory bank SMB flag Although general purpose register areas can be used for stack operations be careful to avoid data loss due to simultaneous use of the same register s Since the reset value of the stack pointer is not defined in firmware we recommend that you initialize the stack pointer by program code to location This sets the first register of the stack area to NOTE A subroutine call occupies six nibbles in the stack an interrupt requires six When subroutine nesting or interrupt routines are used continuously the stack area should be set in accordance with the maximum number of subroutine levels To do this estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly 59 PROGRAMMING Initializing the Stack Pointer To initialize the stack pointer SP 1 When EMB 1 SMB 15 Select memory bank 15 LD EA 00H Bit 0 of SP is always cleared to 0 LD SP EA Stack area initial address OOH lt SP 1 2 When EMB 0 LD EA 00H LD SP EA
165. bank specified by the select memory bank SMB value 0 1 or 15 using 1 4 or 8 bit instructions You can use both direct and indirect addressing modes The addressable RAM areas when EMB 1 are as follows If SMB 0 000 If SMB 1 100 1 If SMB 15 EMB 0 When the enable memory bank flag EMB is set to logic zero the addressable area is defined independently of the SMB value and is restricted to specific locations depending on whether a direct or indirect address mode is used If EMB 0 the addressable area is restricted to locations 000H 07FH in bank 0 and to locations in bank 15 for direct addressing For indirect addressing only locations 000 in bank 0 are addressable regardless of SMB value To address the peripheral hardware register bank 15 using indirect addressing the EMB flag must first be set to 1 and the SMB value to 15 When a system reset occurs the EMB flag is set to the value contained in bit 7 of ROM address 0000 EMB Independent Addressing At any time several areas of the data memory can be addressed independent of the current status of the EMB flag These exceptions are described in Table 3 1 Table 3 1 RAM Addressing Not Affected by the EMB Value Addressing Method Affected Hardware Program Examples 000 4 bit indirect addressing using WX Not applicable LD A WX and WL register pairs 8 bit indirect addressing
166. ble 7 2 When an interrupt is requested during normal program execution interrupt status flags ISO and IS1 are set to 1 and 0 respectively This setting allows only highest priority interrupts to be serviced When a high priority request is accepted both interrupt status flags are then cleared to 0 by software so that a request of any priority level can be serviced In this way the high and low priority requests can be serviced in parallel see Figure 7 4 Table 7 2 151 and ISO Bit Manipulation for Multi Level Interrupt Handling Before INT Effect of ISx Bit Setting After INT ACK REMIT I II RE current settings in the IPR register are serviced o No actonalinterupt requests wil be served _ Normal Program Processing Single Status 0 Interrupt INT Disable gt 2 Level Set IPR Interrupt gt INT Disable gt Status 1 3 Level Interrupt INT Enable 3 odify Status Low or INT Enable gt Status 0 High Level Lowor y High Level Interrupt High Level Interrupt Status 1 Status 2 Generated Interrupt 4 Generated Generated Figure 7 4 Multi Level Interrupt Handling 7 6 ELECTRONICS KS57C3316 P3316 INTERRUPTS INTERRUPT PRIORITY REGISTER IPR The 4 bit interrupt priority register IPR is used to control multi level interrupt handling Its reset value is logic zero Before the IP
167. ble memory bank EMB and enable register bank ERB flag values that are needed to initialize the service routines 16 byte vector addresses are organized as follows To set up the vector address area for specific programs use the instruction VENTn The programming tips on the next page explain how to do this Vector Address Area 16 Bytes General Purpose Area 16 Bytes Instruction Reference Area 96 Bytes General Purpose Area 16 256 Byte Figure 2 1 ROM Address Structure Figure 2 2 Vector Address Structure 2 2 ELECTRONICS KS57C3316 P3316 PROGRAMMING Defining Vectored Interrupts ADDRESS SPACES The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory 1 When all vector interrupts are used ORG VENTO VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 VENT7 0000H 1 0 RESET 0 0 INTB 0 0 INTO 0 0 INT1 0 0 INTS 0 0 INTTO 0 0 INTCE 0 0 INTIF EMB EMB EMB EMB EMB EMB EMB EMB 1 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 Jump to RESET address 0 Jump to INTB address 0 Jump to INTO address 0 Jump to INT1 address 0 Jump to INTS address 0 Jump to INTTO address 0 Jump to INTCE address 0 Jump to INTIF address 2 When a specific vectored interrupt such as INTO and INTTO is not used the unused vect
168. by the instructions IDLE and STOP PCON 3 and PCON 2 can be addressed only by the STOP and IDLE instructions respectively to engage the idle and stop power down modes Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag EMB PCON bits 1 and 0 can be written only by 4 bit RAM control instruction PCON is a write only register There are three basic choices Main system clock fx or subsystem clock fxt Divided fx clock frequency of 4 8 or 64 Divided fxt clock frequency of 4 PCON 1 and 0 settings are also connected with the system clock mode control register SCMOD If SCMOD 0 0 the main system clock is always selected by the PCON 1 and 0 setting if SCMOD 0 1 the subsystem clock is selected A system reset sets PCON register values and SCMOD to logic zero Table 6 1 Power Control Register PCON Organization PCON Bit Settings Resulting CPU Operating Mode PCON 3 PCON 2 ELECTRONICS 6 5 OSCILLATOR CIRCUITS 557 3316 3316 59 PROGRAMMING Setting the CPU Clock To set the CPU clock to 0 89 us at 4 5 MHz BITS EMB SMB 15 LD A 3H LD INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on whether the main system clock fx or a subsystem clock fxt is used and on how the oscillator clock signal is divided by 4 8 or 6
169. c o o o The phase comparator compare the phase difference between divided frequency fy output from the programmable divider and the reference frequency fp output from the reference frequency generator The charge pump outputs the phase comparator s output from error output pins EO The relation between the error output pin divided frequency fy and reference frequency fp is shown below fR gt Low level output lt fx High level output 15 fy Floating level A PLL operation starts when a value is loaded to the PLMOD register The PLL unlock flag ULFG in the PLL flag register PLLREG provides status information regarding the reference frequency and divided frequency The unlock detector detects the unlock state of the PLL frequency synthesizer The unlock flag in the PLLREG register is set to 1 in an unlock state When ULFG 0 the PLL locked state is selected 15 6 ELECTRONICS KS57C3316 P3316 PLL FREQUENCY SYNTHESIZER PHASE DETECTOR CHARGE PUMP AND UNLOCK DETECTOR Continued The ULFG flag is set continuously at a period of reference frequency f by the unlock detector You must therefore read the ULFG flag in the PLLREG register at periods longer than 1 of the reference frequency ULFG is reset wherever it is read The PLLREG register can be read using 1 bit or 4 bit RAM control register instructions PLL operation is controlled by the state of the CE
170. c zero even number and is not replaced with the true value Load contents of EA to the 8 bit RRb register HL WX YZ The E register is loaded into the H W and Y register and the A register into the L X and Z register Load the A register to data memory location pointed to by the 8 bit HL register and the E register contents to the next location HL 1 The contents of the L register must be an even number If the number is odd the LSB of the L register is recognized as logic zero an even number and is not replaced with the true value For example LD HL 36H loads immediate 36H to register HL the instruction LD HL EA loads the contents of into address 36H and the contents of E into address 37H 5 63 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec LDB Load LDB dst src b LDB dst b src Load carry bit to a specified memory bit 2 memb QL C Load carry bit to a specified indirect memory bit H DA b C Load memory bit to a specified carry bit C memb L_ Load indirect memory bit to a specified carry bit C H DA b Description Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand One of the operands must be the carry flag the other may be any directly or indirectly addressable bit The source is unaffected Binary Code Operation Notation z NN IE 5 EXERKS
171. ce Basic timer stops Operates only if external SCK input is selected as the serial clock Operates only if TCL is selected as the counter clock Timer counterO Watch timer Operates only if subsystem clock fxt is selected as the counter clock LCD controller Operates only if a subsystem clock is selected as LCDCK INT1 INT2 and INT4 are acknowledged INTO is not serviced External interrupts STOP after setting SCMOD 2 to 1 Main clock fx Both main system clock and subsystem clock oscillation stop Basic timer stops Operates only if external SCK input is selected as the serial clock Operation stops Operation stops Operation stops INT1 INT2 and INT4 are acknowledged INTO is not serviced IDLE Main clock fx or Sub clock fxt Only CPU clock oscillation stops main and subsystem clock oscillation continues Basic timer operates with IRQB set at each reference interval Operates if a clock other than the CPU clock is selected as the serial I O clock Timer counter 0 operates Watch timer operates LCD controller operates INT1 INT2 and INT4 are acknowledged INTO is serviced 2 KS57C3316 P3316 CE pin Low input fx Main clock fx or Sub clock fxt Clock oscillation is not stopped Basic timer operates with IRQB set at each reference interval Serial I O interface operates Timer counter 0 operates Watch timer operates
172. ce routine can be initiated Multiple Interrupts By manipulating the two interrupt status flags ISO and 151 you can control service routine initialization and thereby process multiple interrupts simultaneously If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction Power Down Mode Release An interrupt can be used to release power down mode stop or idle but INTO is possible to release only idle when using fxx 64 clock Interrupts for power down mode release are initiated by setting the corresponding interrupt enable flag Even if the IME flag is cleared to zero power down mode will be released by an interrupt request signal when the interrupt enable flag has been set In such cases the interrupt routine will not be executed since IME 0 7 2 ELECTRONICS KS57C3316 P3316 INTERRUPTS Interrupt is generated INT xx Request flag IRQx 1 Retain value until IEx 1 Y es Generate corresponding vector interrupt and release power down mode No e MESE gt Retain value until IME 1 Yes Yes Retain value until interrupt service routine is completed IS1 0 1 0 Store conten
173. chip enable pin The PLL frequency synthesizer is disabled and the error output pin is set to floating state whenever the CE pin is Low When CE pin is High level the PLL operates normally The chip enable flag in the PLLREG register CEFC provides the status of the current level of the CE pin Whenever the state of the CE pin goes from Low to High the CEFG flag is set to 1 and a CE reset operation occurs When the CE pin goes from High to Low the CEFG flag is cleared to 0 and a CE interrupt is generated ELECTRONICS 15 7 PLL FREQUENCY SYNTHESIZER KS57C3316 P3316 USING THE PLL FREQUENCY SYNTHESIZER This section describes the steps you should follow when using the PLL direct frequency division method and the pulse swallow method In each case you must make the following selections in this order 1 Frequency division method Direct frequency division AM or pulse swallow FM 2 Output pin VCOAM or VCOFM 3 Reference frequency fn 4 Frequency division value N Direct Frequency Division Method Select the direct frequency division method by writing a 0 to PLMOD 3 The VCOAM pin is configured for input when you select the direct frequency division method Select the reference frequency by writing the appropriate values to the PLLREF register The frequency division value is y where the input frequency at the and fp is the reference frequency Example The followin
174. ck location During an interrupt sequence subroutines may be nested up to the number of levels which are permitted in the stack area INTERRUPT PUSH CALL When INT is acknowledged After PUSH SP lt SP 2 After CALL SP SP 6 Upper Register Figure 2 7 Push Type Stack Operations ELECTRONICS 2 13 ADDRESS SPACES KS57C3316 P3316 POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers for the PUSH instruction it is the POP instruction for CALL the instruction RET or SRET for interrupts the instruction IRET When a pop operation occurs the SP is incremented by a number determined by the type of operation and points to the next free stack location POP Instructions A POP instruction references the SP to write data stored in two 4 bit stack locations back to the register pairs and SB register The value of the lower 4 bit register is popped first followed by the value of the upper 4 bit register After the POP has executed the SP is incremented by two and points to the next free stack location RET and SRET Instructions The end of a subroutine call is signaled by the return instruction RET or SRET The RET or SRET uses the SP to reference the six 4 bit stack locations used for the CALL and to write this data back to the PC the EMB and the ERB After the RET or SRET has executed the SP is incremented by six and points to the next
175. clock of 4 5 MHz 1 1 1 52 PROGRAMMING Restarting TCO Counting Operation 1 Set TCO timer interval to 4 39 kHz BITS EMB SMB 15 LD EA 4CH LD TMODO EA 5 2 Clear TCNTO IRQTO and restart TCO counting operation BITS EMB SMB 15 BITS TMODO 3 ELECTRONICS 11 17 TIMERS and TIMER COUNTER KS57C3316 P3316 TCO COUNTER REGISTER The 8 bit counter register for timer counter 0 is read only and can be addressed by 8 bit RAM control instructions A system reset sets to OOH Whenever TMODO 3 is enabled is cleared to OOH and counting resumes The register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the register specifically TMODO 6 TMODO 5 and TMODO 4 Each time is incremented the new value is compared to the reference value stored in the TCO reference buffer TREFO When TCNTO TREFO an overflow occurs in the register the interrupt request flag IRQTO is set to 1 and an interrupt request is generated to indicate that the programmed timer counter interval has elapsed Reference Value n DN DRM DBE Match Match Timer Start Instruction IRQTO Set IRQTO Set 3 is set Figure 11 3 TCO Timing Diagram 11 18 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUN
176. conversion With a system clock frequency fxx 4MHz and setting ADCLK 0 the conversion time can be calculated as follows Start 1 clock 4 clock bit x 8 bits EOC 1 clock 34 clocks 34 x 2 4 MHz 17 us 13 4 ELECTRONICS KS57C3316 P3316 A D CONVERTER tinit lt gt ADSTR EOC Previous Vaild Value Value Remains Undetermined Data Figure 13 2 A D Converter Timing Diagram ADC PROCEDURE DESCRIPTION Use these steps as a general guideline for writing A D converter programs 1 Select one of the conversion clocks fxx 2 or fxx 4 Configure port to ADC input mode as using APCON register Select one of the four analog channels ADCO ADC3 as the analog input source To do this write the appro priate value to the ADMOD register bits ADMOD 1 ADMOD 0 Start the A D converter by setting the ADSTR flag of the AFLAG register to logic one When the converter starts the EOC End Of Conversion flag in the AFLAG register is automatically set to logic one and the ADSTR flag is cleared to logic zero 6 analog to digital conversion speed is determined by the oscillator frequency as follows tconv 34 x conversion clock fxx 2 or fxx 4 For example with a 4 5 MHz oscillator clock and fxx 4 the tegny value is 30 2 us The tinit value is determined by the instruction type and the speed of the CPU clock 7 When conversion has been completed the EOC flag is set autom
177. cs ELECTRONICS 4 1 MEMORY KS57C3316 P3316 Table 4 1 I O Map for Memory Bank 15 Memory Bank 15 Addressing Mode oe The address F82H F84H are not F89H address F8BH is not mapped ep oe ee ee The address F8FH is not F91H 5 5 address F93H is not mapped F96H TREFO F98H WDMOD F9AH WDTCF F9CH IFCNTO F9EH IFCNT1 See No No Yes The address Sa are not mapped a 2 w mw ve The address FAFH is not mapped Yes gt 2 ELECTRONICS KS57C3316 P3316 MEMORY MAP Table 4 1 Map for Memory Bank 15 Continued FBOH PSW 151 150 ERB RW Yes Yes Yes FB1H SC2 SCO FB2H FB3H FB4H 5 6 7 FB8H Register Yes 2 Yes 2 2 Yes w Ww v 1 4 IEB Yes The Address FB9H is not mapped E IEO IE2 4441 IMOD1 IMOD2 SCMOD 3 INT 8 IE4 FBBH INT B FBCH INT FBDH INT FBEH INT FBFH INT FCOH BSCO BSC1 2 5 2 5 7 FC4H PLLDO FC5H PLLD1 FC6H PLLD2 FC7H PLLD3 FC8H PLMOD PLLREF gt IRQIF 9 9 m
178. d Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs or when stop mode is terminated ELECTRONICS 19 7 53 7335 53 7335 7335 Table 19 6 Subsystem Clock Oscillator Characteristics TA 40 85 C Vpp 1 8V to 5 5V Crystal Oscillator External XT IN XTouT Clock input high and low level width txTH NOTES 1 Oscillation frequency and XT yy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs 19 8 ELECTRONICS 53 7335 7335 53 7335 Table 19 7 Input Output Capacitance TA 25 C Vpp 0 V 1 MHz Unmeasured pins are returned to Vas capacitance Table 19 8 A C Electrical Characteristics TA 40 to 85 C Vpp 1 8V to 5 5 V Symbol Conditions Instruction cycle Vpp 2 7 V to 5 5V 0 67 time 1 VDD 1 8V to 5 5V Interrupt input tINTH INTO 2 high low width INT1 2 INT4 KSO KS2 10 10 RESET and CE tRSL Input 1 Input Low Width NOTES 1 Unless otherwise specified Instruction Cycle Time condition values assume a main system clock 4 fx 4 source 2 Minimum value for INTO is based on a clock of 2t y or 128 fxx as assigned by the IMODO register setting Table 19 8 A C Electr
179. d to the ERB flag and bit 7 of the address to the flag and bit 7 of the address to the EMB flag EMB flag Stack pointer SP Undefined Undefined Data Memory RAM Working registers E A L H X W Z Y Undefined Bank selection registers SMB SRB BSC register BSCO BSC3 Clocks Power control register PCON Clock output mode register CLMOD System clock control register SCMOD Interrupt request flags IRQx Interrupt enable flags IEx Interrupt priority flag IPR Interrupt master enable flag IME INTO mode register IMODO INT1 mode register IMOD1 INT2 mode register IMOD2 d ELECTRONICS 9 3 RESET 557 3316 3316 Preliminary Spec Table 9 1 Hardware Register Values After a System Reset Continued If a Reset Occurs During Power Down Mode Hardware Component or Subcomponent Ports Output buffers Output latches Port mode flags PM Pull up resistor mode register PUMOD Port N ch open drain register PNE Basic Timer Count register BCNT Mode register BMOD Output enable flag BOE Timer Counter 0 Count registers Reference register TREFO Mode register TMODO Output enable flag TOEO Watch Dog Timer WDT mode register WDMOD WDT clear flag WDTCF Watch Timer Watch timer mode register WMOD LCD Driver Controller LCD mode register LMOD LCD control register LCON Display data memory Output buffers 9 4 Value
180. e PR ME E RR ur dibs ates ena 20 1 Target Bogarde osrin ccc ES 20 1 EAE TOE E 20 1 573316 Target Board 20 3 lid LEE 20 5 Stop LED 20 5 KS57C3316 P3316 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 3C7335 Simplified Block 1 4 1 2 9367335 80 QFP PIn ASSIQNIMGN io ceed senate 1 5 1 3 GIFCUlt tes n peo ede dada eot edo dete 1 9 14 2 1 9 1 5 Pin Circuit Type A 4 P 1 osi esc ete teinte b coute Ee ee eR Oed e ER HE 1 9 1 6 Pin Circuit Type B RESET Jarrett detta ede een depu p ieee 1 9 1 7 Pin Circuit Type t ee MN 1 9 1 8 Pin Circuit Type B 5 GE sits ies tiv be a i ed ei dece oria e ond 1 9 1 9 Pin Circuit Type C osi crescente ea dee Ge Aes 1 10 1 10 Pin Circuit Type D 2 re ee an ees ee 1 10 1 11 Piri Circuit ro iret oi eb e SUR REED DER DR oes 1 10 1 12 Pini Circuit Type D 7 ie cet eite cidem ade p Dune CORN da dee dde gee 1 10 1 13 Pin Circuit Type F 10 PS enisi c bad eee a Mane
181. e REF has a redundancy effect this effect is canceled and the referenced instruction is not skipped Ifthe instruction following the REF has a redundancy effect the instruction following the REF is skipped PROGRAMMING Example of the Instruction Redundancy Effect ORG 0020H ABC LD Stored REF instruction reference area ORG 0080H LD EA 40H Redundancy effect is encountered REF ABC No skip EA lt REF ABC EA lt 30 LD EA 50H Skip ELECTRONICS 5 3 SAM47 INSTRUCTION SET KS57C3316 P3316 Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear the SAM47 instruction set can also perform bit tests bit transfers and bit Boolean operations Bits can also be addressed and manipulated by special bit addressing modes Three types of bit addressing are supported mema b memb L 9H DA b The parameters of these bit addressing modes are described in more detail in Table 5 2 Table 5 2 Bit Addressing Modes and Parameters Addressing Mode Addressable Peripherals Address Range ERB 151 150 IRQx Ports 1 2 3 4 5 6 8 9 Ports 1 2 3 4 5 6 8 9 and BSC FCOH FFFH H DA b All bit manipulable peripheral hardware All bits of the memory bank specified by EMB and SMB that are bit manipulable Instructions Which Have Skip Conditions The following instructions have a
182. e any bit that is addressable using direct or indirect addressing modes DA b 1 DAbet 2222222 00 m memb 1 7 2 L 3 2 b L 1 0 1 H DA b DA 3 O b lt 1 22 Second Byte Bit Addresses monet E oe es feet ree 1 1 a2 TFFOHFFFH Examples 1 Assuming that bit location 30H 2 in the RAM has a current value of 0 the following instruction sets the second bit of location 30H to 1 BITS 30H 2 2 lt 1 2 You can use BITS the same way to manipulate port address bit BITS P2 0 2 0 lt 1 ELECTRONICS 5 33 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BITS Bit Set BITS Continued Examples LD BP2 BITS INCS JR 3 Given that P2 2 P2 3 and P3 0 P3 3 are set to 1 L 0AH P1 L First P1 OAH P2 2 111100B 10B 10B OF2H 2 L BP2 4 If bank 0 location 0 is set 1 and the EMB 0 BITS has the following effect FLAG EQU LD BITS 0 H 0AH H FLAG Bank 0 1 NOTE Since the BITS instruction is used for output functions pin names used in the examples above may change for different devices in the SAM47 product family 5 34 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET BOR Bit Logical OR BOR C src b
183. e by a reset is 29 1 ms at 4 5 MHz main oscillation clock 6 8 ELECTRONICS 557 3316 3316 Main operating mode Main Idle mode Main Stop mode Sub operating mode Sub Idle Mode Sub Stop mode Main Sub Stop mode NOTE current consumption is A gt B gt C gt D gt E Table 6 5 System Operating Mode Comparison Main oscillator runs Sub oscillator runs stops System clock is the main oscillation clock Main oscillator runs Sub oscillator runs stops System clock is the main oscillation clock Main oscillator runs Sub oscillator runs System clock is the main oscillation clock Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Main oscillator runs Sub oscillator is stopped by SCMOD 2 System clock is the main oscillation clock ELECTRONICS STOP or IDLE Mode Entering Method IDLE instruction STOP instruction IDLE instruction Setting SCMOD 2 to 1 This mode can be released only by an external RESET signal STOP instruction This mode can be released by an interrupt and reset OSCILLATOR CIRCUITS Current Consumption 6 9 OSCILLATOR CIRCUITS 557 3316 3316 SWITC
184. e value into the TREFO register TCNTO is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMODO 4 TMODO 5 settings To generate an interrupt request the TCO interrupt request flag IRQTO is set to 1 the status of TOLOis inverted and the interrupt is generated The content of TCNTO is then cleared to 00H and TCO continues counting The interrupt request mechanism for TCO includes an interrupt enable flag IETO and an interrupt request flag IRQTO 0 OPERATION SEQUENCE The general sequence of operations for using TCO can be summarized as follows Set TMODO 2 to 1 to enable TCO Set TMODO 6 to 0 to enable the system clock fxx input Set TMODO 5 and TMODO 4 bits to desired internal frequency 21 Load a value to TREFO to specify the interval between interrupt requests Set the TCO interrupt enable flag IETO to 1 Set TMODO 3 bit to 1 to clear TCNTO IRQTO and and start counting TCNTO increments with each internal clock pulse When the comparator shows TCNTO TREFO the IRQTO flag is set to 1 Output latch TOLO logic toggles high or low o o uoo 10 Interrupt request is generated 11 is cleared to OOH and counting resumes 12 Programmable timer counter operation continues until TMODO 2 is cleared to 11 12 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER TCO EVENT COUNTER FUNCTION Tim
185. ectly service them EREEBBERIT __ fo Ee Tt Example If the IME bit bit 3 of the IPR is logic one e g all instructions are enabled the instruction DI sets the IME bit to logic zero disabling all interrupts ELECTRONICS 5 51 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec El Enable Interrupts El Operation Operation Summary Bytes Cycles Description Bit 3 of the interrupt priority register IPR IME is set to logic one This allows all interrupts to be serviced when they occur assuming they are enabled If an interrupt s status latch was previously enabled by an interrupt this interrupt can also be serviced EREEBBBBIT __ 5 3 1 92 6 ic Example If the IME bit bit 3 of the IPR is logic zero e g all instructions are disabled the instruction EI sets the IME bit to logic one enabling all interrupts 5 52 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET IDLE Operation IDLE Description IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register PCON After an IDLE instruction has been executed peripheral hardware remains operative In application programs an IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three NOP instructions are
186. ector ral fxxX2 4 NOTE Instruction Execution Figure 14 1 Serial I O Interface Circuit Diagram 14 2 ELECTRONICS KS57C3316 P3316 SERIAL INTERFACE SERIAL I O MODE REGISTER SMOD The serial mode register SMOD is an 8 bit register that specifies the operation mode of the serial interface Its reset value is logic zero SMOD is organized in two 4 bit registers as follows SMOD register settings let you to select either MSB first or LSB first serial transmission and to operate in transmit and receive mode or receive only mode SMOD is a write only register and can be addressed only by 8 bit RAM control instructions One exception to this is SMOD 3 which can be written by a 1 bit RAM control instruction When SMOD 3 is set to 1 the contents of the serial interface interrupt request flag IRQS and the 3 bit serial clock counter are cleared and SIO operations are initiated When the SIO transmission starts SMOD 3 is cleared to logic zero Table 14 1 SIO Mode Register SMOD Organization Most significant bit MSB is transmitted first Least significant bit LSB is transmitted first Receive only mode output buffer is off Transmit and receive mode Disable the data shifter and clock counter retain contents of IRQS flag when serial transmission is halted Enable the data shifter and clock counter set IRQS flag to 1 when serial transmission is halted Clear IRQS flag and 3 bit clock counter to 0 initi
187. ee 11 13 TOO Glock Frequency 11 14 TCO Serial VO Clock Generation 11 15 TCO External Input Signal Divider pp 11 15 TCO Mode Register 0 11 16 TCO Counter Register i adet 11 18 TCO Reference Register 11 19 Watch Timer 11 21 11 21 Watch Timer Mode Register WMOD mee meme nene nhe hne 11 24 viii KS57C3316 P3316 MICROCONTROLLER Table of Contents Continued Chapter 12 LCD Controller Driver OVEIVIOW di lec avid eins eg ade Cie deeb Dive ed deities 5 derunt de eei LCD Control Registe ECON LCD Mode Register LMOD LCD Port Control Register LET LCD Drive Voltage LCD Voltage Dividing ResISIOrS 2n Common COM Signals eee a dece Segment SEG Signals cinerea ted ra a Po DRE Chapter 13 A D Converter e M EE ADC Dat
188. egisters E L H X W Z and Y PLL mode register PLL data register PLLDO PLLD3 Serial buffer register SBUF ELECTRONICS 9 1 RESET KS57C3316 P3316 Oscillation Stabilization 29 1ms 4 5 MHz Internal t RESET Signal Normal Mode or Power Down Idle Mode Operating Mode a Internal Reset Operation Figure 9 1 Reset Operation by RESET Pin c 2 9 Oscillation Stabilization 29 1ms 4 5 MHz Internal RESET Signal Normal Mode or Power Down Mode Idle Mode Operating Mode lene Internal Reset Operation Figure 9 2 Reset Operation by CE Pin 9 2 ELECTRONICS KS57C3316 P3316 RESET HARDWARE REGISTER VALUES AFTER A SYSTEM RESET Table 9 1 gives you detailed information about hardware register values after a system reset occurs during power down mode or during normal operation Table 9 1 Hardware Register Values After a System Reset Hardware Component If a Reset Occurs During Power If a Reset Occurs During or Subcomponent Down Mode Normal Operation Program counter PC 13 8 lt ADDR 00H 13 8 ROM ADDR PC7 0 lt ROM ADDR 01H PC7 0 lt ADDR 01H Program Status Word PSW Interrupt status flags IS0 IS1 Bank enable flags EMB ERB Bit 6 of address OOOOH in program Bit 6 of address OOOOH in program memory is transferred to the ERB memory is transferre
189. er counter 0 can monitor or detect system events by using the external clock input at the TCLO pin I O port 0 2 as the counter source The TCO mode register selects rising or falling edge detection for incoming clock signals The counter register is incremented each time the selected states transition of the external clock signal occurs With the exception of the different TMOD0 4 TMOD0 6 settings the operation sequence for TCO s event counter function is identical to its programmable timer counter function To activate the TCO event counter function Set TMODO0 2 to 1 to enable TCO Clear TMODO 6 to 0 to select the external clock source at the TCLO pin Select TCLO edge detection for rising or falling signal edges by loading the appropriate values to TMODO 5 and TMODO 4 0 2 must be set to input mode Table 11 5 TMODO Setting for TCLO Edge Detection TMODO 6 TMODO 5 TMODO 4 TCLO Edge Detection Rising edges ELECTRONICS 11 13 TIMERS TIMER COUNTER KS57C3316 P3316 TCO CLOCK FREQUENCY OUTPUT Using timer counter 0 you can output a modifiable clock frequency to the TCO clock output pin TCLOO To select the clock frequency you load the appropriate value to the TCO mode register TMODO The clock interval is selected by loading the desired reference value into the reference register TREFO To enable the output to the TCLOO pin at port 0 1 the following conditions must be met
190. ernal clock source and loading a reference value into the TCO reference register TREFO you can divide the incoming clock signal by the TREFO value and then output this modified clock frequency to the TCLOO pin The sequence of operations used to divide external clock input can be summarized as follows 1 Load signal divider value to the TREFO register Clear TMODO 6 to 0 to enable external clock input at the TCLO pin Set TMODO 5 and TMODO 4 to desired TCLO signal edge detection Set port 0 1 output mode flag PMO 1 to output 1 Set P0 1 output latch to 0 Set TOEO flag to 1 to enable output of the divided frequency to the TCLOO pin 59 PROGRAMMING External TCLO Clock Output to the TCLOO Pin Output external TCLO clock pulse to the TCLOO pin divided by four External TCLO Clock Pulse TCLOO Output Pulse LD EA 79H LD TREFO EA LD EA 0CH LD TMODO EA LD EA 02H LD P0 1 lt output mode BITR PO 1 P 0 1 BITS TOEO ELECTRONICS 11 15 TIMERS TIMER COUNTER KS57C3316 P3316 TCO MODE REGISTER TMODO TMODO is the 8 bit mode control register for timer counter 0 It is addressable by 8 bit write instructions One bit TMODO 3 is also 1 bit writeable A system reset clears TMODO to 00H and disables TCO operations 0 2 is the enable disable bit for timer counter 0 When TMODO 3 is set to 1 the contents of TCNTO IRQTO and T
191. errupt enable flags can be read written or tested directly by 1 bit instructions IEx flags can be addressed directly at their specific RAM addresses despite the current value of the enable memory bank EMB flag Table 7 7 Interrupt Enable and Interrupt Request Flag Addresses ms ma m rm o o E e e Ee mm NOTES 1 IEx refers generally to all interrupt enable flags 2 IRQxrefers generally to all interrupt request flags 3 IEx 0 is interrupt disable mode 4 1 is interrupt enable mode 7 12 ELECTRONICS KS57C3316 P3316 INTERRUPTS Interrupt Request Flags IRQx Interrupt request flags are read write addressable by 1 bit or 4 bit instructions IRQx flags can be addressed directly at their specific RAM addresses regardless of the current value of the enable memory bank EMB flag When a specific IRQx flag is set to logic one the corresponding interrupt request is generated The flag is then automatically cleared to logic zero when the interrupt has been serviced Exceptions are the watch timer interrupt request flags IRQW and the external interrupt 2 flag IRQ2 which must be cleared by software after the interrupt service routine has executed IRQx flags are also used to execute interrupt requests from software In summary follow these guidelines for using IRQx flags 1 IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generati
192. f STOP Instruction Figure 19 3 Stop Mode Release Timing When Initiated by RESET Idle Mode Operating Execution of STOP Instruction Power down Mode Terminating Signal Interrupt Request Figure 19 4 Stop Mode Release Timing When Initiated by an Interrupt Request ELECTRONICS 19 13 53 7335 53 7335 7335 0 8 VDD _ _w 0 8 VDD Measurement Points 0 2 4 7 0 2 Figure 19 5 A C Timing Measurement Points Except for XIN 0 1 V 0 1 V Figure 19 6 Clock Timing Measurement at XIN 0 1 V 0 1 V Figure 19 7 Clock Timing Measurement at XTIN 19 14 ELECTRONICS 53 7335 7335 53 7335 Figure 19 8 Input Timing for RESET Signal INTO 1 2 4 0 to KS2 Figure 19 9 Input Timing for External Interrupts and Quasi Interrupts ELECTRONICS 19 15 53 7335 53 7335 7335 5 19 16 ELECTRONICS KS57C3316 P3316 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for KS57 KS86 KS88 families of mic
193. f P2 0 0 then skip RET If P2 0 1 then return JP LABEL3 ELECTRONICS 5 37 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BTSF Bit Test and Skip on False BTSF Continued Examples 3 P2 2 P2 3 and P3 0 P3 3 are tested LD L 0AH BP2 BTSF P1 O OL First P1 90AH P2 2 111100B 10B 10B 2 2 RET INCS L JR BP2 4 Bank 0 location 0 is tested and regardless of the current EMB value BTSF has the following effect FLAG EQU 0 BITR EMB LD H 0AH BTSF H FLAG If bank 0 AH 0 OAOH O 0 then skip RET 5 38 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET BTST Bit Test and Skip on True BTST dst b Operation Test carry bit and skip if set 1 DA b Test specified bit and skip if memory bit is set H DA b Description specified bit within the destination operand is tested If it is 1 the instruction that immediately follows the BTST instruction is skipped otherwise the instruction following the BTST instruction is executed The destination bit value is not affected DA b m od memb L Skip if memb 7 2 L 3 2 L 1 0 1 Dis H DAb 1 1 1 1 1 0 0 1 5 3 0 f o v1 bo Second Byte Bit Addresses EL ies jt fot FFonFF Examples 1 If RAM bit location 30H 2 is
194. fxx 233 ms 1 Input clock frequency fxx 29 8 789 kHz Signal stabilization interval 217 29 1 ms Input clock frequency 27 35 16 kHz Signal stabilization interval 215 7 28 ms 1 Input clock frequency fxx 2 140 6 kHz Signal stabilization interval 213 1 82 ms 0 Always logic zero NOTES 1 Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt The stabilization interval can also be interpreted as Interrupt Interval Time 2 When asystem reset occurs the oscillation stabilization time is 29 1 ms 217 at 45 MHz 3 fxx is the system clock rate given a clock frequency of 4 5 MHz ELECTRONICS 4 11 MEMORY KS57C3316 P3316 clock Output Mode Register FDOH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 4 4 4 3 Clock Output Enable Bit 2 Bit 2 Always logic zero 1 and 0 Clock Source and Frequency Selection Bits CPU clock source fxx 4 fxx 8 or fxx 64 1 125 MHz 562 5 kHz or 70 312 kHz Disable clock output 1 Enable clock output 1 System clock fxx 8 562 5 kHz 1 System clock fxx 16 281 25 kHz System clock fxx 64 70 312 kHz NOTE fxx is the system clock at an oscillator frequency of 4 5 MHz 4 12 ELECTRONICS 557 3316 3316 MEMORY IEO 1 j IRQO 1 INTO 1 Interrupt Enable Request Flags FBE
195. g data are used to receive an AM band broadcasting station Receive frequency 1422 kHz Reference frequency 9 kHz Intermediate frequency 450 kHz The frequency division value N is calculated as follows fVcoaM im fn fR 208 decimal hexadecimal You would modify the PLL data register and PLMOD register as follows PLLD3 PLLD2 PLLD1 PLLDO PLMOD NF 1 1 0 1 0 0 0 NOTE the direct method the contents of PLLDO and NF are not evaluated 15 8 ELECTRONICS KS57C3316 P3316 PLL FREQUENCY SYNTHESIZER Pulse Swallow Method 1 Select the pulse swallow method by writing a 1 to PLMOD 3 The VCOFM pin is configured for input when you select the pulse swallow method Select the reference frequency by writing the appropriate value to the PLLREF register Boom Calculate the frequency division value as follows N COFM fR where fV copy is the input frequency at the VcoFM and fp is the reference frequency Example The following data are used to receive an FM band broadcasting station Receive frequency 100 0 MHz Reference frequency 25 kHz Intermediate frequency 10 7 kHz The frequency division value N is calculated as follows fV 6 _ _ 100 0 10 7 x 10 4428 decimal fn 2 x 25 x 103 114CH hexadecimal You would modify the PLL data register and PLMOD register as follows PLLD3 PLLD2 PLLD1 PLLDO PLMOD NF
196. geable Microcontrollers With features such as LCD direct drive capability 4 channel A D converter 8 bit timer counter watch timer and PLL frequency synthesizer it offers you an excellent design solution for a wide variety of applications that require LCD functions and audio applications Up to 56 pins of the 80 pin QFP package it can be dedicated to I O Eight vectored interrupts provide fast response to internal and external events In addition the S3C7335 s advanced CMOS technology provides for low power consumption and a wide operating voltage range OTP The S3C7335 microcontroller is also available in OTP One Time Programmable version S3P7335 The S3P7335 6 microcontroller has an on chip 16 Kbyte one time programmable EPROM instead of masked ROM The S3P7335 6 is comparable to S3C7335 both in function and pin configuration ELECTRONES 1 1 PRODUCT OVERVIEW FEATURES Memory e 512 RAM e 16K byte ROM Pins e Input only 4 pins e Output only 28 pins e l O 24 pins LCD Controller Driver e Maximum 14 digit LCD direct drive capability 28 segment x 4 common signals e Display modes Static 1 2 duty 1 2 bias 1 3 duty 1 2 or 1 3 bias 1 4 duty 1 3 bias 8 Bit Basic Timer e Programmable interval timer functions e Watch dog timer function 8 Bit Timer Counter e Programmable 8 bit timer e External event counter e Arbitrary clock frequency output e External clock signal divider e
197. graphics information is arranged in the following order Standard Electrical Characteristics Absolute maximum ratings D C electrical characteristics System clock oscillator characteristics capacitance A C electrical characteristics Operating voltage range Miscellaneous Timing Waveforms A C timing measurement point Clock timing measurement at Xy Clock timing measurement at XT i Input timing for RESET Input timing for external interrupts and Quasi Interrupts Stop Mode Characteristics and Timing Waveforms RAM data retention supply voltage in stop mode Stop mode release timing when initiated by RESET Stop mode release timing when initiated by an interrupt request ELECTRONES 17 1 ELECTRICAL DATA KS57C3316 P3316 Table 17 1 Absolute Maximum Ratings Ta 25 Symbol Conditions Units Input voltage Applies to all I O ports 0 3 to Vpp 0 3 Output current high One I O port active mA AIL VO poris active Output current low One I O port active 30 peak value 15 note Total value for output ports 100 peak value 60 NOTE The values for output current low lo are calculated as Peak Value xy Duty 17 2 ELECTRONES KS57C3316 P3316 ELECTRICAL DATA Table 17 2 D C Electrical Characteristics TA 25 C to 85 1 8V to 5 5 V Symbol Conditions Typ Max Units Input high All input pins except those specified 0 7
198. h timer clock selection WMOD 0 Watch timer speed control WMOD 1 Enable disable watch timer WMOD 2 XTy input level test WMOD 3 Buzzer frequency selection WMOD 4 and WMOD 5 Enable disable buzzer output WMOD 7 Table 11 8 Watch Timer Mode Register WMOD Organization sime vaws pm WMOD 7 WMOD 6 Disable buzzer BUZ signal output F89H 1 Enable buzzer BUZ signal output Always logic zero WMOD5 4 o 2kHz buzzer BUZ signal output ofa 4 kHz buzzer BUZ signal output 1 8 kHz buzzer BUZ signal output 16 kHz buzzer BUZ signal output 1 1 WMOD 3 Input level to pin is low F88H Input level to pin is high Enable watch timer Normal mode sets IRQW to 0 5 seconds WMOD 1 d High speed mode sets IRQW to 3 91 ms WMOD 0 Select fxx 128 as the watch timer clock fw 1 Select subsystem clock fxt as watch timer clock fw NOTE System clock frequency fxx is assumed to be 4 19 MHz subsystem clock fxt is assumed to be 32 768 kHz WMOD 2 Disable watch timer clear frequency dividing circuits I 11 24 ELECTRONICS 557 3316 3316 PROGRAMMING Using the Watch Timer TIMERS and TIMER COUNTER 1 Select a subsystem clock as the LCD display clock 0 5 second interrupt and 2 kHz buzzer enable BITS SMB EMB 15 EA 08H PMGO EA EA 85H WMOD EA IEW 2 Sample real time clock processing method C
199. hasta 27 dob55V 400 width External SCK source k 67 14 48 00 50 Internal SCK source 2 50 1 8 V to 5 5V 1600 External SCK source Internal SCK source tkcy 2 150 SI setup time to External SCK source 100 SCK high Internal SCK source 150 SI hold time to External SCK source 400 SCK high Internal SCK source 400 Output delay for tkso Vpp 2 7 V to 5 5V SCK to SO External SCK source 1 8 V to 5 5 V External SCK source NOTE Unless otherwise specified Instruction Cycle Time condition values assume a main system clock 4 fx 4 source ELECTRONICS 19 11 53 7335 53 7335 7335 CPU Clock Main Oscillator Frequency 15MHz _ 6 MHz EBEN o ee ioe _ _ 2 3 4 Supply Voltage V CPU Clock 1 n x oscillator frequency n 4 8 or 64 When PLL IFC operation operating voltage range is 2 5 V to 3 5 V or 4 0 V to 5 5 V Figure 19 2 Standard Operating Voltage Range Table 19 9 RAM Data Retention Supply Voltage in Stop Mode 40 C to 85 Data retention supply voltage Normal operation 18 9 pee Data retention supply current Vpppr 1 8 V 19 12 ELECTRONICS 53 7335 7335 S3P7335 OTP TIMING WAVEFORMS Internal RESET Operation 4 31 Stop Mode gt Idle Mode Data Retention Mode Operating Mode A Execution o
200. he current SMB value For 8 bit addressing two 4 bit registers are addressed as a register pair Also when using 8 bit instructions to address RAM locations remember to use the even numbered register address as the instruction operand Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks bank 0 1 2 and 3 Each register bank has eight 4 bit registers and paired 4 bit registers are 8 bit addressable Register A is used as a 4 bit accumulator and register pair EA as an 8 bit extended accumulator The carry flag bit can also be used as a 1 bit accumulator Register pairs WX WL and HL are used as address pointers for indirect addressing To limit the possibility of data corruption due to incorrect register addressing it is advisable to use register bank 0 for the main program and banks 1 2 and 3 for interrupt service routines LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 1 Register locations in this area that are not used to store LCD data can be assigned to general purpose use 2 6 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES Table 2 2 Data Memory Organization and Addressing 000H 01FH Working registers 020 Stack and general purpose registers 100H 1E3H General purpose registers 1 1 1 1E4H 1FFH Display registers F80H FFFH hardware registers 59 PROGRAMMING Clearing Data Memory Banks
201. hen enable SBUF read write operation x means don t care 1 4 39 kHz clock fxx 210 1 1 1 281 kHz clock 24 NOTE You cannot select a 24 clock frequency if you have selected a CPU clock of fxx 64 Not used Always logic zero Serial I O Start Bit Clear IRQS flag and 3 bit clock counter to logic zero then initiate serial transmission When SIO transmission starts this bit is cleared by hardware to logic zero SIO Data Shifter and Clock Counter Enable Disable Bit Disable the data shifter and clock counter the contents of IRQS flag is retained when serial transmission is completed 1 Enable the data shifter and clock counter the contents of IRQS flag is set to logic one when serial transmission is completed Serial Transmission Mode Selection Bit Receive only mode Transmit and receive mode LSB MSB Transmission Mode Selection Bit Transmit the most significant bit MSB first Transmit the most significant bit LSB first 4 41 MEMORY KS57C3316 P3316 NOTE All frequency given in kHz assume a system clock of 4 5 MHz TMODO rimer Counter 0 Mode Register F91H F90H Bit 3 2 1 0 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W Bit Addressing 8 8 8 1 8 8 7 Not used Always logic zero 6 4 Timer 0 Input Clock Selection Bits External clock input at TCLO on rising edge ERES External clock input at T
202. ical Characteristics continued Ty 10 to 70 Vpp 3 5 to 5 5 V A D converting Resolution Absolute accuracy 17 34 fxx note Analog input VIAN Vss V voltage Analog input Ran Vpp 5 2 1000 MQ impedance NOTE stands for the system clock fx or fxt 2 DD AD conversion tcon time ELECTRONICS 19 9 53 7335 53 7335 7335 Table 19 8 A C Electrical Characteristics Continued TA 40 to 85 2 5 V to 3 5 V or Vpp 4 0 V to 5 5 V VCOFM VCOAM VIN Sine wave input FMIF and AMIF Input Voltage Peak to Peak Frequency VCOAM mode sine wave input Vin 03Vp p VCOFM mode sine wave input Vin 0 3Vp p fAMIF AMIF mode sine wave input Vi 0 3V p p FMIF mode sine wave input N 0 3VP P 19 10 ELECTRONICS 53 7335 7335 53 7335 Table 19 8 A C Electrical Characteristics continued Ty 40 to 85 Vpp 1 8V to 5 5 V Instruction cycle Vpp 2 7 V 5 5V 0 time 1 1 8V to 5 5 fxt 1 0 With subsystem clock fxt Vpp 2 7 V to 5 5 1 8 to 5 5V TCLO input high tn Vpp 2 7 V to 5 5 V low width TCLO input frequency 1 8 V to 5 5 V SCK cycle time tkcv 2 7 V to 5 5 V 8 External SCK source 1 8 V to 5 5 V 3200 External SCK source Internal SCK source 3800 SCK high low
203. ified by the HL register is RCF 0 LD A 8H A lt 8H ADS A 6H A lt 8H 6H OEH ADC A HL 7H C lt 1 ADS A 0AH Skip this instruction because C 1 after ADC result JPS XXX 9 4 decimal addition the contents of the address specified by the HL register is 4H RCF C e 0 LD lt ADS A 6H A 3H 6H 9H ADC A HL A lt 9H 4H 0 ADS A 0AH Noskip lt OAH 7H The skip function for ADS A im is inhibited after an ADC A QHL instruction even if an overflow occurs JPS XXX ELECTRONICS 5 25 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec ADS And Skip On Overflow ADS dst src Add 4 bit immediate data to A and skip on overflow 1 5 Add 8 61 immediate data to EA and skip on overflow 2 5 A HL Add indirect data memory to A and skip on overflow 1 5 Add register pair RR contents to EA skip 2 2 5 overflow RRb EA Add EA to register pair RRb and skip on overflow 245 Description source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the skip signal is generated and a skip is executed but the carry flag value is unaffected If ADS A im follows an ADC A HL instruction in a program ADC skips the ADS instruction if an overflow
204. is EE EAEE EA A cO du 1 9 Chapter 2 Address Spaces Program Memory ROM een 2 1 VOIVIOW teat cde ete 2 1 General Purpose Memory 2 2 Vector Address Area ie ei eade a ie 2 2 Instruction Reference Area coii tta ua Ente a iie PO Ene e Gea Ede Era dns 2 4 Data Memory boxe Cus Mage Der GER 2 5 c M O Ow mH 2 5 Working Registers 2 30 cete t oc ett tote Pete M 2 8 Stack OperatlOns debe em debi 2 12 Stack Pointer SP i oer ct do utes un poe cle aut eee eter Eee ced mv doe dele tour 2 12 PusH Operatioris s cn eene RE 2 13 Pop Operations HH 2 14 Bit Sequential Carrier BSC 2 15 Program Counter ROGER 2 16 Program Status OP 2 16 Interrupt Status Flags 150 2 17 EMS Fiag TE ree 2 18 ERB Flag Em 2 19 Skip Condition
205. is used as the signal source according to the following formula y doki amp stem cock IX 32768 kHz hx 4 19 MHz This feature is useful for controlling timer related operations during stop mode When stop mode is engaged the main system clock fx is halted but the subsystem clock continues to oscillate By using the subsystem clock as the oscillation source during stop mode the watch timer can set the interrupt request flag IRQW to 1 thereby releasing stop mode Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller f Therefore if the watch timer is disabled the LCD controller does not operate ELECTRONICS 11 21 TIMERS and TIMER COUNTER KS57C3316 P3316 Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz 4 kHz 8 kHz or 16 kHz signal to the BUZ pin To select the desired BUZ frequency load the appropriate value to the WMOD register This output can then be used to actuate an external buzzer sound To generate a BUZ signal three conditions must be met The WMOD 7 register bit is set to 1 The port 0 3 output mode flag PMO 3 set to output mode The output latch for I O port 0 3 is cleared to 0 Timing Tests in High Speed Mode By setting WMOD 1 to 1 the watch timer will function in high speed mode generating an interrupt every 3 91 ms At its normal speed WMOD 1 07 the watch timer ge
206. istics Ta 25 to 85 1 8V to 55V Symbol _ Conditions Instruction cycle Vpp2 2 7 V to 5 5V time 1 1 8 V to 5 5 V Interrupt input tintH INTO high low width INT1 INT2 INT4 KS0 KS2 10 RESET and CE tRSL Input Input Low Width NOTES 1 Unless otherwise specified Instruction Cycle Time condition values assume a main system clock 4 fx 4 source 2 Minimum value for INTO is based on a clock 24 or 128 fxx as assigned by the IMODO register setting Table 17 6 A C Electrical Characteristics Continued Ta 10 to 70 Vp 3 5 V to 55V NOTE stands for the system clock fx or fxt 8 17 8 ELECTRONES KS57C3316 P3316 ELECTRICAL DATA Table 17 6 A C Electrical Characteristics Continued Ta 25 to 85 Vp 2 5 V to 3 5 Vor Vp 4 0 V to 5 5 V EM ML UE VCOFM VCOAM Sine wave input FMIF and AMIF Input Voltage Peak to Peak mode sine wave input 5 Vin 0 3Vp_p Frequency fVcoAM VCOAM mode sine wave input Vin 03V PP VCOFM mode sine wave input Vin 0 3V pp mode she wave input Vi 0 1 0 3V PP ELECTRONES 17 9 ELECTRICAL DATA KS57C3316 P3316 Table 17 6 A C Electrical Characteristics Concluded Ta 25 C to 85 Vp 1 8V to 5 5 Parameter Symbol Conditions Typ Max Units us Instruction cycle tcy 2 7 V to
207. it Accumulator 1 Set the carry flag to logic one SCF Cet LD EA 0C3H EA lt 0C3H LD HL Z0AAH HL lt 0AAH ADC EA HL EA lt 0C3H C lt 1 2 Logical AND bit 3 of address 3FH with P3 3 and output the result to P2 0 LD Set the upper four bits of the address to the register value LDB C H 0FH 3 lt bit 3 of BAND C P3 3 C lt AND P3 3 LDB P2 0 C Output result from carry flag to P2 0 ELECTRONICS 2 21 ADDRESS SPACES KS57C3316 P3316 NOTES 2 22 ELECTRONICS KS57C3316 P3316 ADDRESSING MODES ADDRESSING MODES OVERVIEW The enable memory bank flag EMB controls the two addressing modes for data memory When the EMB flag is set to logic one you can address the entire RAM area when the EMB flag is cleared to logic zero the addressable area in the RAM is restricted to specific locations The EMB flag works in connection with the select memory bank instruction SMB n You will recall that the SMB n instruction is used to select RAM bank 1 or 15 The SMB setting is always contained in the upper four bits of a 12 bit RAM address For this reason both addressing modes EMB 0 and EMB 1 apply specifically to the memory bank indicated by the SMB instruction and any restrictions to the addressable area within banks 0 1 or 15 Direct and indirect 1 bit 4 bit and 8 bit addressing methods can be used Several RAM locations are addressable at all times regardle
208. k by manipulating the SCMOD 3 and SCMOD O bit settings If SCMOD 3 0 and SCMOD 0 1 the subsystem clock is selected and main system clock oscillation continues If SCMOD 3 1 and SCMOD 0 1 fxt is selected but main system clock oscillation stops If you have selected fx as the CPU clock setting SCMOD 3 to 1 will stop main system clock oscillation But this mode must not be used To stop main system clock oscillation safely main oscillation clock should be stopped only by a STOP instruction in main system clock mode Table 6 3 System Clock Mode Register SCMOD Organization SCMOD Register Bit Settings Resulting Clock Selection SCMOD 3 SCMOD 2 SCMOD 0 fx Oscillation fxt Oscillation CPU Clock note e o NOTE CPU clock is selected by PCON register settings ELECTRONICS 6 7 OSCILLATOR CIRCUITS 557 3316 3316 Table 6 4 Main or Sub Oscillation Stop Mode Condition Method to issue Osc Stop Stop Release Source 2 Main oscillator runs Sub oscillator runs or stops System is operating with the main clock Main Oscillation STOP Mode Main oscillator runs Sub oscillator runs System is operating with sub clock Sub Main oscillator runs Oscillation Sub oscillator runs STOP Mode System is operating with the main clock Main oscillator runs or stops Sub oscillator runs
209. k pointer are popped into the program counter a Code Operation Notation Notation PC13 8 SP 1 SP 7 0 SP 3 SP 2 lt SP 4 1 ERB lt SP 4 0 SP lt SP 6 then skip If the stack pointer contains the value OFAH and RAM locations OFAH OFBH OFCH and OFDH contain the values 1H 5H and 2H respectively the instruction SRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0125H then skips unconditionally During a return from subroutine data is popped from the stack to the PC as follows ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET STOP Stop Operation STOP Operation Description Example The STOP instruction stops the system clock by setting bit 3 of the power control register PCON to logic one When STOP executes all system operations are halted with the exception of some peripheral hardware with special power down mode operating conditions In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three NOP instructions are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus as tele Given that bit 3 of the PCON register is cleared to logic zero and all sys
210. l Bit Disconnect port 0 pull up resistor Connect port 0 pull up resistor lel NOTE Pull up resistors for all I O ports are automatically disabled when they are configured to output mode ELECTRONICS 4 3 MEMORY KS57C3316 P3316 SCMOD System Clock Mode Control Register FB7H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 1 1 1 3 2 and 0 CPU Clock Selection and Main System Clock Oscillation Control Bits Select main system clock fx enable main system clock Select main system clock fx disable sub system clock 5 f elect sub system clock fxt enable main system clock Select sub system clock fxt disable main system clock Always logic zero NOTE SCMOD bits 3 and 0 cannot be modified simultaneously by a 4 bit instruction they can only be modified by separate 1 bit instructions 4 40 ELECTRONICS KS57C3316 P3316 MEMORY MAP SMOD serial 1 0 Mode Register FE1H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W Bit Addressing 8 8 8 1 8 8 8 8 7 5 ELECTRONICS CPU Clock Selection and Main System Clock Oscillation Control Bits Use an external clock at the SCK pin Enable SBUF when SIO operation is halted or when SCK goes High 1 Use the TOLO clock from timer counter 0 Enable SBUF when SIO operation is halted or when SCK goes High 1 Use the selected CPU clock fxx 4 8 or 64 fxx is the system clock t
211. lag The source value is unaffected Binary Code Operation Notation C mema b mema b 1 L2 C memb L pee C XOR memb 7 2 L 3 2 L 1 0 0 0 as a4 c HDAb 1 1 1 1 1 XOR H DA3 0 b o o bt bo a2 Jat Second Byte BitAddresses Addresses 1 1 a ao FFonFF Examples 1 The carry flag is logically XORed with the P1 0 value RCF BXOR 1 0 2 lt 0 IfP1 0 1 then lt 1 if P1 0 then lt 2 The P1 address is FF1H and register L contains the value 9H 1001B The address memb 7 2 is 111100 and 1 3 2 10B The resulting address is 11110010B or FF2H specifying P2 The bit value for the BXOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD L 9H BXOR C P1 L P1 L is specified as P2 1 C XOR 2 1 ELECTRONICS 5 43 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec BXOR Bit Exclusive OR BXOR Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and 3 0 is 0000 The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20 3 LD H 2H BXOR C H FLAG XOR FLAG 20H 3 5 44 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET CALL
212. lator Stop Signal Frequency dividing Circuit 1 2 1 16 fx 1 2 16 Y SCMOD 3 SCMOD 0 gt SCMOD2 fxt 1 1 1 1 1 1 1 1 1 1 1 v 1 XTIN 1 i 1 OSCILLATOR CIRCUITS Watch Timer Sub System LCD Controller Oscillator Basic Timer Timer Counter 0 Watch Timer Serial Interface LCD Controller A D Converter PLL Frequency Synthesizer IF Converter PCON 1 1 4 CPU stop signal By IDLE or STOP instruction CPU Clock Wait release signal Oscillator Control Circuit 2 PCON 3 Internal system reset signal Power down release signal PCON 3 2 clear fx Main system clock fxt Sub system clock fxx System clock Figure 6 1 Clock Circuit Diagram ELECTRONICS 6 3 OSCILLATOR CIRCUITS 557 3316 3316 MAIN SYSTEM OSCILLATOR CIRCUITS SUBSYSTEM OSCILLATOR CIRCUITS XIN XOUT Figure 6 2 Crystal Ceramic Oscillator Figure 6 4 Crystal Ceramic Oscillator XIN External Clock XOUT Figure 6 3 External Oscillator Figure 6 5 External Oscillator 6 4 ELECTRONICS 557 3316 3316 OSCILLATOR CIRCUITS POWER CONTROL REGISTER PCON The power control register PCON is a 4 bit register that is used to select the CPU clock frequency and to control CPU operating and power down modes The PCON can be addressed directly by 4 bit write instructions or indirectly
213. le 12 7 LCD Drive Voltage Values LCD Power Supply Static Mode 1 2 Bias 1 3 Bias NOTE TheLCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage LCD VOLTAGE DIVIDING RESISTORS On chip voltage dividing resistor for the LCD circuit are configured by software option LMOD 7 Using these optional internal voltage resistor you can drive a 2 5V 3V or 5V LCD panel using external biasing BIAS pins are connected externally to the pin so that it can handle the different LCD drive voltage To cut off the current supply to the voltage dividing resistors clear 1 when you turn the LCD display off COMMON COM SIGNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle n static mode COMO pin is selected In 1 2 duty mode COMO COM pins are selected In 1 3 duty mode COMO CONM2 pins are selected n 1 4 duty mode 0 pins are selected SEGMENT SEG SIGNALS The 28 LCD segment signal pins are connected to corresponding display RAM locations at bank 1 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin
214. le 6 6 4 means available 5 fx Main system clock Sub system clock M C Machine Cycle When fx is 4 5 MHz and fxt is 32 768 kHz PROGRAMMING Switching Between Main System and Subsystem Clock 1 Switch from the main system clock to the subsystem clock MA2SUB BITS SCMOD 0 Switches to subsystem clock CALL DLY80 Delay 80 machine cycles BITS SCMOD 3 Stop the main system clock RET DLY80 LD A 0FH DEL1 NOP NOP DECS A JR DEL1 RET 2 Switch from the subsystem clock to the main system clock SUB2MA BITR SCMOD 3 Start main system clock oscillation CALL DLY80 Delay 80 machine cycles CALL DLY80 Delay 80 machine cycles BITR SCMOD 0 Switch to main system clock RET ELECTRONICS 6 11 OSCILLATOR CIRCUITS 557 3316 3316 CLOCK OUTPUT MODE REGISTER CLMOD The clock output mode register CLMOD is a 4 bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency CLMOD is addressable by 4 bit write instruction only FDOH CLMOD3 9 CLMOD 1 CLMOD 0 RESET clears CLMOD to logic zero which automatically selects the CPU clock as the clock source without initiating clock oscillation and disable clock output CLOMD 3 is the enable disable clock output control bit CLOMD 1 and CLOMD 0 are used to select one of four possible clock sources and frequencies normal CPU clock fx 8 fx 16 or fx 64 Table 6 7
215. lock fxt as the CPU clock and to start or stop main or sub system clock oscillation The resulting clock source either main system clock or subsystem clock is referred to as the CPU clock The main system clock is selected and oscillation started when all SCMOD bits are cleared to logic zero By setting SCMOD 3 2 and SCMOD 0 to different values CPU can operate a subsystem clock source and start or stop main or sub system clock oscillation To stop main system clock oscillation you must use the STOP instruction assuming the main system clock is selected or manipulate SCMOD 3 to 1 assuming the sub system clock is selected The main system clock frequencies can be divided by 4 8 or 64 and a subsystem clock frequencies can only be divided by 4 By manipulating PCON bits 1 and 0 you select one of the following frequencies as CPU clock fx 4 fxt 4 fx 8 fx 64 Using a Subsystem Clock If a subsystem clock is being used as the selected system clock the idle power down mode can be initiated by executing an IDLE instruction The subsystem clock be stopped by setting SCMOD 2 to 1 The watch timer buzzer and LCD display operate normally with a subsystem clock source since they operate at very slow speeds 122 us at 32 768 kHz and with very low power consumption 6 2 ELECTRONICS 557 3316 3316 Main System Oscillator Circuit Sub 1 Oscillator Stop Signal 1 8 1 4096 Main Oscil
216. lock and display changing subroutine Subsystem clock main system clock switch subroutine Engage idle mode NOTE You must execute three NOP instructions after IDLE and STOP instructions to avoid flowing of leakage current due to the floating state in the internal bus ELECTRONICS POWER DOWN KS57C3316 P3316 PORT PIN CONFIGURATION FOR POWER DOWN MODE The following method describes how to configure port pins to reduce power consumption during power down modes stop idle Condition 1 If the microcontroller is not configured to an external device 1 2 Connect unused port pins according to the information in Table 8 2 Disable pull up resistors for input pins configured to Vpp or levels in order to check the current input option Reason If the input level of a port pin is set to Vgg when a pull up resistor is enabled it will draw an unnecessarily large current Condition 2 If the microcontroller is configured to an external device and the external device s Vpp source is 8 6 turned off in power down mode Connect unused port pins according to the information in Table 8 2 Disable pull up resistors for input pins configured to or levels in order to check the current input option Reason If the input level of a port pin is set to when a pull up resistor is enabled it will draw an unnecessarily large current Disable the pull up resistors of input pins connected to the external de
217. loped and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Lee Kiheung Si Yongin City Kyungi Do Korea 37 Suwon 449 900 TEL 0331 209 6526 02 760 6526 FAX 0331 209 6547 H P www samsungsemi com Printed in the Republic of Korea Preface The S3C7335 User s Manual is designed specifically for application designers and programmers who are using Samsung s S3C7335 microcontroller for product development The manual is divided into two parts Programmer s Reference Part Il Hardware Descriptions Part Programmer s Reference contains software related information to familiarize programmers with the microcontroller s architecture programming model and instruction set Part has five Chapters Chapter 1 Product Overview Chapter 4 Memory Map Chapter 2 Address Spaces Chapter 5 SAM47 Instruction Set Chapter 3 Addressing Modes Chapter 1 Product Overview is a high level introduction to the S3C7335 ranging from a general product description to detailed information about pin characteristics and circuit types Chapter 2 Address Spaces introduces you to the S3C7335 programming model the program memory ROM and data memory RAM structures and how to address them Chapter 2 also includes information about stack operations CPU registers and the bit sequential carrier BSC register Chapter 3 Addressing Mode
218. lt 0 5 150 Allow interrupts according to IPR priority level El Enable interrupt ELECTRONICS 2 17 ADDRESS SPACES KS57C3316 P3316 EMB FLAG EMB The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12 bit data memory addresses In this way it controls the addressing mode for data memory banks 0 1 or 15 When the EMB flag is 0 the data memory address space is restricted to and addresses 000 07 of memory bank 0 and addresses of memory bank 15 regardless of the SMB register contents When the EMB flag is set to 1 the general purpose areas of bank 0 1 and 15 can be accessed by using the appropriate SMB value 52 PROGRAMMING Using the EMB Flag to Select Memory Banks EMB flag settings for memory bank selection 1 When EMB 0 SMB 1 Non essential instruction since EMB 0 LD A 9H LD 90H A F90H lt A bank 15 is selected LD 34H A lt A bank 015 selected SMB 0 Non essential instruction since EMB 0 LD 90H A F90H A bank 15 is selected LD 34H A 034H lt A bank 0 is selected SMB 15 Non essential instruction since EMB 0 LD 20H A 020H A bank 0 is selected LD 90H A F90H lt A bank 15 is selected SMB 1 Select memory bank 1 LD A 9H LD 90H A 190H A bank 1 is selected LD 34H A 134 lt A bank 1 is selected SMB 0 Select memory bank 0
219. me BMOD BT Input Clock WDCNT Input Clock WDT Interval Time Main Clock Sub Clock frequency frequency x000b fxx 212 x 28 212 28x 29 x 1 63 1 86sec 224 256 sec x010b fxx 29 x 28 29 x 28 x 23 2039 233 ms 28 32 sec x100b fxx 27 x 28 27 x 28 x 23 51 0 58 3 ms 7 8 sec x110b fxx 25 x 28 25 x 28 x 23 12 8 14 6 ms 1 75 2 sec NOTES 1 Assuming that fxx is main system clock 4 5 MHz or subsystem clock 32 768 KHz 2 Ifthe WDMOD changes such as disable and enable you must set WDTCF flag to 41 for starting WDCNT from zero state ELECTRONICS 11 7 TIMERS TIMER COUNTER 59 PROGRAMMING Using the Watchdog Timer RESET MAIN 5 SMB LD LD LD LD BITS JP WDONT input clock is 7 28 ms KS57C3316 P3316 Main routine operation period must be shorter than watchdog timer s period ELECTRONICS 557 3316 3316 TIMERS and TIMER COUNTER 8 BIT TIMER COUNTER TCO OVERVIEW Timer counter TCO is used to count system events by identifying the transition high to low or low to high of incoming square wave signals To indicate that an event has occurred or that a specified time interval has elapsed TCO generates an interrupt request By counting signal transitions and comparing the current counter value with the reference register value TCO can be used to measure specific time intervals TCO has a reloadable counter that consists of two parts a
220. mpleted this bit is set so that an A D conversion result is ready to be read EOC is cleared by ADSTR setting While this flag is set the ADC cannot start a new conversion EOC is 1 bit or 4 bit read only addressable Table 13 3 A D Converter Control Flag Settings Effect of AFLAG Bit Setting Enable A D converter when the ADSTR bit is set to 1 the A D converter starts operating and the ADSTR bit is cleared automatically A D conversion is not completed the start of a new conversion is blocked A D conversion is completed Select fxx 2 clock for conversion Select fxx 4 clock for conversion DIGITAL TO ANALOG CONVERTER DAC BLOCK The 8 bit digital to analog converter DAC generates analog voltage reference values for the comparator The DAC is a 256 step resistor string type digital to analog converter that uses successive approximation logic to convert digital input into the reference analog voltage VDA VDA values are input from the DAC to the comparator where they are compared to the multiplexed external analog source voltage VA Since the DAC has 8 bit resolution it generates the 256 step analog reference voltage as follows 1 Vre Sag 515 1 2 LSB compensation VREF n 0 256 as determined by successive approximation logic CONVERSION TIMING The A D conversion process requires 8 clock to convert each bit Therefore a total of 34 clocks are required to complete an 8 bit
221. n 10 10 io ris ej 10 11 Port 6 Circuit Diagram ecco eed cereo 10 12 Basic Timer Circuit 11 3 GO Circuit I ett e EN ade th eet etn 11 11 TCO Timing Diagrar hg egeo evo Ld de au dug 11 18 Watch Timer Circuit meme eene ener 11 23 EGD Function Diagrari cutie aA eed 12 1 LCD Circuit Dia Gren 12 2 LCD Display Data RAM 12 3 Voltage Dividing Resistor Circuit 12 8 LCD Signal Waveforms Static 12 9 LCD Connection Example in Static 12 10 LCD Signal Waveforms at 1 2 Duty 1 2 12 11 LCD Connection Example at 1 2 Duty 1 2 Bias 12 12 LCD Signal Waveforms at 1 3 Duty 1 2 12 13 LCD Signal Waveforms at 1 3 Duty 1 3 Bias 12 14 LCD Connection Example at 1 3 Duty 1 3 Bias sse 12 15 LCD Signal Waveforms at 1 4 Duty 1 3 Bias 12 16 LCD Connection Example at 1 4 Duty 1 3 Bias
222. n port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 6 Port 6 Circuit Diagram 10 12 ELECTRONICS KS57C3316 P3316 TIMERS and TIMER COUNTER 1 1 TIMERS and TIMER COUNTER OVERVIEW The KS57C3316 microcontroller has three timer modules 8 bit basic timer BT 8 bit timer counter TCO Watch timer WT The 8 bit basic timer BT is the microcontroller s main interval timer It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register The basic timer also functions as watchdog timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a chip reset The 8 bit timer counter TCO is programmable timer that is used primarily for clock frequency modification The watch timer WT module consists of an 8 bit watch timer mode register a clock selector and a frequency divider circuit Watch timer functions include real time and watch time measurement main and subsystem clock interval timing buzzer output generation It also generates a clock signal for the LCD controller ELECTRONICS 11 1 TIMERS and TIMER COUNTER KS57C3316 P3316 BASIC TIMER BT OVERVIEW The 8 bit basic timer BT has five functional components Clock selector logic
223. n 8 bit reference register TREFO into which you write the counter reference value and an 8 bit counter register whose value is automatically incremented by counter logic 8 bit mode register TMODO is used to activate the timer counter and to select the basic clock frequency to be used for timer counter operations To dynamically modify the basic frequency you can load new values into the TMODO register during program execution TCO FUNCTION SUMMARY 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency External event counter Counter various system events based on edge detection of external clock signal at the TCO input pin TCLO To start the event counting operation TMODO 2 is set to 1 and TMODO 6 is cleared to 0 Arbitrary frequency output Output selectable clock frequencies to the TCO output pin TCLOO External signal divider Divides the frequency of an incoming external clock signal according to a modifiable reference value TREFO and outputs the modified frequency to the TCLOO pin Serial I O clock source Output a modifiable clock signal for use as the SCK clock source ELECTRONICS 11 9 TIMERS TIMER COUNTER TCO COMPONENT SUMMARY Mode register TMODO Reference register TREFO Counter register TCNTO Clock selector circuit 8 bit comparator Output latch TCLO Output enable flag TOEO Interrupt request flag
224. nal source and be used for input port When LCON 1 is 1 P6 is open with an external source so the states of P6 is high impedance The reason this mode exists is to enhance LCD quality during a key scanning The effect of the LCON O setting is depends on the setting value of LMOD 3 When is 1 and LMOD 3 is 0 the LCD display is turned off When 0 is 1 and LMOD 3 is 1 the LCD display is turned and the COM and SEG signal outputs operation in normal display mode Table 12 2 LCD Control Register LCON Organization Always logic zero Always logic zero Port 6 input enable Port 6 input disable LCD output low cut off current to dividing resistor When LMOD 3 0 Turn display off When LMOD 3 1 COM and SEG output in display mode Table 12 3 LCON 0 and LMOD 3 Bit Settings LCON 0 LMOD 3 COMO0 COM3 SEGO SEG27 Reuts X Output low turn LCD Output low turn LCD LCD display off display off display off Cut off current to dividing resistors 1 COM output corresponds to SEG output corresponds to LCD display on display mode display mode Mis LCD display off LCD display off LCD display off 12 4 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER LCD MODE REGISTER LMOD The LCD mode control register LMOD is used to control display mode LCD clock segment or port output and display on off LMOD can be manipulated using 8 bit write in
225. ncy LCDCK Frequency 1 2 Duty 1 3 Duty 1 4 Duty fw 29 64 Hz 32 21 fw 2 256 Hz fw 26 512 Hz NOTES fw 32 768 kHz LCD PORT CONTROL REGISTER LPOT The LCD port control register LPOT is used to control using P7 P13 as segment or normal output port LPOT can be manipulated using 4 bit write instructions Following a system reset all LPOT values cleared to 0 Table 12 6 LCD Port Control Register Setting L3 1 Select to use P8 P13 pins as SEG4 SEG27 and pins as normal output port 1 Select to use P9 P13 pins as SEG8 SEG27 and P7 P8 pins as normal output port 1 1 Select to use P10 P13 pins as SEG12 SEG27 and P7 P9 pins as normal output port EBENE KNEES Select to use P11 P13 pins as SEG16 SEG27 and P7 P10 pins as normal output port Select to use P12 P13 pins as SEG20 SEG27 and P7 P11 pins as normal output port Select to use P13 pins as SEG24 SEG27 and P7 P12 pins as normal output port Select to use P7 P13 pins as normal output port 12 6 ELECTRONICS KS57C3316 P3316 LCD CONTROLLER DRIVER LCD DRIVE VOLTAGE The LCD display is turned on only whenever the voltage difference between the common and segment signals is greater than Vi cp The LCD display is turned off whenever the difference between the common and segment signal voltages is less than V The turn on voltage Vi cp or Vi cp is generated only when both signals are the selected signals of the bias Tab
226. ncy effect LD Ac 1H LD EA 2H NOP LD A 3H NOP LD 23H A 23H lt 1H LD HL 10H gt HL lt 10H LD HL 20H NOP LD A 3H lt LD EA 35H NOP LD HL A 10H lt The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes Instruction LD LD LD LD LD LD LD LD 5 62 A im A RRa A DA A Ra Ra im RR imm DA A Operation Description and Guidelines Since the redundancy effect occurs with instructions like LD EA imm if this instruction is used consecutively the second and additional instructions of the same type will be treated like NOPs Load the data memory contents pointed to by 8 bit RRa register pairs HL WX WL to the A register Load direct data memory contents to the A register Load 4 bit register Ra E L H X W Z Y to the A register Load 4 bit immediate data into the Ra register E L X W Y 2 Load 8 bit immediate data into the Ra register EA HL WX YZ There is a redundancy effect if the operation addresses the HL or EA registers Load contents of register A to direct data memory address Load contents of register A to 4 bit Ra register E L H X W Z Y ELECTRONICS KS57C3316 P3316 LD Load LD Concluded Examples Instruction LD LD LD LD LD LD LD EA HL EA DA EA RRb HL A DA
227. ne cycle ELECTRONICS 5 7 SAM47 INSTRUCTION SET KS57C3316 P3316 HIGH LEVEL SUMMARY This Chapter contains a high level summary of the SAM47 instruction set in table format The tables are designed to familiarize you with the range of instructions that are available in each instruction category These tables are a useful quick reference resource when writing application programs If you are reading this user s manual for the first time however you may want to scan this detailed information briefly and then return to it later on The following information is provided for each instruction Instruction name Operand s Brief operation description Number of bytes of the instruction and operand s Number of machine cycles required to execute the instruction The tables in this Chapter are arranged according to the following instruction categories CPU control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions 5 8 ELECTRONICS 557 3316 3316 SAM47 INSTRUCTION SET Table 5 9 CPU Control Instructions High Level Summary Samen doe Reset cay tegens a e mmeCPUMeme 2 Engage CPU stop mode ETE mp m t meme Remo EMB 0 1 Load enable memory bank flag
228. nerates an interrupt request every 0 5 seconds High speed mode is useful for timing events for program debugging sequences Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD 3 If WMOD 3 is 1 the input level at the pin is high if WMOD 3 is the input level at the XT y pin is low 11 22 ELECTRONICS KS57C3316 P3316 om n Ne mand Clock Selector fxt fx 128 ENABLE DISABLE TIMERS and TIMER COUNTER P0 3 LATCH PMO 3 MUX A fw 2 16kHz fw 4 8 2 fw 8 4kHz Selector fw 16 Circuit 2kHz fw2 214 2 Frequency Dividing 32 768 kHz Circuit fw 2 54096 fx Main system clock fxt Sub system clock fw Watch Timer Frequency fxx System clock Figure 11 4 Watch Timer Circuit Diagram ELECTRONICS 11 23 TIMERS TIMER COUNTER KS57C3316 P3316 WATCH TIMER MODE REGISTER WMOD The watch timer mode register WMOD is used to select specific watch timer operations It is 8 bit write only addressable An exception is WMOD bit the XT jy input level control bit which is 1 bit read only addressable A system reset automatically sets WMOD 3 to the current input level of the subsystem clock XT y high if logic one low if logic zero and all other WMOD bits to logic zero In summary WMOD settings control the following watch timer functions Watc
229. nne nnne 6 13 KS57C3316 P3316 MICROCONTROLLER xi Figure Number 7 1 7 2 7 3 7 4 7 5 7 6 8 1 8 2 8 3 8 4 8 5 xii List of Figures Continued Title Page Number Interrupt Execution FlOWCN aM Ra Ee 7 3 Interrupt Control Circuit 7 4 Two Level Interrupt Handling 7 5 Multi Level Interrupt 7 6 Circuit Diagram for INTO and 7 9 puce 7 11 Timing When Idle Mode is Released by 8 3 Timing When Idle Mode is Released by an 8 3 Timing When Stop Mode is Released by RESET 8 4 Timing When Stop Mode is Release by an Interrupt essem 8 4 Timing When CE Low Mode is Release by CE rising edge 8 4 Reset Operation by RESET 9 2 Reset Operation by 9 2 Circuit Diagram dese Eee Re ade RE 10 7 Port 1 Circuit Diagram 10 8 Ports 2 3 Circuit DIagralm oce ione rere oret eto ea er ORE ene dde Net vanes ie P 10 9 Port 4 Circuit Diagram re
230. nstruction even if an overflow occurs 5 81 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec SBS Subtract SBS dst src A HL Subtract indirect data memory from A skip on borrow EA RR Subtract register pair RR from EA skip on borrow RRb EA Subtract EA from register pair RRb skip on borrow Description source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected A skip is executed if a borrow occurs The value of the carry flag is not affected one 4 4 0 1 Ab skp on boron EA RR EA EA RR skip on borrow me usus 7 pEDS p xr Examples 1 The accumulator contains the value register pair HL contains the value and the carry flag is cleared to logic zero RCF 0 SBS EA HL EA lt 0C7H SBS instruction skips on borrow but carry flag value is not affected JPS XXX Skip because a borrow occurred JPS YYY Jump to YYY is executed 2 The accumulator contains the value OAFH register pair HL contains the value OAAH and the carry flag is set to logic one SCF E C e 1 dd EA HL EA lt 1 JPS XXX Jump to XXX JPS was not skipped since no borrow occurred after SBS 5 82 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET SCF set Carry
231. o select the input pin and to start or stop IFC counting operation You stop the counting operation by clearing IFMOD 2 and IFMOD 3 to 0 The IFC retains its previous value until IFMOD register values are specified Setting bits IFMOD 3 and IFMOD 2 starts the frequency counting operation Counting continues as long as the gate is open The 16 bit counter value is automatically cleared to OOOOH after it overflows at FFFFH and continues counting from zero The 16 bit count value IFCNT1 IFCNTO can be read by 8 bit RAM control instructions A reset operation clears the counter to zero When the specified gate open time has elapsed the gate closes in order to complete the counter operation At this time the IFC interrupt request flag IRQIF is automatically set to 1 and an interrupt is generated The IRQIF flag is automatically cleared to 0 when the interrupt is serviced The IFC gate flag IFCFG is set to 1 at the same time the gate is closed Since the IFCFG flag is cleared to O when IFC operation start you can check the IFCFG flag to determine when IFC operation stops that is when the specified gate open time has elapsed The frequency applied to FMIF or AMIF pin is counted while the gate is open The frequency applied to FMIF pin is divided by 2 before counting The relationship between the count value and input frequencies far and is shown below FMIF pin input frequency is N DEC
232. occurs If there is no overflow the ADS instruction is executed normally This skip condition is valid only for ADC A HL instructions however If an overflow occurs following ADS instruction the next instruction is not skipped 7119 e e at acAemsiponoetos EA imm 1 1 EA lt imm skip on overflow 95 a4 d3 a2 at do EJ 6 Po fa 1 1 1 1 skip on overtiow Te 4 1 0 RRb lt RRb EA skip on overflow E s RRb EA Examples 1 The extended accumulator contains the value OC3H register pair HL the value OAAH and the carry flag 0 ADS EA HL EA lt 6DH lt 0 ADS skips on overflow but carry flag value is not affected JPS XXX This instruction is skipped since ADS had an overflow JPS YYY Jump to YYY 5 26 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET ADS And Skip On Overflow ADS Examples Continued 2 If the extended accumulator contains the value OC3H register pair HL the value 12H and the carry flag 0 ADS EA HL EA lt 0C3H 12H OD5H C lt 0 JPS XXX Jump to XXX no skip after ADS If ADC is followed by an ADS A im the ADC skips on overflow to the instruction immediately after the ADS An ADS A im instruction immediately afte
233. ode Operation Notation Fo f as ee ar Polo aca amy Fo 1 so 9 e AND cops e lt AND EA olo RRb EA Example If the extended accumulator contains the value 11000011B and register pair HL the value 55H 01010101 the instruction AND leaves the value 41H 01000001 in the extended accumulator EA 5 28 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET BAND Bit Logical And BAND C src b Operation Operand Operation Summary Logical AND carry flag with memory bit SS C memb L C H DA b Description specified bit of the source is logically ANDed with the carry flag bit value If the Boolean value of the source bit is a logic zero the carry flag is cleared to 0 otherwise the current carry flag setting is left unaltered The bit value of the source operand is not affected oporana Binary Code operation Notation C mema b C amp C AND memab C memb L AND memb 7 2 L 3 2 L 1 0 EXEXEJEXEIES Fes for on a us far ao Second Byte Bit Addresses C 1 1 a2 FFOHFFFH Examples 1 The following instructions set the carry flag if P1 0 port 1 0 is equal to
234. on 2 is set to 1 by hardware and then cleared by hardware when the interrupt has been serviced with the exception of IRQW and IRQ2 3 When IRQx is set to 1 by software an interrupt is generated When two interrupts share the same service routine start address interrupt processing may occur in one of two ways When only one interrupt is enabled the IRQx flag is cleared automatically when the interrupt has been serviced When two interrupts are enabled request flag is not automatically cleared so that the user may have an opportunity to locate the source of the interrupt request In this case the IRQx setting must be manually cleared using a BTSTZ instruction Table 7 8 Interrupt Request Flag Conditions and Priorities Source External Priority Name 2 mo E INTTO Signals for TCNTO and TREFO registers match 5 IRQTO INTCE E When falling edge is detected at CE pin IRQCE INTIF When gate closes 7 IRQIF INT2 E Rising edge detected at INT2 or elsea falling edge is IRQ2 detected at any of the KSO KS3 pins NTW 1 Time interval of 0 5 s or 3 19 ms Row 5 Completion signal for serial transmit and receive or receive 4 IRQS only operation ELECTRONICS 7 13 INTERRUPTS PROGRAMMING Setting the INT Interrupt Priority To simultaneously enable INTB and INT4 interrupts INTB INT4 BTSTZ IRQB JR INT4 e IRET BITR IRQ4 e
235. onc 7 14 Chapter 8 Power Down Reducing Power Consumption for Key Input Interrupt 8 5 KS57C3316 P3316 MICROCONTROLLER xix List of Programming Tips Concluded Description Page Number Chapter 10 Ports Configuring I O Ports to Input or Output mn 10 3 Enabling and Disabling I O Port Pull Up Resistors 10 4 Chapter 11 Timers Using the Basic Timer 11 6 Using the Watchdog 11 8 TCO Signal Output to the TCLOO 11 14 External TCLO Clock Output to the TCLOO 11 15 Restarting TCO Counting eene nnne nnne 11 17 0 Timer Interval cec tere trente Men cele nexu nh pe Ire a Eg RR e ule RR ERR E n ee 11 20 Using the Waten Titer cC 11 25 Chapter 13 A D Converter Configuring A D Converter Input 13 6 Chapter 14 Serial I O Interface Setting Transmit Receive Modes for Serial 14 5 Chapter 16 Intermediate Frequency Counter Counting the Frequency at the FMIF pin 8 ms Gate Time 16 7
236. onfiguration ELECTRONICS DEVELOPMENT TOOLS KS57C3316 P3316 Table 20 1 Power Selection Settings for TB573316A User_Vcc Settings Operating Mode To User The SMDS2 SMDS2 supplies Voc to the target board 573316 Vcc gt evaluation chip and the target Vss system To User Vcc The SMDS2 SMDS2 supplies Off e e s On External Target Voc only to the target board gt System evaluation chip The target Vss gt system must have its own power supply Table 20 2 Pin Selection Settings for TB573316A Operating Mode TB573316A FMIF AMIF VCOAM VCOFM 20 4 ELECTRONICS KS57C3316 P3316 DEVELOPMENT TOOLS Table 20 3 Sub clock Selection Settings for 573316 Sub Clock Setting Operating Mode EVA Chip Set the XTI switch to MDS KS57E3300 when the target board is connected to the A SMDS2 SMDS2 XTIN XT OUT L No connection 100 pin connection SMDS2 SMDS2 Set the switch to XTAL EVA Chip when the target board is used KS57E3300 as a standalone unit and is not connected to the A SMDS2 SMDS2 XTIN XT OUT Target Board IDLE LED This LED is ON when the evaluation chip KS57E3300 is in idle mode STOP LED This LED is ON when the evaluation chip KS57E3300 is in stop mode ELECTRONICS 20 5 DEVELOPMENT TOOLS P4 1 SO P4 3 CLO P5 1 ADC1 P5 3 ADC3 P6 1 KS1 P6 3 KS3 Vsso XIN XT IN RESET VLCO VLC2 COM1
237. ons All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Microcontroller Business has been awarded 15014001 certification BVQ1 Certificate No FM9330 All semiconductor products are deve
238. ook Up Table ae 2 4 Clearing Data Memory Banks 0 and 1 2 7 Selecting the Working Register Areaa pp 2 11 Initializing the Stack 1 2 12 Using the BSC Register to Output 16 Bit 2 15 Setting ISx Flags for Interrupt 2 17 Using the EMB Flag to Select Memory 2 18 Using the ERB Flag to Select Register BankKS 2 19 Using the Carry Flag as a 1 Bit 2 21 Chapter 3 Addressing Modes Initializing the and ERB 0 nn nnne nne nsns nnn nnne 3 3 1 Bit Addressing MOJE doeet cse dete 3 7 SS 3 8 8 Bit Addressing itr beoe ea 3 11 Chapter 5 SAM47 Instruction Set Example of the Instruction Redundancy 5 3 Chapter 6 Oscillator Circuits setting the CPU Clocks oo oe eee ee ee eee ete ee 6 6 Switching Between Main System and Subsystem 6 11 CPU Clock Output to the 6 13 Chapter 7 Interrupts Setting the INT Interrupt Priority Using the 2 as Key Input mme nmn e n EEEE 7 10 Setting the INT Interr pt PrOFIty us cios ate
239. or 16K CALL instruction is 4 cycles The REF instruction is used to rewrite into 1 byte form arbitrary 2 byte or 3 byte instructions or two 1 byte instructions stored in the REF instruction reference area in program memory REF reduces the number of program memory accesses for a program me v e s w w e u vo uv TJP and TCALL are 2 byte pseudo instructions that are used only to specify the reference area 1 When the reference area is specified by the TJP instruction that is memc 7 6 00 PC13 8 lt memc 5 0 PC7 0 lt memc 1 2 When the reference area is specified by the TCALL instruction that is 7 6 01 SP 1 SP 2 EMB ERB SP 3 SP 4 PC7 0 SP 5 SP 6 lt PC13 8 SP lt SP 6 PC13 8 lt memc 5 0 PC7 0 lt memc 1 3 Other case that is memc 7 1 memc memc 1 execution The instructions referenced by REF occupy 2 bytes of memory space for two 1 byte instructions or one 2 byte instruction and must be written as an even number from 0020H to 007FH in ROM In addition the destination address of the and TCALL instructions must be located with the 3FFFH address and TCALL are reference instructions for JP JPS and CALL CALLS If the instruction following REF is subject to the redundancy effect the redundant instruction is skipped If however the REF follows a redundant instruction it is executed On the other hand the binary code of a REF instruc
240. or interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations ORG VENTO VENT1 ORG VENT3 VENT4 ORG VENT6 VENT7 ORG 0000H 1 0 RESET 0 0 INTB 0006H 0 0 INT1 0 0 INTS 000CH 0 0 INTCE 0 0 INTIF 0010H lt 1 ERB lt 0 Jump to RESET address EMB lt 0 ERB lt 0 Jump to INTB address INTO interrupt not used EMB lt 0 ERB lt 0 Jump to INT1 address EMB lt 0 ERB lt 0 Jump to INTS address INTTO interrupt not used EMB lt 0 ERB lt 0 Jump to INTCE address EMB lt 0 ERB lt 0 Jump INTIF address 3 If an INTO interrupt is not used and if its corresponding vector interrupt area is not fully utilized or if it is not written by a ORG instruction as in Example 2 a CPU malfunction will occur ORG VENTO VENT1 VENT3 VENT4 VENT5 VENT6 VENT7 ORG General purpose ROM area 0000H 1 0 RESET 0 0 INTB 0 0 INT1 0 0 INTS 0 0 INTTO 0 0 INTCE 0 0 INTIF 0010H EMB EMB EMB EMB EMB EMB EMB TT TT TTT 1 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 Jump to RESET address 0 Jump to INTB address 0 Jump to INTO address 0 Jump to INT1 address 0 Jump to INTCE address 0 Jump to INTTO address 0 Jump to INTS address In this example when interrupt is generated the corresponding vector area is not INT1 but VENTA INTS This causes an
241. otation Description Setting Area Bank Mapping DA b Direct bit is indicated by the 00HO7FH Banko RAM address DA memory All 1 bit bank selection and specified 000H FFFH 5 0 1 15 addressable bit number b mema b Direct bit is indicated by addressable area mema and bit number b peripherals SMB 15 FBOH FBFH Bank 15 ISO 151 EMB FFOH FFFH ERB IRQx Pn n memb L Indirect lower two bits of X FCOH FFFH Bank 15 register L as indicated by the upper 6 bits of RAM area memb and the upper two bits of register L DA b Indirect bit indicated by the lower four bits of the address 1 000H FFFH SMB 0 1 15 All 1 bit DA memory bank selection addressable and the H register identifier peripherals SMB 15 NOTE x means don t care 3 6 ELECTRONICS KS57C3316 P3316 ADDRESSING MODES 52 PROGRAMMING TIP 1 Bit Addressing Modes 1 Bit Direct Addressing 1 If EMB 0 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 BITS AFLAG 34H 3 lt 1 BITS BFLAG F85H 3 lt 1 BTST CFLAG If FBAH O 1 skip BITS BFLAG Else if 0 0 F85H 3 lt 1 BITS P3 0 FF3H 0 P3 0 lt 1 2 1 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 BITS AFLAG 34H 3 lt 1 BITS BFLAG 85H 3 lt 1 BTST CFLAG IFOBAH O 1 skip BITS BFLAG Else if OBAH 0 0 085 3 lt 1 BITS P3 0 FF3H 0 P3 0 lt 1 1 Bit Indirect Addressing 1
242. p modes are terminated either by a RESET or by an interrupt which is enabled by the corresponding interrupt enable flag IEx Exceptions to this rule is INTO Stop2 mode can be terminated by a RESET only When power down mode is terminated by RESET a normal reset operation is executed Assuming that both the interrupt enable flag and the interrupt request flag are set to 1 power down mode is released immediately upon entering power down mode When an interrupt is used to release power down mode the operation differs depending on the value of the interrupt master enable flag IME Ifthe IME flag 0 program execution starts immediately after the instruction issuing a request to enter power down mode is executed The interrupt request flag remains set to logical one Ifthe IME flag 1 two instructions are executed after the power down mode release and the vectored interrupt is then initiated However when the release signal is caused by INT2 or INTW the operation is identical to the IME 0 condition Assuming that both interrupt enable flag and interrupt request flag are set to 1 the release signal is generated when power down mode is entered ELECTRONICS 8 1 POWER DOWN Table 8 1 Hardware Operation During Power Down Modes Stop2 Mode Idle Mode CE Low Mode 1 Stop1 Mode System is Main clock fx operating with Clock oscillator Main system clock oscillation stops Basic timer Serial I O interfa
243. ponding to input port P5 0 P5 3 may be used either for analog input to the A D converter or as normal input ports Since only one of the four pins can be selected at one time as external source of analog data the three remaining input pins are always available for normal inputs Table 13 2 A D Converter Mode Register Settings o Amon wwona ADI Select input channel AD2 Select input channel AD3 ADC AND PORT CONTROL REGISTER APCON Effect of Bit Settings Set P5 to connect the normal input Other settings Each bit corresponds with P5 0 P5 1 P5 2 and P5 3 respectively If the specific bits are set to logic 1 the corresponding pins are connected to ADC block but disconnected from the normal input and automatically the pull up registers off NOTE All bits are cleared to 0 after a chip reset ELECTRONICS 13 3 A D CONVERTER KS57C3316 P3316 ADC CONTROL REGISTER AFLAG The A D converter control register AFLAG is a 4 bit register that contains the control flags used to start the A D converter and to monitor its operational status A conversion is started by setting ADSTR in the AFLAG register ADSTR is write only and is 1 bit and 4 bit addressable The EOC bit End Of Conversion is a flag that can be read to determine the current status of an A D conversion operation When a conversion is co
244. pp 5 V Ports 1 2 3 4 5 and 6 Vin 0 V Vpg 5 V 100 RESET Mem B e e 17 4 ELECTRONES KS57C3316 P3316 ELECTRICAL DATA Table 17 2 D C Electrical Characteristics Concluded TA 25 C to 85 1 8V to 5 5 V Supply 2 Main operating PLL operating Current PCON 0011B SCMOD 0000B VDD Crystal oscillator C1 C2 22 5 V 10 2 CE Low PCON 0011B SCMOD 0000B CE 0V Crystal oscillator C1 C2 22 pF 5 V 10 3 V 10 2 Main mode PCON 0111B SCMOD 0000B Crystal oscillator C1 C2 22pF 5 V 10 3 V 10 1504 2 Sub operating mode PCON 0011B SCMOD 1001B 20 V Vpp V 10 32 kHz crystal oscillator 2 Sub idle mode PCON 0111B SCMOD 1001B CE 0 V 25 3 V 10 32 kHz crystal oscillator 1006 2 Stop mode CPU fxt 4 SCMOD 1101B CE 0 V Ty 25 5 Vt 10 157 2 Stop mode CPU fx 4 SCMOD 0100B 5 V 410 TA 25 NOTES 1 Supply current does not include current drawn through internal pull up resistors and LCD voltage dividing resistors 2 Data includes the power consumption for sub system clock oscillation ELECTRONES 17 5 ELECTRICAL DATA KS57C3316 P3316 Table 17 3 Main System Clock Oscillator Characteristics 25 C 85 Vp
245. pped 16 4 ELECTRONICS KS57C3316 P3316 INTERMEDIATE FREQUENCY COUNTER Gate Time Errors A gate time error occurs whenever the gate signals are not synchronized to the interval instruction clock That is the IFC does not start counter operation until a rising edge of the gate signal is detected even though the counter start instruction setting bits IFMOD 3 and IFMOD 2 has been executed Therefore there is a maximum 1 ms timing error see Figure 16 4 After you have executed the IFC start instruction you can check the gate state at any time Please note however that the IFC does not actually start its counting operation until stabilization time for the gate control signal has elapsed Instruction Execution IFMOD Setting ims 1 Actual Gate Signal 1 ms Resulting Gate Signal 1 1 1 Gate Time Errors Actual Counting Period Figure 16 4 Gate Timing 1 ms Error Counting Errors The IF counter counts the rising edges of the input signal in order to determine the frequency If the input signal is High level when the gate is open one additional pulse is counted When the gate is close however counting is not affected by the input signal status In other words the counting error is 1 0 ELECTRONICS 16 5 INTERMEDIATE FREQUENCY COUNTER KS57C3316 P3316 IF COUNTER IFC OPERATION IFMOD register bits 2 and 3 are used t
246. r Organization and Addressing ERB SRB Settings Selected Register Bank Always set to bank 0 oe 9 Bmw Paired Working Registers Each of the register banks is subdivided into eight 4 bit registers These registers named Y Z W X H L E and A can either be manipulated individually using 4 bit instructions or together as register pairs for 8 bit data manipulation The names of the 8 bit register pairs in each register bank are EA HL WX YZ and WL Registers A L and Z always become the lower nibble when registers are addressed as 8 bit pairs This makes a total of eight 4 bit registers or four 8 bit double registers in each of the four working register banks Figure 2 5 Register Pair Configuration ELECTRONICS 2 9 ADDRESS SPACES KS57C3316 P3316 Special Purpose Working Registers Register A is used as a 4 bit accumulator and double register EA as an 8 bit accumulator The carry flag can also be used as a 1 bit accumulator 8 bit double registers WX WL and HL are used as data pointers for indirect addressing When the HL register serves as a data pointer the instructions LDI LDD XCHI and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction 1 Bit Accumulator 4 Bit Accumulator 8 Bit Accumul
247. r Overview Register Type Description RAM Addressing Reset Name Address Mode Value BMOD Control Controls the clock frequency mode of 4 bit the basic timer also the oscillation stabilization interval after power down mode release or RESET F85H 4 bit write only BMOD 3 is possible 1 bit write BCNT Counter Counts clock pulses matching the F86H F87H 8 bit read only u BMOD frequency setting note BOE Control Control output of basic timer output 1 bit F92H 1 1 bit read write latch to the BTCO pin WDMOD Controls watchdog timer operation F98H F99H 8 bit write only WDTCF Clear the watchdog timer s counter 1 bi F9AH 3 1 bit write only pw NOTE means that the value is undetermined after a chip reset Clear Signal Clear IRQB BITS Interrupt Instruction CLOCK Request SELECTOR 1 Bit R W CPU Start Signal By Interrupt 1 RESET Clock Input PO 0 latch Stop Clear 5 RESET Instruction Figure 11 1 Basic Timer Circuit Diagram ELECTRONICS 11 3 TIMERS TIMER COUNTER KS57C3316 P3316 BASIC TIMER MODE REGISTER BMOD The basic timer mode register BMOD is a 4 bit write only register Bit 3 the basic timer start control bit is also 1 bit addressable All BMOD values are set to logic zero following a chip reset and interrupt request signal generation is set to the longest interval BT counter operation cannot be stopped BMOD settings have the following effect
248. r by a label or by an actual address in program memory operand 5 Far as as sa at wo 1 label SUB is assigned to the instruction at program memory location OOFFH The instruction JPS SUB at location OEABH will load the program counter with the value OOFFH ELECTRONICS 5 57 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec JR Jump Relative Very Short JR Operation Description 5 58 dst Branch to relative immediate address Branch relative to contents of WX register Branch relative to contents of EA JR causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC The range of the relative address is current PC 15 to current PC 16 The destination address for this jump is specified to the assembler by a label an actual address or by immediate data using a plus sign or a minus sign For immediate addressing the range is from 2 to 16 and the range is from 1 to 15 If a O 1 or any other number that is outside these ranges are used the assembler interprets it as an error For JR WX and JR EA branch relative instructions the valid range for the relative address is 000H OFFH The destination address for these jumps be specified to the assembler by a label that lies anywhere within the current
249. r the ADC A HL does not skip even if overflow occurs This function is useful for decimal adjustment operations 8 9 decimal addition the contents of the address specified by the HL register is RCF 0 LD A 8H lt 8H ADS A 6H A 8H OEH ADC A HL 7 lt 1 ADS A 0AH Skip this instruction because 1 after ADC result JPS XXX 3 4 decimal addition the contents of the address specified by the HL register is RCF 0 LD A 3H lt ADS A 6H A lt 6H 9H ADC A HL A 9H 4H C 0 ADS A 0AH lt OAH 7H The skip function for ADS A im is inhibited after an ADC A QHL instruction even if an overflow occurs JPS XXX ELECTRONICS 5 27 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec AND Logical And AND dst src Operation oporana Operation Summary eyes Logical AND A immediate data to A Logical AND A indirect data memory to A EA RR Logical AND register pair RR to EA RRb EA Logical AND EA to register pair RRb Description source operand is logically ANDed with the destination operand The result is stored in the destination The logical AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both 1 otherwise a bit is stored The contents of the source are unaffected Operand Binary C
250. ration Summary Bytes Cycles Description accumulator value is complemented if the bit value of A is 1 it is changed to 0 and vice versa ACA EZEXEHESKSESENEN Example If the accumulator contains the value 4H 0100B the instruction COM leaves the value OBH 1011B in the accumulator 5 48 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET CPSE Compare and Skip if Equal CPSE dst src Operation Operand Operation Summary Bytes Compare and skip if register equals im HL im Compare and skip if indirect data memory equals im A HL Compare and skip if A equals indirect data memory EA HL Compare and skip if EA equals indirect data memory EA RR Compare and skip if EA equals RR a Description CPSE compares the source operand subtracts it from the destination operand and skips the next instruction if the values are equal Neither operand is affected by the comparison Binary Code Operation Notation 111 1 1 0101 1 SkipitR im 2 rope es oo 1 Skip if A m an 2 pu m 2 Cop pope p eerie 4 79141919171 extended accumulator contains the value and register pair HL contains 56H The second instruction RET in the instruction sequence EN E EN apepre E E EH
251. ress Mode Value TMODO Control Controls TCO enable disable bit 2 9 91 8 bit write only clears and resumes counting TMODO 3 is operation bit 3 selects clock also 1 bit frequency bits 6 4 writeable TCNTO Counter Counts clock pulses matching the F94H F95H 8 bit read only TMODO frequency setting TREFO Reference Stores reference value for the F96H F97H 8 bit write only FFH timer counter 0 interval setting TOEO Flag Controls timer counter 0 output to 1 bit F92H 2 1 bit write only the TCLOO pin Clock Selector Inverted Serial Figure 11 2 TCO Circuit Diagram ELECTRONICS 11 11 TIMERS TIMER COUNTER KS57C3316 P3316 TCO PROGRAMMABLE TIMER COUNTER FUNCTION You can program timer counter 0 to generate interrupt requests at various interval based on the selected system clock frequency Its 8 bit TCO mode register TMODO is used to activate the timer counter and to select the clock frequency The reference register TREFO stores the value for the number of clock pulses to be generated between interrupt requests The counter register TCNTO counts the incoming clock pulses which are compared to the TREFO value as is incremented When there is a match TREFO an interrupt request is generated To program timer to generate interrupt requests at specific intervals choose one of four internal clock frequencies divisions of the system clock fxx and load a counter referenc
252. ress and bit location assignment is FC3H 3 Table 2 4 BSC Register Organization Aes ms mz s BSCO FCOH 5 0 3 5 0 2 BSCO 1 5 0 0 BSC1 BSC1 3 BSC1 2 BSC1 1 BSC1 0 5 2 2 5 2 3 5 2 2 BSC2 1 BSC2 0 BSC3 FC3H BSC3 3 BSC3 2 BSC3 1 BSC3 0 PROGRAMMING Using the BSC Register to Output 16 Bit Data To use the bit sequential carrier BSC register to output 16 bit data 5937H to the P1 0 pin BITS EMB SMB 15 LD EA 37H 5 BSCO lt A BSC1 lt LD EA 59H LD BSC2 EA BSC2 lt 5 lt E SMB 0 LD L 0H AGN LDB C BSCO QL LDB P1 0 C C 5 L JR AGN RET ELECTRONICS 2 15 ADDRESS SPACES KS57C3316 P3316 PROGRAM COUNTER PC A 14 bit program counter PC stores addresses for instruction fetches during program execution Whenever a reset operation or an interrupt occurs bits PC13 through PCO are set to the vector address Usually the PC is incremented by the number of bytes of the instruction being fetched One exception is the 1 byte REF instruction which is used to reference instructions stored in the ROM PROGRAM STATUS WORD PSW The program status word PSW is an 8 bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced PSW values are mapped as follows MSB LSB FBOH 151 150
253. ring power down mode but when normal operating mode resumes its value is undefined The carry flag can be directly manipulated by predefined set of 1 bit read write instructions independent of other bits in the PSW Only the ADC and SBC instructions and the instructions listed in Table 2 7 affect the carry flag Table 2 7 Valid Carry Flag Manipulation Instructions Operation Type Instructions Carry Fiag Manipulation Clear carry flag to 0 reset carry flag LDB C LDB LDB Load contents of the specified bit to carry flag contents of the Load contents of the specified bit to carry flag e bit to carry flag Boolean manipulation BAND C operand AND the specified bit with contents of carry flag and save the result to the carry flag BOR C operand OR the specified bit with contents of carry flag and save the result to the carry flag BXOR C operand 1 XOR the specified bit with contents of carry flag and save the result to the carry flag Interrupt routine INTn 2 Save carry flag to stack with other PSW bits Return from interrupt IRET Restore carry flag from stack with other PSW bits NOTES 1 The operand has three bit addressing formats mema a memb L and OH DA b 2 INTn refers to the specific interrupt being executed and is not an instruction 2 20 ELECTRONICS KS57C3316 P3316 ADDRESS SPACES PROGRAMMING Using the Carry Flag as a 1 B
254. rocontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM57 The SASM57 is an relocatable assembler for Samsung s KS57 series microcontrollers SASM57 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM57 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX
255. rrupt 1 INT1 Mode Register 4 22 IMOD2 External Interrupt 2 INT2 Mode Register 4 23 IPR 4 24 LCON LCD Outp t Control 4 25 LMOD LCD Mode Control 4 26 LPOT LCD Port GontroliRieglster ier re ea en 4 27 PCON Power GontroliBeglstet UE 4 28 KS57C3316 P3316 MICROCONTROLLER xxi List of Register Descriptions Register Full Register Name Page Identifier Number PLLREF PLL Reference Frequency Selection 4 29 PLLREG PEL Status 4 30 PLMOD PEL Mode 4 31 PMGO Port I O Mode Control Register Port 0 4 32 1 Port I O Mode Control Register Port 2 and 4 33 PMG2 Port I O Mode Control Register Port 4 and 5 4 34 Port I O Mode Control Register Port 6 4 35 PNE Port Open drain Enable 4 36 POFR Power On Flag Register 4 37 PSW PE SO 4 38 PUMOD Pull up Resistor Mode 4 39 SCMOD System Clock Mode Control Register ppp 4 40 SMOD Serial
256. s Restart the basic timer Control the frequency of clock signal input to the basic timer Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt By loading different values into the BMOD register you can dynamically modify the basic timer clock frequency during program execution Four BT frequencies ranging from 212 to fxx 25 are selectable Since BMOD s reset value is logic zero the default clock frequency setting is fxx 21 The most significant bit of the BMOD register BMOD 3 is used to restart the basic timer When BMOD 3 is set to logic one enabled by a 1 bit write instruction the contents of the BT counter register BCNT and the BT interrupt request flag IRQB are both cleared to logic zero and timer operation is restarted The combination of bit settings in the remaining three registers BMOD 2 and BMOD 1 determines the clock input frequency and oscillation stabilization interval Table 11 2 Basic Timer Mode Register BMOD Organization Restart basic timer clear IRQB BCNT and BMOD 3 to 0 Always zero a NOTES 1 Assuming that fxx is a selected system clock 4 5 MHz 2 Oscillation stabilization time is the time required to stabilize clock signal oscillation after a chip reset or stop mode are released 3 The standard stabilization time for main clock oscillation following a RESET signal is 29 1 ms at 4 5 MHz
257. s describes types of addressing supported by the SAM47 instruction set direct indirect and bit manipulation and the addressing modes which are supported 1 bit 4 bit and 8 bit Numerous programming examples make the information practical and usable Chapter 4 Memory contains a detailed map of the addressable peripheral hardware registers in the memory mapped area of the RAM bank 15 Chapter 4 also contains detailed descriptions in standard format of the most commonly used hardware registers These easy to read register descriptions can be used as a quick reference source when writing programs Chapter 5 Instruction Set first introduces the basic features and conventions of the SAM47 instruction set Then two summary tables orient you to the individual instructions One is a high level summary of the most important information about each instruction the other is designed to give expert programmers a summary of binary code and instruction notation information The final part of Chapter 5 contains detailed descriptions of each instruction in a standard format Each instruction description includes one or more practical examples A basic familiarity with the information in Part will make it easier for you to understand the hardware descriptions in Part Il If you are unfamiliar with the SAM47 product family and are reading this user s manual for the first time we recommend that you read Chapters 1 3 carefully and just scan
258. s retained If a Reset Occurs During Normal Operation Undefined ELECTRONICS KS57C3316 P3316 Preliminary Spec RESET Table 9 1 Hardware Register Values After a System Reset Continued Hardware Component If a Reset Occurs During If a Reset Occurs During or Subcomponent Power Down Mode Normal Operation Serial I O Interface SIO interface buffer SBUF Undefined IF Counter a 7 9 A D convert data register ADATA A D port control register APCON Table 9 1 Hardware Register Values After a System Reset Concluded Hardware Component If a Reset Occurs During If a Reset Occurs After or Subcomponent Operation Mode Power On PLL mode register PLMOD Undefined PLL data register PLLDO PLLD3 Undefined PLL reference freq Register Undefined Power on flag register POFR Value retained NOTES 1 The value of ULFG is undefined current state of CE pin and IFCFG 0 2 The value of ULFG is undefined CEFG current state of CE pin and IFCFG is undefined ELECTRONICS 9 5 RESET KS57C3316 P3316 Preliminary Spec NOTES 9 6 ELECTRONICS KS57C3316 P3316 PORTS PORTS OVERVIEW The KS57C3316 has 14 ports There are total of 4 input pins 28 output pins 16 configurable I O pins and 8 n channel open drain pins for a maximum number of 56 pins Pin addresses for all ports except ports 7 13 are mapped in bank 15 of the RAM
259. set otherwise the carry flag is cleared If ADC A HL is followed by an ADS A im instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This condition is valid only for ADC A HL instructions If an overflow occurs following an ADS A im instruction the next instruction will not be skipped now 1 1 194191414142 uw ES Examples 1 The extended accumulator contains the value register pair HL the value OAAH and the carry flag is set to 1 SCF 3 E us ADC EA HL EA lt 1H lt 1 JPS XXX Jump to XXX no skip after ADC 2 If the extended accumulator contains the value register pair HL the value and the carry flag is cleared to 0 RCF 0 ADC EA HL EA OH 6EH lt 1 JPS XXX Jump to XXX no skip after ADC 5 24 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET ADC With Carry ADC Examples Continued 3 If ADC A HL is followed by an ADS A im the ADC skips on carry to the instruction immediately after the ADS An ADS instruction immediately after the ADC does not skip even if an overflow occurs This function is useful for decimal adjustment operations 8 9 decimal addition the contents of the address spec
260. set to 0 5 seconds or 3 91 milliseconds NOTE Since INTW is a quasi interrupt the IRQW flag must be cleared by software ELECTRONICS 4 19 MEMORY KS57C3316 P3316 IFMOD IF counter Mode Register F9BH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 and 2 Interrupt Sampling Clock Selection Bits IFC is disabled FMIF AMIF are pulled down and FMIF AMIF s feed back resistor are off Enable IFC operation AMIF pin is selected FMIF is pulled down and AMIF s feed back resistor is off 1 Enable IFC operation FMIF pin is selected AMIF is pulled down and AMIF s feed back resistor is off Enable IFC operation Both AMIF and FMIF are selected 1 and 0 Gate Time Selection Bits Gate opens in 1 millisecond intervals Gate opens in 4 millisecond intervals 1 0 Gaeopensnamisecondnevas __ O Gate remains open continuously 4 20 ELECTRONICS KS57C3316 P3316 MEMORY MAP IMODO Externa Interrupt 0 INTO Mode Register FB4H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 4 4 1 0 ELECTRONICS Interrupt Sampling Clock Selection Bit Select CPU clock as sampling clock Select sampling clock frequency of the selected system clock fxx 64 Bit 2 Always logic zero External Interrupt Mode Control Bits lolo Interrupt requests are triggered by a rising signal edge Interrupt requests are triggered by
261. sistors can be configured by program 0 P1 FFFH 4 bit input port 1 bit and 4 bit read test are possible 4 bit pull up resistors can be configured by program P2 0 P2 3 FF2H FFeH Same as PO P3 0 P3 3 Port 2 3 and port 4 5 can be paired to support 8 bit P4 0 P4 3 data transfer P5 0 P5 3 P6 0 P6 3 P7 0 P7 3 FF7H FFDH 1 bit or 4 bit output port P8 0 P8 3 N Channel open drain output P9 0 P9 3 LCD segment output port P10 0 P10 3 P11 0 P11 3 P12 0 P12 3 P13 0 P13 3 1 bit test Input or test data at each pin Input or test data at output latch 1 bit input 4 bit input 8 bit input LD P2 3 Output latch contents undefined Output pin status is modified 4 bit output LD 2 Transfer accumulator data to the Transfer accumulator data to the 8 bit output LD P4 EA output latch output pin 10 2 ELECTRONICS 557 3316 3316 PORTS PORT MODE FLAGS FLAGS Port mode flags PM are used to configure ports to input or output mode by setting or clearing the corresponding buffer For convenient program reference PM flags are organized into four groups PMGO0 PMG1 PMG2 and PMG3 as shown in Table 10 3 They are addressable by 8 bit write instructions only When PM is 0 the port is set to input mode when it is 1 the port is enabled for output A system reset clears all port mode flags to logical zero automatically configuring the corresponding ports to input mode Table 1
262. ss of the current EMB flag setting Here are a few guidelines to keep in mind regarding data memory addressing When you address peripheral hardware locations in bank 15 the mnemonic for the memory mapped hardware component can be used as the operand in place of the actual address location Always use even numbered RAM address as the operand in 8 bit direct and indirect addressing With direct addressing use the RAM address as the instruction operand with indirect addressing the instruction specifies a register which contains the operand s address ELECTRONICS 3 1 ADDRESSING MODES KS57C3316 P3316 Addressing DA HL WX _ EMB 1 EveB o 1 x x Working t Registers Bank 0 General Registers and Stack Bank 1 General SMB 1 Registers Display SMB 1 Registers Bank 15 Peripheral eee SMB 15 SMB 15 Registers NOTES 1 X means don t care 2 Blank columns indicate RAM areas that are not addressable given the addressing method and enable memory bank EMB flag setting shown in the column headers Figure 3 1 RAM Address Structure 3 2 ELECTRONICS KS57C3316 P3316 ADDRESSING MODES EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are system reset set automatically by the values of the reset vector address and the interrupt vector address When a system reset is generated internally bit 7 of program memory address 0000H is written to the EMB
263. ssable by 4 bit write instructions A system reset clears all IMOD values to logic zero selecting rising edges as the trigger for incoming interrupt requests Table 7 5 IMODO 1 and 2 Register Organization moves effector mOD0 Setings 2221 ising cage etecton _ o 1 Both rising and falling edge detection IRQO flag cannot be set to 1 IMOD1 0 Effect of IMOD1 Settings Rising edge detection Falling edge detection IMODO IMOD1 7 8 ELECTRONICS KS57C3316 P3316 INTERRUPTS EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS Continued When a sampling clock rate of fxx 64 is used for INTO an interrupt request flag must be cleared before 16 machine cycles have elapsed Since the INTO pin has a clock driven noise filtering circuit built into it please take the following precautions when you use it trigger an interrupt the input signal width at INTO must be at least two times wider than the pulse width of the clock selected by IMODO You can use INTO to release IDLE mode when fxx 64 is selected as a sampling clock Noise Filter Edge Detection Clock Selector CPU Clock fxx 64 Edge Detection Figure 7 5 Circuit Diagram for INTO and INT1 Pins When modifying the IMODO and IMOD registers it is possible to accidentally set an interrupt request flag To avoid unwanted interrupts take these precautions when writing
264. sters and Stack Area 224 x 4 Bits General purpose and LCD Data Registers 256 x 4 Bits Unused Area Memory mapped I O Address Registers 128 x 4 Bits Figure 2 3 Data Memory RAM Map ELECTRONICS 2 5 ADDRESS SPACES KS57C3316 P3316 Memory Banks 0 and 15 Bank 0 OOOH OFFH The lowest 32 nibbles of bank 0 000H 01FH are used as working registers the next 224 nibbles 020 can be used both as stack area and as general purpose data memory Use the stack area for implementing subroutine calls and returns and for interrupt processing Bank 1 100H 1FFH The lowest 228 nibbles of bank 1 100H 1E3H are for general purpose use use the remaining 28 nibbles 1E4H 1FFH as display registers of as general purpose memory Bank 15 The microcontroller uses bank 15 for memory mapped peripheral I O Fixed RAM locations for each peripheral hardware address are mapped into this area Data Memory Addressing Modes The enable memory bank EMB flag controls the addressing mode for data memory banks 0 1 or 15 When the EMB flag is logic zero the addressable area is restricted to specific locations depending on whether direct or indirect addressing is used With direct addressing you can access locations 000 07 of bank 0 and bank 15 With indirect addressing only bank 0 QOOH OFFH can be accessed When the EMB flag is set to logic one all three data memory banks can be accessed according to t
265. struction can be used in three ways Using the 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch address that is stored in the look up table Calling subroutines at any location by referencing a call address that is stored in the look up table If necessary a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence In addition the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions Two byte instructions can be referenced by using a REF instruction An exception is XCH A DA If the MSB value of the first 1 byte instruction in the reference area is 0 the instruction cannot be referenced by a REF instruction Therefore if you use REF to reference two 1 byte instructions stored in the reference area specific combinations must be used for the first and second 1 byte instruction These combinations are described in Table5 1 Table 5 1 Valid 1 Byte Instruction Combinations for REF Look Ups First 1 Byte Instruction Second 1 Byte Instruction Opernd instruction Operand _ R Instuc on LD RRb R LD A RRq R RRb R LD HL A R RRb R NOTE Ifthe MSB value of the first one byte binary code in instruction is 0 the instruction cannot be referenced by a REF instruction 5 2 ELECTRONICS KS57C33
266. structions bit 3 LMOD 3 can be also written by 1 bit instructions The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw the watch timer must be enabled when the LCD display is turned on A chip reset clears the LMOD register values to logic zero The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source The LCD mode register LMOD controls the output mode of the 8 pins used for normal outputs P8 0 P9 3 Bits LMOD 7 6 define the segment output and normal output configuration Table 12 4 LCD Mode Register LMOD Organization LCD Voltage Dividing Register Control Bit Internal voltage dividing resistor 1 External voltage dividing resistor Internal voltage dividing resistors are off LMOD 6 Always logic zero LMOD 5 LMOD 4 LCD Clock LCDCK Frequency 5 fw 29 64 Hz 25 128 Hz fwr 25 512 Hz o ww em 3 eoms 1 2 duty 1 2 bias 9 1 1 3 duty 1 2 bias 3 0 3 8 NOTES 1 means don t care 2 fw 32 768 kHz watch timer clock 3 Biascan be configured as external connections ELECTRONICS 12 5 LCD CONTROLLER DRIVER KS57C3316 P3316 Table 12 5 LCD Clock Signal LCDCK and Frame Freque
267. t EP dE 1 11 1 14 Pin Circuit Type 0 1 11 1 15 Pi Circuit EypezEE4 ete deret ER MD ER RR Ue 1 11 1 16 Pin Circuit Type H 28 P7 P13 1 11 2 1 ROM Address 2 2 2 2 Vector Address EPI eee lia eee 2 2 2 3 Data Memory 2 5 2 4 Working Register 2 8 2 5 Register Pair Configuration Se ee 2 9 2 6 1 Bit 4 Bit and 8 Bit 2 10 2 7 Push Type Stack Operations 2 13 2 8 Stack 2 14 3 1 FAM Address Str ct te ce cx coder e ae D e ee aet 3 2 3 2 SMB and SRB Values in the SB 3 5 4 1 Register Description Formal recreare ne neediness cients 4 7 6 1 Clock Circuit Diagrami 6 3 6 2 Crystal Ceramic 6 4 6 3 External Gscoillator 6 4 6 4 Crystal Geramic Oscillator ceti ct rie Ree eret e RE 6 4 6 5 d tiene 6 4 6 6 CLO Output Pin Circuit Diagram emen n
268. t Addressing 1 4 4 4 4 COM Signal Enable Disable Bit Enable COM signal Disable COM signal LCD Port Selection Bits 0 0 0 Select LCD P7 PISISEGO SEG27 _ o 1 Select LCD P8 P18 P7 as output port E Select LCD P9 P13 P7 P8 as output port Select LCD P10 P13 P7 P8 P9 as output port Select LCD P11 P13 P7 P8 P9 P10 as output port Select LCD P12 P13 P7 P8 P9 P10 P11 as output port 111 0 Select LCD P13 P7 P8 P9 P10 P11 P12 as output port All output port P7 P13 1 4 27 MEMORY 557 3316 3316 PCON Power Control Register FB3H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 4 4 4 4 3 2 CPU Operating Mode Control Bits 1 0 NOTE fx is the main system clock is the subsystem clock 4 28 ELECTRONICS KS57C3316 P3316 MEMORY MAP PLLREF Reference Frequency Selection Register FC9H Bit 3 2 1 0 RESET Value note note note note Read Write W W W W Bit Addressing 4 4 4 4 3 0 Reference Frequency Selection Bits EN ES SSCS 1 po o o sese NOTE If a system reset occurs during operation mode the current value contained is retained If a system reset occurs after power on the value is undefined
269. t lie between the Vpp and the Vss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type ADC and port control register APCON control register AFLAG mode register ADMOD Four multiplexed analog data input pins ADCO ADC3 8 bit A D conversion data output register ADATA To operate the A D converter P5 must be configured to ADC mode as using APCON register and one of the 4 channel is selected by writing the appropriate value to the A D mode register ADMOD and the conversion start bit AFLAG 3 must be set to 1 Conversion speed is determined by the system clock fx or fxt When the A D operation is complete the EOC flag must be tested in order to verify that the conversion was successful When the EOC value is 1 the converted digital values stored in the data register ADATA can be read ELECTRONICS 13 1 A D CONVERTER KS57C3316 P3316 Data Bus Successive Approximation Logic Multiplexer Resistor String Digital to Analog Converter Figure 13 1 A D Converter Circuit Diagram Table 13 1 A D Converter Component Overview ADC Function Digital to analog converter DAC Uses successive approximation logic to convert digital input into the reference analog voltage VDA These Vp values are input to the comparator and then compared to the multiplexed external analog source
270. t priory Fo o Process at hianost pony recess INTO incrupt at highest pony Process erupt at highest 1 4 24 ELECTRONICS KS57C3316 P3316 MEMORY MAP LCON tcp Output Control Register Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W Bit Addressing 1 4 1 4 3 LCD Output Control Test Bit EN Always logic zero 2 Not used Always logic zero 41 Port 6 Control Bit Port 6 input enable 0 LCD Output Control Bit LCD output is low and current to dividing registers is cut off 1 Port 6 input disable If LMOD 3 0 LCD output Low and display is turned off If LMOD 3 1 output COM and SEG signals in display mode ELECTRONICS 4 25 MEMORY KS57C3316 P3316 LMOD LCD Mode Control Register F8DH F8CH Bit 3 2 1 0 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W Bit Addressing 8 8 8 1 8 8 8 8 7 LCD Voltage Dividing Resistor Selection Bit Internal dividing resistor 1 External dividing resistor 6 Not used Always logic zero 5 and 4 LCD Clock LCDCK Frequency Selection Bits 32 768 kHz watch timer clock fw 29 64 fw 28 128 Hz fw 2 256 Hz fw 26 512 Hz Static NOTE x mean don t care 4 26 ELECTRONICS 2 0 ELECTRONICS KS57C3316 P3316 MEMORY MAP LCD Port Control Register F8AH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bi
271. t to output mode SCF Ce LDB P1 0 C 1 0 lt 1 5 The P4 address is and L 5H 0101B The address memb 7 2 is 111101 and L 3 2 is 01B The resulting address 11110101B specifies P5 The bit value L 1 0 is specified as 01B bit 1 Therefore P4 L P5 1 SCF Ce 1 LD L 9H LDB P4 L C P4 L specifies P5 1 P5 1 lt 1 6 In this example 2H and FLAG 20H 3 and the address 20H is specified Since the bit value is 3 H FLAG 20H 3 FLAG EQU 20H 3 RCF 0 LD H 2H LDB H FLAG C FLAG 20H 3 ELECTRONICS 5 65 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec LDC Load Code Byte LDC dst src EA WX Load code byte from WX to EA 1 Load code byte from EA to EA Description X This instruction is used to load byte from program memory into an extended accumulator address of the byte fetched is the five highest bit values in the program counter and the contents of an 8 bit working register either WX or EA The contents of the source are unaffected mew a olo o 0 eacrcwe wom EA lt PC13 8 EA EA Examples 1 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator LD EA 00H CALL DISPLAY JPS ORG 0500H DB 66H DB 77H DB DB DISPLAY LDC EA lt address 05
272. tems are operational the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one stopping all controller operations with the exception of some peripheral hardware The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 87 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec VENT Load EMB ERB and Vector Address VENTn dst Operation operara Operation Summary Byes EMB 0 1 Load enable memory bank flag EMB and the enable 2 2 ERB 0 1 register bank flag ERB and program counter to vector ADDR address then branch to the corresponding location Description VENT instruction loads the contents of the enable memory bank flag EMB and enable register bank flag ERB into the respective vector addresses It then points the interrupt service routine to the corresponding branching locations The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged Then when an interrupt is generated the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed After the return from interrupt
273. the detailed information in Chapters 4 and 5 very briefly Later you can refer back to Chapters 4 and 5 as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C7335 P3316 microcontroller Also included Part Il are electrical mechanical OTP and development tools data Part II has 13 Chapters Chapter 6 Oscillator Circuits Chapter 14 Serial I O Interface Chapter 7 Interrupts Chapter 15 PLL Frequency Synthesizer Chapter 8 Power Down Chapter 16 Intermediate Frequency Counter Chapter 9 RESET Chapter 17 Electrical Data Chapter 10 Ports Chapter 18 Mechanical Data Chapter 11 Timers and Timer Counter Chapter 19 KS57P3316 OTP Chapter 12 LCD Controller Driver Chapter 20 Development Tools Chapter 13 A D Converter Two order forms are included at the back of this manual to facilitate customer order for S3C7335 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative KS57C3316 P3316 MICROCONTROLLER iii Table of Contents Part Programmer s Reference Chapter 1 Product Overview QM CEU 1 1 Mc em C 1 1 1 2 the abies 1 4 PINVASSIQMIMOMIS un 1 5 eee 1 6 Pin Gircuit DIAagralr
274. thin 2K bytes 11 bits The CALLS instruction unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction Then it pushes the result onto the stack decreasing the stack pointer six times The higher bits of the PC with the exception of the lower 11 bits are cleared The subroutine call must therefore be located within the 2K bytes 0000H 07FFH of program memory SP 1 SP 2 lt EMB ERB SP 3 SP 4 lt PC7 0 SP 5 SP 6 lt PC13 8 SP SP 6 PC13 11 0 10 0 lt 11 The stack pointer value is 00H and the label PLAY is assigned to program memory location 0345H Executing the instruction CALLS PLAY at location 0123H will generate the following values SP OFFH OFEH EMB ERB OFDH 2H 5H OFBH OH OFAH 1H PC 0345H Data is written to stack locations OFFH OFAH as follows OFAH OFBH OFCH OFDH ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET CCF Complement Carry Flag CCF Description carry flag is complemented if 1 it is changed to 0 and vice versa a EE Example If the carry flag is logic zero the instruction CCF changes the value to logic one ELECTRONICS 5 47 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec COM Complement Accumulator COM A Operation Operand Ope
275. tion Register PLLREF pp Phase Detector Charge Pump and Unlock Using the PLL Frequency KS57C3316 P3316 MICROCONTROLLER Table of Contents Concluded Chapter 16 Intermediate Frequency Counter SN ies esa panes 16 1 IFC Mode Register FMOD as 16 2 16 2 Gate 16 3 IF Counter IFG Operation Lione comen Leere ete tre tetur eon Pena 16 6 Input Le eee ee eo etie eee tene eene epa ge v Lime eve Ope ete esee p eO Ee 16 7 Fe puer eV unc xS 16 8 Chapter 17 Electrical Data e H 17 1 Timing WaVveforms idco doeet ter deckt etd edet p acea pur UIDES eu Ee Aarts 17 12 Chapter 18 Mechanical Data eu ATE 18 1 Chapter 19 KS57P3316 OTP Overview 19 1 Operating Mode Characteristics tees 19 3 NEEDED Enn 19 13 Chapter 20 Development Tools eh m 20 1 SHINE eet nee Ee od rd Ub e cete do ee eee eve ete 20 1 SAMA ASSEMDIG Me EE 20 1 ul ydp EE 20 1 HEX2ROM eire sates ona xou kae rd dee ERSTE rr
276. tion is 1 byte The upper 4 bits become the higher address bits of the referenced instruction and the lower 4 bits of the referenced instruction x 1 2 becomes the lower address producing a total of 8 bits or 1 byte see Example 3 below ELECTRONICS 5 75 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec REF Reference Instruction REF Continued Examples 1 Instructions can be executed efficiently using REF as shown in the following example ORG 0020H AAA LD HL 00H BBB LD EA 0FFH CCC TCALL SUB1 DDD TJP SUB2 ORG 0080H REF AAA LD HL 00H REF BBB LD EA 0FFH REF CCC CALL SUB1 REF DDD JP SUB2 2 The following example shows how the REF instruction is executed in relation to LD instructions that have a redundancy effect ORG 0020H AAA LD EA 40H ORG 0100H LD EA 30H REF BBB Not skipped REF BBB LD EA 50H Skipped SRB 2 5 76 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET REF Reference Instruction REF Concluded Examples 3 In this example the binary code of REF 1 at locations 20H 21H is 20H for at locations 22H 23H it is 21H and for REF at 24H 25H the binary code is 22H Opcode Symbol Instruction ORG 0020H 83 00 A1 LD HL 00H 83 03 A2 LD HL 03H 83 05 A3 LD HL 05H 83 10 A4 LD HL 10H 83 26 5 LD HL 26H 83 08 A6 LD HL 08H 83 OF A7 LD HL 0FH 83 FO A8 LD HL 0FOH 83 67 9 LD HL 67H 41 0B A10 TCALL SUB1 01 0D A11 SUB2
277. tion of rising 79 P1 3 falling edges Sto 50 53 Quasrinterrupt input with falling edge detection 8 11 P6 0 Input D 7 P6 3 ADCO ADC input ports 4 7 P5 0 Input F 10 ADC3 P5 3 SEGO LCD segment signal output 28 31 P7 0 Output H 28 SEG3 P7 3 SEG4 LCD segment signal output 32 55 8 13 Output H 28 SEG27 1 8 ELECTRONES 557 3316 3316 Preliminary Spec PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD Pul Up P Channel Resistor In In N Channel Schmitt Trigger Figure 1 3 Pin Circuit TypeA Figure 1 6 Pin Circuit Type B RESET Up P Channel Out Feedback Enable Down lt N Channel Pull Down Enable Figure 1 4 Pin Circuit Type 2 Figure 1 7 Pin Circuit Type B 4 no Pull Up Enable Figure 1 5 Pin Circuit Type A 4 P1 Figure 1 8 Pin Circuit Type 5 ELECTRONES 1 9 PRODUCT OVERVIEW 3C7335 P7335 Pul up 2 Enable P Channel Data Out Circuit Output Disable P Channel Output N Channel Disable Schmitt Trigger Figure 1 9 Pin Circuit Type C Figure 1 11 Pin Circuit Type D 4 Pull up Pull up Enable Enable MD P Channel Data 2 Data Circuit P Channel Circuit Output Type C Output Type C Disable Disable Schmitt Trigger Figure 1 10 Pin Circuit Type D 2 Figure 1 12 Pin Circuit Type D 7 P6 1 10 EL
278. to A increment register L contents and skip on carry A HL Load indirect data memory contents to A decrement register L contents and skip on carry EA WX Load code byte from WX to EA EA EA Load code byte from EA to EA 2 42 245 Rotate right through carry bit RR o Push register pair onto stack Push SMB and SRB values onto stack 1 1 1 1 1 1 1 1 1 1 2 1 Pop to register pair from stack Pop SMB and SRB values from stack 2 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET Table 5 12 Logic Instructions High Level Summary AND 2 Logical AND A immediate data to A 2 Logical AND A indirect data memory to A Logical AND register pair RR to EA Logical AND EA to register pair RRb Logical OR immediate data to A Logical OR indirect data memory contents to A Logical OR double register to EA Logical OR EA to double register Exclusive OR immediate data to A Exclusive OR indirect data memory to A Exclusive OR register pair RR to EA Exclusive OR register pair RRb to EA Table 5 13 Arithmetic Instructions High Level Summary ADC Add indirect data memory to A with carry 1 1 Add register pair RR to EA with carry 2 2 Add EA to register pair RRb with carry 2 2 A im Add 4 bit immediate data to A and skip on carry EA Add 8 bit immediate data to EA and skip on carry A HL Add indirect data memory to A and skip on carry EA RR Add register pair RR contents to EA and skip on c
279. top mode Idle Mode Normal Mode A dM Oscillation Clock 59 Oscillation Resumes Signal Figure 8 3 Timing When Stop Mode is Released by RESET Oscillation Stabilization Stop BMOD Setting Instruction Mode Y INT ACK IME 1 Release signal Normal Mode Stop mode Idle Mode Normal Mode Oscillation Clock Stops Oscillation Resumes gal Signal Figure 8 4 Timing When Stop Mode is Release by an Interrupt CE Pin PLL Status PLL Enable PLL Disable PLL Enable cm 4 INTCE interrupt A system reset is generated is generated Figure 8 5 Timing When CE Low Mode is Release by CE rising edge 8 4 ELECTRONICS 557 3316 3316 POWER DOWN er Programming Tip Reducing Power Consumption for Key Input Interrupt Processing The following code shows real time clock and interrupt processing for key inputs to reduce power consumption In this example the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on KEYCLK CALL MA2SUB SMB 15 LD EA 00H LD P4 EA LD LD IMOD2 A SMB 0 BITR IRQW BITR IRQ2 BITS IEW BITS 2 CLKS1 CALL WATDIS BTSTZ IRQ2 JR CIDLE CALL SUB2MA CIDLE IDLE NOP NOP NOP JPS CLKS1 Main system clock gt subsystem clock switch subroutine All key strobe outputs to low level Select KS0 KS3 interrupt Execute c
280. tputs are the SEGO 27 or the port 7 13 data Table 10 6 LPOT Setting for Port 7 13 Output Control LPOT 2 LPOT 1 0 Effect of LPOT Settings Select to use P7 P13 pins as SEGO SEG27 1 Select to use P8 P13 pins as SEG4 SEG27 and P7 pin as normal output port Select to use P9 P13 pins as SEG8 SEG27 and P7 P8 pins as normal output port 1 Select to use P10 P13 pins as SEG12 SEG27 and P7 P9 pins as normal output port Select to use P11 P13 pins as SEG16 SEG27 and P7 P10 pins as normal output port 1 Select to use P12 P13 pins as SEG20 SEG27 and P7 P11 pins as normal output port Select to use P13 pin as SEG24 SEG27 and P7 P12 pins as normal output port Select to use P7 P13 pins as normal output port Locations that are unused for LCD or port I O can be used as normal data memory After a system reset the values connected in the port 7 13 data are left undetermined NONU 10 6 ELECTRONICS KS57C3316 P3316 PORTS PORT 0 CIRCUIT DIAGRAM VDD BTCO ae BUZ u P0 0 BTCO PO 1 TCLOO 22 P0 3 BUZ di ec du When port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD TCLO Figure 10 1 Port 0 Circuit Diagram ELECTRONICS 10 7 PORTS PORT 1 CIRCUIT DIAGRAM 10 8 P1 0 INTO P1 1 INT1 P1 2 INT2 P1 3 IN
281. ts of PC and PSW in the stack area set PC contents to corresponding vector address Are both interrupt sources of shared vector address used IRQx flag value remains 1 Reset corresponding IRQx flag Jump to interrupt start address Jump to interrupt start address Verify interrupt source and clear IRQx with a BTSTZ instruction Figure 7 1 Interrupt Execution Flowchart ELECTRONICS 7 3 INTERRUPTS KS57C3316 P3316 gt INTT0 INTCE mese INTIF INTW _ gt SELECTOR so xsa0 Power Down Mode Release Signal GN 151 ISO Interrupt Control Unit Vector Interrupt Noise Filtering Circuit Generator Edge Detection Circuit NOTE INTO can release Idle mode olny when fxx 64 is selected as a sampling clock Figure 7 2 Interrupt Control Circuit Diagram 7 4 ELECTRONICS 557 3316 3316 INTERRUPTS MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways as two level interrupts where either all interrupt requests or only those of highest priority are serviced or as multi level interrupts when the interrupt service routine for a lower priority request is accepted during the execution of a higher priority routine Two Level Interrupt Handling Two level interrupt handling is the standard method for processing multiple interrupts When the 161 and 160 bits of the PSW FBOH 3 and FB
282. ummary SCF RCF CCF EMB ERB ROM 2 x n 7 6 PC13 12 ROM 2 x n up 11 8 lt ROM 2 x n 3 0 PC7 0 lt ROM 2 x n 1 7 0 n 0 1 2 3 4 5 6 7 5 14 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET Table 5 16 Program Control Instructions Binary Code Summary ba HL im 1 4 1 Skip if HL im peo pepe o a 1 1 01 11 11 1 0 1 SkpitA R xe o o i i o Bera EA HL ip i HL E HL 1 EA RR Skip if EA RR ea ew ee ADR14 1 1 0 1 1 14 s v sis ws ssi oo s 1 PCt3 0 13 12 Far as as a Pcrs 0 annie PC13 ADR 15 0 16 QWX 1 1 0 11 11 1 0 1 PCt3 8 lt 8 ull 5 E PC7 0 lt WX 13 8 lt PC13 8 ADR14 1 1 1 1 1 1 SP 1 5 2 lt EMB ERB SP 3 SP 4 lt PC7 0 1 13 12 11 a10 SP 5 SP 6 lt PC13 8 SP SP 6 Fer as ss se ws lt CALLS ADR11 1 1 1 1 10 SP 1 SP 2 EMB ERB SP 3 SP 4 lt PC7 0 SP 5 SP 6 lt PC13 8 a7 a5 a4 a3 a2 al SP lt SP 6 PC13 11 0 PC10 0 lt ADR11 First Byte Condition First Byte 8
283. utine i cie teo eto Het to er e todd M RE Eo RE SUP eed ER gs 5 78 RRC Rotate Accumulator Right Through 5 79 SBC Subtract With CANY rne 5 80 SBC Subtract uer li m 5 81 SBS Silio 5 82 SCF Set Carry Flag iiec kk aC 5 83 SMB ELE pacco 5 84 SRB Select Register Bank 2 CA AAEE EENE a ER 5 85 SRET Return From Subroutine and 5 86 STOP Stop Operation ms 5 87 Load EMB ERB and Vector Address pp 5 88 Load ERB Vector 0 5 89 XCH Exchange or EA with Nibble or 5 90 XCHD Exchange and Decrement 5 91 KS57C3316 P3316 MICROCONTROLLER XXV Exchange and 5 92 XOR Logical Exclusive OR 5 93 KS57C3316 P3316 MICROCONTROLLER 53 7335 7335 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The 53 7335 single chip CMOS microcontroller has been designed for high performance using Samsung s newest 4 bit CPU core SAM47 Samsung Arran
284. ution at location 123H During a return from interrupt data is popped from the stack to the program counter The data in stack locations OFFH OFAH is organized as follows PC11 PC8 ELECTRONICS 5 55 SAM47 INSTRUCTION SET KS57C3316 P3316 Preliminary Spec JP Jump JP dst Operation Operation Summary Bytes Cycles ADR14 Jump to direct address 14 bits Description causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand The destination can be anywhere in the 16K bytes program memory address space operand Binary Code GpesionNouion repe C CES o as ate ars as ae as a6 The label SYSCON is assigned to the instruction at program location 07 The instruction JP SYSCON at location 0123H will load the program counter with the value 07FFH 5 56 ELECTRONICS KS57C3316 P3316 SAM47 INSTRUCTION SET JPS Jump Short JPS dst Operation Operation Summary Bytes Cycles ADR12 Jump direct a 4K byte page 12 bits Description JPS causes an unconditional branch to the indicated address within the 4K bytes block of the program memory Bits 0 11 of the program counter are replaced with the directly specified address The destination address for this jump is specified to the assemble
285. ve pull up resistors BITS EMB SMB 15 LD EA 40H LD PUMOD EA Enable P6 to have pull up resistors 10 4 ELECTRONICS 557 3316 3316 PORTS ADC AND PORT CONTROL REGISTER e _ SaPStecomec _ Other settings Each bit corresponds with P5 0 P5 1 P5 2 and P5 3 respectively If the specific bits are set to logic 1 the corresponding pins are disconnected from the normal port and automatically the pull up registers N CHANNEL OPEN DRAIN MODE REGISTER PNE The N channel open drain mode register PNE is used to configure port 7 to 13 to N channel open drain modes or push pull modes When a bit in the PNE register is set to 1 the corresponding output pin is configured to N channel open drain when set to 0 the output pin is configured to push pull mode The PNE register consists of an 8 bit register as shown below PNE can be addressed by 8 bit write instructions only Table 10 5 N Channel Open Drain Mode Register PNE Setting PNE FD6H PNE10 9 PNE8 7 7 PNE13 PNE12 PNE11 ELECTRONICS 10 5 PORTS KS57C3316 P3316 PIN ADDRESSING FOR OUTPUT PORT 7 13 The buffer addresses for the port 7 13 pins are located in both bank1 and bank15 To output the port 7 13 in bank15 use the setting SMB 15 Otherwise to output SEGO 27 in bank1 use the setting EMB 1 and SMB 1 The LCD port control register LPOT is used to control whether the pin ou
286. vi ce by making the necessary modifications to the PUMOD register Configure the output pins that are connected to the external device to low level Reason When the external device s Vpp source is turned off and if the microcontroller s output pins set to high level 0 7 V is supplied to the Vpp of the external device through its input pin This causes the device to operate at the level Vpp 0 7 V In this case total current consumption would not be reduced Determine the correct output pin state necessary to block current pass in according with the external transistors PNP NPN ELECTRONICS KS57C3316 P3316 POWER DOWN RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption please configure unused pins according to the guidelines described in Table 8 2 Table 8 2 Unused Pin Connections for Reducing Power Consumption Pin Share Pin Names Recommended Connection 0 Input mode Connect to Vpp PO 1 TCLO Output mode Do not connect PO 2 TCL P0 3 BUZ P1 0 INTO Connect to P1 1 INT1 P1 2 INT2 P1 3 INT4 P2 0 P2 3 Input mode Connect to Vpp P3 0 P3 3 Output mode Do not connect P4 0 SCK P4 1 SO P4 2 SI P4 3 CLO P5 0 ADC0 P5 3 ADC3 P6 0 KS0 P6 3 KS3 Vioo Vice Connect to Vas BIAS If all of the Vi co Vi co pins are unused connect BIAS to Vas and set LCON 0 and LMOD 7 to 0 Vm ELECTRONICS 8 7 POWER DOWN 8 8 NOTES KS5
287. xamples of the ADC A HL and A HL skip feature Table 5 3 Skip Conditions for ADC and SBC Instructions Sample If the result of Then the execution Reason Instruction Sequences instruction 1 is sequence is ADC A HL Overflow ADS cannot skip ADS A im instruction 3 even if it XXX No overflow has a skip function XXX SBC A HL Borrow ADS cannot skip ADS A im instruction 3 even if it XXX No borrow has a skip function XXX ELECTRONICS 5 5 SAM47 INSTRUCTION SET SYMBOLS AND CONVENTIONS Table 5 4 Data Type Symbols Symbol Data Type a a mas Tinie Table 5 5 Register Identifiers Full Register Name D 4 bit accumulator 4 bit working registers 8 bit extended accumulator 8 bit memory pointer 8 bit working registers Select register bank n Select memory bank Carry flag Program status word Port n m th bit of port n Interrupt priority register Enable memory bank flag Enable register bank flag KS57C3316 P3316 Table 5 6 Instruction Operand Notation Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4 bit immediate data number 8 bit immediate data number Immediate data prefix 000H 1FFFH immediate address bit address A E L H X W Z Y L H X W Z EA HL WX YZ HL WX WL HL WX YZ WX WL FFOH FFFH

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