CPU Read/Write Access 4 LANCE Interrupt Status 4 Read
Contents
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4. 36 IN INEC S MECHANICAL TOLERANCE XX 77 09192 XXX 905 TI al FRONT TO BACK RESTSTRATION i MINIMUIM CONDUCTOR MINIMUM AIRGAP 008 x z MATERIAL TO Bt GLASS FR 4 UL APPROVED 2 1 07 COPPER PLATE TO 2 07 QUTER LAYERS PER 515 MIL P 47226 MIN 99 5 COLOR NATURAL 1 METAL CLAD LAMINATES SHALL IN ACCORDANCE WITH MIL P 13949 gt e ERE PEN 258 zi o o o o o o o 2 BOARG THICKNESS TO BF 62 005 GLASS TO GLASS r8 89 Doa EE aa seat V oop e00g09 oacavac og o o s INSPECTION CRITERIA PER IPC A 6380 9009090 9 0006020 00000000 o 0290000 000000000t i i o 4 5 o g 9 oneddoooe 0000000 09 343 ee VENDOR SHALL SELECT PROCESSIES EQUIPMENT AND MATERIALS i DER MEN MIL 9 o 849 T i ccu E pode d M du SS x UL re 1 n o o o o o i SOLDERMASK BOIH SIDES OF BOORG USING ARTHORK PROVIDED MEUS Ad oeooocuo b 9090508 0 gt S 9 o 0r000000000 SRS Sis SOLDERMASK SHALL PC401 ORY FILM OR PROBIMER 00000555 90000004 9009000 0 9009000000 2000330000 o
5. 42 1 AU Tie MUS C aes i VCC NCC nx TRANS e XMIT DAL IS RCLK 2 15 29 gt Jz 1 RENA RENA TRANS ee CLSN CLSN j 49 gt 32 6 OAL 15 TX TX 5 iz REC DALI2 TELK TELK oT gt v2 12 TENA TENA RCVR l 7 DALII x gt 32 2 DALIO evTE 3 DAL xz m gt 32 9 pees DALI cou AM7992 DALB HOLD 5 pr INTR n DALT Ave TEST HEC MORE I GND GND2 GND CU RA CUM E ICONE o 2 DALS 5 _ e B DAL 4 EA o B XMT 9 DAL amp ES MIT M DAES TENA D Ca ASA DALI TAS M HOLD DALO 4 INTR PA 53 e 4 vp Be 0 RPI eset Fi z em 53K READ 22 Lt oo 5vDC J ee peer sen p aras aor 21 i GND 55 Apo ADR os gt 2 6 AS 14 1 DA OAS 5 CIS 2 C17 Clg ER 2 a duoa T220 7i20 74 7 To Loss ce R4 READY w A L ee READY uo T A ERRE gt GNO GNDZ 22 C25 C24 25 2K 24 R5 on 4 1 330 E 16 Oe 00243 ool L smer OF 5 1 A A BUS 1 6 17 2
6. u CSEL Z XCVOE X OMAEN DBUS 15 evo x N BUS 1 2 B dl 745288 741 5175 e DIR oE DO gt 02 A 4 10 2 pi AZ ae ui s2 gt A e 2D d fa 3 51 gt w ale 2 s aras o 253 J Ax com 49 gt A 5 CLK CLR ee SU ee 5 De eL DI 7 L gt eH STOMA 14F 245 DIR OE 14 C A A ec She ony xD12 2 ie 012 78 gt 5 D 3 77 gt epee xDI4 5 18 015 3 i 7 oS is DO A e JAFZ245 a M gt J1 17 1415395 CE Y gt 2s v Le A ord n 2 CLR A CLR A YF A Y A v E 9 Y E 3 al t I O DEC B XIQENK 2 18 PALIGLSA EE XZ0MCK R2 o 4 41 MET BACK o 5 lt a 3 3K 5 3 N res O gt 4 8 i xRSTK B n 1 59 o XCVEN X EZ 58 RST 375 s cS Bi H Ilo RW 74774 A s il fe MOOS ME nos TS 3 36 ___xuos C u xX RIW a o u RQ tE READL oe
7. Signal GND 6 GND 11 Not Used COL Not Used 12 RCVR Not Used 1 13 PLUS12 COL Not Used TRANS Not Used Software Interface The EEB occupies the standard 256Kbyte or 128K word block assigned to each expansion slot Ethernet Expansion Board Theory of Operation Expansion Slot The expansion cards in the UNIX PC are each assigned 256K bytes of address space Since all addressing is done on word boundaries 128K words of address space is available Expansion bus address bits XAl XA17 define this space Each expansion slot contains hardwired identification bits XIDO XID2 to define seven unique slot addresses Bits XA18 XA20 are compared against the slot identification bits to validate the address Also address bit XA21 is always zero similarly expansion addresses XA22 and XA23 are always ones Therefore once the EEB is plugged into its slot the predetermined XA18 XA23 bits generate the offset address while Rita AYAT x 7 2 ha hanana aAa m T ZA A L C gt AA 1 lt CLISG 52 2 lt 7 AVAL lt lt LY LC devices The offset addresses used in the UNIX PC are listed below Table 2 Expansion Slot Offset Addresses Slot Number Offset Address h 0C00000 0C40000 0C80000 0CCOOO00 0000000 0040000 0080000 ODCO000 0 l 2 3 4 5 6 7 On Board Addressing Only
8. 60 0 8 i oo SILKSCREEN COMPONENT SIDE USING ARTWORK PROVICED 90 P o E ooooodbooon 9 2 9990200200 9 9302909002 848 i COLOR WHITE CONDUCT LYE Y yee o 200000005 o 200020029 9 2 9 oe T i o 0090000 o 0000700 0 0006000005 00000002000 P S 099009005 32 UNLESS OTHERWISE SPECIFIED ALL HOLES ARE PLATED THROUGH oo 9600000 oochoooooo 9 9 9099998 9 1 99 o 0020 0 o 2000990 9 9000000099 0 0000202900 22 02096099000 9 0000622 97 o 939 ALL HOLES TO BE FINISHED SIZE AFTER PLATING 959 108 o k Sog Ping o9 q oo 233 go ooo 0000900 o 4 9000009000 0900909000 9006000 og 00 k s D 9 ALL HOLES SHALL BF LOCATED WITHIN 803 Of THEIR sr ee UU Ra VEO RIP q s Sepe EIL TRUE POSITION WITH RESPECT IO THE PAD CENTER ooo ooog 0900000000005 5 o o acexootien 28 OE nr SEL 0000000000 00 d 3000000000
9. 600 OR 1400 ZZD PEESO j DAL 15 00 VALID DATA ira S NN Figure 7 CPU LANCE Write Timing Diagram X13 X14 X15 X16 X10 X11 X19 XO X1 X11 e JTUUPLIULILTLUILIUGILILT NN T END 9 jo paeog uotsuedxy TCLK EXPRQ DAL BUS hee 75 MAX el LAS DAS READY XDBUS DATA IN 120 MIN X1 X2 X3 X4 X5 X6 X7 X8 X9 2 3 Mimics CENE 4 lt 29 2 37 6 MAX XABUS VALID ADDRESS 35 MIN 75 MIN 90 MAX soMIN gt Figure 8 LANCE DMA Read Cycle uoTje1edg jo paeog uoTsuedxy ce T6 Ti T2 T3 T4 re T3 TCLK 0 1 2 3 13 5 MAX EXPRQ gt 445 29 2 MAX gt XABUS ee a CLERUM DNE VALID ADDRESS ae BUS DATA OUT ADDRESS DATA OUT y ADDRESS TE Een 75 MAX rie MIN TE 8 Ie 120 MIN MN LAS 120 MIN je 8 MIN ASM s win 10 MIN 8 MIN sa s je 80MIN gt I gt Dr E er z 15 MAX a 15 MAX READY I 75 250 l
10. T wunout the puar written tg 777 Convergent Technologies ASSE MB Y DRAW ING bold _ 2 2 ETHERNET P C B E melee S an D 68 00243 00 aS nie EROR APPLICATION 00 NOT SCALE DRAWING ai ee ee ter Jameer OL ar 8 7 5 REVISIONS ru RELEASE TO CONTROL A 3 2 y 1 68 22243 02 i
11. control register to provide selection of interrupt line LAN interface type and a DMA disable for diagnostic purposes This register is reset to zeros by hardware or software reset Bit Signal Description DO DMAEN 1 DMA Enabled I Il DMA Disabled D1 RESERVED 1 Other Selected 0 Ethernet Selected D2 INTSEL 1 Use Interrupt 01 0 Use Interrupt 05 D3 SPARE Ethernet Expansion Board Theory of Operation A read of this address also resets the board interrupt Base Address R W Description 000004 RW Control Register LANCE Register Address and Data Ports The LANCE chip in slave mode contains two ports The register address port is a 2 bit port that selects which of the four 16 bit control and status ports are accessed through the register data port Base Address R W Description 000002 RW LANCE Register Address Port 000000 RW LANCE Register Data Port Software Operation Once the LANCE chip has been started all data and status transfers are done through DMA No I O access is permitted to the board except the software reset and interrupt reset functions 10 Ethernet Expansion Board Theory of Operation Troubleshooting The following procedu are a simplified description for troubleshooting a UNIX PC Ethernet Expansion Board that is not functioning properly or has failed a diagnostics test The following items are required to perform these procedures roa lt Kernel debugger program An Oscillosco
12. 32 bytes of the board address block A write to any of these addresses produces a board reset CPU Read Write Access The status and command section provides CPU read write access to the LANCE chip address and data ports However due to the long access time of the chip LANCE reads do not provide data to the CPU in a single cycle Data is latched on board during the LANCE read it is then read by the CPU in a separate latch read cycle LANCE Interrupt Status This section contains a 16 bit register and an 8 bit counter The LANCE interrupt status is written automatically to memory at the location of the combined 24 bit address by the on board DMA Read Write Control Register A 4 bit read write control register is also contained in this section This register allows the CPU to disable DMA for diagnostic purposes select Ethernet and make selections between INT 01 and INT 05 The register contains one unused bit State Machine Control Circuitry The state machine control section consists of five PALs providing control and timing signals for all other sections A 20R8 PAL determines when a board cycle needs to be initiated and what type of cycle it should be The 20R8 arbitrates between LANCE DMA requests HOLD LANCE interrupts and CPU I O requests and generates the LANCE HLDA and expansion bus requests as well as on board I O cycles Ethernet Expansion Board Theory of Operation Each of 11 non idle cycles has its own timing an
13. 6 X17 X18 X19 XO XA 21 01 VALID ADDRESS 2 XR W 77 0 1 2 3 4 5 6 CYCLE END CYCLE I O READ CYCLE XCVDIR 7 2 XCVOE K Figure 4 CPU non LANCE Read Timing Diagram jo uotsuedxy 6T XO x1 X2 X3 X4 x5 X6 X7 X8 x9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 XO XIOEN 77 ZZ XA 21 01 DK VALID ADDRESS 77 0 1 2 3 4 5 6 CYCLE END CYCLE WRITE CYCLE XCVDR WIV E pm TZ u tot s PORC E TCR XCVOE IOCYC B _ Figure 5 CPU non LANCE Write Timing Diagram jo paeog uotsuedxy 3ouuioua3d oz x13 X14 X15 X16 X17 X18 X19 X X1 X X5 X6 X18 X19 X NN XPCLK NN NN XIOEN 22 GZ NN uon MN CPU LANCE READ NN eaten LOUTLE READ DAS READY 600 OR 1400 VALID DATA DAL 15 00 n n O V JV hJq WN Figure 6 CPU LANCE Read Timing Diagram jo paeog uoTsuedxy TZ X2 X3 X4 x5 X6 X7 X8 X9 0 1 2 3 Ls CYCLE NN CPU LANCE WRITE XCVOE EN XD 15 00 VALID DATA DATA NN NN LINLE LINOE LCS READ D DAS NN NN READY
14. Address R Not Used O3FFC7 R Ethernet Address O3FFC6 R Not Used O3FFC5 R Ethernet Address 4 R Not Used R Ethernet Address O3FFC2 R Not Used R LSB Ethernet Address O3FFCO R Not Used Software Reset A write to any of the four board ID addresses causes the board to be reset and put into an inactive state Base Address R W through W Description Software Reset Software Reset Ethernet Expansion Board Theory of Operation LANCE Data Latch This read only 16 bit latch is required to accommodate the slow LANCE register access time to the expansion board timing requirements through a two step process Reading the on chip LANCE registers does not produce valid data in time for the active I O cycle but the data is stored in the LANCE data latch Subsequently a read of the latch will return the desired data to the CPU Base Address R W Description 000006 R LANCE Data Latch Status Ring Address This write only 16 bit register is used to supply bits A9 to A21 of the status ring address Bits Al to A8 are supplied by an on board counter which is cleared on reset Together they supply the addressing for the on board DMA to place LANCE status in memory automatically A write to this address clears any pending interrupts Base Address R W Description 000006 W otatus Ring Address Control Register The board contains a read write 4 bit
15. Contents Ethernet Expansion Board Ethernet Interface Interface I O Description status and Command Circuitry CPU Read Write Access LANCE Interrupt Status Read Write Control Register State Machine Control Circuitry LANCE Interface Ethernet Interface Software Interface Expansion Slot On Board Addressing Pid gt Contents interface Registers and Command Descriptions ID Register Base Address O3FFFF Software Reset LANCE Data Latch otatus Ring Address Control Register LANCE Register Address and Data Ports Software Operation Troubleshooting I O Cycle Register Read Write Cycle Board ID Read Only Cycle CPU LANCE Read Write Cycle DMA Cycle DMA Read Write Single DMA Read Write Burst Interrupt Cycle 0 0 00 00 10 10 11 11 13 14 14 14 15 17 17 Contents Figures 1 Expansion Board Block Diagram 2 2 Ethernet State Diagram 12 3 Expansion Board Cycle Diagram 16 4 CPU non LANCE Read Timing Diagram 18 5 CPU non LANCE Write Timing Diagram 19 6 CPU LANCE Read Timing Diagram 20 7 CPU LANCE Write Timing Diagram 21 8 LANCE DMA Read Cycle 22 9 LANCE DMA Write Cycle 23 Tables 1 Ethernet 15 Pin D Connector 6 2 Expansion Slot Offset Addresses 7 3 State Assignments 13 Ethernet Expansion Board Theory of Operation This overview summarizes the major functions performed by the UNIX PC Ethernet Expansion Board hardware The topics covered h
16. D END END END END END IDLE IDLE IDLE IDLE IDLE ST j IDLE IDLE IDLE DMAWR 1011 END IDLE sa s 7 THT CO m 5 2 Rt lt a 14 341 LaL cilii 12 Ethernet Expansion Board Theory of Operation Table 3 State Assignments 3121110 0 0 IDLE o 1 x 0 o 1 0 STLRD 10 1 1 STLWR 0 1 0 0 CPUREGRD Le d posed did oO 3 1 0 CPULRD Onde SEC i ae ae E CPULWR 1 0 0 LDMARD 1 o 0 1 LDMAWR 1 O 1 1 STDMAWR 2 1 IORDCYC x 1 1 0 1 IOWRCYC 0 1 RQCYC 1 1 1 Register Read Write Cycle A failure of this cycle is a result of a malfunctioning PAL or wrong PAL equation a cycle status being misread to the state machine or a clock failure The following components should be checked for the listed conditions O 4B PAL16L8A located on schematic page 4 is either malfunctioning or the wrong equation is being read 4C PAL20R8A located on schematic page 5 is either malfunctioning or the wrong equation is being read Also use the logic analyzer to check pins 19 22 for the correct CYCO CYC3 sequence refer to the cycle diagram Figure 3 4C 4F PAL20R8A PAL16R8A PAL16R6A and PAL16R8A located on schematic sheet 5 are not receiving clock signals on pin 1 13 Ethernet Expansion Board Theory of Operation Board ID Read Only Cycle The follo
17. E interrupt and a CPU interrupt is generated at the same time Ethernet Expansion Board Theory of Operation The 20R8 PAL encodes the cycle type in 4 bits These 4 bits are fed to three additional registered PALS These signals combine with a 3 bit counter for timing within each cycle and with several handshake signals from the LANCE allowing these three PALS to generate all LANCE related timing and control signals In addition an I O cycle signal is generated for on board non LANCE cycles This signal goes to the fifth PAL This PAL is a nonregistered PAL that generates timing and control for on board I O that is based on I O cycle and address decodes LANCE Inter face The LANCE interface consists of a 16 bit multiplexed address and data bus with associated handshake signals The hardware provides three sets of 16 bit latches for address read data and write data This section also includes a buffer for the upper 5 bits of address and a 4 bit data buffer These buffers provide for the status write to clear the LANCE interrupt Ethernet Inter face The Ethernet interface is handled by the AMD chip set The LANCE chip sends transmit data to the 7992 and gets receive data and collision detection from the 7992 The 7992 provides the interface to the off board transceiver through a standard 15 pin D connector interface Tabie i iists the pin out assignments for this connector Table 1 Ethernet 15 Pin D Connector Signal Signal Pin
18. Miss UP sade Mo O SBS 90 se 999997229 299999999 9 9999999999 2009207 999009 38d o Sedo venies uum ROS nene m es o 38 792 zt Preorov00a 3 P a d boooQo 9 P 85 13995 H 2 Ed 33 NC v DERI S CN 96 a 660066 EX an 2 09929299729 ac 920209 F 9 9992299099 9 9 9 9990 ad 98 29 a Tas 35 555055058 8 Um 380 a006 556 90 ey 5 88 38 MC o8 qi POMMES Lis oodd do y peser 9900 60 Jl WM 904 95 8 99 on 000000009909009900 E ssooossee b e 99 ICT L E PM n Hee o E Tg AE Om e i L e y pues 98 Pen eg edt uL 9 a 9 a 10 zz e a COMPONENT SIDE VIEW 64 7 PART OF 5 2PL ZPL tae oe 7 OF 69 m e ae Um E WASHER BETWEEN PLATE AND LATCH 4 2 AS SHOWN NUT 15 NOT REQUIRED 968 MAX e AN Q YO 2PL SWAGE THIS SIDE 3 5 _ INCHES E ow ZU AGE UNLESS OTHERWISE SPECIFIED This drawing contains Informatlan which meer memes roe itera Convergent Technologies lt m la
19. OL amp STATUS BUFFER TRANSMIT 5V 12V DC DC CONVERTER T GND Figure 1 Expansion Board Block Diagram Aaoeup pieog uotTsuedxy Ethernet Expansion Board Theory of Operation Once the LANCE chip is initialized all data transfers including buffer chaining are handled by the chip Timing and control are maintained by the on board state machine LANCE status is transferred to memory by a separate state machine DMA controller on each LANCE interrupt This status is placed in a 256 word ring in memory allowing the software a 256 packet interrupt latency Because of maximum throughput the CPU is able to find all data and status in memory and never needs to talk directly to the board The board is also not required to wait for CPU response or to share board resources with the CPU accesses LANCE operation consists of two distinct modes transmit and receive In the transmit mode the LANCE chip directly accesses data in memory Data is conditioned by adding a preamble sync pattern and appending a 32 bit cycie redundancy check CRC This packet is sent from the LANCE to the AM7992A Serial Interface Adapter SIA The SIA then transmits this packet to the Ethernet system AM7995 transceiver In the receive mode packets are sent by the SIA to the LANCE Ethernet Interface The Ethernet system to which the EEB is connected consists of an external AM7995 transceiver
20. S Ant IN INCHES TOLERANCES AA PROJECTION D sSHSIONS MATERIAL APPLICATION 00 NOT SCALE DRAWING D 08 00243 SCHEMATIC E THERNE Rey Q8 CO2AZ ins AGE 5 3 1 a WA TCLK STATAOROE Lal D BUS 15 WW LOUTOE EH LOUTLE ASM DAL BUS 2 5 c BY BS JAE TAY LO 5 e c 18 c CLRADREN 5 STATWROE 5 LINLE An ex LE alu 36 BB i TAF 244 REV A lt lt lt x lt 4 lt lt SIACK 4 LA BUS 16 21 D O8 OO245 OOC 7415144 CLK2D 4 XA BUS 1 21 ai K RST Tuv 5 7 6 5 T 4 3 2 DU 1 5N 74 STACK ES CLK20 LO Lee ME S zum 3 CSELKZ D 5N 5 48 2 2 BUS ec azs NCC 25ns DELAY 8 a22 LINE ae Ana AM799 m 1 azo o 4H N RE x See CAS C
21. a small number of addresses are decoded for on board functions These addresses are mot fully decoded in hardware Undefined addresses should not be used they may affect on board functions Reads and writes are always full words even if only 8 bit values are significant Interface Registers and Command Descriptions The following paragraphs list the registers used in Ethernet interface operations and the command descriptions that select the I O functions Ethernet Expansion Board Theory of Operation ID Register Base Address When the UNIX PC is first powered up the UNIX kernel reads the ID register into memory The ID register is a set of 8 bit registers located at odd byte addresses in the upper 32 words of the board address block The upper four words contain the required board identification numbers The lowest six words contain the board specific Ethernet station address The appropriate driver must determine where the hardware is located The getslot system call see System V User anu drivers 7 locates the offset slot The base address is then added to the offset address to access the appropriate registers Base Address R W Description O3FFFF R MSB of ID two s complement O3FFFE R Not Used O3FFFD R LSB of ID less than two s complement R Not Used O3FFFB R MSB of ID R through O3FFCD Not Used O3FFCC R MSB Ethernet Address O3FFCA R Not Used O3FFC9 R Ethernet
22. d control requirements see timing diagrams for more detail These cycles consist of five CPU initiated operations which are CPU non LANCE Read CPU non LANCE Write CPU LANCE Read LANCE Write CPU Data Latch Read These are all individual cycles that c cur only when the Wea A Aii Cou state machine is in its idle state The state machine is always returned to the idle state Three additional cycles are initiated by LANCE DMA requests These are request cycle LANCE DMA read cycle LANCE DMA write cycle The request cycle precedes a single LANCE DMA cycle or burst of cycles This cycle insures UNIX PC LANCE synchronization The LANCE DMA read or write cycies follow the request cycie The state machine goes directly from the request cycle to the read or write without going through idle As long as the LANCE DMA request stays active each DMA cycle leads directly to the next again without idle LANCE DMA requests are either single cycle for buffer management fetches or bursts of eight cycles for data transfers The three final cycle types are also linked together with no intervening idle states When the LANCE asserts its interrupt the state machine executes a status LANCE read cycle reading the LANCE interrupt status into the on board data latch A status DMA cycle is executed to place the status in the status ring in memory Finally a status LANCE write is executed to clear the LANC
23. ere include Imterface I O description Status and command circuitry State machine control circuitry LANCE interface Ethernet interface Software interface Ethernet Expansion Board The Ethernet Expansion Board EEB when plugged into an AT amp T UNIX PC provides an interface to an Ethernet communications network operating at a transfer rate of 10MB sec The EEB is based on the AMD 7990 and 7992 chip set which performs the following functions AM7990 Local Area Network Controller for Ethernet LANCE performs memory management packet handling error reporting and interface functions 7992 Serial Interface Adapter SIA performs Manchester encoding and decoding of the serial bit stream with phase lock loop clock recovery The Expansion Board as shown in the Figure 1 block diagram is a circuit board containing the I O and DMA interface to the LANCE chip a state machine with a read write control register a separate DMA controller for LANCE status and a board ID Ethernet address ROM XA BUS INTERFACE CONTROL XR W BUFFER XRST EXPRQ EXPBG XR W 08 INT D BUS BUFFER BUFFER HLDA RDY DAS LAG BUFFER RECEIVE AMD7992 COLL AMD7990 SERIAL XMIT LANCE INTERFACE ADAPTOR REC SYSTEM CONTROLLER STATUS RING ADDRESS AND DATA INT HOLD RDY DAS LAS DAL BUS LINES CONTR
24. pe Voltmeter VOM Logic Analyzer O O OO The following reference books will also be useful Ethernet Board Installation and Diagnostics Guide Advanced Micro Devices Local Area Network Controller AM7990 LANCE Technical Manual Before beginning with the troubleshooting procedures check the schematic against the ICs on the board so they can be identified readily Also during operation of the expansion board the voltage at J2 13 should be 12 13 Vdc Troubleshooting is concerned with the EEB s three basic cycles and how they relate to components that have failed Figure 2 is a diagram of the Ethernet states and Table 3 lists the state assignment functions during specific cycles These cycles are cycle DMA cycle Imterrupt cycle I Q Cycle The I O cycle consists of three individual cycles as follows Register Read Write cycle Board ID Read Only cycle CPU LANCE Read Write cycle When the EEB has been reset either by a hardware or software reset it is at the idle state By using the Kernel debugger program the I O cycle can be examined for the three read and write functions listed above A failure of any of these cycles indicates the following hardware problems 11 Ethernet Expansion Board Theory of Operation IDLE 0000 INT END END END END END END EN END ND L f C 5 lt 5 9 DMAWR DMARD REGRD LRD LRD RD RG 1001 1000 0100 0110 0010 1100 0001 END END END END EN
25. t 26 4 22 5 XDBUS VALID DATA OBS AUD DAT 1 s Figure 9 LANCE DMA Write Cycle uorqeaodo jo uorsuedxj E zu _ 1 6 E NOTES UNLESS OTHERWISE SPECIFIED L ALL RESISTOR VALUES ARE IN OHMS Aw 2 ALL CAPACITOR VALUES ARE IN MICROFARADS 5 PAGE REFERENCE SHOWN AS SHEET NO TONE 4 THE FOLLOWING COMPONENTS ARE NOT USED ON C37 4 2 RIO VR2 CR2 SPRI Ji 5 6 912 45 20 25 26 J1 4 5 7 810 U 13 14 18 19 21 22 24 25 27 32 33 ci 36 4i 42 45 49 53 ES p E 5 2 26 5 55 TAF 373 DE Jae 574 TALSI25 gt 26 50 3E BF 36 3H 7415125 7ALS244 7 7405 595 2 1 1 PALIGRGA XFMR ISO AM799 7992 MM eese prion m ES cux l RELEASE TO CON Lx REFERENCE _DESIGNATIONS LAST USED NOT USED REVISIONS SPARES EXCL S UNUSED PINS A REV 31 54 56 51 42 45 67 71 74 85 91 14 16 INCHES FINISH MEXT USED ON UNLESS OTHERWISE SPECIFIED THIRD ANGLE DIMENSION
26. ters 2B and 2C located on schematic page 4 These are written to during initialization The LANCE performs 12 single DMA READ cycles when a 1 is being written to the initializing bit of the LANCE control status register Using a logic analyzer check 5D pin 8 RQ located on schematic page 4 for these 12 requests corresponding to bus grant BG from 1H pin 16 with 1A pin 12 XR W high Also as follows 4H pin 17 HOLD schematic page 3 4H pin 19 HLDA 4H pin 18 LAS 4H pin i4 DAS 4H pin 22 READY O O OOO Refer to the timing diagram in Figure 3 After initialization LANCE generates the interrupt active low at 4H pin 11 The state machine gets the status from the LANCE and writes to the status ring The content is 01 1 see the bit definition in the LANCE technical manual The state machine then generates the interrupt to the CPU at the same time that it writes 1s to the LANCE ciearing the LANCE interrupt and status If the initialization is complete and correct the status content at the CPU memory will be 01 1 15 Ethernet Expansion Board Theory of Operation COMPONENT SIGNAL LANCE HOLD dum J 4 LANCE LAS J i LANCE DAS 4E READY 4 RQ 2 CPU BG 500ns XR W Figure 3 Expansion Board Cycle Diagram Next the LANCE performs a single DMA read to the TMD1 every 1 6 msec Using the oscilloscope check the RQ and BG acti
27. vity BG should have a 500 nsec pulse width RQ should be gone 100 nsec after BG is active If there is no activity neither RQ nor BG check if HOLD HLDA LAS DAS READY and CYCO through CYC3 are generated from 4C located on schematic page 5 The cycle should not be stuck at DMA Read longer than 3 us If it is this indicates that 4C and 4E on schematic page 5 or the LANCE is defective 16 Ethernet Expansion Board Theory of Operation DMA Read Write Burst Using a logic analyzer observe the DMA Read Write burst The burst should consist of a transfer of 8 words except for the last cycle if data is fewer than 8 words If the DMA Read Write burst does not perform properly check 4C and 4E on schematic page 5 or the LANCE Interrupt Cycle The interrupt cycle consists of the LANCE sending an interrupt to the state machine at the completion of an operation If there is an error the state machine reads the LANCE status and requests that the status DMA Write cycle be performed Once the state machine gets the bus it writes to the location of the current status ring address and updates the status ring address Then the state machine generates the interrupt to the CPU Note that the status ring content normally shows whether the problem is in either reception or transmission of data Check the receive or transmit descriptor ring for further status information 17 ST XO X 2 3 4 X5 X6 X X8 x9 X10 X11 X12 X13 X14 X15 X1
28. wing components should be checked for failure 2 PROM 745288 or 823123 located on schematic sheet 4 has failed 4B PAL16L8A located on schematic sheet 4 has failed There is no clock present CPU LANCE Read Write Cycle The LANCE location address is being accessed by writing to the Register Address Pointer RAP The CPU LANCE Read cycle is performed in two steps First location 0000 is read second location 0006 is read returning the valid data from the address pointed to by RAP If the CPU LANCE Read Write cycle fails check the following components for the listed conditions 4C PAL20R8 located on schematic sheet 5 the pin 19 22 CYCOM CYC3 is not correct 4E PALI6R6A located on schematic sheet 5 is not providing the proper signal interface DAS and READY to the LANCE 4H 7990 LANCE located schematic sheet 3 is malfunctioning DMA Cycle The DMA cycle consists of three individual cycles as follows DMA Read single or burst cycle DMA Write single or burst cycle STATUS DMA Write single cycle A failure of any of these cycles indicates the following hardware problems as discussed in the following paragraphs 14 Ethernet Expansion Board Theory of Operation DMA Read Write Single On the first two cycies DMA Read and DMA Write the address is provided by LANCE For STATUS DMA Write the address comes from the on board registers 1G and 1E and ring coun
29. with power supply and the Ethernet coax transmission line The EEB is connected to this system by cable For a detailed description of the Ethernet system interface refer to the Ethernet IEEE 802 3 specification and the technical manual for Local Area Network Controller AM 7990 LANCE by Advanced Micro Devices Interface I O Description The expansion board interface consists of drivers and receivers for all required signals to and from the UNIX PC s expansion bus The expansion data bus goes through buffers that are controlled by the state machine section to create the internal data bus The address bus and the bus cycle control signals are received with buffers that are always enabled to create the internal address and control bus The internal address and control bus with the comparator for board ID allows constant monitoring for board I O requests which are then passed on to the state machine For board initiated DMA cycles the state machine generated request read write and data strobe signals are also driven onto the expansion bus by this section Ethernet Expansion Board Theory of Operation Sta ic 1 Ci it The amount of on board status and command information is limited The board ID function has been expanded to allow the CPU to interrogate the board for the 6 byte Ethernet address as well as for the required 4 byte board ID This information is contained in a 32 byte prom accessed at odd byte addresses in the upper
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