Tews Datentechnik TPMC901 Manual
Contents
1. A rtisan Artisan Technology Group is your source for quality TecmologyGrap new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra zer REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED EE Contact us 888 88 SOURCE sales artisantg com www artisantg com IEN SZ The Embedded I O Company TECHNOLOGIES TPMC901 6 4 2 Channel Extended CAN Bus PMC Module Version 1 0 User Manual Issue 1 3 September 2006 D76901801 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone 49 0 4101 4058 0 9190 Double Diamond Parkway Phone 1 775 850 5830 25469 Halstenbek Germany Fax 49 0 4101 4058 19 Suite 127 Reno NV 89521 USA Fax 1 775 201 0347 www tews com e mail info tews com www tews com e mail usasales tews com Artisan Technology Grou2. To enable PCI I O Space access to the PCI9050 set bit 0 to 1 To enable PCI Memory Space access to the PCI9050 set bit 1 to 1 For further information please refer to the PCI9050 1 manual which is also part of the TPMC901 ED Engineering Documentation TPMC901 User Manual Issue 1 3 Page 13 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9050 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9050 Local Configuration Registers is PCI9050 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9050 PCI Configuration Register Space or PCI9050 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9050 PCI Configuration Register Space Do not change hardware dependent bit settings in the PCI9050 Local Configuration Registers Offset from PCI Register Value Description Base Address 0x00 Local Address Space 0 Range OxOFFFF800 Memory Space 6x CAN Controller 0x04 Local Address Space 1 Range OxOFFFFFFD Interrupt Status Register 0x08 Local Address Space 2 Range 0x00000000 Not used 0x0C Local Address Space 3 Range 0x00000000 Not used 0x10 Local Exp ROM Range 0x00000000 Not used 0x14 Local Re map Register Space 0 0x00000001 Enabled lo
3. 0x00 Device ID Vendor ID N 9050 10B5 9050 10B5 Target Chip PCI 9050 1 PLX Technology 0x04 Status Command Y 0280 0000 0280 0000 0x08 Class Code Revision ID N 028000 XX 028000 XX 0x0C BIST Header Type PCI Latency Cache line Size Y 7 0 00 00 00 00 00 00 00 00 Timer 0x10 PCI Base Address 0 for Memory Mapped Configuration Y 00000000 FFFFFF80 Registers 0x14 PCI Base Address 1 for I O Mapped Configuration Registers Y 00000001 FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y 00000000 FFFFF800 Ox1C PCI Base Address 3 for Local Address Space 1 Y 00000000 FFFFFFFD 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 00000000 0x28 Cardbus CIS Pointer N 00000000 00000000 0x2C Subsystem ID Subsystem Vendor ID N 0385 1498 0385 1498 TPMC901 TEWS TECHNOLOGIES GmbH 0x30 PCI Base Address for Local Expansion ROM Y 00000000 00000000 0x34 Reserved N 00000000 00000000 0x38 Reserved N 00000000 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 00 00 01 00 Figure 4 1 PCI Configuration Register Map TPMC901 User Manual Issue 1 3 Page 12 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9050 PCI Base Address Initializat
4. 12 has two CAN bus channels D CAN CAN High Speed K Controller Bus Interface 82527 CAN CAN l High Speed Knnn Controller Bus Interface 82527 CAN CAN Gy High Speed K Controller Bus Interface High Speed Bus Interface High Speed Controller Bus Interface 82527 CAN High Speed Bus Interface Figure 1 1 Block Diagram TPMC901 User Manual Issue 1 3 Page 6 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card PMC Interface Single Size PCI Signaling Voltage 5V PCI Target Chip PC19050 1 PLX Technology CAN Controller Intel 82527 Physical Interface CAN High Speed according to ISO 11898 Bus Line Termination On board 120 ohms selectable by jumper for each channel Transfer Rate 1Mbit s maximum bus line length up to 40m I O Interface Number of Channels TPMC901 10 6 channels TPMC901 11 4 channels TPMC901 12 2 channels UO Connector 1 DB25 male connector all modules Physical Data Power Requirements TPMC901 10 685mA typical 5V DC TPMC901 11 505mA typical 5V DC TPMC901 12 325mA typical 5V DC Temperature Range Operating 0 C to 70 C Storage 55 to 125 MTBF TPMC901 10 378144 h TPMC901 11 446368 h TPMC901 12 544630 h Hum
5. 5 3 Local Bus Little Big Endian TPMC901 User Manual Issue 1 3 Page 17 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Standard use of the TPMC901 Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space TEWSS TECHNOLOGIES 8 bit bus in Little Endian Mode not used not used not used not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a value of 0 indicates Little Endian For further information please refer to the PCI9050 manual which is also part of the TPMC901 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset LASOBRD LAS1BRD LAS2BRD LAS3BRD EROMBRD Name 0x28 Ox2C 0x30 0x34 0x38 Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TPMC901 User Manual Issue 1 3 Page 18 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECH
6. CPU Interface Register 0x02 0x01 Clock divider 1 CLKOUT Register 0x1F 0x20 CLOUT 8MHz Figure 5 2 Required Hardware Initialization TPMC901 User Manual Issue 1 3 Page 16 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWS amp TECHNOLOGIES 5 3 Local Software Reset The PCI9050 Local Reset Output LRESETo is used to reset the on board local logic The PCI9050 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PC19050 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9050 and issues a reset to the Local Bus LRESETof asserted The PCI9050 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9050 PCI and Local Configuration Registers are not reset The PCI9050 PCI Interface is not reset 5 4 Big Little Endian e PCI Bus Little Endian Byte0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 e Every Local Address Space 0 3 and the Expansion ROM Space can programmed to operate in Big or Little Endian Mode Big Endian Little Endian 32 Bit 32 Bit Byte 0 S Byte 1 SE Byte 2 0123 16 Byte 3 SES 16 Bit upper lane 16 Bit Byte 0 Ca Byte 1 SE 16 Bit lower lane Lo 8 Bit upper lane 8 Bit Byte 0 Ca 8 Bit lower lane PF Byte 0 D 7 0 Figure
7. I Base Address 2 for Local Address Space 0 0x0000 to 0x05FF The TPMC901 10 uses all six channels CANCHO to CANCH5 The TPMC901 11 uses only the channels CANCHO to CANCH3 and the TPMC901 12 uses only the channels CANCHO and CANCH1 CAN controller channel 0 CANCHO PCI Base Address 2 0x0000 to 0x00FF 0x0100 to 0x01FF CAN controller channel 1 CANCH1 PCI Base Address 2 0x0200 to 0x02FF CAN controller channel 2 CANCH2 PCI Base Address 2 CAN controller channel 3 CANCHS PCI Base Address 2 0x0300 to 0x03FF 0x0400 to 0x04FF 0x0500 to 0x05FF CAN controller channel 4 CANCH4 PCI Base Address 2 Lef il Rig pd e CAN controller channel 5 CANCHS PCI Base Address 2 For more information about the register sets of the CAN controller refer to the data sheet of the 82527 Serial Communication Controller which is part of the TPMC901 ED Engineering Documentation TPMC901 User Manual Issue 1 3 Page 9 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 3 2 1 CAN Controller Address Map Following figure shows the Address Offset of CAN Controller Register for the TPMC901 xx Register Offset Function 0x00 Control Register 0x01 Status Register 0x02 CPU Interface Register 0x03 Reserved 0x04 0x05 High Speed Read Regi
8. NOLOGIES 6 Installation TPMC901 6 1 CAN Bus Termination Each end of a CAN bus must be terminated by a 1200hms resistor between the CAN bus lines CAN high and CAN low This termination could be activated by installing jumper on the jumper field J3 Jumper J3 1 2 installed Bus line termination for CAN bus channel 0 active Jumper J3 3 4 installed Bus line termination for CAN bus channel 1 active Jumper J3 5 6 installed Bus line termination for CAN bus channel 2 active Jumper J3 7 8 installed Bus line termination for CAN bus channel 3 active Jumper J3 9 10 installed Bus line termination for CAN bus channel 4 active Jumper J3 11 12 installed Bus line termination for CAN bus channel 5 active Factory setting for J3 is bus line termination active for all channels Figure 6 1 Jumper Location TPMC901 User Manual Issue 1 3 Page 19 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 7 Pin Assignment 7 1 Front Panel I O TEWSS TECHNOLOGIES Pin Function TPMC901 10 TPMC901 11 TPMC901 12 01 GND GND GND 14 CAN Low Channel 0 CAN Low Channel 0 CAN Low Channel 0 02 CAN High Channel 0 CAN High Channel O CAN High Channel 0 15 GND GND GND 03 GND GND GND 16 CAN Low Channel 1 CAN Low Channel 1 CAN Low Channel 1 04 CAN High Channel 1 CAN Hi
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10. cal Address Space 1 0x0000 The Interrupt Status Register is a byte wide read register Bit Symbol Description Access Reset Value 7 6 Always read as 1 R 5 CAN5 Interrupt Status of all six channels 4 CAN4 0 indicates interrupt is pending on corresponding channel 3 CAN3 TPM901 10 uses bits 0 to bit 5 l l l R TPMC901 11 uses only bit 0 to bit 3 the bit 4 to bit 7 are 2 CAN2 always 1 1 CAN1 TPMC901 12 uses the bit 0 and bit 1 the remaining bits are 0 CANO always 1 Figure 3 3 Interrupt Status Register STATREG If the PCI Interrupt Enable of the PCI target chip is disabled INTCSR bit 6 is set to 0 the Interrupt Status Register STATREG can be used as a polling register for interrupts of the CAN controllers For disabling the PCI interrupts change only bit 6 of the Interrupt Control Status Register INTCSR Do not change any other bit of this register TPMC901 User Manual Issue 1 3 Page 11 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 PCI 9050 Target Chip 4 1 PCI Configuration CFG Registers 4 1 1 PCI Header of the TPMC901 TEWSS TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits PCI Read after Read after Register write Reset initialization GASS 137 24 123 16 15 817 pe ES rd ren
11. cal 0x0000 0x18 Local Re map Register Space 1 0x00000801 Enabled local 0x0800 0x1C Local Re map Register Space 2 0x00000000 Not used 0x20 Local Re map Register Space 3 0x00000000 Not used 0x24 Local Re map Register ROM 0x00000000 Not used 0x28 Local Address Space 0 Descriptor 0x80307802 Local Timing 6x CAN Controller 0x2C Local Address Space 1 Descriptor 0x00000080 Local Timing Interrupt Status Register 0x30 Local Address Space 2 Descriptor 0x00000000 Not used 0x34 Local Address Space 3 Descriptor 0x00000000 Not used 0x38 Local Exp ROM Descriptor 0x00000000 Not used 0x3C Chip Select 0 Base Address 0x00000401 Chip select 6x CAN 0x40 Chip Select 1 Base Address 0x00000803 Chip select Interrupt Status Register 0x44 Chip Select 2 Base Address 0x00000000 Not used 0x48 Chip Select 3 Base Address 0x00000000 Not used 0x4C Interrupt Control Status 0x00000043 Interrupt Configuration 0x50 Miscellaneous Control Register 0x00780000 Retry Delay max Figure 4 2 PCI9050 Local Configuration Register TPMC901 User Manual Issue 1 3 Page 14 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the PCI9050 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data e Address 0x00 to OxOF PCI9050 PCI Configuration Registe
12. gh Channel 1 CAN High Channel 1 17 GND GND GND 05 GND GND NC 18 CAN Low Channel 2 CAN Low Channel 2 NG 06 CAN High Channel 2 CAN High Channel 2 NC 19 GND GND NC 07 GND GND NC 20 CAN Low Channel 3 CAN Low Channel 3 NC 08 CAN High Channel 3 CAN High Channel 3 NC 21 GND GND NC 09 GND NC NC 22 CAN Low Channel A NC NC 10 CAN High Channel 4 NC NC 23 GND NC NC 11 GND NC NC 24 CAN Low Channel 5 NC NC 12 CAN High Channel 5 NC NC 25 GND NC NC 13 NC NC NC Figure 7 1 DB25 Male Connector TPMC901 User Manual Issue 1 3 Page 20 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality TecmologyGrap new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra zer REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technic
13. idity 5 95 non condensing Weight 859 Figure 2 1 Technical Specification TPMC901 User Manual Issue 1 3 Page 7 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES TPMC901 Local Space Addressing 3 1 PCI9050 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9050 local spaces PCI9050 PCI9050 PCI Size Port Endian Description Local PCI Base Address Space Byte Width Mode Space Offset in PCI Mapping Bit Configuration Space 0 0 0x10 MEM 128 32 LITTLE Local Configuration Registers 1 1 0x14 I O 128 32 LITTLE Local Configuration Registers 2 2 0x18 MEM s b 8 LITTLE Local Address Space 0 3 3 0x1C VO 4 8 LITTLE Local Address Space 1 4 4 0x20 Local Address Space 2 5 5 0x24 Local Address Space 3 6 6 0x30 Local Expansion ROM Space Figure 3 1 PCI9050 Local Space Configuration Size of Local Address Space 0 TPMC901 10 2048 byte TPMC901 11 1024 byte TPMC901 12 512 byte TPMC901 User Manual Issue 1 3 Page 8 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 3 2 Local Address Space 0 The complete register sets of the CAN controllers of the TPMC901 xx are accessible in the memory space of the PMC module Address range PC
14. ion 1 Write OxFFFF FFFF to the PCI9050 PCI Base Address Register 2 Read back the PCI9050 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI UO Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9050 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9050 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9050 PCI Base Address Register After programming the PCI9050 PCI Base Address Registers the software must enable the PCI9050 for PCI I O and or PCI Memory Space access in the PCI9050 PCI Command Register Offset 0x04
15. nnnnnnvnnnnnnnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnennnnn 16 5 2 CAN Controller Hardware Initialization rravvnnnnvnnnnnvnnnnvnnnnnvnnnnnnnnnnvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 16 5 3 Local Software Resets eia EENEG 17 5 4 Big Little Endid aa aaee aa aana aaaea aa naa ae aaan aa suck uate A anaa a aaa anaa aaa aNu 17 6 INSTALLATION TPNGCSOTL eegen 19 6 1 CAN Bus Termination eebe cssnceeececenteecesnecenscueenaededhie EENEG 19 7 PIN ASSIGNMENT E E E 20 TA Front EH E 20 TPMC901 User Manual Issue 1 3 Page 4 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Table of Figures FIGURE 1 1 4 BEOGK DIAGRAM veiene dedikere dd de d 6 FIGURE 2 1 TECHNICAL SPECIFICATION rerrrrravvvnrrrrrvvrnrrrrrnrnrrrsnnnnrrrsnnrnrrrrnnrnrrrrnnnnrrrrrnnnnrsrrnnnnrsrrnnnrsrnnnnne 7 FIGURE 3 1 PCI9050 LOCAL SPACE CONFIGURATION innrrrrrrnnvnrrrrnnvvrrrrnnnvrerrrnnnnrsrrnnnnrsrrnnrnrrrrnnrnnrsrrnnnnn 8 FIGURE 3 2 CAN CONTROLLER ADDRESS MAP TPMCOo0O XN nnne 10 FIGURE 3 3 INTERRUPT STATUS REGISTER STATREG ssssssseessnnssssnnnnnnnnssernnnsttnnnsernnnnttnnnnentnnnntnn nnne 11 FIGURE 4 1 PCI CONFIGURATION REGISTER MAR 12 FIGURE 4 2 PCI9050 LOCAL CONFIGURATION REGISTER rrnnrorernrnnrverrrnavvennrnavrenrrnarseerrnnrresrrnsrresrnrnnnn 14 FIGURE 4 3 CONFIGURATION EEPROM TPMC901 XX rrnnrvvrrrnnvvvrrrnnnvvrrrrnarverrrnnrrerrrnrvre
16. p Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TPMC901 10 6 channel extended CAN bus PMC module TPMC901 11 4 channel extended CAN bus PMC module TPMC901 12 2 channel extended CAN bus PMC module TPMC901 User Manual Issue 1 3 TEWSS TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 1997 2006 by TEWS TECHNOLOGIES GmbH Page 2 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Issue Description Date 1 0 First Issue September 1997 1 1 Revised User Manual September 1999 1 2 General Re
17. r Values e Address 0x10 to 0x64 PCI9050 Local Configuration Register Values e Address 0x65 to Ox7E Not used e Address Ox7F TPMC variant See the PCI9050 Manual for more information Address Offset 0x00 0x02 0x04 0x06 0x08 Ox0A 0x0C Ox0E 0x00 0x9050 0x1498 0x0280 0x0000 0x0385 0x1498 0x0000 0x0100 0x10 OxOFFF s b OxOFFF OxFFFD 0x0000 0x0000 0x0000 0x0000 0x20 0x0000 0x0000 0x0000 Oe 0x0000 0x0801 0x0000 00000 0x30 0x0000 0x0000 0x0000 0x0000 0x8030 0x7802 0x0000 0x0080 0x40 0x0000 0x0000 0x0000 0x0000 00000 0x0000 0x0000 s b 0x50 0x0000 0x0803 0x0000 0x0000 0x0000 0x0000 0x0000 0x0043 0x60 0x0078 0x0000 EFFE 0xFFFF 0xFFFF 0OxFFFF OxFFFF OxFFFF 0x70 OxFFFF OxFFFF OxFFFF 0xFFFF 0xFFFF OxFFFF OxFFFF s b Figure 4 3 Configuration EEPROM TPMC901 xx LSW of Range for PCI to Local Address Space 0 Offset 0x12 TPMC901 10 OxF800 TPMC901 11 OxFDOO TPMC901 12 0xFE00 LSW of Chip Select CS0 Offset Ox4E TPMC901 10 0x0401 TPMC901 11 0x0201 TPMC901 12 0x0101 Subsystem ID Value Offset 0x7E TPMC901 10 Ox000A TPMC901 11 0x000B TPMC901 12 0x000C For changing these configuration values and more details about the EEPROM please refer to the PLX9050 1 data sheet which is part of the TPMC901 ED Engineering Documentation TPMC901 User Manual Issue 1 3 Page 15 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 5 Configu
18. ration Hints 5 1 PCI Interrupt Control Status All CAN controllers generate interrupts at pin INTA of the PCI bus The interrupt status can be read at the Interrupt Status Register STATREG The interrupts can be disabled by setting bit 6 to 0 in the PCI Interrupt Control Status Register INTCSR Bit Symbol Description Access Reset Value 31 8 unused R 0 7 Software Interrupt R W 0 6 PCI Interrupt Enable R W 1 5 Local Interrupt 2 Status R 0 4 Local Interrupt 2 Polarity R W 0 3 Local Interrupt 2 Enable R W 1 2 Local Interrupt 1 Status R 0 1 Local Interrupt 1 Polarity R W 0 0 Local Interrupt 1 Enable R W 1 Figure 5 1 Interrupt Control Status Register INTCSR Address 0x4C 5 2 CAN Controller Hardware Initialization Before reading or writing to any of the CAN controller of the TPMC901 the user must initialize the clock registers of each CAN controller chip It is necessary to do this in a specific order Starting with CAN controller channel 0 then channel 1 channel 2 channel 3 channel 4 and finally channel 5 The following figure lists the hardware initialization required for each CAN controller of the TPMC901 lt is absolutely necessary to initialize the CAN controller of the TPMC901 in the following order Cho Ch1 Ch2 Ch3 Ch4 and Ch5 Register Channel_ Base Address DATA Decryption Control Register 0x00 0x40 Change Configuration Enable
19. rrnnnrerrrnnrreerrnnnn 15 FIGURE 5 1 INTERRUPT CONTROL STATUS REGISTER INTCSR ADDRESS 0X40 aaiisssnnnnneennen 16 FIGURE 5 2 REQUIRED HARDWARE INITIALIZATION erernnnrvvrrrnnvrenrrnnvrvenrrnarverrrnavrenrrnrresrrnrrererrnnrreerrnnnn 16 FIGURE 5 3 LOCAL BUS LITTLE BIG ENDIAN nnne nn anneer anenee nnen 17 FIGURE 6 1 JUMPER LOCATION vescversurandeeceene rakanira nin a EENE NEENA Eade EEEE ANAE a eea eia 19 FIGURE 7 1 DB25 MALE CGONNECTOR 20 TPMC901 User Manual Issue 1 3 Page 5 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 1 Product Description The TPMC901 is a PCI Mezzanine Card PMC compatible module The TPMC901 10 provides six complete CAN bus interfaces using six Intel 82527 CAN controllers Additionally to the standard data and remote frame all channels support the extended data and remote frame according to the CAN specification 2 0 part A and B standard 11 bit identifier and extended 29 bit identifier All channels have the capability to transmit receive and perform message filtering on extended and standard messages Each channel supports CAN High Speed according to 15011898 as the physical interface The bus line termination is selectable by a jumper separate for each bus line pair The data transfer rates of up to 1 Mbps are supported for a bus line length of 40 m The TPMC901 11 supports only four CAN bus channels and the TPMC901
20. ster 0x06 0x07 Global Mask Standard 0x08 0x0B Global Mask Extended 0x0C 0x0F Message 15 Mask 0x10 Ox1E Message 1 0x1F CLKOUT Register 0x20 0x2E Message 2 0x2F Bus Configuration Register 0x30 0x3E Message 3 Ox3F Bit Timing Register 0 0x40 Ox4E Message 4 Ox4F Bit Timing Register 1 0x50 Ox5E Message 5 Ox5F Interrupt Register 0x60 Ox6E Message 6 Ox6F Reserved 0x70 Ox7E Message 7 Ox7F Reserved 0x80 Ox8E Message 8 Ox8F Reserved 0x90 Ox9E Message 9 Ox9F P1CONF OxA0 OxAE Message A OxAF P2CONF 0xB0 OxBE Message B OxBF P1IN OxCO OxCE Message C OxCF P2IN OxDO 0xDE Message D OxDF P10UT OxE0 OxEE Message E OxEF P2OUT OxFO OxFE Message F OxFF Serial Reset Address Figure 3 2 CAN Controller Address Map TPMC901 xx TPMC901 User Manual Issue 1 3 TEWSS TECHNOLOGIES Page 10 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 3 3 Local Address Space 1 The interrupt status register of the TPMC901 is accessible in the I O space of the PMC module Address range PCI Base Address 3 for Local Address Space 1 0x0000 3 3 1 Interrupt Status Register All CAN controllers generate interrupts at pin INTA of the PCI bus The interrupt status can be read at the Interrupt Status Register STATREG It is accessible through the PCI Base Address 3 for Lo
21. vision May 2003 1 3 New address TEWS LLC September 2006 TPMC901 User Manual Issue 1 3 Page 3 of 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION sicsisicscicsisssencsaxcssncsecnxencsacerencencsusnsvadsrenceanstenteadstencsennieneientes 6 2 TECHNICAL SbREGIEIGGTION reese reese eegt eebe Cer Ee ECKE EE ENEE 7 3 TPMC901 LOCAL SPACE ADDRESSING cccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeess 8 3 1 PCI9050 Local Space Configuration rrrsssrrnnvvnnnnvnnnnnvnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 8 3 2 Local Address Eer eege 9 3 2 1 CAN Controller Address Map 10 3 3 Local Address Space DEE 11 SECH Interrupt Status Ee UE EE 11 4 PC 9050 EAR 12 4 1 PCI Configuration CFG Registers rmsrrnnsvrnnnvvnnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnen 12 4 1 1 PCI Header of the TPMC901 aeeseeseeseeseeseesseessessesssissrisstnnstnnnnnnntnnnttnnttnnennnntnnnennnennnnt 12 4 1 2 PCI Base Address Intttalzation neee nn nene ent tnnt tnnnsenn nentrn tnnt tnnnnnnn nannten annene nnne 13 4 2 Local Configuration Register LCR rrrrrnnnnvnnnnnnnnnvvnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnn 14 4 3 Configuration FERRON geed Eege EES 15 5 CONFIGURATION HINTS gees een 16 5 1 PCI Interrupt Control Status rrnssrnnnnvnnnnvennnnvnnnn
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