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Handel-C Language Reference Manual

1. Int G X while trysema RAMsema 0 delay wait till you ve got the RAM x danger count releasesema RAMsSema www celoxica com Page 101 Handel C Language Reference Manual Celoxica 6 Expressions 6 1 Introduction to expressions 6 1 1 Clock cycles required Expressions in Handel C take no clock cycles to be evaluated and so have no bearing on the number of clock cycles a given program takes to execute They affect the maximum possible clock rate for a program the more complex an expression the more hardware is involved in its evaluation and the longer it is likely to take because of combinational delays in the hardware The clock period for the entire hardware program is limited by the longest such evaluation in the whole program Because expressions are not allowed to take any clock cycles expressions with side effects are not permitted in Handel C For example if a lt b CC NOT PERMITTED 7 This is not permitted because the operator has the side effect of assigning b 1 to b which requires one clock cycle 6 1 2 Breaking down complex expressions The longest and most complex C statement with many side effects can be written in terms of a larger number of simpler expressions and assignments The resulting code is normally easier to read For example a DHF FC Cee 2 e i e y ER can be rewritten as a bDt f b bt 1 if c d d 1 else e e IJ c c L 6 1 3 Prefix and postfix o
2. TIMING DIAGRAM SSRAM READ CYCLE USING GENERATED RAMCLK The pulse positions and lengths are specified in cycles and half cycles of CLK The westart and welength specifications are used to place the write enable strobe where it is required Pipelining on chip SSRAM By default the DK compiler uses an inverted version of the main Handel C clock to drive on chip synchronous memories This allows it to conform to Handel C s timing semantics of 1 clock cycle per assignment But it can potentially halve the maximum clock rate for a design Handel C can pipeline accesses to on chip SSRAMs if you write your code in a certain way The effect is that the memory is driven by the main non inverted Handel C clock potentially doubling the clock rate for the design and accesses are performed with 1 clock cycle of latency Creating pipelined SSRAM accesses For memory accesses to be pipelined the following rules must be satisfied e The memory must always be read into an uninitialized register and nowhere else e Nothing else must write to this register For multi port memories both rules must be satisfied for every readable port If these rules are satisfied the compiler removes the output register and drives the memory with the main non inverted Handel C clock e A www celoxica com Page 203 Handel C Language Reference Manual Celoxica You can disable the transform by using the N piperam command line switch or by
3. pragma attribute InstanceN propl 0 pragma attribute InstanceN prop2 SomeString pragma attribute InstanceN prop3 0 pragma attribute InstanceN prop4 1 For VHDL the interface will generate a component instantiation with the following VHDL attributes attribute propl integer attribute prop2 string attribute prop3 boolean attribute prop4 boolean attribute propl of InstanceN label is QO attribute prop2 of InstanceN label is SomeString attribute prop3 of InstanceN label is false attribute prop4 of InstanceN label is true Ei For Verilog the properties specification with a bind specification value of O is only supported for Precision output style 12 23 pull specification The pull specification may be given to an input or tri state bus It is only valid for EDIF output When set to 1 a pull up resistor is added to each of the pins of the bus When e A www celoxica com Page 287 Handel C Language Reference Manual Celoxica set to 0 a pull down resistor is added to each of the pins of the bus When this specification is not given for a bus no pull up or pull down resistor is used Actel ProASIC and ProASIC devices have a pull up resistor but no pull down resistor Refer to the appropriate data sheet for details Most Altera devices do not have pull up or pull down resistors Apexll Mercury Stratix and Cyclone devices have a pull up resistor but no pull down resistor Refer to the app
4. 6 7 2 Implicit compares The Handel C compiler inserts implicit compares with zero if a value is used as a condition on its own For example while 1 Is directly expanded to while 1 0 6 8 Logical operators e A www celoxica com Page 114 Handel C Language Reference Manual Celoxica Operator Meaning amp amp Logical and Logical or Logical not These operators are provided to combine conditions as in conventional C Each operator takes 1 bit unsigned operands and returns a 1 bit unsigned result Note that the operands of these operators need not be the results of relational operators This feature allows some familiar looking conventional C constructs Example if x Il y gt zi w Q In this example the variable x need not be 1 bit wide If it is wider the Handel C compiler inserts a compare with 0 if x 0 y gt z w QO The condition of the if statement is true if x is not equal to O or y is greater than z C like example while x II y Again if the variables are wider than 1 bit the Handel C compiler inserts compares with 0 6 8 1 Bitwise logical operators Operator Meaning amp Bitwise and Bitwise or Bitwise exclusive or e Bitwise not These operators perform bitwise logical operations on values Both operands must be of the same type and width the resulting value will also be this type and width For example HE www celoxi
5. LW ADDRESS DAT AQLIT TIMING DIAGRAM SSRAM READ AND WRITE Specifying SSRAM timing You can place the RAM clock pulses at different points within the Handel C clock if the Handel C clock is divided using external_divide or internal_divide If you have a fast undivided clock CLK a divided clock HCLK and you want to generate a RAM clock RAMCLK the following apply e The SSRAM clock RAMCLK is generated from the fast clock CLK according to the specifications rclkpos wclkpos and clkpulselen These specifications can be in whole or half cycles of the external clock i e the specifications are in multiples of 0 5 e rclkpos specifies the positions of the clock cycles of clock RAMCLK for a read cycle These positions are specified in terms of cycles and half cycles of CLK counting forwards from a HCLK rising edge e wclkpos specifies the positions of the clock cycles of RAMCLK for a write cycle These are also counted forward from an HCLK rising edge e A www celoxica com Page 202 Handel C Language Reference Manual Celoxica e clkpulselen specifies the length of the RAMCLK pulses in CLK cycles This is specified once per RAM It applies to both the read and write clocks Fast clock CLK j Handel C clock HELE div J RAM clock RAMCLE rclkpos 3 0 clkpulselen 0 5 RAM clock RAMCLE rclkpos 1 5 2 5 Clkpulselen 0 5 RAM clock RAMCLEK rclkpos 1 0 3 0 cClkpulselen 1 0
6. 5 16 floating point Constante 315 elle e EE 86 89 differences from ANSI C 86 formatting bus and wire names 243 FPGA devices ccccccceeeeeeeeneeaes 179 180 FUNCTION Colle 127 parallel 127 simultaneous 127 functions 19 111 114 117 118 arrays 119 120 121 nH www celoxica com Page 339 Handel C Language Reference Manual clock cycles 114 141 compared to macros 111 113 114 definitions and declarations 118 differences to ANSI C 19 examples 114 inline 68 parameters 320 pointers 122 123 prototypes 118 restrictions 117 127 129 returning macro expr 71 scope 119 shared 127 syntax 316 320 GG GO 269 281 generic Interface 218 generics VHDIL I eee eees 278 getting starte 5 JOE AR 83 greater than xcadecwinoncacsaceusscterneeuan 106 greater than or equal to 106 GTL I O standard 286 289 290 294 GTL 286 290 294 GTL 286 290 Handel C5 12 14 15 25 29 75 95 111 245 309 code 5 compared to ANSI C 15 25 expressions 95 functions 111 getting started 5 keywords 309 macros 111 object specifications 245 operators 12 programs 5 statements 75 www celoxica com Celoxica syntax 309 types 14 values and widths 29 Handel C oreprocessor 303 bardware a NNN ENN AA 177 interfaces 177 225 WS el lu E EE 20 HSTL I O standard 286 289 291 Class 286 Class II 286 Class III 286 Class IV 286 I O standards 265 286 289 290 294
7. expression postfix_expression expression postfix_expression TH www celoxica com Page 333 Handel C Language Reference Manual Celoxica postfix_expression Lassignment_expression E assignment_expression postfix_expression identifier postfix_expression gt identifier postfix_expression postfix_expression select_expression primary_expression select constant_expression constant_expression constant_expression primary_expression identifier constant expression 9 initializer initializer constant integer_constant character_constant string_constant integer_constant NUMBER character Constant CHARACTER string_constant STRING e A www celoxica com Page 334 Handel C Language Reference Manual 15 Index postfix and prefix operators 95 subtraction EE 104 ue 44 107 DS ieee EE A pte eae haa eee ed eet ec te 106 macro concatenation 306 PROCING eege EE 303 Ee 305 PECs E EE 305 Pendil SE 305 EE E 305 ifndef esesenennnnrerrrrrerrrrrrrrrrrnne 305 la te Te TEE 41 116 304 e te REN 303 To LINOGUIO enee ue Sege 104 line breaker ENN NNN 307 comments delimiter 008 10 structure member operator 109 F AVISION Eeer 104 comments delimiter ccce 10 comments delimiter a ca 10 EE 44 109 concatenation cena ees 102
8. memories off chip RAMs off chip memories off chip Celoxica Meaning Set RAM ROM to be off chip Cannot be used in conjunction with ports Set RAM ROM to be in external code Cannot be used in conjunction with offchip Place write enable Signal Position write enable signal Set length of write enable signal Set read cycle position of SSRAM clock Set write cycle position of SSRAM clock Set pulse length of SSRAM clock Set pins for external RAM or ROM clock Set address pins Set output enable pin s Set write enable pin s Set chip select pin s e A www celoxica com Page 257 Handel C Language Reference Manual 12 1 7 Interface and memory attributes Celoxica This specification defines how interfaces and memory connections are built Specification Speed intime outtime standard strength Possible Values 0 1 2 Actel ProASIC only 0 1 Altera and Xilinx Any floating point delay ns Any floating point delay ns Specified keywords representing I O standards E 4 6 8 12 16 24 mA OR O Min 1 Max Default 2 for Actel ProASIC and ProASIC 1 for Altera and Xilinx Virtex Spartan I1 11E 3 3E 3L series None None LVCMOS33 for ProASIC ProAS IC LVTTL for other devices Various refer to device datasheets Applies to o p or tri state interfaces input port or interfaces o
9. results in Handel C generating this VHDL instantiation of the Bloo component component Bloo port myin out std_logic myout in std_logic IS end component S INN www celoxica com Page 261 Handel C Language Reference Manual Celoxica VHDL example 2 with bind set to 1 interface Bloo unsigned 1 myin B unsigned 1 myout x with bind 1 results in Handel C generating this VHDL instantiation declaration of the Bloo component component Bloo port myin out std_logic myout in std_logic I end component for all Bloo use entity work Bloo In this case Bloo is bound to the work library Verilog example 1 with bind set to O interface Bloo unsigned 1 myin BCunsigned 1 myout x with bind 0 results in Handel C generating this Verilog instantiation of the Bloo component module Bloo input myin output myout endmodule module MyModule wire a D Bloo MyInstance myin a myout b endmodule Note that the code includes a black box declaration of Bloo Verilog example 2 with bind set to 1 interface Bloo unsigned 1 myin BCunsigned 1 myout x with bind 1 results in Handel C generating this Verilog instantiation of the Bloo component S INN www celoxica com Page 262 Handel C Language Reference Manual Celoxica module MyModule wire a D Bloo MyInstance myin a myout b endmodule The VHDL or Verilog synthesizer expects the declaration
10. modulo operator Yes drop LSBs No lt take LSBs No read from channel No conditional expression Yes Bitwise XOR Yes amp Bitwise AND Yes Bitwise OR Yes bitwise NOT Yes amp amp Logical AND Yest Logical OR Yes structure member Yes operator lt lt left shift operator Yes gt gt right shift operator Yes lt less than operator Yes gt greater than operator Yes a less or equal operator Not standard S INN www celoxica com Page 317 Handel C Language Reference Manual Celoxica gt greater or equal Not standard operator equality operator Not standard I inequality operator Not standard increment operator Not standard decrement operator Not standard assignment operator Not standard assignment operator Not standard k assignment operator Not standard assignment operator Not standard assignment operator Not standard lt lt assignment operator Not standard assignment operator Not standard amp assignment operator Not standard assignment operator Not standard assignment operator Not standard Reserved Not valid in Yes Handel C but can be used for C C calls gt structure pointer Yes operator concatenation operator No Note the results of these tests are a single bit unsigned int S INN www celoxica com Page 318 Handel C Language Reference Manual Celoxica Keyword assert auto break case chan chanin chanout char
11. par a funclOJ b c d b foo d func 1 e f j 7 2 9 Multiple functions in a statement Because each statement in Handel C must take a single clock cycle you cannot have multiple functions in a single statement Instead of y f g x illegal you can write z g x y f z Instead of y f x g z illegal you can write e A www celoxica com Page 136 Handel C Language Reference Manual Celoxica par a f x b G7 y atb 7 3 Introduction to macros The Handel C compiler passes source code through a standard C preprocessor before compilation allowing the use of define to define constants and macros in the usual manner Since the preprocessor can only perform textual substitution some useful macro constructs cannot be expressed For example there is no way to create recursive macros using the preprocessor Handel C provides additional macro support to allow more powerful macros to be defined for example recursive macro expressions In addition Handel C supports shared macro expressions to generate one piece of hardware which is shared by a number of parts of the overall program similar to the way that procedures allow conventional C to share one piece of code between many parts of a conventional program 7 3 1 Non parameterized macro expressions Non parameterized macro expressions are of two types e simple constant equivalent to define e a constant expression C
12. Block RAM dual port Block RAM in ESBs dual port Block RAM in ESBs dual port Block RAM in ESBs dual port Block RAM in ESBs dual port Block RAM in ESBs dual port Block RAM in EABs dual port Block RAM in EABs dual port Block RAM in EABs dual port Block RAM in EABs dual port Block RAM in ESBs dual port quad port SelectRAM dual port SelectRAM dual port SelectRAM dual port SelectRAM dual port Block RAM dual port Block RAM in ESBs dual port Block RAM in ESBs dual port Block RAM in ESBs dual port Block RAM in ESBs dual port M4K dual port RAM M4K dual port RAM Block RAM in ESBs dual port Block RAM in EABs dual port Block RAM in EABs dual port Block RAM in EABs dual port Block RAM in EABs dual port Block RAM in ESBs dual port quad port 3 types of dual port RAM in TriMatrix blocks 3 types of dual port RAM in TriMatrix blocks 3 types of dual port RAM in TriMatrix blocks Block RAM Block RAM dual port E E www celoxica com Page 188 Handel C Language Reference Manual Celoxica Xilinx Spartan 3 series SelectRAM dual Block RAM dual port FPGAS port Xilinx Spartan 3E SelectRAM dual Block RAM dual port series FPGAs port Xilinx Spartan 3L SelectRAM dual Block RAM dual port series FPGAs port Xilinx Virtex series SelectRAM dual Block RAM dual port FPGAS port Xilin
13. DUS TO arena E EN 218 221 bus Ce cdock wm 218 224 b s ts latch tb eege 218 222 buses50 52 219 220 221 230 233 243 bidirectional 221 222 224 clocked 221 input 219 latched 220 naming 243 read write 221 read write clocked 224 registered 220 222 simulating 230 specification 50 52 timing 233 235 write 221 busformat specification 243 259 HE www celoxica com Page 336 Handel C Language Reference Manual Eine UE EE 15 25 compared to Handel C 15 25 Eeer Ee 65 calling from Handel C 65 type mapping in Handel C 65 Gis gt tee 88 CASUIAG geet 17 39 96 97 Clie a EE E cones 44 319 CANANI EE 177 319 E E E E E 6 44 46 arrays 46 between clock domains 162 164 166 168 238 chanin and chanout 177 channels AIT OY S csceecteancauavessanse ecesseaccsmeses 46 communication 6 44 162 164 examples 164 metastability 237 238 reading from 44 restrictions 46 Simulating 177 Simultaneous access 46 specifying 319 syntax 319 writing to 44 CON OUT E 177 319 leie ee ER character Constants ccceeeeeees 315 CIOS E 180 el EE 204 261 clkpulselen ccc cee eee eeeeeeeees 195 282 Clock cycles used ees 141 147 clock PIN specfications 261 clock position specifications 282 COCK Vale cea ccestue EEE TA 281 clocked reading from external pins 221 HE www celoxica com Celoxica clockport specification sesser 262 COE ee 141 160 161 162 clock dom
14. Expression Expression Variable Variable Variable Expression Expression Variable lt lt Variable Variable lt lt Expression Expression Variable gt gt Variable Variable gt gt Expression Expression Variable amp Variable Variable amp Expression Expression Variable Variable Variable Expression Expression Variable Variable Variable Expression Expression 5 6 1 continue continue moves straight to the next iteration of a for while or do loop For do or while this means that the test is executed immediately In a for statement the increment step is executed This allows you to avoid deeply nested if else statements within loops e A www celoxica com Page 89 Handel C Language Reference Manual Celoxica Example for i 100 i gt 0 i x f i if x 1 continue y t x Xi E You cannot use continue to jump out of or into par blocks 5 6 2 goto goto label moves straight to the statement specified by Jabe label has the same format as a variable name and must be in the same function as the goto Labels are local to the whole function even if placed within an inner block Formally goto is never necessary It may be useful for extracting yourself from deeply nested levels of code in case of error Example TOP Asse A FOG 2 if disaster goto Error Errori output error_code E You cannot use goto to jump out of or int
15. Length of body length of Iter number of iterations Length of executed case branch e A www celoxica com Page 155 Handel C Language Reference Manual Celoxica prialt 1 clock cycle for case communication when other party is ready plus length of executed case branch or length of default branch if present and no communication case is ready or infinite if no default branch and no communication case is ready releasesema 1 clock cycle delay 1 clock cycle E The Handel C compiler may insert delay statements to break combinational loops 8 2 Avoiding combinational loops If you wish to wait for a variable to be modified in a parallel process before continuing you might write while x 3 WARNING This is bad Handel C code because it generates a combinational loop in the logic This is because of the way that Handel C expressions are built to evaluate in zero clock cycles This is easier to see if it is written as while x 3 wait until x 3 This empty loop must be broken by changing the code to while x 3 d delay This code takes no longer to execute but does not contain a combinational loop because of the clock cycle delay in the loop body The Handel C compiler spots this form of error inserts the delay statement and generates a warning It is considered better practice to include the delay statement in the code to make it explicit Similar problems occur with
16. external P1 void main void unsigned 20 MicroSeconds unsigned 6 Seconds unsigned 6 Minutes unsigned 16 Hours unsigned 3 Count par Count 0 MicroSeconds Q Seconds Q Minutes Q0 Hours Q while 1 d if Count 4 CLOUT THRs else par d Count Q if MicroSeconds 999999 MicroSeconds else par MicroSeconds Q if Seconds 59 Seconds else par d Seconds U if Minutes 59 Minutest else par www celoxica com Page 160 Handel C Language Reference Manual Celoxica Minutes Q HOUT Sts 8 5 Time efficiency of Handel C hardware Handel C requires that the clock period for a program is longer than the longest path through combinational logic in the whole program This means that for example once FPGA or PLD place and route has been completed the maximum clock rate for the system can be calculated from the reciprocal of the longest path delay in the circuit For example suppose the FPGA place and route tools calculate that the longest path delay between flip flops in a design is 70ns The maximum clock rate that that circuit Should be run at is then 1 70ns 14 3MHz If this calculated rate is not fast enough for the system performance or real time constraints you can optimize your program to reduce the longest path delay and increase the maximum possible clock rate You can also use the retiming option to try and match your target clock rate One standard
17. www celoxica com Page 240 Handel C Language Reference Manual Celoxica Even though a read is assigned to both x and y on the same clock cycle if the delay from pin 1 to the flip flop implementing the x variable is significantly different from that between pin 1 and the flip flop implementing the y variable then x and y may end up with different values Handel C clock Pin 1 Input to X Y aue of A Input to Y Value of The delay between pin 1 and the input of y is slightly longer than the delay between pin l and the input to x As a result when the rising edge of the clock registers the values of x and y there is one clock cycle when x and y have different values This effect can also occur in places that are more obscure interface bus_in int 1 read a with data P1 while a read 1 x x l Although a read is only apparently used once the implementation of a while loop requires the signal to be routed to two different locations giving the same problem as before The solution to this problem is to use either a bus_latch_in ora bus_clock_in interface sort The compiler will detect any occurrences of a pin feeding more than one register and issue a warning S INN www celoxica com Page 241 Handel C Language Reference Manual Celoxica 11 5 2 Example timing considerations for output buses int 83 xX int 8 y interface bus_out output int out x y
18. 0 integer prop2 SomeString string prop3 0 boolean prop4 1 boolean For Verilog this interface will generate the instantiation EXtI ning 00 77 propl Somestring prop2 HE J props 1 prop4 InstanceN anothervar x_QOut myvar W_10 For VHDL the interface will generate the following component declaration component ExtThing generic propl integer 0 prop2 string SomeString prop3 boolean false prop4 boolean true a port anothervar in unsigned 5 downto 0 myvar out unsigned 5 downto 0 I end component and the following component instantiation InstanceN ExtT hing generic map propl gt prop2 gt prop3 gt prop4 gt p SomeString false true port map anothervar gt x_Out myvar gt globals_W_10 ds S INN www celoxica com Page 286 Handel C Language Reference Manual Celoxica VHDL Verilog example bind 0 When the bind specification has a value of O attributes are produced instead of generics or parameters for example interface ExtThing unsigned 6 myvar InstlExt Thing unsigned 6 anothervar x with bind 0 properties propl 0 integer prop2 SomeString string 1 props 20 boolean prop4 1 boolean For Verilog and Precision as an output style this interface will generate a module instantiation with the following Precision attributes
19. 103 9 USNE Other RAM E 224 11 NTERFACING WITH EXTERNAL HARDWARE uer Ke Ke KEE KEE KE KEE Kee 225 11 1 UNTERFACE CH KC 225 11 1 1 Reading from external PINS bus Im 226 11 1 2 Registered reading from external pins bus latCh_ wm 227 11 1 3 Clocked reading from external pins DUS dock wm 228 11 1 4 Writing to external pins DUS out 228 11 1 5 Bidirectional data transfer DUS Te 228 11 1 6 Bidirectional data transfer with registered input bus ts latch_in 229 11 1 7 Bidirectional data transfer with clocked input bus ts clock_In 231 11 1 8 Example hardware Imtertace cece cece ee eeeeeee eee eeeeeeeeeeeeeeeeeeestanenaes 232 11 2 SIMULATING INTERFACES Aere bg eege Ee ge EEN e E SNE NEEN 235 11 3 BUSES AND THE SIMULATOR eren KENE KREE KENE E KREE EK RRE KEE RER EEN 237 LLA MERGING TEE 238 11 4 1 Merging clock ons 238 UNE e er OHA NDUE DIN aciera ara A EE AREER TEO EE 239 11 4 3 Merging tri state Pi Suirsine ates cecnyeiissageranmantieciintetisecian eentenenbrnncrentesanuls 239 S INN www celoxica com Page 5 Handel C Language Reference Manual Celoxica 11 5 TIMING CONSIDERATIONS FOR BUSES wenn vn enk KN KKK KK NN KEEN KR KN KREE Ke 240 11 5 1 Example timing considerations for input buses cece eee cece cece ee eeeeees 240 11 5 2 Example timing considerations for Output buses cc eee cece ee eee eeeeeees 242 11 6 METASTABILITY EE 242 11 6 1 Techniques to minimize the problem 243 11 6 2 Using interfaces
20. 224 EVI ee 14 16 22 32 72 clarifier 72 conversion 17 96 97 mapping for C and C 32 65 names 321 operators 16 68 70 71 qualifiers 71 summary 14 type clarifier e 72 AY 0 lt 1 0 ee 69 ENEE 70 TYPOS cece eee eeee 14 16 22 29 31 44 Page 347 Handel C Language Reference Manual architectural 44 logic 31 overview 14 29 types in C and Handel C 16 22 VHDL 295 UNCONStrainedperiOd 00ee cece ees 297 CGS TING oe EE 33 undivided external clOCK 05 190 Bloe La 21 309 GASIGNEG WE 31 32 107 VAIUES wee cc cccee cece ee sseeeeeeeeeeeeeeteaeeneees 29 overflow 29 NGI e 73 151 auto 64 default values 73 initialization 30 64 71 73 local 64 parallel access 151 width of variables 17 29 Vgl e e DEE 278 instantiating components 254 parameters 278 VO BE 295 generics 278 instantiating component 254 types 295 vhdl_ type specificatton 298 Virtex Oevices cece eeeee eee e eee 180 183 constraints files 281 I O standards supported 286 296 mprams 59 on chip RAM 212 RAM timing issues 256 Slew rate of output buffer 286 specifying clock input 262 specifying DC 265 Vie CU PrO EE 180 183 Celoxica e 6 E 39 84 117 WON nee EE 71 warn SfDecCficGation ccc eeeee seen 300 WCIKDOS 2 cece ccc cees scene eee eeeeeees 195 282 WO ieee ene nee yen aero 2 6 WeEgate cece eee eee 188 190 192 300 welength 187 188 190 192 300 westart 187 188 190 192 3
21. External resynchronizing example ssssserererrerrrrerrrrn 246 11 7 PORTS INTERFACING WITH EXTERNAL LOGIC neen enen enka KN KR KK NK kk V 248 11 8 SPECIFYING THE INTERFACE ccceccccncncensnceueneeueneeueneeusneeusneeuenenuen 249 11 9 TARGETING PORTS TO SPECIFIC TOOLS enen kuk KKK KN KE KK KN KEN KE KEN KEN 250 12 OBJECT SPECIFICATIONS EE 252 12 1 SUMMARY OF SPECIFICATIONS unn enen KN Ka KN KEREN KEREN KREE KE KN KEREN KEE EN Ku 252 e lal COMME a leie 252 12 1 2 Simulator QUIMDULES EE 253 ee Des od e elei airs gg lee 254 12 1 4 Channel Ce e die fe EE 256 12 1 5 Channel and memory attributes ccc ccceceee cess eee e eee eeeeeeeeeeeeeeeeeenas 256 e D MCI NOY AC DULG Sams srcacexaiiestaraanlatener ne EEEN 256 12 1 7 Interface and memory attributes ccc ceceee sees eect eee eeeeeeeeeeeeeeeeeeees 258 12 1 8 EES EE 259 a dig EE 260 12 2 BASE SPECIFICATION WE 261 1 2 3 BEND SPECI FICATI a 261 12 4 BLOCK SPECI FI CATION witecntaccamasmennmenamanimenamaens reweewawscwewsaeseuewews 263 12 5 BUFFER SPECIFICATION eege EE EEN 266 12 6 BUSFORMAT SPECIFICATION wunnen Kn Ka KN KE KN KEREN KEE EN KEEN KE KN KEREN KEE EN Ku 266 12 7 SPECIFYING THE CLOCK PIN FOR DRAN e enke KK NN KN KN KR KN KN KEN Ku 268 12 8 CLOCKPORT SPECIFICATION un une a Kn Ka KN KE KN KEREN KEE EN KR KEN KE KN KEREN KEE EN Ku 269 12 9 DATA SPECIFICATION PIN CONSTRAINTS un unn aan KKK KN KE KEN KEN KEN KEN KN 271 12 10 DCI SPECIFICATION HEEN 272 1
22. Handel C Language Reference Manual Celoxica macro proc mp_Swap x y par x y x If you call mp_swap a b the values of a and b will be swapped If you call call f_pseudoswap a b the values a and b are copied to the formal parameters x and y of f_pseudoswap x and y are swapped but a and b are unaffected The swap function with the same behaviour as the macro procedure is therefore void inline f_swap int 12 x int 12 y par a a y ew Xs with a call of the form f_swap amp a amp b Typed or untyped parameters Function parameters must have a type although the width can sometimes be inferred by the compiler Macro expressions and procedures are un typed in the sense that their formal parameters can t be given types The type of macro parameters is inferred from the type in the call statement This means that it is better to use macros for parameterizable code For example macro procedures can be used in libraries if you want to create multiple instances of hardware but leave them untyped to make the code more generic Recursion In Handel C functions may not be recursive Macro procedure and macro expressions can be used to capture compile time recursion If you use recursive macro procedures you need to use ifselect to guard the base case the condition where the recursion terminates If you use recursive macro expressions you need to use select to guard the base case
23. Handel clock with clack divide of 4 welength of 1 5 ech westart of 1 WRITE ENABLE STROBE WITH A WESTART OF 1 A WELENGTH OF 1 5 AND A CLOCK DIVIDE OF 4 applying the specifications to ports mpram wom unsigned 6 r 32 with westart 1 welength 1 5 wom unsigned 6 s 32 rom unsigned 6 t 32 rom unsigned 6 u 32 with westart 1 5 welength 0 5 This example would result in a compiler warning as the specifications at the end would be applied to all ports that do not have their own specification s t and u t and u are read only ports and therefore cannot have write enable specifications However the moram would build correctly with the first set of specifications applied to port r and the second set to port s S INN www celoxica com Page 308 Handel C Language Reference Manual Celoxica www celoxica com Page 309 Handel C Language Reference Manual Celoxica 13 Handel C preprocessor The preprocessor is invoked by the Handel C compiler as the first stage in the compilation process and is used to manipulate the text of source code files Correct use of this tool can simplify code development and the subsequent maintenance process There are a number of functions performed by the preprocessor e Macro substitution e File inclusion e Conditional compilation e Line splicing e Line control e Concatenation e Error generation e Predefined macro substitution Co
24. Ploy P10 P17 P18 P19 P20 PLL PLE fs we P23 oe P24 cs P25 Note that the lists of address and data pins are in the order of most significant to least significant It is possible for the compiler to infer the width of the RAM 8 bits in this example and the number of address lines used 14 in this example from the RAM s usage This is not recommended since this declaration deals with real external hardware which has a fixed definition Accessing RAM Accessing the RAM is the same as for accessing internal RAM For example www celoxica com Page 199 Handel C Language Reference Manual Celoxica ExtRAML1234 23 y ExtRAM 5678 Similar restrictions apply as with internal RAM only one access may be made to the RAM in any one clock cycle The compiled hardware generates the following cycle for a write to external RAM Handel clock Address Data C 29 WEH em E ee IEF The compiled hardware generates the following cycle for a read from external RAM Handel CC clock mates CoR WEH AT This cycle may not be suitable for the RAM device in use In particular asynchronous static RAM may not work with the above cycle due to set up and hold timing violations For this reason the westart welength and wegate specifications may also be used with external RAM declarations 10 3 2 Synchronous RAMs SSRAM clocks Handel C timing sema
25. S INN www celoxica com Page 36 Handel C Language Reference Manual Celoxica When writing programs in Handel C care should be taken that data paths are no wider than necessary to minimize hardware usage While it may be valid to use 32 bit values for all items a large amount of unnecessary hardware is produced if none of these values exceed 4 bits Care must also be taken that values do not overflow their width This is more of an issue with Handel C than with conventional C because variables should be just wide enough to contain the largest value required and no wider You cannot cast a variable or expression to a type with a different width Use the concatenation operator to zero pad or sign extend a variable to a given width 4 1 2 String constants String constants are allowed in Handel C A string constant consists of a string of characters delimited by double quotes They will be stored as a null terminated array of characters as in ANSI C String constants can contain any of the special characters listed below Arrays and pointers can be initialized with string constants and string constants can be assigned to pointers If a string constant is assigned to a pointer the storage for the string will be created implicitly Special characters a alert b backspace VI formfeed n newline r carriage return t tab V vertical tab E backslash Ke question mark S single quote Kg double quote onumber oc
26. as is often done when using a for loop the variable must be declared unsigned Example This loop initializes all the elements in array ax to the value of index S INN www celoxica com Page 41 Handel C Language Reference Manual Celoxica unsigned int 6 ax 7 unsigned index index 0 do d axLindex 0 index index while index lt 6 Note that the width of index has to be adjusted in the assignment This is because its width will be inferred to be 3 from the array dimension the array has 7 elements so index will only ever need to count as far as 6 Multidimensional arrays You can declare multi dimensional arrays of variables For example unsigned int 6 x 4 5 6 This declares 4 5 6 120 variables each of which is 6 bits wide Accessing the variables is as expected from conventional C For example v XicILOILL Pointers to arrays If you want to declare a pointer to the whole of an array rather than an individual element you must enclose the variable name and the in brackets You must also use brackets when initializing a pointer to an entire array Declare an array unsigned 4 MyArray 2 Declare a pointer to an array element unsigned 4 pointer_to_array_element Declare a pointer to the entire array brackets are required unsigned 4 pointer_to_array 2 void main void Initialize pointer to point to an individual array element pointer_to_arr
27. chanout lt type_name gt S INN www celoxica com Page 326 Handel C Language Reference Manual Celoxica 14 11 Ram specifiers syntax ram_specifier ram lt type_name gt rom lt type_name gt wom lt type_name gt 14 12 Declarators syntax declarator width pointer direct_declarator width undefined primary_expression direct_declarator identifier pointer direct_declarator direct_declarator Lconstant_expression direct_declarator parameter_declaration pointer type_qualifier pointer type_qualifier pointer 14 13 Function parameters syntax parameter_declaration declaration_specifiers declaration_specifiers width declaration_specifiers abstract_declarator declaration_specifiers declarator e A www celoxica com Page 32 7 Handel C Language Reference Manual Celoxica 14 14 Type names and abstract declarators syntax type_name type_specifier type_qualifier lt type_specifier type_qualifier abstract_declarator lt type_specifier type_qualifier width abstract_declarator width pointer direct_abstract_declarator direct_abstract_declarator pointer direct_abstract_declarator Ldirect_abstract_declarator constant_expression Ldirect_abstract_declarator L tparameter_declaration 14 15 Statements syntax statement semi_statement non_semi_s
28. clock const continue default delay do double else enum expr extern external external_divide family Ti1odt for goto IT ifselect in inline Meaning diagnostic macro to print to stderr auto variable immediate exit from code block selection within switch and prialt define channel variable simulator channel in simulator channel out 8 bit variable define clock specify that variable s value will not change force next iteration of loop default case within switch prialt wait one clock cycle start do while loop Reserved Not valid in Handel C conditional execution enumeration constant define macro as expression define global variable clock from device pin clock from device pin with integer division define target device s family Reserved Not valid in Handel C for loop iteration jump to specified label conditional execution conditional compilation on compile time selection define scope for local macro expression declaration declaration of inline function ANSI C C Not standard Yes Yes Yes No No No Yes No Yes Yes Yes No Yes C only Yes Yes No Yes No No No C only Yes Yes Yes No No No ee A www celoxica com Page 319 Handel C Language Reference Manual int interface internal internal divid intwidth let long macro mpram par part prialt proc ram register releasesema semaphore reset retu
29. except for external foreign code or off chip RAMs are declared with the interface keyword in Handel C Interfaces are used to communicate with e external devices e external logic such as other Handel C programs programs written in VHDL etc You can communicate between blocks of internal logic using channels The interface definition is in two parts e an interface sort the name of the black box or primitive that the interface connects to e an instance name the name of the instance of the interface sort in Handel C Interface definitions may be split into declarations and definitions You must use a declaration if you want to define multiple instances of the same interface sort or to use forward references The declaration gives the sort name and port names and types associated with that interface sort The definition gives the instance name object specifications and the data transmitted for a single instance of the interface sort Only signed and unsigned types may be passed over interfaces Your license may not allow you to use interfaces If this is the case you can only interface to external devices using macros provided in any Celoxica libraries you have licenses for such as PAL 4 6 1 Interface declaration You need to use an interface declaration if you want to define multiple instances of an interface sort or to use forward references If you only want a single instance of an interface sort you only need t
30. int 4 left right return left right Function declaration A function declaration lists the function name return type and the types of the parameters The syntax is returnType Name parameterlType_1 parameter_1 parameterType_n parameter_n Note the semicolon following the parameter list e A www celoxica com Page 125 Handel C Language Reference Manual Celoxica You may omit the parameter names in a declaration The parameter types are used by the compiler to check that the correct types are used for the function arguments within the rest of the file Old style ANSI C declarations where the names but not the type of the parameters are given are not supported 7 2 2 Functions scope Functions cannot be defined within other functions By default functions are extern they can be used anywhere Functions can also be defined as static they can only be used in the file in which they are defined 7 2 3 Arrays of functions An array of functions is a collection of identical functions It is not the same as an array of function pointers each of whose elements can point to a different function A function array allows you to run different copies of the same function in parallel Without this construct the only safe way to run a function in parallel with itself would be to explicitly declare two functions with different names Function arrays allow functions to be copied and shared neatly For example un
31. not array or struct The compiler generates an error if the ports and offchip specification are both set to 1 for the same memory All other specifications can be applied If you use the ports specification with an MPRAM a separate interface will be generated for each port You cannot initialize a memory that uses the ports specification Examples mpram ram lt unsigned 8 gt ReadWritel256 Read write port rom lt unsigned 8 gt Read 256 Read only port Joan with ports 1 busformat B lt I gt generates EDIF ports with names prefixed by Joan_Read and Joan_ReadWrite For example interface port Joan_Read_addr lt 0 gt direction INPUT port Joan_Read_addr lt 1 gt direction INPUT interface port Joan_ReadWrite_addr lt 0 gt direction INPUT port Joan_ReadWrite_addr lt l gt direction INPUT www celoxica com Page 284 Handel C Language Reference Manual Celoxica 12 22 properties specification The properties specification can be given to generic interfaces If you are generating EDIF it is used to parameterize instantiations of external black boxes Each valid property is propagated through to the EDIF netlist as an EDIF property If you are generating VHDL or Verilog the result of the properties specification depends on the value of the bind specification When the bind specification has a value of 1 it is used to define generics VHDL or parameters Verilog when creating a
32. pointerName parameter list The parentheses at the end of the declaration declare the pointer to be a pointer to a function The before the pointerName declares it to be a pointer declaration S INN www celoxica com Page 48 Handel C Language Reference Manual Celoxica There is the standard C type ambiguity between the declaration of a function returning a pointer and a pointer to a function To ensure that is associated with the pointer name rather than the return type you need to use parentheses int 8 functionName function returning pointer and int 8 pointerName pointer to function 4 3 3 Pointers to interfaces When declaring pointers to interfaces you must ensure that you declare a pointer to an interface sort and then assign a defined interface to it much as when you declare a pointer to a function You cannot combine the definition of an object with the declaration of a pointer to it The members of the interface must have the same name in the declaration of the pointer type as in the definition of the interface object which you assign the pointer to Example declaration of pointer to interface of sort Dus out interface bus_out p int 2 x interface bus_out bCint 2 x y interface definition p amp b p now points to b 4 3 4 Structure pointers The structure pointer operator gt can be used as in ANSI C It is used to access the members of a structure when the structur
33. wiin data P7 POT Re mPa wero 5 ES P1 BTS A multiplier contains deep logic so some of the 8 pins may change before others leading to intermediate values It is possible to minimize this effect although not eliminate it completely by adding a variable before the output This effectively adds a flip flop to the output The above example then becomes Int o X nio y Int 8 Z interface bus_out output Cint out zZ with idata i PZ Po Pas PA Ee P2 P1 POTEP z xX y You must now take care to update the value of z whenever the value output on the bus must change 11 6 Metastability If the input of a flip flop is connected to a signal which is not synchronous with the flip flop s clock then its setup or hold time may be violated This can result in the flip flop entering a metastable state when it is clocked The output of the flip flop will then have an unpredictable value for an indeterminate period of time but will eventually become either O or 1 In some circumstances such as when two independent clocks are involved metastability cannot be avoided While a metastable flip flop may remain so for any length of time there is a high probability that it will enter a stable state after a relatively short delay e A www celoxica com Page 242 Handel C Language Reference Manual Celoxica The metastability characteristics of digital logic devices vary enormously Refer to product data shee
34. would give the three bit value on pins P3 P4 and P5 If the input pins have an intime specification you need to ensure that these match 11 4 3 Merging tri state pins Tri state bus pins can be merged though doing so will generate a compiler warning as the compiler cannot detect whether the outputs for both pins might be enabled at the same time If both outputs are enabled at the same time the result is undefined If you have used any intime and outtime specifications make sure that they match You might wish to merge output pins for a tri state bus if you wished to switch the circuit connections from one external piece of logic to another For example int 1 enl en2 int 4 X y interface bus_ts_clock_in int 4 read BiBusl int 4 writePort x 1 unsigned 1 enable en1 1 with data P4 P3 P2 P1 interface bus_ts_clock_in int 4 read BiBus2 int 4 writePort y l unsigned 1 enable en2 1 with data P4 P3 P2 PI Fi x Take care when driving tri state buses that the FPGA PLD and another device on the bus cannot drive simultaneously as this may result in damage to one or both of them S INN www celoxica com Page 239 Handel C Language Reference Manual Celoxica 11 5 Timing considerations for buses bus_in interfaces This form of bus is built with no register between the external pin and the points inside the FPGA or PLD where the data is used If the value on the external pin change
35. www celoxica com Page 296 Handel C Language Reference Manual Celoxica 12 32 31 O standard details The following input output standards are available in Handel C To select a standard use the standard specification AGP 1x 2x Advanced Graphics Port The AGP standard is specified by the Advanced Graphics Port Interface Specification Revision 2 0 introduced by Intel Corporation for graphics applications AGP is a voltage referenced standard requiring a reference voltage of 1 32 V an input output source voltage of 3 3 V and no termination This standard requires a Differential Amplifier input buffer and a Push Pull output buffer BLVDS Bus Low Voltage Differential Signal BLVDS is a differential I O scheme although it is not currently defined by any EEE EIA TIA industry standards Unlike LVDS and LVPECL which are intended for point to point communications BLVDS allows for bi directional data transfer over the same set of transmitter receiver pin pairs also known as transceivers It thus enables transmission of high speed differential signals over multipoint backplanes Due to the bi directional transfer capability 50 ohm termination resistors are needed at both ends of the transmission line CTT Center Tap Terminated The CTT standard is a 3 3V memory bus standard specified by JEDEC Standard J ESD 8 4 Center Tap Terminated CTT Low Level High Speed Interface Standard for Digital Integrated Circuits and sponsore
36. x 4 Cy 4 x temp2 0 temp1 4 temp1 3 0 Comparison example while x lt y RTT can be replaced with while x y XH The and comparisons produce much shallower logic although in some cases it is possible to remove the comparison altogether Consider the following code LAA www celoxica com Page 162 Handel C Language Reference Manual Celoxica unsigned 8 x x 0 do Xx xet 1 while x 0 This code iterates the loop body 256 times but it can be re written as follows unsigned 9 x x 0 do Xx xet 1 while xL8 By widening x by a single bit and just checking the top bit we have removed an 8 bit comparison Complex expression example Sg Pat Oa ee EN AN reduces to par templ temp2 temp3 temp4 Q MO MQ OD templ templ temp2 temp3 temp3 temp4 x templ temp3 This code takes three clocks cycles as opposed to one but each clock cycle is much Shorter and so the rest of the circuit should be speeded up by the faster clock rate permitted Se www celoxica com Page 163 Handel C Language Reference Manual Celoxica Empty statement example if a gt b x if b gt c x if c gt d x if d gt e St if e gt f x 3 If none of these conditions is met then all the comparisons must be made in one clock cycle By filling in the else statements with delays the
37. 0 V PCI 66 MHz 3 3 V PCI X GTL GTL HSTL 1 5v Class HSTL 1 5v Class Il LVCMQS33 EV GMUS25 LV GMOS 1G LVCMQSI15 LVCMQSI12 PPG hoo 9 Polo PCI66_3 WEE GTL GTL HSTL_I HSTL_II HSTL 1 8v Class I HSTL 1 8v Class III HSTL 1 8v Class IV SSTL 2 5v Class SSTL 2 5v Class Il SSTL 3 3v Class SSTL 3 3v Class Il SSTL 1 8v Class SSTL 1 8v Class Il CTT AGP 1x AGP 2x Horie LIS HSTL18_III HSTLI8_IV TSS Ea e RE e AT STES L7 eeh e I7 eh JMI 1 CTT AGP 1X AGP 2X Celoxica LVDS 3 3V BLVDS 2 5V see note 1 LVPECL 3 3V see note 1 LVDCI 3 3 V see note 2 LVDCI 2 5V see note 2 LVDCI 1 8 V see note 2 LVDCI 1 5 V see note 2 LVDCI 3 3 V Split termination see note 3 LVDCI 2 5 V Split termination see note 3 LVDCI 1 8 V Split termination see note 3 LVDCI 1 5 V split termination see note 3 HyperTranspo rt LVDS33 RAN DEE EVDCI_33 LVDCI_25 LY DGL Io LVL ae UVOCL DV2 33 CHE DV 2 25 LVYDCI_DV2_18 LVYDCI_DV2_15 HyperlTranspo rt e A www celoxica com Page 295 Handel C Language Reference Manual Celoxica HSTL HSTL ITI 1 5v Class III HSTL HSTL_IV 1 5v Class IV Notes 1 The only differenti
38. 10 The base specification can be used to write to the outfile in different formats Block data transfers allow algorithms to be debugged and tested without needing to build actual hardware For example an image processing application may store a source image in a file and place its results in a second file All that need be done outside the Handel C compiler is a conversion from the image e g J PEG file into the text file which can then be used by the simulator and a conversion back from the output file to the image format The results can then be viewed and the correct operation of the Handel C program confirmed 10 2 Targeting FPGA and PLD devices The Handel C language is designed to target real hardware devices To do this you must Supply this information to the compiler S INN www celoxica com Page 186 Handel C Language Reference Manual Celoxica the FPGA PLD family and part that the design will be implemented in These are supplied on the Chip tab of the Project gt Settings dialog They can also be specified in the source code using the set family and set part statements or they can be supplied to the command line using the f family and p part switches They will be passed to the FPGA PLD place and route tool to inform it of the device it should target in some cases the location of a reset source required for Actel devices The reset source is specified using the set reset command Your license may restrict the
39. 293 12 31 SPEED SPECIFICATION eege ee 293 12 32 STANDARD SbPECIEICATION unn un Kn KR KEEN EN KR ER KEEN E KN ENER KN KN ER KEEN ENN 293 12 32 1 Available e Gran Te LEE 294 12 32 2 I O standards supported by different chpe cece ee esse tees eeeeeeeeeeees 296 12 32 3 I O Standard details 297 12 32 4 Differential I O standardS EE 301 12 33 STD_LOGIC_ VECTOR SPECIFICATION see KEE KEE KEE KEE 302 12 34 STRENGTH SPECIFICATION nun u a KN KR KEEN EN KN ER KEEN E KN ENER KN KN ER KEEN ENN 303 12 35 SYNCHRONOUS SPECIFICATION ssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 304 12 36 UNCONSTRAINEDPERI OD SPECIFICATION oun un vn Kn KK a KN KR ER ENKE KN KR KE 304 12 37 VHDL_ TYPE SPECIFICATION unn E KEE KEE KEE KEE 305 12 38 WARN SPECIFICATION scesecnceneneeenceueuecscenueueusnuaueueuenenuaueueuanus 307 12 39 WEGATE SPECI FICATION euer 307 12 40 WESTART AND WELENGTH SPECIFICATIONS sssnnnnnnnnnnnnnnnnnnnnnnnnnnnn 307 13 HANDEL C PREPROCESSOR aen KR KN KN KN KR ER ENKE KN KR KEREN KN ER KEEN EN KN ER KEEN ENN 310 13 1 PREPROCESSOR MACROS uvsescececcceueuececeeueueuennnenueuenenesueueuenenenuans 310 Ke FILE INCLUSION NEE 311 13 3 CONDITIONAL COMPILATION unn un Kn KR KEEN EN KN ER KEEN E EN KEEN KN KN ER KEEN ENN 312 Se EVN CONTROL BEEN 313 13 5 CONCATENATION IN MACROS vccscencccccceuecenecceueuenenecueusnenuaueueuagegs 313 13 6 ERROR GENERA TI ON EEN 314 13 7 PREDEFINED MACRO SUBSTITUTION unn u a Kn KR KEEN E KN KR KEEN E KR KEEN ENN 314 13 8 LINE SPU CUN
40. 4 ReturnData void main void while 1 delay program will wait until data received ReturnData result x File transmit hcc secondary clock domain running at half the speed of the primary one SE set clock external_divide R25 2 chan unsigned 4 ReturnData channel must have global scope void main void Static unsigned 4 x while 1 ye a ReturnData x l www celoxica com Page 172 Handel C Language Reference Manual Celoxica Example channels between clock domains File transmit hcc chan 8 c channel must have global scope set clock external P1 with paranoia 2 void main void int 8 x y c X program will wait until data successfully transmitted c L y File receive hcc extern chan cC set clock external P2 void main void int o Pe Gs cr p C4 Managing channel timing The timing of channels between clock domains is controlled by e the number of flip flops used to resolve metastability this is set by the paranoia specification defaulting to 1 e the value of resolutiontime how long it is before you sample a signal OR the value of minperiod how long is available before the signal is moved on Se www celoxica com Page 173 Handel C Language Reference Manual Celoxica e the value of unconstrainedperiod This is the timing constraint on the compiler generated synchronizing control paths
41. 5011 7012 3 1341 2010 5013 4 1808 2513 4013 5 1510 2155 3215 6 1343 1888 2731 7 1008 1010 2389 8 1102 1443 2269 9 1012 1348 1926 10 1012 1265 1771 11 1012 1192 1634 12 1012 1128 1521 13 1012 1070 1422 14 1012 1010 1354 15 1008 1010 1304 16 1012 1018 1239 17 1012 1018 1188 18 1012 1018 1142 19 1012 1018 1060 20 1012 1018 1060 This demonstrates that timing between different clock domains cannot be predicted accurately FIFOs with a length of a power of 2 are slower Other differences may be accounted for by layout It will not vary widely over different devices and different clock rates Synchronization between clock domains You may use a zero width channel to convey synchronization information between clock domains Sending 0 along a O width channel will create the synchronization hardware such that subsequent statements will be synchronized For example if you have two statements in different clock domains and you want one to execute if and only if the other one does then you can do something like Domain lL S INN www celoxica com Page 178 Handel C Language Reference Manual Celoxica chan unsigned O ch ehti lt statement 1 gt Domain 2 extern chan ch unsigned 0 junk ch junk lt statement 2 gt In this example each domain will wait for the other before statement 1 and statement 2 are executed Using interfaces to communicate between clock domains If you are using interfaces rather than ch
42. C code to VHDL or Verilog you can only use the data specification to constrain pin locations for Precision and Synplify style outputs If you compile for ModelSim or Active HDL the data specification is ignored In Precision VHDL or Verilog output styles pin constraints are implemented using the pin_number attribute In Synplify style output pin constraints are implemented using the loc attribute If the busformat specification is used as well as data specifications for port type or generic interfaces the data specifications are ignored and a warning is issued S INN www celoxica com Page 271 Handel C Language Reference Manual Celoxica Bus type interface example macro expr dataPins 4 P3 PZ Pl PO s interface bus_in unsigned 4 inPort hword with data dataPins intime 5 Port type interface example macro expr dataInNames I3 I2 I1 I0 macro expr dataOutNames 03 02 02 O1 unsigned 4 x interface port_in unsigned 4 in Ig with data dataInNames interface port_out Og unsigned 4 out x with data dataOutNames Generic interface example macro expr dataInNames I3 I2 I1 I0 macro expr dataOutNames 03 02 02 O1 unsigned 4 x interface Igator unsigned 4 in with data dataInNames InstI gator unsigned 4 out x with data dataOutNames d 12 10 dci specification The dci specification may be used with th
43. Clock A Channel synchronisers L time to transfer between domains paranoia in domain B 1 Xt La clock period in domain B Gis unconstrainedperiod Li minperiod Using clock specifications to manage timing between clock domains You can use clock specifications to specify the timing of the synchronization hardware Set the values on a clock to affect the timing of ALL channels to and from that domain set clock external C43 with rate 40 resolutiontime 20 This gives a clock period of 25ns It assumes that 20ns is required for the control signal to stabilize leaving 5ns for it to be routed onwards p T o MRR pm mm mm l M mm mmm E lres Minperiod perad RESOLUTION TI ME AND PROPAGATION TI ME IN ONE CLOCK TICK www celoxica com Page 174 Handel C Language Reference Manual Celoxica If it takes longer for the data to stabilize you can increase the number of flip flops used to stabilize the data by setting the paranoia specification In this case the stabilization time in each clock period is resolutiontime paranoia If paranoia is set to 3 then the resolution time required in each clock tick is 1 3 the value of resolutiontime giving a larger possible value for data to be routed on Jo 3 a bk t Imp A up me Speed versus metastability When you increase the paranoia specification on the clock domains you increase the latency of channels into the domain T
44. Compound statements with replicators ccc cece cece eee eeeeeeeeeeeeeeeeenas 14 16 REPLICATORS SYNTAX ZEN 14 17 EXPRESSIONS SYNTAX neu ENKER KEN KEN ENNEN KEN KEN KEN KREE ER KN ENNER KEE KEN Ku 15 AND EX EE S INN www celoxica com Page 8 Celoxica Handel C Language Reference Manual Celoxica Conventions A number of conventions are used in this document These conventions are detailed below x Warning Message These messages warn you that actions may damage your hardware Ei Handy Note These messages draw your attention to crucial pieces of information Hexadecimal numbers will appear throughout this document The convention used is that of prefixing the number with Ox in common with standard C syntax Sections of code or commands that you must type are given in typewriter font like this void main Information about a type of object you must specify is given in italics like this copy SourceFileName DestinationFileName Optional elements are enclosed in square brackets like this Struct type Name Curly brackets around an element show that it is optional but it may be repeated any number of times string tcharacter e A www celoxica com Handel C Language Reference Manual Celoxica Assumptions amp Omissions This Manual assumes that you e have used Handel C or have the Handel C Language Reference Manual e are familiar with common programming terms e g functions e a
45. E 154 EE 84 CPUN sere aE E G 37 319 enumerated types 00ee eee 37 319 EIER 106 error Oeneration 99 307 ESB E ed ee 180 256 examples asynchronous RAM 188 190 between clock domains 164 function pointers 123 functions 114 120 121 interfacing to hardware 225 macros 114 mprams 61 optimizing code 123 154 157 prialt 79 SSRAM 200 205 207 targeting external RAM 192 204 targeting ports to specific tools 243 timing 141 152 270 Excalibur devices c 180 183 I O standards supported 289 296 RAM 211 exit from code DIOCK c cece eee 89 EXPIESSIONS cccceeeeeeeeeeeees 23 95 314 comparison with ANSI C 23 complex 72 constant 314 shared 135 136 syntax 325 timing 95 extern external variables 65 Celoxica extern linking to C C code 65 external cdocke 161 187 189 external bardware 218 external ROMS cceeeeeeeeeeeeeees 212 external variables 65 external dIVIde cece eee ees 160 161 EEN ee 266 EE 266 Alle eee a en eee 266 Eelere EE 268 TAMINIOS cece cece e eee ees 179 180 183 recognized 180 183 fast external clock 187 e Leen TEEN 268 Slaet EE 6 268 code example 46 145 timing 144 TC Sock Gee Ee 304 Including 304 reading and writing 178 timing constraints 269 281 Flex d vices cece cece cece eeeeees 180 183 constraints files 281 I O standards supported 289 RAMs 211 WO ee sees 16 309 floating point arithmetic
46. EEE E E E 99 5 6 13 releasesema nunnenererrererrererrrrrrerrrrrrerrrrerrrrrrerrrrrrererrererrrrererrrrerrrre 100 EXPRESS ONS ege eg bereede NEE EEEE 102 6 1 INTRODUCTION TO EXPRESSIONS uk ek KE KEE KEE KEE KEE KEE E Ku e 102 ZER Ba DR Clock Cy eS FEOU INGO EE 102 6 1 2 Breaking down complex EXPIESSIONS cece cece cece eee eeeeeeeeeeeeeeeeseeneeneeegs 102 6 1 3 Prefix ANd postfix operatore cece cece seen eee e tees sees eeeeeeeeeeeteeeeeaennengs 102 6 2 CASTING OF EXPRESSION TYPES ere KE KEE KEE EE EE KEE KK ebe 103 62 1 IRESEFICUIONS ON Cast e EE 104 6 3 RESTRICTIONS ON RAMS AND ROMS EE KEE KEE KEE KK ebe 104 6 4 ASSERT E 106 6 5 BIT MANIPULATION OPERATORS unn e Ke KEE KEE KEE KEE KEE KEE E Ku e LOS 65 1 SNIE OC EE 109 6 5m Take Grop OCCA eet 109 6 5 3 CONCAtENAtLION operator cess cece cece eeeeseeeeeeeeeeeseeeaeeeeeesteseeaanneengs 109 omer ao Lies 2 den EE 110 6 930 VIG O06 aCOl EE 111 6 6 ARITHMETIC OPERATORS une ek KEN EK REENEN E KREE EK NEE KREE KEE KEE KK ue 111 6 7 RELATIONAL OPERATORS ssssssss 2 22 20020202202u20u2u0u0uunununnununnnnnnnnnnn 113 6 7 1 SIGNEG UNSIONEO Been EE 114 S INN www celoxica com Page 3 Handel C Language Reference Manual Celoxica SE SE Ree EREE AR TEE 114 6 8 LOGICAL OPERATOR EEN e E 6 8 1 Ee E logical Operators EE 115 6 9 CONDITIONAL OPERATOR ssssnnuuunnnnnuunnnnnnununnnnnununnnnnnnnnnnnnnnnnnnnnn L LO 6 10 MEMBER OPERATORS gt auuusnnnnnsnnnnuununnnnnnnnnnnn
47. Each of these statements takes one clock cycle Notice that even the most complex expression can be evaluated in a single clock cycle Handel C builds the combinational hardware to evaluate such expressions they do not need to be broken down into simpler assembly instructions as would be the case for conventional C Parallel statements par x y Da g This code executes in a single cycle because each branch of the parallel statement takes only one clock cycle This example illustrates the benefits of parallelism You can have as many non interdependent instructions as you wish in the branches of a parallel statement The total time for execution is the length of time that the longest branch takes to execute For example par x y b c d This code takes two clock cycles to execute On the first cycle x y anda b take place On the second clock cycle c d takes place Since both branches of the par statement must complete before the par block can complete the first branch delays for one clock cycle while the second instruction in the second branch is executed While loop X 5 while x gt 0 Ame This code takes a total of 6 clock cycles to execute One cycle is taken by the assignment of 5 to x Each iteration of the while loop takes 1 clock cycle for the assignment of x 1 to x and the loop body is executed 5 times The condition of the while loop takes no clock cycles as no assignment is invol
48. Fall through of cases in a prialt construct is prohibited This means that each case must have its own break statement If the same channel is listed twice in its cases only the first occurrence will ever be accessed You would only wish to do this if the channel within the prialt is the result of an expression e g a pointer to a channel or a reference to an array of channels The compiler cannot reliably check this condition so it will not cause a warning If a channel between clock domains has fifolength 0 default and has a prialt on both sides the compiler will convert it to have a fifolength 1 This is also true if a channel within a prialt has the other side within a try reset in a different clock domain 5 5 Using prialt examples The prialt statement selects the first channel ready to communicate from a list of channel cases int 4 x y Z chan lt int 4 gt first second par prialt case first x break case second y break seq delay second Z Send and receive statements can be mixed within a prialt For example e A www celoxica com Page 86 Handel C Language Reference Manual int 4 num even odd chan lt int 4 gt chl ch2 par if numLO 0 chl odd else ch2 num prialt case chl num break case ch2 even break Restrictions on using prialt mE 4 X y Chan lt int 4 gt ch prialt case ch x break case ch y illegal ch alread
49. INN www celoxica com Page 281 Handel C Language Reference Manual Celoxica 12 19 paranoia specification The paranoia specification controls the number of flip flops used in synchronization hardware for channels across clock domains The higher the value for paranoia the higher the stability and latency of the channels The default is 1 which should be adequate in most cases If latency is an issue it is possible to set paranoia to 0 but the circuit is more likely to be metastable Circuit with paranoia set to default of 1 The diagram below shows a circuit with paranoia set to 1 In this case the synchronization data goes through one extra flip flop before generating the clock enable signal for the register Clock A Clock B Channel synchronisers TIMES WITH PARANOIA AT ITS DEFAULT OF 1 L time to transfer between domains paranoia 1 xt tup unconstrainedperiod Bee minperiod t clock period S INN www celoxica com Page 282 Handel C Language Reference Manual Celoxica Circuit showing constraints if paranoia Is set to 0 Clock A Clock B Channel t CE t contral logic synchronisers TIMES WITH PARANOIA SET TO O 12 20 Pin specifications The addr data we cs and oe specifications each take a list of device pins and are used to define the connections between the FPGA PLD and external devices The Specifications only have meaning for EDIF V
50. Macro procedure example www celoxica com Page 119 Handel C Language Reference Manual Celoxica unsigned 4 g macro proc p x ifselect width x 0 g 0 x p x 1 else delay set clock external void main d unsigned 4 1 Oe Lae Macro expression example macro expr copycat copies bits select copies lt 0 unsigned 0 0 bits copycat copies 1 bits 7 1 2 Functions and macros sharing hardware Calls to functions and shared expressions result in a single shared piece of hardware This is equivalent to an ANSI C function resulting in a single shared section of machine code Shared hardware will reduce the size of your design but care is needed if you have parallel code where multiple branches access the shared hardware Shared hardware may also compromise the speed of your design as it tends to lead to an increase in logic depth Each call to an inline function macro procedure or macro expression results in a separate piece of hardware Arrays of functions allow a specified number of copies to be created S INN www celoxica com Page 120 Handel C Language Reference Manual Celoxica 7 1 3 Functions and macros clock cycles Macro expressions and shared expressions are evaluated in a single clock cycle where the expression is assigned to a variable Functions and macro procedures may involve control logic and may take many cycles 7 1 4 Functions and macros example
51. Non terminated Digital Integrated Circuit This is a single ended general purpose standard used for 2 5V or lower applications It uses a 5V tolerant CMOS input buffer and a Push Pull output buffer This standard requires a 2 5V input output source voltage but does not require the use of a reference voltage or a board termination voltage Altera documentation refers to this Standard as simply 2 5 V LVCMOS 1 8 V 1 8 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard and is documented by J EDEC Standard JESD 8 7 1 8 V 0 15 V Normal Range and 1 2 V to 1 95 V Wide Range Power Supply Voltage and Interface Standard for Non terminated Digital Integrated S INN www celoxica com Page 298 Handel C Language Reference Manual Celoxica Circuit This is a single ended general purpose standard used for 1 8V power supply levels and reduced input and output thresholds It uses a 5V tolerant CMOS input buffer and a Push Pull output buffer This standard does not require the use of a reference voltage or a board termination voltage Altera documentation refers to this standard as simply 1 8 V LVCMOS 1 5 V 1 5 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard This is a single ended general purpose standard used for 1 5V applications It uses a 5V tolerant CMOS input buffer and a Push Pull output buffer This standard does not require the use of a reference voltage or a board term
52. Set std_logic_vector to 1 if you want to e instantiate an external block of code in Handel C generated VHDL and the external block uses one or more std_logic_vector ports e produce a block of VHDL that will be linked into another VHDL block that uses one or more std_logic_vector ports The default value for std_logic_vector is 0 You can apply the std_logic_vector specification to an individual port If you place the specification at the end of the interface statement it will be applied to all the ports The std_logic_vector specification is ignored for all outputs except for VHDL Example 1 Handel C instantiation of a Bloo component with std logic vector set to 0 default Interface Bloo unsigned 1 myin BCunsigned 4 myout x with std_logic_vector 0 results in Handel C generating this VHDL instantiation of the Bloo component www celoxica com Page 302 Handel C Language Reference Manual Celoxica component Bloo port myin out std_logic myout in unsigned 3 downto 0 E end component Example 2 Handel C instantiation of a Bloo component with std_logic_vector set to 1 interface Bloo unsigned 1 myin B unsigned 4 myout x with std_logic_vector 1 results in Handel C generating this VHDL instantiation of the Bloo component component Bloo port myin out std_logic_vector 0 downto 0 myout in std_logic_vector 3 downto 0 F end component 12 34 strength specification The strength
53. TCL files When applied to Xilinx chips Handel C generates a a Netlist S INN www celoxica com Page 276 Handel C Language Reference Manual Celoxica Constraints File NCF These files are used by the place and route tools to constrain the relevant paths 12 16 Timing constraints example This example shows the use of the rate specification and the intime and outtime specifications to constrain a design for speed The use of these specifications causes the generation of a timing constraints file with the type of file determined by the target platform The design is constrained for a clock speed of 40MHz with input data from two sources taking a maximum of 5 5 and 5 0 nanoseconds and output data taking a maximum of 4 nanoseconds to transmit e A www celoxica com Page 277 Handel C Language Reference Manual Celoxica Clock set clock external C13 with rate 40 Data path width macro expr OpWidth 8 Data pins macro expr DatalnA 7D C5 Er 5 GG HO AS AO 5 Bo macro expr DatalnB 7 66 D7 Fo EO Go 4 Fo G10 FLO e macro expr DataOut Bl2 D12 D13 F13 G13 H13 H14 C14 Data In Out timing requirements macro expr InlimeRequirementA 5 5 macro expr InlimeRequirementB o0 macro expr OutTimeRequirement 4 Input data interface bus_in unsigned OpWidth dina DINA C with data DatalInA intime InlTimeRequirementA Pa interface bus_in unsigne
54. as in ANSI C It is used to access the members of a structure or mpram when the structure mpram is referenced through a pointer mpram Fred ram lt unsigned 8 gt ReadWritel256 Read write port rom lt unsigned 8 gt Read 256 Read only port Joan mpram Fred mpramPtr mpramPtr amp Joan x mpramPtr gt Read 56 If a memory is made up of structures the structure member operator can be used to reference structure members within the memory ram struct S compRAM 100 ram struct S ramStructPtr ramStructPtr amp compRAM x ramStructPtr l10 a S NN www celoxica com Page 117 Handel C Language Reference Manual Celoxica 7 Functions and macros 7 1 Functions and macros overview Handel C includes and extends the range of functions and macros offered by ANSI C Return Typed Called by Shared value return reference hardware values and parameters A Functions Can have Yes No Yes Arrays of functions Can have Yes No Yes Inline functions Can have Yes No No Preprocessor macros Can have No Yes No Macro expressions Must have No Yes No Shared expressions Must have No Yes Yes Macro procedures None No Yes No 7 1 1 Functions and macros language issues Called by reference or value Functions employ call by value on their parameters whereas macros effectively employ call by reference Consider the code void inline f_pseudoswap int 12 x int 12 y par S INN www celoxica com Page 118
55. be connected see below Generic interfaces If you have written a custom generic interface you will need to co simulate the interface with a model of the component to which it will be connected in hardware If you write the model in Handel C you can co simulate it with your Handel C interface using S INN www celoxica com Page 236 Handel C Language Reference Manual Celoxica dkconnect Oil To synchronize the simulations use dksync d11 If your model ts in VHDL or Verilog you can co simulate it with your Handel C design using the Co Simulation Bridge for ModelSim provided in the Platform Developer s Kit 11 3 Buses and the simulator The Handel C simulator cannot simulate buses directly because the simulation of buses cannot determine when input and output should occur The recommended process for debugging is For simple data use a channel or a chanin chanout to connect to a file This is the simplest method For more complex buses interfaces write a C C function and call it to bring in data This allows you to operate on the data or read it in a complex format This models functionality but not hardware To model buses accurately use the Plugin Library to write a plugin which can be co simulated This is precise and allows you to read I O signals using the Waveform Analyzer but can be slow and cumbersome Using preprocessor definitions By using the define and ifdef endif constructs of the preprocesso
56. bit selecthon cece ee cece eens 103 drop Operator EE 102 bitwise XOR EE 108 ClO Ci T E EE 162 __isfamily constnut 182 addition asssssssssesesnsnensrnrnrnnn 104 prefix and postfix operators 95 lt ESS d RER 106 lt Li keoperator sees 102 lt lt Shift opDerator eens 102 lt less than or eouall 106 lt gt type qualifier ccccceeeeeeees 72 L ssldpnrment eeeeeeeeees 81 Celoxica equal TO RE 106 gt greater than ccceeeeeeeeeeees 106 gt structure pointer operator 109 gt greater than or equal 106 gt gt Shift operator eee ees 102 de 286 292 AE 286 292 OW tee 286 291 SE Ee 286 291 dee Ee 286 291 B3BMHZ 2 2 286 293 B3BMHZ BON 286 293 G6MHZ D 286 290 abstract declaratore esesserererru 321 ACF TIOS eee ee 269 281 PCTS E 180 183 devices 180 183 on chip RAM 210 specifying reset pin 186 COICO EE 104 ell 276 EE 286 290 AGP I O standard 286 289 290 AGP 1X 286 AGP 2X 286 AIGOLILAIN LEE 22 178 debugging 22 178 ARNE a ME 180 183 211 devices 180 183 on chip RAM 211 ROMs 256 ampersand address operator 43 ANS E EE 15 25 calling from Handel C 65 compared to Handel C 15 25 Apex devices cece eeeee cece eee eeees 180 183 arithmetic operators 104 S NN www celoxica com Page 335 Handel C Language Reference Manual constraints files 281 I O standa
57. built Specification Possible values Default Applies to fifolength O or any positive A Channel integer 12 1 5 Channel and memory attributes This specification defines where memories and FIFOs are built Specification Possible values Default Applies to block AUTO for any AUTO memories device on chip BlockRAM for FIFOs of Actel two or LUT EAB more parts M512 M4K or M RAM for Altera BlocKRAM or SelectRAM for Xilinx 12 1 6 Memory attributes These specification defines how memories are built Celoxica Meaning Create FIFO of specified length Meaning Specify memory resource type to use for RAM ROM S INN www celoxica com Page 256 Handel C Language Reference Manual Specification offchip ports wegate westart welength rclkpos wclkpos clkpulselen clk addr oe we CS Possible Values 0 1 1 0 1 in multiples of 0 5 to clock division 0 5 in multiples of 0 5 to clock division in multiples of 0 5 to clock division 0 5 in multiples of 0 5 to clock division 0 5 in multiples of 0 5 to clock division Any valid pin list Any valid pin list Any valid pin list Any valid pin list Any valid pin list Default None None None None None None None None None None Applies to memories memories RAMs RAMs RAMs memories memories memories memories off chip memories off chip
58. can specify what type of memory you want to build by using the block specification Type of block specification memory M512 with block M512 M4K with block M4K M RAM with block M RAM S INN www celoxica com Page 216 Handel C Language Reference Manual Celoxica If you do not use the block specification the memory is set to AUTO and Quartus determines the most appropriate memory type when you place and route All Stratix memories are fully synchronous If you try to make them asynchronous for example by using the westart and welength specifications you will get a compiler error M RAM cannot be initialized This means that you cannot have a ROM built out of M RAM You will get a compiler error if you build a ROM using the with block M RAM specification M512 memory cannot be configured as a bi directional dual port MPRAM If you try to create this the compiler will issue a warning Example set family AlteraStratix Set part EP1S10B672C7 set clock external ram unsigned 8 autoRamL1l6 Let Quartus select a suitable memory structure ram unsigned 8 m512RamL16 with block M512 Use M512 blocks ram unsigned 8 m4kRamL16 with block M4k Use M4K blocks ram unsigned 8 mRamL1l6 with block M RAM Use M RAM blocks void main void autoRamLO 1 m512RamLO 1 m4kRamLO 1 mRamLO 1 tC J 10 3 4 Using on chip RAMs in Actel devices On
59. ccc cece eee ees 245 S INN www celoxica com Page 342 Handel C Language Reference Manual sie 20 BE 2 6 COICO eere E 274 on chip RAMS 180 210 211 212 operatorsl2 101 102 104 106 10 7 108 109 arithmetic 104 bit manipulation 101 bitwise logical 108 comparison 106 concatenation 102 conditional 109 drop 102 logical 107 precedence 12 relational 106 107 shift 102 Summary 12 take 102 trysema 92 width 104 optimizing code 123 154 157 examples 123 154 157 OUTS EE 269 EIERE 269 286 290 294 files 269 standards 286 290 294 Oouttime cece cece eee ee eee e ee eeeees 269 270 OVON cecdncestecuicurie a 29 overview of Handel C5 12 14 15 25 29 36 75 95 111 245 309 padding EE 29 38 102 Da aa E E EA 75 76 parallel 5 9 44 75 151 access to variables 151 branch synchronization 6 44 164 execution 75 functions 119 Celoxica programs statements structure parameterized macro expressions parameter ageet see ga functions macros Verilog paranoia PCI 1 O standard 33MHz 3 3V 33MHz 5 0V 66MHz 3 3V PCI X pin specifications omitting Din number attribute sllslel fC Specifying SE 218 231 232 264 constraining merging naming reset specifying tri state pipelining 00 eee 76 157 196 examples PLD d wvices eens pointers addresses casting declaration operations
60. celoxica com Page 209 Handel C Language Reference Manual Celoxica MPRAM Example 1 transform is performed void main void mpram ram unsigned 4 raxl1 4 ram unsigned 4 rax2 4 max with block 1 Static unsigned 2 il 12 unsigned 4 x x is Uun initialized unsigned 4 y y is un initialized interface bus_in unsigned 4 il I1 interface bus_out Ol unsigned 4 ol x interface bus_in unsigned 4 i2 I 2 interface bus_out 02 unsigned 4 02 y while 1 max raxlLil I1 il max rax2Li2 12 12 TEPE Lett x max raxlLil mpram port raxl only read into x y max rax2Lli2 mpram port rax2 only read into y S NN www celoxica com Page 210 Handel C Language Reference Manual Celoxica MPRAM Example 2 transform is not performed port rax2 does not read into a register void main void mpram ram unsigned 4 raxl1 4 ram unsigned 4 rax2 4 max with block 1 Static unsigned 2 il 12 unsigned 4 x x is un initialized interface bus_in unsigned 4 il I1 interface bus_out Ol unsigned 4 ol x interface bus_in unsigned 4 i2 12 port rax2 read directly into an interface not a pipeline register interface bus_out O2 unsigned 4 02 max rax2 i2 while 1 max raxlLil I1l il max rax2 i2 12 i2 EE ap Lett x max raxlLill mpram port raxl only read into x Targeting external synchronous RAMs Off chip synchronous SRAM
61. cette eeeeseeeeeneennes 29 3 6 9 Handel C v C memory allocaton ccc cece cece eee cece eeeeeeeeeeeeeeessennentenees 29 30 10 Hanael G V C standard OMAN y ere eene EEEE EA 29 3 6 11 C and Handel C types and objects eneruerrererrerererrrrererrererrrrrrerrrrerrrre 29 3 6 12 Expressions in C and Handel Ce 30 3 6 13 Statements in C and Handel C EEN 32 3 7 HANDEL C CONSTRUCTS NOT FOUND IN ANSI C suen enke Ka KN Ka KN Kn 32 A DECLARATIONS E 36 Bok INTRODUCTION TO feed 36 4 1 1 Handel C values and wid ths ccc cece ccc cece cece eee e eee eeeeeeeeeeeeneeaeeaneeneeaeens 36 4 1 2 String COMSUONUS EE 37 A eo OM gn oaa A A E EAA EE 37 AL LOIC wd EE 38 72 E EE 38 4 2 2 Signed unsigned SYNCAX cece cece cece eee eee n AREER ete teense enn b aba 39 4 2 3 Supported types for Dortimg 39 e Kat glate Wd EE 40 S INN www celoxica com Page 1 Handel C Language Reference Manual Celoxica e gt PAYS E 41 e Be ge ln ee 43 BEd SUC EE 43 74 ay 2 e EE 44 Ae BE E e EE 45 AS POINTER onoriano EAEE AEAEE 46 4 3 1 Pointers and addresses 2 0 cece cece cence cence eeeeeeeeeeeueeteueeeeueeteueeneueenaunes 48 4 er Me lte CECR ed ln e gl EEN 48 4 33 POmMters CO Mer a CES Ee 49 43 4 Structure vie Lu CN 49 4 3 5 address and indirection operatore cece cece cece eeeeeeeeeeeeeeeeeeeeeeeeeeeeneaes 50 AA ARCHITECTURAL TYPES EEN 51 TS CHANNEL EE 51 4 5 1 FIFO code example cccccccccee eee e cece ee eeeeeeeeeeeeeeeeeeeenaeeeeeeeeeeesegga
62. chip RAMs in Actel ProASIC and ProASIC devices use the embedded memory structures which are of a fixed width and depth These blocks can be combined to create deeper and wider memory spaces When writing Handel C programs you must be careful not to exceed the number of memory blocks in the target device or the design will not place and route successfully It is possible to use RAMs that do not match one of the width depth combinations but memory space may be wasted e A www celoxica com Page 217 Handel C Language Reference Manual Celoxica Synchronous and asynchronous access Memory blocks in ProASIC and ProASIC parts can be configured to be either synchronous or asynchronous If you do not apply any clock or write enable Specifications Handel C will create RAMs with a synchronous write port and asynchronous read port If you apply clock position specifications to the RAM the read and write ports will both be synchronous If you apply any of the write enable specifications westart welength or wegate to the RAM both write and read access will be asynchronous When declaring a memory as a MPRAM if you only apply write enable specifications to the read port AND you apply clock specifications to the write port you will get a compiler error aS you cannot have an asynchronous write port and a synchronous read port Initialization Actel memories may not be initialized 10 3 5 Using on chip RAMs in Altera devices EAB
63. complete statements to avoid tedious repetition while coding A single macro procedure can be expanded into a complex block of code It generates the hardware for the statement each time it is referenced The general syntax of macro procedures Is macro proc Name Params Statement Macros may be prototyped like functions This allows you to declare them in one file and use them in another A macro prototype consists of the name of the macro plus a list of the names of its parameters E g macro proc work x y www celoxica com Page 145 Handel C Language Reference Manual Celoxica If you have local or static declarations within the macro procedure a copy of the variable will be created for each copy of the macro Macro procedures that don t take any parameters require an empty parameter list For example macro proc MyMacro Example macro proc output x y d out x out y outputa D d outputla bD c d This example writes the two expressions a b and c d twice to the channel out This example also illustrates that the statement may be a code block in this case two instructions executed sequentially It expands to 4 channel output statements 7 3 12 Macro procedures compared to pre processor macros Macro procedures differ from preprocessor macros in that they are not simple text replacements The statement section of the definition must be a valid Handel C statement The following co
64. devices you can target The devices available to you are listed in the Family box on the Chip tab in Project Settings 10 2 1 Summary of supported devices In order to target a specific FPGA or PLD the compiler must be supplied with the part number Ultimately this information is passed to the place and route tool to inform it of the device it should target You can specify your target device using the Chip tab on the Project Settings dialog or within your source code Your license may restrict the devices you can target The devices available to you are visible in the Family list on the Chip tab Recognized families are Description On chip On chip synchronous asynchronous RAMs RAMs Actel ProASIC series Block RAM dual Block RAM dual port FPGAS port S INN www celoxica com Page 187 Handel C Language Reference Manual Celoxica Actel ProASIC series FPGAS Altera Apex 20K series PLDs Altera Apex 20KE series PLDs Altera Apex 20KC series PLDs Altera Apexll series PLDs Altera Cyclone PLDs Altera Cyclone II PLDs Altera Excalibur ARM series PLDs Altera Flex10K series PLDs Altera FlexLOKA series PLDs Altera FlexLOKB series PLDs Altera Flex1OKE series PLDs Altera Mercury series ASSPs Altera Stratix PLDs Altera Stratix GX PLDs Altera Stratix II PLDs Xilinx Spartan series FPGAS Xilinx Spartan XL series FPGAs Xilinx Spartan Il series FPGAS Xilinx Spartan IlE series FPGAs
65. do while loops and switch statements in similar circumstances for loops with no iteration step can also cause combinational loops S INN www celoxica com Page 156 Handel C Language Reference Manual Celoxica Further combinational loop code example Code may look correct but still include an empty loop For example while x 3 if y gt z att This if statement may take zero clock cycles to execute if y is not greater than z so even though this loop body does not look empty a combinational loop is still generated This is more obvious written as while x 3 if y gt z att else do nothing The solution is to add the else part of the if construct as follows while x 3 if y gt z att else delay e A www celoxica com Page 15 7 Handel C Language Reference Manual Celoxica 8 3 Parallel access to variables The rules of parallelism state that the same variable must not be accessed from two separate parallel branches This avoids resource conflicts on the variables The rule may be relaxed to state that the same variable must not be assigned to more than once on the same clock cycle but may be read as many times as required This gives powerful programming techniques For example par a b b a This code swaps the values of a and b in a single clock cycle Since exact execution time may be run time dependent the Handel C compiler cannot de
66. ensure that the body of a loop will always execute at least once or else provide an alternative execution point using an if else For example if you had the following ANSI C code while 71 0 MyFunction i The while loop would not be executed if i was equal to 0 You could re write this in Handel C as SEN if i 0 while i 0 MyFunction 1 sei else delay Note that you need to decrement i before you enter the while body to preserve the order dependency of the ANSI C code 3 6 7 Handel C v C unions If there is no relationship between members of the union you can use a struct instead If the members of the union are of related types e g int Tong and char you can reuse a single variable which is the width of the widest variable in the union For example if you have the following union in your C code union unsigned long ul unsigned char uc short ss Lu you could use a single variable of the same width as the long unsigned int 32 1 You could then get values equivalent to ul ss and ul by casting and using the take operator e A www celoxica com Page 28 Handel C Language Reference Manual Celoxica u ul would be written as i u uc would be written as i lt 8 u ss would be written as signed i lt 16 Note that in ANSI C there is no guarantee about whether ul uc and ss would share storage and so the Handel C code above might not exactly reproduce
67. for all variables that have not been assigned a specific width or declared as undefined This is done as follows set Intwidth 16 Int X unsigned int y S INN www celoxica com Page 40 Handel C Language Reference Manual Celoxica This declares a 16 bit wide signed integer x and a 16 bit wide unsigned integer y Any width may be used in the set intwidth instruction including undefined You can still declare variables that must have their width inferred by using the undefined keyword For example set clock external set intwidth 27 pl void main void unsigned x unsigned undefined y This example declares a variable x with a width of 27 bits and a variable y that has its width inferred by the compiler This example also illustrates that the int keyword may be omitted when declaring unsigned integers You may also set the default width to be undefined set intwidth undefined 4 2 5 Arrays You can declare arrays of variables in the same way that arrays are declared in conventional C For example int X 7 This declares 7 registers each of which is 6 bits wide Accessing the variables is exactly as in conventional C For example to access the fifth variable in the array xL4 1 Note that as in conventional C the first variable has an index of 0 and the last has an index of n 1 where n is the total number of variables in the array When a variable is used as an array index
68. for loop may be executed zero or more times according to the results of the condition test There is a direct correspondence between for loops and while loops Because of the benefits of parallelism it is nearly always preferable to implement a while loop instead for Init Test Inc Body is directly equivalent to e A www celoxica com Page 93 Handel C Language Reference Manual Celoxica Init while Test Body Lic unless the Body includes a continue statement In a for loop continue jumps to before the increment in a while loop continue jumps to after the increment Unless a specific continue statement is needed it is always faster to implement the for loop as a while loop with the Body and Inc steps in parallel rather than in sequence when this is possible Each of the initialization test and iteration statements is optional and may be omitted if not required Note that for loops with no iteration step can cause combinational loops As with all other Handel C constructs Statement may be replaced with a block of Statements For example FOr Z zs Key 2 K a b c Or The difference between a conventional C for loop and the Handel C version is in the initialization and iteration phases In conventional C these two fields contain expressions and by using expression side effects such as and and the sequential operator conventional C allows complex operations to be performed Since H
69. function addeven checks whether the sum of two numbers is even Similar checks are carried out by minuseven difference of two numbers diveven division and modeven modulus The function check simply calls the function whose pointer it receives with the arguments it receives This gives a consistent interface to the xxxeven oo Y www celoxica com Page 132 Handel C Language Reference Manual Celoxica functions Pay close attention to the declaration of check and of function pointer p The parentheses around p and chk in the declaration of check are necessary for the compiler to make the correct interpretation Possible code optimization Inside the main program body check was called like this check amp m amp n p It could have been written like this check amp m amp n xXxxeven eliminating the need for an additional pointer variable Here is the main section written using this form of expression TH www celoxica com Page 133 Handel C Language Reference Manual Celoxica void main void short int m n unsigned 2 choice unsigned 1 result par m 19 Switch choice case 0 result check amp m amp n amp addeven break case l result check amp m amp n amp multeven break case 2 result check amp m amp n amp diveven break case 3 result check amp m amp n amp modeven break default break choicet while choice 7 2 8 Simultaneo
70. functions For example a printf function would take at least one clock cycle even if the return value is ignored and a C function with a body that takes 0 clock cycles and a void return type would not take any clock cycles Examples extern C int printf const char format declares printf with C linkage extern C int 14 x declares a variable x with C linkage extern C remove Microsoft specific extensions from the header file define cdecl include lt stdio h gt causes everything in stdio h to have C linkage Mapping of types to C C Handel C types will be mapped to C C types in the following way when inside an extern language construct Se www celoxica com Page 73 Handel C Language Reference Manual Celoxica Handel C type C C type char char short short long long int int only valid within an extern language construct int width Int lt width gt C only unsigned int width UInt lt width gt C only struct struct type ram n convertedTypeLn type rom n convertedTypeLn Others Generate an error Mapping of types outside extern Mapping of types outside the extern language construct is the same except signed and unsigned ints must have a specified width When outside an extern language construct an int without a specified width will generate an error For example the following Handel C extern GC int printf Ceonst cha
71. held constant during the write strobe It is held constant by the two assignments to Dummy CLK Dummy x 3 3 Data Dummy x 3 Undivided external clock This method of accessing asynchronous RAMs is a compromise between the other two methods fast external clock and multiple RAM accesses wegate is used with an undivided external clock and keeps the write strobe in the first or second half of the clock cycle It is still necessary to hold the address constant either in the clock cycle before or in the clock cycle after the access For example ram unsigned 6 x 34 with wegate 1 xL3 Data Dummy x 3 This places the write strobe in the second half of the clock cycle use a value of 1 to put it in the first half and holds the address for the clock cycle after the write The RAM therefore has half a clock cycle of set up time and one clock cycle of hold time on its address lines wegate example The wegate specification may be used when a divided clock is not available For example to declare a 16Kbyte by 8 bit RAM S INN www celoxica com Page 197 Handel C Language Reference Manual Celoxica ram unsigned 8 ExtRAM 16384 with offchip 1 wegate l data P1 P2 P3 P4 hos POs PA IO y addr P9 P10 P11 P12 PSs PIA PL PI RK Ee Ee EN A eee 4 PIT SPE we P23 oe P24 CS 4 75 The compiled hardware generates
72. is known as passing by reference Architectural types hardware constructs must be passed by reference a pointer to or address of the construct The only architectural type that can be passed to or returned by a function by value is a signal All others and structures containing them must be passed by reference Arrays and functions can also only be passed by reference e A www celoxica com Page 124 Handel C Language Reference Manual Celoxica 7 2 1 Function definitions and declarations Function definitions and declarations are defined as in ANSI C Functions must be declared in every file that they are used in though they should only be defined once It is common to put function declarations into a header file and include that in every file where they are used Function definition The definition of a function consists of its name and parameters followed by the function body the block of code that it performs when it is called The syntax Is returnlType Name parameterList declarations statements For example int 4 add int 4 left int 4 right int 4 sum Sum left right return sum If there is nothing returned from the function a void return type must be specified Old style ANSI C function definitions where the types of the parameters are specified between the parameter list and the function body are not supported For example int 4 add left right old style not supported
73. is seen in this example w width x 4 y Z The example generates hardware to compare the width of the variable x with 4 and set w to the value of y or z depending on whether this value is equal to 4 or not This is probably not what was intended because both width x and 4 are constants What was probably intended was for the compiler to check whether the width of x was 4 and then simply replace the whole expression above with y or z according to the value This can be written as follows w select width x 4 y Z In this example the compiler evaluates the first expression and replaces the whole line with either w y or w z No hardware for the conditional is generated Combining with macros This is more useful when macros are combined with this feature S INN www celoxica com Page 138 Handel C Language Reference Manual Celoxica macro expr adjust x n Sselect width x lt n 0 x x lt n unsigned 4 a unsigned 5 b unsigned 6 C b adjust a width b b adjust c width b This example is for a macro that equalizes widths of variables in an assignment If the right hand side of an assignment is narrower than the left hand side then the right hand side must be padded with zeros in its most significant bits If the right hand side is wider than the left hand side the least significant bits of the right hand side must be taken and assigned to the left hand side The select
74. long path through all these if statements can be split at the expense of having each if statement take one clock cycle whether the condition is true or not 8 5 2 Pipelining A classic way to increase clock rates in hardware is to pipeline A pipelined circuit takes more than one clock cycle to calculate any result but can produce one result every clock cycle The trade off is an increased latency for a higher throughput so pipelining is only effective if there is a large quantity of data to be processed it is not practical for single calculations S INN www celoxica com Page 164 Handel C Language Reference Manual Celoxica Pipelined multiplier example unsigned 8 sum 8 unsigned 8 aL 8 unsigned 8 b 8 ina dat is a data file You must provide your own chanin inputa with infile ina dat chanin inputb with infile ina dat chanout output with outfile out dat par while 1 inputa a 0 while 1 inputb b 0 while 1 op tput A sumi while 1 par macro proc level x par sum x sumLx 1 a x 0 0 0 bLx alx aLx 1 gt gt 1 b x b x 1 lt lt 1 sumLO aLOJLO 0 O bL O par i l i lt i level i www celoxica com Page 165 Handel C Language Reference Manual Celoxica This multiplier calculates the 8 LSBs of the result of an 8 bit by 8 bit multiply using long multiplication The multiplier pro
75. other words pointer chp now points to variable cha The third line simply assigns a value to HE www celoxica com Page 50 Handel C Language Reference Manual Celoxica cha The fourth line dereferences pointer chp to access what it s pointing to which is cha In other words chb is assigned the value of the object pointed to by chp The last line assigns the address of chb to pointer chp In other words pointer chp now points to variable chb Example pointer to pointer assignment struct S d int 6 a b F Si Scy FSD Spp sp Asil Spp asp si spp This declares two variables of type struct S sl and s2 a pointer to a variable of this type sp and a pointer to a pointer to a variable of this type spp The next line assigns the address of structure s1 to pointer sp pointer sp to point to structure s1 The following line assigns the address of pointer sp to pointer spp pointer spp to point to pointer sp The last line dereferences pointer spp twice and it assigns the dereferenced value which is s1 to structure s2 i e s2 now equals s1 4 4 Architectural types The architectural types are e channels used to communicate between parallel processes e interfaces used to connect to pins or provide signals to communicate with external code e memories rom ram wom and mpram e signal declares a wire The type clarifier lt gt has been provided to help clarify the definitions of memories
76. parallel Handel C parallelism is true parallelism not the time sliced parallelism familiar from general purpose computers When instructed to execute two instructions in parallel S INN www celoxica com Page 12 Handel C Language Reference Manual Celoxica those two instructions will be executed at exactly the same instant in time by two separate pieces of hardware When a parallel block is encountered execution flow splits at the start of the parallel block and each branch of the block executes simultaneously Execution flow then re joins at the end of the block when all branches have completed Any branches that complete early are forced to wait for the slowest branch before continuing Statement Parallel Block This diagram illustrates the branching and re joining of the execution flow The left hand and middle branches must wait to ensure that all branches have completed before the instruction following the parallel construct can be executed 2 1 3 Channel communication Channels provide a link between branches executing in parallel One parallel branch outputs data onto the channel and the other branch reads data from the channel Channels can be constructed with and without FIFO capacities e Channels constructed as FIFOs A channel can be constructed as a FIFO queue In this case the data is written to the head of the FIFO and is read from the tail If the FIFO is full a write blocks until an element is read from
77. parallel composition keyword par to allow statements in a block to be executed in parallel Three assignments that execute in parallel and in the same clock cycle par 1 2 Zz 3 Three assignments that execute sequentially requiring three clock cycles fae Zz 3 The par example executes all assignments literally in parallel Three specific pieces of hardware are built to perform these three assignments This is about the same amount as is needed to execute the assignments sequentially Sequential branches Within parallel blocks of code sequential branches can be added by using a code block denoted with the brackets instead of a single statement For example par x 1 Tai Zz 3 In this example the first branch of the parallel statement executes the assignment to x while the second branch sequentially executes the assignments to y and z The assignments to x and y occur in the same clock cycle the assignment to z occurs in the next clock cycle e A www celoxica com Page 82 Handel C Language Reference Manual Celoxica ES The instruction following the par will not be executed until all branches of the parallel block complete 5 2 seq To allow replication the seq keyword exists Sequential statements can be written with or without the keyword The following example executes three assignments sequentially x 1 y 2 Z 3 as does this seq x 1
78. pin set clock external C1 with standard HSTL_III dci l 12 11 extinst extlib extfunc specifications The extlib extfunc and extinst specifications are used when connecting a Handel C interface to a simulation d 1 There is a default value for extfunc but extlib and extinst must both be specified S INN www celoxica com Page 273 Handel C Language Reference Manual Celoxica Specification Possible Default Meaning values extlib Name of a None Specify external plugin for simulator plugin dl extfunc Name of a PlugInSet or Specify external function within the function within PlugInGet simulator for this port the plugin depending on port direction extinst Instance name None Specify simulation instance used with optional parameters extlib extlib takes the name of a dl It specifies that the named d11 plugin will be connected to the port or interface extfunc extfunc specifies the name of an external function within the d11 On output ports this function is called by the simulator to pass data from the Handel C simulator to the plugin default PlugInSet It is guaranteed to be called every time the value on the port changes but may be called more often than that On input ports this function is called by the simulator to get data from the plugin default PlugInGet It is guaranteed to be called at least once every clock cycle extinst extinst takes a string which is passed to the PlugInOpenInstanc
79. section of the Celoxica web site 3 6 11 C and Handel C types and objects e A www celoxica com Page 29 Handel C Language Reference Manual In both Conventional Handel C C only only int double chan unsigned float ram char union rom long wom Short mpram enum Signal register chanin Static chanout extern undefined struct interface volatile lt gt void inline const typeof auto signed typedef Celoxica 3 6 12 Expressions in C and Handel C S INN www celoxica com Page 30 Handel C Language Reference Manual Celoxica In both Conventional Handel C C only only pointer sizeof select indirection amp address of width wA lt multiplication J Iert 2m lt lt gt gt gt lt gt lt amp bitwise and A www celoxica com Page 31 Handel C Language Reference Manual Celoxica 3 6 13 Statements in C and Handel C In both Handel C only ez par Switch delay do while while if else prialt Tor 32 seq break 1fselect continue return goto assert assert is an expression in Handel C and not the same as in ANSI C 3 7 Handel C constructs not found in ANSI C Handel C is designed to target hardware It allows you to specify timing and to target components such as memory ports buses and wires One of the most important differences to ANSI C is the ability to create code that executes in parallel Handel C constructs
80. that are not found in ANSI C are listed below Parallelism The par keyword specifies that a block of code should execute in parallel Each statement within the block is executed in the same clock cycle If the par keyword is not used statements within a code block are executed sequentially You can use the seq keyword to make this more explicit Channels allow communication between parallel branches of code They are specified using the chan keyword or by chanin and chanout when you are simulating code You can read from and write to channels using statements of the form Channel Variable reads from a channel Channel Expression writes to a channel prialt statements are used with multiple channels to select the first one that is ready for a read or write Semaphores sema allow you to coordinate the use of resources that are shared between parallel branches of code The trysema construct tests to see if the sema is owned e A www celoxica com Page 32 Handel C Language Reference Manual Celoxica The releasesema construct frees a semaphore once it is no longer needed by a resource inline functions arrays of functions macro procedures and macro expressions help you to create multiple copies of functions You need copies of a function if it is to be accessed by parallel branches of code Timing The set clock construct specifies the clock source for each main function You can have more than one clock int
81. that have their own specification For example interface Bloo unsigned 4 in InstBloo unsigned 4 out x with busformat BI with busformat B I first port has spec B I and second port has spec BI If you want to apply a busformat specification to a 1 bit wide bus you need to place the specification after the port If the specification is applied to the whole interface it will be ignored for any 1 bit wide buses in the interface to enable these to be used as signals etc Examples interface port_in int 4 signals_to_HC with busformat BLI read creates four ports named signals_to_HCL0O signals_to_HCL1 signals_to_HCL2 and signals _to_HC 3 interface port_in unsigned 6 myvar MyFunction with busformat B N 0 creates a single 6 bit port myvar 5 0 S INN www celoxica com Page 267 Handel C Language Reference Manual Celoxica unsigned 6 x interface ExtThing unsigned 6 myvar InstlExt Thing unsigned 6 anothervar x with busformat B N 0 creates two ports myvar 5 0 and anothervar 5 0 interface ExtThing unsigned 5 a unsigned 1 b with busformat B I unsigned 1 c InstExtThing unsigned 6 d with busformat B I In this example the busformat specification is applied to ports a and d because they are more than 1 bit wide and to port b as this has an individual busformat specification but not to port c as this is 1 bit wide and does not have an indivi
82. the FIFO If the FIFO is empty a read blocks until there is data ready to be read e Channels constructed without FIFO capacity These channels provide synchronization between parallel branches because the data transfer can only complete when both the transmitter and the receiver are ready If one side is not ready the other must wait S INN www celoxica com Page 13 Handel C Language Reference Manual Celoxica Channel synchronization ota tement Channel SYNCHRONIZATION OF NORMAL CHANNELS Here the channel is shown transferring data from the left branch to the right branch If the left branch reaches point a before the right branch reaches point b the left branch waits at point a until the right branch reaches point b Communication without synchronization If you are using a channel FIFO the left branch will not have to wait at point aif there is Space in the FIFO Instead it can write to the FIFO once per clock tick until the FIFO is full Only then will it have to wait Each time the right branch reads from the FIFO at point b the data at the head of the FIFO is read and the next piece of data becomes the head The right branch must wait if the FIFO is empty A In this case the two branches will not be synchronized after every read and write www celoxica com Page 14 Handel C Language Reference Manual Celoxica 2 1 4 Scope and variable sharing The scope of declarations is based around cod
83. the location specified at Addr will be read e At time t4 the main Handel C clock rising edge clocks the memory as well as Initiating the next read cycle e At event e4 after the read operation has completed the data that has been read becomes available at the output from the memory Dout e At time t5 the data that was read DO in this case is ready to be clocked into its destination Two further read cycles are performed starting at time t4 and t5 Effect of performing a pipelining transform The output from the pipeline register Rout in the non pipelined version and the output from the memory Dout in the pipelined version are equivalent showing that the transformation does not change the overall behaviour of the circuit Valid data is available from the memory output one whole clock cycle later in the pipelined version which is why the transform is only valid when there s a pipeline register Pipelined SSRAM examples The following examples demonstrate how you can pipeline accesses to on chip SSRAM see page 203 If the correct conditions are met the RAM will use the main Handel C clock instead of an inverted clock and the output register will be removed S INN www celoxica com Page 207 Handel C Language Reference Manual Celoxica SPRAM Example 1 transform is performed void main void ram unsigned 4 raxL4 with block BlockRAM Static unsigned 2 1 unsigned 4 x x is UNn initialized inte
84. the target device or the design will not place and route successfully 10 3 7 Using external ROMs An external ROM is declared as an external RAM with an empty write enable pin list For example S INN www celoxica com Page 219 Handel C Language Reference Manual Celoxica ram unsigned 8 ExtROM 16384 with OTT Cn p 1 dais Sp pe Poe a Po POs Pr RO Ps addr P9 P10 P11 P12 Plos Plae Plo s PO PIZ s PIS Peo P207 lg E E we oe P24 C6 E Note that no westart welength or wegate specification is required since there is no write strobe signal on a ROM device 10 3 8 Connecting to RAMs in foreign code You can create ports to connect to a RAM by using the ports 1 specification to your memory definition This will generate VHDL Verilog or EDIF wires which can be connected to a component created elsewhere The ports specification cannot be used in conjunction with the offchip 1 specification but all other specifications will apply The interface generated will have separate read output and write data ports write enable data enable and clock wires This ensures that it can be connected to any device Pin names provided in the addr data cs we oe and clk specifications will be passed through to the generated EDIF They are not passed through to VHDL or Verilog since VHDL and Verilog interfaces are generated as n bit wide buses rather than n
85. to return to its initial state and resets global and static variables to their initial values However it does not reset any RAMs distributed or block By default the reset is asynchronous and thus occurs immediately it does not wait for the next clock tick To make the global reset synchronous use the synchronous specification Examples Signal unsigned 1 x set reset internal x resets when x 1S zero set reset external Pl resets when signal sent to named pin set reset external connects to pin but doesn t specify which 10 3 Use of RAMs and ROMs with Handel C Handel C provides support for e interfacing to on chip and off chip RAMs and ROMs using the ram and rom keywords e specifying RAMs and ROMs external to the Handel C code by using the ports specification keyword e controlling the timing for read write cycles by using specification keywords that define the relationship between the RAM strobe and the Handel C clock The usual technique for specifying timing in synchronous and asynchronous RAM is to have a fast external clock which is divided down to provide the Handel C clock and used directly to provide the pulses to the RAM HE www celoxica com Page 193 Handel C Language Reference Manual Celoxica 10 3 1 Asynchronous RAMs There are three techniques for timing asynchronous RAMs depending on the clock available e Fast external clock Use the Handel C westart and welength specificat
86. unconstrainedperiod specification The unconstrainedperiod specification gives the maximum period in nanoseconds on channel control paths between clock domains If this specification is not used the place and route tools may generate a warning for affected paths crossing the clock domain Clock A Clock B ee bes cr unconstrainedperiod i resolution time tres Be minperiod S INN www celoxica com Page 304 Handel C Language Reference Manual Celoxica If the specification is used it applies to unconstrained paths into the clock domain The diagram below shows where it is used Clock A Clock B Channel t Synchronisers Ti MES WITH PARANOIA AT ITS DEFAULT OF 1 t time to transfer between domains paranoia 1 xt t unconstrained period ta Minperiod t clock period set clock external with unconstrained period 10 12 37 vhdl_ type specification The vhdl_type specification may be given to port_in port_out or generic interfaces to specify the type of a port in VHDL Valid string values of this specification are unsigned signed std logic std_logic_vector The default type of a port is std_logic tf the port is 1 bit wide unsigned otherwise You can apply the vhd _type specification to individual ports If you place the specification at the end of the interface statement it will be applied to all the ports Ei The vhdl_type specification replaces the deprecated std_l
87. used to drive a clock in the Handel C design This is useful when the clock for the Handel C design originates in an external black box component For example e A www celoxica com Page 269 Handel C Language Reference Manual Celoxica unsigned 1 En interface BlackBox unsigned 1 CLK with clockport 1 Instance unsigned 1 Enable En set clock internal Instance CLk ES If you don t use the clockport specification you may end up with combinational loops Clock declaration You can use the clockport specification with clockport 1 when declaring external clocks to assign the clock to a dedicated clock input resource on the target device If you apply the clockport specification to Xilinx Virtex parts you can use it to specify a particular input clock buffer If clockport is set to 0 the clock is assigned to a pin that is not a dedicated clock input and the I O standard and dci specifications are not available Example clock declarations set family XilinxVirtexII set clock external with standard LVCMOS33 dci 1 OR set family XilinxVirtexII set clock external with clockport 1 standard LVCMOS33 dci 1 both instruct the compiler to build an external clock interface using a dedicated Virtex clock input IBUFG resource That is the clock interface logic built will be Handel C clock Pin IDUIEG BUF G Standard LYCMOS33 dc 1 set family XilinxVirtexII set clock ex
88. user defined interface to an existing VHDL or Verilog code block When the bind specification is 0 the properties specification is used to define attributes for black boxes Properties are specified as a list of property items where each item comprises two or three values property_name property_value property_type e property_name is a string e property_value can be a String or an integer e property_type is optional with 3 possible values all strings integer boolean or string If your property is a boolean you need to specify O false or 1 true as the property value and specify boolean as the type If your property is an integer or string the type can be inferred from the property value and you do not need to specify it Compiler warnings are issued if illegal values are entered or if there is a mismatch between the property type and property value EDIF Example unsigned 6 x interface ExtThing unsigned 6 myvar InstlExtThing unsigned 6 anothervar x with properties LPM_TYPE LPM_RAM_DQ LPM_WIDTH 6 integer busformat B N 0 This interface will generate an EDIF block with the following EDIF properties LPM_TYPE and LPM_WIDTH S INN www celoxica com Page 285 Handel C Language Reference Manual Celoxica VHDL Verilog example bind 1 interface ExtThing unsigned 6 myvar InstlExt Thing unsigned 6 anothervar x with bind 1 properties propl
89. variables i e those declared outside all code blocks may be initialized with their declaration For example static int 15 x 1234 Static int 7 y 45 with outfile out dat Variables declared within functions or macros can only be initialized if they have static storage or are consts Global and static variables may only be initialized with constants If you do not initialize them they will have a default value of zero If you use the set reset construct variables will be reset to their initial values If you use the try reset construct variables will not be re initialized e A www celoxica com Page 80 Handel C Language Reference Manual Celoxica All other variables Local non static variables have no default initial value You cannot initialize them Instead you must use an explicit sequential or parallel list of assignments following your declarations to achieve the same effect For example int 4 x unsigned 5 y x b Simulation In simulation variables including static variables inside functions are initialized before the simulation run begins i e before the first clock cycle is simulated S INN www celoxica com Page 81 Handel C Language Reference Manual Celoxica 5 Statements 5 1 Sequential and parallel execution Handel C implicitly executes instructions sequentially When targeting hardware it is extremely important to use parallelism For this reason Handel C has a
90. will run from 400 to 403 Joan Read 100 will run from 800 to 807 Joan Read 50 will run from 400 to 407 Joan ReadWrite 100 is equivalent to Joan Read 50 0 3 Apexl bit mapping To find the bits that an array element occupies in an Apexll RAM you can use the formula RAM array ram y NameLa will have a start bit of y a 1 1 and an end bit of y a Apexll mapping is little endian This means that the address points to the LSB The bits between the declarations of RAM are mapped directly across so that bit 27 in one declaration will have the same value as bit 27 in another declaration even though the bits may be in different array elements in the different declarations mpram Joan ram lt unsigned 4 gt ReadWritelL256 Read write port rom lt unsigned 8 gt Read 256 Read only port Joan ReadWrite 100 will run from 400 to 403 Joan Read 100 will run from 800 to 807 Joan Read 50 will run from 400 to 407 Joan ReadWrite 100 is equivalent to Joan Read 50 0 3 e A www celoxica com Page 67 Handel C Language Reference Manual Celoxica 4 8 3 mprams example Using an mpram to communicate between two independent logic blocks File 1 moram Fred ram lt unsigned 8 gt ReadWritelL256 Read write port rom lt unsigned 8 gt Read 256 Read only port J3 mpram Fred Joan Declare Joan as an mpram like Fred set clock internal F8M void main void unsigned 8 data Joan
91. y 6 5 Bit manipulation operators The following bit manipulation operators are provided in Handel C lt lt Shift left gt gt Shift right lt Take least significant bits Drop least significant bits Concatenate bits J Bit selection width Expression Width of expression Se www celoxica com Page 108 Handel C Language Reference Manual Celoxica 6 5 1 Shift operators The shift operators shift a value left or right by a variable number of bits resulting in a value of the same width as the value being shifted Any bits shifted outside this width are lost When shifting unsigned values the right shift pads the upper bits with zeros When right shifting signed values the upper bits are copies of the top bit of the original value Thus a shift right by 1 divides the value by 2 and preserves the sign For example Static unsigned 4 a 0b1101 Static unsigned log2ceil width a 1 b 2 a a gt gt b a becomes 0b0011 e 3 a a gt gt b a becomes 0b0001 The width of b needs to have a width equal to 10g2 width a 1 rounded up to the nearest whole number This can be calculated using the og2ceil macro which is provided as part of the standard library in the Platform Developer s Kit 6 5 2 Take drop operators The take operator lt returns the n least significant bits of a value The drop operator returns all but the n least significant bits of a value n must be a compile tim
92. 00 While OOPS cece cece cece eee eeeees 85 86 Lee EE 17 29 33 104 adjustment 17 102 inference 33 of variables 17 29 operator 104 WSS reeled are cesses 63 243 naming 243 KREIS Seet eebe e 245 WOM write only memory ports 57 62 WOVKK ee EE 254 write enable 008 187 193 300 asynchronous RAM 187 300 positioning 300 synchronous RAM 193 We SODE tee eege dE eege 187 write Only Memory cceeee scene eens 62 writing to external PINs 065 221 PMX EE 180 183 212 bit mapping 59 block specification 256 devices 180 183 on chip RAM 212 ZBT compatible devices 065 193 S INN www celoxica com Page 348
93. 1 etc qi14 ql13 out ql14 e A www celoxica com Page 84 Handel C Language Reference Manual Celoxica 5 4 prialt The prialt statement selects the first channel ready to communicate from a list of channel cases The syntax is similar to a conventional C switch statement prialt case CommsStatement Statement break case CommsStatement Statement break default Statement break prialt selects between the communications on several channels depending on the readiness of the other end of the channel CommsStatement must be one of the following Channel Variable Channel Expression The case whose communication statement is the first to be ready to transfer data will execute and data will be transferred over the channel The statements up to the next break statement will then be executed If no channel is ready within a given clock tick the default clause will be executed if one is present Priority If two channels are ready simultaneously then the first one listed in the code takes priority Default prialt with no default case execution halts until one of the channels becomes ready to communicate prialt statement with default case if none of the channels is ready to communicate immediately then the default branch statements executes and the prialt statement terminates S INN www celoxica com Page 85 Handel C Language Reference Manual Celoxica Restrictions
94. 1 bit wide wires This means that it is ambiguous to specify a separate identifier for each wire If they are used when compiling to VHDL or Verilog the compiler issues a warning For VHDL or Verilog output the compiler generates meaningful port names For example with the following RAM declaration compiled to VHDL ram unsigned 4 rax 4 with ports 1 data dataPins addr addrPins we wePins cS csPins oe oePins the compiler will warn that all the pins specifications have been ignored and will generate an interface in VHDL with the following ports S INN www celoxica com Page 220 Handel C Language Reference Manual Celoxica component rax_SPPort port rax_SPPort_addr in unsigned l downto 0 rax_SPPort_clk in std_logic rax_SPPort_cs in std_logic rax_SPPort_data_en in std_logic rax_SPPort_data_in out unsigned 3 downto 0 rax SPPort data out in unsigned 3 downto UI rax_SPPort_oe in std_logic rax_SPPort_we in std_logic The port names consist of the memory name rax in this case description of the memory type SPPort single port in this case and an identifier describing the ports function A clock port will always be generated If you use the ports specification with an MPRAM a separate interface will be generated for each port Generating an interface to a foreign code RAM set family X1linxVirtex set part V1000BG5600 4 set clock external C1 unsigned 4 a ram
95. 2 11 EXTI NST EXTLI B EXTFUNC SPECIFICATIONS nn en a KK a KR KN KR KN KN Kn 273 12 12 EXTPATH SPECI FICATION WE 275 12 13 FIFOLENGTH SPECIEICATION wn un vn ka KR Ka KR KE KN KEREN KEE E KE KN KEREN KEE EN Ku 275 12 14 INFILE AND OUTFILE SPECIEICATIONS wun un en Kn Kn KN KK EN KEEN KR KN KK EN Ku 276 12 15 INTIME AND OUTTI ME SPECIFICATIONS nenn KK EN KEN KR KN KR KN KN KEN Kn 276 12 16 TIMING CONSTRAINTS EXAMPLE wenn sn KN KK KN KEREN KEN KR KN KEREN KK EN Ku 277 12 17 MINPERIOD SPECIFICATION un un KK a KR KA KR KN KN KEREN KEE E KN KN KEREN KEE EN Ku 280 12 18 OFFCHIP SPECIFI CATION ssssssnnnnnnunnnnnnnunnnnnnnnunnnnnnnnnnnnnnnnnnnnnnn 281 12 19 PARANOIA SPECIFICATION wen un KK a KR KN KR KN KN KEREN KREE KN KN KEREN KEE EN Ku 282 12 20 PIN SEELEN 283 12 21 PORTS SPECIFICATION EG 284 12 22 PROPERTIES SPECIFI CATION sssssnsssuuu22220uuu222200uu2222uuuunnnnnnnnnnnnn 285 12 23 PULL SPECIFICATION ege 287 S INN www celoxica com Page 6 Handel C Language Reference Manual i L Celoxica 12 24 QUARTUS PROJ ASSIGN SPECIFICATION see E KEE KEE KEE 288 12 25 RATE SPECIFICATION WEE 288 12 26 RCLKPOS WCLKPOS AND CLKPULSELEN SPECIFICATIONS SSRAM Tl MAING BE 289 12 27 RESOLUTI ONTI ME SbPECIEICATION ounen u a KN KR KEEN E EN KR KEEN E ER KEEN ENN 291 12 28 RETI ME SPECIEICATION un enen a a KN KR KEEN EN KN ER ER ENKEN ER KEEN KN KN ER KEEN ENN 291 12 29 SC_ TYPE SPECIFICATION unenee RRE EE KEE KEE KEE KEE 292 12 30 SHOW SPEC FICATION WEE
96. 82 CONVETS ON EE 17 96 97 Ee 2 6 SS BN 286 290 CTT I O standard 286 289 290 current ClOCK EE 162 Cyclone devices cece eees 183 209 constraints files 281 I O standards supported 289 296 mprams 57 59 pull up resistors 280 RAMs 211 targeting embedded memory 209 6 Gc Leen ee eee 22 178 Celoxica file format 178 input and output 22 data Specification ccceeeee eens 264 dci specification cece cece cece eee eens 265 DDR ee 193 DUG REES 99 assertions 99 CEG II EE 30 declarations 118 320 disambiguating 72 functions 118 interfaces 49 mpram 57 RAM 54 ROM 54 syntax 320 declaratorS sesesererererererrrrrrrrrrrns 320 Cefault cccccccceeeeeeeeeeeeeeeeeeees 78 88 defining the cdock cece cece eee 160 al Seen ee ere ee ere 90 141 147 device specClflere cece cece eee eeee eens 183 devices aen 179 180 182 183 218 detecting current device 182 external 218 specifying 183 differential bereed ee ee 294 differential I O standards 294 Digital Controlled Impedance 265 dsambguator ccc cece ee eeeeeeeeeeeees 72 GIN ISO HEEN 104 AG x5 EE 86 89 does not eoual 106 domaine 162 168 172 channel timing 168 multiple clocks 162 172 COU DIG orner torier AEE 16 309 drop Operator EE 102 S INN www celoxica com Page 338 Handel C Language Reference Manual SE 180 211 256 EDIF ere ee er re arene eee 243 259 buses 259 wire names 243 CINCIGNCY
97. A Handel C interface definition consists of an interface sort an instance name and data ports together with information about each port The definition defines a single instance of an interface sort If you want to define multiple instances or use forward references to the interface declare the interface and then make multiple definitions of that interface sort You do not need to declare interfaces of predefined sorts The general format of an interface definition is interface Sort ports_in_to_Handel C InstanceName ports_out_from_Handel C with GeneralSpecs S INN www celoxica com Page 57 Handel C Language Reference Manual Celoxica Sort Pre defined interface sort or used defined sort This Should match the sort in the interface declaration if you are using one ports_in_to_Handel C Definitions of one or more ports bringing data into the Handel C code Port definitions are described below InstanceName User defined identifier for that instance of the interface You can define any number of instances of an interface sort if you make a declaration of the interface sort ports_out_from_Handel C Definitions of one or more ports sending data from the Handel C code Each output port should be assigned an expression The value of the expression will be connected to that port General Specs Handel C interface specifications These specify hardware details of the interface such as chip pin numbers or a
98. CI 33 MHz 5 0 V 5 0 Volt PCI Some Xilinx devices may be configured in this mode an extension of the 3 3 Volt PCI Standard which makes them 5V tolerant No Altera devices currently support this mode PCI X The PCI X standard is an enhanced version of the PCI standard that can support higher average bandwidth and has more stringent requirements SSTL2 Stub Series Terminated Logic for 2 5 V The SSTL2 standard specified by JEDEC Standard J ESD 8 9 Stub Series Terminated Logic for 2 5 Volts SSTL 2 is a general purpose 2 5 V memory bus standard sponsored by Hitachi and IBM This is a voltage referenced standard and has two variations or classes both of which require a reference voltage of 1 25 V an input output source voltage of 2 5 V and a termination voltage of 1 25 V This standard requires a Differential Amplifier input buffer and a Push Pull output buffer SSTL2 is used for high speed SDRAM interfaces e A www celoxica com Page 300 Handel C Language Reference Manual Celoxica SSTL3 Stub Series Terminated Logic for 3 3 V The SSTL2 standard specified by JEDEC Standard J ESD 8 8 Stub Series Terminated Logic for 3 3 Volts SSTL 3 is a general purpose 3 3 V memory bus standard sponsored by Hitachi and IBM This is a voltage referenced standard and has two variations or classes both of which require a reference voltage of 1 5 V an input output source voltage of 3 3 V and a termination voltage of 1 5 V This stan
99. Celoxica eet Handel C Language Reference Manual For DK version 4 Handel C Language Reference Manual Celoxica Celoxica the Celoxica logo and Handel C are trademarks of Celoxica Limited All other products or services mentioned herein may be trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous development and improvement All particulars of the product and its use contained in this document are given by Celoxica Limited in good faith However all warranties implied or express including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product Celoxica Limited shall not be liable for any loss or damage arising from the use of any information in this document or any incorrect use of the product The information contained herein is subject to change without notice and is for general guidance only Copyright 2005 Celoxica Limited All rights reserved Authors RG Document number RM 1003 4 2 Customer Support at http www celoxica com support Celoxica in Europe Celoxica in Japan Celoxica in the Americas T 44 0 1235 863 656
100. E KE KE KEE Ku 71 eZ MUO EE 71 4 12 2 E age Me en EREECHEN 72 4 13 EXTERN LANGUAGE CONSTRUCT en vn ee KK KE KEN KE KEE KEE KEE KE KE Ka KN 72 GEG REGISTER EEN 75 4 15 INLINE FUNCTIONS nx vn Ka Ka KE KENE ERR KE KE KE KENE ERR KE KE KE KN KN KR KEN 75 Be LO STATIC vesecesercnewisesetetenensswaessecsncssocsssuscececunsceescseececcasuesesenaseess 76 Aa TYPEDEF EE 76 ALOT PEOP EE 77 MLS CON ST arara EREEREER 78 S INN www celoxica com Page 2 Handel C Language Reference Manual i WT Celoxica A LO VOCATILE EE 78 421 COMPLEX DECLARATI e KETTEN 78 4 21 1 Macro expressions IN widthbe ccc cccc esse cece eee eee eeeeeeeeeeeeeeeeeeeneneeeeeeenegs 78 D er de LY De ET E EE 79 4 21 3 Using signals to split Up complex EXPIESSIONS cce cece cece ee eeeeeeeeeeeeeeeeees 79 4 22 VARIABLE INITIALIZATION negeegeueg ege ege NEE R RENE ENEE ENNEN NEEN 80 9 STATEMENT CN 82 5 1 SEQUENTIAL AND PARALLEL EXECUTION one ue Ke KEE KEE KEE E KEE E Ku e 82 5 2 SEQ 83 5 3 REPLICATED PAR AND SEQ une een e Ka E KEE KEE KEE KEE KEE KEE KEE E Ku e 83 Da PRUAUCT EE 85 5 5 USING PRI ALT ESPERANCE VEER NNN 86 DO ASSIGNMENT CEET 88 SGAL COMES EE 89 ENE WA OU EE 90 5 0 5 return EXPres SiON gees 91 5 6 4 Conditional execution if eleel cece cccee esse cece tees eeeeeeeeeeeeeeeeseeeenenteegs 91 Oe Wi COO EE 92 SOO e ae WE TOOP EE 93 5 6 7 for loops ee Ee Ee A EET Ee 93 e SVN EE E 95 BO Ol Cake bebe 96 Di Ord e EEN 97 e ATN E EE 97 OLR TV SCI E E
101. G soxweeetetes 131 Selection within switchen 88 See EE 62 semaphores ccc cece ee eeeeeeeees 62 92 93 SOO WEE 76 sequential and parallel execution 75 sequential repltcation 76 S E A A 33 160 183 186 clock 160 family 183 intwidth 33 part 183 reset 186 Celoxica BEL ClO GG ee 160 El UE 183 BE DOP eo cname tees ccceacenretespeananeiceceecuns 183 set EE eebe 186 Shared code 113 116 127 135 136 Shared expreSSionS s es 135 136 restrictions 136 shift operators shift operators 102 EE ee EEN ER SNOW specification c cece cece eens 286 side CITGClS EE 18 95 sign EXTENSION 00e eee 97 102 133 EENEG 63 319 SINE eegene 31 32 107 Signed unsigned 32 96 107 casting 96 SIMULATIONS ccc cece cece eee e eee eeeeeeees 228 clock required 160 file I O 178 simulating buses 230 simulating interfaces 228 Simulator eee e eee tee ee eee teen eeeeees 178 input file format 178 output 286 SIZCOD Gegen 17 SORES ee E E 218 interfaces 218 Spartan devices ccceeeee eens 180 183 constraints files 281 I O standards supported 289 296 mprams 59 on chip RAMs 212 RAM timing issues 256 Slew rate of output buffer 286 Specifications cee eee 245 2 6 base 254 S INN www celoxica com Page 345 Handel C Language Reference Manual bind 254 block 256 busformat 259 clk 261 clkpulselen 282 clock position 282 clockport 262 data 264 dci 265
102. HDL and Verilog output If the specifications are omitted the place and route tools will assign the pins The specifications apply to the following objects Specification Meaning Input Output Tri state RAM ROM bus bus bus addr Address pins e data Data pins e e e e e we Write Enable pin P e g ES Chip Select pin e oe Output Enable e e pin clk Clock pin e Pin lists are always given in the order most significant to least significant Multiple write enable chip select and output enable pins can be given to allow external RAMs and ROMs to be constructed from multiple devices For example when using two 4 bit wide chips to make an 8 bit wide RAM the following declaration could be used S INN www celoxica com Page 283 Handel C Language Reference Manual Celoxica ram unsigned 8 ExtRAM 256 with toffchip l addr Pi Pe Pos Pa Po SEET P77 Pari data P9 P10 P11 P12 P13 P14 P15 P16 we P17 P18 cs P19 P20 oe P21 P22 is 12 21 ports specification The ports specification may be given to a RAM ROM or MPRAM declaration and is valid for EDIF VHDL and Verilog output When set to 1 the compiler builds an external memory interface allowing you to connect to dedicated memory resources on an FPGA PLD or to connect to RAMs in external code You can only use simple types for memories with the ports specification e g int unsigned
103. Handel C Language Reference Manual Celoxica 12 1 2 Simulator attributes These specifications are interpreted by the simulator Specification show base infile outfile extlib extfunc extinst Possible values 0 1 2 8 10 16 Any valid filename Any valid file name Name ofa plugin We Name ofa function within the plugin Instance name with optional parameter S Default 10 None None None PlugInSet or PlugInGet depending on port direction None Applies to variables channels o p interfaces tri state interfaces variables chanouts o p interfaces tri state interfaces chanins Up interfaces tri state interfaces chanouts o p interfaces tri state interfaces variables interface or port interface or port interface or port Meaning Show variable during Simulation Print variable in specified base Redirect from file Redirect to file Specify external plugin for Simulator Specify external function within the simulator for this port Specify simulation instance used TH www celoxica com Page 253 Handel C Language Reference Manual Celoxica 12 1 3 Clock attributes These specifications apply to a clock and affect the hardware built in that clock domain l www celoxica com Page 254 Handel C Language Reference Manual Specification clockport minperiod paranoia rate resolutiontim e
104. If you had the following expression written in ANSI C a b c dte this could be separated into single statements in Handel C S INN www celoxica com Page 25 Handel C Language Reference Manual Celoxica seq t C D cd te a b However you could rewrite the same code to run all the statements in parallel par The a adte b d te 3 6 5 Handel C v C functions There are a number of differences in the way in which functions can be used in ANSI C and Handel C In Handel C e Functions may not be called recursively since all logic must be expanded at compile time to generate hardware e You can only call functions in expression statements These statements must not contain any other calls or assignments e Variable length parameter lists are not supported e Old style ANSI C function declarations where the type of the parameters is not specified are not supported e main functions take no arguments and return no values e You can have more than one main function Each main function is associated with a clock If you have more than one main function in the Same source file they must all use the same clock e You can have arrays of functions and inline functions These are useful when you are writing parallel code Re writing recursive functions If you want to port code that uses recursive functions to Handel C the options for rewriting it include e Using recursive macro expressi
105. LP specifies that the clock should use a low power clock buffer for Actel Where no buffer spec is used the default buffer type is used 12 6 busformat specification The busformat specification may be given to e generic and port type port_in and port_out interfaces but not bus type interfaces e port memories memories using with ports 1 to connect to external code busformat specifications are ignored for VHDL and Verilog output and for bus type interfaces bus_in bus_ts etc S INN www celoxica com Page 266 Handel C Language Reference Manual Celoxica When compiled to EDIF the busformat string defines the format of the wire names Valid values for the busformat string are BI B_I BLI BCI B lt gt B represents the bus name and the wire number The default format is BI If you want to specify a single port for the entire bus use B DIN OI B lt N 0 gt B N 0 B specifies a bus without specifying a width and BLN 0 and B lt N 0 gt specify a bus of width N 1 A 6 bit port could therefore be generated as port portL5 0Jor port lt 5 0 gt depending on the value of busformat E If data specifications are used with busformat they are ignored and a warning is issued You can place the busformat specification after any port or at the end of an interface statement If you place a specification at the end of the interface declaration it will apply to all ports in the declaration except for any ports
106. M entry Value bLOJLOILOI 1 bLOIJLOILII 2 bLOILIILOI 3 bLOILIIL1I 4 bLIILOILOIJ 5 bLIILOIL1I 6 bLIILIILOIJ 7 bLIILIIL1I 8 bL2IJLOILO J 9 bL2ILOIL1 10 bL2IL1ILO J 11 bL2IL1IL1 12 bL3ILOILOJ 13 bL3ILOIL14 14 bL3ILIILOJ 15 bLSILIIL1I 16 Because of their architecture RAMs and ROMs are restricted to performing operations sequentially Only one element of a RAM or ROM may be addressed in any given clock cycle and as a result familiar looking statements are often disallowed For example ram lt unsigned int 8 gt x 4 MIT Ste l This code is inadvisable because the assignment attempts to read from the third element of x in the same cycle as it writes to the first element In a multi dimensional array you can access separate elements of the arrays so long as you are not accessing the same RAM For example x 2 1 x 3 0 is valid x 2 1 x 2 0 is invalid Note that arrays of variables do not have these restrictions but may require substantially more hardware to implement than RAMs depending on the target architecture 4 8 mpram multi ported RAMs You can create multiple ported RAMs MPRAMs by constructing something similar to an ANSI C union You must use the mpram keyword mprams can be used to connect two independent code blocks The clock of the mpram port is taken from the function in which it is used The normal declaration of a MPRAM would be to create a dual ported RAM by declaring two ports of equal width e
107. Operator Meaning F Addition Subtraction S Multiplication Division Modulo arithmetic Any attempt to perform one of these operations on two expressions of differing widths or types results in a compiler error For example int 4 w int 3 X int 4 y unsigned 4 Z y Ww x ILLEGAL z wety ILLEGAL The first statement is illegal because w and x have different widths The second statement is illegal because w and y are signed integers and z is an unsigned integer Width of results All operators return results of the same width as their operands Thus all overflow bits are lost For example unsigned int 8 x unsigned int 8 y unsigned int 8 Z x 128 y 192 Z 2 X X z Z y This example results in x being set to 64 and z being set to 128 By using the bit manipulation operators to expand the operands it is possible to obtain extra information from the arithmetic operations For instance the carry bit of an addition or the overflow bits of a multiplication may be obtained by first expanding the operands to the maximum width required to contain this extra information For example S INN www celoxica com Page 112 Handel C Language Reference Manual Celoxica unsigned int 8 unsigned int 8 unsigned int 9 8 8 1 we e we unsigned int unsigned int unsigned int x xXx z lt Or N we w 0 u 0 v z 0 x 0 y In this example w and z contai
108. RAMCLK rclkpos 1 5 clkpulselen 0 5 toe thes rz The rising HCLK edge at tO initiates the read cycle Some time later the address A1 is set up which is sampled somewhere in the middle of the HCLK cycle t0 1 5 in this case By the time the next HCLK rising edge occurs at t1 the data is available for reading The cycle completes within one Handel C clock cycle Write cycle for a flow through SSRAM Flow through SSRAMs perform a late write cycle the data is clocked in one clock cycle after the address is sampled The timing diagram shows the complete write cycle E www celoxica com Page 213 Handel C Language Reference Manual Celoxica Fast clack CLK div A FAM cack RAMCLE Withpos 125 3 5 ckhoulselen 0 5 Ry Mestat AO welength 1 0 ADDRESS DAT Al The HCLK rising edge at tO initiates the write cycle causing the ADDRESS and DATAIN signals to change Two cycles of RAMCLK are needed to clock the new data into the RAM at the specified address the first to sample the address the second to sample the data However since we re not expecting to read from the RAM s output we can wait until the last possible moment In this case the two rising edges of RAMCLK occur at t0 2 5 and t0 3 5 The write enable signal must be low during the rising edge of RAMCLK that samples the address but not during the one that samples the data This can be done by setting westart and wel
109. ReadWrite 7 data File 2 mpram Fred ram lt unsigned 8 gt ReadWritel256 Read write port rom lt unsigned 8 gt Read 256 Read only port extern mpram Fred Joan set clock external P2 void main void unsigned 8 data data Joan Read 7 S INN www celoxica com Page 68 Handel C Language Reference Manual Celoxica 4 9 WOM write only memory You can declare a write only memory using the keyword wom The only use of a write only memory would be to declare an element within a multi ported RAM Since woms only exist inside multi port rams it is illegal to declare one outside an mpram declaration Syntax wom variable_Type variable_Size WOM_Namel dimension initialize_Values with specs Example mpram connect wom lt unsigned 8 gt Writeonlyl256 Write only port rom lt unsigned 8 gt Read 256 Read only port 4 10 sema Handel C provides semaphores for protecting critical areas of code Semaphores are declared with the sema keyword For example sema RAMguard Semaphores have no type or width associated with them They cannot be assigned to or have their value assigned to anything else You can only access semaphores through the trysema semaphore expression and releasesema semaphore statement trysema tests to see if the semaphore is currently taken If it is not it takes the semaphore and returns one If it is taken it returns zero releasesema releases the sema
110. Ss can be specified in exactly the same way as on chip synchronous SRAMs with the addition of the rcl kpos wclkpos clkpulselen and clk Specifications clk specifies the pin on which the generated RAMCLK will appear when the SSRAM in question is external offchip 1 e A www celoxica com Page 211 Handel C Language Reference Manual Example macro expr addressPins Pin List macro expr dataPins Pin List macro expr csPins Pin List macro expr wePins Pin List macro expr oePins Pin List macro expr clkPins Pin List ram unsigned 32 ExtBankL1024 with offchip 1 addr addressPins data dataPins cs csPins we wePins oe oePins westart 2 welength 1 rclkpos 41 55 2 5 wclkpos 1 5 2 5 3 5 clkpulselen 0 5 3 elk cik Finis Flow through SSRAM example ram unsigned 18 FlowBank 1024 with block 1 westart 2 welength rclkpos wclkpos clkpulselen 0 5 Celoxica This code instructs the compiler to build hardware to generate SSRAM control signals as Shown below It is also applicable for reading from block RAMs in Actel and Xilinx FPGAs and Altera ESB and tri matrix memories Se www celoxica com Page 212 Handel C Language Reference Manual Celoxica Read cycle for a flow through SSRAM The timing diagram shows a read cycle from a flow through SSRAM Fast clock CLK G Handel clock CLK div 4 RAM clock
111. T 81 0 45 331 0218 T 1 800 570 7004 E sales emea celoxica com E sales japan celoxica com E sales america celoxica com S INN www celoxica com Handel C Language Reference Manual WT Celoxica Contents LNT ROOUCTI ON EEN 11 E REFERENCES eene E E EEEE 11 2 GETTING STARTED WITH HANDEL C xnsnk eene KK NN KEN KR KN KN KN KN KEREN KK KR Ka V 12 s Wee elle 2 ee EE 12 Fi Lol Aandele progr alis snctapaeisicarer reve arase inn caeierritestyses EEREN ar Ena eraran tine 12 2 1 2 Parallel porograms cece ceeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeeeenaeeeeetetseggauneregs 12 2 1 3 Channel COMIMUNICALION EE 13 2 1 4 Scope and variable change 15 3 LANGUAGE BASICS eege EE eege 16 3 1 PROGRAM STRUCTURE EE 16 3 2 COMMENTS cnatenedi ces sweu emer cuevsenuemeu E A 17 3 3 STATEMENT SUMMARY us NEK ENER ENER ERKIEEKNN ENNEN NENNEN KENNEN NR 17 3 4 OPERATOR SUMMARY deeg 19 3 9 TYPE SUMMARY e 21 3 6 COMPARISON OF HANDEL C AND ANSI C neues KKK KN KN KR KN KN KE Kn 22 3 6 1 Handel C v C types and Dvpeoperatore cece cece cece eeeeeeeeeeeeeeeeeneanennees 23 3 6 2 Handel C v C floating point variable 23 3 6 3 Handel C v C variable widths ANd castmg cc cece ccceee sees eee eeeeeeseneenneennes 24 3 6 4 H ndel C y C side ut EE 25 3 6 5 Handel C v Er ln ei ge CN 26 3 6 6 Handel C v C loop statements cece ccccee sees cece cece eeeeeeeeeeeeeeteeeeeeneneengs 27 306 7 Handel y C UNON eege 28 3 6 8 Handel C v C data input and output e esse
112. Te EN 314 14 LANGUAGE SYNTAX EE 316 14 1 LANGUAGE SYNTAX CONVENTIONS enen en KR KR KR KR KR KR ER ER ER ER ER ER KR ER ER KR KR Kn 316 14 2 KEYWORD SUMMARY ug EEEEREEER ENEE EREER EE REEEEENEN ENKEN KE KENKNE NEEN ERR 316 14 3 CONSTANT EXPRESS ONS wen enka KN KN KR ENER EN KN ER ENER EN ER KEEN KN KN ER KEEN ENN 321 1473 4 fe Eau IER 321 14 3 2 Integer CONSTANTS SYNTAX cece eee ce eee ce eee teeeeeeeeeeeeeseneeteueetenteteettnagegs 322 14 3 3 Character Constants Syntax ENNEN 322 IAS OOS SY Ga E E E E E E setenerseaueseunes 322 14 3 5 Floating point constants svntanx cece cece cee eect essen eee ee eeeeeeeeeneeeeeeeeneas 322 14 4 FUNCTIONS AND DECLARATIONS SYNTAX cscseneneneneneneneueueneneneueneuas 323 S INN www celoxica com Page 7 Handel C Language Reference Manual 14 5 MACRO SHARED EXPRS PROCS SYNTAX unn aa KENE ENK ENK KE KEN KEN KEN KN 14 6 NTERFACES SYNTAX eer EE Eege 14 7 STRUCTURES AND UNIONS SYNTAX uk Ka KN KEREN KEREN KREE KR KN KR KEN KK EN Ku 14 8 ENUMERATED TYPES SYNTAX en KN Ka KN KE KN KEREN KEE EN KREE KE KN KEREN KEE EN Ku 14 9 Si GNAL SPECI FIERS SYNTAX gege EE EE NENNEN 14 10 CHANNEL SYNTAX EE 14 11 RAM SPECIFIERS SYNTAN enen KN KR KEEN E KN KR ER KN E KR ENER KN KN KR KEEN KN abe Ee Ale giel CC eh gh EE 14 13 FUNCTION PARAMETERS SYNTAX ua Kn Ka KN KEREN KEREN KREE KR KN KK EN KEE EN Ku 14 14 TYPE NAMES AND ABSTRACT DECLARATORS SYNTAX eau KN KR KEEN KN V 14 15 STATEMENTS SYNTAX TN 14 15 1
113. _specifiers declarator declaration_specifiers abstract_declarator declaration_specifiers width int_parameter_declaration declaration_specifiers with initializer declaration_specifiers declarator with initializer declaration_specifiers abstract_declarator with initializer declaration_specifiers width with initializer int_init_parameter_declaration int_parameter_declaration declaration_specifiers declarator initializer with initializer assignment_expr_spec assignment_expression with initializer S INN www celoxica com Page 325 Handel C Language Reference Manual Celoxica 14 7 Structures and unions syntax struct_or_union_specifier aggregate_form identifier struct_declaration aggregate_form identifier aggregate_form struct union mpram struct_declaration type_specifier type_qualifier struct_declarator with initializer struct_declarator declarator Ldeclarator constant_expression He The current version of Handel C does not support unions 14 8 Enumerated types syntax enum_specifier enum identifier enumerator enumerator enum identifier enumerator identifier identifier constant_expression 14 9 Signal specifiers syntax Signal_specifier signal lt type_name gt signal 14 10 Channel syntax Channel_specifier chan lt type_name gt chanin lt type_name gt
114. _statement goto identifier continue break return return expression selection_statement if expression statement if if expression statement else statement 1fselect constant_expression statement if ifselect constant_expression statement else statement Switch expression statement prialt L prialt_statement set_statement set part STRING set clock clock set family identifier set intwidth constant_expression set intwidth undefined set reset reset clock internal expression with initializer www celoxica com Page 330 Handel C Language Reference Manual Celoxica external expression with initializer internal_divide expression expression with initializer external_divide expression expression with initializer reset internal expression external expression iteration_statement while expression statement for Lfor_statement L expression for_statement statement 14 15 1 Compound statements with replicators compound_statement seq par declaration statement seq par Lrep l_macro_param repIl_macro_param constant_expression Lrep _update_param repl_update_param declaration statement 14 16 Replicators syntax Replicator initialization definitions repl_macro_param repl_param initializer repl_param initializer Replicator update definitions repl_update_para
115. ace and route tools Note that Handel C provides no information about the timing of the change of state of a Signal within a Handel C clock cycle Timing analysis is available from the FPGA or PLD manufacturer s place and route tools Handel C programs can also interface to external logic other Handel C programs programs written in VHDL or Verilog etc by using user defined interfaces or Handel C ports He Your license may not allow you to use interfaces If this is the case you can only interface to external devices using macros provided in any Celoxica libraries you have licenses for such as PAL 11 1 Interface sorts Handel C provides a number of predefined interface sorts bus type interfaces bus_ generate the hardware for buses connected to pins port type interfaces port_ generate the hardware for floating ports buses which are not connected to pins These can be of any width and can carry signals between different sections of Handel C code or to software or hardware beyond the Handel C program You can also define your own sorts to interface to external blocks of code generic or custom interface sorts S INN www celoxica com Page 225 Handel C Language Reference Manual Celoxica Predefined interface sorts Sort identifier Description bus_in Input bus from pins bus_latch_in Registered input bus from pins bus_clock_in Clocked input bus from pins bus_out Output bus to pins bus_ts Bi dire
116. ack box between ports 1 and 2 and between ports 3 and 4 The interface also specifies an external connection from port 2 to port 3 this connection is outside the black box 3 12 13 fifolength specification The fifolength specification converts a channel into a FIFO of the given length If fifolength is two or greater the block specification can be used If fifolength is not a power of 2 and the paranoia specification is O or 1 default the FIFO will be created with low latency else it will be created with a higher latency Example int 8 chan _FIFO with fifolength 7 block MK4 creates a FIFO in Altera Cyclone block RAM S INN www celoxica com Page 275 Handel C Language Reference Manual Celoxica 12 14 infile and outfile specifications The infile specification may be given to chanin port_in port_out bus_in bus_latch_in bus clock mm bus_ts bus_ts_latch_in and bus_ts_clock_in declarations The outfile specification may be given to chanout bus_out bus_ts bus_ts_latch_in and bus_ts_clock_in declarations The strings that these specifications are set to will inform the simulator of the file that data should be read from infile or the file that data should be written to outfile Note that when applying the outfile specification it should not be given to multiple channels For example the following declarations are allowed but it would be better to place them in separate files to avoid undefined re
117. adding a O bit as its MSB to preserve the value of 10 A programmer must explicitly cast the variables to the same type Assuming that they wish to use the 4 bit value as a signed integer the above example then becomes e A www celoxica com Page 103 Handel C Language Reference Manual Celoxica int 4 x unsigned int 4 y x int 4 y It is now clear that the value of x is the result of treating the 4 bits extracted from y as a signed integer 6 2 1 Restrictions on casting Casting cannot be used to change the width of values For example this is not allowed unsigned int 7 x int 12 y y int 12 x Not allowed The conversion should be done explicitly y int SCHEER xJ Here the concatenation operation produces a 12 bit unsigned value The casting then changes this to a 12 bit signed integer for assignment to y This is to ensure that the programmer is aware of such conversions Explanation mt 7 X unsigned int 12 y X 5 y unsigned int 12 x The Handel C compiler could take two routes One would be to sign extend the value of x and produce the result 4091 The second would be to zero pad the value of x and produce the value of 123 Since neither method can preserve the value of x in y Handel C performs neither automatically Rather it is left up to the programmer to decide which approach is correct in a particular situation and to write the expression accordingly You may sign extend using
118. ains 162 172 clock pins 231 261 current 162 cycles 195 dummy 160 external 161 external resynchronization 172 fast 187 193 internal 161 inverted 193 196 locating 160 multiple 160 162 172 period 154 position specifications 282 reading from external pins 221 resynchronizing 172 simulation 160 source 160 specifying 160 SSRAM 193 196 SSRAMs 193 195 196 261 combinational loops 90 149 262 COMIN GINS E 10 communication 5 6 44 162 164 between clock domains 162 164 channels 6 44 164 COMDPALISON ce ceee cece ee eeee eens 106 107 Implicit 107 operators 106 Ssigned unsigned 107 compile time 5 70 99 131 132 messages 99 selection 70 131 132 complex declarations 08 69 71 complex exvDteselons 72 95 Page 337 Handel C Language Reference Manual compound statements with replicators E 324 CONCATENATION cce cece eee es 102 306 operator 102 preprocessor 306 conditional compilations 305 conditional directives cee cece eee 305 conditional execution if elSe 84 conditional operator 109 131 Wel 71 constant EXPreSSIONS ccee eee ees 314 constant macro expressions 130 CORSUONUS gege ee EE 30 315 binary 30 character 315 decimal 30 hexadecimal 30 manifest 303 octal 30 constraints 006 264 269 270 281 files 269 281 pins 264 timing 269 270 281 single TE
119. al I Os supported for tri state interfaces are BLVDS25 on the Virtexll Virtexil Pro and Virtex 4 and LVDS25 and LVPECL33 on the VirtexE 2 LVDCI standards are equivalent to using LVCMOS standards with a dci specification of 1 3 LVDCI split termination standards are equivalent to using LVCMOS standards with a dci specification of 0 5 If no I O standard is specified the default for Actel ProASIC and ProASIC is LVCMOS33 with drive strength High or Max The default for all other devices is LVTTL with a drive current of 12mA in the case of Xilinx families supporting Select 1 0 Examples set clock external C1 with standard HSTL_III interface bus_out Eel int 4 outPort x with data dataPinsO standard HSTL_I interface bus_ts unsigned 3 Baboon unsigned 3 apel y unsigned 1 ape en with data dataPinsT standard LVTTL strength 24 12 32 2 1 O standards supported by different chips You can specify the I O standard for a particular device using the standard specification Consult the manufacturer s datasheet for the standards supported by a particular chip e Spartan Spartan XL and Flex10 series devices do not support selectable Standards e Actel ProASIC and ProASIC only support the LVCMOS33 default and LVCMOS25 standards e If you are using differential I Os with Mercury devices you need to use the dedicated pins interfacing to the HSDI high speed differential interface S INN
120. amount of time used for it to settle is known as the resolution time t e You can specify a maximum period for this by using the resolutiontime specification A sensible value for resolutiontime is three quarters of the clock period The amount of time left is the amount of time for the control signal to get from one flip flop to the next including all output setup and routing delays This is the minperiod specification This would normally only be used if paranoia is set to 0 How channels are designed to deal with metastability When you use a channel to communicate across clock domains synchronization hardware is built automatically Clock A Clock B Channel m synchronisers L time to transfer between domains paranoia in domain B 1 Xt Us clock period in domain B Be unconstrainedperiod TH www celoxica com Page 245 Handel C Language Reference Manual Celoxica tnp minperiod The control signals are clocked through a number of flip flops specified by paranoia On each clock edge the data is moved through another flip flop such that it is less likely to be metastable 11 6 2 Using interfaces External resynchronizing example This example shows the three files required to connect two EDIF blocks bbA and bbB which use different clocks The small files bbA hcc and bbB hcc compile to the EDIF code using the port_out from and port_in to interfaces The metastable hcc file connects the two together an
121. andel C does not allow side effects in expressions the initialization and iteration expressions have been replaced with statements For example for xX 0 xX 202 x SLD y dE Here the assignment of 0 to x and adding one to x are both statements and not expressions These initialization and iteration statements can be replaced with blocks of statements by enclosing the block in brackets For example FOr 4 x 0 y 237 e KX lt 20s xf l X7 2 yoy ER e A www celoxica com Page 94 Handel C Language Reference Manual Celoxica 5 6 8 switch Handel C provides switch statements similar to those in conventional C Switch Expression case Constant Statement break default Statement break The switch expression is evaluated and checked against each of the case compile time constants The statement s guarded by the matching constant is executed until a break statement is encountered If no matches are found the default statement is executed If no default option is provided no statements are executed Each of the Statement lines above may be replaced with a block of statements by enclosing the block in brackets As with conventional C it is possible to make execution drop through case branches by omitting a break statement For example switch x case 10 a D case 11 c d break case 12 e f break Here if x is 10 b is assigned to a and d is assigne
122. anifest constants cece ee eee eee 303 mapping of different width ports 59 maximum clock rate cece cece eee 154 member operatore 109 memory 54 57 62 186 187 193 196 Actel 210 allocation 22 Altera 211 asynchronous 187 192 300 block 256 initialization 54 multi port 57 off chip 274 on Cyclone devices 209 on Stratix devices 209 on chip 180 210 211 212 pipelining 196 207 Celoxica RAM 54 186 restrictions 97 ROM 54 186 simultaneous access 97 specifications 256 274 synchronous 193 204 261 282 type 256 WOM 62 Xilinx 212 Mercury devices sses 180 183 I O standards supported 289 296 mprams 57 pull up resistors 280 RAM 211 merging PINS seen ee eens 231 232 metastabultv 168 235 channels across clock domains 168 237 238 clock domains 168 examples 172 external resynchronization 172 stabilizing data in interfaces 236 MIF ko 211 minperiod ccc cece e eee eee 167 273 modulo arithmetic cece eee eee 104 mpram multi ported RAM 57 59 61 multidimensional arrayS 00eeeee 56 Multi file projects c cece cece eee eee 116 multiple ote ceed inenantetawiaciaseusans 160 162 channel timing issues 163 166 communicating between clock domains 162 172 multiple ClOCKS ccceee eee eees 160 162 mulDplcatton ccc cce eee e ener ee ee etna 104 ek ODEON NN 196 NCF TGS cpicicn E 269 281 NOU egual UG E 106 Object epecificoetions
123. annels to communicate between hardware components in separate clock domains you will need to insert resynchronizing hardware if it is not included in the components For example if data is sent from port_out A in domain bbA and received from port_in B in domain bbB the data must be resynchronized to the clock in domain bbB Using interfaces External resynchronizing example This example shows the three files required to connect two EDIF blocks bbA and bbB which use different clocks The small files bbA hcc and DbB hcc compile to the EDIF code using the port_out from and port_in to interfaces The metastable hcc file connects the two together and generates one flip flop that resynchronizes the data by reading the value from bbA into a variable clack Pl clock Pr Metastable File metastable hcc www celoxica com Page 179 Handel C Language Reference Manual Celoxica ZS Black box code to resynchronize Needs to be clocked from the reading clock i e DbB hcc s clock Wi int 1 x interface bbACint 1 from A interface bbB BCint 1 to x unsigned 1 clk __clock set clock external P1 void main void while l x stabilize the data by adding resynchronization FF ay x A from File bbA hcc x Domain bbA Compiles to bbA edf SE interface port_in unsigned 1 clk with clockport 1 clk set clock internal clk clk void main void int 1 ys inte
124. anual Celoxica the FPGA or to other IP on the FPGA The retime specification can be added to any variable declaration to lock the position of the flip flops generated by that variable unsigned 16 Inl In2 with retime 0 unsigned 8 SomeOtherVar For instance in the code above variables Inl and In2 are prevented from moving whereas SomeOtherVar can be moved as required by the retimer to meet the specified clock rate To disable all flip flops from being retimed in a specific clock domain the retime specification can be applied to a clock for instance set clock external D17 with retime 0 12 29 sc_ type specification The sc_type specification may be given to port_in port_out or generic interfaces to specify the type of a port in SystemC Valid string values of this specification are SC mt sc_uint bool sc_logic sc _lv The default type of a port is bool if the port is 1 bit wide sc_uint otherwise You can apply the sc_type specification to individual ports If you place the specification at the end of the interface statement it will be applied to all the ports Example 1 Handel C ports in SystemC without sc_type specification set int A out interface port_in int 1 To read interface port_out drive int 4 From X_out results in Handel C generating the SystemC ports SC_in lt bool gt To sc_out lt sc_uint lt 4 gt gt From Example 2 Handel C ports in SystemC with sc_type specification se
125. aracter 14 3 5 Floating point constants syntax float_constant Aee Te e TLA NEE E Oe SPT TFE EL Lk ebe Ee EJF J EE F T thd SH Set EIL J Oe PEF R T e E S INN www celoxica com Page 322 Handel C Language Reference Manual Celoxica 14 4 Functions and declarations syntax function_definition declaration_specifiers declarator compound_ statement with initializer declarator compound_statement with initializer declaration declaration_specifiers init_declarator_list with initializer interface_declaration macro_declaration declaration_specifiers storage_class_specifier declaration_specifiers type _ specifier declaration_specifiers type qualifier declaration_specifiers storage_class_specifier auto register inline typedef extern static type_specifier void char short L int long float double signed unsigned typeof expression signal_specifier channel_specifier ram_specifier struct_or_union_specifier enum_specifier typedef_name type_qualifier const volatile HE www celoxica com Page 323 Handel C Language Reference Manual Celoxica typedef_name identifier init_declarator_list declarator initializer declarator initializer 14 5 Macro shared exprs procs syntax macro_declaration macro_proc_decl macro_expr_decl macro_proc_decl static ext
126. ational_expression cat_expression relational_expression lt cat_expression relational_expression gt cat_expression relational_expression lt cat_expression e S www celoxica com Page 332 Handel C Language Reference Manual Celoxica relational_expression gt cat_expression cat_expression shift_expression cat_expression shift_expression shift_expression additive_expression shift_expression lt lt additive_expression shift_expression gt gt additive_expression additive_expression multiplicative_expression additive_expression multiplicative_expression additive_expression multiplicative_expression multiplicative_expression take_drop_expression multiplicative_expression take_drop_expression multiplicative_expression take_drop_expression multiplicative_expression take_drop_expression take_drop_expression cast_expression take_drop_expression lt cast_expression take_drop_expression cast_expression cast_expression unary_expression type_name cast_expression unary_expression postfix_expression unary_expression Unary_expression unary_operator cast_expression sizeof unary_expression sizeof type_name width expression unary_operator amp zx postfix_expression select_expression postfix_expression expression postfix_expression expression expression postfix_expression
127. ay_element amp MyArrayLO S INN www celoxica com Page 42 Handel C Language Reference Manual Celoxica Initialize pointer to point to the entire array brackets are required pointer_to_array amp MyArray If you wanted to view all the referenced values MyArray in the Watch window during simulation you would need to type in pointer_to_array 4 2 6 Array indices When an array is declared the index has the smallest width possible For instance in array 8 the index need only go up to seven and will therefore be a three bit number If a variable is declared to represent the index it too will be three bits 4 2 7 struct Struct defines a data structure a grouping together of variables under a single name The format of the structure can be identified by a type name The variable members of the structure may be of the same or different types Once a structure has been declared its type name can be used to define other structures of the same type Structure members may be accessed individually using the construct struct_Name member_Name Syntax A structure type is declared using the format struct Ltype_Name member list Linstance_Name instance_Name member Jist is a list of variable definitions terminated by semi colons The use of 7nstance_Names declares variables of that structure type Alternatively you may declare variables as follows Struct type_Name instance_Name Stora
128. ble Value 4 bit Conversion to 8 representation bit representation S 0b1110 0b11111110 6 0b0110 0b00000110 The following code suffices for a 4 bit to 8 bit conversion TAG Oo int 4 y x y 3 y 3 y 3 y 3 Q y but it is tedious for variables that differ by a significant number of bits It also does not deal with the case when the exact widths of the variables are not known What is needed is a macro to sign extend a variable For example macro expr copy x n select n 1 x x copy x n 1 macro expr extend y m copy yLwidth y 1 m width y y int a int b Where b is known to be wider than a b extend a width b The copy macro generates n copies of the expression x concatenated together The macro is recursive and uses the select operator to evaluate whether it is on its last iteration in which case it just evaluates to the expression or whether it should continue to recurse by a further level The extend macro concatenates the sign bit of its parameter m k times onto the most Significant bits of the parameter Here m is the required width of the expression y and k is the actual width of the expression y The final assignment correctly sign extends a to the width of b for any variable widths where width b is greater than width a S INN www celoxica com Page 141 Handel C Language Reference Manual Celoxica 7 3 6 Recursive macro expressions example This example il
129. bus_clock_in The bus_clock_in interface sort is similar to the bus_in interface sort but allows the input to be clocked continuously from the Handel C global clock This may be required to synchronize the signal to the Handel C clock Its general usage is interface bus_clock_in type portName Name with Specs Reading the bus is performed by accessing the identifier Name portName as a variable which will return the value on those pins at that clock edge If no input port name is given the port name defaults to in The rising edge of the Handel C clock clocks the external signal into the internal value For example interface bus _clock_in int 4 InTo InBus with data P4 TESCH p2 P1 x InBus Inlo Read flip flop value 11 1 4 Writing to external pins bus out The bus_out interface sort allows Handel C programs to write to external pins Its general usage Is interface bus_out Name type portName Expression with data Pin List A specific example is interface bus out OutBus int 4 OutPort xty with data P4 Po g P2 PIE This declares a bus connected to pins 1 2 3 and 4 where pin 4 is the most significant bit and pin 1 is the least significant bit The value appearing on the external pins is the value of the expression x y at all times 11 1 5 Bidirectional data transfer bus_ts The bus_ts interface sort allows Handel C programs to perform bi directional off chip communication
130. by using write enable specifications westart welength or wegate However you cannot have an asynchronous write port and a synchronous read port since this would violate Handel Ce timing semantics Syntax moram MPRAM_name ram_Type variable_Type RAM_Name size with ClockPosition WriteEnableSpecs value ram_Type variable_Type RAM_Name size with ClockPosition WriteEnableSpecs value e Examples In the example below the first MPRAM is a bi directional dual port RAM with clock specifications applied to the whole MPRAM The second is a simple dual port RAM with different clock specifications applied to each port e A www celoxica com Page 65 Handel C Language Reference Manual Celoxica set clock external_divide Cl 4 moram ram unsigned 4 Port1 4 ram unsigned 4 Port2 4 TMax with wclkpos 2 rclkpos 2 5 clkpulselen 1 mpram wom unsigned 4 WritePortL4 with wclkpos 2 clkpulselen 1 rom unsigned 4 ReadPortL4 with rclkpos 2 5 clkpulselen 1 SMax 4 8 1 Initialization of mprams The first member of the mpram can be initialized Static mpram Fred ram lt unsigned 8 gt ReadWritelL256 Read write port rom lt unsigned 8 gt Read 256 Read only port Mary 10 11 12 13 This would have the same effect as Mary ReadWriteL0J 10 Mary ReadWriteL1J 11 Mary ReadWrite 2 12 Mary ReadWrite 3 13 The other elements of Fred ReadWrite wi
131. ca com Page 115 Handel C Language Reference Manual Celoxica unsigned int 6 w unsigned int 6 x unsigned int 6 y unsigned int 6 Z w 0b101010 x 0b011100 y W amp X Zz w Xx WS WI x This example results in y having the value 0b001000 z having the value 06111110 and w having the value 0b001001 6 9 Conditional operator Handel C provides the conditional expression construct familiar from conventional C Its format is Expression Expression Expression The first expression is evaluated and if true the whole expression evaluates to the result of the second expression If the first expression is false the whole expression evaluates to the result of the third expression For example XS ly SZ ye Za This sets x to the maximum of y and z This code is directly equivalent to Lt y gt Z A a else X Z The advantage of using this construct is that the result is an expression so it can be embedded in a more complex expression For example x w 0 y z 4 In this case the signedness and widths of x y and z must match as the value of y or z may be assigned to x but those of w need not 6 10 Member operators gt The structure member operator is used to access members of a structure or mpram or to access a port within an interface e A www celoxica com Page 116 Handel C Language Reference Manual Celoxica The structure pointer operator gt can be used
132. can also infer the widths types and the number of entries in RAMs and ROMs from their usage Thus it is not always necessary to explicitly declare these attributes For example ram int undefined a 123 ram int 6 b ram cl43 ram dL 4 7 3 Accessing RAMs and ROMs RAMs and ROMS are accessed in the same way as arrays For example ram int 6 b 56 bL7 4 This sets the eighth entry of the RAM to the value 4 Note that as in conventional C the first entry in the memory has an index of 0 and the last has an index of n 1 where n is the total number of entries in the memory 4 7 4 Differences between RAMs and arrays RAMs differ from arrays in that an array is equivalent to declaring a number of variables Each entry in an array may be used exactly like an individual variable with as many reads and as many writes to a different element in the array as required within a clock cycle RAMs however are normally more efficient to implement in terms of hardware resources than arrays but they only allow one location to be accessed in any one clock cycle Therefore you should use an array when you wish to access the elements more than once in parallel and you should use a RAM when you need efficiency S INN www celoxica com Page 62 Handel C Language Reference Manual Celoxica 4 7 5 RAM and ROM support on different devices Creating internal RAMs can only be done if the target device supports on chip RAMs Most devices c
133. celoxica com Page 182 Handel C Language Reference Manual Celoxica 9 3 2 Simulating multiple clock domains You may simulate your design by e using the DK simulator e untimed simulation of generated VHDL code e simulation of back annotated netlist Note that as the timing accuracy of the simulation increases it is harder to relate errors to the original Handel C code Using the DK simulator E The DK simulator may not simulate the timing of channels between clock domains identically to that in the generated hardware You must not rely on observed latency or timing behaviour in either simulation or hardware When you simulate designs with multiple clocks you will get a Select Clock dialog in the GUI asking you which clock you want to follow If you want to synchronize the clocks in a simulation use the DKSync d11 plugin TH www celoxica com Page 183 Handel C Language Reference Manual Celoxica 10 Targeting hardware and simulation 10 1 Interfacing with the simulator Communication with the simulator takes place over channels They are declared using the keywords chanin and chanout Standard channel communication statements can then be used to transfer data It is assumed that channels to and from the simulator never block and will always complete a transfer in one clock cycle He Channels to and from the simulator are declared using chanin and chanout instead of chan The special channels chanin and c
134. channels and signals 4 5 Channels Handel C provides channels for communicating between branches of code executing in parallel One branch writes to a channel and a second branch reads from it Channels are declared with the chan keyword For example chan int 7 link e A www celoxica com Page 51 Handel C Language Reference Manual Celoxica The width and type of data sent down the channel must be of the same width and type as the channel The width and type of a channel can sometimes be inferred by the Handel C compiler if they are not explicitly declared The channel can be an entry in an array of channels or be pointed to by a channel pointer If you want to select the first channel that is ready to communicate from a list of channels use the prialt statement If you wish to convert the channel into a FIFO use the fifolength specification This creates a FIFO with the specified number of data stores of the same width as the channel If you are simulating code you may use chanin and chanout to specify interfaces to the simulator These do not represent architectural channels but can be addressed in a similar way Syntax chan logicType Name with specifications Reading from a channel Channel Variable This assigns the value read from the channel to the variable It may also be read to a signal an array element RAM element or WOM element Writing to a channel Channel Expression This writes t
135. char Short and long For example unsigned char w Short y unsigned long Z Note that these are fixed widths in Handel C and implementation dependent in ANSI C The widths used for each of these types in Handel C is as follows S INN www celoxica com Page 39 Handel C Language Reference Manual Celoxica Type Width char 8 bits signed Short 16 bits long 32 bits Smaller and more efficient hardware will be produced by using variables of the Smallest possible width 4 2 4 Inferring widths The Handel C compiler can infer the width of variables from their usage It is therefore not always necessary to explicitly define the width of all variables and the undefined keyword can be used to tell the compiler to try to infer the width of a variable For example Int O x int undefined y x y In this example the variable x has been declared to be 6 bits wide and the variable y has been declared with no explicit width The compiler can infer that y must be 6 bits wide from the assignment operation later in the program and sets the width of y to this value If the compiler cannot infer all the undefined widths it will generate errors detailing which widths it could not infer The undefined keyword is optional so the two definitions below are equivalent int x int undefined x Handel C provides an extension to allow you to override this behaviour to ease porting from conventional C This allows you to set a width
136. clock relative to the Handel C clock to enable full memory accesses to be performed within 1 Handel C clock cycle For example you might want to advance the write clock or delay the read clock This is most suitable for off chip RAMs and is illustrated by the Flow through SSRAM example see page 212 and the Pipelining off chip SSRAM example see page 214 SSRAM devices supported Handel C supports ZBT compatible Zero Bus Turnaround flow through and pipelined output devices DDR double data rate and QDR quad data rate devices are not Supported directly you can write your own interfaces SSRAM write enable The Handel C compiler checks the block and of fchip specifications to find out what type of RAM is being built and generates the appropriate write enable signal e g active low for ZBT SSRAM devices and active high for block RAMs within Xilinx Virtex chips e A www celoxica com Page 201 Handel C Language Reference Manual Celoxica SSRAM read and write cycles The inputs to most inputs to SSRAMs are captured on the rising edge of the input clock During a read cycle there is a latency of at least one clock cycle between an address being captured at the input and data becoming available at the output This is also true for the write cycle in many devices an address is captured on one clock cycle and data on the next A diagram of a typical timing for a read or write cycle for an SSRAM device is shown below
137. clock specification is set clock Location with Rate_spec periodSpec If you are communicating between clock domains you also need to set timing Specifications resolutiontime or minperiod These control the synchronization hardware generated You must specify a clock When generating simulation output a dummy clock such as set clock external P1 Is valid 9 1 Locating the clock Since each Handel C main code block generates synchronous hardware a single clock source is required for each one The general syntax of the clock specification is set clock Location Location may be any of the following Location Meaning internal Expression Clock from expression internal_divide Clock from expression with integer division Expression Factor external Pin Clock from device pin external_divide Clock from device pin with integer division Pin Factor HE www celoxica com Page 167 Handel C Language Reference Manual Celoxica 9 1 1 External clocks External clocks may be accessed by associating the clock with a specific pin using set clock external pin_Name or set clock external_divide pin_Name factor where the external_divide keyword is a constant integer For example set clock external P35 set clock external_divide P35 3 set clock external_divide 3 The first of these examples specifies a clock taken from pin P35 The second specifies a clock taken from pin P35 which is divi
138. ctional tri state bus bus _ts_latch_in Bi directional tri state bus with registered input bus Ce clock mp Bi directional tri state bus with clocked input port_in Input port from logic port_out Output port to logic Custom or generic interface sorts You can define your own interface sorts to connect to non Handel C objects e Hardware descriptions written in another language VHDL Verilog and EDIF are currently supported For a VHDL code interface the interface sort would be the name of the VHDL entity For a Verilog code interface the interface sort would be the name of the Verilog module e Native PC object code used in simulation Programs that run on your PC for simulation and connect to a Handel C interface are known as plugins There are special port specifications to enable you to connect user defined interfaces with a plugin for simulation These are extlib extfunc and extinst 11 1 1 Reading from external pins bus mm The bus_in interface sort allows Handel C programs to read from external pins Its general usage Is interface bus_in type portName Name with data Pin List Reading the bus is performed by accessing the identifier Name portName as a variable which will return the value on those pins at that clock edge If no input port name is given the port name defaults to in e A www celoxica com Page 226 Handel C Language Reference Manual Celoxica Example interface bus_in int 4 To InBu
139. d 1 binVal unsigned 4 digitVal Interface definition interface tt l 446 unsigned 7 segments unsigned 1 rbon decode unsigned 1 Itn ItnVal unsigned 1 rbin rbinVal unsigned 4 digit digitVal unsigned 1 bin binVal with extlib PluginModelSim dll extinst decode model ttl 446_wrapper delay 1 This declares an interface of sort tt1 7446 The inputs from the interface to the Handel C design are segments and rbon The interface would therefore connect to a black box named tt17746 with ports segments rbon Itn rbin digit and bin The instance of the interface is decode The instance specifies the data going into the ports ltn rbin digit and bin and connects to a plugin PluginModelSim dl1 for Simulation If you did not want to use forward references to the interface and only wanted to define a single instance of the interface sort tt17446 you would not need to declare the interface The interface definition would be exactly the same as that shown above 4 6 4 Interface specifications Predefined bus interface specs Default data list the pins used for transferring data MSB to LSB None e A www celoxica com Page 59 Handel C Language Reference Manual Celoxica Speed set buffer speed output pul set pull up or pull down for bus pins infile set file source for input bus data outfile set file destination for output bus data All interface specs base specify display base for variables in debugger b
140. d OpWidth dinb DINB with data DatalInB intime InlTimeRequirementB E Output data unsigned result interface bus_out DOUTCunsigned OpWidth dout result with data DataOut outtime OutTimeRequirement e Main program pipelined multiplier void main void unsigned xx OpWidth unsigned yylOpWidth unsigned rr lOpWidth nH www celoxica com Page 278 Handel C Language Reference Manual Celoxica while 1 par Read operands from input interfaces xxLO DINA dina yy 0 DINB dinb rreLO xxLO LO yyLO 0 IE Replicator generates the pipeline stages of the long multiplier which are done in parallel a par Stage l Stage lt OpWidth Staget xx Stage xx Stage 1 gt gt 1 yyLStage yy Stage 1 lt lt 1 rr Stage rr Stage 1 xx Stage 0 yy Stage 0 Update result result rrLOpWidth 1 www celoxica com Page 279 Handel C Language Reference Manual Celoxica 12 17 minperiod specification The minperiod specification specifies the maximum delay in nanoseconds between flip flops in a synchronizer including output delay setup time and skew at either end Its value must be less than the clock period Clock A Clock B feet eae tres cr unconstrainedperiod Hie resolution time tres EEN minperiod The higher the value for minperiod the less time will be available within a clock tick for control signa
141. d by Fujitsu CTT is a voltage referenced standard requiring a reference voltage of 1 5 V an input output source voltage of 3 3 V anda termination voltage of 1 5 V The CTT standard is a superset of LVTTL and LVCMOS CTT receivers are compatible with LYVCMOS and LVTTL standards CTT drivers when un terminated are compatible with the AC and DC specifications for LYCMOS and LVTTL This standard requires a Differential Amplifier inout buffer and a Push Pull output buffer GTL Gunning Transceiver Logic Plus The GTL standard is a high speed bus standard J ESD 8 3 first used by Intel Corporation for interfacing with the Pentium Pro processor and is often used for processor interfacing or communication across a backplane GTL is a voltage referenced standard requiring a 1 0 V input reference voltage and board termination voltage of 1 5 V The GTL standard is an open drain standard that requires a minimum input output source voltage of 3 0 V S INN www celoxica com Page 297 Handel C Language Reference Manual Celoxica HSTL High speed Transceiver Logic The HSTL standard specified by JEDEC Standard J ESD 8 6 High Speed Transceiver Logic HSTL is a 1 5 V output buffer supply voltage based interface standard for digital integrated circuits This is a voltage referenced standard and has four variations or classes Classes amp II require a reference voltage of 0 75 V and a termination voltage of 0 75 V classes Ill amp IV requir
142. d expression For example to share a recursive multiplier you could write macro expr multiply x y select width x 0 D multiply x 1 y lt lt 1 xLO 1 y 0 Shared expr mult x y multiply x y a mult b C d mult e f The macro expression builds a multiplier and the shared expression allows that hardware to be shared between the two assignments 7 3 9 Restrictions on shared expressions Shared expressions must not be shared by two different parts of the program on the same clock cycle For example S INN www celoxica com Page 143 Handel C Language Reference Manual Celoxica Shared expr mult x y x y par a mult b c mult e f NOT ALLOWED j This is not allowed because the single multiplier is used twice in the same clock cycle You need to ensure that shared expressions in parallel branches are not shared on the same clock cycle 7 3 10 let in let and in allow you to declare macro expressions within macro expressions In this way complex macros may be broken down into simple ones whilst still being grouped together in a single block of code They also provide easy sharing of recursive macros The let keyword starts the declaration of a local macro the in keyword ends the declaration and defines its scope Example macro expr Fred x let macro expr y x 2 in Vrs Returns x243 The top line defines the macro name and parameters The second l
143. d generates one flip flop that resynchronizes the data by reading the value from bbA into a variable clack Pl clock PZ Bec astable File metastable hcc Se www celoxica com Page 246 Handel C Language Reference Manual Celoxica ZS Black box code to resynchronize Needs to be clocked from the reading clock i e DbB hcc s clock Wi int 1 x interface bbACint 1 from A interface bbB BCint 1 to x unsigned 1 clk __clock set clock external P1 void main void while l x stabilize the data by adding resynchronization FF ay x A from File bbA hcc x Domain bbA Compiles to bbA edf SE interface port_in unsigned 1 clk with clockport 1 clk set clock internal clk clk void main void int 1 ys interface port_out from int 1 from y File bbB hcc l www celoxica com Page 247 Handel C Language Reference Manual Celoxica ZS Domain bbB Compiles to bbB edf SZ set clock external P2 void main void int 1 q interface port_in int 1 to to par while 1 q to to Read data 11 7 Ports interfacing with external logic Handel C provides the interface sorts port_in and port_out These allow you to have a set of wires unconnected to pins which you can use to connect to a simulated device or to another function within the FPGA or PLD Handel C supplies the interface declaration for th
144. d to c if x is 11 d is assigned to c and if x is 12 f is assigned to e zE The values following each case branch must be compile time constants www celoxica com Page 95 Handel C Language Reference Manual Celoxica 5 6 9 break Handel C provides the normal C break statement for e terminating loops e separation of case branches in switch and prialt statements break cannot be used to jump into or out of par blocks Loops When used within a while do while or for loop the loop is terminated and execution continues from the statement following the loop For example for x 0 x lt 32 x if aLxJ 0 break bE xJ aLlx Execution continues here switch When used within a switch statement execution of the case branch terminates and the statement following the switch is executed For example Switch x case l case 2 ytt break case 3 LTR break Execution continues here prialt When used within a prialt statement execution of the case branch terminates and the statement following the prialt is executed For example e A www celoxica com Page 96 Handel C Language Reference Manual Celoxica prialt case a X ae ae break case D y yrr break Execution continues here 5 6 10 delay Handel C provides a delay statement not found in conventional C which does nothing but takes one clock cycle to do it This may be useful to avoid resourc
145. dard requires a Differential Amplifier input buffer and an Push Pull output buffer SSTL3 is used for high speed SDRAM interfaces SSTL18 Stub Series Terminated Logic for 1 8 V The SSTL18 standard specified by J EDEC Preliminary Standard J C42 3 is a general purpose 1 8V memory bus standard This is a voltage referenced standard and has two variations or classes both of which require a reference voltage of 0 90 V an input output source voltage of 1 8 V and a termination voltage of 0 90 V This standard requires a Differential Amplifier input buffer and a Push Pull output buffer SSTL18 is used for high speed SDRAM interfaces GTL Gunning Transceiver Logic Terminated The GTL standard is a high speed bus standard JESD 8 3 invented by Xerox Xilinx has implemented the terminated variation for this standard Altera has not This standard requires a differential amplifier inout buffer and an Open Drain output buffer 12 32 4 Differential O standards Differential I O standards can be used with bus type interfaces offchip memories and external clocks in EDIF output They are specified using the standard specification The differential I O standards supported by Handel C are LVDS25 LVDS33 BLVDS25 LVPECL33 and HyperTransport If you want to build a tri state interface you can use only the BLVDS25 standard To specify pins for a bus_ type interface with a differential I O use the data specification Pins are specified in pairs e
146. de selecting the Enable memory pipelining transformations box on the Synthesis tab in Project Settings The transform is effective for all forms of hardware output Simulation is not affected Devices supporting pipelined on chip SSRAM The transform only applies to certain devices and configurations Family Actel ProAsic Actel ProASIC Altera Apex20K Altera Apex20KE Altera Apex20KC Altera Excalibur ARM Altera Mercury Altera Apexl Altera Stratix Altera StratixGX Altera Stratix II Altera Cyclone Altera Cyclone II Xilinx Virtex Xilinx Spartan I Xilinx Virtex Il Xilinx Virtex I1 Pro Xilinx Spartan 3 Xilinx Spartan 3E Xilinx Spartan 3L S INN BlockRAM yes n a n a n a n a no yes www celoxica com EAB n a yes yes except for single port RAMs and true dual port RAMs n a n a n a n a M512 n a n a n a yes except for true dual port RAMs No n a n a M4K n a n a n a yes except for single port RAMs and true dual port RAMs except for Single port RAMs and true dual port RAMs n a n a Page 204 M RAM n a n a n a No No n a n a Handel C Language Reference Manual Celoxica Pipelined on chip SSRAM timing diagrams The timing diagrams below illustrate the difference between pipelined accesses to SSRAM and non pipelined accesses The non pipelined RAM can be transformed into a pipel
147. de is valid as a define pre processor macro but not as a macro procedure define test x y if x y lt lt 2 not valid as a macro procedure as not a complete statement test a b ATT else DFE Incomplete statements will not compile as macro procedures www celoxica com Page 146 Handel C Language Reference Manual Celoxica macro proc test x y if x l y lt lt 2 Incomplete statement will not compile A complete statement will not successfully replace an incomplete one macro proc test x y if xl y lt lt 2 Complete statement will compile test a b will expand to if x y lt lt 2 att else this else has no associated if Das Here the macro procedure is not defined to be a complete statement so the Handel C compiler generates an error This restriction provides protection against writing code which is generally unreadable and difficult to maintain S INN www celoxica com Page 147 Handel C Language Reference Manual Celoxica 8 Introduction to timing A Handel C program executes with one clock source for each main statement It is important to be aware exactly which parts of the code execute on which clock cycles This is not only important for writing code that executes in fewer clock cycles but may mean the difference between correct and incorrect code when using Handel C s parallelism Experienced programmers can immediately tell which instructions ex
148. ded on the FPGA PLD by a factor of 3 The third option shows a clock divided by 3 with no pin number specified When the pin number is omitted the place and route tools will choose an appropriate pin Omitting pin specifications can speed up the clock rate of the design You can also define an interface that reads an external clock If the clock is associated with a specific pin you can use the interface sort bus_in You would only need to do this if the external clock has been divided otherwise you can use the intrinsic __ clock Example interface bus_in unsigned 1 in with clockport 1 InputBus with data Pinl set clock external_divide Pini 4 You can now use InputBus in to get an undivided external clock 9 1 2 Internal clocks fed from expressions You can set the clock to be any expression or any expression divided by a given factor set clock internal lt Expression gt set clock internal_divide lt Expression gt factor The clock division factor specified with the internal_divide keyword must be a constant integer Example This allows you to set the clock to a value read from an interface interface port_in unsigned 1 clk with clockport 1 ClockPort set clock internal ClockPort clk S INN www celoxica com Page 168 Handel C Language Reference Manual Celoxica 9 2 Current clock The current clock used by a function can be referenced using the keyword _ clock This allows the funct
149. differential 294 I O standards supported 289 296 BOF EE 262 IOdentfere cece cece ee eeeeeeeeeeeeeenees 314 W EE 84 L en 132 implicit Comperes cece eee cece ee eee 107 le AT scl EE 137 indirection operator ccceee cece ees 43 indirection techniques 66 39 43 inferring widths eee ee eeees 33 WATTS EE N E E sean 269 initialization ccc cece cece eee eeee ees 59 73 MPRAM 59 RAM and ROM 54 210 211 structures 36 variables 73 ENEE 64 68 INDUt esantis 220 221 269 290 294 clocked 221 files 269 latched 220 Standards 286 290 294 Lei SE 31 Page 340 Handel C Language Reference Manual COO EE 31 315 constants 315 range 31 syntax 315 Interface ANEN 49 50 52 218 bidirectional buses 221 222 224 bus interfaces 219 220 221 222 224 customized 218 242 debugging 228 declaration 49 51 definition 50 52 format 242 generic 218 242 overview 49 pointers 42 port_ interfaces 241 simulating 228 sorts 218 Specification 50 52 syntax 318 types 218 interfacing eens 177 218 241 with external hardware 218 with external logic 218 241 with memory 186 213 with the simulator 177 Internal clocks c cece ee eee ees 160 161 internal RAM and ROM 54 Internal divide cceee es 160 161 MUNG EN 269 270 Iete Ate n HE ER inverted docke 193 196 273 Kier e 15 25 calling from Handel C 65 compared to Handel C 15 25 KEY WOl OS ti cineniot esi tinaece
150. drineapedertats 309 Celoxica ie SE language EE 9 language summary 9 15 25 309 language SYNTAX ccs cece cece eee teens 309 Fei ME 220 register 220 IALCNCY EEN 48 157 169 O S e 102 OSS Aa EE 106 less than or equal to 106 OE acy I WEEN 137 line Control 306 HAESSDIICING WEE 307 IOC ie gll EE 264 locating the clock ccceeeeeeeees 160 OG IC el e RE 154 reducing 154 IOGIC Dvpes cece ccc cece ee eseeeeeeeeeeeeeeees 31 logical operators cece cece eee eee 107 ONG EE 32 Jee e GE 20 85 86 89 149 combinational 149 do while 86 for loops 86 termination 89 while loops 85 LVCMOS I O standard286 289 291 292 1 2V 286 292 1 5V 286 292 1 8V 286 291 2 5V 286 291 3 3V 286 291 LVDCI I O standard 265 286 289 292 1 5V 286 1 8V 286 2 5V 286 3 3V 286 S INN www celoxica com Page 341 Handel C Language Reference Manual split termination 265 286 LVDS I O standard 286 289 292 294 LVPECL I O standard 286 289 293 294 LVTTL I O standard 286 289 293 macro expressions71 130 131 133 135 136 in widths 71 macro procedures ssseesn 138 139 MACTOS 0005 111 130 131 138 303 compared to functions 111 113 114 differences to ANSI C 19 examples 114 introduction 130 parameterized 131 138 preprocessor 303 recursion 133 135 136 substitution 303 307 syntax 317 Main function ENNEN AN 9 MAOC erreren a e a A 22 m
151. dual busformat specification 12 7 Specifying the clock pin for SSRAM The clk specification is used for external SSRAM or ROM declarations for EDIF VHDL or Verilog output It specifies the pin s that carry the RAM ROM clock to the external SSRAM ROM To use this specification you must be using the external_divide or internal_divide clock types with a division factor of 2 or more and you must use the wclkpos rclkpos and clkpulselen specifications to define the clock that will appear at the specified pin s S INN www celoxica com Page 268 Handel C Language Reference Manual Celoxica Example set clock external_divide Cl 4 ram unsigned 4 ExtSyncMem 32 with OTT Chip 1 wclkpos 2 5 rclkpos 2 5 clkpulselen 1 clk 1 P22 westart 2 welength 1 we P23 cs P24 oe P25 4 F void main void d Static unsigned index Static unsigned data ExtSyncMemLindex data etc data ExtSyncMem Lindex etc The clock pattern defined by the wclkpos rclkpos and clkpulselen specifications appears at pin P22 The write enable strobe defined by westart and welength appears at pin P23 12 8 clockport specification The clockport specification can be used when declaring a port on an interface or when declaring a clock You can use it for EDIF VHDL or Verilog output Port declaration You can use the clockport specification to indicate that a port on an interface is
152. duce undefined results Example of disallowed condition evaluation ram unsigned int 8 x 4 if xXL0 0 xL1 1 double access disallowed This code is illegal because the condition evaluation must read from element 0 of the RAM in the same clock cycle as the assignment writes to element 1 Similar restrictions apply to while loops do while loops for loops and switch statements I ncorrect execution with conditional operator This code will not execute correctly because of the double access x y gt z RamA 1 RamA 2 The solution is to re write the code as follows x RamALy gt z 1 2 Here there is only a single access to the RAM so the problem does not occur Arrays of variables do not have these restrictions but may require substantially more hardware to implement than RAMs depending on the target architecture S INN www celoxica com Page 105 Handel C Language Reference Manual Celoxica 6 4 assert assert allows you to generate messages at compile time if a condition is met The messages can be used to check compile time constants and help guard against possible problematic code alterations The user uses an expression to check the value of a compile time constant and if the expression evaluates to false an error message is sent to the standard error channel in the format filename line number start column end column Assertion failed user defined error string The default error
153. duces one result per clock cycle with a latency of 8 clock cycles This means that although any one result takes 8 clock cycles you get a throughput of 1 multiply per clock cycle Since each pipeline stage is very simple combinational logic is shallow and a much higher clock rate is achieved than would be possible with a complete single cycle multiplier At each clock cycle partial results pass through each stage of the multiplier in the sum array Each stage adds on 2 multiplied by the b operand if required The LSB of the a operand at each stage tells the multiply stage whether to add this value or not Stages are generated with a macro procedure instantiated several times using a replicator Operands are fed in on every clock cycle through aL0 and bL0 Results appear 8 clock cycles later on every clock cycle through sum 7 e A www celoxica com Page 166 Handel C Language Reference Manual Celoxica 9 Clocks overview You can have multiple clocks interfacing with your design Each main function must be associated with a single clock If you have more than one main function in the same source file they must all use the same clock Clocks may be fed from expressions internal clocks or fed from a pin external clocks The current clock may be referred to using the keyword _ clock You can specify the maximum delay in MHz allowed between components fed from a clock by using the rate specification The general syntax of the
154. e The pull specification allows you to create a pull up or pull down resistor for bus pins The speed specification allows you to specify the slew rate for the output buffer on pins The extern language construct is the same as that found in C It allows you to connect to blocks of ANSI C or C code for co simulation Bit manipulation Handel C types are not constrained to a specific width so you can specify the exact width needed for a variable to minimize hardware usage Bit manipulation is required to connect objects of different widths In addition to the ANSI C bit manipulation operators e A www celoxica com Page 34 Handel C Language Reference Manual Celoxica Handel C provides the take and drop operators which take and drop the least significant bits of a variable and the concatenation operator to extend variable width The bit selection operator allows you to select individual bits of a variable l www celoxica com Page 35 Handel C Language Reference Manual Celoxica 4 Declarations 4 1 Introduction to types Handel C uses two kinds of objects logic types and architecture types The logic types specify variables The architecture types specify variables that require a particular sort of hardware architecture e g ROMs RAMs and channels Both kinds are specified by their scope static or extern their size and their type Architectural types are also specified by the logic type that uses them Both
155. e constant For example macro expr four 8 2 unsigned int 8 x unsigned int 4 y unsigned int 4 Z x QxC x lt four z x 4 This results in y being set to 7 and z being set to 12 or OxC in hexadecimal 6 5 3 Concatenation operator The concatenation operator joins two sets of bits together into a result whose width is the sum of the widths of the two operands For example e A www celoxica com Page 109 Handel C Language Reference Manual Celoxica unsigned int 8 x unsigned int 4 y unsigned int 4 Z y Hat z 0x7 X y z This results in x being set to OxC7 The left operand of the concatenation operator forms the most significant bits of the result You may also use the concatenation operator to zero pad a variable to a given width unsigned int 8 x unsigned int 8 y unsigned int 16 z width of zero constant inferred to be 8 bits z 0 x 0 y If you want to use sign extension you need to copy the 1 or the 0 from the most significant bit into the new bits For example Signed int 8 1 Signed int 12 j j il7 iL7 iL7 iL7 i 6 5 4 Bit selection Individual bits or a range of bits may be selected from a value by using the operator Bit O is the least significant bit and bit n 1 is the most significant bit where n is the width of the value For example unsigned int 8 x unsigned int 1 y unsigned int 5 Z 0b01001001 xL4 Sek Z This results i
156. e 130 Handel C Language Reference Manual Celoxica set clock external P1 unsigned 1 check short int a short int b unsigned 1 4chk const short int const Short int unsigned 1 addeven const short int x const short int y unsigned 1 minuseven const short int x const short int y unsigned 1 diveven const short int x const short int y unsigned 1 modeven const short int x const short int y void main void short int m n unsigned 2 choice unsigned 1 result unsigned pyCconst short const short par m 19 n 47 do d Switch choice case 0 p addeven break case l p minuseven break case 2 p diveven break case 3 p modeven break default delay l www celoxica com Page 131 Handel C Language Reference Manual Celoxica break par result check amp m Am p CholCcer while choice unsigned 1 check short int a short int b unsigned 1 lt chk const short int const short int return chk a b unsigned 1 addeven const short int x const short int y return unsigned x y 0 unsigned 1 minuseven const short int x const short int y return unsigned x y 0 unsigned 1 diveven const short int x const short int y return unsigned kx y 0 unsigned 1 modeven const short int x const short int y d return unsigned x y 0 The
157. e Flow through SSRAM e Targeting external synchronous RAMs Se www celoxica com Page 290 Handel C Language Reference Manual Celoxica 12 27 resolutiontime specification The resolutiontime specification specifies the maximum time in nanoseconds for metastability to resolve in the channel synchronization hardware It is needed when you are using channels to communicate between multiple clock domains The higher the value for resolutiontime the less time will be available within a clock tick for combinational logic in the synchronizer This only matters if you have set paranoia to 0 p mmm p EE les Minperiod i period Its value must be less than clock period x paranoia where paranoia is gt O If paranoia has been set to 0 you should use minperiod rather than resolutiontime Either resolutiontime or minperiod may be set but not both Achieving a given value of resolution time If you need a higher value of resolution time you can increase the value of the paranoia specification The resultant value for minperiod will be clock period resolutiontime paranoia RESOLUTI ON TI ME SUMMED OVER THREE CLOCK TICKS WHEN PARANOIA 3 12 28 retime specification In some circumstances it is desirable to prevent some flip flops in a circuit from being moved by the retimer This often occurs when writing interfaces to devices external to www celoxica com Page 291 Handel C Language Reference M
158. e a reference voltage of 0 9 V and a termination voltage of 1 5 V All four classes require an input output source voltage of 1 5 V This standard requires a Differential Amplifier input buffer and a Push Pull output buffer HyperTransport HyperTransport technology is a differential high speed high performance I O interface Standard It is a point to point standard requiring a 2 5 V VCCIO in which each HyperTransport technology bus consists of two point to point unidirectional links Each link is 2 to 32 bits The HyperTransport technology standard does not require an input reference voltage However it does require a 100 ohm termination resistor between the two signals at the input buffer LVCMOS 3 3 V 3 3 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard and is defined in J EDEC Standard JESD 8 A Interface Standard for Nominal 3 0 V 3 3 V Supply Digital Integrated Circuits This is a single ended general purpose standard also used for 3 3V applications It uses a 5V tolerant CMOS input buffer and a Push Pull output buffer This standard requires a 3 3V input output source voltage but does not require the use of a reference voltage or a board termination voltage LVCMOS 2 5 V 2 5 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard and is documented by J EDEC Standard JESD 8 5 2 5 V 0 2 V Normal Range and 1 7 V to 2 7 V Wide Range Power Supply Voltage and Interface Standard for
159. e blocks A code block is denoted with brackets This means that e Global variables must be declared outside all code blocks e An identifier is in scope within a code block and any sub blocks of that block The scope of variables is illustrated below int w void main yvoid d int x d Wt y DK EE x I d Tt 2 SKS e i I Since parallel constructs are simply code blocks variables can be in scope in two parallel branches of code This can lead to resource conflicts if the variable is written to Simultaneously by more than one of the branches Handel C states that a single variable must not be written to by more than one parallel branch but may be read from by several parallel branches If you wish to write to the same variable from several processes the correct way to do so IS by using channels which are read from in a single process This process can use a prialt statement to select which channel is ready to be read from first and that channel is the only one which will be allowed to write to the variable e A www celoxica com Page 15 Handel C Language Reference Manual Celoxica while 1l Priati case chanl y break case chanz y break case chan3 y break In this case three separate processes can attempt to change the value of y by sending data down the channels chanl chan2 and chan3 y will be changed by whichever process sends the data first ES A single variable sh
160. e bus 0 Clear the read strobe Data Read Write one word back to external device Reg Data 1 while WriteReady wr 0 delay par En 1 Drive the bus Write 1 Set the write strobe Write 0 Clear the write strobe En 0 Stop driving the bus Writing data You can change the values on the output buses by setting the values of the Data Write and Read variables You can drive the data bus with the contents of Data by setting En to 1 The variables that drive buses have been initialized to 0 That means that these variables must be static or global This may be important when driving write strobes Care should be taken during configuration that the FPGA pins are disconnected in some way from the external devices because the FPGA pins become tri state during this time The main program The main program reads a word from the external device before writing one word back www celoxica com Page 234 Handel C Language Reference Manual Celoxica void main void int 4 Data Reg Read word from external device while ReadReady readySignal 0 delay Read 1 Set the read strobe par Data dataB DataIn Read the bus Read O Clear the read strobe Write one word back to external device Reg Data 1 while WriteReady wr 0 delay par En 1 Drive the bus Write 1 Set the write strobe Write D Clear the write strobe En QO Stop drivin
161. e conflicts for example to prevent two accesses to one RAM in a single clock cycle or to adjust execution timing delay can also be used to break combinational logic cycles 5 6 11 try reset try reset allows you to perform actions on receipt of a reset signal within a specified section of code You can form the same kind of construct with other control statements but this requires more complex code and therefore more hardware Syntax try statements reset condition statements During the execution of statements within the try block if condition is true the reset statement block will be executed immediately else it will not The condition expression is continually checked If it occurs in the middle of a function execution will immediately go to the reset thread Static variables within the function will remain in the state they were in when the reset condition occurred Variables and RAMs will not be re initialized e A www celoxica com Page 97 Handel C Language Reference Manual Celoxica Examples void main void interface bus_in int 1 input resetbus try someFunction reset resetbus input 1 cleanUpSomeFunction If you have nested try reset statements and more than one try condition is true only the outermost reset statement is executed For example www celoxica com Page 98 Handel C Language Reference Manual unsigned 4 a s t xX y Static unsigned 1 conditio
162. e function within the plugin If parameters must be passed to the dl11 instance they can be done so in the string A new instance of the plugin will be generated for each unique extinst string Examples interface bus_out MyBusOut outPort MyOutExpr with extlib pluginDemo dl1 extinst 0 extfunc MyBusOut interface TITL 446 unsigned 7 segments unsigned 1 rbon decode unsigned 1 Itn ItnVal unsigned 1 rbin rbinVal unsigned 4 digit digitVal unsigned 1 bin binVal with extlib PluginModelSim dll extinst decode model IITL 446_wrapper delay 1 e A www celoxica com Page 274 Handel C Language Reference Manual Celoxica 12 12 extpath specification The extpath specification is used when connecting a Handel C interface to external black box logic It is valid for any DK output extpath is used during simulation to tell the simulator about ports within the black box so that it Knows what order to update the ports in It specifies that a Handel C output port on an interface will have direct logic connections via the black box to one or more input ports on the same interface Its usage is portName with textpath portNameList portNameList is a comma separated list of port names Example interface blackBox int 1 Two int 1 Four bbl int 1 One out with extpath bb1 Two int 1 Three bb1 Two with extpath bb1 Four This example tells the compiler that there are direct connections within the bl
163. e is no padding in Handel C so nothing can be assumed about it e A www celoxica com Page 45 Handel C Language Reference Manual Celoxica Syntax struct tag_name field_Type field_Name field_Width Linstance_names Example This example defines an identical array of flags as a structure and as a bit field struct struct re d unsigned int 1 LED unsigned int 1 value unsigned int 1 state outputs Struct bitfield unsigned int LED 1 unsigned int value l unsigned int state 1 signals 4 3 Pointers A pointer declaration consists of the name of the pointer and the type of the variable that it points to type Name Pointers are used to point to variables in conjunction with the unary operator amp which gives the address of an object To set a pointer to point to a variable you assign the address of the variable to the pointer For example Int 8 ptr declare a pointer to an int 8 int 8 object x object 6 x 10 ptr amp object assigns address of object to ptr x sours x is now 6 sptr 12 object is now 12 LULA www celoxica com Page 46 Handel C Language Reference Manual Celoxica EN The behaviour of uninitialized pointers is undefined De referencing an uninitialized pointer during simulation will result in a run time error after which the simulator will terminate Casting pointers In Handel C you may only cast void point
164. e is referenced through a pointer struct 5 Sp gt b sp gt a The last line accesses the member variables of structure s through pointer sp Because the pointer is being used to access the structure the gt operator is used to refer to the member variables Sp gt a sp q You can cast structure pointers between structures with the same member types and names For example ee www celoxica com Page 49 Handel C Language Reference Manual Celoxica struct lt il int O X PSLI struct S2 int 6 x Pols set clock external void main void d int r struct s1 stiructPtri struct 52 structPtrz StructPtrl amp stl structPirz struct 52 JSTPUCTPUPI structPtr2 gt x 7 Stl xe E 7 4 3 5 address and indirection operators The indirection operator is the same as it is in ANSI C It is used to de reference pointers i e to access objects pointed to by pointers The address operator amp works as it does in ANSI C The following can also be used pointers to arrays pointers to channels pointers to Signals pointers to memory elements pointers to structures pointers to pointers arrays of pointers Example pointer assignment unsigned char cha chb chp chp amp cha cha 90 ch ere chp amp chb The first line declares two unsigned variables cha and chb and a pointer to an unsigned chp The second line assigns the address of cha to pointer chp In
165. e standard specification on external bus interfaces connected to pins not port_in or port_out to select whether Digital Controlled Impedance is to be used on all pins of that interface You can also use it with the standard specification when declaring external clocks The dci specification may also be applied to off chip memories The specification is only valid for EDIF and is ignored for all other outputs The only devices that currently support DCI are Xilinx Virtex Il Virtex II Pro Virtex 4 and Spartan 3 3E 3L For more information on DCI please refer to the Xilinx Data Book If you have used the clockport specification and set it to 0 dci specifications will be ignored The default for clockport ts 1 NN www celoxica com Page 272 Handel C Language Reference Manual J i Celoxica Standards supporting dci are GTL GTL HSTL Class HSTL Class II HSTL Class III HSTL Class IV LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 SSTL2 Class SSTL2 Class II SSTL3 Class SSTL3 Class The possible values for the dci specification are No DCI default DCI with single termination O e O wo DCI with split termination This can only be used with LVCMOS standards If dci is used on a device or standard that does not support it a warning is issued and the specification is ignored Examples Use dci on all pins interface bus_out Eel int 4 outPort x with data dataPinsO standard HSTL_I dci 1 Use dci for clock
166. e summary of statement timings for more detail 8 1 2 Statement timing summary l www celoxica com Page 154 Handel C Language Reference Manual Celoxica Statement bce par Function break goto continue return Expression Variable Expression Variable Variable Variable Variable Variable Expression Variable Expression Variable Expression Variable Expression Variable Expression Variable lt lt Constant Variable gt gt Constant Variable amp Expression Variable Expression Variable Expression Channel Variable Channel Expression if Expression else while Expression do while Expression for Init Test Iter legad switch Expression Timing Sum of all statements in sequential block Length of longest branch in block No clock cycles 1 clock cycle if Expression is assigned on return otherwise none 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle 1 clock cycle when transmitter is ready in same clock domain 1 clock cycle when receiver is ready in same clock domain Length of executed branch Length of loop body number of iterations Length of loop body number of iterations Length of Init
167. e the signal only holds the value assigned to it for a single clock cycle if it is read from just before or just after it is assigned to you get its initial value For example e A www celoxica com Page 70 Handel C Language Reference Manual Celoxica int 15 a bD static signal lt int gt sig 690 a 7 par sig e r Db SEI gz ST Here b is assigned the value of a through the signal as before Since there is a clock cycle before the last line a is finally assigned the signal s initial value of 690 4 12 Storage class specifiers Storage class specifiers define how variables are accessed extern and static are used within functions to allocate storage static gives the declared objects static storage class and extern specifies that the variable is defined elsewhere For compatibility with ANSI C the specifiers auto and register can be used but have no effect The expansion of a function is defined by the specifier inline The typedef specifier does not reserve storage but allows you to declare new names for existing types 4 12 1 auto auto defines a local automatic variable In Handel C all local variables default to auto You cannot initialize an auto variable but must assign it a value The initialization status of auto variables is undefined Example set clock external P1 void main void auto 8 pig pig 15 S INN www celoxica com Page 71 Handel C Language Reference Man
168. e use of a reference voltage or a board termination voltage is not required but a 100 ohm termination resistor is required between the two traces at the input buffer S INN www celoxica com Page 299 Handel C Language Reference Manual Celoxica LVPECL Low Voltage Positive Emitter Coupled Logic LVPECL is a differential I O standard It requires that one data bit be carried through two signal lines The LVPECL standard is similar to LVDS In LVPECL the voltage swing between the two differential signals is approximately 850 mV The use of a reference voltage or a board termination voltage is not required but an external termination resistor is required LVTTL Low Voltage TTL The Low Voltage TTL or LVTTL standard is a single ended general purpose standard for 3 3V applications that uses an LVTTL input buffer and a Push Pull output buffer The LVTTL interface is defined by JEDEC Standard J ESD 8 A Interface Standard for Nominal 3 0 V 3 3 V Supply Digital Integrated Circuits This standard requires a 3 3V output source voltage but does not require the use of a reference voltage or a termination voltage PCI 33 MHz 3 3 V amp PCI 66 MHz 3 3 V 3 3 Volt PCI The PCI standard specifies support for 33 MHz 66 MHz and 133 MHz PCI bus applications It uses a LVTTL input buffer and a Push Pull output buffer This standard requires a 3 3V input output source voltage but not the use of input reference voltages or termination P
169. e write enable strobe within the Handel C clock cycle If they are used in the absence of SRAM clock specifications rclkpos wclkpos and clkpulselen they force the generation of an asynchronous memory or memory port The specifications may be given to internal or external RAM declarations You can only use these specifications together with external_divide or internal_divide clock types with a division factor greater than 1 If you have an undivided clock use the wegate specification instead westart and welength are valid for EDIF VHDL and Verilog output westart Is used to specify the starting position of the write enable strobe and welength is used to specify its length For both of these specifications a unit value corresponds to a single cycle of the fast clock which has been divided in order to generate the Handel C clock The size of welength and westart can be given in multiples of 0 5 but westart welength must not exceed the clock divide e A www celoxica com Page 307 Handel C Language Reference Manual Celoxica You can apply the specification to the whole of a RAM or MPRAM or to individual write ports within a memory Specifications applied to the whole memory will apply to each port that does not have its own specification Examples applying the specifications to the whole RAM set clock external_divide P 8 4 ram unsigned 6 xL34 with twestart 1 welength 1 5 fast undivided clock 0 1 2 3 0
170. ecute on which clock cycles This information becomes very important when your program contains multiple interacting parallel processes Knowing about clock cycles also becomes important when considering interfaces to external hardware It is important to understand timing issues before moving on to implementing such interfaces because it is likely that the external device will place constraints on when signals should change Avoiding certain constructs has a dramatic influence on the maximum clock rate that your Handel C program can run at 8 1 Statement timing The basic rule for working out the number of cycles used in a Handel C program is Ee Assignment and delay take 1 clock cycle Everything else is free e One clock cycle is used every time you write an assignment statement or a delay statement releasesema also uses one clock cycle A special case statement is supported of the form a f x to allow function calls which take multiple clock cycles e Channel communications use one clock cycle in the same clock domain if both ends are ready to communicate If one of the branches is not ready for the data transfer then execution of the other branch waits until both branches become ready e You can write any other piece of code and not use any clock cycles to execute it 8 1 1 Example timings Statements X y SES EK ae W a yae S INN www celoxica com Page 148 Handel C Language Reference Manual Celoxica
171. ed output SSRAMs perform a late late write cycle This means that data is written to memory two clock cycles after the address is sampled GH www celoxica com Page 215 Handel C Language Reference Manual Celoxica The timing diagram shows the complete cycle Fast clock CLK Handel C clock HELK die Ai RAM clock RAMCLK welkpos lid Sat elkpuls en 0 5 RAY westart 1 5 welength 1 0 ADDRESS DAT AIN t t 1 t 2 t 3 ti tl 1 ti 2 The HCLK rising edge at tO initiates the write cycle causing the ADDRESS and DATAIN Signals to change Three cycles of RAMCLK are needed to clock the new data into the RAM at the specified address the first to sample the address and the third to sample the data Since you will not read from the RAM on a write strobe you can sample the data as late as possible to give the circuit maximum time to set up the data In this case the three rising edges of RAMCLK occur at t0 1 5 t0 2 5 and t0 3 5 The write enable signal must be low during the rising edge of RAMCLK that samples the address but not during the one that samples the data This can be done by setting westart and welength as shown The entire cycle completes within a single Handel C clock cycle 10 3 3 Targeting Stratix and Cyclone memory blocks Altera Stratix Stratix GX and Stratix II devices have 3 types of embedded memory M512 M4K and M RAM Cyclone and Cyclone II devices only have M4K You
172. edinedesentecereniseesuieeweneeeseeenieewieeeeweuns 167 a deiert Elei 168 9 1 2 Internal clocks fed from exvptreselons cece cece eee eeee seen ee eeeeeeeneeenennenenes 168 9 2 CURRENT CLOCK EE 169 9 3 MULTIPLE CLOCK DOMAINS unenee E RER EK KREE KREE EE KREE E KREE EK ERR KKK ke 169 9 3 1 Channels communicating between clock domaine 169 9 3 2 Simulating Multiple clock domaine 183 10 TARGETING HARDWARE AND SIMULATION uvscssessccsneesceneeesecneeseennueesonas 184 10 1 INTERFACING WITH THE SIMULATOR nee ke KEE KEE KEE KEE EE EEN 184 10 1 1 Simulator input file format 185 101 2 BlOCK data EE 185 10 2 TARGETING FPGA AND PLD DEVICES ane KEE E KEE KEE EK Ek KEN 186 10 2 1 Summary Of SUPPOrted CEVICES cece eee eeee esse e Ei 187 10 2 2 Detecting the current device Tam 189 10 2 3 Targeting specific devices via source Code 190 10 24 SPeEcIrVING E OlODal EE 193 10 3 USE OF RAMS AND ROMS WITH HANDEL C sees ere KKK KEE KEN 193 10 3 1 Asynchronous E EE 194 10 32 SYVMCAVOMOUS EE 200 10 3 3 Targeting Stratix and Cyclone memory DIOCKS cc ccc ceceee seen ee eeeeeeenes 216 10 3 4 Using on chip RAMs in Actel devices cece eee eeeeeeeeeeeeeeessenenaes 217 10 3 5 Using on chip RAMs in Altera devices ccc ccc cc cece cece cece eeeeeeeeeeeeeeseanenaes 218 10 3 6 Using on chip RAMS in Xilinx devices cc ccccceee cece cece eee eeeeeeeeeeeeeeeeeananes 219 VO ct Using CX er ail EE 219 10 3 8 Connecting to RAMS in foreign Code 220
173. eeeeeeneenas 53 45 2 Arrays OL Channels acicatcntae va oucresexoninsdarcepetetieneanntensudsantteunmee een 53 4 5 3 Restrictions on Channel ACCESSES c cece ce cece ence eee eeeeeeeeeeeeueeseueeneueenenngs 53 4 5 4 Timing and latency IN FIFOS cece ccccc eee e eee e eee e ee eeeeeeeeeeeeeeeeeeeneneeeeeeeengs 55 4 6 INTERFACES OVERVIEW eege 56 4 6 1 Interface declaration TEE 56 E EENHEETEN eet ee EE EEE ETRE EE NEE EE a EE 57 4 6 3 Example interface to external code 58 4 6 4 Interface specifications NENNEN 59 4 7 RAMS AND Lei LN 61 AF A Aale TE e a MER 61 4 7 2 INFErring SIZE MOM use ENNEN ENNEN 62 4 7 3 Accessing RAMS and ROMS cccccceceeee eee e eee eeeeeeeeeeeeeeeeeeeeeeeeeneeeeeennegs 62 4 7 4 Differences between RAMS and arrave 62 4 7 5 RAM and ROM support on different devices cece cece cece ee eee ee eeeeeeeeeeeeeeags 63 4 7 6 Multidimensional memory artaye sees eee e cece eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeengs 63 4 8 MPRAM MULTI PORTED RAMS aseene Ke Ke KEN KEREN KEN KEN E KEN 64 48 1 initialization Of INDLGINS aciavins Grncrenria eran ra a EEEN EEA va RE EAn ai 66 4 8 2 Mapping of different width mpram porte 66 4 8 3 mprams evample cc cccccccccce eee e eee e eee ee eeee sees eee eeeeeeeeneeeeeeeeeeeeegeaeeeeeeeeanas 68 4 9 WOM WRITE ONLY MEMORY ssssssssssunnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 69 AO SEMA E E E E E 69 Sp ee TN BEN 70 4 12 STORAGE CLASS SPECI FI ERS wen xn Kn Ke KKK KE KE KEEN KE
174. efined specify a variable of undefined width union Reserved Not valid in Handel C unsigned declare an unsigned variable void specify void return type volatile declare volatile variable while loop statement width return integer width with specify interface signals channels RAM and ROM types variables etc wom declare a WOM array The following character sequences are also reserved ay A L 14 3 Constant expressions The following constants are available in Handel C e Identifiers e Integer constant e Character constants e String constant e Floating point constants 14 3 1 Identifiers syntax identifier letter letter 0 9 letter A Z a Z Celoxica No No Yes No No Yes Yes Yes Yes Yes No No No S INN www celoxica com Page 321 Handel C Language Reference Manual Celoxica 14 3 2 Integer constants syntax integer_constant 1l 9 4 0 9 E 0x OX 0 9 A F a f t L Cas cad L 0b 0B 0 1 14 3 3 Character constants syntax character is any printable character or any of the following escape codes Escape code ASCII value Meaning a 7 Bell alert b 8 Backspace VI 12 Form feed t 9 Horizontal tab n 10 New line VV 11 Vertical tab r 13 Carriage return Double quote mark VU A String terminator KS Backslash Single quote mark Vi Question mark 14 3 4 Strings syntax String ch
175. els and mprams 7 1 6 Recursion in macros and functions Macros can be recursive in Handel C but due to the absence of a stack in Handel C functions cannot be recursive The depth of recursion though unbounded must be determinable at compile time 7 2 Introduction to functions Functions are similar to functions in ANSI C A function is compiled to be a single shared piece of hardware much as a C compiler generates a single shared block of machine code Handel C has been extended to provide arrays of functions and inline functions Arrays of functions provide multiple copies of a function You can select which copy is used at any time Inline functions are similar to macros in that they are expanded wherever they are used You may also use a macro proc a parameterized macro procedure Functions take arguments and return values A function that does not return a value Is of type void Valid return types are integers and structs The default return type Is int undefined Functions that do not take arguments have void as their parameter list for example void main void As in ANSI C function arguments are passed by value This means that a local copy is created that is only in scope within the function Changes take place on this copy To access a variable outside the function you must pass the function a pointer to that variable A local copy will be made of the pointer but it will still point to the same variable This
176. ement int a 8 not allowed int a a 8 OK Static int a 8 OK The Handel C typeof operator allows you to determine the type of an object at compile time 3 6 2 Handel C v C floating point variables There are no floating point types float double or long double in Handel C Floating point arithmetic is more complex than integer or fixed point arithmetic and tends to require more hardware If you are porting C code to Handel C check if there is a way to avoid using floating points For example you might be able to use fixed point values which have a binary point or to change the units to remove the decimal places e g uSe pence or cents instead of pounds or dollars If you do need to use floating point arithmetic use the Celoxica floating point library This allows you to specify the exact width of the mantissa and exponent You can download the floating point library from the downloads section of the Celoxica support web site If you can use fixed point arithmetic use the Celoxica fixed point library This is provided in the Platform Developer s Kit S INN www celoxica com Page 23 Handel C Language Reference Manual Celoxica 3 6 3 Handel C v C variable widths and casting Handel C widths Handel C types are not limited to specific widths When you define a Handel C variable you should specify the minimum width required to minimize hardware usage For example if you have a variable x that can ho
177. ength as shown The entire cycle completes within a single Handel C clock cycle Pipelining off chip SSRAM example This method of pipelining SSRAM is most suitable for off chip RAMs For on chip SSRAM it is usually more efficient to use a pipelining transformation ram unsigned 18 PipeBank 1024 with block 1 westart 1 5 welength 1 rclkpos 1 55 2 5 wclkpos 1 5 2 5 3 5 clkpulselen 0 5 S INN www celoxica com Page 214 Handel C Language Reference Manual Celoxica Read cycle for a pipelined output SSRAM The timing diagram shows the read cycle Fast clock CLK Handel CC clack HELK div 4 RAM clock RAMCLK relkpos 1 5 2 5 clkpulsen 0 5 RAY westart 1 5 elkpulsen 1 0 ADDRESS DATAOQUT t t 1 t 2 t 3 ti t1 1 t1 2 This read cycle is very similar to that for a flow through RAM The rising HCLK edge at tO initiates the read cycle Some time later the address A1 is set up which is sampled somewhere near the middle of the HCLK cycle t0 1 5 in this case The RAM contents at address Al are then piped to the RAM s output register it must be made available at the RAM output A second RAMCLK pulse at t0 2 5 in this case is used to do this By the time the next HCLK rising edge occurs at t1 the data is available for reading by the Handel C design The cycle completes within one Handel C clock cycle Write cycle for a pipelined output SSRAM Pipelin
178. equired for every expression in the whole program This can mean that large parts of the hardware are idle for long periods Shared expressions allow hardware to be shared between different parts of the program to decrease hardware usage The shared expression has the same format as a macro expression but does not allow recursion You can use recursive macro expressions or let in to generate recursive shared expressions S INN www celoxica com Page 142 Handel C Language Reference Manual Celoxica Example dapa e d e f Sn 13 This code generates three multipliers Each one will only be used once and none of them simultaneously This is a massive waste of hardware You can improve the hardware efficiency with a shared expression shared expr mult x y x y a m lt b d mult e f g multch T In this example only one multiplier is built and it is used on every clock cycle If speed is required you can build three multipliers executing in parallel Warning It is not always the case that less hardware is generated by using shared expressions because multiplexors may need to be built to route the data paths Some expressions use less hardware than the multiplexors associated with the shared expression 7 3 8 Using recursion to generate shared expressions Although shared expressions cannot use recursion directly macro expressions can be used to generate hardware which can then be shared using a share
179. erfacing with your design by specifying more than one main function If you want to simulate code you can set a dummy clock You can specify the frequency of a clock using the rate specification The clockport specification can be used to assign a dedicated clock input resource on your target device You can also use it to specify that a port on an interface is used to drive the Handel C clock Assignments and delay take one clock cycle in Handel C Everything else is free The delay statement does nothing but takes one clock cycle This can be used to avoid timing conflicts such as combinational loops The intime and outtime specifications can be used to specify the maximum delay between an interface and an element interacting with an interface e g the port reading data into a RAM Compile time selection and expansion and generic code When you write code to target hardware all logic needs to be expanded at compile time This means that you cannot use recursive functions However macro procedures macro expressions and shared expressions allow compile time recursion in combination with the select ifselect and let in constructs The select operator allows you to select between expressions at compile time It is similar to the conditional operator cond exprl expr2 but no hardware is generated for the conditional The ifselect construct is similar to anif else but selects between alternative blocks of code at compile t
180. ern macro_proc_spec identifier L macro_param macro_param statement with initializer macro_expr_decl static extern macro_expr_spec identifier Lmacro_param macro_param L static extern macro_expr_spec identifier L macro_param macro_param let_initializer with initializer macro_proc_Spec Macro proc macro_expr_spec macro expr shared expr let_tnitializer initializer let macro_expr_decl in let_initializer macro_param identifier Se www celoxica com Page 324 Handel C Language Reference Manual Celoxica 14 6 Interfaces syntax interface_declaration interface identifier Lint_parameter_declaration int_parameter_declaration identifier L assignment_expr_spec assignment_expr_spec with initializer interface_type_declarator old_style_interface_declarator interface_type_declarator interface identifier int_parameter_proto int_parameter_proto identifier Lint_init_parameter_declaration i int_init_parameter_declaration This format is deprecated but retained for compatibility reasons old_style_interface_declarator interface identifier Lint_parameter_declaration int_parameter_declaration identifier L assignment_expr_spec assignment_expr_spec with initializer interface static extern interface int_parameter_proto declaration_specifiers declaration
181. ernal components generated by foreign tools You can do this using the busformat specification to a port This allows you to specify how the bus name and wire number are formatted To specify a format you use the syntax with busformat formatString formatstring can be one of the following strings B represents the bus name and I represents the wire number BI B_I BLI BCI B lt gt B specifies a bus BLN 0 B lt N 0 gt or B N 0 Specify a bus of width N 1 e A www celoxica com Page 250 Handel C Language Reference Manual Celoxica Example format B I interface port_in int 4 signals_to_HC with busformat BLI read would produce wires Signals_to_HC 0 Signals_to_HC 1 Signals_to_HC 2 Signals_to_HC 3 Example format B lt I gt ram unsigned 4 raxL4 with ports 1 busformat B lt I gt would produce wires rax_SPPort_addr lt 0 gt Address rax_SPPort_addr lt l gt rax_SPPort_data_in lt 0 gt Data In rax_SPPort_data_in lt l gt rax_SPPort_data_in lt 2 gt rax_SPPort_data_in lt 3 gt rax_SPPort_data_out lt 0 gt Data Out rax_SPPort_data_out lt 1 gt rax_SPPort_data_out lt 2 gt rax_SPPort_data_out lt 3 gt rax_SPPort_data_en Data Enable rax_SPPort_clk Clock rax_SPPort_cs Chip Select rax_SPPort_oe Output Enable rax_SPPort_we Data In aH www celoxica com Page 251 Handel C Language Reference Manual Celoxica 12 Object specifications Handel C pr
182. error error_message This may be useful with conditional compilation if your design only supports certain combinations of parameter definitions 13 7 Predefined macro substitution The preprocessor contains a number of useful predefined macros which may be placed into source code v PIE Expands to the name of the current file being compiled LINE _ Expands to the number of the current source line TIME _ Expands to the current time of compilation in the form hh mm ss DATE _ Expands to the current date of compilation in the form mmm dd yyyy 13 8 Line splicing You can splice multiple lines together by placing a backslash character followed by a carriage return between them This feature allows you to break lines for aesthetic purposes when writing code which are then joined by the preprocessor prior to compilation For example if a macro is defined H define ERRORCHECK error if Cerror 0 H return error The line www celoxica com Page 314 Handel C Language Reference Manual Celoxica ERRORCHECK 1 Expands to if 1 0 return i l www celoxica com Page 315 Handel C Language Reference Manual Celoxica 14 Language syntax The complete Handel C language syntax Is given in BNF like notation The overall syntax for the program is program external_declaration void main void declaration statement Language external_declaration function_definition declarat
183. ers void pointerName to a different type All other pointers may only be cast to change the sign of an object pointed to and whether it is const or volatile These restrictions are the standard casting restrictions in Handel C You can change a void pointer s type by casting assignment or comparison Void must have a consistent type so v id p Int O 7s Ine ER DS p t invalid Pointer arithmetic You cannot perform arithmetic on a void pointer because the size of the object being pointed to is not known e Valid pointer operations are e Assign a pointer to another pointer of the same type e Add a pointer and an integer e Subtract an integer from a pointer e Subtract or compare using lt lt gt or gt a pointer to an array or memory member with another pointer to a member of the same array or memory e Compare two pointers for equality using or e Assign or compare a pointer to NULL The result of subtracting or comparing pointers to members of different arrays or memories or to other objects is undefined The behaviour of arithmetic on pointers that moves the pointer beyond the extent of the object is undefined An exception is that an address one element beyond an array or memory at the high end is valid but it is not valid to dereference a pointer at such an address the behaviour of the dereference would be undefined This one beyond address is useful for loops S INN www celoxica c
184. ese sorts and you supply the instance definition port_in For a port_in you define the port s carrying data to the Handel C code and any associated specifications interface port_in Type data_TO_hc with port_specs Name with Instance_specs For example interface port_in int 4 signals_to_HC read You can then read the input data from the variable Name data_TO_hc in this case read signals_to_HC S INN www celoxica com Page 248 Handel C Language Reference Manual Celoxica port out For a port_out you define the port s carrying data from the Handel C code the expression to be output over those ports and any associated specifications interface port_out Name Type data_FROM_hc output_ExprLwith port_specs with Instance_specs For example int A OUT interface port_out drive int 4 signals_from_HC X_out In this case the width of X_out would be inferred to be 4 as that is the width of the port that the data is sent to Port names The name of each port ina port_in or port_out interface must be different as they will all be built to the top level of the design The examples below would both generate a compiler error Example 1 interface port_in unsigned 1 soggy Inl interface port_in unsigned 1 soggy In2 Example 2 interface port_in unsigned 1 soggy Inl void main void interface port_in unsigned 1 soggy In2 Both examples build two ports to t
185. extinst extlib extfunc 266 extpath 268 fifolength 268 infile and outfile 269 intime and outtime 269 minperiod 167 273 object 245 offchip 274 paranoia 169 275 pin 2 6 ports 2 7 properties 2 8 pull 280 quartus proj assign 281 rate 281 rcikpos 282 retime 284 sc_type 285 show 286 speed 286 standard 286 290 std_logic_vector 295 strength 296 unconstrainedperiod 297 vhdl_type 298 warn 300 wclkpos 282 wegate 300 Celoxica westart and welength 300 EE eege 286 S SRAM geiert din 193 195 261 282 pipelined access 196 198 200 read and write cycles 195 198 SSRAMs 193 195 196 261 timing 195 196 198 200 282 SSTL I O standard 286 289 293 294 SSTL18 Class 286 294 SSTL18 Class ll 286 294 SSTL2 Class 286 293 SSTL2 Class Il 286 293 SSTL3 Class 286 294 SSTL3 Class Il 286 294 Standard specification 286 289 290 AGP 286 290 BLVDS 286 290 CTT 286 290 GTL 286 294 HSTL 286 291 LVCMOS 286 291 292 LVDCI 286 292 LVDS 286 292 LVPECL 286 293 LVTTL 286 293 PCI 286 293 SSTL 286 293 294 Standarde 286 290 294 statements 10 25 75 141 147 321 comparison with ANSI C 25 compound 324 syntax 321 timing 141 147 SAU EE 69 73 initializing static variables 73 std_logic_vector specification 295 Storage class epecifiere cece eee 64 HE www celoxica com Page 346 Handel C Language Reference Manual Stratix Odevices cee 180 183 209 cons
186. first value from the FIFO When the FIFO is full the first branch must wait until the FIFO is read from before it can write to it again The precise timing of FIFOs depends on many different factors The throughput will be close to one word per cycle for sufficiently large FIFOs FIFO channel and FIFO comparison code This example shows a loop using a channel to communicate between two processes S INN www celoxica com Page 152 Handel C Language Reference Manual Celoxica Process A Static unsigned 4 Val 1 while 1 Val Val 2 0 J Val 3 MyChan Val Send delay Process B Static unsigned 4 Count while 1 wait 0 or more cycles while Count 0 Count MyChan Count Receive delay The delay statements in each process always take place on the same clock cycle in the Same clock domain Example with FIFO This shows the same process but using a FIFO with fifolength 4 The loop in process A would execute 4 times without pausing and then run after each time process B reads from the FIFO e A www celoxica com Page 153 Handel C Language Reference Manual Celoxica chan myFIFO with fifolength 4 Process B Static unsigned 4 Count while 1 wait 0 or more cycles while Count 1 Count MyFIFO Count Receive delay Process A Static unsigned 4 Val 1 while 1 Val Val 2 0 Val 3 MyFIFO Val Send delay See th
187. fon Z 3 5 3 Replicated par and seq You can replicate par and seq blocks by using a counted loop a similar construct to a for loop The count is defined with a start point index_Base below an end point index_Limit and a step size index_Count The body of the loop is replicated as many times as there are steps between the start and end points If it is a par loop the replicated processes will run in parallel tf a seg they will run sequentially Syntax par seq index_Base index_Limit index_Count Body The apparent variables used in index_Base index_Limit and index_Count are macro exprs that are implicitly declared index_Base index_Limit and index_Count do not need to be single expressions for example you could declare par i 0 j 23 i 76 i j In this casei and j are implicit macro exprs S INN www celoxica com Page 33 Handel C Language Reference Manual Example par 1 0 163 i ali bli expands to par al0 b 0 a l bL1 a 2 bL2 Replicated pipeline example unsigned init unsigned ql149 unsigned 31 out init 57 par r 0 re Lo PP ifselect r 0 aCe init else ifselect r 15 out qlr 1 else qlr qLr 1 Celoxica ifselect checks for the start of the pipeline the replicator rules create the middle sections and ifselect checks the end The replicated code expands to par q 0 init qL1 qLO0 qi2 ql
188. for Actel devices one port must be read only and one write only e A www celoxica com Page 64 Handel C Language Reference Manual Celoxica e for Altera Apexll and Mercury devices both ports can be bi directional For Cyclone and Stratix devices this depends on the type of memory used For other Altera families one port would be read only and one write only e Altera Mercury devices can have up to four ports You can have one or two write ports AND one or two read ports OR two read write ports Depending on how you have configured the port you can have up to four simultaneous accesses of the same block of memory e for Virtex and Spartanii devices both ports would be read write for block RAM and for LUT RAM one port would be read write and one read only Spartan and SpartanXL devices only have distributed LUT RAM You can use mpram ports of different widths for certain devices The mpram construct allows the declaration of any number of ports Your only restriction is the target hardware You can apply clock specifications to the whole MPRAM or to individual ports MPRAM write ports will be synchronous and read ports will be asynchronous by default if the target hardware allows it For example Stratix memories are fully synchronous and do not allow an asynchronous read port You can create synchronous read ports explicitly by using clock position specifications rclkpos and clkpulselen and asynchronous write ports
189. g the bus j Note that during the write phase the data bus is driven for one clock cycle after the write strobe goes low to ensure that the data is stable across the falling edge of the strobe 11 2 Simulating interfaces You can combine the hardware and simulation versions of your program by using the ifdef construct For example LULA www celoxica com Page 235 Handel C Language Reference Manual Celoxica define SIMULATE ifdef SIMULATE Hendi f There are several ways to simulate the reading and writing of data across an interface Bus type and port type interfaces If you have a bus type interface or a port type interface port_in or port_out you can use the infile and outfile specifications to read and write data Bus type interfaces are bus_in bus_latch_in bus_clock_in bus_out bus_ts bus_ts_latch_in and bus_ts_clock_in For example set clock external P1 unsigned 8 out interface port_in unsigned 8 i pi with infile in txt interface port_out po out with outfile out txt void main void do Out pisi whileCout 0 infile and outfile can only connect to files with data in a simple format If your data is more complex you could write a C C function and call it to bring in the data If you want to model the hardware as well as the functionality of your design you will need to co simulate your interface with a model of the component to which it will
190. ge e Structures may be passed through channels and signals e Structures may be stored in internal memory elements e Structures cannot be stored in off chip RAMs S INN www celoxica com Page 43 Handel C Language Reference Manual Celoxica If a structure contains a memory element a channel or a signal it cannot be stored in another memory element it cannot be passed to a function by value it cannot be assigned to and it cannot be passed through a channel or a Signal If a structure contains a memory element it cannot be assigned or assigned to another structure as the assignment cannot be performed in a single clock cycle Whole structures may not be sent directly to interfaces Example Struct human Declare human struct type unsigned int 8 age Declare member types int 1 sex char name 25 Define human type Struct human sister Sister age 25 Initialization You can use a list initializer to initialize static or const structures or structures with global scope List initializers may be flat or structured Struct Boris int l2 Wie is int 8 a D r Static Struct Boris b 1 2 3 4 5 4 2 8 enum enum specifies a list of constant integer values for example enum weekdays MON TUES WED THURS FRI The first name in this case MON has a value of 0 the next 1 and so on unless explicit values are specified If not all values are specified values increment from the
191. ge 243 Handel C Language Reference Manual Celoxica Int 4 Xe yZ interface bus_clock_in int 4 read InBus with data P4 epon Sp E Pie ys par while 1 x InBus read while 1 y Xi AE Designing the system to minimize the problem Remember to keep the problem in perspective by examining the details of the board to estimate the probability of metastability You can use external buffers to stabilize data from synchronous hardware before it is input to the FPGA Techniques to minimize the problem If using channels to communicate between clock domains you may use clock specifications to balance speed and metastability issues If using interfaces to communicate between clock domains you can insert extra Stabilizing flip flops to reduce the likelihood of metastability being propagated through the circuit Timing constraints used for channels across clock domains Within a single clock tick data transmitted from another asynchronous clock domain must settle stop being metastable and be routed to the next flip flop S INN www celoxica com Page 244 Handel C Language Reference Manual Celoxica If you are using channels to communicate between clock domains you can set the timing constraints which specify how long it is before you sample data the amount of time for it to settle OR the amount of time available for it to move onwards Ba E EX Lues minperiod penod The
192. gnment of x to y which like all assignments takes 1 clock cycle A more complex example is chan unsigned 8 link par d Parallel branch 1 a b C d link x link y Parallel branch 2 Here the first branch of the par statement takes three clock cycles to execute However the second branch of the par statement also takes three clock cycles to execute because it must wait for two cycles before the transmitting branch is ready The usage of clock cycles is as follows Cycle Branch 1 Branch 2 1 a b delay 2 c d delay 3 Channel output Channel input FI FOs FIFOs add another layer of complexity e A www celoxica com Page 151 Handel C Language Reference Manual Celoxica chan unsigned link_FIFO with fifolength 4 int 1 Q par while 1 Er Cannot be in parallel to channel write Do not change a variable in parallel with sending it Jink_FIFO i Parallel branch 1 Parallel branch 2 a b Parallel code used here instead of delay c d link _FIFO y Here the write branch of the par statement takes two clock cycles to execute and the read branch takes three clock cycles to execute If it were a simple channel the write branch would have to wait until the channel had been read before it could write the next value of i However because it is a FIFO the write branch can keep writing until the FIFO ts full On the third clock cycle the read branch reads the
193. h the following code set clock external C1 with trate 10 clock declaration in file one hcc set clock external C1 with rate 20 clock declaration in file two hcc you would get a compiler error as the rate specifications don t match If one of the clocks is divided you need to divide the value of the rate specification to match For example set clock external C1 with rate 10 file one hcc set clock external divide 3 CL with rate 33333333333333 333 F 7 file two hcc If you need to use decimal places to specify the rate for the divided clock the compiler will round up the value to the nearest whole number as long as you use at least 16 decimal places 3 x3 3333333333333333 is rounded up to 10 e A www celoxica com Page 238 Handel C Language Reference Manual Celoxica 11 4 2 Merging input pins Input pins can be merged so that pins can be read simultaneously into multiple variables This can be done by specifying multiple interfaces bus mm bus_clock_in bus_latch_in which have some pins in common If required a different subset of pins can be specified for each instance of the interface For example interface bus_in int 8 wide wideDataBus with data P PO Pons P4 SEA p f pT POMII interface bus_in int 3 thin thinDataBus with fdata ed PS reer ad eo ta a ae wideDataBus wide would give the values of pins PO P7 whereas thinDataBus thin
194. hanout are normally connected to files Only integer values can be used as input data and files connected to chanin must be correctly formatted An unconnected channel that outputs data to the simulator will be displayed in the debug window You can declare multiple channels for input and output and connect more than one channel to the same file but you cannot read from the same channel more than once in a clock cycle If the simulation is still running when the end of the file has been reached the simulator will read in zeroes You cannot use chanin or chanout in a struct Use pointers to chanin or chanout instead Simple example chanin unsigned Input with tinfile Data source dat chanout unsigned Output input xX output y This example declares two channels one for input from the simulator and one for output to the simulator The input channel connects to a file managed by the simulator the output channel connects to the simulator s standard output the debug window in the DK GUI S INN www celoxica com Page 184 Handel C Language Reference Manual Celoxica Multiple channel example chanin int 8 input_l with infile Data source_l dat chanin int 16 input_2 with infile Data source_2 dat chanout unsigned 3 output_l chanout char output_2 int 8 a int To pi Input IZ a input_z z D output_l unsigned 3 0 a D lt 3 output_2 a When simulated such a program disp
195. hat cannot be assigned to This means that they keep the initialization value throughout They may be initialized in the declaration statement The const keyword can be used instead of define to declare constant values It can also be used to define function parameters which are never modified The compiler will perform type checking on const variables and prevent the programmer from modifying it Example 1 const int 1 5 1 10 Error Ttt i Error Example 2 const int const p tepti oy Error a SE E EPROP 4 20 volatile In ANSI C volatile is used to declare a variable that can be modified by something other than the program It is mostly used for hard wired registers volatile controls optimization by forcing a re read of the variable It is only a guide and may be ignored The initial value of volatile variables is undefined Handel C does nothing with volatile It is accepted for compatibility purposes 4 21 Complex declarations It is possible to have extremely complex declarations in Handel C You can combine arrays of functions structs arrays and pointers with architectural types To clarify such expressions it is wise to use typedef 4 21 1 Macro expressions in widths If you use a macro expression to provide the width in a type declaration you must enclose it in parentheses This ensures that it will be correctly parsed as a macro S INN www celoxica com Page 78 Handel C Language Reference Man
196. he format specification is one of oC Display as a character As Display as a string d Display as a decimal AT Display as a floating point 0 Display as an octal Au Display as a hexadecimal e A www celoxica com Page 106 Handel C Language Reference Manual Celoxica An assert evaluates to an empty statement and can only appear after all declarations in a macro or function Using assert as a statement In the example below assert is used as a statement set clock external C1 int f int x assert width x 3 0 Width of x is not 3 it is 4d width x return xtl void main void int 4 y y f y x will be inferred to have a width of 4 so the following message will be displayed F proj test hcc 4 2 Assertion failed Width of x is not 3 it is 4 Using assert as an expression In the example below assert is used as an expression LAA www celoxica com Page 107 Handel C Language Reference Manual Celoxica set clock external C1 unsigned func unsigned p unsigned q macro expr WidthSum a b width a width b macro expr CheckWidths a b assert WidthSum a b 32 WidthSum a b 16 WidthSum a b Sum of widths of function parameters is not 16 or 32 it is 4d WidthSum a b unsigned 16 ReturnVal ReturnVal CheckWidths p q return ReturnVal i void main void Static unsigned 9 x Static unsigned 7 y unsigned result result func x
197. he top level of the design called soggy When they were integrated with external code the PAR tools wouldn t know which soggy to use where 11 8 Specifying the interface You can specify your own interface format This allows you to communicate with code written in another language such as VHDL Verilog or EDIF and allows the Handel C simulator to communicate with an external plugin program e g a connection to a VHDL simulator S INN www celoxica com Page 249 Handel C Language Reference Manual Celoxica The expected use for this is to allow you to incorporate bought in or handcrafted pieces of low level code in your high level Handel C program It also allows your Handel C program code to be incorporated within a large EDIF VHDL or Verilog program You can also use it to communicate with programs running on a PC that simulate external devices To use such a piece of code requires that you include an interface definition in the Handel C code to connect it to the external code block This interface definition also tells the simulator to call a plugin which in turn may invoke a simulator for the foreign code Be Plugin Cock Plugin language Wil simulator Plugin monitor 11 9 Targeting ports to specific tools Handel CC code Handel C a simulator Other When compiling to EDIF Handel C has the capacity to format the names of wires to external logic according to the different syntaxes used by any ext
198. he value of the expression to the channel Expression may be any expression of the correct type Example set clock external void main void unsigned 8 Res chan Bill par Bill 1 23 Bill Res e A www celoxica com Page 52 Handel C Language Reference Manual Celoxica 4 5 1 FIFO code example chan unsigned 8 ch with fifolength 2 unsigned a D C d lt chil FIFO becomes lz ch 2 FIFO becomes Cl d chea FIFO becomes lt 2 gt a becomes 1 ch 3 FIFO becomes lt 2 3 gt ch b FIFO becomes lt 3 gt b becomes 2 ch c FIFQ becomes empty c becomes 3 ch 4 FIFO becomes lt 4 gt ch 5 FIFO becomes lt 4 5 gt ch d FIFO becomes lt 5 gt d becomes 4 ch 6 FIFO becomes lt 5 6 gt 4 5 2 Arrays of channels Handel C allows arrays of channels to be declared For example chan unsigned int 5 x 6 This is equivalent to declaring 6 channels each of which is 5 bits wide A channel can be accessed by specifying its index As with variable arrays the index for the nth element is n 1 For example xL4 3 Output 3 on channel x 4 X 3 y Input to y from channel x 3 It is also possible to declare multi dimensional arrays of channels For example chan unsigned int 6 x 4 5 6 This declares 4 5 6 120 channels each of which is 6 bits wide Accessing the channels is similar to accessing arrays in conventional C For example XE2 E3 01 4 Outp
199. he value of the paranoia specification sets the number of flip flops used to give the synchronization data time to stabilize The higher the value of paranoia the more stable the data and the greater the latency Se www celoxica com Page 175 Handel C Language Reference Manual Celoxica Setting paranoia to O to decrease latency If you know there is not going to be a metastability problem e g the clock domains you are working with have a low clock rate or are synchronous with each other you may choose to set paranoia to 0 In this case you must use the minperiod constraint rather than the resolutiontime constraint Clock A Clock B Channel CE t contral logic contral logic synchronisers L time to transfer between domains clock period in domain B when paranoia 0 tp unconstrainedperiod ta minperiod Latency between clock domains The latency of channels between clock domains is unpredictable It is dependent on e the value of resolutiontime e the value of paranoia e the value of unconstrainedperiod For FIFOs whose size is an exact power of two latency is higher In addition it may be affected by e the way a channel has been implemented in hardware the sequence of communications sent across the channel e the number of clock cycles elapsed since power up e environmental factors such as temperature and supply voltage e the individual FPGA Program your code
200. hl ch2 unsigned int 1 thing Code that affects thing par EIS 2 ex prialt d case chl y break case che l y Undefined simultaneous send break if thing chl Z else ehe 7 z If thing is false then channel ch2 is the only channel that becomes ready to receive so the prialt tries to send y over ch2 simultaneously with the statement sending x over ch2 resulting in an illegal simultaneous access There is a conflict even when thing is true as ch2 undergoes readiness negotiations within the prialt statement and this also requires access to the channel Restrictions on channels accesses between clock domains If you have channels communicating between clock domains all writes to a channel must take place within a single clock domain and all reads must take place within a single clock domain For more information on using channels to communicate between clock domains see Channels communicating between clock domains see page 169 4 5 4 Timing and latency in FIFOs Note that if fifolength is a power of 2 the channel will be implemented in a different way to when it is not in order to save memory Channels with FIFO sizes of a power of 2 may have greater latency www celoxica com Page 55 Handel C Language Reference Manual Celoxica The latency of channels is dependent on the target architecture and the way the code has been implemented within it 4 6 Interfaces overview All interfaces
201. ical operators return values to match this meaning but it is also possible to use variables as conditions For example if x a D else c d This is expanded by the compiler to if x 0 a D else c d When executed if x is not equal to 0 then b is assigned to a If x is O then d is assigned to c 5 6 5 while loops Handel C provides while loops exactly as in conventional C while Expression Statement The contents of the while loop may be executed zero or more times depending on the value of Expression While Expression is true then Statement is executed repeatedly Statement may be replaced with a block of statements For example e A www celoxica com Page 92 Handel C Language Reference Manual Celoxica x 0 while x 45 J CS a This code adds 5 to y 45 times equivalent to adding 225 to y 5 6 6 do while loops Handel C provides do while loops exactly as in conventional C do Statement while Expression The contents of the do while loop is executed at least once because the conditional expression is evaluated at the end of the loop rather than at the beginning as is the case with while loops Statement may be replaced with a block of statements For example do a a b Xx x l while x gt y 5 6 7 for loops Handel C provides for loops similar to those in conventional C for Initialization Test Iteration Statement The body of the
202. ices S INN www celoxica com Page 288 Handel C Language Reference Manual Celoxica e aTCLscript for use with Quartus for Altera Apex Cyclone and Stratix devices e a Netlist Constraints File NCF for Xilinx devices The place and route tools then use these timing requirements to constrain the relevant paths so that the part of the design connected to the clock in question can be clocked at the specified rate In the example below the clock will need to run at 17 5MHz set clock external _divide D17 4 with rate 17 5 When rate Is applied to a divided clock as shown it is the divided clock that will be constrained by the specification not the external clock Undivided clocks are also constrained to the appropriate value as calculated from the specified rate and the division factor 12 26 rclkpos wclkpos and clkpulselen specifications SSRAM timing The rclkpos wclkpos and clkpulselen may be given to internal or external SSRAM declarations They are valid for EDIF VHDL and Verilog outputs They are specified as floating point numbers in multiples of 0 5 To use these specifications you must be using the external_divide or internal_divide clock types with a division factor of 2 or more rclkpos specifies the positions of the clock cycles of the RAM clock for a read cycle These positions are specified in terms of cycles of a fast external clock counting forwards from the rising edge of the divided Handel C clock
203. igned unsigned unsigned unsigned typeof Expression Note 1 Width will be appears before the declaration int n int char short long int32 int64 Width See Note 1 n bits Compiler infers width 8 bits 16 bits 32 bits 32 bits 64 bits Yields type of object inferred by compiler unless the set intwidth n command Architectural types Prefixes to the above types for different architectural object types are e A www celoxica com Page 21 Handel C Language Reference Manual Celoxica Prefix Object chan Channel chanin Simulator channel chanout Simulator channel ram Internal or external RAM rom Internal or external ROM Signal Wire wom WOM within multi port memory Compound types The compound types are Prefix Object SErUCt Structure mpram Multi port memory Special types Type Object interface Interface to external logic or device sema Semaphore Has no width or logic type Interfaces connect to logic beyond the Handel C design whether on the same or a different device 3 6 Comparison of Handel C and ANSI C Handel C has many similarities to ANSI C ISO C However Handel C is a language for digital logic design which means that the way in which DK interprets it may different to the way in which compilers interpret ANSI C for software design Handel C has some extensions to ANSI C to allow additional functionality for hardware design It also lacks some ANSI C cons
204. ility include file directory 13 3 Conditional compilation Conditional directives You can control preprocessing with conditional directives These statements can add a great deal of flexibility to source code For example they may be used to alter the behaviour of a design depending upon whether a macro definition is present Conditional statements must begin with an if directive and an expression to be evaluated and end with the endif directive Valid directives are if expression elif expression else endif Example if a include this section if a is equal to b elif a gt b include this section if a is greater than b else otherwise include this section endi f If the expression is evaluated to be zero then any text following the directive will be discarded until a subsequent elif else or endif statement is encountered otherwise the lines will be included as normal Note that each directive should be placed individually on its own line starting at column O A useful application for conditional directives is easy exclusion of code without the use of comments For example e A www celoxica com Page 312 Handel C Language Reference Manual Celoxica if 0 Code for debugging purposes endif Code continues By amending the above evaluation to 1 the code can quickly be included during compilation Conditional definition To test for the existence of a macro definition use
205. ime The typeof operator allows the type of an object to be determined at compile time The undefined keyword specifies that the compiler should infer the width of a variable These constructs allow you to create parameterizable code For example the Celoxica fixed point library uses macros to pass the integer width and fraction width of a fixed point number into code that creates a struct to hold the number Targeting hardware FPGAs and PLDs The set family and set part constructs allow you to specify the device you want to target in your source code You can also set the device using the DK GUI Targeting hardware memory The ram and rom keywords allow you to create on chip RAM and ROM and to interface to external RAM and ROM If you want to create a block RAM use the block specification E www celoxica com Page 33 Handel C Language Reference Manual Celoxica To interface to off chip RAMs or ROMs use the offchip specification The addr data we cS oe and clk specifications define the pins used between the FPGA PLD and external RAM or ROM An mpram is a multi ported RAM This allows you to read from and write to a RAM within the same clock cycle or to make two read or two write accesses Individual ports can be specified as read write read only and write only using the ram rom and wom keywords If you want to interface to a dedicated memory resource on the FPGA PLD use the ports specification The clkpulselen rclk
206. in Their first use defines their direction and the domains e A www celoxica com Page 169 Handel C Language Reference Manual Celoxica in which they transmit and receive If you attempt to re use the channel in a different direction or to or from a different clock domain the compiler generates an error Channels used between clock domains must be defined in one file and then declared as extern in another The timing between domains is unspecified but the transmission is guaranteed to occur provided metastability is resolved If fifolength is 0 both sides will wait until the transmission is certain to complete Otherwise the channel will write as soon as the FIFO is ready and has space and read as soon as the FIFO is ready and isn t empty If you use channels to communicate between clock domains you must specify the rate and the resolutiontime for both clocks Most cases will be dealt with by setting the resolution time to three quarters of the clock period Example For a 10ns clock set clock external A22 with rate 100 resolutiontime 5 Note that the rate is in MHz and the resolutiontime is in nanoseconds If you need to adjust the channel timing due to latency issues you may do so by adjusting the resolutiontime and the number of flip flops used to prevent metastability being propagated through the circuit x If the resolution time is set incorrectly then intermittent failures due to metastabilit
207. in write mode i e condition is non zero you will get the value that you are writing to the bus The rising edge of the Handel C clock reads the external values into the internal flip flops on the chip For example unsigned 1 condition int 4 x Interface bus_ts_clock_in int 4 read BiBus int 4 writePort x tl unsigned 1 enable condition with data P4 P3 P24 Pu E condition 0 Tri state external pins x BiBus read Read registered value condition 1 Drive x l onto external pins This example reads the value from the flip flop into variable x and then drives the value of x 1 onto the external pins x Take care when driving tri state buses that the FPGA PLD and another device on the bus cannot drive simultaneously as this may result in damage to one or both of them S INN www celoxica com Page 231 Handel C Language Reference Manual Celoxica 11 1 8 Example hardware interface The example shows the use of buses The scenario is of an external device connected to the FPGA PLD which may be read from or written to The device has a number of signals connected to the FPGA PLD Signals connected Signal FPGA pin Description Name Deana 1 2 3 4 Data Bus Write 5 Write strobe Read 6 Read strobe WriteRdy 7 Able to write to device ReadRdy 8 Able to read from device Read cycle timing A read from the device is performed by waiting for ReadRdy to become active high The Read signal i
208. ination voltage Altera documentation refers to this standard as simply 1 5 V LVCMOS 1 2 V 1 2 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard This is a single ended general purpose standard used for 1 2V applications It uses a 5V tolerant CMOS input buffer and a Push Pull output buffer This standard does not require the use of a reference voltage or a board termination voltage LVDCI Low Voltage Digital Controlled Impedance Xilinx Virtex Il devices are able to provide controlled impedance input buffers and output drivers that eliminate reflections without an external source termination Output drivers can be configured as controlled impedance drivers or as controlled impedance drivers with half impedance Inputs can be configured to have termination to Veco Or tO Veco 2 split termination where Veco is the input output source voltage All of these are available at four voltage levels 1 5 V 1 8 V 2 5 V and 3 3 V For further details please refer to the Xilinx Data Book LVDS Low Voltage Differential Signal LVDS is a differential I O standard It requires that one data bit be carried through two Signal lines The LVDS I O standard is used for very high performance low power consumption data transfer Two key industry standards define LVDS IEEE 1596 3 SCl LVDS and ANSI TIA EIA 644 Both standards have similar key features but the IEEE Standard supports a maximum data transfer of 250 Mbps Th
209. ind bind component to work library busformat text format of exported wires in EDIF netlist data list the pins used for transferring data MSB to LSB deci apply Digital Controlled Impedance to buses Xilinx only ext lib specify external plugin for simulator ext func specify external simulator function for this port extpath specify any direct logic combinational logic connections to another port extinst specify connection to external code intime maximum allowable time between a port and the sequential elements it drives in ns outtime maximum allowable time between a port and the properties sequential elements it is driven from in ns parameterize instantiations of external black boxes sc_type specify type of port in port_in port_out or generic interface for SystemC standard specify I O standard electrical characteristics to use on port s in question strength specify drive strength in mA for output buses 2 Actel ProASIC ProAS IC 1 others None None None Default 10 0 Boy None O No None PlugInSet or PlugInGet None None None None None bool for 1 bit ports sc_uint otherwise LVCMOS33 for Actel ProAS C ProAS IC LVTTL for others Standard dependent S N www celoxica com Page 60 Handel C Language Reference Manual Celoxica vhdl_type specify type of port in port_in port_out or std_logic for generic interface in VHDL 1 bit ports unsigned otherwise warn di
210. ine defines y within the macro definition The last line expresses the value of the macro in full Independent let in definitions macro expr op a b let macro expr t2 x x 2 in let macro expr d3 x x 3 in let macro expr t4 x x 4 in t2 a d3 b t4 a b t2 b a is equivalent to writing macro expr opla D a 2 b 7 3 la D 4 C bD a 2 Related let in definitions macro expr op a b let macro expr sum x y x y in let macro expr mult x y x sum x y in mult a b b b aN www celoxica com Page 144 Handel C Language Reference Manual Celoxica sum is defined within the macro definition then mult is defined using sum This example is equivalent to macro expr opta DY a a Dd bd D Shared recursive macro A recursive multiplier illustrating the way in which Iert mn can be used to share recursive macros Shared expr mult p q let macro expr multiply x y select width x 0 0 multiply x 1 y lt lt 1 xL0 1 y 0 in multiply p q Scope of definitions The inner macros are not accessible outside the outer macro chanout lt unsigned 16 gt och int 16 i j Kk d macro expr Cube x let macro expr Saqr x x x in x Sar x i Cube 3 Correct use j Sar 3 Error out of scope k Cube 2 Error out of scope 7 3 11 Macro procedures Macro procedures may be used to replace
211. ined RAM if the memory is read into an uninitialized register reserved specifically for the use of the memory Non pipelined access to RAM t0 t1 L t3 t4 15 tb tf S saar EEPE EE eee pt oat noe ee ee ON ei ON W i LA D tn 3 write cycles are performed e At time tO the rising edge of the main Handel C clock CLK initiates a write cycle e At event el WE is asserted and Addr and Din are set up so that when the memory is next clocked the data at Din will be written at the location specified in Addr e At time t0 5 the inverted clock rising edge clocks the memory causing it to execute the write operation e At event e2 after the write operation has completed the data that has been written becomes available at the output from the memory Dout Two further write cycles are performed starting at time t1 and t2 This is followed by a read cycle TH www celoxica com Page 205 Handel C Language Reference Manual Celoxica e At time t3 the main Handel C rising clock edge initiates a read cycle e At event e3 WE is de asserted and Addr is set up so that when the memory is next clocked the location specified at Addr will be read e At time t3 5 the inverted clock rising edge clocks the memory causing it to execute the read operation e At event e4 after the read operation has completed the data that has been read becomes available at the output from the memory Dout e A
212. ion Fxpression l Expression A A Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Meaning Test if semaphore owned Take if not Compile time selection Array or memory subscripting Bit selection Bit range extraction One of the two constants may be omitted but not both Function call Structure reference Structure reference Logical NOT Bitwise NOT Unary minus Unary plus Yields pointer to operand Yields object or function that the operand points to Width of expression Type casting Take LSBs Drop LSBs Multiplication Division Modulo arithmetic Addition Subtraction Shift left Shift right Concatenation Less than Greater than Less than or equal Greater than or equal Equal Not equal Bitwise AND Bitwise XOR e A www celoxica com Page 20 Handel C Language Reference Manual Expression Expression Expression Expression assert 3 5 Type summary Expression amp amp Expression Expression Expr Fxpr Celoxica Bitwise OR Logical AND Logical OR Conditional selection diagnostic macro to print to stderr The most common types that may be associated with a variable and the prefixes for architectural and compound types are listed below Common logic types Type int signed signed undefined signed signed signed signed signed unsigned unsigned unsigned uns
213. ion set_statement 14 1 Language syntax conventions BNF Backus Naur Format is a way to describe the syntax of file formats It consists of definitions of the form identifier definition The identifier is a word which describes this part of the syntax The represents consists of The definition lists the permitted contents of the identifier The conventions used in this language reference are e Terminal symbols are set in typewriter font like this e Non terminal symbols are set in italic font Tike this e Square brackets denote optional components e Braces denotes zero one or more repetitions of the enclosed components e Braces with a trailing plus sign denote one or several repetitions of the enclosed components e Parentheses denote grouping 14 2 Keyword summary The keywords listed below are reserved and cannot be used for any other purpose E www celoxica com Page 316 Handel C Language Reference Manual Celoxica Keyword Meaning ANSI C C A assignment operator Yes statement terminator Yes comma operator Yes code block delimiters Yes lt gt type clarifier No open delimiter Yes close delimiter Yes array index delimiters Yes bit selection bit range selection No l logical NOT operator Yes l output to channel No addition operator Yes subtraction operator Yes unary minus operator Yes r multiplication operator Yes division operator Yes
214. ion to pass the current clock to an external interface The value of the system variable _ clock will be the value after any divide The clock may be an internal or an external clock Example The code below shows the assignment of the current clock to a port in an interface interface reg32xlk registers unsigned addr address unsigned data data_in unsigned 1 clk __clock unsigned out write 9 3 Multiple clock domains You can have multiple clock domains in your Handel C design by declaring more than one main function If you have more than one main function in the same source file they must all use the same clock The clock is defined in each file using the set clock construct You can communicate between clock domains by e using channels with time constraints set on the clock e using a defined custom interface You cannot use multiple clock domains within the pre defined Handel C interface sorts Variables signals and functions cannot be written to by one clock domain and read in another Communicating between clock domains means that you need to consider metastability issues x If you reset one clock domain without synchronously resetting any clock domains that it communicates with the communicating channels will go to an undefined state 9 3 1 Channels communicating between clock domains Channels that connect between clock domains can only be written to in a single domain and read from in a single doma
215. ions to position the write strobe e External clock at the same speed as the Handel C clock Use multiple reads to give the RAM enough time to respond e Use the wegate specification to position the write enable signal within the Handel C clock Fast external clock This method of timing asynchronous RAMs depends on having an external clock that is faster than the internal clock i e the location of the clock is internal_divide or external_divide with a division factor greater than 1 If so Handel C can generate a write strobe for the RAM which is positioned within the Handel C clock cycle This is done with the westart and welength specifications For example set clock external_divide P 8 4 ram unsigned 6 xL34 with westart 2 welength 1 The write strobe can be positioned relative to the Handel C clock cycle by half cycle lengths of the external undivided clock The above example starts the pulse 2 whole external clock cycles into the Handel C clock cycle and gives it a duration of 1 external clock cycle Since the external clock is divided by a factor of 4 this is equivalent to a strobe that starts half way through the internal clock cycle and has a duration of one quarter of the internal clock cycle This signal is shown below External clock py eed en eee cea Weier Handel C clock Write strobe TIMING DIAGRAM POSITIONED WRITE STROBE This timing allows half a clock cycle for the RAM set up time on
216. ite cycle welkpos 3 5 ckpulselen 0 5 weetart 3 0 welength 1 0 RAM2ZA400R RAM2 An www celoxica com Page 265 Handel C Language Reference Manual Celoxica HCLK initiates the parallel read from and write to the different blocks of RAM The settings of rclkpos and clkpulselen delay the read cycle until the address is stable Read clock pulse 1 CLK pulse after HCLK held for 0 5 CLK pulses The settings of wclkpos and clkpulselen delays the write cycle until after the data has been read and is stable The settings of westart and welength position the write enable appropriately 12 5 buffer specification The buffer specification can be applied to all bus type interfaces and external clock reset declarations It accepts a string and it specifies the type of buffer that should be built on the corresponding interface None may be used to specify that no buffer Should be built Example 1 interface bus_in unsigned 3 1 I with buffer IBUFG builds a standard bus_in interface where the buffer is of type IBUFG specifying that the bus_in should feed a global buffer for Xilinx instead of a basic input buffer for connecting to DCMs for instance Example 2 interface bus_in unsigned 3 i I with buffer None builds a standard bus_in interface with no buffer That is any logic reading from 1 i will be fed by pins directly Example 3 set clock external with buffer GL25
217. last specified value If you do not specify a width for the enum the program must contain information from which the compiler can infer the width You can declare variables of a specified enum type They are effectively equivalent to int undefined or unsigned undefined The signedness is inferred from use To specify enum values www celoxica com Page 44 Handel C Language Reference Manual Celoxica enum weekdays MON 9 TUES WED THURS FRI To specify the width of an enum enum weekdays MON unsigned 4 9 TUES WED THURS FRI To declare a variable of type enum enum weekdays x To assign enum values to a variable Static int x MON Example The example below illustrates how to infer the width of an enum The cast ensures the enumerated variable has a width associated with it set clock external P1 typedef enum void main void En num int undefined result num int 7 D result num 4 2 9 Bit fields A bit field is a type of structure member consisting of a specified number of bits The length of each field is separated from the field name by a colon Each element can be accessed independently Since Handel C allows you to specify the width of integers in bits a bit field is merely another way of specifying a standard structure In ANSI C bit fields are made up of words and only the specified bits are accessed the rest are padded Padding in ANSI C is implementation dependent Ther
218. lays the name of channels before outputting their value on the simulating computer screen 10 1 1 Simulator input file format The data input file should have one number per line separated by newline characters either DOS or UNIX format text files may be used Each number may be in any format normally used for constants by Handel C You can only use integer values Blank lines are ignored as are lines prefixed by comments For example 56 0x34 0654 0b001001 iS a comment blank lines ignored 2 If EOF file is reached while reading an input file zeroes will be read in until the simulation completes 10 1 2 Block data transfers The Handel C simulator has the ability to read data from a file and write results to another file For example TH www celoxica com Page 185 Handel C Language Reference Manual Celoxica chanin int 16 input with f infile in dat chanout int 16 output with outfile out dat void main void while 1 int value Input value output valuetl This program reads data from the file in dat and writes its results to the file out dat The simulator will open and close the specified files for reading or writing as appropriate If EOF file is reached while reading an infile file zeroes will be read in until the Simulation completes If the in dat file consists of D6 0x34 0654 0b001001 the out dat will contain the decimal results as follows oy Ee 429
219. ld a value between 1 and 20 use a 5 bit int int amp X Casting There is no automatic conversion between signed and unsigned values in Handel C you have to explicitly cast them The 12 xX unsigned int 12 y y x not allowed y unsigned x 0K Similarly there is no automatic type conversion If you wanted to add an int 5 and a long together you would need to pad the int to 32 bits by using the concatenation operator However it would be more usual to perform arithmetic on ints of specific widths Pointers can be cast to void and back to another pointer of the same type except for the addition or removal of a type qualifier between signed and unsigned and between similar structs e g a struct with identical elements except for the width of the types You cannot perform the following casts in Handel C e from a pointer of one type to a pointer of another type except for those listed above e from a pointer to an integral type e from an integral type to a pointer e from a pointer to a function to a pointer to another function type Arithmetic and comparisons on variables of different width In Handel C you need to use the concatenation operator or the take operator when performing arithmetic or comparisons on variables of different width For example e A www celoxica com Page 24 Handel C Language Reference Manual Celoxica int 12 x int 8 y xX y not allowed y x not allowed
220. ll be initialized as zero since Mary is static In this case since Fred Read is the same size as Fred ReadWrite elements O 3 of Fred Read would be initialized with the same values 4 8 2 Mapping of different width mpram ports If the ports of the mpram are of different widths they will be mapped onto each other according to the specifications of the chip you are using If the ports used are of different widths the widths should have values of 2 Different width ports are available for Xilinx Virtex and Spartan Il Spartan IIE and Spartan 3 devices and Altera Apex II Stratix and Cyclone devices They are not available with other Altera devices or Actel devices S INN www celoxica com Page 66 Handel C Language Reference Manual Celoxica Xilinx bit mapping To find the bits that an array element occupies in a Xilinx Virtex or Spartan RAM you can use the formula RAM array ram y NameLa will have a start bit of y a 1 1 and an end bit of y a Xilinx mapping is little endian This means that the address points to the LSB The bits between the declarations of RAM are mapped directly across so that bit 27 in one declaration will have the same value as bit 27 in another declaration even though the bits may be in different array elements in the different declarations mpram Joan ram lt unsigned 4 gt ReadWritel256 Read write port rom lt unsigned 8 gt Read 256 Read only port ie Joan ReadWrite 100
221. ls to stabilize resolutiontime You may set the value of minperiod or resolutiontime but not both If paranoia has been set to 0 you should use minperiod Clock A Clock B Channel 3 synchronisers PERIODS WITH PARANOIA AT ITS DEFAULT OF 1 www celoxica com Page 280 Handel C Language Reference Manual J BT Celoxica Gas minperiod iG unconstrainedperiod tp clock period Clock A Clock B Channel CE t contral logic contral logic synchronisers PERIODS IF PARANOIA SET TO O In this case it is possible that the control signal may be metastable within the first flip flop and if minperiod is inadequate the metastability may be propagated into the rest of the circuit 12 18 offchip specification The of fchip specification may be given to a RAM or ROM declaration you cannot have offchip MPRAMs When set to 1 the Handel C compiler builds an external memory interface for the RAM or ROM using the pins listed in the clk addr data cs we and oe specifications When set to 0 the Handel C compiler builds the RAM or ROM on the FPGA or PLD and ignores any pins given with other specifications You can use the offchip specification for EDIF VHDL or Verilog output The compiler generates an error if the ports and offchip specification are both set to 1 for the same memory You cannot initialize an offchip RAM Example ram int 8 al 15 43 with f offchip 1 S
222. lustrates the generation of large quantities of hardware from simple macros The example is a multiplier whose width depends on the parameters of the macro Although Handel C includes a multiplication operator as part of the language this example serves as a Starting point for generating large regular hardware structures using macros The multiplier generates the hardware for a single cycle long multiplication operation from a single macro The source code Is macro expr multiply x y select width x 0 0 multiply x 1 y lt lt 1 Ogos 1 Ss 0 a multiply b c At each stage of recursion the multiplier tests whether the bottom bit of the x parameter is 1 If it is then y is added to the running total The multiplier then recurses by dropping the LSB of x and multiplying y by 2 until there are no bits left in x The overall result is an expression that is the sum of each bit in x multiplied by y This is the familiar long multiplication structure For example if both parameters are 4 bits wide the macro expands to a b 3 LOJ 1 c lt lt 3 0 CUB AN 2 LOj 1 2 Gees zs 0 Ch AN 1 LOJS 1 2 g lt 0 BLOT Ze e 0 This code is equivalent to a b amp 8 8 c 8 0 b amp 4 4 c 4 0 b amp 2 2 c 2 0 b amp 1 1 c 0 which is a standard long multiplication calculation 7 3 7 Shared expressions By default Handel C generates all the hardware r
223. m repl_update_param_body repl_update_param repl_update_param_body repl_param assignment_operator initializer repl_param repl_param repl_param repl_param repl_param identifier repl_param e A www celoxica com Page 331 Handel C Language Reference Manual Celoxica 14 17 Expressions syntax constant_expression assignment_expression expression assignment_expression expression assignment_expression assignment_expression conditional_expression unary_expression assignment_operator assignment_expression assignment_operator 4 lt lt gt gt Ar s initializer assignment_expression conditional_expression logical_or_expression logical_or_expression expression conditional_expression logical_or_expression logical_and_expression logical_or_expression logical_and_expression logical_and_expression inclusive_or_expression logical_and_expression amp amp inclusive_or_expression inclusive_or_expression exclusive_or_expression inclusive_or_expression exclusive_or_expression exclusive_or_expression and_expression exclusive_or_expression and_expression and_expression equality_expression and_expression amp equality_expression equality_expression relational_expression equality_expression relational_expression equality_expression relational_expression rel
224. message Is Error User assertion failed If the expression evaluates to true the whole assert expression is replaced by a constant expression assert can be used as a statement by passing O as the trueVa ue If the condition is true the whole assert statement is replaced by O a null statement This is shown in the example below If the width of x is 3 the condition is true the whole statement is replaced by the trueValue of 0 so nothing happens assert width x 3 0 Width of x is not 3 it is 4d width x A more detailed example is given below assert can also be used as an expression where its return value is assigned to something This is illustrated in the second example below where the return value is assigned to ReturnVal Syntax assert condition trueValue string with format specification s argument s If condition is true the whole expression reduces to trueValue If condition is false string will be sent to the standard error channel with each format specification replaced by an argument When assert encounters the first format specification if any it converts the value of the first argument into that format and outputs it The second argument is formatted according to the second format specification and so on If there are more expressions than format specifications the extra expressions are ignored The results are undefined if there are not enough arguments for all the format specifications T
225. mmunication with the preprocessor occurs through the use of directives Directives are lines within source code which begin with the character followed by an identifier known as the directive name For example the directive to define a macro Is define 13 1 Preprocessor macros Simple macros The preprocessor supports several types of macros Simple macros or manifest constants involve the simplest form of macro substitution and are defined with the form define name sequence subsitute Any occurrences of the token name found in the source code are replaced with the token sequence sequence substitute which may include spaces All leading and trailing white Spaces around the replacement sequence are removed For example define FOO 1024 define loop_forever while 1 Parameterized macros You can also define macros with arguments This allows replacement text to be passed as parameters For example define mul A B A B This will replace x mul 2 3 S INN www celoxica com Page 310 Handel C Language Reference Manual Celoxica Take care to preserve the intended order of evaluation when passing parameters For example the line x mul a 2 3 will be expanded into Xag 2 24 2 The multiplication is evaluated first then the result subtracted from variable a This is almost certainly not the intention and errors of this type may be difficult to locate If a parameter name is preceded by a whe
226. n Q par while 1 condition a 1 try try a l a 2 a 3 reset condition s 1 t 1 reset condition x l TSL will execute the second reset statement only 5 6 12 trysema Celoxica trysema semaphore tests to see if the semaphore is owned If not it returns one and takes ownership of the semaphore If it is it returns zero A semaphore may be freed by using the statement releasesema semaphore S INN www celoxica com Page 99 Handel C Language Reference Manual Celoxica Example inline void critRAMaccess sema RAMSema ram int 8 danger L4 unsigned count Into xX wait till you ve got the RAM while trysema RAMsema 0 delay x danger count releasesema RAMSema ze Note that you can no longer take the semaphore twice without releasing it while 1 d always succeeds because its the same trysema expression if trysema s In DK version 1 this worked In DK version 1 1 and subsequent versions the second and subsequent trysema will always fail Instead use while 1 if trysema s releasesema s 5 6 13 releasesema releasesema semaphore releases a semaphore that was previously taken by trysema semaphore Se www celoxica com Page 100 Handel C Language Reference Manual Celoxica Example inline void critRAMaccess sema RAMSema ram int 8 danger L4 unsigned count
227. n all the information obtainable from the addition and multiplication operations Note that the constant zeros do not require a width Specification because the compiler can infer their widths from the usage The zeros in the first assignment must be 1 bit wide because the destination is 9 bits wide while the source operands are only 8 bits wide In the second assignment the zero constants must be 8 bits wide because the destination is 16 bits wide while the source operands are only 8 bits wide 6 7 Relational operators Operator Meaning s Equal to Not equal to lt Less than gt Greater than lt Less than or equal Greater than or equal These operators compare values of the same width and return a single bit wide unsigned int value of O for false or 1 for true This means that this conventional C code is invalid unsigned 8 w X Y Z w xX y gt z NOT ALLOWED Instead you should write w x 0 y gt z TH www celoxica com Page 113 Handel C Language Reference Manual Celoxica 6 7 1 Signed unsigned compares Signed signed compares and unsigned unsigned compares are handled automatically Mixed signed and unsigned compares are not handled automatically For example unsigned 8 x int 8 y if x gt y Not allowed TO compare signed and unsigned values you must sign extend each of the parameters The above code can be rewritten as unsigned 8 x int 8 y if Cint 0 x gt yL7 y
228. n declared as part of a macro it is expanded into a quoted string by the preprocessor E g if a macro is defined define quickassert X assert width X 1 0 Width of X is not E The line quickassert length will expand into assert width X 1 0 Width of length is not 1 n Undefining identifiers To undefine an identifier the undef directive may be used E g undef FOO Note that no error will occur if the identifier has not previously been defined xe Preprocessor directives cannot be used unexpanded in a library use macro procedures instead 13 2 File inclusion File inclusion makes it possible to easily manage and reuse declarations macro definitions and other code The feature is helpful when writing general purpose functions and declarations which can be reused for a number of designs File inclusion is achieved using directives of the form include filename www celoxica com Page 311 Handel C Language Reference Manual Celoxica or include lt fi ename gt Such lines are replaced by the contents of the file indicated by filename If the file name is enclosed by quotation marks the preprocessor looks for the file in the directory containing source code for the current design If the file cannot be found there or the file name is enclosed with angular brackets the search examines user defined include file directories specified using Tools gt Options gt Directories and the main Ag
229. n y being set to O and z being set to 9 Note that the range of bits is of the form MSB LSB and is inclusive Thus the range 7 3 is 5 bits wide The bit selection values must be fixed at compile time e A www celoxica com Page 110 Handel C Language Reference Manual Celoxica The value before or after can be omitted If you omit the value after the semi colon then zero is assumed so the LSBs are taken If you omit the value before the semi colon then n 1 is assumed so the MSBs are taken Bit selection is allowed in RAM ROM and array elements For example ram int 7 w 23 int 5 x 4 int 3 y unsigned int 1 z w 10 4 2 unsigned 1 x 2 0 The 10 specifies the RAM entry and the 4 2 selects three bits from the middle of the value in the RAM w is set to the value of the selected bits J Z Similarly z is set to the least significant bit in the x 2 variable Ei You cannot assign to bit ranges only read from them 6 5 5 Width operator The width operator returns the width of an expression It is a compile time constant For example x y lt width x This takes the least significant bits of y and assigns them to x The width operator ensures that the correct number of bits is taken from y to match the width of x 6 6 Arithmetic operators The following arithmetic operators are provided in Handel C e A www celoxica com Page 111 Handel C Language Reference Manual Celoxica
230. nal 188 190 192 foreign code 213 initialization 54 56 multi ported 57 61 off chip 188 190 192 274 on chip 180 210 211 212 overview 54 restrictions 97 simultaneous access 97 synchronous 193 195 204 261 282 syntax 320 targeting 192 204 use of 186 writing to 54 Xilinx 212 ANG Spas eee eee T E E T 31 rate epecificotion 270 281 ERDO aaar 195 282 reading from external pins 219 220 Kail S ON cesnenccwiendescctcnsee 111 117 133 recursive macros111 133 135 136 137 Shared expressions 135 136 137 reducing logic depth cee 154 reference DOOKS cccceeeee eect eeeeeeeeees 4 FEGISUCL eege 68 registered reading from external pins220 relational Operators ccceee eee ees 106 releASCSEMA cee cee ccseeeeeeeeeeeeees 93 e A www celoxica com Page 344 Handel C Language Reference Manual replicated code 76 FODICQUOMS EE 324 KE 90 186 297 global 186 specifying reset pin 186 restrictions 46 97 117 127 136 casting 97 functions 117 127 129 on channels 46 on RAM and ROM 97 on shared expressions 136 retime specification cccee cece ees 284 FGCU eet eebe 84 117 types 117 ele EE 102 RONI uean eria 54 186 212 external 212 LUT ROM in Altera devices 256 overview 54 same rate external clock 85 189 SC Dvpespechfication ees 285 Seele 8 29 119 variable sharing 8 Select Clock dalog cece ees 162 Select EENE
231. nclosed in braces interface bus_in unsigned 2 datain I with standard LVDS25 data PI P2 P3 P4 The first pin in a pair is the positive one You can omit the second pin of each pair but you still need to enclose the single pins within braces S INN www celoxica com Page 301 Handel C Language Reference Manual Celoxica You also need to specify pair of pins enclosed in braces for pin specifications for offchip memories addr we cs oe and clk when you are using a differential I O For example ram unsigned 4 ExtRAM 256 with toffchip l standard LVPECL33 gddr ii Pl PZ ts 2 P35 Pay TT PO TR POO Pe SEA KR PO PLO e PLII PIZ Fe CPIS Prs PIT PIOI we P17 P18 CS E P19 P20 A e P21 P22 Si If you use a differential I O for an external clock the pins are specified using the set clock construct rather than the data specification set clock external C1 C2 With standard ZENS SH The standard specification is ignored for VHDL and Verilog output but if you have used a data specification with pairs of pins and then build the code for VHDL or Verilog output the first pin in each pair will be assigned and the other pin will be ignored 12 33 std_logic_vector specification The std_logic_vector specification may be given to port_in port_out or generic interfaces where you want to use a std_logic_vector port instead of an unsigned port in VHDL
232. nd write the value into another on a single cycle the value read is the value in block RAM on the previous clock cycle not the current cycle Code example with timing issues Static ram unsigned 8 RAMI 4 0 1 2 3 with block BlockRAM ram unsigned 8 RAM2L4 with bDlock BlockKRAM Signal s unsigned x unsigned 1 while 1 par s RAMI i RAM i s xX S a Here x and RAM2Li get different values s changes on the falling edge x is written to on the rising edge RAM2 i is written to on the falling edge Therefore RAM2 i gets the value of RAM1 i 1 and x gets the value of RAM1 7 To alter this you must use the rclkpos wclkpos and clkpulselen specifications to set the RAM clock cycle positions e A www celoxica com Page 264 Handel C Language Reference Manual Celoxica Solution to timing problem divide CLK by four to give Handel C clock set clock external_divide Cl 4 Static ram unsigned 8 RAMI L4 0 1 2 3 with block BlockRAM rclkpos 1 0 wclkpos 3 5 clkpulselen 0 5 westart 3 0 welength 1 0 ram unsigned 8 RAM2 4 with block BlockRAM rclkpos 1 0 wclkpos 3 5 clkpulselen 0 5 westart 3 0 welength 1 0 Fast clock CLE Handel C clock FF HELK div Ai RAMTADDR RAM An RAM clack RAMCLE read cycle rclkpos 1 0 ckpulselen 0 5 HAM DATA ut RAN DATAQut An RAM clack AMELE wr
233. ndard specification may be applied to any external bus interface not port_in or port_out connected to pins to select the I O standard to be used on all pins of that interface It may also be applied to external clocks and to off chip memories If the standard supports it you can use the strength specification to set the drive current and the dci specification to set digital controlled impedance The standard specification only applies to EDIF output it is ignored for other outputs Standard and dci specifications are ignored if you have used the clockport specification and set it to 0 The default for clockport is 1 Different device families support different standards Consult the data sheet for a specific device for details of which standard it supports The compiler will issue errors if a non Supported standard is selected for a particular device or if the standard specification is used on a family not supporting selectable I O standards TH www celoxica com Page 293 Handel C Language Reference Manual 12 32 1 Available I O standards I O Handel C I O Handel C standard keyword standard keyword LVTTL LVTTL HSTL HSTLI8_II 1 8v Class Celoxica I O Handel C standard keyword LVDS 2 5V LVDS25 see note 1 HE www celoxica com Page 294 Handel C Language Reference Manual LVCMOS 3 3 V LVCMOS 2 5 V LVCMOS 1 8 V LVCMOS 1 5 V LVCMOS 1 2 V PCI 33 MHz 3 3 V PCI 33 MHz 5
234. ndel C programs Since Handel C is based on the syntax of conventional C programs written in Handel C are implicitly sequential Writing one command after another indicates that those instructions should be executed in that exact order To execute instructions in parallel you must use the par keyword Handel C provides constructs to control the flow of a program For example code can be executed conditionally depending on the value of some expression or a block of code can be repeated a number of times using a loop construct You can express your algorithm in Handel C without worrying about how the underlying computation engine works This philosophy makes Handel C a programming language rather than a hardware description language In some senses Handel C is to hardware what a conventional high level language is to microprocessor assembly language The hardware design that DK produces is generated directly from the Handel C source program There is no intermediate interpreting layer as exists in assembly language when targeting general purpose microprocessors The logic gates that make up the final Handel C circuit are the assembly instructions of the Handel C system 2 1 2 Parallel programs The target of the Handel C compiler is low level hardware This means that you get massive performance benefits by using parallelism It is essential for writing efficient programs to instruct the compiler to build hardware to execute statements in
235. nnnnnnnnnnnnnnnnn tb LO 7 FUNCTIONS AND MACROS sasunnnsnnnuunnnnnnuunnnnnnuunnnnnnnnnnnnnnnnnnnnnnnnnnnn L LO 7 1 FUNCTIONS AND MACROS OVERVIEW cscsscsuccunccncnuseuseunenuseuseuseussssssL LO 7 1 1 Functions and macros language Iesues cece cece eect eeeeeeeeeeeeeeeeaeeeaaes 118 7 1 2 Functions and macros sharing bardware 120 7 1 3 Functions and macros clock ovces seen cece eee eeeeeneeeeeeeeeeteneeaaes 121 7 1 4 Functions and macros evammples cece cece eeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeaeagags 121 7 1 5 ACCESSING External NAMES ccccccee cess cece rner ran EAA Ea 123 7 1 6 Recursion IN macros and funchions cc cccccce eee e cece cece eeeeeeeeeeeeeeeeeseaneaaes 124 7 2 INTRODUCTION TO FUNCTIONS unsere EK KREE EE RER EK KREE RER E ERR ks ren LOG 7 2 1 Function definitions and declaratons cece eeeeeeeeseeeeeeeeeeseneaaes 125 7 222 FUNCUONS SCOPE EE 126 7 2 3 Arrays of Lu e de EE 126 7 224 Function arrays ln un EE 127 7 2 5 Function arrays example with static varables 128 L BR getrei CEET 129 722 7 PURCHON PONTET GXaIN EE 130 7 2 8 Simultaneous FUNCTION CAIIS cece cece cece cece eee eeeeeeee seen eeeeeeeeeneeeeetetseanegaes 134 7 2 9 Multiple functions IN a STATEMENL cece ccce cece cece cette eeeeeeeeeeeeeeeeeteneeanes 136 7 3 INTRODUCTION TO Lie e CERS e 7 3 1 Non parameterizZed macro exvDreseiong sees cece eee eeeeeeeeeeeeeeeesaneeaaes 137 7 3 2 Parameterized macro EXPIESSIONS sessrrrrererrrrerrr
236. nsion will be generated on compilation to feed into the Max Plus II or Quartus software This process is transparent if they are in the same directory as the EDIF edf extension file generated by the Handel C compiler Creating RAMs without an inverted clock If you declare a single port RAM for Altera Flex Apex 20 Mercury or Excalibur devices the Handel C compiler converts this into an MPRAM with a ROM port and a WOM port This removes the inverted clock and so increases the possible clock rate If you want to remove the inverted clock from an on chip memory on an Apexi device you need to do this manually by creating an MPRAM instead of a RAM The compiler does not do this automatically as the hardware created for an MPRAM is larger than that for a RAM on Apexll devices Stratix and Cyclone memories are totally synchronous so creating an MPRAM with a ROM and a WOM port does not automatically result in the inverted clock being removed Instead you can pipeline the MPRAM or you can customize the clock using the rclkpos wclkpos and clkpulselen specifications 10 3 6 Using on chip RAMs in Xilinx devices Handel C supports the synchronous RAMs on Virtex series and Spartan I and Spartan 3 parts directly simply by declaring a RAM or ROM For example ram unsigned 6 x 34 This will declare a RAM with 34 entries each of which is 6 bits wide When writing Handel C programs you must be careful not to exceed the number of memory blocks in
237. ntics require that any assignment takes one clock cycle Typically SSRAMs have a latency of at least one clock cycle Therefore in order for accesses to a e A www celoxica com Page 200 Handel C Language Reference Manual Celoxica SSRAM device to conform to Handel C s one clock cycle per assignment rule the SSRAM clock needs to be offset from the Handel C clock If the SSRAM has a latency of more than one clock cycle its clock needs to be faster than the Handel C clock as well as being offset from it This is done by using an independent fast clock RAMCLK to match the SSRAM timings with the Handel C timing constraints A fast external clock CLK is divided to provide the Handel C clock HCLK and is also used to generate pulses to clock the SSRAM where the pulses can be placed within a single HCLK cycle This placed clock is the RAMCLK It can be carried to an external SSRAM using the clk specification By default the Handel C compiler uses an inverted copy of the Handel C clock to drive synchronous on chip memories This may mean you need to run your design at a lower clock frequency than you want to You can increase the efficiency of your design by e using pipelined memory accesses for certain on chip SSRAMs This is illustrated by the Pipelined on chip SSRAM examples see page 207 and the Pipelined on chip SSRAM timing diagrams see page 205 e using the clock position specifications to alter the position of the RAM
238. o par blocks Se www celoxica com Page 90 Handel C Language Reference Manual Celoxica 5 6 3 return expression The return statement is used to return from a function to its caller return terminates the function and returns control to the calling function Execution resumes at the line immediately following the function call return can return a value to the calling function The value returned is of the type declared in the function declaration Functions that do not return a value should be declared to be of type void Example int power int base int n Int Te p pad for iz lr i lt n i p p base return p E You cannot use return to jump out of par blocks 5 6 4 Conditional execution if else Handel C provides the standard C conditional execution construct as follows if Expression Statement else Statement As in conventional C the else portion may be omitted if not required For example if x 1 Xx xet 1 Statement may be replaced with a block of statements by enclosing the block in brackets For example e A www celoxica com Page 91 Handel C Language Reference Manual Celoxica if x gt y a b C Gs else a d c The first branch of the conditional is executed if the expression is true and the second branch is executed if the expression is false Handel C treats zero values as false and non zero values as true Relational and log
239. o use an interface definition Interfaces of pre defined sorts do not need to be declared The general format of the interface declaration Is www celoxica com Page 56 Handel C Language Reference Manual Celoxica interface Sort ports_in_to_Handel C ports_out_from_Handel C Sort user defined name or predefined interface sort ports_in_to_Handel C Optional One or more prototypes of ports bringing data into the Handel C code ports_out_from_Handel C Optional One or more prototypes of ports sending data from the Handel C code A port prototype consists of the port type and the port name At least one port whether to Handel C or from Handel C must be declared Port declarations are delimited by commas For example interface MyInterface int 5 InPort int 4 Drot int 4 OutPort2 E The name of each port in a port_in or port out interface must be different as they will all be built to the top level of the design Once you have declared an interface sort you can define multiple instances of that sort The interface definition creates a named instance of the interface sort assigns data to be transmitted to the output ports and may also specify properties using interface specifications You cannot use interface specifications in interface declarations only in interface definitions You can declare pointers to an interface declaration and then assign a defined interface to the pointer 4 6 2 Interface definition
240. of Bloo to be provided in another block of HDL 12 4 block specification The block specification may be given to a RAM or ROM declaration for EDIF VHDL or Verilog output The block specification may also given to channels where fifolength is 2 or greater The specification takes a string to specify the type of block memory required Possible values are e Actel devices BlockRAM e Altera devices LUT EAB M512 M4kK M RAM EAB should be used for both EABs and ESBs e Xilinx devices SelectRAM BlockRAM e All devices AUTO This is the same as not using the block specification but can be used as a placeholder to pass in an active value For example ram int 8 aL15 43 with block BlockRAM chan lt unsigned 1 gt ch with fifolength 15 block SelectRAM If you want to build a ROM from look up tables distributed memory in Altera devices you need to declare the ROM with block LUT M512 M4K and M RAM are used to specify memory blocks in Stratix and Cyclone devices The block specification has changed since DK1 1 although the old method using block 1 to specify block RAMs is still supported for backward compatibility S INN www celoxica com Page 263 Handel C Language Reference Manual Celoxica Issues with Xilinx Virtex VirtexE and Spartan I1E Due to the pipelined nature of Virtex and Spartan IIE block RAM if you attempt to read from one bank of block RAM a
241. of a variable or a function static functions and static variables declared outside functions can only be used in the file in which they appear static variables declared within an inline function or an array of functions can only be used in the copy of the function in which they appear Handel C uses static in a different way to C In C if you have an inline function and a local static variable one copy of the variable is shared across each function instantiation In Handel C there is one copy of the variable per function instantiation Static variables are the only local variables excluding consts that can be initialized To get a default value initialize the variable Example Static int 16 local_function int water int weed Static int 16 local_fish 1234 void main void int fresh pondweed local_fish local_function fresh pondweed Syntax Static variable_declaration Static functionName parameter type list Static variables in arrays of functions If a static variable is declared in an arrayed function each instance of the function will have its own independent copy of the variable 4 17 typedef typedef defines another name for a variable type This allows you to clarify your code The new name is a synonym for the variable type typedef int 4 SMALL_FISH If the typedef is used in multiple source files it is good practice to collect all the type definitions in a header file included at the to
242. of operations and the increment and decrement operations are included as statements to reflect the fact that Handel C expressions cannot contain side effects 3 4 Operator summary The following table lists all operators Entries at the top have the highest precedence and entries at the bottom have the lowest precedence Entries within the same group have the same precedence Precedence of operators is as expected from conventional C For example X X y Z This performs the multiplication before the addition Brackets may be used to ensure the correct calculation order as in conventional C Note that assignments are not true operators in Handel C S INN www celoxica com Page 19 Handel C Language Reference Manual Celoxica Operator trysema select Constant Expr Expr Expression Expression Expression Constant Expression Constant Constant functionName Arguments pointerToStructure gt member structureName member Expression Expression Expression Expression amp object x pointer width Expression Type Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression Expression lt Constant Constant h lt lt Expression gt gt Expression lt gt lt Fxpression gt Express
243. ogic_vector specification S INN www celoxica com Page 305 Handel C Language Reference Manual Celoxica Example 1 Handel C instantiation of a Bloo component without vhdl_ type specification set interface Bloo unsigned 1 myin B Cunsigned 4 myout x results in Handel C generating this VHDL instantiation of the Bloo component COMPONENT Bloo PORT myin OUT sta Togic myout IN unsigned 3 DOWNTO OU ys END COMPONENT Example 2 Handel C instantiation of a Bloo component with vhdl_ type applied to entire interface interface Bloo unsigned 1 myin BCunsigned 4 myout x with vhdl_type std_logic_vector results in Handel C generating this VHDL instantiation of the Bloo component COMPONENT Bloo PORT myin OUT std_logic_vector 0 DOWNTO 0 myout IN std_logic_vector 3 DOWNTO Di E END COMPONENT Example 3 Handel C instantiation of a Bloo component with vhdl_ type applied to individual ports interface Bloo unsigned 1 myin with vhdl_type std_logic_vector B unsigned 4 myout x with vhdl_type signed results in Handel C generating this VHDL instantiation of the Bloo component COMPONENT Bloo PORT myin OUT std_logic_vector 0 DOWNTO Di myout IN signed 3 DOWNTO 0O END COMPONENT e A www celoxica com Page 306 Handel C Language Reference Manual Celoxica 12 38 warn specification The warn specification may be given to a variable RAM ROM channel b
244. om Page 47 Handel C Language Reference Manual Celoxica Examples In the examples below p and q can point to any part of Single or an element of Array AnotherArray or Memory int undefined 1 int 4 Single Array 10 AnotherArray 20 ram int 4 Memory 10 int A p q unsigned int 1 test p amp Single p 2 undefined behaviour invalid address p amp Single p defined valid address but p 0 undefined behaviour p amp Array 4 p 2 now p amp Array 6 p Array q amp Array 4 i q p meaningful now i 4 test p lt q meaningful true in this case test p q meaningful false in this case p Array q AnotherArray 1 q p undefined behaviour test p lt q undefined behaviour test p q meaningful false for pointers into different objects 4 3 1 Pointers and addresses Pointers in Handel C are similar to those in conventional C They provide the address of a variable or a piece of code This enables you to access variables by reference rather than by value The indirection operator is the same as it is in ANSI C It is used to de reference pointers i e to access objects pointed to by pointers The address of operator amp works as it does in ANSI C 4 3 2 Pointers to functions If you point to code a function the address operator is optional The syntax Is returnType
245. on 0 Tri state external pins get 0 get 1 Register external value x BiBus read Read registered value condition 1 Drive x 1 onto external pins This example samples the external bus and reads the registered value into variable x and then drives the value of x 1 onto the external pins x Take care when driving tri state buses that the FPGA PLD and another device on the bus cannot drive simultaneously as this may result in damage to one or both of them e A www celoxica com Page 230 Handel C Language Reference Manual Celoxica 11 1 7 Bidirectional data transfer with clocked input bus _ts_clock_in The bus_ts_clock_in interface sort allows Handel C programs to perform bidirectional off chip communications via external pins with inputs clocked continuously with the Handel C clock Its general usage is interface bus_ts_clock_in type inPortName Name type outPortName Value type conditionPortName Condition with Specs Value is an expression giving the value to output on the pins Condition is an expression giving the condition for driving the pins When Condition is non zero i e true the value of Value is driven on the pins When the value of Condition is zero the pins are tri stated and the value of the external bus can be read using the identifier Name inPortName If 7nPortName is not defined the port name defaults to in If you attempt to read from a tri state bus when it is
246. ons or recursive macro procedures It must be possible to determine the depth of recursion at compile time e Creating multiple copies of a function www celoxica com Page 26 Handel C Language Reference Manual Celoxica e Re writing the function to create iterative code This is relatively easy if the function is calling itself simple recursion and the recursive call is the last item within the function definition tail recursion The following ANSI C function has simple tail recursion unsigned long Factorial unsigned long n if n 0 return 1 else return n Factorial n 1 It can be re written in Handel C as unsigned int 32 Factorial unsigned int 32 n d unsigned int 32 nfact nfact 1 if n 0 delay else while n 0 nfact n n return nfact Note that the if else is required to prevent the possibility of a combinatorial loop if the while loop is not executed 3 6 6 Handel C v C loop statements for loops in Handel C are slightly different to those in ANSI C the initialization and iteration steps are written as statements rather than expressions This is because of restrictions on side effects in expressions in Handel C You need to ensure that loop statements take at least one clock cycle in Handel C This means that e you cannot have empty loops in Handel C www celoxica com Page 27 Handel C Language Reference Manual Celoxica e you need to
247. onstant This first form of the macro is a simple expression For example macro expr DATA_WIDTH 15 int DATA_WIDTH x This form of the macro is similar to the define macro Whenever DATA_WIDTH appears in the program the constant 15 is inserted in its place Constant expression To provide a more general solution you can use a real expression For example macro expr sum x y y 2 y sim W Sum S INN www celoxica com Page 137 Handel C Language Reference Manual Celoxica 7 3 2 Parameterized macro expressions Handel C allows macros with parameters For example macro expr add3 x x 3 y add3 zZ This is equivalent to the following code en SE This form of the macro is similar to the define macro in that every time the add3 macro is referenced it is expanded in the manner shown above In this example an adder is generated in hardware every time the add3 macro is used 7 3 3 select operator The select operator is used to mean select at compile time Its general usage is Select Expressionl1 Expression2 Expression3 Expressionl must be a compile time constant If Expressionl evaluates to true then the Handel C compiler replaces the whole expression with Expression2 If Expression evaluates to false then the Handel C compiler replaces the whole expression with FExpression3 Comparison with conditional operator The difference between select and the conditional operator
248. operator is used here to tell the compiler to generate different expressions depending on the width of one of the parameters to the macro The last two lines of the example could have been written by hand as follows b 0 a Db E 5 The macro comes into its own if the width of one of the variables changes Suppose that during debugging it is discovered that the variable a is not wide enough and needs to be 8 bits wide to hold some values used during the calculation Using the macro the only change required would be to alter the declaration of the variable a The compiler would then replace the statement b 0 a with b a lt 5 automatically This form of macro also comes in useful when variables of undefined width are used If the compiler is used to infer widths of variables it may be tedious to work out by hand which form of the assignment is required By using the select operator in this way the correct expression is generated without you having to know the widths of variables at any stage 7 3 4 ifselect ifselect checks the result of a compile time constant expression at compile time If the condition is true the following statement or code block is compiled If false it is dropped and an else condition can be compiled if it exists Thus whole statements can be selected or discarded at compile time depending on the evaluation of the expression The ifselect construct allows you to build recursive macros in a simila
249. ou needed parts of your program to run at different speeds and so use different clocks A main function is defined as follows Global Declarations Clock Definition void main void Local Declarations Body Code The main function takes no arguments and returns no value This is in line with a hardware implementation where there are no command line arguments and no environment to return values to The argc argv and envp parameters and the return value familiar from conventional C can be replaced with explicit communications with an external system e g a host microprocessor within the body of the program 3 2 Comments Handel C uses the standard delimiters for comments These comments may not be nested For example Valid comment This is NOT valid Handel C also provides the C style comment marker which tells the compiler to ignore everything up to the next new line For example X x 1 This is a comment 3 3 Statement summary e A www celoxica com Page 17 Handel C Language Reference Manual Celoxica Statement Barbe seq par Init Test Iter seq Init Test Iter Variable Expression Variable Variable Variable Variable Variable Expression Variable Expression Variable Expression Variable Expression Variable Expression Variable lt lt Expression Variable gt gt Expression Variable amp Ex
250. ould not be written to by more than one parallel branch 3 Language basics 3 1 Program structure Sequential structure As in a conventional C program a Handel C program consists of a series of statements which execute sequentially These statements are contained within a main function that tells the compiler where the program begins The body of the main function may be split into a number of blocks using brackets to break the program into readable chunks and restrict the scope of variables and identifiers Handel C also has functions variables and expressions similar to conventional C There are restrictions where operations are not appropriate to hardware implementation and extensions where hardware implementation allows additional functionality Parallel structure Unlike conventional C Handel C programs can also have statements or functions that execute in parallel This feature is crucial when targeting hardware because parallelism is the main way to increase performance by using hardware Parallel processes can communicate using channels A channel is a point to point link between two processes e A www celoxica com Page 16 Handel C Language Reference Manual Celoxica Overall structure The overall program structure consists of one or more main functions each associated with a clock This is unlike conventional C where only one main function is permitted You would only use more than one main function if y
251. ovides the ability to add tags to certain objects variables channels ports buses RAMs ROMs mprams clocks resets and signals to control their behaviour These tags or specifications are listed after the definition of the object using the with keyword All specifications can be applied to generic output Others are only valid for Simulation Debug or Release or for hardware output When defining multiple objects the specification must be given at the end of the line and it applies to all objects defined on that line For example extern unsigned x y unsigned x y with show 0 This attaches the show specification with a value of 0 to both x and y variables Specifications can only be applied to the definition of objects not to declarations extern rom unsigned 32 SomeRomlL1 with Spec Wrong spec applied to de claration rom unsigned 32 SomeRom 1 1 with Spec OK spec applied to definiti on The with keyword takes one or more of the following attributes 12 1 Summary of specifications 12 1 1 Compiler atttributes These specifications are interpreted by the compiler Specification Possible Default Applies to Meaning values warn 0 1 1 variables Enable warnings for object memories channels interfaces clocks extpath Name of port None port FROM Specify any direct logic TO Handel C Handel C combinational logic on the same connections to another port interface S INN www celoxica com Page 252
252. ox_data_in_O Data into Handel C out from foreign code memory mox_rox_data_in_l mox_rox_data_in d mox_rox_data_in_3 The declaration of the read only port wox would produce wires S INN www celoxica com Page 223 Handel C Language Reference Manual Celoxica mox_wox_addr_0O Address mox_wox_addr_l mox_wox_clk 7 A OCK MOX_WOX_CS Chip select mox_wox_data_en Data enable mox_wox_data_out_0O Data out from Handel C into foreign code memory mox_wox_data_out_1l mox_wox_data_out_2 mox_wox_data_out_3 mox_wox_oe Output enable mox_wox_we Write enable 10 3 9 Using other RAMs The interface to other types of RAM such as DRAM should be written by hand using interface declarations Macro procedures can then be written to perform complex or even multi cycle accesses to the external device S NN www celoxica com Page 224 Handel C Language Reference Manual Celoxica 11 Interfacing with external hardware All off chip accesses are based on the idea of a bus which is just a collection of external pins Handel C provides the ability to read the state of pins for input from the outside world and set the state of pins for writing to the outside world Tri state buses are also Supported to allow bi directional data transfers through the same pins The pins used may be defined in Handel C by using pin specifications e g data If this is omitted the pins will be left unconstrained and can be assigned by the pl
253. p of each source file using the include headerFileName directive It is conventional to differentiate typedef names from Standard variable names so that they are easily recognizable HE www celoxica com Page 76 Handel C Language Reference Manual Celoxica Example typedef int 4 SMALL_FISH extern SMALL_FISH stickleback 4 18 typeof The typeof type operator allows the type of an object to be determined at compile time The argument to typeof must be an expression Using typeof ensures that related variables maintain their relationship It makes it easy to modify code by simplifying the process of sorting out type and width conflicts A typeof construct can be used anywhere a type name could be used For example you can use it in a declaration in casts Syntax typeof expression Example unsigned 9 ch typeof ch ch q struct d typeof ch cha chb sl typeof s1 s2 ch sl cha s2 chb q sl chb s2 cha If the width of variable ch were changed in this example there would be no need to modify any other code This is also useful for passing parameters to macro procedures The code below shows how to use a typeof definition to deal with multiple parameter types macro proc swap a b d typeof a t t a a b b t J e A www celoxica com Page 77 Handel C Language Reference Manual Celoxica 4 19 const const defines a variable or pointer or an array of variables or pointers t
254. perators Handel C provides the prefix and postfix and operations as statements rather than expressions For example S INN www celoxica com Page 102 Handel C Language Reference Manual Celoxica seg is directly equivalent to G O O o II Ce E oO o 6 2 Casting of expression types Automatic conversions between signed and unsigned values are not allowed Values must be cast between types to ensure that the programmer is aware that a conversion is occurring that may alter the meaning of a value You can cast to a type of undefined width For example int 4 x unsigned int undefined y x int undefined y The compiler will infer that y must be 4 bits wide Explanation of signed unsigned casting The following piece of Handel C is invalid TAG A X Range of x 8 7 unsigned int 4 y Range of y 0 15 X y Not allowed This is because x is a signed integer while y is an unsigned integer When generating hardware it is not clear what the compiler should do here It could simply assign the 4 bits of y to the 4 bits of x or it could extend y with an extra zero as its most significant bit to preserve its value and then assign these 5 bits to x assuming x was declared to be 5 bits wide To see the difference consider the case when y is 10 By simply assigning these 4 bits to a signed integer a result of 6 would be placed in x A better solution might be to extend y to a five bit value by
255. phore After you have taken a semaphore you should ensure that you release it cleanly once you have left the critical area Semaphores may be included in structures They cannot be passed to directly to functions over channels or interfaces They may be passed to functions or channels by reference Syntax sema Name S INN www celoxica com Page 69 Handel C Language Reference Manual Celoxica Example inline void critRAMaccess sema RAMSema ram int 8 danger L4 unsigned count Int G xX wait till you ve got the RAM while trysema RAMsema 0 delay x danger count releasesema RAMSema 4 11 signal A signal is an object that takes on the value assigned to it but only for that clock cycle The value is assigned at the start of the clock cycle and can be read back during the same clock cycle At all other times the signal takes on its initialization value The optional disambiguator lt gt can be used to clarify complex signal definitions If a signal is assigned to when you are debugging code values shown in the Watch and Variables windows are updated immediately rather than at the end of the clock cycle step Signals represent wires in hardware Syntax signal lt type data width gt signal_Name Example int 15 a bD signal lt int gt sig a par sig a b sig sig is assigned to and read from in the same clock cycle so b is assigned the value of a Sinc
256. pos and wclkpos specifications allow you to synchronize a RAM clock with the Handel C clock The westart welength and wegate specifications allow you to specify timing of a RAM clock that is asynchronous to the Handel C clock Targeting hardware wires If you specify a signal in Handel C this creates a wire in hardware A signal takes on the value assigned to it but only for that clock cycle The value assigned to it can be read back during the same clock cycle Targeting hardware resets set reset allows you to reset your device into a known state It can also be used to configure devices that are not in a known state at start up try reset allows you to specify some actions that occur if a particular condition becomes true within a particular block of hardware Interfacing to existing modules and to peripherals Handel C interfaces can be used to connect to external devices or to external logic on your target FPGA PLD such as other programs written in Handel C VHDL or Verilog Port type interfaces allow you connect to external logic The bind properties and Std_logic_vector specifications allow you to parameterize interfaces connecting to external code Bus type interfaces connect to pins connected to peripheral devices The standard specification selects the I O standard for interface pins and the strength specification determines the drive current You can use the dci specification if you want to use digital controlled impedanc
257. pression Variable Expression Variable Expression Channel Variable Channel Expression if Expression statement else statement ifselect Expression statement else statement while Expression statement do while Expression for Init Test Iter break continue return l LExpression goto label Switch Expression statement prialt statement Meaning Parallel execution Sequential execution Parallel replication Sequential replication Assignment Increment Decrement Increment Decrement Add and assign Subtract and assign Multiply and assign Divide and assign Modulo and assign Shift left and assign Shift right and assign Bitwise AND and assign Bitwise OR and assign Bitwise XOR and assign Channel input Channel output Conditional execution Conditional compilation Iteration Iteration Iteration Loop switch and prialt termination Resume execution Return from function Jump to label Selection Channel alternation aH www celoxica com Page 18 Handel C Language Reference Manual Celoxica releasesema Make semaphore available after use of trysema expression CPV owas Perform statements on reset condition reset Condition statement delay Single cycle delay Note RAM and ROM elements signals and array elements are included in the set of variables above However ram x 3 xLO is invalid yE The assignment group
258. r it is possible to combine both the simulation and hardware versions of your program into one Channel example define SIMULATE ifdef SIMULATE Input value else value BusIn in endi f External function call example define SIMULATE ifdef SIMULATE extern C int 8 bus_input_function void data_in bus_input_function else interface bus_in int 8 in BusIn data_in BusIn 1n endi f e A www celoxica com Page 23 7 Handel C Language Reference Manual Celoxica Example with plugin To simulate a tri state bus Interface bus_ts int 32 in with extlib MyPlugin dl1 extinst 1 extfunc DataBusIn DataBus int 32 out DataOut with textlib MyPlugin dll extinst 1 extfunc DataBusOut int 1 enable WriteBus in with extlib MyPlugin dll extinst 1 extfunc DataBusEnable with data pinList In this case the functions DataBusIn DataBusOut and DataBusEnable would be provided in the plugin MyPlugin dl1 and called by the simulator The extlib extfunc and extinst specifications are ignored if compiled to HDL so the interface definition does not have to be within an ifdef 11 4 Merging pins 11 4 1 Merging clock pins You can merge clock pins as long as e any pins specifications given to the two clocks match e there are no conflicts between any timing specifications given to the clocks For example if you specified two clock domains in the same project wit
259. r rormat asf extern C int 14 x long y char f long y outside extern construct will map to this C int printt const char Tormat ef Intels x long e char f long y S INN www celoxica com Page 74 Handel C Language Reference Manual Celoxica 4 14 register register has been implemented for reasons of compatibility with ANSI C register defines a variable that has local scope Its initial value is undefined Example register int 16 fish Tish TColep 4 15 inline functions inline causes a function to be expanded where it is called The logic will be generated every time it is invoked This ensures that the function is not accessed at the same time by parallel branches of code He If you have a local static variable in an inline function there is one copy of the variable per function instantiation By default functions are assumed to be shared not inline Example inline int 4 knit int needle int stitch needle needle stitch return needle int 4 jumper 100 par needle 1 needle lt 100 needle needlet2 jumper needle knit needle 1 Syntax inline function_Declaration e A www celoxica com Page 75 Handel C Language Reference Manual Celoxica 4 16 static Static gives a variable static storage its values are kept at all times This ensures that the value of a variable is preserved across function calls It also affects the scope
260. r tri state interfaces external RAMs output port or interfaces or tri state interfaces external RAMs any external interface or external clock dependent on FPGA type and off chip memories external interfaces and off chip memories Meaning Set buffer speed Maximum allowable delay between interface and variable Maximum allowable delay between variable and interface I O standard used electrical characteristics Signal strength S INN www celoxica com Page 258 Handel C Language Reference Manual dci 0 0 5 1 busformat pull 0 1 data Any valid pin list O No DCI Format string BI None None 12 1 8 Interface attributes external interfaces and external clocks Virtex Il Virtex ll Pro and Spartan 3 3E 3L only and off chip memories generic interfaces port type interfaces and ports to memories in external logic Xilinx and Apextl interfaces memories interfaces These specifications defines how interfaces are built Celoxica Digital control impedance enabled only valid with some standards Specify the way that wire names are formatted in EDIF Add pull up or pull down resistor s Set data pins Se www celoxica com Page 259 Handel C Language Reference Manual Celoxica Specification bind buffer properties quartus_proj_assign Sc_type vhdl_type 12 1 9 Examples Possible Default values 0 1 0
261. r error The source code specified in the DoThing1l function would be selected 10 2 3 Targeting specific devices via source code If you are not using the GUI or the command line to specify the target device you must insert lines in the code to specify it In order to target a specific FPGA or PLD the compiler must be supplied with the FPGA part number Ultimately this information is passed to the FPGA PLD place and route tool to inform it of the device it should target Targeting devices is in two parts specifying the target family and the target device The general syntax Is set family Family set part Chip Number Recognized families are e A www celoxica com Page 190 Handel C Language Reference Manual Celoxica Family name Actel500K ActelPA AlteraFlexl0K AlteraFlexlOKA AlteraFlex10KB AlteraFlexlOKE AlteraApex20K AlteraApex20KE AlteraApex20KC AlteraApexII AlteraMercury AlteraStratix AlteraStratixII AlteraStratixGX AlteraCyclone AlteraCyclonell AlteraExcaliburARM Description Actel ProASIC series FPGAs Actel ProASIC series FPGAs Flex10K series Altera PLDs FlexlOKA series Altera PLDs Flex1OKB series Altera PLDs Flex10KE series Altera PLDs Apex 20K series Altera PLDs Apex 20KE series Altera PLDs Apex 20KC series Altera PLDs Apex II series PLDs Altera Mercury series PLDs Altera Stratix PLDs Altera Stratix II PLDs Altera Stratix GX PLDs Altera Cyclone PLDs Altera Cyclone II PLDs Alte
262. r way to select It is also useful inside replicated blocks of code as the replicator index is a compile time constant Hence you can use ifselect to detect the first and last items in a replicated block of code and build pipelines e A www celoxica com Page 139 Handel C Language Reference Manual Celoxica Syntax ifselect condition statement 1 else statement 2 Example int 12 as int 13 p int undefined c ifselect width a gt width b C a else c c is assigned to by either a or b depending on their width relationship Pipeline example unsigned init unsigned q 15 unsigned 31 out Init 57 bar fF 02 rs Toe TH ifselect r 0 glr init else ifselect r 15 out qlr 1 else qtr qLr 1 7 3 5 Recursive macro expressions Preprocessor macros those defined with define cannot generate recursive expressions By combining Handel C macros those defined with macro expr and the select operator recursive macros can express complex hardware simply This type of macro is particularly important in Handel C where the exact form of the macro may depend on the width of a parameter to the macro S INN www celoxica com Page 140 Handel C Language Reference Manual Celoxica Variable sign extension example When assigning a narrow signed variable to a wider variable the most significant bits of the wide variable should be padded with the sign bit MSB of the narrow varia
263. ra Excalibur ARM series PLDs Se www celoxica com Page 191 Handel C Language Reference Manual Celoxica Xi linxVirtex Xi linxVirtexE XilinxVirtexI1 XilinxVirtexIIPro Xi linxVirtexlIProx Xi linxVirtex4 XilinxSpartan X11inxSpartanxl XilinxSpartanII XilinxSpartanIIE XilinxSpartan3 XilinxspartangE XilinxSpartan3L Virtex Xilinx FPGAS VirtexE Xilinx FPGAs Virtex I1 Xilinx FPGAs Virtex I1 Pro Xilinx FPGAs Virtex I1 Pro X Xilinx FPGAs Virtex 4 Xilinx FPGAs Spartan Xilinx FPGAs Spartan XL Xilinx FPGAs Spartan I Xilinx FPGAs Spartan IIE Xilinx FPGAs Spartan 3 Xilinx FPGAs Spartan 3E Xilinx FPGAs Spartan 3L Xilinx FPGAs E Your license may restrict the devices you can target The devices available to you are visible in the Family list on the Chip tab in Project Settings The part string is the complete Actel Altera or Xilinx device string For example set family XilinxVirtex Set part V1000BG560 4 This instructs the compiler to target a v1000 device in a BG560 package It also specifies that the device is a 4 speed grade This last piece of information is required for the timing analysis of your design by the Xilinx tools The family is used to inform the compiler of which special blocks it may generate To target Altera Flex 10K devices set family AlteraFlexlOK set part EPFI1OK20RC240 3 This instructs the compiler to target an Altera Flex 10K20 device in a RC240 package It also specifies
264. rds supported 289 296 mprams 59 RAM 211 architectural Dvpes 44 arithmetic Operators cccee eee 104 AU AY eege 34 36 46 56 119 channels Eege 46 functions 119 120 121 indices 36 multi dimensional 34 56 pointers to 34 OS Sele EE 99 assertion failed cece cee eee eee ee eee e eens 99 ASSIGMINICIIUS nie Seed 81 asterisk indirection operator 43 asynchronous RAM 187 192 300 divided clock 300 examples 188 190 generating 300 timing 187 undivided clock 300 asynchronous reset 186 297 GLU e EE 245 SIE ee N 64 base epechfication cece eee e eens 254 DASIC CONCENHS ccc ceeeeseeee eee eeeeeees 5 bidirectional data transfers221 222 224 clocked input 224 registered input 222 SIRIEI D AE eT E E E 30 bind specification cece cece eee e eens 254 DIC TIC o E 38 bit manpulatton cece cece eee ees 101 operators 101 Dit SelSCUON EE 103 Celoxica bitwise logical operators s es 108 bitwise AND 108 bitwise NOT 108 bitwise OR 108 bitwise XOR 108 block BAM 256 block SPECIFICATION cece cece eee ees 256 DOCK E 178 256 data transfer 178 BY E 286 290 BLVDS I O standard 286 290 294 break ccceeeeeeeeeeeeeeeeees 78 86 88 89 breaking lines cece cece eee e eee teens 307 buffer specification ccccee cece eee 259 Ee 262 DUS alle dn DEE 218 221 DUS I EE 218 219 bus_latch in 218 220 DUS TE 218 221
265. re familiar with MS Windows This Manual does not include e instruction in VHDL or Verilog e instruction in the use of place and route tools e tutorial example programs These are provided in the Handel C User Manual S N www celoxica com Handel C Language Reference Manual Celoxica 1 Introduction 1 1 References e The C Programming Language 2nd Edition Kernighan B and Ritchie D Prentice Hall 1988 e Altera Databook Altera 2004 www altera com literature lit index html e Xilinx Data Book Xilinx 2004 www X1linx com literature index htm e VHDL for logic synthesis Author Andrew Rushton Publisher John Wiley and Sons ISBN 0 471 98325 X Published May 1998 e IEEE standard 1364 1995 IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language http standards ieee org e A www celoxica com Page 11 Handel C Language Reference Manual Celoxica 2 Getting started with Handel C 2 1 Basic concepts Handel C uses much of the syntax of conventional C with the addition of inherent parallelism You can write sequential programs in Handel C but to gain maximum benefit in performance from the target hardware you must use its parallel constructs These may be new to some users If you are familiar with conventional C you will recognize nearly all the other features Handel C programs e Parallel programs e Channel communications e Scope and variable sharing 2 1 1 Ha
266. re signed The int type may be qualified with the unsigned keyword to indicate that the variable only contains positive integers or 0 For example Int 5 X unsigned int 13 y These two lines declare two variables a 5 bit signed integer x and a 13 bit non negative integer y In the second example here the int keyword is optional Thus the following two declarations are equivalent unsigned int 6 x unsigned 6 x You may use the signed keyword to make it clear that the default type is used The following declarations are equivalent S INN www celoxica com Page 38 Handel C Language Reference Manual Celoxica Int Za Ze Signed int 5 x Signed 5 X The range of an 8 bit signed integer is 128 to 127 while the range of an 8 bit unsigned integer is O to 255 inclusive This is because signed integers use 2 s complement representation You may declare a number of variables of the same type and width simultaneously For example D ke Xa Vo Z This declares three 17 bit wide signed integers x y and zZ 4 2 2 Signed unsigned syntax Signed unsigned is declared in the same way as in ANSI C except that Handel C allows the width to be declared The width may be undefined an expression or nothing For example e int as e long D e unsigned int 7 C e signed undefined d e long signed int e 4 2 3 Supported types for porting Handel C provides support for porting from conventional C by allowing the types
267. re used to specify an external simulator using the extlib directive Interface specifications apply to all ports in the interface You can also assign specifications to individual ports Port definitions If the interface has been previously declared the port definitions must be prototyped in their interface declaration and must have the same types as those in the prototype The declaration must have at least one port into Handel C or from Handel C Port definitions are delimited by commas Each port definition consists of e the data type that uses it either defined or inferred from its first use Only Signed and unsigned types may be passed over interfaces e aport name e port specifications optional The port specifications are enclosed in a set of braces and delimited by commas Example interface Sort_A int 4 inPortl int 4 inPort2 iInterfaceName unsigned outPort x 4 6 3 Example interface to external code This example shows an interface declaration used to connect to a piece of foreign code and the definition that uses this declaration e A www celoxica com Page 58 Handel C Language Reference Manual Celoxica set clock external D17 set family X1linxVirtex set part V1000BG560 4 Interface declaration interface tt l 446 unsigned 7 segments unsigned 1 rbon unsigned 1 Itn unsigned 1 rbin unsigned 4 digit unsigned 1 bin unsigned 1 ItnVal unsigned 1 rbinVal unsigne
268. retime unconstrained period Possible Values 0 1 Any time in nanoseconds O or any positive integer above 10 Causes a warning Any floating point frequency in MHz Any time in nanoseconds OU orl Any time in nanoseconds Default O fora port on an interface 1 fora clock declaration None None None None Applies to ports on interfaces external clocks clocks with channels to other clock domains clocks clocks clocks with channels to other clock domains clocks variables clocks with channels to other clock domains Celoxica Meaning Mark port as feeding a clock When applied to a generic interface port it marks that port as feeding a clock When applied to an external clock it marks that clock aS using a dedicated clock pin minimum period for place and route tools to achieve between flip flops specifies number of extra flip flops used in stabilizing synchronization data Minimum frequency at which the clock in question should be capable of running Time for metastability to resolve on channels into clock domains Prevent flip flops in a specific clock domain or generated by a variable from being moved by the retimer Constraint for compiler generated control paths into clock domain aH www celoxica com Page 255 Handel C Language Reference Manual 12 1 4 Channel attributes This specification defines how channels are
269. returna t D zk Es void main void unsigned 7 p q r S t Us V W X Y Z par p A q r s 1 t 1 u 1 par v funclO p q Vv 3 t in func 0 is 1 w funcLl r s Ww 3 t in func 1 is 1 x func 0 t u H e e t in func 0 is 2 y func O v w y 9 t in func 0 is 3 Se ERSTEN y zc Ib t in func 1 is 2 7 2 6 Function pointers These are a very powerful yet potentially confusing feature In situations where any one of a number of functions can be called at a particular point it is neater and more concise to use a function pointer where the alternative might be a long if else chain or a long switch statement See example S INN www celoxica com Page 129 Handel C Language Reference Manual Celoxica Function pointers can be assigned with or without the address operator amp similar to assigning array addresses Functions pointed to can be called with or without the indirection operator A function name can be assigned to a pointer without the amp p addeven although the amp format is clearer p amp addeven A function pointed to can be called by writing ERKI d kt This can also be written in the shorthand form chk a b The first form is preferable as it tips off anyone reading the code that a function pointer is being used 7 2 7 Function pointers example Consider the following program LULA www celoxica com Pag
270. rface bus_in unsigned 4 i I interface bus_out OCunsigned 4 o x while 1 raxLi I i bes xX Fax RAM only read into x SPRAM Example 2 transform is not performed register is initialized void main void ram unsigned 4 raxl4 with block BlockRAM Static unsigned 2 1 Static unsigned 4 x x is initialized to zero interface bus_in unsigned 4 i I interface bus_out O unsigned 4 0 x while 1 raxLijJ I i bie x raxLlil RAM only read into x S INN www celoxica com Page 208 Handel C Language Reference Manual Celoxica SPRAM Example 3 transform is not performed memory read into two destinations void main void ram unsigned 4 raxl4 with block BlockRAM Static unsigned 2 1 unsigned 4 x x is un initialized unsigned 4 y y 1S un initialized interface bus_in unsigned 4 i I interface bus_out O unsigned 4 0 x while 1 raxLi I i ears x raxLlil RAM read into x y rax i but also into y SPRAM Example 4 transform is not performed pipeline register written to from elsewhere void main void d ram unsigned 4 raxL4 with block BlockRAM Static unsigned 2 1 unsigned 4 x x is UNn initialized interface bus_in unsigned 4 i I interface bus_out O unsigned 4 o x while 1 Pai dd Isl TE X raxLil RAM only read into x x l but x also written to from elsewhere Se www
271. rface port_out from int 1 from y File bbB hcc www celoxica com Page 180 Handel C Language Reference Manual Celoxica ZS Domain bbB Compiles to bbB edf SZ set clock external P2 void main void int 1 q interface port_in int 1 to to par while 1 q to to Read data Internal resynchronizing example The resynchronizing flip flop can be placed in the file that reads the data from the foreign code block This example shows the three files required to connect two EDIF blocks bbA and bbB which use different clocks The small files bbA hcc and bDbB hcc compile to the EDIF code using the port_out from and port_in to interfaces The toplevel hcc file connects them together The data is resynchronized in the bbB hcc file clack Pl clock PZ Coplevpl File toplevel hcc www celoxica com Page 181 Handel C Language Reference Manual Celoxica ZS Code to connect data between two cores interface bbACint 1 from AC interface bbB BCint 1 to A from File bbA hcc x x Domain bbA Compiles to bbA edf bi set clock external P1 void main void int 1 y interface port_out from int 1 from y File bbB hcc Domain bbB Complies to bbB edf a ff set clock external P2 void main void int 1 q y interface port_in int 1 to to while 1 par q to to Resynchronize data y q www
272. rising edge You need to write the value s for the specification in braces For example with rclkpos 1 5 wclkpos specifies the positions of the clock cycles of the RAM clock for a write cycle You need to write the value s for the specification in braces For example with twclkpos Likes eos clkpulselen specifies the length of the pulses of the RAM clock in terms of cycles of a fast external clock rclkpos wclkpos and clkpulselen can be applied to the whole of a RAM or MPRAM or to individual ports within a memory Specifications applied to the whole memory will apply to each port that does not have its own specification If you apply rclkpos or wclkpos to the whole memory the compiler will issue a warning as rclkpos only applies to the read port s and wclkpos only applied to the write port s However the memory will build correctly e A www celoxica com Page 289 Handel C Language Reference Manual Celoxica Illustration Fast clock CLK Handel C clock HELK div 4 RA clock RAMCLK rclkpos 3 0 clkpulselen 0 5 RAM clock RAMCLK rclkpos 1 5 2 5 cilkpulselen 0 5 RAM clock RAMCLEK rclkpos 1 0 3 0 cClkpulselen 1 0 to tO 1 tO0 2 t 3 II t1i 1 t1 Examples e Applying RAM clock specifications to ports mpram rom int 1 ro 16 with rclkpos 1 clkpulselen 0 5 wom int 1 wo 16 with wclkpos 1 5 clkpulselen 0 5 Mympram e Pipelined out SSRAM timing
273. rn rom select sema set seq shared short signal signed sizeof static struct switch e A definable width variable declaration of off chip interface use Internal clock internal clock with integer division set integer width start declaration of local macro expression declare 32 bit variable declare a macro declare a multi port RAM execute statements in parallel define target hardware execute first ready channel define macro as procedure declare a RAM array declare register variable free semaphore reset design return from function declare a ROM array select expression or macro expr at compile time declare a semaphore specify device family or part int width target reset or clock execute statements in sequence declare a shared expression declare 16 bit variable declare a signal object declare a signed variable Reserved Not valid in Handel C specify variable with limited scope declare a structure variable switch statement between cases www celoxica com Yes No No No No No Yes No No No No No No No Yes No No Yes No No No No No No Yes No Yes Yes Yes Yes Yes Celoxica Page 320 Handel C Language Reference Manual try execute statements if Condition reset Condition is true during execution within related try block kers trysema Test if semaphore owned Take if not typedef define type typeof return type of expression und
274. ropriate data sheet for details Refer to the Xilinx FPGA data sheet for details of pull up and pull down resistors By default no pull up or pull down resistors are attached to the pins Example interface bus clock nimmt 4 in InBus with pull 1 data EK Jee Pe P1 F 12 24 quartus proj assign specification The quartus_proj_assign specification can be given to bus type interfaces or offchip RAM for EDIF output It allows you to specify Quartus project pins assignments Assignments are specified as a list of pairs of items enclosed in braces The items are strings and enclosed in quotes The first item in each pair specifies the item you are assigning and the second item specifies its value assignment_name assignment_value Example interface bus_out MyBusOut unsigned 3 outPort MyQutExpr with quartus_proj_assign TERMINATION Series ENABLE BUS HOLD CIRCUITRY On Standard HSTL_I strength 1 12 25 rate specification The rate specification may be given to a clock and is used to specify the frequency in MHz at which the clock will need to be driven The specification only applies to EDIF output it is ignored for other outputs The rate specification causes Handel C to generate one of the following e a Gate field Constraints File GCF for Actel ProASIC and ProASIC e an Assignments and Constraints File ACF for use with Max Plusll for non Apex Altera dev
275. rrrererrererrrrrrerrrrsrrrre 138 7 33 SCICCE el e LEE 138 E EP MSS EE 139 7 3 5 Recursive macro EXPFESSIONS eee e ee eeeee eee eeeeeeeeeeseeeeeeeseeegaeeeeeeages 140 7 3 6 Recursive macro expressions example cc cee cece cece cece eeeeeeeeeeeeeeeeeeeeegaes 142 K er EE ge RE e e EE 142 7 3 8 Using recursion to generate Shared EXPIreSSIONS ccccceeeee eee eeeeeeeeeeeeeees 143 7 3 9 ele ON shared exvpreseions cece ccccce cece cece cece eeeeeeeeeeeeeeeeeeeeeeenees 143 K OS eee Pee ee ee Tn ee ee te E re errr Tere 144 7 3 11 Macro eee SEENEN 145 7 3 12 Macro procedures compared to pre processor maCTOos 146 8 l NTRODUCTI ON TO TI MI NG EENEG E 8 1 STATEMENT TI MI NG AEA AG oL EXIM ENNO aE a E EE A E EA 148 8 1 2 Statement timing SUMMALY essssesersererrrrrrerrrrerrrrrrererrrrerrererrrrererrrrerrrre 154 8 2 AVOIDING COMBI NATI ONAL LOOPS ssunnnsnnnuunnnnnnununnnnnuunnnnnnnnnnnnnnnn LOO 8 3 PARALLEL ACCESS TO VARIABLES sssssnnuuunnnnnuuunnnnnnuunnnnnnnnnnnnnnnnnnnnn LDO 8 4 DETAILED TIMING EXAMPLE ssssnunnnnnnnuunnnnnnnunnnnnnnunnnnnnnnnnnnnnnnnnnnnn LOQ 8 5 TIME EFFICIENCY OF HANDEL C HARDWARE sasussnnuunnnnunnnnunnnnnnnnnnnnn LOL e Reducing logic e EE 161 S INN www celoxica com Page 4 Handel C Language Reference Manual Celoxica o REPA GA e ie e E EE 164 9 CLOCKS OVERVIEW caccsosscescastecescoatecunseussnsucwaeswavensienewesuvesuvewevcsecowenn 167 9 1 LOCATING THE CLOCK fiisnssessse
276. s There are many ways in which a much used code fragment can be expressed The examples below all multiply a value by 1 5 For hints on when to use the different types of macros and functions see e Functions and macros overview e Comparison of macros and functions Preprocessor macro define de_sesqui s s s gt gt 1 define dp_sesqui d s d s s gt gt 1 Macro expression macro expr me_sesqui s s s gt gt 1 Shared expression Shared expr se_sesqui s s s gt gt 1 Macro procedure macro proc mp_sesqui d s d S d d gt gt Ers Function void f_sesqui int d int s shared function without return d S sA a d gt gt Li S INN www celoxica com Page 121 Handel C Language Reference Manual Celoxica int rf_sesqui int s shared function with return int ret ret S ret ret gt gt 1 return ret Array of functions void af_sesqui 5 int d int s function array without return C 5 oe CC dy Ge Kies int arf_sesqui 5 int s function array with return int ret ret S ret ret gt gt 1 return ret Inline function void inline if_sesqui int d int s inline function without return x d S d CES d gt gt 17 inline function with return int inline irf_sesqui int s int ret ret S ret ret gt gt 1 return ret How to call
277. s with data P4 g P2 RITEN int 4 x x InBus 1o This declares a bus connected to pins P1 P2 P3 and P4 where pin P4 is the most Significant bit and pin P3 is the least significant bit The variable x is set to the value on the external pins The type of InBus To is int 4 as specified in the type list after the bus_in keyword 11 1 2 Registered reading from external pins bus_latch_in The bus_latch_in interface sort is similar to bus_in but allows the input to be registered on a condition This may be required to sample the signal at particular times Its general usage Is interface bus_latch_in type portName Name type conditionPortName Condi tion with data Pin List Reading the bus is performed by accessing the identifier Name portName as a variable which will return the value on those pins at that clock edge If no input port name is given the port name defaults to in Condition specifies a signal that is used to clock the input registers in the FPGA or PLD The rising edge of this signal clocks the external Signal into the internal value Example unsigned 1 get Intl x interface bus_latch_in int 4 To InBus unsigned 1 condition get with data P4 EST PE PITE get 0 get 1 Register the external value x InBus To Read the registered value S INN www celoxica com Page 227 Handel C Language Reference Manual Celoxica 11 1 3 Clocked reading from external pins
278. s asynchronously with the Handel C clock then routing delays within the FPGA can cause the value to be read differently in different parts of the circuit The solution to this problem is to use either a bus_latch_in or a bus_clock_in interface sort bus out interfaces The output value on pins cannot be guaranteed except at rising Handel C clock edges In between clock edges the value may be in the process of changing Since the routing delays through different parts of the logic of the output expression are different some pins may change before others giving rise to intermediate values appearing on the pins This is particularly apparent in deep combinational logic Adding a flip flop to the output as shown in the bus_out example will minimize these effects Race conditions within the combinational logic can lead to glitches on output pins between clock edges When this happens pins may glitch from O to 1 and back to zero or vice versa as signals propagate through the combinational logic Adding a flip flop at the output removes these effects Bi directional tri state buses The timing considerations for bus_in and bus out interfaces should also be taken into account when using bi directional tri state buses since these are effectively a combination of an input bus and an output bus 11 5 1 Example timing considerations for input buses interface bus_in int 1 read aC with data P1 par d x a read y a read S INN
279. s _ ts_latch_in The bus_ts_latch_in interface sort allows Handel C programs to perform bidirectional off chip communications via external pins with inputs registered on a condition Its general usage Is S INN www celoxica com Page 229 Handel C Language Reference Manual Celoxica Interface bus_ts_latch_in type inPortName Name type outPortName Value type conditionPortName Condition type clockPortName Clock with Specs Value is an expression giving the value to output on the pins Condition is an expression giving the condition for driving the pins Clock is an expression giving the Signal to clock the input from the pins When Condition is non zero i e true the value of Value is driven on the pins When the value of Condition is zero the pins are tri stated and the registered value of the external bus can be read using the identifier Name inPortName If inPortName is not defined the port name defaults to in The rising edge of the value of the third expression clocks the external values through to the internal values on the chip If you attempt to read from a tri state bus when it is in write mode i e condition is non zero you will get the value that you are writing to the bus Example int 1 get unsigned 1 condition int 4 x interface bus_ts_latch_in int 4 read BiBus int write x 1 unsigned 1 enable condition unsigned 1 clock_port get with data P4 P3 P2 PI conditi
280. s then taken high for one clock cycle and the data sampled on the falling edge of the strobe H andel C clock TE Readkeady Read D3 0 S INN www celoxica com Page 232 Handel C Language Reference Manual Celoxica Write cycle timing A write to the device is performed by waiting for WriteRdy to become active high The Write signal is then taken high for one clock cycle while the data is driven to the device by the FPGA The device samples the data on the falling edge of the Write signal Handel C clock 2 e WriteR ear Mun te ER ee Bus declarations The first stage of the code declares the buses associated with each of the external Signals int 4 Data int 1 En Oe interface bus_ts_clock_in int 4 Dataln dataB int outPort Data int EnableSignal En with data 7 P4 P3 MP2 PI int 1 Write 0 interface bus_out writeB int WriteSignal Write with data P5 int 1 Read Q interface bus_out readB int readSignal Read with data P6 interface bus_clock_in int 1 wr WriteReady with data P Interface bus_clock_in int 1 readySignal ReadReady with data P8 S INN www celoxica com Page 233 Handel C Language Reference Manual Celoxica void main void int 4 Data Reg Read word from external device while ReadReady readySignal 0 delay Read 1 Set the read strobe par dataB Dataln Read th
281. s via external pins Its general usage is S INN www celoxica com Page 228 Handel C Language Reference Manual Celoxica interface bus_ts type inPortName Name type outPortName Value type conditionPortName Condition with Specs Value is an expression giving the value to output on the pins Condition is an expression giving the condition for driving the pins When Condition is non zero i e true the value of Value is driven on the pins When the value of Condition is zero the pins are tri stated and the value of the external bus can be read using the identifier Name inPortName If 7nPortName is not defined the port name defaults to in If you attempt to read from a tri state bus when it is in write mode i e condition is non zero you will get the value that you are writing to the bus Example unsigned 1 condition int 4 x interface bus_ts int 4 read BiBus int write x 1 unsigned 1 enable condition With data ACEL PS DR PI condition 0 Tri state the pins x BiBus read Read the value condition 1 Drive x 1 onto the pins This example reads the value of the external bus into variable x and then drives the value of x 1 onto the external pins x Take care when driving tri state buses that the FPGA PLD and another device on the bus cannot drive simultaneously as this may result in damage to one or both of them 11 1 6 Bidirectional data transfer with registered input bu
282. sable some compiler warnings 1 No 4 7 RAMs and ROMs RAMs and ROMs may be built from the logic provided in the FPGA PLD using the ram and rom keywords For example ram int 6 a 43 Static rom int 16 b 4 23 46 69 92 This example constructs a RAM consisting of 43 entries each of which is 6 bits wide and a ROM consisting of 4 entries each of which is 16 bits wide ROMs must be declared as static or global If you declare a static ROM in a macro procedure each call to the macro creates a separate version of the ROM RAMs can be declared as static global or auto i e non static All RAMs and ROMs must be declared as arrays so to declare a RAM that holds one 4 bit integer you must declare it as an array with a dimension of 1 ram int 4 ramname 1 HE RAMs and ROMs may only have one entry accessed in any clock cycle 4 7 1 Initialization You can only initialize ROMs or RAMs if they are static or have global scope For example a global ROM could be initialized as shown below rom int 16 b 4 23 46 69 92 with block 1 The ROM is initialized with the constants given in the following list in the same way as an array would be initialized in C In this example the ROM entries are given the following values S INN www celoxica com Page 61 Handel C Language Reference Manual Celoxica ROM entry Value bLO 23 bL1 46 b 2 69 b 3 92 4 7 2 Inferring size from use The Handel C compiler
283. signed func 2 unsigned x unsigned y return x y Syntax The syntax is a normal function declaration with square brackets added to specify that this is an array declaration as well as a function declaration The general form of a function array declaration is returnlype NameLSize parameterList e A www celoxica com Page 126 Handel C Language Reference Manual 7 2 4 Function arrays example set clock external P1 Function array prototype unsigned func 2 unsigned x unsigned y Main program void main void unsigned a b c d e f nsigned snort rl r2 r3 T4 unsigned result par d a 12 b 22 c 32 d 42 e 52 f 62 par d rl funclOl a b PZ TUNEL Cy d par d r3 funclOl e f r4 funclLllj rl r2 result funcLO r3 r4 Celoxica l www celoxica com Page 127 Handel C Language Reference Manual Celoxica Function array definition unsigned func 2 unsigned x unsigned y return x y 7 2 5 Function arrays example with static variables In the example below each function in the array has its own copy of the static variable t Thus if func 0O s copy of t is modified func 1 s copy remains unaffected S INN www celoxica com Page 128 Handel C Language Reference Manual Celoxica set clock external C1 unsigned funclL2 unsigned a unsigned b Static unsigned t 0 Ls
284. so it can deal with variable latency It is unsafe to rely on a particular observed latency either in hardware or in simulation S INN www celoxica com Page 176 Handel C Language Reference Manual Celoxica x Do not make assumptions about the latency of cross clock domain channels The effect of constraining unconstrained paths Unconstrained paths are created in the synchronization hardware used to connect channels across clock domains set clock external C43 with rate 40 unconstrainedperiod 100 minperiod 5 unconstrainedperiod can be given a value to stop place and route tools giving an unconstrained period warning If latency Is critical in your design note that as the value of unconstrainedperiod increases latency may increase Clock A Clock B ee tes cr unconstrainedperiod KR resolution time tres BEEN minperiod Throughput between clock domains using channels To ensure a throughput of one word per cycle between clock domains you need to have a sufficiently large FIFO The table below shows the average clock cycles needed to send 1000 words from one clock domain to another of a similar frequency and back again It was measured in the originating domain using timing accurate simulation of a back annotated netlist S INN www celoxica com Page 177 Handel C Language Reference Manual Celoxica fifolength paranoia 0 1 2 0 5008 7010 9011 1 5008 7010 9011 2 3009
285. specification may be used in conjunction with the standard specification on any external bus interface not port_in or port_out connected to pins to select the drive current in mA to be used on all pins of that interface It may also be applied to off chip memories You can only use the strength specification for EDIF output Different device families support different values The compiler will issue warnings if a non supported value is selected for a particular device Check the device datasheet to confirm what values it supports The following standards do not support drive strength selection PCI GTL HSTL III HSTL IV CTT AGP 1x AGP 2x LVDS LVPECL LVDCI and BLVDS The following devices do not support drive strength selection for any standards Excalibur Apex 20 Apex 20KE and Apex 20KC Example interface bus_out Eel int 4 outPort x with data dataPinsO standard HSTL_I strength 1 interface bus_ts unsigned 3 inPort Baboon apel y ape2 en with data dataPinsT standard LVTTL strength 24 S INN www celoxica com Page 303 Handel C Language Reference Manual Celoxica 12 35 synchronous specification The synchronous specification may be given to a reset signal The value of this specification controls whether the reset is synchronous occurs on next clock tick or asynchronous occurs immediately The default is asynchronous 0 Example set reset external with synchronous 1 12 36
286. string Depends on value target architecture and type of interface string None value pair OR string value string triplet string None value pair string bool for 1 value bit wide ports uint otherwise string Std_logic value for 1 bit wide ports unsigned otherwise Specifications can be added to objects as follows unsigned 4 w with show 0 int 5 x with show 0 base 2 chanout char y with outfile output dat chanin int 8 z with tinfile input dat interface bus clock nimmt 4 in InBus with K PUL 1 data 4 P47 Pog P2 Applies to interface port bus type interfaces external clocks amp resets generic interfaces bus type interfaces offchip RAM port_in port_out or generic interfaces port_in port_out or generic interfaces Ee d Meaning Bind component to work library In EDIF specify type of buffer to build In EDIF Parameterize Instantiations of external black boxes In VHDL Define generics In Verilog Define parameters In EDIF specify Quartus project pins assignments Create a SystemC port of a specified type Create a VHDL port of a specified type S INN www celoxica com Page 260 Handel C Language Reference Manual Celoxica 12 2 base specification The base specification may be given to variable output channel output bus and tri state bus declarations You can only use it for simulation output Deb
287. structures On chip RAMs in Altera FlexlOK devices use the EAB structures These blocks can be configured in a number of data width address width combinations When writing Handel C programs you must be careful not to exceed the number of EAB blocks in the target device or the design will not place and route successfully While it is possible to use RAMs that do not match one of the data width address width combinations EAB space may be wasted by such a RAM Synchronous and asynchronous access RAM blocks in Flex Apex Excalibur and Mercury parts can be configured to be either synchronous or asynchronous If you do not apply any clock or write enable Specifications Handel C will create RAMs with a synchronous write port and asynchronous read port as long as the target hardware supports It If you apply clock position specifications to the RAM the read and write ports will both be synchronous If you apply any of the write enable specifications westart welength or wegate to the RAM both write and read access will be asynchronous When declaring a memory as a MPRAM if you only apply write enable specifications to the read port AND you apply clock specifications to the write port you will get a compiler error aS you cannot have an asynchronous write port and a synchronous read port S INN www celoxica com Page 218 Handel C Language Reference Manual Celoxica nitialization RAM ROM initialization files with a mif exte
288. sults chanout int x y with foutfile out dat chanout unsigned a b with outfile out dat The filename passed to infile and outfile is a standard string and follows all string rules including the need to specify the backslash character as 12 15 intime and outtime specifications The intime specification may be given to an input port or bus tri state bus foreign code memory or off chip memory The outtime specification may be given to an output port or bus tri state bus foreign code memory or off chip memory The specifications are only valid for EDIF output intime specifies the maximum delay in ns allowed between an interface or memory interface and the sequential elements it feeds outtime specifies the maximum delay in ns allowed between an interface or memory interface and the sequential elements it is fed from They can be floating point numbers For example macro expr memoryPins P13 P12 P11 P10 P9 PB al a cae PO ks macro expr dataPins P4 P3 P2 P1 interface bus_in unsigned 4 dataIn hword with data dataPins intime 5 interface port_out new_hword unsigned 4 out hword dataIn 1 with outtime 5 2 ram int 8 aL15 L43 with outtime 5 2 OTT Chip 1 data memoryPins When applied to Actel ProASIC devices intime and outtime specifications cause Handel C to generate a GCF file for the design When an Altera device is the target Handel C generates ACF or
289. t int A out interface port_in int 1 To read with sc_type sc_logic interface port_out drive int 4 From X_out with sc_type sc_int results in Handel C generating the SystemC ports Sc ins sc logic gt Io sc_out lt sc_int lt 4 gt gt From e A www celoxica com Page 292 Handel C Language Reference Manual Celoxica 12 30 show specification The show specification may be given to variable channel output bus and tri state bus declarations When set to 0 this specification tells the Handel C simulator not to list this object in its output This means that it will not appear in the Variables debug window in the GUI but it can be seen in the Watch window The default value of this specification is 1 int 5 x with show 0 12 31 speed specification The speed specification may be given to an output or tri state bus It only applies to EDIF output The value of this specification controls the slew rate of the output buffer for the pins on the bus For Actel ProASIC and ProASIC devices there are three possible values O slow 1 normal and 2 fast default value For Altera devices Xilinx Virtex series and Xilinx Spartan I and Spartan 3 series O is Slow 1 is fast and the default value is 1 Refer to the Altera or Xilinx data sheets for details of slew rate control Example interface bus_out drive int 4 signals_from_HC X_out with speed 0 12 32 standard specification The sta
290. t time t4 the main Handel C rising clock edge clocks the data that has been read from the memory into the pipeline register as well as initiating the next read cycle e At event e5 after the write to register operation has completed the data that has been written becomes available at the register output Rout e At time t5 the data that was read via the pipeline register DO in this case is ready to be clocked into its destination Two further read cycles are performed starting at time t4 and t5 Pipelined access to RAM ei ea ea adj 3 write cycles are performed e At time tO the main Handel C rising clock edge initiates a write cycle e At event el WE is asserted and Addr and Din are set up meaning that when the memory is next clocked the data at Din will be written at the location specified in Addr e At time t1 the main Handel C rising clock edge clocks the memory as well as initiating the next write cycle www celoxica com Page 206 Handel C Language Reference Manual Celoxica e At event e2 after the write operation has completed the data that has been written becomes available at the output from the memory Dout Two further write cycles are performed starting at time t1 and t2 This is followed by a read cycle e At time t3 the main Handel C rising clock edge initiates a read cycle e At event e3 WE is de asserted and Addr is set up meaning that when the memory is next clocked
291. tal number e g o 77 xnumber hexadecimal number e g xf3 4 1 3 Constants Constants may be used in expressions Decimal constants are written as simply the number while hexadecimal constants must be prefixed with 0x or 0X octal constants E www celoxica com Page 37 Handel C Language Reference Manual Celoxica must be prefixed with a zero and binary constants must be prefixed with 0b or OB For example w 1234 Decimal SST x 0x1234 Hexadecimal y 01234 OCT al a z 0b00100110 Binary a The width of a constant may be explicitly given by casting For example x unsigned int 3 1 Casting may be necessary where the compiler is unable to infer the width of the constant from its usage 4 2 Logic types The basic logic type is an int It may be qualified as signed or unsigned Integers can be manually assigned a width by the programmer or the compiler will attempt to infer a width from use Enumeration types enums allow you to define a specified set of values that a variable of this type may hold There are derived types types that are derived from the basic types These are arrays pointers structs bit fields and functions The non type void enables you to declare empty parameter lists or functions that do not return a value The typeof type operator allows you to reference the type of a variable 4 2 1 int There is only one fundamental type for variables int By default integers a
292. tatement semi_statement expression_statement do statement while expression jump_statement assert constant_expression assignment_expression assignment_expression delay channel statement set statement non_semi_statement labelled_statement compound_statement selection_statement 7teration_statement The following statements can appear in for start end conditions e A www celoxica com Page 328 Handel C Language Reference Manual Celoxica for_statement non_semi_statement expression_statement do statement while expression assert constant_expression constant_expression L assignment_expressiont assignment_expression delay channel statement These are the statements that can appear in prialt blocks l www celoxica com Page 329 Handel C Language Reference Manual Celoxica prialt_statement semi_statement non_semi_prialt_statement non_semi_prialt_statement prialt_labelled_statement compound_statement selection_statement 7teration_statement labelled_statement identifier statement case constant_expression statement default statement prialt_labeled_statement identifier prialt_statement case channel_statement prialt_statement default prialt_statement expression_statement expression Channel_statement unary_expression expression logical_or_expression expression jump
293. technique for optimizing efficiency is to use pipelining 8 5 1 Reducing logic depth Certain operations in Handel C combine to produce deep logic Deep logic results in long path delays in the final circuit so reducing logic depth should increase clock speed Guidelines for reducing logic depth e Division and modulo operators produce the deepest logic Multiplication also produces deep logic A single cycle divide mod or multiplier produces a large amount of hardware and long delays through deep logic so you should avoid using them wherever possible e Most common division and multiplications can be done with the shift operators Also consider using a long multiplication with a loop shift and add routine or a pipelined multiplier e Most common modulo operations can be done with the AND operator e Wide adders require deep logic for the carry ripple Consider using more clock cycles with shorter adders e Avoid greater than and less than comparisons they produce deep logic www celoxica com Page 161 Handel C Language Reference Manual Celoxica e Reduce complex expressions into a number of stages e Avoid long strings of empty statements Empty statements result from for example missing else conditions from if statements Adder example To reduce a single 8 bit wide adder to 3 narrower adders unsigned 8 x unsigned 8 y unsigned 5 templ unsigned 4 temp2 par templ 0 x lt 4 0 y lt 4 temp2
294. termine when two assignments are made to the same variable on the same clock cycle You should therefore check your code to ensure that the relaxed rule of parallelism is still obeyed Example Using this technique a four place queue can be written while 1 d par int A ECK xLO in xL1 xL0 x 2 x 1 Out X2 The value of out is the value of in delayed by 4 clock cycles On each clock cycle values will move one place through the x array For example e A www celoxica com Page 158 Handel C Language Reference Manual Celoxica Clock in x O x 1 x 2 out 1 5 0 0 0 0 2 6 5 0 0 0 3 7 6 5 0 0 4 8 7 6 5 0 5 9 8 7 6 5 6 10 9 8 7 6 7 11 10 9 8 7 8 12 11 10 9 8 9 13 12 11 10 9 8 4 Detailed timing example This is an analyzed example that generates signals tied to real world constraints It shows the generation of signals for a real time clock The signals required are for microseconds seconds minutes and hours The hardware generated will eventually be driven from an external clock In order to write the program the rate of this clock must be known It has been assumed to be 5 MHz on pin P1 The loop body takes one clock cycle to execute The Count variable is used to divide the clock by 5 to generate microsecond increments As each variable wraps round to zero the next time step up is incremented S INN www celoxica com Page 159 Handel C Language Reference Manual Celoxica set clock
295. ternal with clockport 0 standard LVCMOS33 dci 1 e A www celoxica com Page 2 70 Handel C Language Reference Manual Celoxica This instructs the compiler to build an external clock interface without using a dedicated Virtex I1 clock input resource That is the clock interface logic built will be Handel C clock Pin BUF G 12 9 data specification pin constraints The data specification can be used to constrain pin location or to name ports e When applied to bus type interfaces or off chip memories data specifies pin locations as a list of pin numbers separated by commas If you are using a differential I O standard the pins must be specified as pairs enclosed in braces e When applied to foreign code memories using with ports 1 port type interfaces and generic interfaces data specifies port names as a list of names separated by commas If the data specification is omitted for bus type interfaces or off chip memories the place and route tools will assign the pins The pins are listed in order MSB to LSB but the LSB pin rightmost element of list is assigned first If you do not assign all the pins used the MSB pins remain unassigned If you are targeting EDIF output the data specification can also be used for a port_in or port_out interface to specify the names of the ports to be exported This part of the data specification is ignored for VHDL or Verilog output If you are compiling your Handel
296. that the device is a 3 speed grade This last piece of information is required for the timing analysis of your design by the Altera Max Plus II or Quartus tools Note that when performing place and route on the resulting design the device and package must also be selected via the menus in the Max Plus II or Quartus software To target Actel ProASIC devices set family Actel500K Set part A500K270 BG4561 e A www celoxica com Page 192 Handel C Language Reference Manual Celoxica This instructs the compiler to target an Actel ProASIC device with 270 000 gates ina BG456 package It also specifies that the device is a standard speed grade and that the device is to be used for an industrial application the I at the end of the part string Specifies that the device is to conform to industrial temperature range standards The speed information is required for the timing analysis of your design by the Actel Designer tools The application information industrial in this example is required for place and route of your design by the Actel Designer tools Note that when performing place and route on the resulting design the device and package must also be selected via the menus in the Designer software 10 2 4 Specifying a global reset set reset allows you to reset your device into a known state at any time It is particularly useful for setting up devices which are not in a known state at start up set reset causes the program
297. the address and data lines and one quarter of a clock cycle for the RAM hold times This is the recommended way to access asynchronous RAMs e A www celoxica com Page 194 Handel C Language Reference Manual Celoxica Fast external clock example To declare a 16Kbyte by 8 bit RAM set clock external_divide P99 4 ram unsigned 8 ExtRAM 16384 with offchip 1 westart 2 welength 1 data dE Po Mot eA DEN He py Pe addr po P10 Pi Pi is pie pis Pig Rtg Pie PTO p20 P21 LSK we P23 oe P24 65 4 P25 1s The compiled hardware generates the following cycle for a write to external RAM Handel C clock hanes Data C 29 WEA IEF TH www celoxica com Page 195 Handel C Language Reference Manual Celoxica The compiled hardware generates the following cycle for a read from external RAM Handel C clock Address Data C 29 WEA IEF Same rate external clock This method of timing asynchronous RAMs uses multiple Handel C RAM accesses to meet the setup and hold times of the RAM ram unsigned 6 x 34 Dummy xL3 xL3 Data Dummy xL3 This code holds the address constant around the RAM write cycle enabling a write to an asynchronous RAM e A www celoxica com Page 196 Handel C Language Reference Manual Celoxica The timing diagram below shows the address being
298. the adjs macro and zero pad using the adju macro These macros are provided in the standard macro library within the Celoxica Platform Developer s Kit 6 3 Restrictions on RAMs and ROMs Because of their architecture RAMs and ROMS are restricted to performing operations sequentially Only one element of a RAM or ROM may be addressed in a single clock HE www celoxica com Page 104 Handel C Language Reference Manual Celoxica cycle In hardware this means you can only write one value to the address port of a memory allowing one read access or one write access You can detect simultaneous memory accesses when you are debugging your code by using the Detection of simultaneous memory accesses option on the Debug tab in Project Settings or the S parmem option in the command line compiler If you want to make more than one access to a memory at a time use an MPRAM multi ported RAM You can access more than one port at a time but you can only make a Single access to any one mpram port in a single clock cycle Example of disallowed assignment Only one element of a RAM or ROM may be addressed in any given clock cycle and as a result familiar looking statements will often produce unexpected results For example ram lt unsigned int 8 gt x 4 IUJ SL F 1 This code should not be used because the assignment attempts to read from the third element of x in the same cycle as it writes to the first element and the memory may pro
299. the behaviour of the ANSI C code in your C compiler 3 6 8 Handel C v C data input and output Handel C does not have functions equivalent to scanf and printf You can use scanf and printf when you are simulating a design as Handel C allows you to make calls to Handel C functions Alternatively you can use the Handel C infile and outfile specifications Both these methods allow you to debug an algorithm before you build it in hardware When you are targeting hardware data is passed between different parts of your Handel C design using channels If your Handel C design will receive data from or send data to external components you need to specify an interface These external components might be written in EDIF Verilog or VHDL or they could be an additional component specified in Handel C 3 6 9 Handel C v C memory allocation Memory allocation is not relevant when you are targeting hardware so Handel C has no equivalent of malloc and free You can use Handel C to create RAM or ROM blocks on an FPGA or PLD or interface to off chip memory 3 6 10 Handel C v C standard library The standard library in Handel C is called stdlib hcl This has no relationship to the C library stdlib 1lib or to stdio 1ib Stdlib hcl contains bit manipulation and arithmetic macros The standard library is now provided as part of the Platform Developer s Kit PDK If you do not already have a copy of PDK you can download it from the support
300. the example macros and functions The example macros and functions above can be called using code such as www celoxica com Page 122 Handel C Language Reference Manual Celoxica nt o x y x 10 y de_sesqui x dp_sesqui y x y me_sesqui x y se_sesqui x mp_sesqui y x f_sesqui amp y x y rf_sesqui x af_sesqui 2 amp y x y arf_sesqui 2 x if_sesqui amp y x y irf_sesqui x 7 1 5 Accessing external names You can refer to functions macros and shared expressions that have been defined in another file by prototyping them You prototype by declaring an object at the top of the file in which it is used Function prototypes are in the following format returnlype functionName parameterlypeList Macro prototypes are of the form macro expr Name parameterList macro proc Name parameterList Functions and macros may be static or extern static functions and macros may only be used in the file where they are defined You can collect all the prototypes into a single header file and then include it within your code files You can access variables declared in other files by using the extern keyword TH www celoxica com Page 123 Handel C Language Reference Manual Celoxica You cannot use variables to communicate between clock domains Variables are restricted to a single clock domain The only items that can connect across separate clock domains are chann
301. the following cycle for a write to external RAM Handel C clock Adc ess A x Data C 29 IEF The compiled hardware generates the following cycle for a read from external RAM Handel clock Address Data C 28 WEH QER Note that the timing diagram above may violate the hold time for some asynchronous RAM devices If the delay between rising clock edge and rising write enable is longer than the delay between rising clock edge and the change in data or address then corruption in HE www celoxica com Page 198 Handel C Language Reference Manual Celoxica the write may occur in these devices The two cycle access does not solve the problem since it is not possible to hold the data lines constant beyond the end of the clock cycle If this causes a problem then a multiplied external clock must be used as described above E Using the wegate specification may violate the hold time for some asynchronous RAM devices Targeting external asynchronous RAMs Handel C provides support for accessing off chip static RAMs in the same way as you access internal RAMs The syntax for an external RAM declaration is ram Type Name Size with offenip L data Pins addr Pins we Pins oe Pins cs Pins To declare a 16Kbyte by 8 bit RAM ram unsigned 8 ExtRAM 16384 with SECTEUR L dta a Pr po e Hae PHN PE P bot addr P9 P10 P11 P12 PLS Pe
302. the following directives ifdef identifier equivalent to if defined identifier ifndef identifier equivalent to if defined identifier These are used in the same way as if but are followed by an identifier rather than an expression The ifndef directive is often used to ensure that source code is only included once during compilation E g ifndef UTILCODE define UTILCODE Utility code is written here endi f 13 4 Line control A directive of the form line integer instructs the compiler that the next source line is the line number specified by integer If a filename token is also present line integer filename the compiler will additionally regard filename as the name of the current input file 13 5 Concatenation in macros If a macro is defined with a token sequence containing a operator each instance of is removed along with any surrounding white space thus concatenating adjacent tokens into one For example if the macro below was declared H define million X X e6 then TH www celoxica com Page 313 Handel C Language Reference Manual Celoxica i million 3 is expanded into 1 3e6 Take care when specifying parameters In the example above if 3e6 was passed instead of 3 then the line would be expanded into 1 3e6e6 which would result in an error 13 6 Error generation Fatal error messages may be reported during preprocessing using the directive H
303. to arrays to functions to interfaces 231 179 180 39 41 42 122 nH www celoxica com Page 343 75 131 278 111 111 278 275 293 293 293 290 293 276 276 264 276 276 276 264 232 264 186 276 232 207 207 183 122 41 17 39 39 34 123 42 Handel C Language Reference Manual DORE UW E 218 241 DOM SE 218 241 porting C to Handel Ce 32 Sieg 241 277 interfacing with external logic 241 port names 241 264 Specification 277 DO CANCE ee 12 PrEProCeSSOF ssssssrersre 303 305 306 concatenation 306 conditional compilation 305 error generation 307 file inclusion 304 line control 306 line splicing 307 macros 139 303 307 Droit 46 78 79 89 prialt examples 79 ProASIC de vices 180 183 constraints files 281 I O standards supported 289 296 pull up resistors 280 RAMs 210 slew rate on output buffer 286 Eeer 138 139 program Structure cece eee cece eens 9 EE 278 specification 278 protecting critical code 62 prototypes iccsrerestusirvacaseos 116 118 138 functions 118 macros 116 138 DU secsttccatesecatecusteratecscaubeeeseceusawes 280 QDR de vices ccc ceee eee e ee eeeeeeeeeeas 193 Oualftere ccc cece cece cece eee eeeeeeeeeeeeees 29 STan e E E E sens 281 assignments 281 Celoxica quartus proj assign specification 281 RAN BEE 57 186 187 193 Actel 210 Altera 211 arrays 56 asynchronous 187 192 300 block RAM 256 different to arrays 54 exter
304. traints files 281 embedded memory 209 I O standards supported 289 296 mprams 59 pull up resistors 280 RAMs 211 Strength epecification 296 string Constants cece cece cece eee eees 30 SUNG E 30 315 E e WEEN 36 structure member operator 109 structure pointer operator 109 structure pDointere cece cece eee eens 42 Strucures cece cece eee ee neces 36 42 319 storage 36 syntax 319 subtraction 104 SUMMAT ES eee c eee eee ees 10 12 14 309 keywords 309 operators 12 statements 10 types 14 SU ODON tee 32 180 devices 180 types for porting 32 SVG perrieri numerare tnae 88 89 termination 89 synchronization sssssererrererrrrerrrrne 6 synchronous RAMs193 195 204 261 282 clocks 193 195 196 261 examples 196 200 205 207 generating 282 read and write cycles 195 198 timing 196 198 200 282 EE EE E E E E 309 www celoxica com Celoxica take operator 102 Largdetmg 177 179 183 186 FPGA PLD devices 179 183 209 hardware 177 ports 243 RAM and ROM 54 186 specific tools 243 Bebe 269 281 RUNG E 141 154 233 asynchronous RAM 187 buses 233 235 constraints 269 270 281 efficiency 154 examples 141 152 233 introduction 141 SSRAM 195 282 statements 141 147 TriMatrix memon 209 tri state 218 221 222 224 232 294 buses 218 221 222 224 interfaces 218 294 pins 232 UY as EE 90 LEV SONU eege 92 CS eae ue E N 218 221 222
305. tructs which are not appropriate to hardware implementation This section summarizes the differences between Handel C and ANSI C It is not a definitive list Refer to specific sections to see how DK implements each of the language constructs S INN www celoxica com Page 22 Handel C Language Reference Manual Celoxica 3 6 1 Handel C v C types and type operators Handel C supports all ANSI C types apart from float double and long double You can still perform floating point arithmetic char short and long are supported to help the porting of code from ANSI C However it can be better more efficient in hardware terms to re express these as a signed or unsigned int of a specific width In Handel C ints are not limited to 64 bits Handel C has a range of additional types for creating channels and interfaces between different hardware blocks and for specifying memories and signals The Celoxica wide number library provides signed and unsigned compiler independent implementations of int32 and int64 Handel C also allows all ANSI C storage class specifiers and type qualifiers but volatile and register have no meaning in hardware terms and are accepted for compatibility only You have to specify the size of an array in Handel C For example you couldn t write int ailSIZE and then define SIZE Handel C variables can only be initialized if they are static const or global Otherwise you must assign a value to them in a stat
306. ts for details The diagram shows flip flops in separate clock domains The central flip flop receives data from the other clock domain Its value is copied to the second flip flop after 1 clock tick In that clock tick it must resolve metastability and pass through any routing and output and setup delays 11 6 1 Techniques to minimize the problem e use extra registers to stabilize the data e decouple the FPGA PLD from external synchronous hardware by using external buffer storage Stabilizing the data The ideal system is designed such that when data is clocked into a register it is guaranteed to be stable The solution is to clock the data into the Handel C program more than once so it is clocked into one register and the output of that register is then clocked into another register On the first clock edge the data could be changing state so the output could be metastable for a short time after the clock However as long as the clock period is long relative to the possible metastable period the second clock edge will clock stable data Even more clock edges further reduce the possibility of metastable states entering the program however the move from one clock to two clock ticks is the most significant and should be adequate for most systems The example below has 4 clock edges The first is in the bus_clock_in procedure and the next 3 are in the assignments to the variables x y and zZ TH www celoxica com Pa
307. types can be used in derived types such as structures arrays or functions but there may be some restrictions on the use of architectural types Specifiers The type specifiers signed unsigned and undefined define whether the variable is signed and whether it takes a default defined width You can use the storage class specifiers extern and static to define the scope of any variable Functions can have the storage class inline to show that they are expanded in line rather than being shared Type qualifiers Handel C supports the type qualifiers const and volatile to increase compatibility with ANSI C These can be used to further qualify logic types Disambiguator Handel C supports the extension lt gt This can be used to clarify complex declarations of architectural types 4 1 1 Handel C values and widths A crucial difference between Handel C and conventional C is Handel C s ability to handle values of arbitrary width Since conventional C is targeted at general purpose microprocessors it handles 8 16 and 32 bit values well but cannot easily handle other widths When targeting hardware there is no reason to be tied to these data widths and so Handel C has been extended to allow types of any number of bits Handel C has also been extended to cope with extracting bits from values and joining values together to form wider values These operations require no hardware and can provide great performance improvements over software
308. ual Celoxica 4 12 2 extern external variables extern declares a variable that is external to all functions the variable may be accessed by name from any function External variables must be defined exactly once outside any function and declared in each function that wants to access them The declaration may be an explicit extern or else be implicit from the context if the variable has been defined outside a function without static If the variable is used in multiple source files it is good practice to collect all the extern declarations in a header file included at the top of each source file using the include headerFileName directive You may use extern language to access variables in C or C files Ei You cannot access the same variable from different clock domains Example extern int 16 global_fish int global_frog 1234 maint global_fish global_frog Syntax extern variable declaration 4 13 extern language construct The extern language construct allows you to declare that names used in Handel C code have ANSI C or C linkage e For ANSI C functions use extern C e For C functions use extern C These functions can only be compiled for simulations targeting the simulator They may not be used in targeting devices S INN www celoxica com Page 72 Handel C Language Reference Manual Celoxica extern C and extern C functions have the same timing as Handel C
309. ual Celoxica int mac x y To declare a pointer to a function returning that type you get int mac x f 4 21 2 lt gt type clarifier lt gt is a Handel C extension used to disambiguate complex declarations of architectural types You cannot use it on logic types It is good practice to use it whenever you declare channels memories or signals to clarify the format of data passed or stored in these variables It is required to disambiguate a declaration such as chan int x pointer to channel or channel of pointers This should be declared as chan lt int gt x channel of pointers or chan lt int gt x pointer to channel Example Struct fishtank int 4 koi int 6 Carp Int 2 Guppy bowl Signal lt struct fishtank gt drip chan lt int 8 runwater gt tap 4 21 3 Using signals to split up complex expressions You can use signals to split up complex expressions E g b Ca Zi 55 lt lt 2 100 could also be written S INN www celoxica com Page 79 Handel C Language Reference Manual Celoxica int LE a Db Signal sl s2 s3 S54 par sl a s2 Sl 2 s3 s2 55 s4 So lt lt 2 b s4 100 Breaking up expressions also enables you to re use sub expressions unsigned 15 a b signal sigl par sigl x 2 a sigl 3 b sigl 2 4 22 Variable initialization Global static and const variables Global
310. ug or Release The value that this specification is set to tell the Handel C compiler which base to display the value of the object in Valid bases are 2 8 10 and 16 for binary octal decimal and hexadecimal respectively The default value of this specification is 10 If you write with base 0 this is equivalent to not specifying a base Example int 5 x with base 2 12 3 bind specification The bind specification may be given to a user defined interface that connects to a component in external logic It only has meaning when instantiating an external block of code from Handel C generated VHDL or Verilog If bind is set to 1 it is assumed that the definition of the component exists in HDL elsewhere If it is set to O it does not and the component is assumed to be a black box In VHDL setting bind to 1 instantiates the component and generates a declaration of this component of which the definition is assumed to be within the work library Setting bind to O default instantiates the component and generates a black box component declaration In Verilog setting bind to 1 instantiates the component but does not declare it Setting bind to 0 instantiates the component and generates a black box component declaration This black box component declaration is an empty module which merely describes the interfaces of the component VHDL example 1 with bind set to 0 interface Bloo unsigned 1 myin BCunsigned 1 myout x with bind 0
311. unsigned 4 rax 4 with ports 1 void main void Static unsigned 2 1 Q while l par ae att rax i a a rax i LAA www celoxica com Page 221 Handel C Language Reference Manual The declaration of rax would produce wires rax_SPPort_addr lt 0 gt rax_SPPort_addr lt l gt rax_SPPort_data_in lt 0 gt rax_SPPort_data_in lt l gt rax_SPPort_data_in lt 2 gt rax_SPPort_data_in lt 3 gt rax_SPPort_data_out lt 0 gt rax_SPPort_data_out lt l1 gt rax_SPPort_data_out lt 2 gt rax 5FPort data out lt 3 gt rax_SPPort_data_en rax_SPPort_clk Fax SrPort es rax_SPPort_oe rax_SPPort_we i e LE e ei e 2 Address Data In Data Out Data Enable Clock Chip Select Output Enable Write Enable Celoxica www celoxica com Page 222 Handel C Language Reference Manual Generating an interface to a foreign code MPRAM set family X1linxVirtex set part V1000BG560 4 set clock external C1 unsigned 4 a mpram Mpaz wom unsigned 4 wox 4 rom unsigned 4 rox 4 mox with ports 1 void main void Static unsigned 2 1 0 while 1 par TTE grr mox woxLi a a mox rox i The declaration of the read only port rox would produce wires mox_rox_addr_0 Address mox_rox_addr_l mox_rox_clk Clock mMOX_rOX_CS Chip select mox_rox_data_en Data enable mox_rox_oe Output enable mox_rox_we Write enable Celoxica mox_r
312. urrently targeted by Handel C do so e g Altera Flex 10K APEX APEXII Mercury Stratix and Cyclone Xilinx Spartan series devices and Virtex series devices No Actel families support ROMs ProASIC and ProASIC devices support RAMs but these may not be initialized 4 7 6 Multidimensional memory arrays You can create simple multi dimensional arrays of memory using the ram rom and wom keywords The definitions can be made clearer by using the optional disambiguator lt gt Syntax ram rom wom logiclype entry_width NameLLconst_expression tLLconst_expression initialization Possible logic types are ints structs pointers and arrays The last constant expression is the index for the RAM The other indices give the number of copies of that type of RAM Example ram lt int 6 gt al 15 43 static rom lt int 16 gt b 4 2 2 1 2 3 4 Vs TA Oks EE 7 8 ie tA oy Oss 11 12 F 13 14 CS 1O e This example constructs 15 RAMs each consisting of 43 entries of 6 bits wide and 4 2 ROMs each consisting of 2 entries of 16 bits wide The ROM is initialized with the constants in the following list in the same way as a multidimensional array would be e A www celoxica com Page 63 Handel C Language Reference Manual Celoxica initialized in C The last index that of the RAM entry changes fastest In this example the ROM entries are given the following values ROM entry Value RO
313. us function calls In Handel C a function corresponds to a shared piece of hardware which may only be used by one thread at a time Simultaneous calls to a function or even overlapping execution of a function will cause problems S INN www celoxica com Page 134 Handel C Language Reference Manual Celoxica You can check for simultaneous accesses to a function when you are debugging your code by using the Detection of simultaneous function calls option on the Debug tab in Project Settings or the St tparfunc option in the command line compiler You can ensure that the function usage does not overlap by declaring functions to be inline so they are expanded whenever they are used or by declaring an array of functions one to be used in each parallel branch This ts illustrated in the example below Example int FUNGCINE x int Mk void main void d int a b c d e f foo etc ax par a func b c b foo d func e f NOT ALLOWED etc int func int x int y if x y delay else X X ky x 10 return x This is not allowed because part of the single function is used twice in the same clock cycle The code can be re written to use inline functions or an array of functions www celoxica com Page 135 Handel C Language Reference Manual Celoxica inline int func x y par a func b c b foo d func e f or int funcL2 x y
314. us or clock It can be used for any DK output When set to zero certain non crucial warnings will be disabled for that object When set to one the default value all warnings for that object will be enabled int 5 x with warn 0 12 39 wegate specification The wegate specification may be given to external or internal RAM declarations to place the write enable strobe You can only use this specification with an undivided clock If it is used in the absence of SRAM clock specifications rclkpos wclkpos and clkpulselen it forces the generation of an asynchronous memory or memory port If you have a divided clock use the westart and welength specifications instead The wegate specification is valid for EDIF VHDL and Verilog output When the wegate specification is set to 0 the write strobe will appear throughout the Handel C clock cycle When set to 1 the write strobe will appear only in the first half of the Handel C clock cycle When set to 1 the write strobe will appear only in the second half of the Handel C clock cycle You can apply the specification to the whole of a RAM or MPRAM or to individual write ports within an MPRAM Specifications applied to individual ports take precedence over Specifications applied to the whole memory Specifications applied to the whole memory apply to each port that does not have its own specification 12 40 westart and welength specifications The westart and welength specifications position th
315. ut 4 on channel 4 5 3 Restrictions on channel accesses No two statements may simultaneously write to or simultaneously read from a single channel S INN www celoxica com Page 53 Handel C Language Reference Manual Celoxica par out 3 Undefined simultaneous send to a channel out 4 This code will give an undefined result as it attempts to write simultaneously to a single channel Similarly the following code will not work because an attempt is made to read Simultaneously from the same channel par in x Undefined simultaneous receive from a channel in y Your code should not rely on the perceived behaviour of multiple simultaneous reads and writes in either simulation or hardware You can detect parallel accesses to channel during simulation using the Detection of simultaneous channel reads writes option on the Compiler tab in Project Settings or by using the S parchan option in the command line compiler Simultaneous channel access concealed within prialt The prialt construct negotiates the readiness of the remote i e non prialt end of channel It does not resolve conflicts at the local i e prialt end of the channel The programmer must still avoid simultaneous channel accesses even if the send or receive statements are inside a prialt statement e A www celoxica com Page 54 Handel C Language Reference Manual Celoxica Examples int 4 x y Z chan lt int 4 gt c
316. ved S INN www celoxica com Page 149 Handel C Language Reference Manual Celoxica For loop for OC Es xX Sg XEF a t b 2 This code has an almost direct equivalent x 0 while x lt 5 a b k Zs t This code takes 16 clock cycles to execute One is required for the initialization of x and three for each execution of the body Since the body is executed 5 times this gives a total of 16 clock cycles Decision if a gt b d X a else x b This code takes exactly one clock cycle to execute Only one of the branches of the if statement is executed either x aorx b Each of these assignments takes one clock cycle Notice again that no time is taken for the test because no assignment is made A slightly different example is if Ca gt b xX a Here if a is not greater than b there is no else branch This code therefore takes either 1 clock cycle if a is greater than b or no clock cycles if a is not greater than b e A www celoxica com Page 150 Handel C Language Reference Manual Celoxica Channels Channel timings can be complex The simplest example is with a channel link of fifolength O default chan unsigned 8 link par link x Transmit link y Receive This code takes a single clock cycle to execute because both the transmitting and receiving branches are ready to transfer at the same time All that is required is the assi
317. x yL yL7 y 7 yL7 y OK y x lt 8 OK preserves the sign and copies the 7 LSBs Alternatively you can use the width adjustment macros in the Celoxica standard macro library stdlib hcl The adju macro adjusts the width of unsigned numbers and the adjs macro adjusts the widths of signed numbers The standard library is now provided as part of the Platform Developer s Kit PDK If you do not already have a copy of PDK you can download it from the support section of the Celoxica web site sizeof There is no sizeof in Handel C For simple types signed and unsigned char int long and short you can use the width operator For example sizeof long in Cis equivalent to width long in Handel C except that the number of bytes is returned in C and the number of bits is returned in Handel C 3 6 4 Handel C v C side effects There are restrictions on how you can use side effects in Handel C because each statement must only take one clock cycle Each statement can only contain a single assignment or an increment or a decrement This means that e Shortcut assignments e g must appear as standalone statements e The initialization and iteration phases of for loops must be statements not expressions If you are porting ANSI C code complex statements have to be re written as multiple single statements It is often more efficient to run these statements in parallel You cannot use comma operators in Handel C
318. x VirtexE series SelectRAM dual Block RAM dual port FPGAS port Xilinx Virtex I1 series SelectRAM dual Block RAM dual port FPGAS port Xilinx Virtex I1 Pro SelectRAM dual Block RAM dual port series FPGAS port Xilinx Virtex I1 Pro X SelectRAM dual Block RAM dual port series FPGAS port Xilinx Virtex 4 series SelectRAM dual Block RAM dual port FPGAS port Generic VHDL or Verilog projects only Results in HDL without target specific constructs 10 2 2 Detecting the current device family The __isfamily construct allows you to detect what the current device family is If you are writing platform independent libraries you can use this to conditionally select pieces of the source code to exploit the resources available on different FPGAs The construct takes a device string and returns true or false The possible device names are the same as those used to specify devices with the set family construct An error is returned if the string specified inside the construct is not a recognized family string e A www celoxica com Page 189 Handel C Language Reference Manual Celoxica Example set family X1linxVirtex macro expr DoThis select __isfamily XilinxVirtex DoThingl select __isfamily AlteraApex20K DoThing2 select __isfamily MadeUpDevice DoThing3 DoThing4 The first use of __isfamily would return true the second would return false and the third would result in a compile
319. y may cause the generated hardware to be unreliable You must test channels communicating between clock domains extremely thoroughly unless you know that resolutiontime is sufficiently long to guarantee an acceptable probability of failure Timing issues for channels communicating between clock domains The timing of channels across clock domains is unspecified The values read into i and j may differ in the example below as the reads may not complete on the same clock cycle S INN www celoxica com Page 170 Handel C Language Reference Manual Celoxica Domain lL set clock external with paranoia l minperiod 2 0 unconstrainedperiod 9 rate 101 chan lt unsigned 8 gt chl ch2 unsigned 8 1 Q while 1 par while 1 7 chi JL a ehiz 1 Domain 2 set clock external with minperiod 2 0 unconstrainedperiod 10 rate 100 extern chan chl ch2 unsigned 81 j while 1 par chi j Chic T Channel communication example This example uses a channel to communicate between two clock domains One clock domain runs at half the speed of the other e A www celoxica com Page 171 Handel C Language Reference Manual Celoxica ZS File receive hcc primary Clock domain SS set clock external A22 with rate 100 resolutiontime 7 5 unsigned 4 result interface bus_out OCunsigned o result with warn 0 channel defined in other file extern chan unsigned
320. y used break IAL 4 X y chan lt int 4 gt ch prialt case ch x break case ch y illegal ch already used break Celoxica www celoxica com Page 87 Handel C Language Reference Manual Celoxica 5 6 Assignments Handel C assignments are of the form Variable Expression For example X 3 y a b The expression on the right hand side must be of the same width and type signed or unsigned as the variable on the left hand side The compiler generates an error if this is not the case The left hand side of the assignment may be any variable array element or RAM element The right hand side of the assignment may be any expression Short cuts The following short cut assignment statements cannot be used in expressions as they can in conventional C but only in stand alone statements See Introduction Expressions for more information Shortcuts cannot be used with RAM variables as they contravene the RAM access restrictions e A www celoxica com Page 88 Handel C Language Reference Manual Celoxica Statement Expansion Variable Variable Variable 1 Variable Variable Variable 1 Variable Variable Variable 1 Variable Variable Variable 1 Variable Variable Variable Expression Expression Variable Variable Variable Expression Expression Variable Variable Variable Expression Expression Variable Variable Variable

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