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SN8F27E64

1. Ji DC 7 5V Di U1 7805CT 1 1 3 VDD 50 Q a 14004 iii vo so 50 d VDD Ext x 9 tas 0822 VDD SW 1 VDD Ext ol 1 100u 16V 2uj6V VDD 42 VDD Ext is VDD EXT VDD Ext 5 3 VDD d d VDD_EXT JP4 2 VRD JP3 O 1 2p X o 3 5 55 vss U2 1117 33 aes Pii VSS VDD 503 2 VDD 5 5 PLO VSS 2 VIN VOUT S 9 8 IUUD a WCU LED 10 o 65 d DEBUG VSS 22u 16V R2 55 470 1 32 04 VDD3V AVREFH imn a bos PTS DD DD 3 9 30 P0 6 5 Poo 41501 0 6 29 VSS 0 0 biz 21008 vaes 28 VDD3V ca R3 P0 2 H 3 a 27 0 10 0 10 10 47K R4 8 P0 5 URXPO 2 of 2 eee R 508 35 H VSS SDAPL2 o 2 B 1 35 SERER 25 vss vss 24 240 PORTO UARTIMSP SETE P4 23 22 4 2 PQs PQS 9 swa C10 JPG Pio 121511 PA2 2i 1 0 1 1 JP10 18 pre bay 20 16M lo RESET CAP 512 o 4 P13 0021 4 2 b 21 5801 bis T0 PAS Pia gs PLS SCKPLE 51 2 B ELISCS 1024 HA Lie otu tou ci C15 vss SS 1 7 Poo d Fo Dis LIT Par 20p 20p 510 vss vss PORTI SNSFZ7E6
2. 174 17 ROM PROGRAMMING PIN cccccssscscsssssssssssccsssssssscscesssesessscescsssssescssesssessssscesssssesessssecssessssssessssseses 175 17 1 WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT 175 17 2 WRITER PROGRAMMING PIN 176 RR m 179 18 INTRODUCTION Em 179 18 2 MARKING INDETIFICATION 5 5 179 18 3 MARKING EXAMPLE 55 5 180 18 4 DATECODE SYSTEM 181 19 PACKAGE INFORMATION 182 19 1 01 32 PIN 5i ette i eee ten ie tes 182 19 2 32 PIN nette eite totu etinm hen etu e d Ee 183 19 3 QFN 5X5 32 PIN 184 19 4 S DIP 32 185 19 5 55 1 1 28 dE 186 19 6 SOP 28 PIN 187 19575550 26 188 19 5 QFN 4X4 28 PIN 189 19 9 P DIP 20 PIN 190 1910S P IN 191 5 TECHNOLOGY CO LTD Pag
3. 35 2 2 8 5 36 2 29 W REGISTERS D 37 2 3 ADDRESSING MODE mm 38 2 3 1 IMMEDIATE ADDRESSING MODE div eM b RR A ade 38 2 3 2 DIRECTLY ADDRESSING MODE 38 2 3 3 INDIRECTLY ADDRESSING MODE bla 38 2A Wy e rS TION P 39 24A VFOYERVIE de 39 Pr M NITE POINTER qc e 39 24 3 STACK BUFFER C 40 24 45 40 2 4 5 STACK OPERATION EXAMPLE tu Leni 41 29 CODE OPTION TABLE rc 42 2 5 1 Code bi 43 2 3 2 I EEEa 43 2 5 3 Security ODEON 43 2 3 4 Noise Filter T I mU LIUM 43 44 Be UAV adire 44 3 2 POWER ON REED 45 33 WATCHDOG RESE 4
4. 133 10 5 BREAK c OQ 133 10 6 ABNORMAL POCKET 134 10 7 UART RECEIVER CONTROL REGES TER 134 10 8 DART TRANSMITTER CONTROL REGISTER cte tinte bre 135 10 9 DART DATA BUFFER 135 10 10 HART OPERATION EXAMLPE pe tU 136 11 SERIAL INPUT OUTPUT TRANSCEIVER SIO u ccsssssssssssssssesscossecessesscassecssseeucassecssaceucnssecseaceees 139 POV S LEY OAE 139 TL2 SIO OPERA TION 139 11 3 SIOM MODE REGISTER 142 TLASIOB DATA BUFFER rcp 143 11 5 SIOR REGISTER DESCRIPTION ade ase 144 12 MAIN SERIAL PORT MSP 145 XE PIU SIDA 145 145 12 3 MSPMODE REGISTER 146 125 MSP MODE REGISTER 2 147 12 5 MSP REGISTER 148 12 6 MSP MSPADR REGISTER 148 125 F GAVE MODE OPERATION
5. timer is 8 bit binary up timer with basic timer event counter PWM functions The basic timer function supports flag indicator TCOIRQ bit and interrupt operation interrupt vector The interval time is programmable through TCOM TCOC TCOR registers The event counter is changing TCO clock source from system clock to external clock like signal e g continuous pulse R C type oscillating signal TCO becomes a counter to count external clock number to implement measure application TCO also builds in duty cycle programmable PWM The PWM cycle and resolution are controlled by TCO timer clock rate TCOR and TCOD registers so the PWM with good flexibility to implement IR carry signal motor control and brightness adjuster The main purposes of the TCO timer are as following 8 8 programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency interrupt function TCO timer function supports interrupt function When TCO timer occurs overflow the TCOIRQ actives and the system points program counter to interrupt vector to do interrupt sequence A Event Counter The event counter function counts the external clock counts A Duty cycle programmable PWM The PWM is duty cycle programmable controlled by TCOR and TCOD registers Green mode function All TCO functions timer PWM event counter auto reload keep running in green mode an
6. 0C6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4CON7 PACONG 5 PACONA P4CON3 P4CON2 P4CON1 P4CONO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 4 7 01 P4 n configuration control bits 0 P4 n can be a digital I O pin 1 P4 n will be set as input mode and disable pull up resistor 0C7H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5CON P5CONS3 P5CON2 P5CON1 P5CONO Read Write R W R W RAN R W After reset 0 0 0 0 Bit 3 0 5 3 01 P5 n configuration control bits 0 P5 n can be a digital I O pin 1 P5 n will be set as input mode and disable pull up resistor 5 TECHNOLOGY CO LTD Page 126 Version 1 4 N 7 SONIX 9 4 4 ADC OPERATION EXAMLPE ADC CONFIGURATION Reset ADC CLR ADM Set ADC clock rate and ADC resolution MOV A 0nmn0000b BOMOV ADR A Set ADC input channel configuration MOV A value1 BOMOV A value2 PAM A value3 Enable ADC BOBSET FADENB Execute ADC 100us warm up time delay loop CALL 100usDLY Select ADC input channel MOV A value OR ADM A Enable ADC input channel BOBSET FGCHS Enable ADC interrupt function BOBCLR FADCIRQ BOBSET FADCIEN Start to execute ADC converting BOBSET FADS SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP
7. Cad Cad TCOIRQ TCO timer overflows TCOIRQ set as 1 a Reload TCOC from TCOR automatically TCOIRQ is cleared by program 8 3 8 PULSE WIDTH MODULATION PWM PWM is duty cycle programmable design to offer various PWM signals When TCO timer enables and PWMOOUT bit sets as 1 enable PWM output the PWM output pin P5 1 outputs PWM signal One cycle of PWM signal is high pulse first and then low pulse outputs TCOR register controls the cycle of PWM and TCOD decides the duty high pulse width length of PWM TCOC initial value is TCOR reloaded when TCO timer enables and TCO timer overflows When TCOC count is equal to TCOD the PWM high pulse finishes and exchanges to low level When TCO overflows counts from OxFF to 0x00 one complete PWM cycle finishes The PWM exchanges to high level for next cycle The PWM is auto reload design to load TCOC from TCOR automatically when TCO overflows and the end of PWM s cycle to keeps PWM continuity If modify the PWM cycle by program as PWM outputting the new cycle occurs at next cycle when TCOC loaded from TCOR Enable TCO and PWM TCOC overflows from OxFF to 0x00 TCOC is loaded from TCOR TCOC TCOD TCOC is loaded from TCOR PWM outputs high status PWM exchanges to low status PWM exchanges to high status i PWM Output One complete cycle of PWM Next cycle The resolution of PWM is decided by TCOR TCOR range is from 0
8. 0 0 0 0 0 0 0 0 The equation of TCOR initial value is as following TCOR initial value 256 interrupt interval time clock rate gt Example To calculation TCOC and TCOR value to obtain 10ms TCO interval time TCO clock source is Fcpu 16 2 16 1MHz Select TCORATE 000 128 TCO interval time 10ms TCO clock rate 16MHz 16 128 TCOC TCOR initial value 256 TCO interval time input clock 256 10ms 16MHz 16 128 256 10 2 16 106 16 128 B2H 8 3 6 TCOD PWM DUTY REGISTER TCOD register s purpose is to decide PWM duty In PWM mode TCOR controls PWM s cycle and TCOD controls the duty of PWM The operation is base on timer counter value When TCOC TCOD the PWM high duty finished and exchange to low level It is easy to configure TCOD to choose the right PWM s duty for application 0B7H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOD TCOD7 TCOD6 TCOD5 TCOD4 TCOD3 TCOD2 TCOD1 TCODO Read Write R W R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 The equation of TCOD initial value is as following TCOD initial value TCOR PWM high pulse width period clock rate gt Example To calculate TCOD value to obtain 1 3 duty PWM signal The TCO clock source is 16 2 16 1MHz Select 000 128 TCOR B2H TCO inter
9. gp gq gt PWM1OUT 0 PWM1OUT 1 The pin exchanges to output PWM1OUT 0 The pin exchanges PWMTOUT 1 mode and outputs PWM signal automatically to last GPIO mode output low PWM Output gt lt gt 1 0 PWM1OUT 1 The pin exchanges to output PWM1OUT 0 The pin exchanges PWMTOUT 1 mode and outputs PWM signal automatically to last GPIO mode output high PWM Output High impendence floating 7 Ce yO PWM1OUT 0 PWM1OUT 1 pin exchanges to output PWM1OUT 0 pin exchanges PWMTOUT 1 mode and outputs PWM signal automatically last GPIO mode input 8 4 9 TC1 TIMER OPERATION EXPLAME TC1 TIMER CONFIGURATION Reset TC1 timer CLR TC1M Clear TC1M register Set TC1 clock source and TC1 rate MOV A 0nnn0n00b BOMOV TC1M A Set TC1C and TCHR register for TC1 Interval time MOV A value IC1C must be equal to TC1R BOMOV TC1C A BOMOV Clear TC1IRQ BOBCLR FTC1IRQ Enable TC1 timer and interrupt function BOBSET FTC1IEN Enable TC1 interrupt function BOBSET FTC1ENB Enable TC1 timer 5 TECHNOLOGY CO LTD Page 104 Version 1 4 SONIN N D E A e TC1 EVENT COUNTER CONFIGURATION Reset TC1 timer CLR TC1M Enable TC1 event counter BOBSET FTC1CKS1 Set TC1C and TCHR register for TC1 Interval time MOV A value BOMOV TC1C A BOMOV Clear TC1IRQ BOBCLR FTC1IRQ E
10. Vdd 0 5V PO P1 P4 P5 pins Vss 0 5V XIN XOUT pins Vss 0 5V PO P1 P4 P5 pins INTO interrupt request pulse width port pull up resistor loH1 output source current loH2 1011 output sink current loL2 INTn trigger pulse width Tinto 3 2 O A I N cycle mA 16 2 4MHz Run Mode 4MHz No loading 1MHz 32 2 4 32 2 4 lt lt lt lt Slow Mode 1442 Internal low RC Stop high clock Vdd 3V ldd3 Mode Vdd 5V Supply Current Disable ADC uA lt lt AES lt lt I E P 2 e P i o o 2 I J N lt lt 2 E lt ajajaja lt lt 15 Ofle 215 gt lt 5 Green Mode No loading Watchdog Disable I 5 N A I N 5 lt Q lt 2 e L D A I N Internal Hihg RC C Vdd 2 4V 5 5V 15 68 16 32 Internal High Oscillator Freq Fihrc IHRC 40 85 Ndd 2 AV 5 5V 154 Vdeto voltage reset level 25 C 1 7 Low voltage reset level 40 C 85 C 1 6 LVD Voltage Low voltage reset indicator level 25 C 2 3 Low voltage reset indicator level 40 C 85 C 2 2 Vdeip Low voltage reset indicator level 25 C 3 2
11. 8 L2SXYSTEMBEOUNR DIAGRAM e 10 1 3 PINASSIGNMEN 11 1 4 PIN DESCRIPTIONS 13 15 PIN CIRCUIT DIAGRAMS 14 2 CENTRAL PROCESSOR UNIT CPU 16 2 1 PROGRAM MEMORY FLASH 16 VECTOR 0000H Ride Rd up pA Orb al Qo ONG Qd i vp E RA 17 2 1 2 INTERRUPT VECTOR 0008 00148 18 21 3 LOOK UP TABLE DESCRIPTION 20 2121 JUMP TABLE DESCRIPTION 22 2 1 5 CHECKSUM CALCULATION 24 2 DATA MEMORY 25 2 2 SYSTEM REGISTER T 26 2 2 1 1 SYSTEM REGISTER TABLE 26 2 2 1 2 SYSTEM REGISTER DESCRIPTION 26 2 2 1 3 BIT DEFINITION of SYSTEM 27 PAL ACCUMULATOR aa a a 29 22 3 FLAG 30 2 2 4 PROGRAM COUNTER 31 22 9 H 34 2 2 60 X REGISTERS TT 29 221 Y ZREGISTERS T
12. X Note The PUSH and POP operations aren t through instruction PUSH POP and can executed save and load and working registers 0 80 0 8 by hardware automatically ROM Priority 0008H WAKE Interrupt vector 1 0009H INTO Interrupt vector 2 000AH INT1 Interrupt vector 3 000 1 4 000 TCO Interrupt vector 5 6 7 8 9 000DH TC1 Interrupt vector 000EH TC2 Interrupt vector 000FH T1 Interrupt vector 0010H ADC Interrupt vector 0011H 510 Interrupt vector 10 0012H MSP Interrupt vector 11 0013H UART RX Interrupt vector 12 0014H UART TX Interrupt vector 13 When one interrupt request occurs and the program counter points to the correlative vector to execute interrupt service routine If WAKE interrupt occurs the program counter points to ORG 8 If INTO interrupt occurs the program counter points to ORG 9 In normal condition several interrupt requests happen at the same time So the priority of interrupt sources is very important or the system doesn t know which interrupt is processed first The interrupt priority is follow vector sequence ORG 8 is priority 1 ORG 9 is priority 2 In the case the interrupt processing priority is as following If WAKE TO TC2 T1 and SIO interrupt requests happen at the same time the system processing interrupt sequence is WAKE TO TC2 T1 and then SIO The system processes WAKE in
13. OBBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1D TC1D7 TC1D6 TC1D5 TC1D4 TC1D3 TC1D2 TC1D1 TC1D0 Read Write RAN R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 The equation of TC1D initial value is as following initial value TC1R PWM high pulse width period TC1 clock rate gt Example To calculate TC1D value to obtain 1 3 duty PWM signal The TC1 clock source is 16MHz 16 1MHz Select TC1RATE 000 Fcpu 128 TC1R B2H TC1 interval time 10ms So the PWM cycle is 100Hz In 1 3 duty condition the high pulse width is about 3 33ms TC1D initial value B2H PWM high pulse width period TC1 clock rate B2H 3 33 16MHz 16 128 B2H 5 TECHNOLOGY CO LTD Page 102 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 4 7 TC1 EVENT COUNTER TC1 event counter is set the TC1 clock source from external input pin 1 When TC1CKS1 1 TC1 clock source is switch to external input pin 1 TC1 event counter trigger direction is falling edge When one falling edge occurs TC1C will up one count When TC1C counts from OxFF to 0x00 TC1 triggers overflow event The external event counter input pin s wake up function of GPIO mode is disabled when TC1 event counter function enabled to avoid event counter signal trigger system wake up and not keep in power s
14. 116 8 6 5 2 High Pulse Width 117 8 6 5 3 Low Pulse Width Measurement 117 8 6 5 4 Input Cycle 118 5 TECHNOLOGY CO LTD Page 5 Version 1 4 N N M SN8F27E60 Series 5 S a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 6 6 CAPTURE TIMER CONTROL REGISTERS 118 8 6 7 TIMER OPERATION 119 9 12 CHANNEL ANALOG TO DIGITAL CONVERTER ADC ccsssssssssssssssssecscessecsssecscasseessasencncees 122 9 1 OVERVIEW mE 122 9 2 ADC REGISTER pene pe DIEN RP toU En RENSAR 123 9 3 ADC DATA BUFFER REGISTERS 124 9 4 ADC OPERATION DESCRIPTION AND 125 9 4 1 SIGNAL 125 9 422 ADCCONVERDINCO TIME 125 94 3 PIN CONFIGURATION 126 9442 ADC OPERATION EXAMLPE 127 9 5 ADC APPLICATION CIRCUIT 129 10 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER 4 0 4 4 24 4 1 130 TY TEE 130 10 2 UARTOPERA TION 131 10 3 UART BAUD 132
15. us ADC current consumption ER 48 HEY L Bee 80 K sec lt lt 3 4 4 7 1 1 Differential Nonlinearity DNL VDD 5 0V AVREFH 3 2V 7 8 Integral Nonlinearity INL VDD 5 0V AVREFH 3 2V Fapsue 7 8 No Missing Code VDD 5 0V AVREFH 3 2V 7 8 Non trimmed gt offset Voltage Trimmed 2 These parameters for design reference not tested 4 1 1 64 i 6 ADC Sampling Rate F VDD 5 0V Set FADS 1 Frequency 3 0 11 o 9 10 5 TECHNOLOGY CO LTD Page 168 Version 1 4 N N 9 SN8F27E60 Series FLASH MEMORY CHARACTERISTIC All of voltages refer to Vss Vdd 5 0V Fosc 4MHz Fcpu 1MHz ambient temperature is 25 C unless otherwise note Erase Program 25 Vdd Endurance time Erase Program 10 85 20K Cycle Erase Program 40 10 20K 70 Cycle Pageerasecurent Vddi 25V 25 5 mA Program current lpg Vddi 25V 1 1 1 1 1 35 7 mA erase time Ter Vdd 25V t page i26 word 1 30 ms Program time Tpgi 2 5 ISP setup 1 380 us Tpg2 Vdd 2 5V 1 word program d d 30 us These parameters are for design reference not tested
16. TC1M A Set TC1 clock 64 MOV A 74H Set TC1C initial value 74H BOMOV TC1C A Set TC1 interval 10 ms BOBSET FTC1IEN Enable TC1 interrupt service BOBCLR FTC1IRQ Clear TC1 interrupt request flag BOBSET FTC1ENB Enable TC1 timer BOBSET FGIE Enable GIE Example TC1 interrupt service routine ORG Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTC1IRQ Check TC1IRQ JMP EXIT_INT TC1IRQ 0 exit interrupt vector BOBCLR FTC1IRQ Reset TC1IRQ MOV A 74H BOMOV TC1C A Reset TC1C 522 TC1 interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 72 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 6 10 TC2 INTERRUPT OPERATION When the TC2C counter overflows the TC2IRQ will be set to 1 no matter the TC2IEN is enable or disable If the TC2IEN and the trigger event TC2IRQ is set to be 1 As the result the system will execute the interrupt vector If the TC2IEN 0 the trigger event TC2IRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the TC2IEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example TC2 interrupt request setup BOBCLR FTC2IEN Disable TC2 interrupt servi
17. Use data pointer HL reads a data from RAM location 012H into ACC Example Indirectly addressing mode with YZ register BOMOV Y 0 To clear Y register to access RAM bank 0 BOMOV Z 12H To set an immediate data 12H into Z register BOMOV A 2 Use data pointer YZ reads a data from RAM location 012H into ACC 5 TECHNOLOGY CO LTD Page 38 Version 1 4 N 5 7 SN8F27E60 Series S 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 4 STACK OPERATION 2 4 1 OVERVIEW The stack buffer has 8 level These buffers are designed to push and pop up program counters PC data when interrupt service routine and CALL instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counter PC data CALL RETI INTERRUPT STACK Buffer STACK Buffer STACK Level High Byte Low Byte STKP 1 STKP 1 2 4 2 The stack pointer STKP is 3 bit register to store the address used to access the stack buffer 13 01 data memory STKnH and STKnL set aside for temporary storage of stack addresses The two stack operations are writing to the top of the stack push and reading from the top of stack pop Push operation decrements the STKP and the pop operation increments each time That makes the STKP always point to the top address of stack
18. 5 TECHNOLOGY CO LTD Page 187 Version 1 4 BN V SN8F27E60 Series a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 19 7 SSOP 28 PIN 0 07 0 40 0 31 0 21 0 0259BSC 0 04 4 5 TECHNOLOGY CO LTD Page 188 Version 1 4 SONI IX 19 8 QFN 4X4 28 PIN SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP NOTES ALL DIMENSIONS ARE IN MILLIMETERS DIMENSION b APPUES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN O 15mm AND 6 30mm FROM THE TERMINAL TIP IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS ro 0 030 0 001 0 008 0 008 0 16 BSC 0 16 BSC 0 016 5 0 016 2 2 PAD SIZE 115x115 2 50 2 60 2 65 2 50 2 60 2 65 5 TECHNOLOGY CO LTD Page 189 Version 1 4 SN8F27E60 Series 19 9 P DIP 20 PIN LM 26 SEATING PLANE A1 5 5 TECHNOLOGY CO LTD Page 190 Version 1 4 7 SN8F27E60 Series S 8 Bit Flash Micro Controller with Embedded ICE and ISP
19. 2 9 PC8 PCH 09H CPUM CPUMO 5 096H 2 097 0988H PA MSPIRQ UTXIRQ URXIRQ SIOIRO WAKEIRQ 09 o9BH UTXIEN URXIEN SIOIEN WAKEIEN R W oocH T J J 2 09DH 09 OFH 3 4J l d 1 POOGO Poem PO4M PO2M Poom RW OA4H PS3M Psom RW OH POM 2 Pot Poo 0A7H P82 5 OACH POGUR PO4UR POSUR 2 POOUR Rw OH 520 500 082 TOENB TOrat2 TOrate TOraeO 0B3H TCOENB TCOrate2 TCOrated TCOCKS1 TCOCKSO PWMOOUT Rw 0 5 0B7H OB8H TCtrate2 TCirate1 0 TC1CKS1 TC1CKSO PWMtOUT 0 OBCH TC2ENB TC2rate2 TC2rate TC2rate0 TC2CKS1 TC2CKSO PWM2OUT OBDH OCOH 2 Ttrateo Ticks J 0 0 2 CPTEN CPTMD CPTStart RW 0C4H 0C5H 0C6H
20. 32 Pin e SN8F27E65U AC field SDIP 32 Pin e SN8F27E65LU DC field SDIP 32 Pin VSS 1 U 32 VDDL VSS 1 U 32 VDD XIN P0 6 2 31 VDDL XIN PO 6 2 31 VDD XOUT PO 5 3 30 VDD 5 3 30 VDD 5 4 4 29 4 4 29 PO 3 UTX T1 5 28 P4 0 AINO PO S UTX T1 5 28 P4 0 AINO 2 2 6 27 P4 1 AIN1 P0 2 URX TC2 6 27 P4 1 AIN1 PO 1 INT1 TC1 7 26 P4 2 AIN2 PO 1 INT1 TC1 7 26 P4 2 AIN2 8 25 P4 3 AIN3 8 25 P4 3 AIN3 1 7 5 5 9 24 P4 4 AIN4 1 7 5 5 9 24 P4 4 AIN4 P1 6 SCK 10 23 5 1 5 1 6 5 10 23 P4 5 AIN5 P1 5 SDI 11 22 P4 6 AIN6 P1 5 SDI 11 22 P4 6 AIN6 P1 4 SDO 12 21 P4 7 AIN7 P1 4 SDO 12 21 P4 7 AIN7 P1 3 SCL 13 20 P5 0 AIN8 P1 3 SCL 13 20 P5 0 AIN8 P1 2 SDA 14 19 P5 1 AIN9 PWMO P1 2 SDA 14 19 P5 1 AIN9 PWMO P1 1 EIDA 15 18 P5 2 AIN10 PWM1 P1 1 EIDA 15 18 P5 2 AIN10 PWM1 P1 0 EICK 16 17 P5 3 AIN11 PWM2 P1 0 EICK 16 17 P5 3 AIN11 PWM2 e SN8F27E65F AC field LQFP 32 Pin e SN8F27E65LF DC field LQFP 32 Pin e SN8F27E65J AC field QFN 5x5 32 Pin e SN8F27E65LJ DC field QFN 5x5 32 Pin 0 pt SES 6 5 D gt Q a gt 5000 a a a tc gt gt x X gt gt gt gt lt ao x x gt gt gt gt lt PO S UTX T1 0 2 9 2 P0 1
21. dea a a 148 12 1 1 DRE E i enei 148 IMS pe SLAVE 149 12 73 Slave Trans MISSO DT 149 12 74 General Call Address 150 151 12 6 MASTER MODE occ EM 153 12 8 1 Mater Mod SS Up i 153 6 2 MSP Rate Cre CANOE MNT ET 153 12 8 3 MSP Mater START petente ta Re trio pisei eae es ko E E 154 12 MM WCOL Status Flag eT 154 12 8 4 MSP Master mode Repeat START 154 12 8 41 WOOL Stat s M 154 12 8 5 Acknowledge Sequence Timing 155 126 1 WOOL 51108 NU m E E 155 12 8 6 STOP Condition PL 155 5 TECHNOLOGY CO LTD Page 6 Version 1 4 N N M SN8F27E60 Series 5 S 8 Flash Micro Controller with Embedded ICE and ISP IA S NB BRI P CU OE 155 12 8 7 Clock Arbitration 156 12 8 8 Master Mode 156 12 8 5 BE Status PIRE ioci 156 pr MA WCOL Flag M 156 1 553 ACKSTAT Status Flag 156 12 8 9 Master Mode R O E ee 157 12 8 9 1 BE Sta
22. Clear TCOM register Set TCO clock source from external input pin P0 0 TCOC must be equal to TCOR Enable TCO interrupt function Enable TCO timer Clear TCOM register TCOC must be equal to TCOR TCOD must be greater than TCOR Enable TCO timer Enable PWM Page 98 Version 1 4 N 7 SN8F27E60 Seri 6 x 8 Bit Flash Micro Controller with Embedded ICE 8 4 TC1 8 BIT TIMER COUNTER 8 4 1 OVERVIEW The TC1 timer is an 8 bit binary up timer with basic timer event counter and PWM functions The basic timer function supports flag indicator TC1IRQ bit and interrupt operation interrupt vector The interval time is programmable through TC1M TC1C registers The event counter is changing TC1 clock source from system clock Fcpu Fhosc to external clock like signal e g continuous pulse R C type oscillating signal TC1 becomes a counter to count external clock number to implement measure application TC1 also builds in duty cycle programmable PWM The PWM cycle and resolution are controlled by TC1 timer clock rate TC1R and TC1D registers so the PWM with good flexibility to implement IR carry signal motor control and brightness adjuster The main purposes of the TC1 timer are as following A 8 bit programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency Interrupt function TC1 timer function supports interrupt
23. Enable PWM Page 112 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 8 6 T1 16 BIT TIMER WITH CAPTURE TIMER FUNCTION 8 6 1 OVERVIEW The T1 timer is a 16 bit binary up timer with basic timer and capture timer functions The basic timer function supports flag indicator T1IRQ bit and interrupt operation interrupt vector The interval time is programmable through T1M T1CH T1CL 16 bit counter registers The capture timer supports high pulse width measurement low pulse width measurement cycle measurement and continuous duration from P0 3 T1 becomes a timer meter to count external signal time parameters to implement measure application The main purposes of the T1 timer are as following 16 bit programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency 16 bit measurement Measure the input signal pulse width and cycle depend on the T1 clock time base to decide the capture timer s resolution The capture timer builds in programmable trigger edge selection to decide the start stop trigger event 16 bit capture timer The 16 bit event counter to detect event source for accumulative capture timer function The event counter is up counting design Interrupt function T1 timer function and capture timer function support interrupt function When T1 timer occurs overflow or capture timer stops counting the T1IRQ actives and the
24. IHRC RTC Running Ext OSC Disable IHRC IHRC RTC By STPHX Ext OSC Disable IHRC IHRC RTC By STPHX Ext OSC Disable Stop ILRC Running Running Running Stop Ext Osc IHRC Disable IHRC RTC Ext OSC Running IHRC Disable Running Ext OSC 5 IHRC STPHX Running Ext OSC STPHX Stop CPU instruction Executing Executing Stop Stop TO timer Active By TOENB Active By TOENB Active By TOENB Inactive TCO timer Timer Event counter PWM Active By TCOENB Active By TCOENB Active By TCOENB Inactive TC1 timer Timer Event counter PWM Active By TC1ENB Active By TC1ENB Active By TC1ENB Inactive TC2 timer Timer Event counter PWM Active By TC2bENB Active By TC2bENB Active By TC2bENB Inactive T1 timer Timer Event counter Active By T1ENB Active By T1ENB Active By T1ENB Inactive SIO Active as enable Inactive Inactive Inactive MSP Active as enable Inactive Inactive Inactive UART Active as enable Inactive Inactive Inactive ADC Active as enable Active as enable Active as enable Inactive Watchdog timer By Watch Dog Code option By Watch Dog Code option By Watch Dog Code option By Watch Dog Code option Internal interrupt All ac
25. Note Don t execute ISP flash ROM program operation for the first page and the last page or affect program operation 5 TECHNOLOGY CO LTD Page 162 Version 1 4 NONA 13 4 ISP PROGRAM ERASE CONTROL REGISTER SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP ODBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PECMD PECMD7 PECMD6 PECMD5 4 PECMD2 PECMD1 PECMDO Read Write After reset 1 Bit 7 0 0x5A Page Program 32 words page 0 Page Erase 128 words page Others Reserved PECMD 7 0 ISP operation control register Note Before executing ISP program and erase operations clear PECMD register is necessary After ISP configuration set ISP operation code in MOV and BOMOV M A instructions to start ISP operations 13 5 ISP ROM ADDRESS REGISTER ISP ROM address length is 16 bit and separated into PEROML and PEROMH registers Before ISP execution set the head address of ISP ROM by program ODCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEROML PEROML7 PEROML6 PEROML5 PEROML4 PEROML3 PEROML2 PEROML1 PEROMLO Read Writ
26. if occur carry then 1 else C 0 M A M if occur carry then C 1 C 0 lt A M if occur carry then C 1 C 0 M bank 0 lt M bank 0 A if occur carry then C 1 0 amp A if occur carry then C 1 else 0 1 if occur borrow then C 0 else C 1 1 N lt if occur borrow then C 0 else 1 SUB M lt A M if occur borrow then C 0 else C 1 SUB 1 if occur borrow then C 0 else C 1 DAA To adjust ACC s data format from HEX to DEC MUL R A M The LB of product stored in Acc and HB stored R register ZF affected by Acc AND A lt A and M AND M lt A and AND Al lt M A AorM M 1 242254 lt Aorl XOR A lt A xor M M c A xor M XOR 1 M lt 1 complement COMM 158 03 00 67 64 07 04 53 00 03 00 07 04 lt M b7 b4 63 60 lt RRC M M lt RRC M A RLC M M Meo Mb lt 0 c 1 M bank 0 b lt 0 M bank 0 b lt 1 2 then skip next instruction 2 IfA M then skip next instruction A lt M 1 0 then skip next instruction M M 1 If M then skip next instruction lt M 1 lt 1 lt 1 0 then skip next instruction lt M 1 0 then skip next instr
27. n Viv rm M Write address and R W to MSPBUF held low T 11 Start transmit while master response MSPIRQ 1131 SCL Ip routine of MSP interrupt S Oleared by Software Cleared by Software A cleared by Software service Write MSPBUF Write MSPBUF SEN LL SEN cleared by hardware PEN after START condition RW 34 MSP Master Transmission Mode Timing Diagram 5 TECHNOLOGY CO LTD Page 156 Version 1 4 N N 7 SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 8 9 Master Mode Receiving Master receiving mode is enable by set RCEN bit The start counting and when SCL change state from low to high the data is shifted into MSPSR After the falling edge of eighth clock the receive enable bit is clear automatically the contents of MSP are load into MSPBUF the BF flag is set the MSPIRQ flag is set and MRG counter is suspended fro counting holding SCL low The MSP is now in IDLE mode and awaiting the next operation command When the MSPBUF data is read by Software the BF flag is cleat automatically By setting ACKEN bit user can send an acknowledge bit at the end of receiving 12 8 9 1BF Status Flag In Reception mode the BF bit is set when an address or da
28. 100 833 TCIM MODE REGISTER 101 8 4 4 1 COUNTING REGISTER sipres a ELO MEME 101 8 4 5 TCIR AUTO RELOAD REGISTER 102 4 6 TCID PWM DUTY REGISTER ee 102 Ba ICLBVENTEDUNTER 103 8 4 8 PULSE WIDTH MODULATION PWM vssscsscvsascnidesnsonsivess otendsssaieusijusnhddspsdsunwersonssessbeinanlesnivedien 103 8 4 9 TCI TIMER OPERATION 104 8 2102 TIMER COUNTER 106 8 5 LOVERVIEW 106 8 5 2 TC2 TIMER OPERATION 107 8 3 3 TCM MODE REGISTER 108 TC2C COUNTING REGISTER 108 8 5 5 TC2ZRAUTO RELOAD REGISTER 109 8 5 6 TC2D PWM DUTY REGISTER 109 857 TC2 EVENT COUNTER 110 8 5 8 PULSE WIDTH 55 REA MEER 110 8 5 9 TC2 TIMER OPERATION EXPEAMIE 111 8 6 16 TIMER WITH CAPTURE TIMER FUNCTION 113 8 6 KOVER VIEW mbi M E d MM 113 8 6 2 ITTIMBR OPERA TIM js a dct ptr el b Fon HERE Eu Cose 113 8 6 3 TIM MODE REGISTER 114 8 6 4 TICH 16 bit COUNTING REGISTERS esee enn 115 8 6 5 TI CPATURE 116 9 0 51 Capture
29. 5 TECHNOLOGY CO LTD Page 114 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 6 4 T1CH T1CL 16 bit COUNTING REGISTERS T1 counter is 16 bit counter combined with T1CH and registers When T1 timer overflow occurs the T1IRQ flag is set as 1 and cleared by program The T1CH T1CL decide T1 interval time through below equation to calculate a correct value It is necessary to write the correct value to T1CH and T1CL registers and then enable T1 timer to make sure the fist cycle correct After one T1 overflow occurs the T1CH and T1CL registers are loaded correct values by program Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1CL T1CL7 T1CL6 T1CL5 T1CL4 T1CL2 T1CL1 T1CLO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0C2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1CH T1CH7 T1CH6 T1CH5 T1CH4 T1CH3 T1CH2 T1CH1 T1CHO Read Write RAN R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 The T1 timer counter length is 16 bit and points to and registers The timer counter is double buffer design The core bus is 8 bit so access 16 bit data needs a latch flag to avoid the transient status affect the 16 bit data mistake occurrence Under write mode the write T1CH is the latch control flag Under read mode the read T1CL is th
30. 7 1 loH2 Vdd 0 5V PO PIPA PBpins 4 loLi Vss 0 59 XINXOUTpins 4 VO output sink current Vss 0 5V 7 INTnirggerpulse width Tinto INTO interrupt request pulse width 2 fcpu Fun Mode m No loading m Slow Mod Stop high clock o s 221 2 0 2 0 2 0 EE BEES Green Mode 2 2 loading Vdd Ext 32KHz X tal Watchdog Disable Vdd ILRC 16KHz hro Internal Hihg RC 40 C 85 C Vdd 2 4V 5 5V Low voltage reset level 25 Low voltage reset level 40 85 LVD Voltage Low voltage reset indicator level 25 C V Low voltage reset indicator level 40 C 85 C Low voltage reset indicator level 25 C Low voltage reset indicator level 40 85 These parameters are for design reference not tested ADC CHARACTERISTIC All of voltages refer to Vss Vdd 5 0V Fosc 4MHz Fcpu 1MHz ambient temperature is 25 C unless otherwise note PARAMETER SYM MAX UNIT AINO AIN11 input voltage Vani 5 0 V ADC reference Voltage Vref ADCenabletime Ready to start convert after set ADENB 1 100
31. Clear TCOM register nn ADCKS 1 0 for ADC clock rate m ADLEN for ADC reolution Set PACON for ADC input channel Set ADC input channel as input mode Disable ADC input channel s internal pull up resistor 100us delay loop Set ADCHSJ3 0 for ADC input channel selection Clear ADC interrupt flag Enable ADC interrupt function Note 1 When ADENB is enabled the system must be delay 100us to be the ADC warm up time by program and then set ADS to do ADC converting The 100us delay time is necessary after ADENB setting not ADS setting or the ADC converting result would be error Normally the ADENB is set one time when the system under normal run condition and do the delay time only one time 2 power saving situation like power down mode and green mode not using ADC function to disable ADC by program is necessary to reduce power consumption 5 TECHNOLOGY CO LTD Page 127 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP ADC CONVERTING OPERATION ADC Interrupt disable mode 51 Check ADC processing flag JMP B 0 ADC is processing BOMOV A ADB 1 End of ADC processing Process ADC result BOMOV BUF1 A MOV A 000000116 AND A ADR BOMOV BUF2 A i End of processing ADC result CLR FEOC Clear ADC processing flag for next ADC converting ADC I
32. Input Signal 000 N 0 0000 Initialization Initialization T1 is counting T1 16 bit Counter T1CH T1CL Un know Data 0x n is the cycle of input signal 1 1 Read it by program through CPTStart 1 Rising Edge Rising Edge registers T1 starts to count T1 stops counting CPTStart 0 The cycle measurement is using rising edge to start and stop T1 timer If set CPTStart bit at high or low pulse duration the capture timer will measure next cycle until the rising edge occurrence When the end of measuring cycle and T1 timer stops the T1IRQ sets as 1 the T1 interrupt executes as 11 1 T1CH 16 bit counter stores the period of input cycle 8 6 6 CAPTURE TIMER CONTROL REGISTERS C3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTStart CPTG1 CPTGO Read Write R W R W R W R W R W After Reset 0 0 0 0 0 Bit 7 CPTEN Capture timer function control bit 0 Disable 1 Enable T1EN must be enabled Bit 3 CPTMD Capture timer mode control bit 0 CPT overflow mode 1 T1 overflow mode Bit 2 CPTStart Capture timer counter control bit 0 Process end 1 Start to count and processing Bit 1 0 CPTG 1 0 Capture timer function control bit 00 Capture timer function 01 High pulse width measurement 10 Low pulse width measurement 11 Cycle measurement 5 TECHNOLOG
33. Low The transfer first bit LSB 110 1 data transfer edge Falling Cone Joa e me m SCK idle status High The transfer first bit LSB 111 SCK data transfer edge Rising Core Cone ome Ker nm 5 idle status Low 11010 The transfer first bit LSB SCK data t fer edge Risi Cum Cons Cms Je logo SCK idle status High 1 1 0 The transfer first bit LSB se re Cone Cer Went ms SCK data transfer edge Falling edge 5 TECHNOLOGY CO LTD SIO Data Transfer Timing Page 140 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP The SIO supports interrupt function SIOIEN is SIO interrupt function control bit SIOIEN 0 disable SIO interrupt function SIOIEN 1 enable SIO interrupt function When SIO interrupt function enable the program counter points to interrupt vector ORG 0011H to do SIO interrupt service routine after SIO operating SIOIRQ is SIO interrupt request flag and also to be the SIO operating status indicator when SIOIEN 0 but cleared by program When SIO operation finished the SIOIRQ would be set to 1 and the operation is the inverse status of SIO START control bit The SIOIRQ and SIO START bit indicating the end status of SIO operation is after
34. value2 Set UART baud rate 8 bit buffer BOMOV URCR A Enable UART TX pin BOBSET FUTXEN Enable UART TX function and UART TX pin Enable UART TX interrupt function BOBCLR FUTXIRQ Clear UART TX interrupt flag BOBSET FUTXIEN Enable UART TX interrupt function Load TX data buffer and execute TX transmitter MOV A value3 Load 8 bit data to UTXD data buffer BOMOV UTXD A After loading UTXD UART TX starts to transmit NOP One instruction delay for UTXBZ flag Check TX operation BOBTSO FUTXBZ Check UTXBZ bit JMP CHKTX UTXBZ 1 TX is operating JMP ENDTX UTXBZ 0 the end of TX Note UART TX operation is started through loading UTXD data buffer 5 TECHNOLOGY CO LTD Page 136 Version 1 4 NONA e Transmit Break Pocket Select parity bit function SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP BOBCLR FUTXPEN Disable UART TX parity bit function BOBSET FUTXPEN Enable UART TX parity bit function Select parity bit format BOBCLR FUTXPS UART TX parity bit format is even parity BOBSET FUTXPS UART TX parity bit format is odd parity Set UART baud rate MOV A value1 Set UART pre scaler URS 2 0 BOMOV URRX A MOV A value2 Set UART baud rate 8 bit buffer BOMOV URCR A Enable UART TX pin BOBSET FUTXEN Enable UART TX function and UART TX pin Enable UART TX interrupt function BOBCLR FUTXIRQ
35. 2 bit When 2 0 TC2 timer stops When TC2ENB 1 TC2 timer starts to count Before enabling TC2 timer setup TC2 timer s configurations to select timer function modes e g basic timer interrupt function TC2C increases 1 by timer clock source When TC2 overflow event occurs TC2IRQ flag is set as 1 to indicate overflow and cleared by program The overflow condition is TC2C count from full scale OxFF to zero scale 0x00 In difference function modes TC2C value relates to operation If TC2C value changing effects operation the transition of operations would make timer function error So TC2 builds in double buffer to avoid these situations happen The double buffer concept is to flash TC2C during TC2 counting to set the new value to TC2R reload buffer and the new value will be loaded from TC2R to TC2C after TC2 overflow occurrence automatically In the next cycle the TC2 timer runs under new conditions and no any transitions occur The auto reload function is no any control interface and always actives as TC2 enables If TC2 timer interrupt function is enabled 21 1 the system will execute interrupt procedure The interrupt procedure is system program counter points to interrupt vector ORG 000EH and executes interrupt service routine after TC2 overflow occurrence Clear TC21RQ by program is necessary in interrupt procedure TC2 timer can works in normal mode slow mode and green mode But in green mode TC2 keep coun
36. 3 0 CHS 3 0 ADC input channel select bit 0000 AINO 0001 AIN1 0010 0011 0100 AIN4 0101 AIN5 0110 AIN6 0111 1000 AIN8 1001 AIN9 1010 AIN10 1011 AIN11 1100 11112 Reserved ADR register includes ADC mode control and ADC low nibble data buffer ADC configurations including ADC clock rate and ADC resolution These configurations must be setup completely before starting ADC converting 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADR ADCKS1 ADLEN ADCKSO ADB1 ADBO Read Write R W R W R W R R After reset 0 0 0 Bit 6 4 ADCKS 1 0 ADC s clock rate select bit 00 16 01 8 10 Fcpu 1 11 2 Bit 5 ADLEN ADC s resolution select bits 0 8 bit 1 10 bit 5 TECHNOLOGY CO LTD Page 123 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 9 3 ADC DATA BUFFER REGISTERS ADC data buffer is 10 bit length to store ADC converter result The high byte is ADB register and the low nibble is ADR 1 0 bits The ADB register is only 8 bit register including bit2 bit9 ADC data To combine ADB register and the low nibble of ADR will get full 10 bit ADC data buffer The ADC data buffer is a read only register and the initial status is unknown after system reset gt ADB 9 2 In 8 bit ADC mode the ADC data is stored ADB
37. GPIO will change to Input mode automatically no matter what Enable chip selection function setting 0 SIO Function Disable GPIO GPIO I O mode are fully controlled by PnM when SIO function Disable 1 If SCKMD 1 for external clock the SIO is SLAVE mode If SCKMD 0 for internal clock the SIO is in MASTER mode 2 Don t set SENB and START bits in the same time That makes the SIO function error 3 SIO pin can be push pull structure and open drain structure controlled by register 4 SCS pin enabled condition is only SCKMD 1 and SCSEN 1 If SCKMDz0 SCSEN 1 SCS pin is still GPIO mode 11 4 SIOB DATA BUFFER OE2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOB SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOBO Read Write RAN R W RAN RAN R W RAN R W R W After reset 0 0 0 0 0 0 0 0 is the SIO data buffer register It stores serial I O transmit and receive data The system is single buffered in the transmit direction and double buffered in the receive direction This means that bytes to be transmitted cannot be written to the SIOB Data Register before the entire shift cycle is completed When receiving data however a received byte must be read from the SIOB Data Register before the next byte has been completely shifted in Otherwise the first byte is lost Following figure shows a typical SIO transfer between two micro controllers
38. If TCO timer interrupt function is enabled TCOIEN 1 the system will execute interrupt procedure The interrupt procedure is system program counter points to interrupt vector ORG 000CH and executes interrupt service routine after TCO overflow occurrence Clear TCOIRQ by program is necessary in interrupt procedure TCO timer can works in normal mode slow mode and green mode But in green mode TCO keep counting set TCOIRQ and outputs PWM but can t wake up system Clock Source 0 00 TCOIRQ timer overflows TCOIRQ set as 17 di Reload TCOC from TCOR automatically TCOIRQ is cleared by program TCO provides different clock sources to implement different applications and configurations TCO clock source includes Fcpu instruction cycle Fhosc high speed oscillator and external input pin P0 0 controlled by TCOCKS 1 0 bits TCOCKSO bit selects the clock source is from Fcpu or Fhosc If 50 0 TCO clock source is Fcpu through TCOrate 2 0 pre scalar to decide Fcpu 1 Fcpu 128 If 50 1 TCO clock source is Fhosc through TCOrate 2 0 pre scalar to decide 1 128 TCOCKS1 bit controls the clock source is external input pin or controlled by TCOCKSO bit If TCOCKS1 0 TCO clock source is selected by TCOCKSO bit If TCOCKS1 1 TCO clock source is external input pin that means to enable event counter function TCOrate 2 0 pre scalar is unless when TCOCKSO
39. LTD Y Z Working YZ and ROM addressing register PFLAG Special flag register WO0 W72 Working register POOC P10OC Open drain control register SIOM SIO mode control register SIOR SIO clock rate control register SIOB SIO data buffer SIOC SIO control register T1M T1 mode register URXD UART receive data buffer P4CON P5CON P4 P5 configuration register ADB ADC data buffer ADT ADC offset calibration register INTRQO 1 Interrupt request register WDTR Watchdog timer clear register Pn Port n data buffer OSCM Oscillator mode register TOM TO mode register TCnM TCn mode register TCnR TCn auto reload data buffer Capture timer control register MSPSTAT MSP status register MSPM1 MSP mode register1 MSPM2 MSP mode register2 PERAM ISP RAM mapping address PERAMCNT ISP RAM programming counter register YZ RAM YZ indirect addressing index pointer STKO STK7 Stack 0 stack 7 buffer Page 26 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 2 2 1 3 BIT DEFINITION of SYSTEM REGISTER Address Remarks 080H L 081H 082H RBIT7 6815 RBIT4 RBIT3 RBI RBTO 083H 084H 085H POR wor RST sko be z RW PFLAG 00H 088H 089H 08AH 08BH 08CH 08DH 090H 091H 093H 04H X 4
40. MSP goes into idle mode 12 8 5 1WCOL Status Flag If user write to MSPBUF when Acknowledge sequence processing then WCOL bit is set and the content of MSPBUF data is un changed the writer doesn t occur Acknowledge sequence start here S Write 1 Ee cleared automatically v Ture Ture gt SDA _ MSPIRQ SetMSPIRQat 7 121101 the end of receive My Sere n Set MSPIRQ at the end of Acknowledge sequence Acknowledge Sequence Timing Diagram 12 8 6 STOP Condition Timing At the end of received transmitted a STOP signal present on SDA pin by setting the STOP bit register PEN MSPM2 1 At the end of receive transmit SCL goes low on the failing edge of ninth clock Master will set SDA go low when set PEN bit When SDA is sampled low MSP rate generator is reloaded and start count down to 0 When MRG overflow SCL pin is pull high After one period SDA goes High When SDA is sampled high while SCL is high bit P is set PEN bit is clear after next one period and MSPIRQ is set 12 8 6 1WCOL Status Flag If user write to MSPBUF when a STOP condition is processing then WCOL bit is set and the content of MSPBUF data is un changed the writer doesn t occur Set PEN here r P bit is set Falling edge of ninth edge v pes SCL 4 Ture _ PEN is clear by hardware and MSPIRQ bit is set SDA Ture gt lt
41. Ture Ture gt goes high on next Tura SDA goes low before the rising edge of 501 to set up STOP signal STOP condition sequence Timing Diagram 5 TECHNOLOGY CO LTD Page 155 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 8 7 Clock Arbitration Clock arbitration occurs when the master during any receive transmit or Repeat START STOP condition that SCL pin allowed to float high When SCL pin is allowed float high the master rate generator MRG suspended from counting until the SCL pin is actually sampled high When SCL is sampled high the MRG is reloaded with the content of MSPADR 6 0 and start down counter This ensure that SCL high time will always be at least one MRG overflow time in the event that the clock is held low by an external device MRG overflow Releas SCL If SCL 1 Reload with MSPADR MRG Overflow and start count down to measure high time Interval Release SCL Slave device held the SCL low 1 SCL 1 r MRG Start counting clock high interval T SCL 1 1 ASCL smapleed once every Fcpu 4 Hold of MRG untial SCL Is sampled high SDA y lt Ture Tusc Clock Arbitration sequence Timing Diagram 12 8 8 Master Mode Transmission Transmission a data byte 7 bit address or the eight bit data is accomplished by simply write to MSPBUF registe
42. and 0x80 0x8F register from buffers End of interrupt service routine Save ACC and 0x80 0x8F register to buffers Load ACC and 0 80 0 8 register from buffers End of interrupt service routine End of program Note It is easy to understand the rules of SONIX program from demo programs given above These points are as following 1 address 0000 is a JMP instruction to make the program starts from the beginning 2 The address 0008H 0014H is interrupt vector 3 User s program is a loop routine for main purpose application 5 TECHNOLOGY CO LTD Page 19 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 1 3 LOOK UP TABLE DESCRIPTION In the ROM s data lookup function Y register is pointed to middle byte address bit 8 bit 15 and 2 register is pointed to low byte address bit O bit 7 of ROM After MOVC instruction executed the low byte data will be stored in ACC and high byte data stored in R register gt Example To look up the ROM data located TABLE1 BOMOV Y TABLE1 M __ To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data ACC 35H Increment the index address for next address INCMS Z 2 1 2 15 not overflow 5 2 overflow gt 00 gt Y Y 1 lookup da
43. when external reset enable by code option gt Example Read data from input port BOMOV A PO Read data from Port 0 BOMOV A P4 Read data from Port 4 BOMOV A P5 Read data from Port 5 gt Example Write data to output port MOV A Write data FFH to all Port BOMOV 4 5 gt Example Write one bit data to output port BOBSET 4 0 Set P4 0 and P5 3 to be 1 BOBSET P5 3 BOBCLR 4 0 Set 4 0 and P5 3 to be 0 BOBCLR P5 3 5 TECHNOLOGY CO LTD Page 82 Version 1 4 SN8F27E60 Series 8 Flash Micro Controller with Embedded ICE and ISP NONA 7 5 PORT 4 PORT 5 ADC SHARE PIN The Port 4 Port 5 are shared with ADC input function and no Schmitt trigger structure Only one pin of port 4 port 5 can be configured as ADC input in the same time by ADM register The other pins of port 4 port 5 are digital I O pins Connect an analog signal to COMS digital input pin especially the analog signal level is about 1 2 VDD will cause extra current leakage In the power down mode the above leakage current will be a big problem Unfortunately if users connect more than one analog input signal to port 4 or port 5 will encounter above current leakage situation PACON is Port4 Configuration register PSCON is Port5 Configuration register Write 1 into PACON n or will configure related port 4 or port 5 pin will be set as input mode and
44. 00 If TCOR 0x00 PWM s resolution is 1 256 If TCOR 0x80 PWM s resolution is 1 128 TCOD controls the high pulse width of PWM for PWM s duty When TCOC TCOD PWM output exchanges to low status TCOD must be greater than TCOR or the PWM signal keeps low status When PWM outputs TCOIRQ still actives as overflows and interrupt function actives as TCOIEN 1 But strongly recommend be careful to use PWM and TCO timer together and make sure both functions work well The PWM output pin is shared with GPIO and switch to output PWM signal as PWMOOUT 1 automatically If PWMOOUT bit is cleared to disable PWM the output pin exchanges to last GPIO mode automatically It easily to implement carry signal on off operation not to control TCOENB bit 5 TECHNOLOGY CO LTD Page 96 Version 1 4 N 7 SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP PWM Output gt lt gt PWMOOUT 0 PWMOOUT 1 The pin exchanges to output PWMOOUT 0 The pin exchanges PWMOOUT 1 mode and outputs PWM signal automatically to last GPIO mode output low PWM Output PWMOOUT 0 PWMOOUT 1 The pin exchanges to output 0 pin exchanges PWMOOUT 1 mode and outputs PWM signal automatically to last GPIO mode output high PWM Output 2 High impendence floating 7 gt PWMOOUT 0 PWMOOUT 1 The pin exchanges to output
45. 1 0 PAS ADLEN 4 pai CHS 3 0 ADC High ADC Reference Clock Voltage Counter eas gt 2 enoo SAR ADC P4 6 gt Analog EOC mut ADCIRQ ADC Offset P4 7 L Calibration ADENB ADS 074 0 ADTS 1 0 5 TECHNOLOGY CO LTD Page 122 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 9 2 ADC MODE REGISTER ADM is ADC mode control register to configure ADC configurations including ADC start ADC channel selection ADC high reference voltage source and ADC processing indicator These configurations must be setup completely before starting ADC converting 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADM ADENB ADS EOC GCHS CHS3 CHS2 CHS1 50 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 ADENB ADC control bit In power saving mode disable ADC to reduce power consumption 0 Disable ADC function 1 Enable ADC function Bit 6 ADS ADC start control bit ADS bit is cleared after ADC processing automatically 0 ADC converting stops 1 Start to execute ADC converting Bit 5 EOC ADC status bit EOC bit must be cleared by program before ADC start 0 ADC progressing 1 End of converting and reset ADS bit Bit 4 GCHS ADC global channel select bit 0 Disable channel 1 Enable AIN channel Bit
46. 1 or TCOCKS1 1 conditions TCO length is 8 bit 256 steps and the one count period is each cycle of input clock TCO Interval Time Fhoscz16MHz Fhosc 4MHz 5 4 FcpuzFhosc 4 ms Unit us ms Unit us 000b Fcpu 128 8 192 32 32 768 001b Fcpu 64 4 096 16 16 384 010b Fcpu 32 2 048 8 8 192 011b Fcpu 16 1 024 4 4 096 100b Fcpu 8 0 512 2 2 048 101b Fcpu 4 0 256 1 1 024 110b Fcpu 2 0 128 0 5 0 512 111b 1 0 064 0 25 0 256 000b Fhosc 128 2 048 8 8 192 001b Fhosc 64 1 024 4 4 096 010b Fhosc 32 0 512 2 2 048 011b Fhosc 16 0 256 1 1 024 100b Fhosc 8 0 128 0 5 0 512 101b Fhosc 4 0 064 0 25 0 256 110b Fhosc 2 0 032 0 125 0 128 111b Fhosc 1 0 016 0 0625 0 064 TCOCKSO TCOrate 2 0 TCO Clock 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 5 TECHNOLOGY CO LTD Page 93 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 3 3 TCOM MODE REGISTER TCOM is TCO timer mode control register to configure TCO operating mode including TCO pre scalar clock source PWM function These configurations must be setup completely before enabling TCO timer 0B4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOM TCOENB TCOrate2 0 TCOrateO TCOCKS1 TCOCKSO PWMOOUT Read Write R W R W R W R W R W R W R W After re
47. 4 6 4 7 0 Co AIO SONiX TECHNOLOGY CO LTD Page 178 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 8 Marking Definition 18 1 INTRODUCTION There are many different types in Sonix 8 bit MCU production line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank Flash ROM MCU 18 2 MARKING INDETIFICATION SYSTEM SN8 X PART X X X Material 5 TECHNOLOGY CO LTD Temperature Range Shipping Package Device ROM Type Title Page 179 B PB Free Package G Green Package 40 C 85 C W Wafer H Dice P P DIP K SKDIP S SOP X SSOP F LQFP J QFN 27E65 27E65L 27E64 27E64L 27E62 27E62L Flash 8 bit MCU Production Version 1 4 NONA 18 3 MARKING EXAMPLE Wafer Dice SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP Name ROM Type Device Package Temperature Material S8F27E65W FLASH 27 65 Wafer 40 85 SN8F27E65H FLASH 27E65 Dice 40 85 Green Package Name ROM Type Device Package Temperature Material SN8F27E65PG FLASH 27E65 P DIP 40 C 85 C
48. A 0nnn0n00b BOMOV TC2M A Set TC2C and TC2R register for TC2 Interval time MOV A value 2 must be equal to TC2R BOMOV TC2C A BOMOV TC2R A Clear TC2IRQ BOBCLR FTC2IRQ Enable TC2 timer and interrupt function BOBSET FTC2IEN Enable TC2 interrupt function BOBSET 2 Enable TC2 timer 5 TECHNOLOGY CO LTD Page 111 Version 1 4 SONIN N TC2 EVENT COUNTER CONFIGURATION Reset TC2 timer CLR TC2M Enable TC2 event counter BOBSET FTC2CKS1 Set TC2C and TC2R register for TC2 Interval time MOV A value BOMOV TC2C A BOMOV TC2R A Clear TC2IRQ BOBCLR FTC2IRQ Enable TC2 timer and interrupt function BOBSET 21 2 TCO PWM CONFIGURATION Reset TC2 timer CLR TC2M Set TC2 clock source and TC2 rate MOV A 4t0nnnOnOOb BOMOV TC2M A Set TC2C and TC2R register for PWM cycle MOV A value1 BOMOV TC2C A BOMOV TC2R A Set TC2D register for PWM duty MOV A value2 BOMOV TC2D A Enable PWM and TC2 timer BOBSET FTC2ENB BOBSET FPWM2OUT SONiX TECHNOLOGY CO LTD SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP Clear TC2M register Set TC2 clock source from external input pin 0 2 TC2C must be equal to TC2R Enable TC2 interrupt function Enable TC2timer Clear TC2M register TC2C must be equal to TC2R TC2D must be greater than TC2R Enable TC2 timer
49. ADDR1 CMPRS A Z Check if low end address JMP AAA If Not jump to checksum calculate MOV A END ADDR2 CMPRS A Y If Yes check if Y 2 middle end address JMP AAA If Not jump to checksum calculate JMP CHECKSUM END If Yes checksum calculated is done Y ADD 1 INCMS Y Increase Y NOP JMP B Jump to checksum calculate CHECKSUM END END USER CODE 5 TECHNOLOGY CO LTD Label of program end Page 24 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 2 2 DATA MEMORY RAM 512X8 bit RAM Bank Address RAM Location Comment Bank 0 000H RAM Bank 0 General purpose area 07 080H E System Register OFFH End of Bank 0 Bank 1 100H RAM Bank 1 General purpose area 1FFH End of Bank 1 Bank 2 200H RAM Bank 2 General purpose area 27FH End of Bank 2 The 512 byte general purpose RAM is separated into Bank1 and Bank2 Accessing the three banks RAM is controlled by register When RBANK 0 the program controls Bank 0 RAM directly When RBANK 1 the program controls Bank 1 RAM directly When RBANK 2 the program controls Bank 2 RAM directly Under one bank condition and need to access the other bank RAM setup the RBANK register is necessary When interrupt occurs RBANK register is saved and RAM bank is still last condition User can select RAM bank through setup RBANK register during processing interrupt servi
50. BOBCLR FT1IEN Disable T1 interrupt service BOBCLR FT1ENB Disable T1 timer MOV A 20 BOMOV T1M Set T1 clock 32 and falling edge trigger CLR T1CH CLR T1CL BOBSET FT1IEN Enable T1 interrupt service BOBCLR FT1IRQ Clear T1 interrupt request flag BOBSET FT1ENB Enable T1 timer BOBSET FGIE Enable GIE Example T1 interrupt service routine ORG OFH Interrupt vector JMP INT_SERVICE INT_SERVICE BOBTS1 FT1IRQ Check T1IRQ JMP EXIT INT T1IRQ 0 exit interrupt vector BOBCLR FT1IRQ Reset T1IRQ BOMOV A BOMOV 1 BOMOV A BOMOV TICLBUF A Save pulse width CLR T1CH CLR T1CL T1 interrupt service routine EXIT INT RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 74 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 12 ADC INTERRUPT OPERATION When the ADC converting successfully the ADCIRQ will be set to 1 no matter the ADCIEN is enable or disable If the ADCIEN and the trigger event ADCIRQ is set to be 1 As the result the system will execute the interrupt vector If the ADCIEN 0 the trigger event ADCIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the ADCIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation gt Example ADC interrupt request setup BOBCLR FADCIE
51. Bit 2 Bit 1 Bit 0 P5M P53M P52M P51M P50M Read Write R W R W R W R W After reset 0 0 0 0 Bit 7 0 PnM 7 0 Pn mode control bits n 0 5 0 Pn is input mode 1 output mode Users program them by bit control instructions BOBSET BOBCLR gt Example I O mode selecting CLR POM Set all ports to be input mode CLR P4M CLR P5M MOV A Set all ports to be output mode BOMOV POM A BOMOV 5 BOBCLR P4M 0 Set P4 0 to be input mode BOBSET 0 Set P4 0 to be output mode 5 TECHNOLOGY CO LTD Page 80 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 7 3 PULL UP REGISTER The pins build in internal pull up resistors and only support input mode The port internal pull up resistor is programmed by PnUR register When the bit of PnUR register is 0 the pin s pull up is disabled When the bit of PnUR register is 1 the I O pin s pull up is enabled OACH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POUR PO6R PO5R 4 PO2R PO1R POOR Read Write RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 OADH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1UR P17R P16R P15R P14R P13R P12R P11R P10R Read Write
52. Clear UART TX interrupt flag BOBSET FUTXIEN Enable UART TX interrupt function Start UART break pocket BOBSET FUTXBRK Transmit UART break pocket NOP One instruction delay for UTXBZ flag Check TX operation BOBTSO FUTXBZ Check UTXBZ bit UTXBZ 1 TX is operating JMP ENDTX UTXBZ 0 the end of TX Note UART TX break pocket is controlled UTXBRK bit and needn t load UTXD buffer 5 TECHNOLOGY CO LTD Page 137 Version 1 4 8 Bit Flash Micro Controller with Embedded ICE and ISP UART RX Configuration Select parity bit function BOBCLR FURXPEN Disable UART RX parity bit function BOBSET FURXPEN Enable UART RX parity bit function Select parity bit format BOBCLR FURXPS UART RX parity bit format is even parity BOBSET FURXPS UART RX parity bit format is odd parity Set UART baud rate MOV A value1 Set UART pre scaler URS 2 0 BOMOV URRX A MOV A value2 Set UART baud rate 8 bit buffer BOMOV URCR A Enable UART RX pin BOBSET FURXEN Enable UART RX function and UART RX pin Enable UART RX interrupt function BOBCLR FURXIRQ Clear UART RX interrupt flag BOBSET FURXIEN Enable UART RX interrupt function NOP One instruction delay for URXBZ flag Check RX operation BOBTSO FURXBZ Check URXBZ bit JMP CHKRX URXBZ 1 RX is operating URXBZ 0 the end of RX Note UA
53. Fcpu frequency is 16KHz 4 4KHz 4 3 NOISE FILTER The Noise Filter controlled by Noise Filter code option is a low pass filter and supports external oscillator including RC and crystal modes The purpose is to filter high rate noise coupling on high clock signal from external oscillator In high noisy environment enable Noise Filter code option is the strongly recommendation to reduce noise effect 4 4 SYSTEM HIGH SPEED CLOCK The system high speed clock has internal and external two type The external high speed clock includes 4MHz 12MHz 32KHz crystal ceramic and RC type These high speed oscillators are selected by High CLK code option The internal high speed clock supports real time clock RTC function Under IHRC_RTC mode the internal high speed clock and external 32KHz oscillator active The internal high speed clock is the system clock source and the external 32KHz oscillator is the RTC clock source to supply a accurately real time clock rate 5 TECHNOLOGY CO LTD Page 52 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 4 4 1 HIGH CLK CODE OPTION For difference clock functions Sonix provides multi type system high clock options controlled by High code option The High CLK code option defines the system oscillator types including 16M RC 32K X tal 12M X tal and 4M X tal These oscillator options support different bandwidth o
54. Green Package SN8F27E65FG FLASH 27E65 LQFP 40 85 C Green Package SN8F27E65JG FLASH 27E65 QFN 40 85 C Green Package SN8F27E65UG FLASH 27E65 S DIP 40 85 C Green Package SN8F27E65LPG FLASH 27E65 P DIP 40 C 85 C Green Package SN8F27E65LFG FLASH 27E65 LQFP 40 C 85 C Green Package SN8F27E65LJG FLASH 27E65 QFN 40 85 SN8F27E65LUG FLASH 27E65 S DIP 40 C 85 C Green Package SN8F27E64KG FLASH 27E65 SK DIP 40 C 85 C Green Package SN8F27E64SG FLASH 27E65 SOP 40 85 SN8F27E64XG FLASH 27E65 SSOP 40 85 SN8F27E64JG FLASH 27E65 QFN 40 85 Green Package SN8F27E64LKG FLASH 27E65 SK DIP 40 C 85 C Green Package SN8F27E64LSG FLASH 27E65 SOP 40 85 C Green Package SN8F27E64LXG FLASH 27E65 SSOP 40 85 C Green Package SN8F27E64LJG FLASH 27E65 QFN 40 85 Green Package SN8F27E62PG FLASH 27E65 P DIP 40 C 85 C Green Package SN8F27E62SG FLASH 27E65 SOP 40 85 SN8F27E62LPG FLASH 27E65 P DIP 40 C 85 C Green Package SN8F27E62LSG FLASH 27E65 SOP 40 85 C Green Package PB Free Package Name ROM Type Device Package Temperature Material SN8F27E65PB FLASH 27E65 P DIP 40 85 PB Free Package SN8F27E65FB FLASH 27E65 LQFP 40 85 PB Free Package SN8F27E65JB FLASH 27E65 QFN 40 85 Package SN8F27E65UB FLASH 27E65 S DIP 40 85 PB Free Package SN8F27E65LPB FLASH 27E65
55. Low Speed Crystal 32K 455K 4 Tost gt 5 TECHNOLOGY CO LTD Page 57 Version 1 4 N 7 SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 5 SYSTEM OPERATION MODE 5 1 OVERVIEW The chip builds in four operating mode for difference clock rate and power saving reason These modes control oscillators op code operation and analog peripheral devices operation Normal mode System high speed operating mode Slow mode System low speed operating mode Power down mode System power saving mode Sleep mode Green mode System ideal mode Operating Mode Control Block CLKMD 1 Reset Control Block One of reset trigger sources actives Wake up condition PO P1 input status is level changing MSP matched device address Power Down Mode One of reset trigger sources actives Wake up condition Normal Mode SowMoe Mode P1 input status is level changing Wake up condition 1 2 TT PO P1 input status is level changing TO timer counter is overflow TO timer counter is overflow Green Mode One of reset trigger sources actives 5 TECHNOLOGY CO LTD Page 58 Version 1 4 NONA Operating Mode Clock Control Table Operating Mode Normal Mode Slow Mode Green Mode SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP Power Down Mode IHRC
56. Low voltage reset indicator level 40 C 85 C 3 1 These parameters are for design reference not tested 3 VoL VoH loH2 Tinto Vdd 3V 16MHz Vdd 5V Vdd 3V 5 TECHNOLOGY CO LTD Page 167 Version 1 4 N N M SN8F27E60 Series 5 S a X 8 Bit Flash Micro Controller with Embedded ICE and ISP SN8F27E60L Series DC CHARACTERISTIC All of voltages refer to Vss Vdd 3 0V Fosc 16MHz ambient temperature is 25 C unless otherwise note PARAMETER DESCRIPTION MIN UNIT NEUEN 20 85 16 2 ISP is inactive 40 85 16MHz ISP actives RAM Data Retention voltage Vor Vdd rise rate Vpor Vdd rise rate to ensure internal power on reset 0 05 Vms Input Low Voltage ViL All input ports Reset pin XIN XOUT pins Vss 0 3 Vdd Input High Voltage All input ports Reset pin XIN XOUT pins 07vdd Output Low Voltage loL1 9mA loL2 14mA Vss 0 5 V Output High Voltage loH1 7mA loH2 8mA vdd 05 Vdd v port input leakage current Pull up resistor disable Vin Vdd 2 uA m in Vss XINIXOUT pins 2 9 ins VO output source current LHI Vaa 0 5 XINXOUT pins 3
57. Master MCU sends SCK for initial the data transfer Both master and slave MCU must work in the same clock edge direction and then both controllers would send and receive data at the same time SIO Master SIO Slave SCKMD 0 SCKMD 1 SCK i i SCK sii SO 2nd Receive Buffer Read SIOB Address SIOB Read SIOB 204 Receive Buffer Address SIOB Write SIOB sng jeujoju sng Shift Register Shift Register SIOB i SIOB SIO Data Transfer Diagram SONiX TECHNOLOGY CO LTD Page 143 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 11 5 SIOR REGISTER DESCRIPTION OE1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOR SIOR7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIORO Read Write After reset 0 0 0 0 0 0 0 0 The SIOR is designed for the SIO counter to reload the counted value when end of counting It is like a post scalar of SIO clock source and let SIO has more flexible to setting SCK range Users can set the SIOR value to setup SIO transfer time To setup SIOR value equation to desire transfer time is as following frequency SIO rate 256 SIOR 2 SIOR 256 1 2 SCK frequency SIO rate gt Example Setup SIO clock to be 5KHz Fhosc 4MHz SIO s rate Fhosc 4 25
58. R W RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4UR P47R P46R P45R P44R P43R P42R P41R P40R Read Write R W RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 0B1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5UR P53R P52R P51R P50R Read Write R W R W R W After reset 0 0 0 0 gt Example I O Pull up Register MOV A Enable 4 5 Pull up register BOMOV POUR A PAUR A BOMOV P5UR A 5 TECHNOLOGY LTD Page 81 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 7 4 PORT DATA REGISTER 6 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PO P05 P04 2 P01 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1 P17 P16 P15 P14 P13 P12 P11 P10 Read Write R W RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 P47 P46 P45 P44 P43 P42 P41 P40 Read Write R W RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P53 52 51 50 Read Write RAN R W R W After reset 0 0 0 0 Note The P04 keeps 1
59. SN8F27E64K S X SKDIP SOP SSOP SN8F27E64LK S X SKDIP SOP SSOP Writer Connector IC and JP3 48 pin text tool Pin Assignment JP1 JP2 JP1 JP2 IC JP3 IC JP3 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Number Pin Name Pin Number VDD GND VSS P4 5 32 P4 5 VDD VPP HLS RST ALSB PDB Bias Voltage Programming Pin Information of SN8F27E65 Series Chip Name SN8F27E64J QFN SN8F27E64LJ QFN Writer Connector IC and JP3 48 pin text tool Pin Assignment JP1 JP2 JP1 JP2 IC IC JP3 IC IC JP3 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Number Pin Name Pin Number 23 233 3 VDD VDD GND CLK CE PGM OE D1 DO D3 D2 D5 D4 D7 D6 VDD VPP HLS RST ALSB PDB Bias Voltage 5 TECHNOLOGY CO LTD Page 177 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Bit Flash Micro Controller with Embedded ICE and ISP Programming Pin Information of SN8F27E65 Series Chip Name SN8F27E62P S PDIP SOP SN8F27E62LP S PDIP SOP Writer Connector IC and JP3 48 pin text tool Pin Assignment JP1 JP2 JP1 JP2 4 4 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Number Pin Name Pin Number VDD VDD VDD GND VSS VSS CLK P4 5 CE e PGM OE D1 DO 03 02 05 D4 D7 D6 VDD VPP HLS RST ALSB PDB Bias Voltage
60. Schmitt trigger structure as input mode Built in pull up resisters vo channel 2 input pin P4 3 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters EQ ADC channel 3 input pin P4 4 AIN4 4 4 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters RST P0 4 XIN P0 6 5 0 PO 1 INT1 TC1 P0 2 URX 2 PO 3 UTX T1 I O P1 0 EICK P1 1 EIDA P1 2 SDA P1 3 SCL P1 4 SDO P1 5 SDI 5 TECHNOLOGY CO LTD Page 13 Version 1 4 N SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP J AIN4 ADC channel 4 input pin P4 5 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters ADC channel 5 input pin P4 6 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters PADANG 45 ADC channel 6 input pin P4 7 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters o ADC channel 7 input pin P5 0 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters vo 50 ADC channel 8 input pin P5 1 AIN9 P5 1 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters PWMO 9 ADC channel 9 input pin 0 PWM 0 output pin P5 2 Bi dire
61. Sum is 2232 hip SNBF27E05 has maximum program ROM size 6188 he program has used size 115 0x72 he program remain free size 6825 for use Find in Files 1 Find in 2 5 0041 NUM count at 1 EY PXT 2 Qe addbuft E 1 an gs 1526 ASI PFLAGBUF 95 1 22 1 os 1 os 1 equ reap equ ORG 1 10046 section start je Reset Reset vector pesto 7 are reserved pointer and bal interrupt iClear call Sysinit System initial a S UG 4 Program test CodeVSNBF27E65Nio toggle 15 16 85M Check Sun is 8660 ecurity Check Sun is 2222 hip SM8F27E65 has maximum program size 6188 program has used size 115 0x73 program remain free size 6825 use ET Reedy Ln Turn off the power of SN8F27E65 Starter kit or target Disconnect SN8F27E65 Starter kit or target from Smart Development Adapter Turn on the power of SN8F27E65 Starter kit or target and MCU works independently 5 TECHNOLOGY CO LTD Page 174 Version 1 4 SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 7 SN8F27E60 series MCUs Flash ROM erase program verify support SDA MP Pro writer and wri
62. TC1 overflows and the end of PWM s cycle to keeps PWM continuity If modify the PWM cycle by program as PWM outputting the new cycle occurs at next cycle when TC1C loaded from TC1R Enable TC1 and PWM TC1C overflows from OxFF to 0x00 TC1C is loaded from TC1R TC1C TC1D TC1C is loaded from TC1R PWM outputs high status PWM exchanges to low status PWM exchanges to high status nis i PWM Output One complete cycle of PWM Next cycle The resolution of PWM is decided by TC1R range is from 0x00 0xFF If TC1R 0x00 PWM s resolution is 1 256 If TC1R 0x80 PWM s resolution is 1 128 TC1D controls the high pulse width of PWM for PWM s duty When TC1C TC1D PWM output exchanges to low status TC1D must be greater than TC1R or the PWM signal keeps low status When PWM outputs still actives as TC1 overflows and TC1 interrupt function actives as TC1IEN 1 But strongly recommend be careful to use PWM and TC1 timer together and make sure both functions work well The PWM output pin is shared with GPIO and switch to output PWM signal as PWM1OUT 1 automatically If PWM1OUT bit is cleared to disable PWM the output pin exchanges to last GPIO mode automatically It easily to implement carry signal on off operation not to control TC1ENB bit SONiX TECHNOLOGY CO LTD Page 103 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP PWM Output
63. The number of ISP flash ROM program operation can be 1 word 32 word at one time but these words must be in the same page ISP flash ROM program ROM map is as following ISP ROM MAP This page includes reset vector and interrupt sector We strongly recommend to reserve the area to do ISP erase This page includes ROM reserved area We strongly recommend to reserve the area not to do ISP erase 0620 0040 8 4 00E0 5 0100 S red 8 71000 1020 peus Ead ISP flash ROM program page density is 32 word which limits program page boundary The first 32 word of flash ROM 0x0000 0x001F includes reset vector and interrupt vectors related essential program operation and the last page 32 word of flash ROM 0x1780 0x17FF includes system reserved ROM area we strongly recommend do not execute ISP flash ROM program operation in the two pages Flash ROM area 0x0020 0x177F includes 187 page for ISP flash ROM program operation ISP flash ROM program operation is a simple memory mapping operation The first step is to plan a RAM area to store programmed data and keeps the RAM address for IS RAM addressing The second step is to plan a ROM area will be programmed from RAM area in ISP flash ROM program operation The RAM addressing is through PERAML 9 0 10 bit buffer to configure the start RAM address The RAM data storage sequence is down up
64. UART transmit interrupt request flag BOBSET FGIE Enable GIE gt Example UART receive interrupt service routine ORG 13H Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FURXIRQ Check RXIRQ JMP EXIT_INT RXIRQ 0 exit interrupt vector BOBCLR FURXIRQ Reset RXIRQ 588 UART receive interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 77 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 6 15 MULTI INTERRUPT OPERATION Under certain condition the software designer uses more than one interrupt requests Processing multi interrupt request requires setting the priority of the interrupt requests The IRQ flags of interrupts are controlled by the interrupt event Nevertheless the IRQ flag 1 doesn t mean the system will execute the interrupt vector In addition which means the IRQ flags can be set 1 by the events without enable the interrupt Once the event occurs the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table For multi interrupt conditions two things need to be taking care of One is that it is multi vector and each of interrupts points to unique vector Two is users have to define the interrupt vector The following example shows the way to define the interrupt vector
65. an easy low battery detector L VD24 LVD33 flags indicate VDD voltage level For low battery detect application only checking LVD24 LVD33 status to be battery status This is a cheap and easy solution OEFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE LVD24 LVD33 STKPB2 STKPB1 STKPBO Read Write RAN R W R W R W After Reset 0 1 1 1 Bit 6 LVD24 LVD24 low voltage detect indicator 0 Vdd gt LVD24 detect level 1 Vdd lt LVD24 detect level Bit 5 LVD33 LVD33 low voltage detect indicator 0 Vdd gt LVD33 detect level 1 Vdd lt LVD33 detect level LVD LVD Code Option LVD_L LVD_M LVD_H 1 8V Reset Available Available Available 2 4V Flag Available 5 2 4V Reset Available 3 3V Flag Available LVD L If VDD 1 8V system will be reset Disable LVD24 and LVD33 bit of PFLAG register LVD M If VDD 1 8V system will be reset Enable LVD24 bit of PFLAG register If VDD gt 2 4V LVD24 is 0 If VDD lt 2 4V LVD24 flag is 1 Disable LVD33 bit of PFLAG register LVD H If VDD 2 4V system will be reset Enable LVD24 bit of PFLAG register If VDD gt 2 4V LVD24 is 0 If VDD lt 2 4V LVD24 flag is 1 Enable LVD33 bit of PFLAG register If VDD gt 3 3V LVD33 is 0 If VDD lt 3 3V LVD33 flag is 1 LVD MAX If VDD 3 3V system will be reset Note 1 After
66. area of bank 0 Page 35 Version 1 4 8 Flash Micro Controller with Embedded ICE and ISP 2 2 8 R REGISTER R register is an 8 bit buffer There are two major functions of the register used as working register For store high byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBITO Read Write R W R W R W R W R W R W R W After reset s Note Please refer to the LOOK UP TABLE DESCRIPTION about register look up table application 5 TECHNOLOGY CO LTD Page 36 Version 1 4 IN N 7 SN8F27E60 Series a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 2 9 W REGISTERS W register includes WO W7 8 bit buffers There are two major functions of the register Can be used as general working registers in assembly language situation Can be used as program buffers in C language situation 088H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WO WOBIT7 WOBIT6 WOBIT5 WOBIT4 WOBIT3 WOBIT2 WOBIT1 WOBITO Read Write R W R W R W R W R W R W R W
67. bit8 bito The head of the page X Y X 2 gt 3 20 DATA1 DATAO start address of ISP 21 DATA3 DATA2 X430 m 31 Y 30 _DATA21 DATA20 end of the page Y 31 PATAAS DATA The end address of ISP 5 TECHNOLOGY CO LTD Page 161 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP gt Example Use ISP flash ROM program to program 32 word data to flash ROM as case 1 Set RAM buffer start address is 0x010 Set flash ROM programmed start address is 0x0020 Load data into 64 byte RAM buffer Set RAM start address of 64 byte buffer MOV A 0x10 BOMOV PERAML A MOV A 0x00 BOMOV PERAMCNT A Set ISP program length to 32 word MOV A 11111000b OR PERAMCNT A Set programmed start address of flash ROM to 0x0020 MOV A 0x20 BOMOV PEROML A MOV A 0x00 BOMOV Clear watchdog timer MOV A 0X5A BOMOV WDTR A Start to execute ISP flash ROM program operation MOV A 0X5A BOMOV PECMD A NOP NOP Set PERAML 7 0 to 0x20 Set PERAML 9 8 to 00b Set PERAMCNT 7 3 to 111110 Move low byte address 0x20 to PEROML Move high byte address 0x00 to PEROMH Start to program flash ROM NOP Delay The end of ISP flash ROM program operation The two instructions make a short delay to let system stable after ISP flash ROM program operation
68. buffer and write the last program counter value PC into the stack buffer OEFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE LVD24 LVD33 STKPB2 STKPB1 STKPBO Read Write R W R R R W R W R W After reset 0 1 1 1 Bit 2 0 5 Stack pointer n 0 2 Bit 7 GIE Global interrupt control bit 0 Disable 1 Enable Please refer to the interrupt chapter gt Example Stack pointer STKP reset we strongly recommended to clear the stack pointers in the beginning of the program MOV A 00000111 BOMOV STKP A 5 TECHNOLOGY CO LTD Page 39 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 4 3 STACK BUFFER The program counter PC value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 OFOH OFFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnH SnPC12 SnPC11 SnPC10 SnPC9 SnPC8 Read Write R W R W R W R W R W After reset 0 0 0 0 0 OFOH OFFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0
69. compared with MSPADD and also the general call address which fixed by hardware If the genera call address matches the MSPSR data is transferred into MSPBUF the BF flag bit is set and in the falling edge of the ninth clock ACK MSPIRQ flag set for interrupt request In the interrupt service routine reading MSPBUF can check if the address is the general call address or device specific Address compare to general address 4 pee After ACK_ set interrupt Y Receiving Data MSPIRQ 211211 1 Cleared by Software SSPOV Read MSPBUF 0 General Call Address Timing Diagram 5 TECHNOLOGY CO LTD Page 150 Version 1 4 NONA 12 7 5 Slave Wake up SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP When MCU enter Power down mode if MSBENB bit is still set MCU can wake up by matched device address The address of MSP bus following START bit 8 byte address will shift into MSPSR if address matched an NOT Acknowledge will response on the ninth clock of SCL and MCU will be wake up MSPWKset and start wake up procedure but MSPIRQ will not set and MSPSR data will not load to MSPUBF After MCU finish wake up procedure MSP will be in idle status and waiting master s START signal Control register MSPIRQ MSPOV and MSPBUF will be the same status data before power down If address not matches a NOT acknowledge is still sent on the ninth clock of SCL but
70. environment the Always On option of watchdog operations is the strongly recommendation to make the system reset under error situations and re start again Watchdog clear is controlled by WDTR register Moving 0x5A data into WDTR is to reset watchdog timer 096H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTR WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTHR1 WDTRO Read Write 0 0 0 0 0 0 0 0 Example An operation of watchdog timer is as following To clear the watchdog timer counter the top of the main routine of the program Main MOV A 5AH Clear the watchdog timer BOMOV WDTR A CALL SUB1 CALL SUB2 JMP MAIN 5 TECHNOLOGY CO LTD Page 86 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP gt Example Clear watchdog timer by RST_WDT macro of Sonix IDE Main RST_WDT Clear the watchdog timer CALL SUB1 CALL SUB2 JMP MAIN Watchdog timer application note is as following Before clearing watchdog timer check 1 status and check RAM contents can improve system error Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function gt Example An op
71. external reset pin MAIN StackChk BOBTS1 STKOV JMP MAIN STKOV 0 program keeps executing BOBCLR P1 0 STKOV 1 stack overflows and set P1 0 output low status to force reset pin to low status to trigger system reset 5 TECHNOLOGY CO LTD Page 40 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 4 5 STACK OPERATION EXAMPLE The two kinds of Stack Save operations refer to the stack pointer STKP and write the content of program counter PC to the stack buffer are CALL instruction and interrupt service Under each condition the STKP decreases and points to the next available stack location The stack buffer stores the program counter about the op code address The Stack Save operation is as the following table STKP Register Stack Buffer STKOV STKPB2 STKPB1 STKPBO High Byte Low Byte 0 1 1 1 Free Free 0 1 1 1 0 1 2 1 o 0o 3 1 0 0 8 2 Description L4 0 1 STOH STGL 0 5 o 1 0 SKH sa 0 p 8 o o t Is 0 1 7 0 0 o STKH STRL 0 j 1 4 1 O xu pl gt 1 538 1 J 1 0 j 1 Stack Over error There are Stack Restore operations correspond to each push operation to restore the program counter PC The RETI instruction uses for interrupt service routin
72. first and then low pulse outputs TC2R register controls the cycle of PWM and TC2D decides the duty high pulse width length of PWM TC2C initial value is TC2R reloaded when TC2 timer enables and TC2 timer overflows When TC2C count is equal to TC2D the PWM high pulse finishes and exchanges to low level When TC2 overflows TC2C counts from OxFF to 0x00 one complete PWM cycle finishes The PWM exchanges to high level for next cycle The PWM is auto reload design to load TC2C from TC2R automatically when TC2 overflows and the end of PWM s cycle to keeps PWM continuity If modify the PWM cycle by program as PWM outputting the new cycle occurs at next cycle when TC2C loaded from TC2R Enable TC2 and PWM TC2C overflows from OxFF to 0x00 TC2C is loaded from TC2R TC2C TC2D TC2C is loaded from TC2R PWM outputs high status PWM exchanges to low status PWM exchanges to high status E PWM Output Next cycle The resolution of PWM is decided by TC2R TC2R range is 0 00 If TC2R 0x00 PWM s resolution is 1 256 If TC2R 0x80 PWM s resolution is 1 128 TC2D controls the high pulse width of PWM for PWM s duty When 2 TC2D PWM output exchanges to low status TC2D must be greater than TC2R or the PWM signal keeps low status When PWM outputs TC2IRQ still actives as TC2 overflows and TC2 interrupt function actives as TC2IEN 1 But strongly recom
73. function TC2rate 2 0 bits are useless Bit 6 4 TC2RATE 2 0 TC2 timer clock source select bits 2 50 0 gt 000 Fcpu 128 001 64 010 Fcpu 32 011 16 100 8 101 4 110 Fcpu 2 111 1 TC2CKS0 1 gt 000 Fhosc 128 001 Fhosc 64 010 Fhosc 32 011 Fhosc 16 100 Fhosc 8 101 Fhosc 4 110 Fhosc 2 111 Fhosc 1 Bit 7 TC2ENB TCO counter control bit 0 Disable TC2 timer 1 Enable TC2 timer 8 5 4 TC2C COUNTING REGISTER TC2C is TC2 8 bit counter When TC2C overflow occurs the TC2IRQ flag is set as 1 and cleared by program The TC2C decides TC2 interval time through below equation to calculate a correct value It is necessary to write the correct value to TC2C register and TC2R register first time and then enable TC2 timer to make sure the fist cycle correct After one TC2 overflow occurs the TC2C register is loaded a correct value from TC2R register automatically not program OBDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC2C TC2C7 TC2C6 TC2C5 204 TC2C3 TC2C2 TC2C1 2 0 Read Write R W RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TC2C initial value is as following TC2C initial value 256 TC2 interrupt interval time TC2 clock rate 5 TECHNOLOGY CO LTD Page 108 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Contro
74. i 0 pin exchanges PWMOOUT 1 mode and outputs PWM signal automatically last GPIO mode input 8 3 9 TCO TIMER OPERATION EXPLAME TIMER CONFIGURATION Reset TCO timer CLR TCOM Clear TCOM register Set TCO clock source and rate MOV A 0nnn0n00b BOMOV TCOM A Set TCOC and TCOR register for TCO Interval time MOV A value must be equal to TCOR BOMOV TCOC A BOMOV TCOR A Clear TCOIRQ BOBCLR FTCOIRQ Enable TCO timer and interrupt function BOBSET FTCOIEN Enable TCO interrupt function BOBSET FTCOENB Enable TCO timer 5 TECHNOLOGY CO LTD Page 97 Version 1 4 SONIN N EVENT COUNTER CONFIGURATION Reset TCO timer CLR TCOM Enable event counter BOBSET FTCOCKS1 Set TCOC and TCOR register for TCO Interval time MOV A value BOMOV TCOC A BOMOV TCOR A Clear TCOIRQ BOBCLR FTCOIRQ Enable TCO timer and interrupt function BOBSET FTCOIEN BOBSET FTCOENB TCO PWM CONFIGURATION Reset TCO timer CLR TCOM Set TCO clock source and TCO rate MOV A 0nnn0n00b BOMOV TCOM A Set TCOC and TCOR register for PWM cycle MOV A value1 BOMOV TCOC A BOMOV TCOR A Set TCOD register for PWM duty MOV A value2 BOMOV TCOD A Enable PWM and TCO timer BOBSET FTCOENB BOBSET FPWMOOUT SONiX TECHNOLOGY CO LTD SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP
75. in the program memory gt Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP ISR WAKE JMP ISR INTO JMP ISR JMP ISR TO JMP ISR TCO JMP ISR TC1 JMP ISR TC2 JMP ISR T1 JMP ISR ADC JMP ISR SIO JMP ISR MSP JMP ISR UART RX JMP ISR UART TX ISR WAKE WAKE UP interrupt service routine RETI Exit interrupt vector ISR INTO INTO interrupt service routine RETI Exit interrupt vector ISR INT1 interrupt service routine RETI Exit interrupt vector ISR UART TX UART TX interrupt service routine RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 78 Version 1 4 NONA 7 I O PORT 7 1 OVERVIEW SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP The micro controller builds in 27 pin Most of the I O pins are mixed with analog pins and special function pins The shared pin list is as following Pin Name Type Shared Pin Shared Pin Control Condition PO 1 1 0 INTO TCO INT1 TC1 URX TC2 UTX 1 RST XOUT XIN EICK EIDA SDA SCL SDO SDI SCK SCS AIN 7 0 AIN 8 AIN 9 PWMO AIN 10 PWM1 AIN 11 PWM2 POOIEN 1 TCOCKS 1 TCOENB 1 PO1IEN 1 TC1CKS 1 TC1ENB 1 URXEN 1 TC2CKS 1 TC2ENB 1 UTXEN 1 T1CKS 1 T1ENB 1 Reset_Pin code option Reset High_CLK co
76. instruction cycle whose clock source includes high low speed oscillator in different operating modes High Fcpu and Low code options select instruction cycle pre scaler to decide instruction cycle rate In normal mode high speed clock the system clock source is high speed oscillator and Fcpu clock rate has eight options including Fhosc 1 Fhosc 2 Fhosc 4 Fhosc 8 Fhosc 16 Fhosc 32 Fhosc 64 Fhosc 128 In slow mode low speed clock the system clock source is internal low speed RC oscillator and the Fcpu including Flosc 1 Flosc 2 Flosc 4 Flosc 8 2 5 2 Reset Pin code option The reset pin is shared with general input only pin controlled by code option Reset The reset pin is external reset function When falling edge trigger occurring the system will be reset P04 Set reset pin to general bi direction pin P0 4 The external reset function is disabled and the is bi direction pin 2 5 3 Security code option Security code option is Flash ROM protection When enable security code option the ROM code is secured and not dumped complete ROM contents 2 5 4 Noise Filter code option Noise Filter code option is a power noise filter manner to reduce noisy effect of system clock If noise filter enable In high noisy environment enable noise filter enable watchdog timer and select a good LVD level can make whole system work well and avoid error event occurrence 5 TECHNOLOGY CO LTD Page 43 Version 1 4 NO
77. negligent regarding the design or manufacture of the part Main Office Address 10F 1 NO 36 Taiyuan Street Chupei City Hsinchu Taiwan R O C Tel 886 3 560 0888 Fax 886 3 560 0889 Taipei Office Address 15F 2 NO 171 Song Ted Road Taipei Taiwan R O C Tel 886 2 2759 1980 Fax 886 2 2759 8180 Hong Kong Office Unit 1519 Chevalier Commercial Centre NO 8 Wang Hoi Road Kowloon Bay Hong Kong Tel 852 2723 8086 Fax 852 2723 9179 Technical Support by Email Sn8fae sonix com tw SONiX TECHNOLOGY CO LTD Page 192 Version 1 4
78. processing Bit 2 UTXBZ UART TX operating status flag 0 UART TX is idle or the end of processing 1 UART TX is busy and processing Note URXBZ and UTXBZ bits are UART operating indicators After setting UART RX TX operations set 2 Fcpu Fuart NOP instruction is necessary and then check UART status through URXBZ and UTXBZ bits 10 9 UART DATA BUFFER 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UTXD UTXD7 UTXD6 UTXD5 UTXD4 UTXD3 UTXD2 UTXD1 UTXDO Read Write R W RAN RAN RAN RAN RAN RAN RAN After Reset 0 0 0 0 0 0 0 0 Bit 7 0 UTXD UART transmitted data buffer OE8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URXD UTXD27 UTXD26 UTXD25 UTXD24 UTXD23 UTXD22 UTXD21 UTXD20 Read Write RAN R W RAN RAN RAN RAN RAN RAN After Reset 0 0 0 0 0 0 0 0 Bit 7 0 UART received data buffer 5 TECHNOLOGY CO LTD Page 135 Version 1 4 8 Flash Micro Controller with Embedded ICE and ISP 10 10 UART OPERATION EXAMLPE UART TX Configuration Select parity bit function BOBCLR FUTXPEN Disable UART TX parity bit function BOBSET FUTXPEN Enable UART TX parity bit function Select parity bit format BOBCLR FUTXPS UART TX parity bit format is even parity BOBSET FUTXPS UART TX parity bit format is odd parity Set UART baud rate MOV A value1 Set UART pre scaler URS 2 0 BOMOV URRX A MOV A
79. structure The first RAM data is the low byte data of the first word of flash ROM The second RAM data is the high byte data of the first word of ROM and so on ISP programming length is 1 word 32 word ISP flash ROM programming length is controlled by 7 3 bits which is 5 bit format Before ISP ROM programming execution set the length by program PEROML 7 0 and 7 0 define the target starting address 15 0 of flash ROM Write the start address into PEROML and PEROMH registers set PECMD register to 5 and the system start to execute ISP flash ROM program operation If the programming length is over ISP flash ROM program page boundary the hardware immediately stops programming flash ROM after finishing programming the last word of the ROM page So it is very important to plan right ROM address and programming length 5 TECHNOLOGY CO LTD Page 160 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP Case 1 32 word ISP program RAM buffer length is 64 byte and RAM address is X X 63 7 3 11111b meets a complete one page 32 word of flash ROM The page address of flash ROM is Y Y 31 The Y is the start address and set to PEROML PEROMH registers RAM byte Flash ROM word RAM Address ROM Address 64 byte 32 word bit15 008 bitO The head of the page The start a
80. system points program counter to interrupt vector to do interrupt sequence Green mode function All T1 functions timer capture timer keeps running in green mode but wake up function Timer IRQ actives as any IRQ trigger occurrence e g timer overflow Rate Read TICL Register Write TICL Register Interrupt Flag T1 timer overflow Capture timer stop Trigger TICH Stop TI Counting Timer Start to Count and Stop Counting CPTG 1 0 CPTStart 8 6 2 T1 TIMER OPERATION T1 timer is controlled by T1ENB bit When T1ENB 0 T1 timer stops When T1ENB 1 T1 timer starts to count Before enabling T1 timer setup T1 timers configurations to select timer function modes e g basic timer interrupt function T1 16 bit counter 1 increases 1 by timer clock source When T1 overflow event occurs T1IRQ flag is set as 1 to indicate overflow and cleared by program The overflow condition is T1CH T1CL count from full scale OxFFFF to zero scale 0x0000 T1 doesn t build in double buffer so load T1CL by program when T1 timer overflows to fix the correct interval time If T1 timer interrupt function is enabled T1IEN 1 the system will execute interrupt procedure The interrupt procedure is system program counter points to interrupt vector ORG 000FH and executes interrupt service routine after T1 overflow occurrence Clear T1IRQ by program is necessar
81. the DC power is regulated from AC power source This kind of power usually couples with AC noise that makes the DC power dirty Or the external loading is very heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power down duration are longer in AC application The system power on sequence protects the power on successful but the power down situation is like DC low battery condition When turn off the AC power the VDD drops slowly and through the dead band for a while 3 4 1 THE SYSTEM OPERATING VOLTAGE To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship System Mini Operating Voltage Vdd V Normal Operating Area System Reset Voltage System Rate Fcpu Normally the system operation voltage area is higher than the system reset voltage to VDD and the reset voltage is decided by LVD detect level The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 4 2 LO
82. with Embedded ICE and ISP NONA 9 4 3 ADC PIN CONFIGURATION ADC input channels are shared with Port4 Port5 ADC channel selection is through ADCHS 3 0 bit ADCHS 3 0 value points to the ADC input channel directly ADCHS 3 0 0000 selects AINO ADCHS 3 0 0001 selects AINT Only one pin of Port4 and Port5 can be configured as ADC input in the same time The pins of Port4 and 5 configured as ADC input channel must be set input mode disable internal pull up and enable PACON P5CON first by program After selecting ADC input channel through ADCHS 3 0 set bit as 1 to enable ADC channel function The GPIO mode of ADC input channels must be set as input mode Theinternal pull up resistor of ADC input channels must be disabled and P5CON bits of ADC input channel must be set ADC input pins are shared with digital pins Connect an analog signal to COMS digital input pin especially the analog signal level is about 1 2 VDD will cause extra current leakage In the power down mode the above leakage current will be a big problem Unfortunately if users connect more than one analog input signal to Port4 or Port5 will encounter above current leakage situation PACON P5CON is Port4 Port5 configuration register Write 1 into PACON 7 0 and 3 0 will configure related Port4 Port5 pin will be set as input mode and disable pull up resistor
83. 0 0 STKn STKnH STKnL n 7 0 2 4 4 STACK OVERFLOW INDICATOR If stack pointer is normal and not overflow the program execution is correct If stack overflows the program counter would be incorrect making program execution error STKOV bit is stack pointer overflow indicator to monitor stack pointer status When STKOV 0 stack pointer status is normal If STKOV 1 stack overflow occurs and the program execution would be error The program can take measures to recover program execution from stack overflow situation through STKOV bit 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG POR WDT RST STKOV C DC Z Read Write H H H H R W R W R W After Reset 0 0 0 Bit 4 STKOV Stack overflow indicator 0 Non overflow 1 Stack overflow Note If STKOV bit is set as stack overflowing only system reset event can clear STKOV bit e g watchdog timer overflow external reset pin low status or LVD reset gt Example Stack overflow protection through watchdog reset Watchdog timer must be enabled MAIN StackChk BOBTS1 STKOV JMP MAIN STKOV 0 program keeps executing JMP STKOV 1 stack overflows and use jump here operation making watchdog timer overflow to trigger system reset gt Example Stack overflow protection through external reset External reset function must be enabled and one GPIO pin output mode connects to
84. 110b 2 32 768 4 2 1 0 5 131 072 1116 1 16 384 0 25 65 536 0006 Fhosc 128 524 288 8 2097 152 001b Fhosc 64 262 144 1048 576 010b Fhosc 32 131 072 524 288 011b Fhosc 16 65 536 262 144 100b Fhosc 8 32 768 4 2 1 0 5 131 072 101b Fhosc 4 16 384 0 25 65 536 110b Fhosc 2 8 192 0 125 32 768 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 111b Fhosc 1 4 096 0 0625 16 384 8 6 3 MODE REGISTER T1M is T1 timer mode control register to configure T1 operating mode including T1 pre scalar clock source capture parameters These configurations must be setup completely before enabling T1 timer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1M T1ENB T1rate2 T1rate1 T1rateO T1CKS Read Write R W RAN R W RAN R W After reset 0 0 0 0 0 Bit 7 T1ENB T1 counter control bit 0 Disable T1 timer 1 Enable T1 timer Bit 6 4 TIRATE 2 0 T1 timer clock source select bits T1CKS20 gt 000 Fcpu 128 001 Fcpu 64 010 Fcpu 32 011 Fcpu 16 100 Fcpu 8 101 4 110 Fcpu 2 111 Fcpu 1 T1CKS 1 gt 000 Fhosc 128 001 Fhosc 64 010 Fhosc 32 011 Fhosc 16 100 Fhosc 8 101 Fhosc 4 110 Fhosc 2 111 Fhosc 1 Bit 3 T1CKS T1 clock source control bit 0 1 Fhosc
85. 15 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for information only and devices are guaranteed to operate properly only within the specified range Internal High RC Oscillator MHz Internal High RC Oscillator MHz Fcpu IHRC 1 IHRC 16 FcpuzIHRC 1 IHRC 16 16 50 1890 48V 16 00 _ 1600 _ 20 S 15 50 1550 25V 20 15 00 15 00 mE 8 1450 00 1450 20 14 00 4 25 C 1400 2 13 50 70 13 50 4 5 1 8 20 25 30 35 40 45 50 5 5 85 40 20T oc 25 70 85 VDD V Temperature C 5 5 Internal Low RC Oscillator KHz Internal Low RC Oscillator KHz 21 00 21 00 18V 19 00 19 00 _ 17 00 40 17 00 1500 205 15 00 22 2 5 1300 05 8 13 00 3 0V 1100 55 1100 MEE 4 0 9 00 9 00 7 00 7 00 4 5 18 20 25 3 0 35 4 0 45 5 0 55 40 200 OC 25 70 85 5 0V VDD V Temperature C 5 5V SONiX TECHNOLOGY CO LTD Page 169 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 1 6 DEVELOPMENT TOOL SONIX provides an Embedded ICE emulator system to offer SN8F27E65 firmware development The platform is a in circuit debugger and controlled by SONIX
86. 19 10 SOP 20 PIN if A A AAA O HHH UHR 1 0 01 6typ 0 050typ SEATING PLANE AT 2 i c 0 004 NOR inch 5 TECHNOLOGY CO LTD Page 191 Version 1 4 N N M SN8F27E60 Series O 8 Flash Micro Controller with Embedded ICE and ISP SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was
87. 28 0 5 0 512 111b 1 0 064 0 25 0 256 000b Fhosc 128 2 048 8 8 192 001b Fhosc 64 1 024 4 4 096 010b Fhosc 32 0 512 2 2 048 011b Fhosc 16 0 256 1 1 024 100b Fhosc 8 0 128 0 5 0 512 101b Fhosc 4 0 064 0 25 0 256 110b Fhosc 2 0 032 0 125 0 128 111b Fhosc 1 0 016 0 0625 0 064 TC2CKSO TC2rate 2 0 TC2 Clock 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SONiX TECHNOLOGY CO LTD Page 107 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 5 3 TC2M MODE REGISTER TC2M is TC2 timer mode control register to configure TC2 operating mode including TC2 pre scalar clock source PWM function These configurations must be setup completely before enabling TC2 timer OBCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC2M 2 TC2rate2 TC2rate0 TC2CKS1 2 50 PWM2OUT Read Write R W RW R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 0 PWM2OUT PWM output control bit 0 Disable PWM output function and P5 3 is GPIO mode 1 Enable PWM output function and P5 3 outputs PWM signal Bit 2 2 50 2 clock source select bit 0 1 Fhosc Bit 3 TC2CKS1 TC2 clock source select bit 0 Internal clock Fcpu and Fhosc controlled by TC2CKSO bit 1 External input pin PO 2 INT2 and enable event counter
88. 5 3 4 BROWN OUT RESET 45 3 4 1 THE SYSTEM OPERATING VOLTAGE 46 5 TECHNOLOGY CO LTD Page 3 Version 1 4 N N M SN8F27E60 Series 5 8 Flash Micro Controller with Embedded ICE and ISP 3 4 2 LOW VOLTAGE DETECTOR VD QUE DH URN SHE Ix tu o aus 46 3 4 3 BROWN OUT RESET IMPROVEMINT eiii ia PER ERR 48 3J EXTERNAL RESE Il ERT M N 49 3 6 EXTERNAL RESET CIRCUIT 49 EXON Simply RC 49 3 6 2 Diode amp RC Reset saii rer enn 50 3 6 3 Zener Diode Reset 50 3 0 4 Voltage Bias Reset mount NP 51 3 6 5 External Reset iei edicere 51 4 SYSTEM CLOCK 52 4 FOVERVIEW 52 4 2 FEU INSTRUCTION CYCLE pola ab RE n m cM E Eo pe E aeaa 52 253 NOSEFUTER 50011 52 445 5 ea 52 HIGH 2509 a 53 4 4 2 INTERNAL HIGH SPEED OSCILLATOR RC TYPE IHRO eee 53 4 4 3 EXTERNAL H
89. 6 1 2 5KHz 4MHz 4 256 0 0001 1000000 256 100 156 5 TECHNOLOGY CO LTD Page 144 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 1 2 MAIN SERIAL PORT MSP 12 1 OVERVIEW The MSP Main Serial Port is a serial communication interface for data exchanging from one MCU to one MCU or other hardware peripherals These peripheral devices may be serial EEPROM A D converters Display device etc The MSP module can operate in one of two modes e Master Tx Rx Mode Slave Tx Rx mode with general address call for multiplex slave in single master situation The MSP features include the following 2 wire synchronous data transfer receiver Master SCL is clock output or Slave SCL is clock input operation SCL SDA are programmable open drain output pin for multiplex salve devices application Support 400K clock rate 2 Fcpuz4MIPs End of Transfer Receiver interrupt 12 2 MSP STATUS REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSPSTAT CKE DA P S RED BF Read Write R W R R R R R After reset 0 0 0 0 0 0 Bit 6 Slave Clock Edge Control bit In Slave Mode Receive Address or Data byte 0 Latch Data on SCL Rising Edge Default 1 Latch Data on SCL Falling Edge 1 In Slave Transmit mode Address Received depended setting Da
90. 6 19200 32 1016 0 16 38400 Fhosc 1 000b 0 16 51200 Fhosc 1 000b 0 16 57600 Fhosc 1 000b 0 08 102400 Fhosc 1 000b 0 16 115200 Fhosc 1 000b 0 64 128000 Fhosc 1 000b 0 80 250000 Fhosc 1 000b 0 00 X Note 1 We strongly recommend not to set URCR OxFF or UART operation would be error 2 If Noise Filter code option is Enable we strongly recommend to set Fcpu as Fhosc 2 Fhosc 16 UART operation would be error If Noise Filter code option is Disable the limitation doesn t exist SONiX TECHNOLOGY CO LTD Page 132 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 10 4 UART TRANSFER FORMAT The UART transfer format includes Bus idle status Start bit 8 bit Data Parity bit and Stop bit as following Stop Start UART Transfer Format with Parity Bit Stop Start UART Transfer Format without Parity Bit Bus Idle Status The bus idle status is the bus non operating status The UART receiver bus idle status of MCU is floating status and tied high by the transmitter device terminal The UART transmitter bus idle status of MCU is high status The UART bus will be set when URXEN and UTXEN are enabled Start Bit UART is a asynchronous type of communication and need a attention bit to offer receiver the transfer starting The start bit is a simple format which i
91. 60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 10 3 UART BAUD RATE UART clock is 2 stage structure including a pre scaler and an 8 bit buffer UART clock source is generated from system oscillator called Fhosc Fhosc passes through UART pre scaler to get UART main clock called Fuart UART pre scaler has 8 selections Fhosc 1 Fhosc 2 Fhosc 4 Fhosc 8 Fhosc 16 Fhosc 32 Fhosc 64 Fhosc 128 and 3 bit control bits URS 2 0 UART main clock Fuart purposes are the front end clock and through UART 8 bit buffer URCR to obtain UART processing clock and decide UART baud rate UART Pre scaler UART Main Fuart Selection Clock Rate Fhosc 16MHz URS 2 0 000b Fhosc 1 16MHz 001b Fhosc 2 8MHz 010b Fhosc 4 0110 Fhosc 8 2MHz 100b Fhosc 16 1MHz 101b Fhosc 32 0 5MHz 110b Fhosc 64 0 25MHz 111b Fhosc 128 0 125MHz OE6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URCR URCR7 URCR6 URCR5 URCR4 URCR3 URCR2 URCR1 URCRO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The UART baud rate clock source is Fhosc and divided by pre scalar The equation is as following UART Baud Rate 1 2 Fuart 1 256 URCR bps Fhosc z 16MHz Baud Rate UART URS 2 0 URCR Hex 2223 1200 32 1016 0 16 2400 32 1016 0 16 4800 Fhosc 32 101b 0 16 9600 Fhosc 32 101b 0 1
92. A MOV A value2 Set low byte BOMOV CPTCL A Clear T1IRQ BOBCLR FT1IRQ Enable T1 timer interrupt function and T1 capture timer function BOBSET FT1IEN Enable T1 interrupt function BOBSET FT1ENB Enable T1 timer BOBSET FCPTEN Enable T1 capture function Set capture timer start bit BOBSET FCPTStart 5 TECHNOLOGY CO LTD Page 120 Version 1 4 N 7 SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP T1 CAPTURE TIMER FOR SINGLE CYCLE MEASUREMENT CONFIGURATION Reset T1 timer MOV A 0x00 Clear T1M register BOMOV T1M A Set T1 clock rate select input source and select enable T1 capture timer MOV A 0000 nnn is T1rate 2 0 for T1 clock rate selection BOMOV T1M A m is T1 clock source control bit MOV A 000000mmb mm is CPTG 1 0 for T1 capture timer function selection BOMOV CPTM A CPTG 1 0 00b capture timer function CPTG 1 0 01b high pulse width measurement CPTG 1 0 10b low pulse width measurement CPTG 1 0 11b cycle measurement Clear T1CH T1CL CLR T1CH Clear high byte first CLR T1CL Clear low byte Clear T1IRQ BOBCLR FT1IRQ Enable T1 timer interrupt function and T1 capture timer function BOBSET FT1IEN Enable T1 interrupt function BOBSET FT1ENB Enable T1 timer BOBSET FCPTEN Enable T1 capture function Set capture timer start bit BOBSET FCPTStart 5 TECHNOLOGY CO L
93. ART interrupt request flag and also to be the UART operating status indicator when URXIEN 0 or UTXIEN 0 but cleared by program When UART operation finished the URXIRQ UTXIRQ would be set to 1 The UART also builds in Busy Bit to indicate UART bus status URXBZ bit is UART RX operation indicator UTXBZ bit is UART TX operation indicator If bus is transmitting the busy bit is 1 status If bus is finishing operation or in idle status the busy bit is 0 status UART TX operation is controlled by loading UTXD data buffer After UART TX configuration load transmitted data into UTXD 8 bit buffer and then UART starts to transmit the pocket following UART TX configuration UART RX operation is controlled by receiving the start bit from master terminal After UART RX configuration URX pin detects the falling edge of start bit and then UART starts to receive the pocket from master terminal UART provides URXPC bit and UFMER bit to check received pocket URXPC bit is received parity bit checker If received parity is error URXPC sets as 1 If URXPC bit is zero after receiving pocket the parity is correct UFMER bit is received stream frame checker The stream frame error definition includes Start bit error Stop bit error Stream length error UART baud rate error Each of frame error conditions makes UFMER bit sets as 1 after receiving pocket 5 TECHNOLOGY CO LTD Page 131 Version 1 4 N N M SN8F27E
94. C RTC High speed internal 16MHz RC XIN XOUT pins are connected to external 32768Hz crystal RC Low cost RC for external high clock oscillator XIN pin is connected to RC High oscillator XOUT pin is bi direction GPIO mode Low frequency power saving crystal e g 32 768 2 for external high 32K X tal clock oscillator 42M X tal High speed crystal resonator e g 12MHz for external high clock oscillator 4 X tal Standard crystal resonator e g 4M for external high clock oscillator Fhosc 1 Normal mode instruction cycle is 1 high speed oscillator clocks Fhosc 2 Normal mode instruction cycle is 2 high speed oscillator clocks High Fcpu Fhosc 4 Normal mode instruction cycle is 4 high speed oscillator clocks Low Fcpu Fhosc 8 Normal mode instruction cycle is 8 high speed oscillator clocks WDT CLK Always On Eo timer is always on enable even in power down and green Watch Dog Enable Enable watchdog timer Watchdog timer stops in power down mode and green mode Enable 0 4 LVD Enable LVD24 bit of PFLAG register for 2 4V low voltage indicator LVD H LVD will reset chip if VDD is below 2 4V Enable LVD33 bit of PFLAG register for 3 3V low voltage indicator LVD MAX LVD will reset chip if VDD is below 3 3V 5 TECHNOLOGY CO LTD Page 42 Version 1 4 N N 7 SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 2 5 1 Fcpu Code Option Fcpu means
95. C1C and TC1R must be set the same value before enabling TC1 timer TC1 is double buffer design If new TC1R value is set by program the new value is stored in 1 buffer Until TC1 overflow occurs the new value moves to real TC1R buffer This way can avoid any transitional condition to affect the correctness of TC1 interval time and PWM output signal Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1R TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 Read Write 0 0 0 0 0 0 0 0 The equation of TC1R initial value is as following TC1R initial value 256 TC1 interrupt interval time TC1 clock rate gt Example To calculation TC1C and TC1R value to obtain 10ms TC1 interval time TC1 clock source is 16 2 16 1MHz Select TC1RATE 000 128 TC1 interval time 2 10ms TC1 clock rate 16MHz 16 128 initial value 256 TC1 interval time input clock 256 10ms 16MHz 16 128 256 10 2 16 106 16 128 B2H 8 4 6 TC1D PWM DUTY REGISTER TC1D register s purpose is to decide PWM duty In PWM mode TC1R controls PWM s cycle and TC1D controls the duty of PWM The operation is base on timer counter value When TC1C TC1D the PWM high duty finished and exchange to low level It is easy to configure TC1D to choose the right PWM s duty for application
96. CTOR 0000H A one word vector address area is used to execute system reset A Power On Reset POR 1 Watchdog Reset WDT 1 A External Reset 5 1 After power on reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from POR WDT and RST flags of PFLAG register The following example shows the way to define the reset vector in the program memory gt Example Defining Reset Vector ORG 0 0000 5 Jump to user program address ORG 15H START 0015H The head of user program User program ENDP End of program Note The head of user program should skip interrupt vector area to avoid program execution error 5 TECHNOLOGY CO LTD Page 17 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 2 1 2 INTERRUPT VECTOR 0008H 0014H A 13 word vector address area is used to execute interrupt request If any interrupt service executes the program counter PC value is stored in stack buffer and jump to 0008h 0014h of program memory to execute the vectored interrupt This interrupt is multi vector and each of interrupts points to unique vector Users have to define the interrupt vector The following example shows the way to define the interrupt vector in the program memory
97. E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 5 7 3 P1W WAKEUP CONTROL REGISTER Under power down mode sleep mode and green mode the I O ports with wakeup function are able to wake the system up to normal mode The wake up trigger edge is level changing When wake up pin occurs rising edge or falling edge the system is waked up by the trigger edge The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register 09 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1W P17W P16W P15W P14W P13W P12W P11W P10W Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 P10W P17W Port 1 wakeup function control bits 0 Disable P1n wakeup function 1 Enable P1n wakeup function 5 TECHNOLOGY LTD Page 64 Version 1 4 N N M SN8F27E60 Series S NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 INTERRUPT 6 1 OVERVIEW This MCU provides 13 interrupt sources including 2 external interrupt INTO INT1 and 11 internal interrupt TO T1 TCO TC1 TC2 SIO MSP UTX URX W AKE ADC The external interrupt can wakeup the chip while the system is Switched from power down mode to high speed normal mode and interrupt request is latched until return to normal mode Once interrupt service is executed the GIE bit in STKP register will clear to 0 for stopping othe
98. EN Enable SIO interrupt service BOBCLR FSIOIRQ Clear SIO interrupt request flag BOBSET FGIE Enable GIE gt Example SIO interrupt service routine ORG 11H Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FSIOIRQ Check SIOIRQ JMP EXIT_INT SIOIRQ 0 exit interrupt vector BOBCLR FSIOIRQ Reset SIOIRQ 238 SIO interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 76 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 14 UART INTERRUPT OPERATION When the UART transmitter successfully the URXIRQ UTXIRQ will be set to 1 no matter the URXIEN UTXIEN is enable or disable If the URXIEN UTXIEN and the trigger event URXIRQ UTXIRQ is set to be 1 As the result the system will execute the interrupt vector If the URXIEN UTXIEN 0 the trigger event URXIRQ UTXIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the URXIEN UTXIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation gt Example UART receive and transmit interrupt request setup BOBSET FURXIEN Enable UART receive interrupt service BOBCLR FURXIRQ Clear UART receive interrupt request flag BOBSET FUTXIEN Enable UART transmit interrupt service BOBCLR FUTXIRQ Clear
99. Embedded ICE function VO pin configuration Four system clocks Bi directional P1 P4 P5 External high clock RC type up to 10MHz Wakeup PO P1 level change External high clock Crystal type up to 16 2 Pull up resisters PO P1 P4 P5 Internal high clock RC type 16 2 External interrupt P0 0 PO 1 Internal low clock RC type 16 2 ADC input pin AINO AIN11 Four operating modes Normal mode Both high and low clock active Fcpu Instruction cycle Slow mode Low clock only Fcpu Fhosc 1 Fhosc 2 Fhosc 4 Fhosc 8 Fhosc 16 Sleep mode Both high and low clock stop Fhosc 32 Fhosc 64 Fhosc 128 Green mode Periodical wakeup by timer Onchip watchdog timer and clock source Package Chip form support 1 8V 2 4V 3 3V 3 level LVD with trim PDIP 32 pin LQFP 32 pin Powerful instructions QFN 32 pin Instruction s length is one word SDIP 32 pin Most of instructions are one cycle only SKDIP 28 pin All ROM area JMP instruction SOP 28 pin All ROM area lookup table function SSOP 28 pin QFN 28 pin DIP 20 pin SOP 20 pin 5 TECHNOLOGY LTD Page 8 Version 1 4 N N M SN8F27E60 Series 5 NS X 8 Bit Flash Micro Controller with Embedded ICE and ISP SN8F27E60 series micro controller includes two types for different power types For AC power type alternating current power source and DC high voltage power lt 5 5V the power pin has VDD and VDDL VDD pin is connect to DC power source from DC DC
100. GISTER TC1C is TC1 8 bit counter When TC1C overflow occurs the TC1IRQ flag is set as 1 and cleared by program The TC1C decides TC1 interval time through below equation to calculate a correct value It is necessary to write the correct value to TC1C register and TC1R register first time and then enable TC1 timer to make sure the fist cycle correct After one TC1 overflow occurs the TC1C register is loaded a correct value from TC1R register automatically not program OB9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1C TC1C7 TC1C6 TC1C5 1 4 TC1C3 TC1C2 TC1C1 TC1CO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TC1C initial value is as following TC1C initial value 2 256 TC1 interrupt interval time TC1 clock rate 5 TECHNOLOGY CO LTD Page 101 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 8 4 5 AUTO RELOAD REGISTER TC1 timer builds in auto reload function and TC1R register stores reload data When TC1C overflow occurs TC1C register is loaded data from TC1R register automatically Under TC1 timer counting status to modify TC1 interval time is to modify TC1R register not TC1C register New TC1C data of TC1 interval time will be updated after TC1 timer overflow occurrence loads new value to TC1C register But at the first time to setup TOM T
101. IGH SPEED 53 4 4 4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT essere 53 4 5 SYSTEM LOW SPEED CLOCK 54 416 eter pbi 54 4 7 SYSTEM CLOCK 55 4 8 SYSTEM C LOCE testi psec Re oed s eru m eod po dioe oi deese ende 55 SYSTEM OPERATION 58 5 LOVERVIEW EHI HOM 58 SANORMAL 59 5 3 SLOW 60 35 4 POWER DOWN MDOE tas Seiten DB 60 ta E de 61 5 6 OPERATING MODE CONTROL MACRO 62 35 2 ande tieu dam ie 63 5 7 l OVERVIEW 63 5 7 2 WAKEUP TIM E 63 5 7 3 PIW WAKBUPCONTROL REGISTER 64 4 65 6
102. INT1 TC1 P1 7 SCS 24 P4 0 AINO PO S UTX T1 23 P4 1 AIN1 2 2 22 P4 2 AIN2 P0 1 INT1 TC1 21 P4 3 AINS 20 P4 4 AIN4 1 7 5 5 19 P4 5 AIN5 1 6 5 18 4 6 6 P1 5 SDI 17 P4 7 AIN7 P1 4 5DO 24 P4 0 AINO 23 P4 1 AIN1 22 P4 2 AIN2 21 P4 3 AIN3 20 P4 4 AIN4 19 P4 5 AIN5 18 P4 6 AIN6 17 P4 7 AIN7 Oa ROM 8 19 gt 8 di gt eINMd LENIV Sd OINMd 6NIV L Sd SN8F27E64K AC field 5 28 Pin X SN8F27E64LK DC field SKDIP 28 Pin SN8F27E64S AC field SOP 28 Pin SN8F27E64LS DC field SOP 28 Pin SN8F27E64X AC field SSOP 28 Pin SN8F27E64LX DC field SSOP 28 Pin VSS 1 0 28 VDDL VSS 1 U 28 VDD XIN PO 6 2 27 VDD AVREFH XIN PO 6 2 27 VDD AVREFH 5 3 26 5 3 26 P4 1 AIN1 4 4 25 2 1 2 4 4 25 P4 2 AIN2 P0 S UTX T1 5 24 P4 3 AIN3 PO S UTX T1 5 24 P4 3 AIN3 PO 2 URX TC2 6 23 P4 4 AIN4 PO 2 URX TC2 6 23 P4 4 AIN4 PO 1 INT1 TC1 7 22 P4 5 AIN5 PO 1 INT1 TC1 7 22 P4 5 AIN5 PO O INTO TCO 8 21 P4 6 AIN6 PO O INTO TCO 8 21 P4 6 AIN6 P1 6 SCK 9 20 P4 7 AIN7 1 6 5 9 20 P4 7 AIN7 P1 5 SDI 10 19 P5 0 AIN8 P1 5 SDI 10 19 P5 0 AIN8 P1 4 SDO 11 18 P5 1 AIN9 PWMO P1 4 SDO 11 18
103. L OVERVIEW 65 6 2 INTERRUPT OPERATION nennen sese esent tags 65 6 3 INTEN INTERRUPT ENABLE REGISTER en nine nnns sestertia nitens 66 6 4 INTRQ INTERRUPT REQUEST REGISTBR 67 6 5 GIE GLOBAL INTERRUPT OPERATION 68 6 6 EXTERNAL INTERRUPT OPERATION 1 1 nnne ener 69 6 7 TO INTERRUPT 00002000 0 0 0 0 0 te esae ee tae tenus 70 6 8 TCO INTERRUPT 71 6 9 TC1 INTERRUPT OPERA UICHN 72 6 10 TC2 INTERRUPT OPERATION 73 6 11 TI INTERRUPT OPERATION secreti niiair e a adarei daa aa asasi e 74 555 PI REGEM DU IN PEE 75 6 13 STIO INTERRUPT OPERATION 76 6 14 UART INTERRUPT OPERATION n stet ease nite nn nes ea tae teens 77 6 15 MEEIPEINTBRRUPT OPERATION ede MEER 78 T IO PORT MEME EM E 79 1143 IEW 79 7 20 reete eere m HM 80 5 TECHNOLOGY CO LTD Page 4 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controlle
104. M register 5 TECHNOLOGY CO LTD Page 14 Version 1 4 BNO WY SN8F27E60 Series 8 Flash Micro Controller with Embedded ICE and ISP Bi direction I O pin shared with specific analog input function e g XIN ADC Pull Up Resistor Specific Analog x Function Control Bit m Pin gt I O Input Bus PnM Latch T O Output Bus Analog IP Input Terminal Some specific functions switch I O direction directly not through PnM register Bi direction I O pin shared with specific analog output function e g Pull Up Resistor Specific Analog Function Control Bit FoM B 4 DR P gt I O Input Bus PnM Output 5 Lath Output Bus Analog IP Output Terminal Some specific functions switch I O direction directly not through PnM register 5 TECHNOLOGY CO LTD Page 15 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP CENTRAL PROCESSOR UNIT CPU 2 1 PROGRAM MEMORY FLASH ROM 6K words FLASH ROM Address ROM Comment 0000 Heset vector Reset vector 0001H User program General purpose area 0007H 0008H WAKE Interrupt vector Interrupt vector 0009H INTO Interrupt vector 000AH INT1 Interrupt vector 000 Interrupt vector 000CH TCO Interrupt vector 000DH TC1 I
105. M2IDE software on Microsoft Windows platform The platform includes Smart Development Adapter SN8F27E65 Starter kit and M2IDE software to build a high speed low cost powerful and multi task development environment including emulator debugger and programmer To execute emulation is like run real chip because the emulator circuit integrated in SN8F27E65 to offer a real development environment SN8F27E65 Embedded ICE Emulator System SN8F27E65 Starter kit Modular Cable to USB Cable to PC Starter kit or gt Sonix Embedded ICE Sonix IDE C Studio Smart Development Adapter SN8F27E65 Embedded ICE Emulator includes Smart Development Adapter USB cable to provide communications between the Smart Development Adapter and a PC SN8F27E65 Starter Kit Modular cable to connect the Smart Development Adapter and SN8F27E65 Starter Kit or target board CD ROM with M2IDE software M2IDE V124 or greater SN8F27E65 Embedded ICE Emulator Feature Target s Operating Voltage 1 8V 5 5V Up to 6 hardware break points System clock rate up to 16MHz Fcpu 16mips Oscillator supports internal high speed RC internal low speed RC external crystal resonator and external RC N8F27E65 Embedded ICE Emulator Limitation EIDA and EICK pins are shared with GPIO pins In embedded ICE mode the shared GPI function can t work We strongly recommend planning the two pins as simple function which can be
106. MCU will be NOT wake up and still keep in power down mode SDA SCL BF SDA SCL MSPIRQ BF Wake up MSPWK o Clear MSPWK L Set FCPUMO MCU Power down mode Power Down L Normal Mode MSP Wake up Timing Diagram Address NOT Matched Receiving Address R W ACK zem Receiving Address R w o Receiving Data _ azYAe 5 aay aay A2 At ra rl 37 6 4 A1 ACK D7 De D5 04 D3 D2 21 Do 5 5 MSPIRQ ee rt Cleared by Software Read MSPBUF Wake up MSPWK LLL 1 MCU A Power down mode 39 Warm up 1 Normal mode OP code executing Mode L Clear MSPWK Set FCPUMO Power Down Normal mode MCU Wake up Clear MSPWK by Software Start Warm up MSP Wake up Timing Diagram Address Matched After into power down mode we need to disable MSP and then enable MSP to reset MSP function and re write the 12 slave address Example BOBSET BOBCLR NOP BOBSET MOV BOMOV FCPUMO FMSPENB FMSPENB A 0xnn MSPADR A Re write the 12 slave address again SONiX TECHNOLOGY CO LTD Page 151 Version 1 4 N 7 SN8F27E60 Series 5 NS 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 MSP function only work Normal mode wh
107. N Disable ADC interrupt service MOV A 10110000B ADM Enable P4 0 ADC input and ADC function MOV A 00000000B Set ADC converting rate 16 BOMOV ADR A BOBSET FADCIEN Enable ADC interrupt service BOBCLR FADCIRQ Clear ADC interrupt request flag BOBSET FGIE Enable GIE BOBSET FADS Start ADC transformation gt Example ADC interrupt service routine ORG 10H Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FADCIRQ Check ADCIRQ JMP ADCIRQ 0 exit interrupt vector BOBCLR FADCIRQ Reset ADCIRQ 522 ADC interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 75 Version 1 4 N N 7 SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 13 SIO INTERRUPT OPERATION When the SIO converting successfully the SIOIRQ will be set to 1 no matter the SIOIEN is enable or disable If the SIOIEN and the trigger event SIOIRQ is set to be 1 As the result the system will execute the interrupt vector If the SIOIEN 0 the trigger event SIOIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the SIOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation gt Example SIO interrupt request setup BOBSET FSIOI
108. N N M SN8F27E60 Series 5 a X 8 Bit Flash Micro Controller with Embedded ICE and ISP SN8F27E60 Series USER S MANUAL Version 1 4 SN8F27E65 SN8F27E64 SN8F27E62 SN8F27E65L SN8F27E64L SN8F27E62L 8 Bit Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY LTD Page 1
109. N6 0111 AIN7 1000 8 1001 AINY 1010 AIN10 1011 AIN11 X Note For P4 n and P5 n general purpose I O function users should make sure of P4 n and P5 n s ADC channel are disabled or P4 n and P5 n are automatically set as ADC analog input when GCHS 1 and CHS 3 0 point to P4 n and P5 n 5 TECHNOLOGY CO LTD Page 83 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP gt Example Set P4 1 to be general purpose input mode PACON 1 must be set as 0 Check GCHS and CHS 3 0 status BOBCLR FGCHS CHS 3 0 point to P4 1 CHS 3 0 0001B set GCHSz0 CHS 3 0 don t point to P4 1 CHS 3 0 0001B don t care GCHS status Clear PACON BOBCLR P4CON 1 Enable P4 1 digital function Enable P4 1 input mode BOBCLR P4M 1 Set P4 1 as input mode gt Example Set P4 1 to be general purpose output P4CON 1 must be set as 0 Check GCHS and CHS 3 0 status BOBCLR FGCHS If CHS 3 0 point to P4 1 CHS 3 0 0001B set GCHS 0 If CHS 3 0 don t point to P4 1 CHS 3 0 0001B don t care GCHS status Clear PACON BOBCLR 4 1 Enable 4 1 digital function Set P4 1 output buffer to avoid glitch BOBSET 4 1 Set P4 1 buffer as 1 BOBCLR 4 1 Set P4 1 buffer as 0 Enable P4 1 output mode BOBSET PAM 1 Set P4 1 as input mode 5 TECHNOLOGY CO LTD P
110. NA 3 RESET 3 1 OVERVIEW The system would be reset in three conditions as following Power on reset Watchdog reset Brown out reset External reset only supports external reset pin enable situation SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP When any reset condition occurs all system registers keep initial status program stops and program counter is cleared After reset status released the system boots up and program starts to execute from ORG 0 The POR WDT and RST flags indicate system reset status The system can depend on POR WDT and RST status and go to different paths by program 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG POR WDT RST STKOV DC Z Read Write R W RAN R W After reset 0 0 0 Bit 7 POR Power on reset and LVD brown out reset indicator 0 Non active 1 Reset active LVD announces reset flag Bit 6 WDT Watchdog reset indicator 0 Non active 1 Reset active Watchdog announces reset flag Bit 5 RST External reset indicator 0 Non active 1 Reset active External reset announces reset flag Finishing any reset sequence needs some time The system provides complete procedures to make the power on reset successful For different oscillator types the reset time is different That causes the VDD rise rate and start up time of different oscillator is not fixed RC type oscillator s sta
111. O Bus Active SCS pin SCSP 0 4 SCS SCSP 1 4 SIOBZ 5 TECHNOLOGY CO LTD Page 141 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP 11 3 SIOM MODE REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOM SENB START SRATE1 SRATEO MLSB SCKMD CPOL CPHA Read Write RAN R W RAN RAN R W RAN R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 4 Bit 3 Bit 2 Bit 1 Bit 0 SENB SIO function control bit 0 Disable SIO function SIO pins are GPIO 1 Enable SIO function GPIO pins are SIO pins SIO pin structure can be push pull structure and open drain structure controlled by P1OC register START SIO progress control bit 0 End of transfer 1 SIO transmitting SRATE1 0 SIO s transfer rate select bit These 2 bits workless when SCKMD 1 00 fcpu 01 32 10 fcpu 16 11 fcpu 8 MLSB MSB LSB transfer first 0 MSB transmit first 1 2 LSB transmit first SCKMD SIO s clock mode select bit 0 Internal Master mode 1 External Slave mode CPOL SCK idle status control bit 0 SCK idle status is low status 1 SCK idle status is high status CPHA The Clock Phase bit controls the phase of the clock on which data is sampled 0 Data receive at the first clock phase 1 Data receive
112. OH P5CON3 5 2 PSCON1 RW 0C8H OCOH ADB9 ADB8 ADB7 ADB6 ADBS ADB4 ADB3 ADB2 OCAH ADLEN ADCKSO ADB ADBO 08 082H 083 084 085 087 088 0898 08 090 O91H 0998 094 095 096H 097 098 O9CH O9DH O9EH O9FH OATH 0 4 5 0 6 0 7 OABH OADH OBIH OB2H OB4H OB5H 0 OB8H OBBH OBCH OBFH OCIH OC2H OC3H OC4H 0 5 OC6H OC7H OC8H OC9H 5 TECHNOLOGY CO LTD Page 27 Version 1 4 N N M SN8F27E60 Series S S 8 Bit Flash Micro Controller with Embedded ICE and ISP OCBH ADTS ADTSO ADT4 ADT3 ADT2 ADT ADTO RW PERAMCN PERAMCN ues nuns aw Pew 03H 8082 SCSEN SCSP Rw 5005 OE4H UTXEN UTXPEN UTXPS UTXBRK 2 UTXBZ 0 0 DA P S BF R
113. P 32 PIN 32 E1 CACC 1 16 zn TERR 1004 0 050typ NOR inch 0 155 3 937 1 650 41 91 0 600 BSC 15 24 BSC 0 545 13 843 0 130 3 302 0 650 16 51 7 5 TECHNOLOGY CO LTD Page 182 7 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 19 2 LOFP 32 PIN emm um 1 4 0 per EIN 4 LZ 5 _ 1 8 z a E B L L1 0 055 5 TECHNOLOGY CO LTD Page 183 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 19 3 QFN 5X5 32 PIN 1 1 yo hor 25 SEATING PLANE 0070000 NOTES C0 35X45 1 JEDEC OUTLINE N A 2 DIMENSION b APPLIES METALLIZED TERMINAL AND IS MEASURED BETWEEN 0 15mm AND 0 30mm FROM THE TERMINAL TIP IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE 1 TERMINAL THE DIMENSION b SHOULD BE MEASURED IN THAT RADIUS AREA 9 3 THE MINIMUM K VALUE OF 0 20 APPLIES 4 BILATERAL COPLANARITY ZONE APPLIES
114. P DIP 40 85 SN8F27E65LFB FLASH 27E65 LQFP 40 85 SN8F27E65LJB FLASH 27E65 QFN 40 85 C PB Free Package SN8F27E65LUB FLASH 27E65 S DIP 40 85 C PB Free Package SN8F27E64KB FLASH 27E65 SK DIP 40 85 C PB Free Package SN8F27E64SB FLASH 27E65 SOP 40 85 C PB Free Package SN8F27E64XB FLASH 27E65 SSOP 40 C 85 C PB Free Package SN8F27E64JB FLASH 27E65 QFN 40 85 C PB Free Package SN8F27E64LKB FLASH 27E65 SK DIP 40 85 C PB Free Package SN8F27E64LSB FLASH 27E65 SOP 40 C 85 C PB Free Package SN8F27E64LXB FLASH 27E65 SSOP 40 85 C PB Free Package SN8F27E64LJB FLASH 27E65 QFN 40 85 C PB Free Package SN8F27E62PB FLASH 27E65 P DIP 40 85 C PB Free Package SN8F27E62SB FLASH 27E65 SOP 40 C 85 C PB Free Package SN8F27E62LPB FLASH 27E65 P DIP 40 85 C PB Free Package SN8F27E62LSB FLASH 27E65 SOP 40 85 C PB Free Package SONiX TECHNOLOGY CO LTD Page 180 Version 1 4 8 Flash Micro Controller with Embedded ICE and ISP 18 4 DATECODE SYSTEM XX XXXXX Internal Use Day Month 1 January ont 2 February 9 September A October B November C December 03 2003 04 2004 05 2005 06 2006 Year 5 TECHNOLOGY CO LTD Page 181 Version 1 4 SN8F27E60 Series SONI IX D E 8 Flash Micro Controller with Embedded ICE and ISP 1 9 PACKAGE INFORMATION 19 1 P DI
115. P5 1 AIN9 PWMO P1 3 SCL 12 17 P5 2 AIN10 PWM1 P1 3 SCL 12 17 P5 2 AIN10 PWM1 P1 2 SDA 13 16 P5 3 AIN11 PWM2 P1 2 SDA 13 16 P5 3 AIN11 PWM2 P1 1 EIDA 14 15 P1 0 EICK P1 1 EIDA 14 15 P1 0 EICK 5 TECHNOLOGY CO LTD Page 11 Version 1 4 SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP N 7 SONIX SN8F27E64J AC field QFN 4x4 28 Pin e I SN8F27E64LJ DC field QFN 4x4 28 Pin I ir ir gt 2 gt lt lt lt gt QA gt c gt 2 gt lt gt lt 2 2 0 2 0 LJ tc gt lt gt lt 25 24 23 25 24 23 0 1 2 2 PO 1 INT1 TC1 21 P4 2 AIN2 20 P4 3 AIN3 19 P4 4 AINA 18 P4 5 AIN5 17 P4 6 AIN6 16 P4 7 AIN7 PO 1 INT1 TC1 PO 3 UTX T1 PO 2 URX TC2 21 P4 2 AIN2 20 P4 3 AINS 19 P4 4 AINA 18 P4 5 AIN5 17 P4 6 AIN6 16 P4 7 AIN7 P1 4 SDO 15 5 0 8 P1 4 SDO 15 1 8 8 9 10 11 12 13 14 8 9 10 11 12 13 14 uU WU VU 20 20 W VU UD VU U 20 U m fF o V Z gomms gt gt 253 2299222 Q lt o lt o N po SN8F27E62P AC
116. Pim ro Pa Ps PAUR ria ADM ADB Aon MSP MSP MSP SIOB URTX URRX URCR UTXD URXD EM STAT MSPM1 MSP 5 ROML ROMH RAML 2 2 1 25 5 REGISTER DESCRIPTION L Working HL addressing register Working register and ROM look up data buffer X Working and ROM address register RBANK RAM bank select register P1W Port 1 wakeup register PEDGE P0 0 P0 1 edge direction register URTX UART transmit control register URRX UART receive control register URCR UART baud rate control register UTXD UART transmit data buffer T1CH L T1 counting registers ADM ADC mode register ADR ADC resolution select register PEDGE P0 0 P0 1 0 2 edge direction register INTENO 1 Interrupt enable register PnM Port n input output mode register PnUR Port n pull up resister control register PCL Program counter TOC counting register TCnC TCn counting register TCnD TCn duty control register CPTCL H Capture timer counting registers MSPBUF MSP buffer register MSPADR MSP address register PECMD ISP command register PEROM ISP ROM address HL RAM HL indirect addressing index pointer STKP Stack pointer buffer 5 TECHNOLOGY
117. R W After reset 089H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W1 W1BIT7 W1BIT6 W1BIT5 W1BIT4 W1BITS3 W1BIT2 W1BIT1 W1BITO Read Write R W R W R W R W R W R W R W After reset 08AH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W2BIT7 W2BIT6 W2BIT5 W2BIT4 W2BIT3 W2BIT2 W2BIT1 W2BITO Read Write R W R W R W R W R W R W R W After reset 08 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W3 W3BIT7 W3BIT6 W3BIT5 W3BIT4 WS3BIT3 WS3BIT2 W3BIT1 W3BITO Read Write R W R W R W R W R W R W R W R W After reset 08 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WA WABIT7 WABIT6 WABIT5 W4BIT4 WABIT3 WABIT2 W4BIT1 WABITO Read Write R W R W R W R W R W R W R W R W After reset 08DH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W5 W5BIT7 W5BIT6 WBBIT5 W5BIT4 WBBIT3 WBBIT2 W5BIT1 W5BITO Read Write R W R W R W R W R W R W R W After reset 08 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W6 W6BIT7 WOBIT6 WOBIT5 WE6BIT4 6 WOBIT2 WE6BIT1 WOBITO Read Write R W R W R W R W R W R W R W R W After reset 08 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W7BIT7 W7BIT6 W7BIT5 W7BIT4 W7BIT3 W7BIT2 W7BIT1 W7BITO Read Write R W R W R W R W R W R W R W R W After reset Note 1 In assembly language situation WO W7 can be used as general working registers 2 In C language situati
118. ROM page location The address must be the head location of a page area e g 0x0080 0x0100 0x0180 0x1600 0x1680 and 0x1700 PEROML 7 0 and PEROMH 7 0 define the target starting address 15 0 of flash ROM Write the start address into PEROML and PEROMH registers set PECMD register to OxC3 and the system start to execute ISP flash ROM erase operation gt Example Use ISP flash ROM erase to clear 0x0080 0x00FF contents of flash ROM Set erased start address 0x0080 MOV A 0 80 BOMOV PEROML A Move low byte address 0x80 to PEROML MOV A 0x00 BOMOV PEROMH A Move high byte address 0x00 to PEROMH Clear watchdog timer MOV A 0X5A BOMOV WDTR A Start to execute ISP flash ROM erase operation MOV A 0XC3 Start to page erase BOMOV PECMD A NOP NOP Delay NOP The end of ISP flash ROM erase operation The two instructions make a short delay to let system stable after ISP flash ROM erase operation Note Don t execute ISP flash ROM erase operation for the first page and the last page or affect program operation SONiX TECHNOLOGY CO LTD Page 159 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 13 3 ISP FLASH ROM PROGRAM OPERATION ISP flash ROM program operation is to write data into flash ROM by program Program ROM doesn t limit written ROM address and length but limits 32 word density of one page
119. RT RX operation is started as start bit transmitted from master terminal 5 TECHNOLOGY CO LTD Page 138 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 1 SERIAL INPUT OUTPUT TRANSCEIVER SIO 11 1 OVERVIEW The SIO serial input output transceiver is a serial communicate interface for data exchanging from one MCU to one MCU or other hardware peripherals It is a simple 8 bit interface without a major definition of protocol packet or control bits The SIO transceiver includes three pins clock SCK data input SI and data output SO to send data between master and slaver terminals The SIO interface builds in 8 mode which are the clock idle status the clock phases and data fist bit direction The 8 bit mode supports most of SIO SPI communicate format The SIO features include the following Full duplex 3 wire synchronous data transfer Master SCK is clock output or Slave SCK is clock input operation MSB LSB first data transfer The start phase of data sampling location selection is 1 or 219 phase controlled register SCK SI SO are programmable open drain output pin for multiple salve devices application Two programmable bit rates Only in master mode End of Transfer interrupt 11 2 SIO OPERATION The SIOM register can control SIO operating function such as transmit receive clock rate data transfer direction SIO clock idle status
120. SF JP7 JP11 P4 0 PWMO gj ___ 5 2 peo p42 pas P42 3 4 3 2 5 98 95 8 PWM 8 C16 C17 C18 c19 PORTS d VSS 4 JP12 VDD VDD ol 1 250 of 5 P5 1 AVREFHAVBEFH 4 4 4 5 p4 6 5 0 ps1 ps2 psa 5 2 O3 3 P5 3 VDD AVREFH PORTS C20 C21 c23 C24 C25 C26 C27 0 tu 1 4 54822265 Siarter 42 0 2692 703 ml ARID HEU LED 02 03 2e mmm ym PLZAISPI7 24124315547 251953 PIOPLZBI4 015 40 2 4 46 2 e Q5 1 48 J1 DC 7 5V power adapter JP2 VDD power source is 5 0V or 3 3V or external power JP1 JP3 External power source SW1 Target power switch U3 SN8F27E65F real chip Sonix standard option D2 Power LED D3 MCU LED C16 C27 12 ch ADC capacitors SW2 External reset trigger source JP5 JP11 connector Y1 C14 C15 External crystal resonator oscillator components R4 C11 External RC type oscillator components JP12 VDD test pad and AVREFH connector 5 TECHNOLOGY CO LTD Page 172 Version 1 4 8 N 9 SN8F27E60 Series aS V 8 Bit Flash Micro Controller with Embedded ICE and ISP 16 3 EMULATOR DEBUGGER INSTALLATION Install the M2IDE Software V124 or gre
121. T FTOENB To enable TO timer Go into green mode GreenMode Declare GreenMode macro directly 5 TECHNOLOGY CO LTD Page 62 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 5 7 WAKEUP 5 7 1 OVERVIEW Under power down mode sleep mode or green mode program doesn t execute The wakeup trigger can wake the system up to normal mode or slow mode The wakeup trigger sources are external trigger PO P1 level change internal trigger TO timer overflow The wakeup function builds in interrupt operation issued IRQ flag and trigger system executing interrupt service routine as system wakeup occurrence Power down mode is waked up to normal mode The wakeup trigger is only external trigger PO P1 level change Green mode is waked up to last mode normal mode or slow mode The wakeup triggers are external trigger PO P1 level change and internal trigger TO timer overflow Wakeup interrupt function issues WAKEIRQ as system wakeup from power down mode or green mode If WAKEIEN is 1 meaning enable the wakeup event triggers program counter point to interrupt vector ORG 8 executing interrupt service routine X Note If wake up source is external interrupt source the WAKE bit won t be set and external interrupt IRQ bit is set The system issues external interrupt request and executes interrupt service routine 5 7 2 WAKEUP TIME When t
122. T1 timer MOV BOMOV A 0x00 1 Clear register Set T1 clock rate MOV BOMOV A 0nnn0000b T1M T1rate 2 0 bits Set T1CH T1CL registers for T1 Interval time MOV A value1 Set high byte first BOMOV T1CH A MOV A value2 Set low byte BOMOV T1CL A Clear T1IRQ BOBCLR FT1IRQ Enable T1 timer and interrupt function BOBSET FT1IEN BOBSET FT1ENB Enable T1 interrupt function Enable T1 timer 5 TECHNOLOGY CO LTD Page 119 Version 1 4 N 7 SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP T1 CAPTURE TIMER FOR CONTINUOUS SIGNAL MEASUREMENT CONFIGURATION Reset T1 timer CLR T1M Clear T1M register Set T1 clock rate and select enable T1 capture timer MOV A 0000 nnn is T1rate 2 0 for T1 clock rate selection BOMOV T1M m is T1 clock source control bit MOV A 000000mmb mm is CPTG 1 0 for T1 capture timer function selection BOMOV CPTM A CPTG 1 0 00b enable T1 capture timer CPTG 1 0 01b 10b 11b enable pulse width or cycle measurement Select capture timer high speed low speed mode BOBCLR FCPTMD CPT overflow mode Or BOBSET FCPTMD T1 overflow mode Clear T1CH T1CL CLR T1CH Clear high byte first CLR T1CL Clear low byte Set CPTCH CPTCL 16 bit capture timer for continuous signal measurement MOV A value1 Set high nibble first BOMOV CPTCH
123. TD Page 121 Version 1 4 N 7 SN8F27E60 Series 8 NS E 8 Flash Micro Controller with Embedded ICE and ISP Q 2 CHANNEL ANALOG TO DIGITAL CONVERTER ADC 9 1 OVERVIEW The analog to digital converter ADC is SAR structure with 12 input sources and up to 1024 step resolution to transfer analog signal into 10 bits digital buffers The ADC builds in 12 channel input source AINO AIN11 to measure 12 different analog signal sources controlled by CHS 3 0 and GCHS bits The ADC resolution can be selected 8 bit and 10 bit resolutions through ADLEN bit The ADC converting rate can be selected by ADCKS 1 0 bits to decide ADC converting time The ADC reference high voltage is AVREFH pin It is necessary to set P4 P5 as input mode without pull up resistor by program After setup ADENB and ADS bits the ADC starts to convert analog signal to digital data When the conversion is complete the ADC circuit will set EOC and ADCIRQ bits to 1 and the digital data outputs in ADB and ADR registers If the ADCIEN 1 the ADC interrupt request occurs and executes interrupt service routine when ADCIRQ 1 after ADC converting If ADC interrupt function is enabled ADCIEN 1 the system will execute interrupt procedure The interrupt procedure is system program counter points to interrupt vector ORG 0010H and executes interrupt service routine after finishing ADC converting Clear ADCIRQ by program is necessary in interrupt procedure ADCKS
124. TD Page 158 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 13 2 ISP FLASH ROM ERASE OPERATION ISP flash ROM erase operation is to clear flash ROM contents to blank status 1 Erasing ROM length is 128 word and has ROM page limitation ISP flash ROM erase ROM 15 as following ISP ROM ROM address bit0 bit6 hex 0000 0001 0002 0010 0011 0050 0051 0070 0071 007 007F This page includes reset vector and interrupt sector We strongly recommend to reserve the area not to do ISP erase 100 108 118 160 168 170 1780 This page includes ROM reserved area We strongly recommend to reserve the area not to do ISP erase ojojo ojojo i vo a i N a o o 6 tc ojo zu ur ISP flash ROM erase density is 128 word which limits erase page boundary The first 128 word of flash ROM 0x0000 0x007F includes reset vector and interrupt vectors related essential program operation and the last page 128 word of flash ROM 0x1780 0x17FF includes system reserved ROM area we strongly recommend do not execute ISP flash ROM erase operation in the two pages Flash ROM area 0x0080 0x177F includes 46 page for ISP flash ROM erase operation The first step to do ISP flash ROM erase is to address
125. TO THE K EXPOSED HEAT SINK SLUC AS WELL AS THE TERMINALS 26 08 0 030 0 750 0 001 0 020 0 008 0 203 0 010 0 250 0 20 5 5 00 5 0 20 5 5 00 5 0 02 5 0 50 5 0 016 0 400 02 2 MIN NOR MAX 134x134 MIL 5 TECHNOLOGY CO LTD Page 184 Version 1 4 N N 7 SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 19 4 S DIP 32 PIN BASE MET d 2221 1 WITH PLATING SECTION B B 0 173 4 40 0 130 3 30 0 060 1 52 0 018 0 46 0 039 5 1 00 5 0 010 0 25 1 102 28 00 0 350 8 90 0 07 5 1 778 5 0 4 5 10 16 5 5 TECHNOLOGY CO LTD Page 185 Version 1 4 N WW SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP 19 5 SK DIP 28 PIN SEATING PLANE 5 TECHNOLOGY CO LTD Page 186 Version 1 4 W BEN WAY SN8F27E60 Series S wy N 8 Bit Flash Micro Controller with Embedded ICE and ISP 19 6 SOP 28 PIN 1 1 dubHHHEg IMS 0 050typ 2 0 004max GAUGE PLANE SEATING PLANE
126. Transmit complete does not include the and stop bits MSPBUF is empty 12 3 MSP MODE REGISTER 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSPM1 WCOL MSPENB SLRXCKP MSPWK MSPC Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 7 WCOL Write Collision Detect bit Master Mode 0 No collision 1 A write to the SSPBUF register was attempted while the MSP conditions were not valid for a transmission to be started Slave Mode 0 No collision 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software Bit 6 PMSPOV Receive Overflow Indicator bit 0 No overflow 1 A byte is received while the SSPBUF register is still holding the previous byte SSPOV is a don t care in transmit mode SSPOV must be cleared in software in either mode must be cleared in software Bit 5 MSPENB MSP Communication Enable 0 Disables serial port and configures these pins as port pins 1 Enables serial port and configures SCL SDA as the source of the serial port pins Note MSP status register will be clear after MSP Disable So user should setting MSP register again before MSP Enable Ex BOBCLR FMSPENB CALL MSP init setting BOBSET FMSPENB Bit 4 CKP SCL Clock Priority Control bit In MSP Slave mode 0 Hold SCL keeping Low Ensure data setup tim
127. UMPING Users can jump around the multi address by either JMP instruction or ADD M A instruction M PCL to activate multi address jumping function Program Counter supports ADD M A ADC and BOADD instructions for carry to PCH when PCL overflow automatically For jump table or others applications users can calculate PC value by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value not change gt Example If PC 0323H PCH PCL 23H 0323H MOV A 28 BOMOV PCL A Jump to address 0328H 0328H MOV A 00H BOMOV PCL A Jump to address 0300H gt Example If PC 0323H PCH PCL 23H 0323H BOADD PCL A PCL PCL ACC the cannot be changed JMP AOPOINT IF ACC 0 jump to AOPOINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to 5 TECHNOLOGY LTD Page 33 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 2 2 5 H L REGISTERS The H and L registers are the 8 bit buffers There are two major functions of these registers Can be used as general working registers Can be use
128. Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP AMENDENT HISTORY Version Date Description VER 0 1 Oct 2009 rst issue VER 0 2 Dec 2009 VER 0 3 2009 VER 0 4 Jan 2010 VER 0 5 Feb 2010 Fi 1 2 1 2 1 2 3 1 2 VER 1 0 Jul 2010 1 2 3 1 2 3 4 5 1 1 1 VER 1 1 Jun 2011 VER 12 Jul 2011 VER 1 3 Jun 2012 VER 1 4 2013 Update electrical characteristic Modify development tool section Update electrical characteristic Modify UART section Update electrical characteristic Add PB Free part number Add QFN package type Fix SN8F27E65LF pin 31 32 VDD name Modify Wafer Form part number as S8F27E65W Update electrical characteristic Modify MSP section Modify QFN 4x4 package dimension Update ROM programming pin Modify QFN 4x4 package dimension Add AVREFH pin name in SN8F27E64 and SN8F27E62 Modify SN8F27E65 starter kit section Update electrical characteristic maximum rating Add SDIP package type Add the schematic of SN8F27E65 starter kit Modify ADC section 5 TECHNOLOGY CO LTD Page 2 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP Table of Content AMENDENTHISTOR Y ft 2 PRODUCT OVERVIEW C HR 8 Tel FEATURES
129. W VOLTAGE DETECTOR LVD VDD LVD Detect Voltage Power 1 l 1 VSS Power is below LVD Detect Voltage and System Reset lt t System Normal System Status system stop On Delay Time 5 TECHNOLOGY CO LTD Page 46 Version 1 4 N N M SN8F27E60 Series 6 NS 8 Flash Micro Controller with Embedded ICE and ISP The LVD low voltage detector is built in Sonix 8 bit MCU to be brown out reset protection When the VDD drops and is below LVD detect voltage the LVD would be triggered and the system is reset The LVD detect level is different by each MCU The LVD voltage level is a point of voltage and not easy to cover all dead band range Using LVD to improve brown out reset is depend on application requirement and environment If the power variation is very deep violent and trigger the LVD the LVD can be the protection If the power variation can touch the LVD detect level and make system work error the LVD can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section The LVD is three levels design 1 8V 2 4V 3 3V and controlled by LVD code option The 1 8V LVD is always enable for power on reset and Brown Out reset The 2 4V LVD includes LVD reset function and flag function to indicate VDD status function The 3 3V includes flag function to indicate VDD status flag function can be
130. Write R W RAN R W R W R W After reset 0 0 0 0 0 Bit 0 TOTB RTC clock source control bit 0 Disable TO clock source from 1 Enable Bit 6 4 2 01 TO timer clock source select bits 000 Fcpu 256 001 Fcpu 128 010 64 011 2 100 16 101 Fcpu 8 110 Fcpu 4 111 2 Bit 7 TOENB TO counter control bit 0 Disable TO timer 1 Enable TO timer Note TORATE is not available RTC mode The interval time is fixed at 0 5 sec 8 2 4 TOC COUNTING REGISTER TOC is TO 8 bit counter When TOC overflow occurs the TOIRQ flag is set as 1 and cleared by program The TOC decides TO interval time through below equation to calculate a correct value It is necessary to write the correct value to TOC register and then enable TO timer to make sure the first cycle correct After one TO overflow occurs the TOC register is loaded a correct value by program OB3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOC TOC7 TOC6 5 0 4 TOC3 TOC2 TOC1 TOCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TOC initial value is as following TOC initial value 256 TO interrupt interval time TO clock rate gt Example To calculation TOC to obtain 10ms TO interval time TO clock source is Fcp
131. X MSPSMT OEBH WCOL MSPOV MSPWK Rw OEFH LVD24 LVD33 81 2 STKPB STKPBO RW STKP OH A 87 12 57 10 7209 57 Rw _ 51 OF3H 567012 5 56 10 56 9 56 STKeH OF5H 557012 5 55 10 55 9 55 Rw _ 5 OF7H 542012 S4PCIO 54 9 S4PCB RW STK4H OFH amp 53 12 53 10 S3PCO S3PCB RW 5 orBH 52 12 SaPCt 2 10 5209 52 8 RW STK2H OFDH 81 12 SIPCIO 1209 51 8 RW orrH 507012 SOPCIO SOPCO SOPCB8 Rw X STKOH 1 To avoid system error make sure to put all the 0 and 1 as it indicates in the above table 2 All of register names had been declared in SNGASM assembler 3 One bit name had been declared in SN8ASM assembler with prefix code 4 bObset bObclr bset bclr instructions are only available to the R W registers 5 TECHNOLOGY CO LTD Page 28 Version 1 4 8 Flash Micro Controller with Embedded ICE and ISP 2 2 2 ACCUMULATOR The is an 8 bit data register responsible for transferring or manipulating data between ALU and data memory If the r
132. Y CO LTD Page 118 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTCL CPTC7 CPTC6 CPTC5 CPTC4 CPTC3 CPTC2 CPTC1 CPTCO Read Write RAN R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTCH CPTC15 CPTC14 CPTC13 CPTC12 CPTC11 CPTC10 CPTC9 CPTC8 Read Write R W R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 The capture timer counter length is 16 bit and points to CPTCH and CPTCL registers The timer counter is double buffer design The core bus is 8 bit so access 16 bit data needs a latch flag to avoid the transient status affect the 16 bit data mistake occurrence Under write mode the write CPTCL is the latch control flag Under read mode the read CPTCL is the latch control flag So write 16 bit counter is to write CPTCH first and then write CPTCL The 16 bit data is written to 16 bit counter buffer after executing writing CPTCL Read 16 bit counter is to read CPTCL first and then read CPTCH The 16 bit data is dumped to CPTCH CPTCL after executing reading CPTCL Read capture timer counter buffer sequence is to read CPTCL first and then read CPTCH Write capture timer counter buffer sequence is to write CPTCH first and then write CPTCL 8 6 7 T1 TIMER OPERATION EXPLAME T1 TIMER CONFIGURATION Reset
133. a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 9 4 ADC OPERATION DESCRIPTION AND NOTIC 9 4 1 ADC SIGNAL FORMAT ADC sampling voltage range is limited by high low reference voltage The ADC low reference voltage is Vss and not changeable The ADC high reference voltage is AVREFH pin ADC reference voltage range limitation is ADC high reference voltage low reference voltage 2V ADC low reference voltage is Vss OV So ADC high reference voltage range is 2V Vdd The range is ADC external high reference voltage range e ADC Internal Low Reference Voltage OV ADC External High Reference Voltage 2V Vdd ADC sampled input signal voltage must be from ADC low reference voltage to ADC high reference If the ADC input signal voltage is over the range the ADC converting result is error full scale or zero ADC Low Reference Voltage x ADC Sampled Input Voltage x ADC High Reference Voltage 9 4 2 ADC CONVERTING TIME The ADC converting time is from ADS 1 Start to ADC convert to EOC 1 End of ADC convert The converting time duration is depend on ADC resolution and ADC clock rate 10 bit ADC s converting time is 1 ADC clock 4 14 sec and the 8 bit ADC converting time is 1 ADC clock 4 12 sec ADC clock source is Fcpu and includes Fcpu 1 2 8 and Fcpu 16 controlled by ADCKS 1 0 bits The ADC converting time affects ADC performance If input high rate analog signal it is necessary to select a hi
134. able function This macro will check the ROM boundary and move the jump table to the right position automatically The side effect of this macro maybe wastes some ROM size gt Example If jump table crosses over ROM boundary will cause errors A MACRO VAL IF 1 18 OXFFOO VAL 18 OXFFOO JMP OXFF ORG OXFF ENDIF ADD PCL A ENDM Note VAL is the number of the jump table listing number 5 TECHNOLOGY LTD Page 22 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP gt Example JMP_A application in SONIX macro file called BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 number of the jump table listing is five JMP AOPOINT 0 jump to AOPOINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP ASPOINT 3 jump to JMP A4POINT ACC 4 jump to A4POINT If the jump table position is across a ROM boundary OxOOFF 0x0100 the JMP_A macro will adjust the jump table routine begin from next RAM boundary 0 0100 gt Example JMP_A operation Before compiling program ROM address BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five OXO00FD JMP AOPOINT ACC 0 jump to AOPOINT A1POINT ACC 1 jump t
135. age 84 Version 1 4 SN8F27E60 Series SONIX D D E 8 Flash Micro Controller with Embedded ICE and ISP 7 6 OPEN DRAIN REGISTER 2 1 0 1 7 built in open drain function These pins must be set as output mode when enable open drain function Open drain external circuit is as following MCU1 Pull up Ressto Open drain Open drain pin MCU2 The pull up resistor is necessary Open drain output high is driven by pull up resistor Output low is sunken by MCU s pin 09CH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Read Write E R W R W After reset 0 0 Bit 1 0 2 P0 2 open drain control bit 0 Disable open drain mode 1 Enable open drain mode 09DH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P10C P170C 16 P150C P140C P130C 120 P110C P100C Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 10 17 P1 0 P1 7 open drain control bit 0 Disable open drain mode 1 Enable open drain mode gt Example Enable P1 0 to open drain mode and output high BOBSET P1 0 Set P1 0 buffer high BOBSET P10M Enable P1 0 output mode BOBSET P100C Enable P1 0 open drain function gt Example Disable open drain mode BOBCLR P100C Disable P1 0 open drain functi
136. ain and start down counter SEN bit will be clear automatically when MRG overflow the MRG is suspend leaving SDA line held low and START condition is complete 12 8 3 1WCOL Status Flag If user write to MSPBUF when START condition processing then WCOL is set and the content of MSPBUF data is un changed the writer doesn t occur _ Set S bit E MSPSTAT 3 Write SEN here Complete SRART signal SDA 1 Tuwew Hardware clear SEN bit SCL 1 Tw gt Set MSPIRQ bit SDA 1st bit 2nd bit Write MSPBUF here SCL S Ture Ture START Condition Timing Diagram 12 8 4 MSP Master mode Repeat START Condition When MSP logic module is idle and RSEN set to 1 Repeat Start progress occurs RSEN set and SCL pin is sampled low MSPADR 6 0 data reload to MSP rate generator and start down counter The SDA pin is release to high in one MSP rate generate counter When the MRG is overflow if SDA is sampled high SCL will be brought high When SCL is sampled high MSPADR reload to MRG and start down counter SDA and SCL must keep high one Ture period In the next Ture period SDA will be brought low when SCL is sampled high then RSEN will clear automatically by hardware and MRG will not reload leaving SDA pin held low Once detect SDA and SCL occur START condition the S bit will be set MSPSTAT 3 MSPIRQ will not set until MRG overflow 1 While any other event is p
137. al mode after wake up If inserting green mode from slow mode the system insets to slow mode after wake up The green mode wake up sources are PO P1 level change trigger and unique time overflow After system wake up from power down mode the WAKE bit set as 1 and cleared by program If wake up source is external interrupt source the WAKE bit won t be set and external interrupt IRQ bit is set The system issues external interrupt request and executes interrupt service routine If the function clock source is system clock the functions are workable as enabled and under green mode e g Timer PWM event counter But the functions doesn t has wake up function Note Sonix provides GreenMode macro to control green mode operation It is necessary to use GreenMode macro to control system inserting green mode The macro includes three instructions Please take care the macro length as using BRANCH type instructions e g 0150 bts1 bObtsO bObts1 ins incms decs decms cmprs jmp or the routine would be error 5 TECHNOLOGY LTD Page 61 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 5 6 OPERATING MODE CONTROL MACRO Sonix provides operating mode control macros to switch system operating mode easily Macro Description SleepMode The system insets into Sleep Mode Power Down Mode GreenMode The system inserts into Green Mod
138. and clock control phase and starting this circuit This SIO circuit will transmit or receive 8 bit data automatically by setting SENB and START bits in SIOM register The SIO data buffer is double buffer design When the SIO operating the SIOB register stores transfer data and one internal buffer stores receive data When SIO operation is successfully the internal buffer reloads into SIOB register automatically The SIO 8 bit counter and SIOR register are designed to generate SIO s clock source with auto reload function The 3 bit counter can monitor the operation of SIO and announce an interrupt request after transmitting receiving 8 bit data After transferring 8 bit data this circuit will be disabled automatically and re transfer data by programming SIOM register CPOL bit is designed to control SIO clock idle status CPHA bit is designed to control the clock edge direction of data receive CPOL and CPHA bits decide the SIO format The SIO data transfer direction is controlled by MLSB bit to decide MSB first or LSB first SENB MLSB Y SENB SENB SCLKMD SIO Time Out SENB SCSP SCSEN SCLKMD 1 Auto Reload SIOR Register SIO Interface Structure Diagram CPUM1 0 Srate1 0 SONiX TECHNOLOGY CO LTD Page 139 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP The SIO supports 8 mode format controlled by MLSB CPOL and CPHA bits The edge dir
139. and oscillator operation Only internal regulator actives to keep all control gates status register status and SRAM contents The power down mode is waked up by PO P1 hardware level change trigger PO wake up function is always enables and P1 wake up function is controlled by P1W register Any operating modes into power down mode the system is waked up to normal mode Inserting power down mode is controlled by CPUMO bit of OSCM register When CPUMO 1 the system inserts into power down mode After system wake up from power down mode the CPUMO bit is disabled zero status automatically and the WAKE bit set as 1 The program stops executing and full functions are disabled All oscillators including external high speed oscillator internal high speed oscillator and internal low speed oscillator stop The system inserts into normal mode after wake up from power down mode The power down mode wake up source is PO and P1 level change trigger After system wake up from power down mode the WAKE bit set as 1 and cleared by program If wake up source is external interrupt source the WAKE bit won t be set and external interrupt IRQ bit is set The system issues external interrupt request and executes interrupt service routine X Note If the system is in normal mode to set STPHXz1 to disable the high clock oscillator The system is under no system clock condition This condition makes the system stay as power down mode and can b
140. and the execution error the watchdog timer can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and the power is still dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal range Watchdog timer application note is as following Reduce the system executing rate If the system rate is fast and the dead band exists to reduce the system executing rate can improve the dead band The lower system rate is with lower minimum operating voltage Select the power voltage that s no dead band issue and find out the mapping system rate Adjust the system rate to the value and the system exits the dead band issue This way needs to modify whole program timing to fit the application requirement External reset circuit The external reset methods also can improve brown out reset and is the complete solution There are three external reset circuits to improve brown out reset including Zener diode reset circuit Voltage bias reset circuit and External reset IC These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and
141. any LVD reset LVD24 LVD33 flags are cleared 2 The voltage level of LVD 2 4V or 3 3V is for design reference only Don t use the LVD indicator as precision VDD measurement 5 TECHNOLOGY CO LTD Page 47 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 3 4 3 BROWN OUT RESET IMPROVEMENT How to improve the brown reset condition There are some methods to improve brown out reset as following LVD reset Watchdog reset Reduce the system executing rate External reset circuit Zener diode reset circuit Voltage bias reset circuit External reset IC 1 The Zener diode reset circuit Voltage bias reset circuit and External reset IC can completely improve the brown out reset DC low battery and AC slow power down conditions 2 For AC power application and enhance EFT performance the system clock is 4MHz 4 1 mips and use external reset Zener diode reset circuit Voltage bias reset circuit External reset IC The structure can improve noise effective and get good EFT characteristic Watchdog reset The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear at one point of program Don t clear the watchdog timer in several addresses The system executes normally and the watchdog won t reset system When the system is under dead band
142. application 3 6 EXTERNAL RESET CIRCUIT 3 6 1 Simply RC Reset Circuit R1 47K ohm 100 ohm This is the basic reset circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing difference Note The reset circuit is no any protection against unusual power or brown out reset 5 TECHNOLOGY CO LTD Page 49 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 3 6 2 Diode amp RC Reset Circuit R1 47K ohm 100 ohm This is the better reset circuit The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal The reset circuit has a simply protection against unusual power The diode offers a power positive path to conduct higher power to VDD It is can make reset pin voltage level to synchronize with VDD voltage The structure can improve slight brown out reset condition Note The R2 100 ohm resistor of Simply reset circuit and Diode amp RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over stress EOS 3 6 3 Zener Diode Reset Circuit R1 33K ohm 40K ohm The zener diode rese
143. at the second clock phase Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOC SIOBZ SCSEN SCSP Read Write R W R W After reset Bit 2 Bit 1 Bit 0 5 TECHNOLOGY CO LTD SIOBZ SIO operating status flag 0 SIO is idle or end of processing 1 SIO is busy and processing SCSEN SIO chip selection function control bit 0 Disable chip selection function SCS pin keeps and returns to GPIO function 1 Enable chip selection function SCS pin transmits SIO chip selection pin when SCKMD 1 or keeps GPIO mode SCSP SIO chip selection direction control bit 0 Idle low and high active 1 Idle high and low active Page 142 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP Because SIO function is shared with GPIO The following table shows the SIO pin mode mode behavior and setting when SIO function enable and disable 1 510 Function Enable SCKMD 1 GPIO will change to Input mode automatically no matter what SIO source External clock PnM setting SCKMD 0 GPIO will change to Output mode automatically no matter what SIO source Internal clock PnM setting GPIO must be set as Input mode in PnM or the SIO function will be abnormal SIO Transmitter Receiver GPIO will change to Output mode automatically no matter what PnM setting SCSEN 1 SCKMD 1
144. ater Connect Smart Development Adapter with PC plugging in USB cable USB Cable to PC gt Sonix Embedded ICE Sonix IDE C Studio Smart Development Adapter X Attach the modular cable between Smart Development Adapter and SN8F27E65 Starter kit or target Embedded ICE 4 wire Interface SN8F27E65 Real Chip po Modular Cable to Starter kit or Application Target Board Target Board SN8F27E65 Starter kit Modular Cable to Starter kit or Target Board Sonix Embedded ICE Sonix Embedded ICE Smart Development Adapter Smart Development Adapter Connect the power supplier to SN8F27E65 Starter kit or target and turn off the power Open M2IDE software and load firmware program A project or a file EE M2ASM 091016 Proj D programitest code SWRF27E65 0_toprle_15_16 PRI 15 16 ASM Yew Debug io toggle 15 16 51 SORiX Template Code for SN8F27E63 st CHIP 5 8 27 65 2 For EU Chip select 5 to use all function NOLIST INCLUDESTD MACROY M INCLUDESTO ukoo 05 1 Temporary buffer For main loop 05 1 05 1 FaeVev 9 4 a Ie Debug log Find in Files 1 Find 21 Resty La 1 601 NUM Turnon the power switch of SN8F27E65 Starter kit or target Embedded ICE emul
145. ator platform is installed and start to execute debugger E 2 091016 Proj D program test code SNBFZ7E65 i0_toggle_15_16 PR4 15_16 ex E Yev Debes Quy Hadow ax 51215 49 xui gt 10401440 22 E 3E counter 05 1 5 addbuFt 95 1 Mane Value addbur2 05 1 a B 10110000 PFLAGBUF 05 1 TX spot Pen 85 3 PFLAG B 10001000 05 1 05 1 Key equ 15 t 6 00 n z CODE m sme ORG Code section start jmp Reset iReset vector Address to 7 are reserved ORG jap 158 2S Reset mov RQBUZER sInitial stack pointer and lt b nov STKP R 14154816 global interrupt 8 A 860A Ree Toe 00 00 00 00 5 Nane Value 5 08 80 80 00 w rc 80 Debug 14 5 RAMZ ROM wordt Woah 20 NUM 5 TECHNOLOGY CO LTD Page 173 Version 1 4 5 8 27 60 Series 8 Flash Micro Controller with Embedded ICE and ISP 16 4 PROGRAMMER INSTALLATION Setup emulator debugger environ
146. aving mode The external event counter input external interrupt function is also disabled when TC1 event counter function enabled and the bit keeps 0 status The event counter usually is used to measure external continuous signal rate e g continuous pulse R C type oscillating signal These signal phase don t synchronize with MCU s main clock Use TC1 event to measure it and calculate the signal rate in program for different applications External Input Signel 0x00 TC1IRQ TC1 timer overflows TC1IRQ set as 1 Reload TC1C from TC1R automatically is cleared by program 8 4 8 PULSE WIDTH MODULATION PWM PWM is duty cycle programmable design to offer various PWM signals When TC1 timer enables and PWM1OUT bit sets as 1 enable PWM output the PWM output pin P5 2 outputs PWM signal One cycle of PWM signal is high pulse first and then low pulse outputs register controls the cycle of PWM and TC1D decides the duty high pulse width length of PWM TC1C initial value is TC1R reloaded when TC1 timer enables and TC1 timer overflows When TC1C count is equal to TC1D the PWM high pulse finishes and exchanges to low level When TC1 overflows TC1C counts from OxFF to 0x00 one complete PWM cycle finishes The PWM exchanges to high level for next cycle The PWM is auto reload design to load TC1C from TC1R automatically when
147. baud rate clocks If YART baud rate is 250000bps the break pocket period is 100us UART TX Break Pocket Period 25 UART Baud Rate sec RX Break Pocket UART receives break pocket will get a frame error signal because the data period is longer than typical UART duration UART can t receive a complete data pocket After receiving a UART pocket the break pocket is still output low UART issues frame error flag UFMER 1 and URXIRQ Maybe the parity bit is error in parity mode UART changes to initial status until detecting next start bit 5 TECHNOLOGY CO LTD Page 133 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 10 6 ABNORMAL POCKET The abnormal pocket occurs in UART RX mode Break pocket is one abnormal pocket of the UART architecture The abnormal pocket includes Stream period error start bit error stop bit error When UART receives abnormal pocket the UFMER bit will be set 1 and UART issues URXIRQ The system finds the abnormal pocket through firmware UART changes to initial status until detecting next start bit Start bit is error we UART check the start bit is error and issue UFMER flag but the UART still finishes receiving the pocket Start bit is error URX Pin Start oro X ona X ons X ons P UART check the stop bit is error and issue UFMER flag but the UART still finishes receiving t
148. by Software Cleared by Software Software 1 set MSPIRQ at the end of t Acknowledge sequence 1 Last bit is shifted into MSPSR Write MSPBUF MSPBUF is pot read E is aii MSPBUF is still full MSPOVket 1 BF MSPOV MSP Master Receiving Mode Timing Diagram 5 TECHNOLOGY CO LTD Page 157 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 1 3 IN SYSTEM PROGRAM FLASH ROM 13 1 OVERVIEW The SN8F27E65 MCU integrated device feature in system programmable ISP FLASH memory for convenient upgradeable code storage The FLASH memory may be programmed via the 8 bit programming interface or by application code The SN8F27E65 provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory ISP Flash ROM provided user an easy way to storage data into Flash ROM The ISP concept is memory mapping idea that is to move RAM buffer to flash ROM Choice ROM RAM address and executing ROM programming command PECMD after programming words which controlled by PERAMCNT PERAML PERAMONT data will be programmed into address PEROML PEROMH RAM byte Flash ROM word RAM Address bit ROM Address bit15 bit8 bit7 DATAO 1 2 gt DATAN 1 During Flash program or erase operati
149. ce BOBCLR 2 Disable TC2 timer MOV A 10H TC2M Set 2 clock 64 MOV A 74 Set TC2C initial value 74H BOMOV TC2C A Set TC2 interval 10 ms BOBSET FTC2IEN Enable TC2 interrupt service BOBCLR FTC2IRQ Clear TC2 interrupt request flag BOBSET FTC2bENB Enable TC2 timer BOBSET FGIE Enable GIE Example TC2 interrupt service routine ORG Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 2 Check TC2IRQ JMP EXIT INT TC2IRQ 0 exit interrupt vector BOBCLR FTC2IRQ Reset TC2IRQ MOV 74 2 2 522 TC2 interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 73 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 11 1 INTERRUPT OPERATION When the counter occurs overflow the T1IRQ will be set to 1 however the is enable or disable If the T1IEN 1 the trigger event will make the T1IRQ to be 1 and the system enter interrupt vector If the T1IEN 0 the trigger event will make the T1IRQ to be 1 but the system will not enter interrupt vector Users need to care for the operation under multi interrupt situation gt Example T1 interrupt request setup
150. ce routine When RETI is executed to leave interrupt operation RBANK register is reloaded and RAN bank returns to last condition Sonix provides Bank 0 type instructions e g bOmov bObts1 bObset to control Bank 0 RAM in non zero RAM bank condition directly gt Example Access Bank 0 RAM in Bank 1 condition Move Bank 0 RAM value to Bank 1 RAM WK01 Bank 1 RBANK 1 BOMOV Use Bank 0 type instruction to access Bank 0 RAM MOV Note 1 For multi bank RAM program it is not easy to control RAM Bank selection Users have to take care the RBANK condition very carefully especially for interrupt service routine The system won t save the RBANK and switch RAM bank to Bank 0 so these controls must be through program It is a good to use Bank 0 type instruction to process the situations 2 The 190H 191H of RAM address doesn t support directly addressing mode to access RAM but support indirectly addressing mode HL YZ 5 TECHNOLOGY CO LTD Page 25 Version 1 4 SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP SONI IX 2 2 1 SYSTEM REGISTER 2 2 1 1SYSTEM REGISTER TABLE 1 15151715 10 80 11 8 z Y wo wi we we wa ws we wr Pot wora _ INTENO INTENT Pooc Proc Piw PEDGE
151. citor first and then O 1uF capacitor B These capacitors are set between AVREFH pin and VSS pin and must be on the side of the AVREFH pin as possible Don t connect the capacitor s ground pin to ground plain directly and must be through VSS pin 5 TECHNOLOGY CO LTD Page 129 Version 1 4 NONA 1 0 Universal Asynchronous SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP Receiver Transmitter UART 10 1 OVERVIEW The UART interface is an universal asynchronous receiver transmitter method The serial interface is applied to low speed data transfer and communicate with low speed peripheral devices The UART transceiver of Sonix 8 bit MCU allows RS232 standard and supports one byte data length The transfer format has start bit 8 bit data parity bit and stop bit Programmable baud rate supports different speed peripheral devices UART pins support push pull and open drain structures controlled by register The UART features include the following Full duplex 2 wire asynchronous data transfer Programmable baud rate 8 bit data length Odd and even parity bit End of Transfer interrupt Support DMX512 protocol Support break pocket function Support wide range baud rate URXPS URXPEN URXM gt URRXD1 8 bit Buf
152. ck is high clock 1 Slow mode System clock is internal low clock Bit 4 3 CPUM 1 0 CPU operating mode control bits 00 normal 01 sleep power down mode 10 green mode 11 reserved STPHX bit controls internal high speed RC type oscillator and external oscillator operations When STPHX 0 the external oscillator or internal high speed RC type oscillator active When STPHX 1 the external oscillator or internal high speed RC type oscillator are disabled The STPHX function is depend on different high clock options to do different controls 16M STPHX 1 disables internal high speed RC type oscillator STPHX 1 disables internal high speed RC type oscillator and external 32768Hz crystal keeps oscillating e RC 4M 12M 32K STPHX 1 disables external oscillator 5 TECHNOLOGY CO LTD Page 54 Version 1 4 SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP SON IX 4 7 SYSTEM CLOCK MEASUREMENT Under design period the users can measure system clock speed by software instruction cycle Fcpu This way is useful in RC mode gt Example Fcpu instruction cycle of external oscillator BOBSET 0 Set P0 0 to be output mode for outputting Fcpu toggle signal BOBSET BOBCLR B Output Fcpu toggle signal in low speed clock mode Measure the Fcpu frequency by oscilloscope Note D
153. count external clock number to implement measure application TC2 also builds in duty cycle programmable PWM The PWM cycle and resolution are controlled by TC2 timer clock rate TC2R and TC2D registers so the PWM with good flexibility to implement IR carry signal motor control and brightness adjuster The main purposes of the TC2 timer are as following 8 8 programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency Interrupt function TC2 timer function supports interrupt function When TC2 timer occurs overflow the TC2IRQ actives and the system points program counter to interrupt vector to do interrupt sequence A Event Counter The event counter function counts the external clock counts Duty cycle programmable PWM The PWM is duty cycle programmable controlled by TC2R and TC2D registers Green mode function All TC2 functions timer PWM event counter auto reload keep running in green mode and no wake up function TC2 Rate 1 128 2 50 Load TC2CKS1 TC2ENB TC2C TC2 Time Out 8 Bit Binary Up Counting Counter PWM2OUT 5 3 2 Schmitter Trigger CPUMO 1 TC2D Data Buffer 5 TECHNOLOGY CO LTD Page 106 Version 1 4 N N M SN8F27E60 Series O 8 Flash Micro Controller with Embedded ICE and ISP 8 5 2 TC2 TIMER OPERATION TC2 timer is controlled by
154. ction pin Schmitt trigger structure as input mode Built in pull up resisters P5 2 AIN10 PWM1 10 ADC channel 10 input pin PWM1 PWM 1 output pin P5 3 AIN1 1 P5 3 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters PWM2 lO 11 ADC channel 11 input pin PWMe2 PWM 2 output pin 1 5 PIN CIRCUIT DIAGRAMS Normal bi direction pin Pull Up Resistor PnM xe PnUR Pin gt Input Bus PnM Output 65 5 Latch I O Output Bus Bi direction I O pin shared with specific digital input function e g INTO event counter SIO MSP UART Pull Up Resistor Specific Input Function Control Bit PnM PnUR Specific Input Bus Pin gt IO Input Bus PnM Output 4 5 5 Output Bus Specific Output Function Control Bit Some specific functions switch I O direction directly not through PnM register Bi direction I O pin shared with specific digital output function e g PWM SIO MSP UART Pull Up Resistor PnM D PnUR Pin gt IO Input Bus PnM Output Latch lt Output Bus e Specific Output Bus Specific Output Function Control Bit Specific Output Function Control Bit Some specific functions switch I O direction directly not through Pn
155. d 32K oscillator when TOTB 1 RTC function is only available in High CIk code option IHRC_RTC A Green mode function TO timer keeps running in green mode and wakes up system when TO timer overflows TO Rate 2 256 Load TOC Value by Program TOC 8 Bit Binary Up Counting Counter TOIRQ Interrupt Flag TO timer overflow TOENB RTC mode the TO interval time is fixed at 0 5 sec and TOC is 256 counts 5 TECHNOLOGY LTD Page 88 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 8 2 2 TO Timer Operation TO timer is controlled by TOENB bit When TOENB O TO timer stops When TOENB 1 TO timer starts to count TOC increases 1 by timer clock source When TO overflow event occurs TOIRQ flag is set as 1 to indicate overflow and cleared by program The overflow condition is TOC count from full scale OxFF to zero scale 0x00 TO doesn t build in double buffer so load TOC by program when TO timer overflows to fix the correct interval time If TO timer interrupt function is enabled TOIEN 1 the system will execute interrupt procedure The interrupt procedure is system program counter points to interrupt vector ORG 000BH and executes interrupt service routine after TO overflow occurrence Clear TOIRQ by program is necessary in interrupt procedure TO timer can works in normal mode slow mode and gr
156. d as RAM data pointers with HL register 081H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBITO Read Write R W R W R W R W R W R W R W After reset 080 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBITO Read Write R W R W R W R W R W R W R W After reset Example want to read data from RAM address 20H of 0 it can use indirectly addressing mode to access data as following BOMOV H 00H To set RAM bank 0 for H register BOMOV L 20H To set location 20H for L register BOMOV A HL To read a data into ACC Example Clear general purpose data memory area of bank 0 using HL register CLR H H 0 bank 0 BOMOV L 07FH L 7FH the last address of the data memory area CLR HL BUF CLR Clear HL to be zero DECMS L L 1 if L 0 finish the routine JMP CLR HL BUF Not zero CLR HL END CLR End of clear general purpose data memory area of bank 0 5 TECHNOLOGY CO LTD Page 34 Version 1 4 NONA 2 2 6 X REGISTERS SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP X register is an 8 bit buffer and only general working register purpose Can be used as general working
157. d no wake up function TCO Rate 1 128 50 TCOCKS1 gt TCO Time Out 8 Bit Binary Up Counting Counter PWMOOUT 1 TCOD Data Buffer 5 TECHNOLOGY CO LTD Page 92 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 8 3 2 TCO TIMER OPERATION TCO timer is controlled by TCOENB bit When 0 TCO timer stops When TCOENB 1 TCO timer starts to count Before enabling TCO timer setup TCO timer s configurations to select timer function modes e g basic timer interrupt function TCOC increases 1 by timer clock source When TCO overflow event occurs TCOIRQ flag is set as 1 to indicate overflow and cleared by program The overflow condition is TCOC count from full scale OxFF to zero scale 0x00 In difference function modes TCOC value relates to operation If TCOC value changing effects operation the transition of operations would make timer function error So TCO builds in double buffer to avoid these situations happen The double buffer concept is to flash TCOC during TCO counting to set the new value to TCOR reload buffer and the new value will be loaded from TCOR to TCOC after TCO overflow occurrence automatically In the next cycle the TCO timer runs under new conditions and no any transitions occur The auto reload function is no any control interface and always actives as TCO enables
158. ddress of ISP 1 DATA1 Y41 2 DATA2 gt 2 3 DATAS Y 3 The end of the page DATAGS DATADA The end address of ISP X 63 DATA63 Case 2 16 word ISP program RAM buffer length is 32 byte PERAMCNT 7 3 01111b meets 16 word of flash ROM The page address of flash ROM is Y Y 31 but the start address isn t the head of the page Define the start address is 10 and set to PEROML PEROMH registers The programmed flash ROM area is 10 25 addresses RAM byte Flash ROM word RAM Address ROM Address 32 byte bit7 bitO 32 word 20115 8 bit7 bitO X DATAO Y The head of the page 1 DATA1 Y44 2 DATA2 gt 3 10 DATA1 The start address of ISP ERE 11 DATA3 30 m m 31 1 25 DATA31 The end address of ISP Y 30 31 The end of the page Case 3 Follow above case and change the ROM start address to 20 The programmed flash ROM area is Y 20 Y 35 addresses The ROM range is out of the page boundary After ISP flash ROM operation the last 4 word data can t be written into flash ROM successfully The programming length is over ISP flash ROM program page boundary the hardware immediately stops programming flash ROM after finishing programming the last word Y 31 of the ROM page RAM byte Flash ROM word HM 22 bit7 bito ROM Address 45
159. de option IHRC_RTC 32K 4M 12M High_CLK code option IHRC_RTC RC 32K 4M 12M Embedded ICE mode Embedded ICE mode MSPENB 1 MSPENB 1 SENB 1 SENB 1 SENB 1 SENB 1 ADENB 1 GCHS 1 CHS 3 0 20000b 01 11b ADENB 1 GCHS 1 CHS 3 0 1000b ADENB 1 GCHS 1 CHS 3 0 1001b TCOENB 1 PWMOOUT 1 ADENB 1 GCHS 1 CHS 3 0 1010b 1 PWM10OUT 1 ADENB 1 GCHS 1 CHS 3 0 101 1b TCOENB 1 2001 1 DC Digital Characteristic AC Analog Characteristic HV High Voltage Characteristic 5 TECHNOLOGY CO LTD Page 79 Version 1 4 8 Flash Micro Controller with Embedded ICE and ISP 7 2 V O PORT MODE The port direction is programmed by PnM register When the bit of PnM register is 0 the pin is input mode When the bit of PnM register is 1 the pin is output mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POM PO6M PO5M 4 2 PO1M POOM Read Write RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1M P17M P16M P15M P14M P13M P12M P11M P10M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAM 47 46 45 P44M P43M P42M P41M P40M Read Write R W RAN R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
160. disable pull up resistor 0C6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4CON7 PACONG 5 PACONA 4 4 2 4 1 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 4 7 0 4 configuration control bits 0 P4 n can be a digital pin 1 P4 n will be set as input mode and disable pull up resistor 0C7H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5CON P5CON3 P5CON2 P5CON1 P5CONO Read Write R W R W RAN R W After reset 0 0 0 0 Bit 3 0 5 3 0 P5 n configuration control bits 0 P5 n can be a digital I O pin 1 P5 n will be set as input mode and disable pull up resistor Port 4 and Port 5 ADC analog input is controlled by GCHS and CHSn bits of ADM register If GCHS 0 P4 n and P5 n are general purpose bi direction I O port If GCHS 1 P4 n and P5 n pointed by CHSn is ADC analog signal input pin 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADM ADENB ADS EOC GCHS 53 CHS2 CHS1 CHSO Read Write R W R W R W RAN R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 4 GCHS Global channel select bit 0 Disable AIN channel 1 Enable channel Bit 3 0 3 0 ADC input channels select bit 0000 AINO 0001 AIN1 0010 AIN2 0011 0100 AIN4 0101 AIN5 0110 AI
161. dure after interrupt service routine execution 15 operation The PUSH and POP operations aren t through instruction PUSH POP and executed by hardware automatically PUSH operation PUSH operation saves the contents of and working registers 0x80 0x8F into hardware buffers PUSH operation executes before program counter points to interrupt vector The RAM bank keeps the status of main routine and doesn t switch to bank 0 automatically The RAM bank is selected by program operation POP operation reloads the contents of ACC and working registers 0x80 0x8F from hardware buffers POP operation executes as RETI instruction executed The RAM bank switches to last status of main routine after reloading RBANK content 0x80 0x87 working registers include L Z Y X PFLAG RBANK 0 7 5 TECHNOLOGY CO LTD Page 65 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 6 3 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including eleven internal interrupts two external interrupts enable control bits One of the register to be set 1 is to enable the interrupt request function Once of the interrupt occur the stack is incremented and program jump to ORG 8 14 to execute interrupt service routines The program exits the interrupt service routine when the returning interrupt service routine ins
162. e SlowMode The system inserts into Slow Mode and stops high speed oscillator Slow2Normal system returns to Normal Mode from Slow Mode The macro includes operating mode switch enable high speed oscillator high speed oscillator warm up delay time gt Example Switch normal slow mode to power down sleep mode SleepMode Declare SleepMode macro directly gt Example Switch normal mode to slow mode SlowMode Declare SlowMode macro directly gt Example Switch slow mode to normal mode The external high speed oscillator stops Slow2Normal Declare Slow2Normal macro directly gt Example Switch normal slow mode to green mode GreenMode Declare GreenMode macro directly gt Example Switch normal slow mode to green mode and enable TO wake up function Set TO timer wakeup function BOBCLR FTOIEN To disable TO interrupt service BOBCLR FTOENB To disable TO timer MOV A 20H set TO clock 64 MOV A 74H BOMOV TOC A To set TOC initial value 74H To set TO interval 10 ms BOBCLR FTOIEN To disable TO interrupt service BOBCLR FTOIRQ To clear TO interrupt request BOBSET FTOENB To enable TO timer Go into green mode GreenMode Declare GreenMode macro directly Example Switch normal slow mode to green mode and enable TO wake up function with RTC CLR TOC Clear TO counter BOBSET FTOTB Enable TO RTC function BOBSE
163. e The RET instruction is for CALL instruction When a pop operation occurs the STKP is incremented and points to the next free stack location The stack buffer restores the last program counter PC to the program counter registers The Stack Restore operation is as the following table STKP Register Stack Buffer STKOV STKPB2 STKPB1 STKPBO High Byte Low Byte 8 1 1 1 STK7H STK7L 0 7 0 0 o se 0 6 0 0 1 ssw sk 0o 5 0 1 0 sm o Description L4 0 1 1 STGH 0 1 0 o ska ska 0 Pp 2 1 0 1 ka o Pp 1 31 0 sro 0 L9 1 tee 0 1 1 Note When stack overflow occurs the system detects the condition and set STKOV flag Logic 1 STKOV flag can t be cleared by program 5 TECHNOLOGY CO LTD Page 41 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 2 5 CODE OPTION TABLE The code option is the system hardware configurations including oscillator type noise filter option watchdog timer operation L VD option reset pin option and Flash ROM security control The code option items are as following table Code Option Content Function Description IHRC 16M 2 internal 16 2 RC XIN XOUT pins are bi direction GPIO IHR
164. e latch control flag So write T1 16 bit counter is to write T1CH first and then write T1CL The 16 bit data is written to 16 bit counter buffer after executing writing T1CL Read T1 16 bit counter is to read T1CL first and then read T1CH The 16 bit data is dumped to T1CH T1CL after executing reading T1CH gt Read 1 counter buffer sequence is to read T1CL first and then read T1CH gt Write 1 counter buffer sequence is to write T1CH first and then write The equation of T1 16 bit counter T1CH T1CL initial value is as following T1CH T1CL initial value 65536 T1 interrupt interval time T1 clock rate gt Example To calculation T1CH and values to obtain 500ms T1 interval time T1 clock source is 16MHz 16 1MHz Select T1RATE 000 Fcpu 128 T1 interval time 500ms T1 clock rate 16MHz 16 128 1 16 bit counter initial value 65536 T1 interval time input clock 65536 500ms 16MHz 16 128 65536 500 10 3 16 106 16 128 FOBDH T1CH T1CL 5 TECHNOLOGY CO LTD Page 115 Version 1 4 N N 7 SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 6 5 T1 CPATURE TIMER The 16 bit capture timer is controlled by CPTEN bit but the T1 must be enabled Set T1ENB 1 and CPTEN 1 to enable capture timer function The capture timer is a pure counter and no clock source to decide interval time Capture timer i
165. e 7 Version 1 4 N N M SNSF27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 PRODUCT OVERVIEW SN8F27E60 series 8 bit micro controller is a new series production applied advanced semiconductor technology to implement flash ROM architecture Under flash ROM platform SN8F27E60 builds in in system programming ISP function extending to EEPROM emulation and Embedded ICE function It offers high performance 12 ch 10 bit ADC 3 set individual programmable PWMs 3 type serial interfaces and flexible operating modes Powerful functionality high reliability and low power consumption can apply to AC power application and battery level application easily 1 1 FEATURES Memory configuration Four 8 bit timer TO TC1 TC2 Flash ROM size 6K x 16 bits Including EEROM TO Basic timer emulation In system programming 0 Timer counter PW MO RAM size 512 x 8 bits TC1 Timer counter PWM1 8levels stack buffer TC2 Timer counter PW M2 13 interrupt sources channel duty cycle programmable PWM to 11 internal interrupts TO TCO TC1 TC2 T1 ADC Generate PWM Buzzer and IR carrier signals SIO MSP UTX UART TX URX UART RX WAKE PWMO 2 2 external interrupts INTO INT1 One 16 bit timer T1 with capture timer function Multi interrupt vector structure 12 channel 10 bit ADC Each of interrupt sources has a unique interrupt vector Serial Interface SIO UART MSP Build in
166. e R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 PEROML 7 0 The low byte buffer of ISP ROM address ODDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEROMH PEROMH7 PEROMH6 5 4 PEROMHS 2 1 PEROMHO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 7 01 The high byte buffer of ISP ROM address 13 6 ISP RAM ADDRESS REGISTER ISP RAM address length is 10 bit and separated into PERAML register and 0 bits Before ISP execution set the head address of ISP RAM by program ODEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERAML PERAML7 PERAML6 5 PERAML4 PERAML3 PERAML2 PERAML1 PERAMLO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 PERAML 7 0 ISP RAM address 7 0 ODFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 PERAMCNT6 PERAMCNT5 PERAMCNT4 PERAMCNT3 E PERAMLS9 PERAML8 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 1 0 01 ISP RAM address 9 8 5 163 Version 1 4 8 Bit Flash Micro Controller with Embedded ICE and ISP 13 7 ISP ROM PROGRAMMING LENGTH REGISTER ISP programming length is 1 word 32 word ISP ROM programming length is controlled by PERAMCNT 7 3 b
167. e RAN R W RAN R W RAN R W R W R W After reset 0 0 0 0 0 0 0 0 12 6 MSP MSPADR REGISTER MSPADR initial value 0000 0000 OEEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSPADR MSPADR7 MSPADR6 MSPADR5 MSPADR4 MSPADRS3 MSPADR2 MSPADR1 MSPADRO Read Write RAN R W RAN R W RAN R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 1 7 0 Address Bit 0 mode control bit 0 1 mode 1 mode 12 7 SLAVE MODE OPERATION When an address is matched or data transfer after and address match is received the hardware automatically will generate the acknowledge ACK signal and load MSPBUF MSP buffer register with the received data from MSPSR There are some conditions that will cause MSP function will not reply ACK signal Data Buffer already full BF 1 MSPSTAT bit 0 when another transfer was received Data Overflow MSPOV 1 MSPM1 bit 6 when another transfer was received When 1 means MSPBUF data is still not read by MCU so MSPSR will not load data into MSPBUF but MSPIRQ and bit will still set to 1 BF bit will be clear automatically when reading MSPBUF register MSPOV bit must be clear through by Software 12 7 1 Addressing When MSP Slave function has been enabled it will wait a START signal occur Following the START signal 8 bit address will shift into the MSPSR register The data of MSPSR 7 1 is compare w
168. e and Slave device ready 1 Release SCL Clock Slave Transistor mode CKP function always enables Slave Receiver CPK function control by SLRXCKP In MSP Master mode Unused SONiX TECHNOLOGY CO LTD Page 146 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP Bit 3 SLRXCKP Slave Receiver mode SCL Clock Priority Control bit In MSP Slave Receiver mode 0 Disable CKP function 1 Enable CKP function In MSP Slave and Slave Transistor mode Unused Bit 2 MSPWK MSP Wake up indication bit 0 MCU NOT wake up by MSP 1 wake up by MSP Note Clear MSPWK before entering Power down mode for indication the wake up source from MSP or not Bit 0 MSPC MSP mode Control register 0 MSP operated on Slave mode 7 bit address 1 MSP operated on Master mode 12 4 MSP MODE REGISTER 2 OECH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSPM2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 GCEN General Call Enable bit In Slave mode only 0 General call address disabled 1 Enable interrupt when a general call address 0000h is received Bit 6 ACKSTAT Acknowledge Status bit In master mode only In master transmit mode 0 Acknowledge was received from slave 1 Acknowledge was not received from slave Bit 5 ACKDT Acknowled
169. e external edge trigger occurs the external interrupt request flag will be set to 1 when the external interrupt control bit enabled If the external interrupt control bit is disabled the external interrupt request flag won t active when external edge trigger occurrence When external interrupt control bit is enabled and external interrupt edge trigger is occurring the program counter will jump to the interrupt vector ORG 0x0009 0 000 and execute interrupt service routine The external interrupt builds in wake up latch function That means when the system is triggered wake up from power down mode the wake up source is external interrupt source 0 0 or 1 and the trigger edge direction matches interrupt edge configuration the trigger edge will be latched and the system executes interrupt service routine fist after wake up 09 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE P01G1 P01G0 POOG1 POOGO Read Write R W R W RAN After reset 1 0 1 0 Bit 3 2 PO1G 1 0 INT1 edge trigger select bits 00 reserved 01 rising edge 10 falling edge 11 rising falling bi direction Bit 1 0 POOG 1 0 INTO edge trigger select bits 00 reserved 01 rising edge 10 falling edge 11 rising falling bi direction Example Setup INTO interrupt request and bi direction edge trigger MOV A BOMOV PEDGE A Set INTO interrupt trigger a
170. e wake up by PO P1 level change trigger 5 TECHNOLOGY CO LTD Page 60 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 5 5 GREEN MODE The green mode is another system ideal status not like power down mode In power down mode all functions and hardware devices are disabled But in green mode the system clock source keeps running so the power consumption of green mode is larger than power down mode In green mode the program isn t executed but the timer with wake up function actives as enabled and the timer clock source is the non stop system clock The green mode has 2 wake up sources One is the PO P1 level change trigger wake up The other one is internal timer with wake up function occurring overflow That s mean users can setup one fix period to timer and the system is waked up until the time out Inserting green mode is controlled by CPUM1 bit of OSCM register When CPUM1 1 the system inserts into green mode After system wake up from green mode the CPUM bit is disabled zero status automatically and the WAKE bit set as 1 The program stops executing and full functions are disabled Onlythe timer with wake up function actives The oscillator to be the system clock source keeps running and the other oscillators operation is depend on system operation mode configuration If inserting green mode from normal mode the system insets to norm
171. ect indicator 0 Vdd gt LVD33 detect level 1 Vdd lt LVD33 detect level Note Refer to instruction set table for detailed information of DC and Z flags 5 TECHNOLOGY CO LTD Page 30 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 2 4 PROGRAM COUNTER The program counter PC is a 13 bit binary counter separated into the high byte 5 and the low byte 8 bits This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit Normally the program counter is automatically incremented with each instruction during program execution Besides it can be replaced with specific address by executing CALL or JMP instruction When JMP or CALL instruction is executed the destination address will be inserted to bit 0 bit 12 Bit 15 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 BitO PC 12 11 10 PC9 PC6 5 PC2 1 PCO After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 PCL ONE ADDRESS SKIPPING There are nine instructions CMPRS INCS INCMS DECS DECMS 50 BTS1 BOBTSO BOBTS1 with one address skipping function If the result of these instructions is true the PC will add 2 steps to skip next instruction If the c
172. ection is Data Transfer Edge When setting rising edge that means to receive and transmit one bit data at SCK rising edge and data transition is at SCK falling edge When setting falling edge that means to receive and transmit one bit data at SCK falling edge and data transition is at SCK rising edge is the clock phase bit controls the phase of the clock on which data is sampled When CPHA 1 the SCK first edge is for data transition and receive and transmit data is at SCK on edge When 0 the 1 bit is fixed already and the SCK first edge is to receive and transmit data The SIO data transfer timing as following figure L PP inti Diagrams Description BILJA SCK idle status Low The transfer first bit MSB 01011 data transfer Falling X bite X bits X bit X bio SCK idle status High The transfer first bit MSB 01111 SCK data transfer edge Rising A bite X bits X X bits X bit X bio edge SCK idle status Low ololo The transfer first bit MSB SCK data transfer edge Rising X bits X bits X bits X X bito X Nextdata edge SCK idle status High 1 0 The transfer first bit MSB SCK data transfer edge Falling bit bits X bits X biz X biti X bio X Nextdata cage SCK idle status
173. een mode In green mode TO keeps counting set TOIRQ and wakes up system when TO timer overflows Clock Source ae 0 00 0 00 b by 7 ore B TOIRQ TO timer overflows TOIRQ set as 1 e Reload TOC by program TOIRQ is cleared by program TO clock source is instruction cycle through TOrate 2 0 pre scalar to decide 2 256 TO length is 8 bit 256 steps and the one count period is each cycle of input clock TO Interval Time Fhoscz16MHz Fhosc 4MHz TOrate 2 0 TO Clock 4 4 115 Unit us 115 Unit us 0000 256 16 384 65 536 0010 128 8 192 32 768 IHRC RTC mode max sec Unit ms 010b Fcpu 64 4 096 16 384 011b 32 2 048 8 192 1000 16 1 024 4 096 101b Fcpu 8 0 512 2 048 110b Fcpu 4 0 256 1 024 111b 0 128 0 512 5 TECHNOLOGY CO LTD Page 89 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 8 2 3 TOM MODE REGISTER TOM is TO timer mode control register to configure TO operating mode including TO pre scaler clock source These configurations must be setup completely before enabling TO timer 0B2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOM TOENB TOrate2 1 TOrateO TOTB Read
174. en wake up from power down mode MCU must operate in Normal mode before Master sent START signal 2 In MSP wake up if the address not matches MCU will keep in power down mode 3 Clear MSPWK before enter power down mode by Software for wake up indication 5 TECHNOLOGY CO LTD Page 152 Version 1 4 N N 7 SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 8 MASTER MODE Master mode of MSP operation from a START signal and end by STOP signal The START S and STOP P bit are clear when reset or MSP function disabled In Master mode the SCL and SDA line are controlled by MSP hardware Following events will set MSP interrupt request MSPIRQ if MSPIEN set interrupt occurs START condition STOP condition Data byte transmitted or received Acknowledge Transmit Repeat START 12 8 1 Mater Mode Support Master mode enable when MSPC and MSPENB bit set Once the Master mode enabled the user had following six options Send a START signal on SCL and SDA line Send a Repeat START signal on SCL and SDA line Write to MSPBUF register for Data or Address byte transmission Send a STOP signal on SCL and SDA line Configuration MSP port for receive data Send an Acknowledge at the end of a received byte of data 12 8 2 MSP Rate Generator In MSP Mode the MSP rate generator s reload value is located in the lower 7 bit of MSPADR register When is loaded with the register t
175. er than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is larger than 0 7V The external reset circuit is with a stable current through R1 and R2 For power consumption issue application e g DC power system the current must be considered to whole system power consumption Note Under unstable power condition as brown out reset Zener diode rest circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well under unstable power situation 3 6 5 External Reset IC The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different application and system requirement to select suitable reset IC The reset circuit can improve all power variation 5 TECHNOLOGY CO LTD Page 51 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 4 SYSTEM CLOCK 4 1 OVERVIEW The micro controller is a dual clock system including high speed and low speed clocks The high speed clock includes internal high speed oscillator and external oscillators selected by High code option The l
176. eration of watchdog timer is as following To clear the watchdog timer counter in the top of the main routine of the program Main Check I O Err JMP or RAM error Program jump here and don t clear watchdog Wait watchdog timer overflow to reset IC Correct and RAM are correct Clear watchdog timer and execute program MOV 5AH Clear the watchdog timer BOMOV WDTR A CALL SUB1 CALL SUB2 JMP MAIN 5 TECHNOLOGY CO LTD Page 87 Version 1 4 N 5 7 SN8F27E60 Series S 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 2 TO 8 BIT BASIC TIMER 8 2 1 OVERVIEW The TO timer is an 8 bit binary up timer with basic timer function The basic timer function supports flag indicator TOIRQ bit and interrupt operation interrupt vector The interval time is programmable through TOM TOC registers and supports RTC function The TO builds in green mode wake up function When TO timer overflow occurs under green mode the system will be waked up to last operating mode A 8 bit programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency Interrupt function TO timer function supports interrupt function When TO timer occurs overflow the TOIRQ actives and the system points program counter to interrupt vector to do interrupt sequence function TO supports RTC function The RTC clock source is from external low spee
177. ess BOMOV A BUF Z Z BUF BOADD 2 BOBTS1 FC Check the carry flag JMP GETDATA FC 0 INCMS Y FC 1 1 NOP GETDATA To lookup data If BUF 0 data is 0x0035 If BUF 1 data is 0x5105 If BUF 2 data is 0x2012 1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H 5 TECHNOLOGY CO LTD Page 21 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 1 4 JUMP TABLE DESCRIPTION The jump table operation is one of multi address jumping function Add low byte program counter PCL and ACC value to get one new PCL If PCL is overflow after PCL ACC PCH adds one automatically The new program counter PC points to a series jump instructions as a listing table It is easy to make a multi jump program depends on the value of the accumulator A Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change gt Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary BOADD PCL PCL PCL ACC PCH 1 when PCL overflow occurs JMP AOPOINT ACC 0 jump to AOPOINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP 3 jump to SONIX provides a macro for safe jump t
178. esult of operating is zero Z or there is carry C or DC occurrence then these flags will be set to PFLAG register ACC is not in data memory RAM so ACC can t be access by instruction during the instant addressing mode gt Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV 0FH Write data from BUF data memory MOV A BUF The system will store ACC and working registers 0x80 0x8F by hardware automatically when interrupt executed gt Example Protect ACC and working registers CODE INT SERVICE Save ACC to buffer Save working registers to buffer Load working registers form buffers Load ACC form buffer RETI Exit interrupt service vector 5 TECHNOLOGY CO LTD Page 29 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 2 2 3 PROGRAM FLAG The PFLAG register contains the arithmetic status of ALU operation system reset status and LVD detecting status POR WDT and RST bits indicate system reset status including power on reset LVD reset reset by external pin active and watchdog reset C DC Z bits indicate the result status of ALU operation LVD24 LVD33 bits indicate LVD detecting power voltage status 086 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG POR WDT RST STKOV C DC Z Read Wr
179. event occurs controlled by CPTMD bit the capture timer and T1 timer stop counting CPTStart bit is cleared and T1IRQ is set as 1 If T1IEN 1 the system executes T1 interrupt function and service routine Capture timer counting trigger source is the rising edge of input signal 16 bit Capture Timer n X nel b 1 2 1 n 3 4 1 5 0 Low speed mode T1ENB 1 1 CPTG 1 0 00 _ _ AD 0 0000 16 bit Capture Timer Set initial value by program CPTStart 1 Un know Data 0 T1 16 bit Timer v Rising edge trigger to count Capture timer is overflow stops counting 0 LE CPTStart 0 Initialization Input signal rate T1 timer rate Use T1 timer to measure input signal continuous duration Set capture timer initial value CPTCH CPTCL and clear T1 counter 1 0x0000 by program Set CPTSatrt bit 1 to start capture timer counting Capture timer and T1 start counting at the first rising edge of input signal When capture timer overflow occurs OxFFFF to 0x0000 T1 stops counting CPTStart is cleared 0 automatically and the T1IRQ sets as 1 The T1 16 bit counter value 1 T1CL is the continuous signal s duration 5 TECHNOLOGY CO LTD Page 116 Version 1 4 N N 7 SN8F27E60 Series 5 NS a X 8 Bit Fla
180. fer gt URXPC URX gt gt f Parity 1 URXEN gt URRXD2 8 bit Buffer lt URXEN Fhosc UARTBaudRale H gt URXS1 0 and interrupt X Control Block UART Counter Pre scaler and Divider interrupt lt UTXEN UTXPS UTXPEN UTXM Y UTXEN gt URTXD 1 8 bit Buffer gt UTXPC v 1 0 gt URTXD2 8 bit Buffer Parity Check UART Interface Structure Diagram 5 TECHNOLOGY CO LTD Page 130 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 10 2 UART OPERATION The UART RX and TX pins are shared with GPIO When UART enables URXEN 1 UTXEN 1 the UART shared pins transfers to UART purpose and disable GPIO function automatically When UART disables the UART pins returns to GPIO last status The UART data buffer length supports 1 byte The UART supports interrupt function URXIEN UTXIEN are UART transfer interrupt function control bit URXIEN 0 disable UART receiver interrupt function UTXIEN 0 disable UART transmitter interrupt function URXIEN 1 enable UART receiver interrupt function UTXIEN 1 enable UART transmitter interrupt function When UART interrupt function enable the program counter points to interrupt vector ORG 0013H 0014H to do UART interrupt service routine after UART operating URXIRQ UTXIRQ is U
181. field DIP 20 Pin SN8F27E62LP DC field DIP 20 Pin SN8F27E62S AC field SOP 20 Pin SN8F27E62LS DC field SOP 20 Pin VSS 1 U 20 VDDL VSS 1 U 20 VDD XIN PO 6 2 19 VDD AVREFH XIN PO 6 2 19 VDD AVREFH XOUT PO 5 3 18 P4 3 AIN3 XOUT PO0 5 3 18 P4 3 AIN3 RST P0 4 4 17 P4 4 AIN4 RST P0 4 4 17 P4 4 AIN4 1 5 16 P4 5 AIN5 PO S UTX T1 5 16 5 1 5 2 2 6 15 P4 6 AIN6 P0 2 URX TC2 6 15 P4 6 AIN6 7 14 P4 7 AIN7 7 14 P4 7 AIN7 P1 1 EIDA 8 13 P5 0 AIN8 P1 1 EIDA 8 13 P5 0 AIN8 P1 0 EICK 9 12 P5 1 AIN9 PWMO P1 0 EICK 9 12 P5 1 AIN9 PWMO P5 3 AIN11 PWMe2 10 11 P5 2 AIN10 PWM1 P5 3 AIN11 PWM2 10 11 P5 2 AIN10 PWM1 5 TECHNOLOGY LTD Page 12 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 1 4 PIN DESCRIPTIONS VDD VSS P Power supply input pins for digital and analog circuit VDDL P Low voltage power pin Connect 0 1uF capacitor to Vss AVREFH P ADC high reference voltage input pin RST System external reset input pin Schmitt trigger structure active low normal stay to high lO PO 4 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up XIN Oscillator input pin while exter
182. function When TC1 timer occurs overflow the TC1IRQ actives and the system points program counter to interrupt vector to do interrupt sequence A Event Counter The event counter function counts the external clock counts Duty cycle programmable PWM The PWM is duty cycle programmable controlled by TC1R and TC1D registers Green mode function All TC1 functions timer PWM event counter auto reload keep running in green mode and no wake up function TC1 Rate 1 128 1 50 TC1CKS1 TC1ENB Load TC1 Time Out 8 Bit Binary Up Counting Counter PWMOOUT 5 2 P0 1 Schmitter Trigger 1 TC1D Data Buffer SONiX TECHNOLOGY LTD Page 99 Version 1 4 N 7 SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 4 2 TC1 TIMER OPERATION TC1 timer is controlled by TC1ENB bit When TC1ENB 0 TC1 timer stops When TC1ENB 1 1 timer starts to count Before enabling TC1 timer setup TC1 timer s configurations to select timer function modes e g basic timer interrupt function TC1C increases 1 by timer clock source When TC1 overflow event occurs TC1IRQ flag is set as 1 to indicate overflow and cleared by program The overflow condition is TC1C count from full scale OxFF to zero scale 0x00 In difference function modes TC1C value relates to operation If TC1C value c
183. g bit 0 Collect UART frame 1 2 UART frame is error including start stop bit stream length Bit 2 0 URS 2 0 UART per scalar select bit 000 Fhosc 1 001 2 010 Fhosc 4 011 Fhosc 8 100 Fhosc 16 101 Fhosc 32 110 Fhosc 64 111 Fhosc 128 5 TECHNOLOGY CO LTD Page 134 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 10 8 UART TRANSMITTER CONTROL REGISTER 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URTX UTXEN UTXPEN UTXPS UTXBRK URXBZ UTXBZ Read Write RAN R W RAN RAN R After reset 0 0 0 0 0 0 Bit 7 UTXEN UART TX control bit 0 Disable UART TX UTX pin is GPIO mode or returns to GPIO status 1 Enable UART TX UTX pin exchanges from GPIO mode to UART TX mode and idle high status Bit 6 UTXPEN UART TX parity bit control bit 0 Disable UART TX parity bit function The data stream doesn t include parity bit 1 Enable UART TX parity bit function The data stream includes parity bit Bit 5 UTXPS UART TX parity bit format control bit 0 UART TX parity bit format is even parity 1 UART TX parity bit format is odd parity Bit 4 UTXBRK UART TX BREAK pocket control bit 0 End of transmitting UART BREAK pocket 1 Start to transmit UART BREAK pocket Bit 3 URXBZ UART RX operating status flag 0 UART is idle or the end of processing 1 UART is busy and
184. ge Data bit In master mode only master receive mode Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive 0 Acknowledge 1 Not Acknowledge bit 4 ACKEN Acknowledge Sequence Enable bit In MSP master mode only In master receive mode 0 Acknowledge sequence idle 1 Initiate Acknowledge sequence on SDA and SCL pins and transmit AKDT data bit Automatically cleared by hardware bit 3 RCEN Receive Enable bit In master mode only 0 Receive idle 1 Enables Receive mode for MSP bit 2 PEN Stop Condition Enable bit In master mode only 0 Stop condition idle 1 Initiate Stop condition on SDA and SCL pins Automatically cleared by hardware bit 1 RSEN Repeated Start Condition Enabled bit In master mode only 0 Repeated Start condition idle 1 Initiate Repeated Start condition on SDA and SCL pins Automatically cleared by hardware bit 0 SEN Start Condition Enabled bit In master mode only 0 Start condition idle 1 Initiate Start condition on SDA SCL pins Automatically cleared by hardware 5 TECHNOLOGY CO LTD Page 147 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 5 MSP MSPBUF REGISTER 5 initial value 0000 0000 OEDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSPBUF MSPBUF7 MSPBUF6 MSPBUF5 MSPBUF4 MSPBUF3 MSPBUF2 MSPBUF1 MSPBUFO Read Writ
185. gh ADC converting rate If the ADC converting time is slower than analog signal variation rate the ADC result would be error So to select a correct ADC clock rate and ADC resolution to decide a right ADC converting rate is very important 10 bit ADC conversion time 1 ADC clock rate 4 14 sec 4 2 16 2 ADLEN EOS ECE ADC Converting ADC Converting ADC Converting ADC Converting ADCKSO Rate 5 time Rate time Rate Fepu ie 1 4 2 16 4 14 4 464KHz 1 16 2 16 4 14 17 857KHz P 224 us 56 us i 1 4MHz 8 4 14 8 929KHz 1 16MHz 8 4 14 35 71KHz 1 10 51 4 112 us 28 us m EHE 1 4MHz 4 14 71 43KHz 1 16MHz 4 14 286KHz 14 us 3 5 us 1 4 2 2 4 14 35 71KHz 1 16MHz 2 4 14 143KHz e e med 8 bit ADC conversion time 1 ADC clock rate 4 12 sec 4 2 16 2 ADLEN mee ie lee s ADC Converting ADC Converting ADC Converting ADC Converting ADCKSO Rate time Rate time Rate 1 4MHz 16 4 12 5 208 2 1 16MHz 16 4 12 20 833KHz cpu 192 us 48 us 1 4 2 8 4 12 10 416KHz 1 16MHz 8 4 12 41 667KHz SE d NER ui NN 0 8 bit 10 1 4MHz 4 12 83 333KHz 1 16MHz 4 12 333 333KHz 12 3us 1 4MHz 2 4 12 41 667KHz 1 16MHz 2 4 12 166 667KHz 11 Fcpu 2 24 US 5 TECHNOLOGY CO LTD Page 125 Version 1 4 SN8F27E60 Series 8 Bit Flash Micro Controller
186. h Micro Controller with Embedded ICE and ISP Reset pin falling edge trigger system reset External Reset Pin Iw Reset pin returns to high status External Reset Flag Oscillator Tcfg Tost lt gt lt Instruction Cy cle pystem is under reset status e Watchdog Reset Timing Watchdog timer overflow Watchdog Reset Flag Oscillator lt Tcfg Tost gt Instruction Cycle Power Down Mode Wake up Timing Edge trigger system wake up Wake up Pin Falling Edge Wake up Pin Rising Edge Oscillator Tost T Instruction Cycle System inserts into power down mode Green Mode Wake up Timing d Edge trigger system wake up Wake up Pin Falling Edge Wake up Pin Rising Edge Timer overflow Timer Oscillator Instruction Cycle System inserts into green mode 5 TECHNOLOGY CO LTD Page 56 Version 1 4 IN N 7 SN8F27E60 Series a X 8 Bit Flash Micro Controller with Embedded ICE and ISP Oscillator Start up Time The start up time is depended oscillator s material factory and architecture Normally the low speed oscillator s start up time is lower than high speed oscillator The RC type oscillators start up time is faster than crystal type oscillator Tost Ceramic Resonator Tost lt Tost gt
187. hanging effects operation the transition of operations would make timer function error So TC1 builds in double buffer to avoid these situations happen The double buffer concept is to flash TC1C during TC1 counting to set the new value to TC1R reload buffer and the new value will be loaded from TC1R to TC1C after TC1 overflow occurrence automatically In the next cycle the TC1 timer runs under new conditions and no any transitions occur The auto reload function is no any control interface and always actives as TC1 enables If TC1 timer interrupt function is enabled TC1IEN 1 the system will execute interrupt procedure The interrupt procedure is system program counter points to interrupt vector ORG 000DH and executes interrupt service routine after TC1 overflow occurrence Clear TC1IRQ by program is necessary interrupt procedure TC1 timer can works in normal mode slow mode and green mode But in green mode TC1 keep counting set TC1IRQ and outputs PWM but can t wake up system Clock Source 2E 0x00 oo Keen TC1IRQ TC1 timer overflows TC1IRQ set as 1 Reload TC1C from TC1R automatically TC1IRQ is cleared by program TC1 provides different clock sources to implement different applications and configurations TC1 clock source includes Fcpu instruction cycle Fhosc high speed oscillator and external input pin PO 1 controlled by TC1CKS 1 0 bits 1 0 bit selects the clock so
188. he MRG count down to 0 and stop until another reload has taken place In MSP mater mode MRG reload from MSPADR automatically If Clock Arbitration occur for instance SCL pin keep low by Slave device the MRG will reload when SCL pin is detected High SCL clock rate Fepu MSPADR 2 For example if we want to set 400Khz in 4Mhz Fcpu the MSPADR have to set 0x05h MSPADR 4Mhz 400Khz 2 5 MSPC MSPM1 MSPC Reload SCL Control SCL Clock Out Down Counter MSP Rate Generator Block Diagram SDA shift in next bit Data SDA DX DX 1 DX 2 No Clock Clock Slave release SCL clock Arbitration 4 Arbitration allowed to transition high S MN DN Down Counter x MRG Reload SCL Is sampled High E Reload occurred and MRG down counter starts count Timing Diagram with and without Clock Arbitration 0 03 SONiX TECHNOLOGY CO LTD Page 153 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 8 3 MSP Mater START Condition To generate a START signal user sets SEN bit MSPM2 0 When SDA and SCL pin are both sampled High MSP rate generator reload MSPADR 6 0 and starts down counter When SDA and SCL are both sampled high and overflow SDA pin is drive low When SCL sampled high and SDA transmitted from High to Low is the START signal and will set S bit MSPSTAT 3 MRG reload ag
189. he pocket URK Pin Start UART RX Stop Processor If the host s UART baud rate isn t match to receiver terminal the received pocket is error But it is not easy to differentiate the pocket is correct or not because the received error pocket maybe match UART rule but the data is error Use checking UFMER bit and URXPC bit status to decide the stream If the two conditions seem like correct but the pocket is abnormal UART will accept the pocket as correct one 10 7 UART RECEIVER CONTROL REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URRX URXEN URXPEN URXPS URXPC UFMER URS2 URS1 URSO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 URXEN UART RX control bit 0 Disable UART RX URX pin is GPIO mode or returns to GPIO status 1 Enable UART URX pin exchanges from GPIO mode to UART mode Bit 6 URXPEN parity bit control bit 0 Disable UART RX parity bit function The data stream doesn t include parity bit 1 Enable UART parity bit function The data stream includes parity bit Bit 5 UTXPS UART RX parity bit format control bit 0 UART parity bit format is even parity 1 UART parity bit format is odd parity Bit 4 URXPC UART RX parity bit checking flag 0 Parity bit is correct or no parity function 1 Parity bit is error Bit 3 UFMER UART RX stream frame error fla
190. he system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 2048 external high speed oscillator clocks and 32 internal high speed oscillator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode X Note Wakeup from green mode is no wakeup time because the clock doesn t stop in green mode The value of the external high clock oscillator wakeup time is as the following The Wakeup time 1 Fosc 2048 sec high clock start up time Example In power down mode sleep mode the system is waked up After the wakeup time the system goes into normal mode The wakeup time is as the following The wakeup time 1 Fosc 2048 0 512 ms Fosc 4MHz The total wakeup time 0 512 ms oscillator start up time The value of the internal high clock oscillator RC type wakeup time is as the following Wakeup time 1 Fosc 32 sec high clock start up time Example In power down mode sleep mode the system is waked up After the wakeup time the system goes into normal mode The wakeup time is as the following The wakeup time 1 322 2us Fhosc 16MHz Note The high clock start up time is depended on the VDD and oscillator type of high clock 5 TECHNOLOGY CO LTD Page 63 Version 1 4 N N M SN8F27
191. inverter or regulator and connects a 0 1uF capacitor to VSS pin ground VDDL is internal power terminal not connect with power source and only connects a 0 1 capacitor to VSS pin ground This pin assignment has high power noise immunity but the static current is larger The application field is household motor control Regulator 0 1uF Rectification 1 8V 5 5V DC Power Source 1 8V 5 5V VSS L AC Power Source N 0 1uF VSS SN8F27E60 Series MCU SN8F27E60 Series MCU For DC power type battery power source the power pin is VDD VDD pin is connect to DC power source from battery and connects a 0 1uF capacitor to VSS pin ground This pin assignment has low power noise immunity but the static current is very low The application field is portable application 1 8V 3 3V Regulator gt 3 3 1 8 3 3 VSS VSS SN8F27E60L Series MCU SN8F27E60L Series MCU Features Selection Table SN8F27E60 Series ISP Timer Ext INT Embedded OPerating Package ICE Voltage DIP32 8 bit 4 LOFP32 16 01 Y 1 8 55 QFN32 SDIP32 SN8F27E65 SKDIP28 8 bit 4 28 SN8F27E64 18 5 5 ssopag QFN28 8 bit 4 DIP20 SN8F27E62 rain SOP20 SN8F27E60L Series ISP Timer Ext INT Embedded ICE Operating Vo
192. is set the TC2 clock source from external input pin 2 When TC2CKS1 1 TC2 clock source is switch to external input pin 2 TC2 event counter trigger direction is falling edge When one falling edge occurs TC2C will up one count When TC2C counts from OxFF to 0x00 TC2 triggers overflow event The external event counter input pin s wake up function of GPIO mode is disabled when TC2 event counter function enabled to avoid event counter signal trigger system wake up and not keep in power saving mode The external event counter input pin s external interrupt function is also disabled when TC2 event counter function enabled and the PO2IRQ bit keeps 0 status The event counter usually is used to measure external continuous signal rate e g continuous pulse R C type oscillating signal These signal phase don t synchronize with MCU s main clock Use TC2 event to measure it and calculate the signal rate in program for different applications External Input Signel 23 0 00 Cm 2 TC2 timer overflows 2 set as 1 Reload TC2C from TC2R automatically TC2IRQ is cleared by program 8 5 8 PULSE WIDTH MODULATION PWM PWM is duty cycle programmable design to offer various PWM signals When TC2 timer enables and 2 bit sets as 1 enable PWM output the PWM output pin P5 3 outputs PWM signal One cycle of PWM signal is high pulse
193. it 2 Bit 1 Bit 0 TCOC TCOC7 TCOC6 TCOC5 TCOC4 TCOC3 TCOC1 TCOCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TCOC initial value is as following initial value 256 TCO interrupt interval time TCO clock rate 5 TECHNOLOGY CO LTD Page 94 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 3 5 TCOR AUTO RELOAD REGISTER TCO timer builds in auto reload function and TCOR register stores reload data When TCOC overflow occurs TCOC register is loaded data from TCOR register automatically Under TCO timer counting status to modify TCO interval time is to modify TCOR register not TCOC register New TCOC data of TCO interval time will be updated after TCO timer overflow occurrence TCOR loads new value to TCOC register But at the first time to setup TCOM TCOC and TCOR must be set the same value before enabling TCO timer TCO is double buffer design If new TCOR value is set by program the new value is stored in 1 buffer Until TCO overflow occurs the new value moves to real TCOR buffer This way can avoid any transitional condition to affect the correctness of TCO interval time and PWM output signal OB6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOR TCOR7 TCOR6 TCORS5 TCOR4 TCOR3 TCOR2 TCOR1 TCORO Read Write
194. ite R W R W R W After Reset 0 0 0 Bit 7 POR Power on reset and LVD brown out reset indicator 0 Non active 1 Reset active LVD announces reset flag Bit 6 WDT Watchdog reset indicator 0 Non active 1 Reset active Watchdog announces reset flag Bit 5 RST External reset indicator 0 Non active 1 Reset active External reset announces reset flag Bit 4 STKOV Stack overflow indicator 0 Non overflow 1 Stack overflow Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shifting out logic 1 comparison result 2 0 0 Addition without carry subtraction with borrowing signal rotation with shifting out logic 0 comparison result lt 0 Bit 1 DC Decimal carry flag 1 Addition with carry from low nibble subtraction without borrow from high nibble 0 Addition without carry from low nibble subtraction with borrow from high nibble Bit 0 Z Zero flag 1 The result of an arithmetic logic branch operation is zero 0 The result of an arithmetic logic branch operation is not zero OEFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE LVD24 LVD33 STKPB2 STKPB1 STKPBO Read Write RAN R W R W R W After Reset 0 1 1 1 Bit 6 LVD24 LVD24 low voltage detect indicator 0 Vdd gt LVD24 detect level 1 Vdd lt LVD24 detect level Bit 5 LVD33 LVD33 low voltage det
195. ith MSPADR register on the falling edge of eight SCL pulse If the address are the same the BF and SSPOV bit are both clear the following event occur 1 MSPSR register is loaded into MSPBUF on the falling edge of eight SCL pulse 2 Buffer full bit BF is set to 1 on the falling edge of eight SCL pulse signal is generated 4 MSPinterrupt request MSPIRQ is set on the falling edge of ninth SCL pulse Status when Data is Received 5 MSPBUF Reply an ACK signal Set MSPIRQ BF MSPOV 0 0 Yes Yes Yes 0 1 Yes No Yes 1 0 No No Yes 1 1 No No Yes Data Received Action Table Note BFz0 MSPOVz1 shows the software is not set properly to clear Overflow register 5 TECHNOLOGY CO LTD Page 148 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 7 2 Slave Receiving When the R W bit of address byte 0 and address is matched the R W bit of MSPSTAT is cleared The address will be load into MSPBUF After reply an ACK signal MSP will receive data every 8 clock The CKP function enable or disable Default is controlled by SLRXCKP bit and data latch edge Rising edge Default or Falling edge is controlled by CPE bit When overflow occur no acknowledge signal replied which either 1 or 1 MSP interrupt is generated in every data transfer The MSPIRQ bit must be clear by software Fol
196. its which is 5 bit format Before ISP ROM programming execution set the length by program ODFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERAMCNT PERAMCNT7 PERAMCNT6 PERAMCNT5 PERAMOCNT4 PERAML9 PERAML8 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 7 3 7 31 ISP ROM programming length control register ISP programming length 7 31 1 PERAMONT 7 3 20 ISP programming length is 1 word PERAMONT 7 3 21 ISP programming length is 2 word 7 31 30 ISP programming length is 31 word PERAMONT 7 3 231 ISP programming length is 32 word Defines the number of words wanted to be programmed The maximum PERAMCNT 7 3 is 01FH which program 32 words 64 bytes RAM to the Flash The minimum PERAMCNT 7 3 is which program only 1 word to the Flash 5 TECHNOLOGY CO LTD Page 164 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 4 INSTRUCTION TABLE Field Description M AM A M MA Mc A BOMOV A lt M bank 0 BOMOV M bank 0 lt MOV AI BOMOV M M lt only supports 0x80 0x87 registers e g PFLAG R Y Z XCH lt gt im gt 2 gt lt
197. lash Micro Controller with Embedded ICE and ISP SONIX 17 2 WRITER PROGRAMMING PIN MAPPING Programming Pin Information of SN8F27E65 Series Chip Name SN8F27E65P U DIP S DIP SN8F27E65LP U DIP S DIP Writer Connector a and JP3 48 pin text tool Pin Assignment JP1 JP2 Pin Number JP1 JP2 Pin Name VDD GND VDD VPP HLS RST ALSB PDB Bias Voltage VOD 2 P4 6 4 7 pepe JP3 Pin Number Pin Number IC Pin Name JP3 Pin Number VDD 39 VSS P4 5 31 P4 6 P4 7 40 Programming Pin Information of SN8F27E65 Series Chip Name Writer Connector SN8F27E65F LQFP SN8F27E65J QFN SN8F27E65LF LQFP SN8F27E65LJ QFN c and JP3 48 pin text tool Pin Assignment JP1 JP2 Pin Number JP1 JP2 Pin Name 4 Pin Number IC Pin Number IC Pin Name JP3 Pin Number VDD VDD 35 GND VSS 37 CLK P4 5 27 CE PGM OE D1 DO D3 D2 D5 D4 D7 D6 VDD VPP HLS RST ALSB PDB Bias Voltage E U gt U gt a 5 TECHNOLOGY LTD Page 176 Version 1 4 N 7 SN8F27E60 Series E 8 Flash Micro Controller with Embedded ICE and ISP Programming Pin Information of SN8F27E65 Series Chip Name
198. ller with Embedded ICE and ISP 8 5 5 TC2R AUTO RELOAD REGISTER TC2 timer builds in auto reload function and TC2R register stores reload data When TC2C overflow occurs TC2C register is loaded data from TC2R register automatically Under TC2 timer counting status to modify TC2 interval time is to modify TC2R register not TC2C register New TC2C data of TC2 interval time will be updated after TC2 timer overflow occurrence TC2R loads new value to TC2C register But at the first time to setup TC2M TC2C and TC2R must be set the same value before enabling TC2 timer TC2 is double buffer design If new TC2R value is set by program the new value is stored 1 buffer Until TC2 overflow occurs the new value moves to real TC2R buffer This way can avoid any transitional condition to affect the correctness of TC2 interval time and PWM output signal Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC2R TC2R7 TC2R6 TC2R5 TC2R4 TC2R3 TC2R2 TC2R1 TC2RO Read Write 0 0 0 0 0 0 0 0 The equation of TC2R initial value is as following TC2R initial value 256 TC2 interrupt interval time TC2 clock rate gt Example To calculation TC2C and TC2R value to obtain 10ms TC2 interval time TC2 clock source is Fcpu 16 2 16 1MHz Select TCORATE 000 128 TC2 interval time 10ms TC2 clock rate 16MHz 16 128 TC2C TC2R i
199. low clock source is the internal low speed oscillator built in the micro controller The low speed oscillator uses RC type oscillator circuit The frequency is affected by the voltage and temperature of the system In common condition the frequency of the RC oscillator is about 16KHz The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD bit of OSCM register Flosc Internal low RC oscillator about 16 2 Slow mode Flosc 1 Flosc 8 controlled by Low code option When watchdog timer is disabled and system is in power down mode the internal low RC stops gt Example Stop internal low speed oscillator by power down mode as watchdog timer disable BOBSET FCPUMO To stop external high speed oscillator and internal low speed oscillator called power down mode sleep mode 4 6 OSCM REGISTER The register is an oscillator control register It controls oscillator status system mode 095H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM 0 0 0 CPUM 1 CPUMO CLKMD STPHX 0 Read Write RAN R W R W RAN After reset 0 0 0 0 Bit 1 STPHX External high speed oscillator control bit 0 External high speed oscillator free run 1 External high speed oscillator free run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clo
200. lowing is the Slave Receiving Diagram SLRXCKP 0 SDA Receiving Address R W 0 Receiving Data Receiving Data ACK_ 4 A7 AG 5 4 2 1 ACK_ D7 D6X D5 044 D3 D2 D1 DO D7 D6 D5 04 D3 02 D1 DO Ae SCL PiE minate MSPIRQ BF F Cleared by Software SSPOV Read MSPBUF MSPOV 1 Because MSPBUF still full BF 1 _ not sent SLRXCKP 1 not sent Receiving Address Receiving Data _ Receiving Data 2 SDA SCL terminate MSPIRQ by Master 1 Cleared by Software pod SSPOV Read MSPBUF 1 BechuseiMSPBUF still full BF 1 Set CKP after Set CKP Set Aread MSPBUF read MSPBUF ane 12 7 3 Slave Transmission After address match the following R W bit is set MSPSTAT bit 2 R W will be set The received address will be load to MSPBUF and ACK_ will be sent at ninth clock then SCL will be hold low Transmission data will be load into MSPBUF which also load to MSPSR register The Master should monitor SCL pin signal The slave device may hold on the master by keep CKP low When set After load MSPBUF set CKP bit MSPBUF data will shift out on the falling edge on SCL signal This will ensure the SDA signal is valid on the SCL high duty An interrupt is generated on every byte transmissi
201. ltage Package DIP32 8 bit 4 LQFP32 16 bit 1 QFN32 SDIP32 SN8F27E65L SKDIP28 SOP28 SN8F27E64L Teves SSOP28 QFN28 8 bit 4 DIP20 16 bit 1 1 8V 3 3V SN8F27E62L 5 TECHNOLOGY CO LTD Page 9 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP 1 2 SYSTEM BLOCK DIAGRAM INTERNAL HIGH 3 Level LVD gt 16 2 Low Voltage Detector FLASH R EXTERNAL INTERNAL WATCHDOG TIMER ROM HIGH OSC LOW RC Embedded ICE FLAGS System PEIDA TIMING GENERATOR 12 10 bit ADC gt AINO AIN11 Y gt MSP gt SCL SDA UART gt UTX URX SCK SDI SDO SIO gt SOK ACC K SYSTEM REGISTERS INTERRUPT PWM1 CONTROL TIMER amp COUNTER 1 P4 P5 SONiX TECHNOLOGY CO LTD Page 10 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 1 3 PIN ASSIGNMENT e SN8F27E65P AC field DIP 32 Pin SN8F27E65LP DC field
202. mend be careful to use PWM and TC2 timer together and make sure both functions work well The PWM output pin is shared with GPIO and switch to output PWM signal as PWM2OUT 1 automatically If PWM2OUT bit is cleared to disable PWM the output pin exchanges to last GPIO mode automatically It easily to implement carry signal on off operation not to control 2 bit SONiX TECHNOLOGY CO LTD Page 110 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Bit Flash Micro Controller with Embedded ICE and ISP PWM Output JULILILILIL 41 PWM2OUT 0 EWMOUT 1 The pin exchanges to output PW PWM2OUT 1 The pin exchanges to output 2 0 The pin PWM2OUT 1 mode and outputs PWM signal automatically to last GPIO mode output low PWM Output __ lt 0 2001 1 The pin exchanges to output 0 PWM2OUT 1 pin exchanges to output 2 0 pin PWM2OUT 1 mode and outputs PWM signal automatically to last GPIO mode output high 7 7 PWM Output High impendence floating gt lt PWM2OUT 0 PWM2OUT 1 The pin exchanges to output 2 0 The exchanges PWM2OUT 1 mode and outputs PWM signal automatically to last GPIO mode input 8 5 9 TC2 TIMER OPERATION EXPLAME TC2 TIMER CONFIGURATION Reset TC2 timer CLR TC2M Clear TC2M register Set TC2 clock source and TC2 rate MOV
203. ment first Compile the firmware program and generate a SN8 file 091016 Proj D programMest code SNGPI7E5S io_toezle_15_16 PRJ 15_16 4SM 12 15 e 4 oue 15 16 3 FILENAME 2 do toggle 15 16 05M G Sou 1 AUTHOR 2 1516 ASI 2 Template Code for 5 27 63 First issue CHIP 5 8 27 65 Disable Security Enable z High_Fcpu Fhos gt High_Cik IHRC 16M E 4 compile progran test codeVSNBF27E65Vio toggle 15 16 05M Bu leg J Find in Fiesi Find Reely la _ 21 69140 Execute download F8 function of M2IDE Open a 5 8 file and press Enter to download firmware to SN8F27E65 Starter kit or target M2ASM 091016 Proj D programliest code SNBF27E65 o_toggle_15_16 PRJ 15_16 45M gt aloa gjej counter S eve 15 16 tie addbut1 E 9 Sowo 05 1 15 162 PFLAGBUF 05 1 Header 1 1 RENEO Swarr J BB oollngeode SNS 2 15 16288 conptie iWrograstest codeXSNBF27E6S Vio toggle 15 16 85M PRON Check Sun is ecurity Check
204. nable TC1 timer and interrupt function BOBSET FTC1IEN BOBSET FTC1ENB TC1 PWM CONFIGURATION Reset TC1 timer CLR TC1M Set TC1 clock source and TC1 rate MOV A 4t0nnnOnOOb BOMOV TC1M A Set TC1C and register for PWM cycle MOV A value1 BOMOV TC1C A BOMOV A Set TC1D register for PWM duty MOV A value2 BOMOV TC1D A Enable PWM and TC1 timer BOBSET FTC1ENB BOBSET FPWM1OUT 5 TECHNOLOGY CO LTD SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP Clear TC1M register Set TC1 clock source from external input pin PO 1 TC1C must be equal to TC1R Enable TC1 interrupt function Enable TC1 timer Clear TC1M register TC1C must be equal to TC1R TC1D must be greater than TC1R Enable TC1 timer Enable PWM Page 105 Version 1 4 N 7 SN8F27E60 Seri 6 x 8 Bit Flash Micro Controller with Embedded ICE 8 5 2 8 TIMER COUNTER 8 5 1 OVERVIEW TC2 timer is an 8 bit binary up timer with basic timer event counter and PWM functions The basic timer function supports flag indicator TC21RQ bit and interrupt operation interrupt vector The interval time is programmable through TC2M TC2C 2 registers The event counter is changing TC2 clock source from system clock Fcpu Fhosc to external clock like signal e g continuous pulse R C type oscillating signal TC2 becomes a counter to
205. nal oscillator enable crystal and RC lO PO 6 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up XOUT Oscillator output pin while external crystal enable 5 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up 0 0 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up INTO External interrupt 0 input pin TCO event counter input pin 1 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up INT1 External interrupt 1 input pin TC1 TC1 event counter input pin 2 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up Programmable open drain structure TC2 TC2 event counter input pin URX UART receive input pin Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up Programmable open drain structure UTX UART transmit output pin T1 T1 event counter input pin P1 0 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up Programmable open drain structure EICK Embedded ICE clock pin P1 1 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake u
206. nitial value 256 TC2 interval time input clock 256 10ms 16MHz 16 128 256 10 2 16 106 16 128 B2H 8 5 6 TC2D PWM DUTY REGISTER TC2D register s purpose is to decide PWM duty In PWM mode TC2R controls PWM s cycle and TC2D controls the duty of PWM The operation is base on timer counter value When TC2C TC2D the PWM high duty finished and exchange to low level It is easy to configure TC2D to choose the right PWM s duty for application OBFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC2D TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2DO Read Write RAN R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 The equation of TC2D initial value is as following TC2D initial value 2 PWM high pulse width period TC2 clock rate gt Example To calculate TC2D value to obtain 1 3 duty PWM signal TC2 clock source is 16 2 16 1MHz Select 2 000 128 TC2R B2H TC2 interval time 10ms So the PWM cycle is 100Hz In 1 3 duty condition the high pulse width is about 3 33ms TC2D initial value B2H PWM high pulse width period TC2 clock rate B2H 3 33 16MHz 16 128 B2H 5 TECHNOLOGY CO LTD Page 109 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 5 7 TC2 EVENT COUNTER TC2 event counter
207. nput source is pin CPTG 1 0 bits select capture timer functions gt CPTG 1 0 00 Capture Timer Function gt CPTG 1 0 01 Measure high pulse width gt CPTG 1 0 10 Measure low pulse width gt CPTG 1 0 11 Measure cycle These functions must be combined T1 timer function to implement The capture timer can measure high pulse width low pulse width cycle and capture duration of input signal P0 3 controlled by CPTG 1 0 CPTStart bit is to execute capture timer function When CPTStart is set as 1 the capture timer waits the right trigger edge to active 16 bit counter The trigger edge finds and the 16 bit counter starts to count which clock source is T1 When the second right edge finds the 16 counter stops CPTStart is cleared and the T11RQ actives 8 6 5 1Capture Timer The capture timer function controlled by CPTG 1 0 bits Set CPTG 1 0 00 to enable capture timer function The capture timer function s purpose is to measure the period of a continuous signal The function includes two modes for difference speed signal controlled by CPTMD bit To start capture timer operation is set CPTStart bit as 1 and the trigger source is the first rising edge of the input signal Before the first rising edge the capture timer and T1 timer keeps ideal status and wait the riding edge event When catch the first edge the capture timer and T1 timer start to count Each of overflow
208. nterface connected with SN8F27E65 IC to build a real application environment In the mode set SN8F27E65 IC on the target is necessary or the emulation would be error without MCU Embedded ICE 4 wire Interface SN8F27E65 Chip O i B Modular Cable to uM Starter kit or Application Target Board Target Board Sonix Embedded ICE Smart Development Adapter EIDA and EICK share with P1 0 P1 1 GPIO In emulation mode EIDA and EICK are Embedded ICE interface and not execute GPIO functions The P1 0 P1 1 GPIO status still display on M2IDE window to simulate P1 0 P1 1 program execution SONiX TECHNOLOGY CO LTD Page 171 Version 1 4 N SN8F27E60 Series 5 N 8 Flash Micro Controller with Embedded ICE and ISP 16 2 SN8F27E65 STARTER KIT SN8F27E65 Starter kit is an easy development platform It includes SN8F27E65 real chip and I O connectors to input signal or drive extra device of user s application It is a simple platform to develop application as target board not ready The starter kit can be replaced by target board because SN8F27E65 integrates embedded ICE in circuit debugger circuitry The schematic and outline of SN8F27E65 Starter Kit is as following
209. nterrupt INTO request flag 0 None INTO interrupt request 1 2 INTO interrupt request Bit 1 External PO 1 interrupt INT1 request flag 0 None INT1 interrupt request 1 interrupt request Bit 2 TOIRQ TO timer interrupt request flag 0 None TO interrupt request 1 TO interrupt request Bit 3 TCOIRQ TCO timer interrupt request flag 0 None TCO interrupt request 1 TCO interrupt request Bit 4 TC1IRQ TC1 timer interrupt request flag 0 None TC1 interrupt request 1 TC1 interrupt request Bit 5 TC2IRQ TC2 timer interrupt request flag 0 None TC2 interrupt request 1 TC2 interrupt request Bit 6 T1IRQ T1 timer interrupt request flag 0 None T1 interrupt request 1 1 interrupt request Bit 7 ADCIRQ ADC interrupt request flag 0 None ADC interrupt request 1 ADC interrupt request 098H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 MSPIRQ UTXIRQ URXIRQ SIOIRQ WAKEIRQ Read Write R W R W R W R W After reset 0 0 0 0 0 Bit 0 WAKEIRQ Wakeup interrupt request flag 0 None wakeup interrupt request 1 Wakeup interrupt request Bit 1 SIOIRQ SIO interrupt request flag 0 None SIO interrupt request 1 10 interrupt request Bit 2 URXIRQ UART receive interrupt request flag 0 None UART receive interrupt request 1 UART receive interrupt request Bit 3 UTXIRQ UART transmit interrupt request flag 0 None UART t
210. nterrupt enable mode ORG 8 Interrupt vector INT SR Interrupt service routine BOBTS1 FADCIRQ Check ADC interrupt flag JMP EXIT INT 0 Not interrupt request BOMOV A ADB ADCIRQ 1 End of ADC processing Process ADC result BOMOV BUF1 A MOV A 0000001 1b AND A ADR BOMOV BUF2 A End of processing ADC result CLR FEOC Clear ADC processing flag for next ADC converting JMP INT EXIT INT EXIT RETI Exit interrupt service routine X Note ADS is cleared when the end of ADC converting automatically EOC bit indicates ADC processing status immediately and is cleared when ADS z 1 Users needn t to clear it by program 5 TECHNOLOGY CO LTD Page 128 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 9 5 ADC APPLICATION CIRCUIT External High Reference Voltage MCU Analog Signal Input AINn P4 n VSS Main Power Trunk The analog signal is inputted to ADC input pin AINn P4 n The ADC input signal must be through a 0 1uF capacitor A The 0 1uF capacitor is set between ADC input pin and VSS pin and must be on the side of the ADC input pin as possible Don t connect the capacitor s ground pin to ground plain directly and must be through VSS pin The capacitor can reduce the power noise effective coupled with the analog signal The external high reference source AVREFH must be through 47uF C capa
211. nterrupt vector 000EH TC2 Interrupt vector 000 T1 Interrupt vector 0010H ADC Interrupt vector 0011H SIO Interrupt vector 0012H 12 Interrupt vector 0013H UART RX Interrupt vector 0014H UART TX Interrupt vector 0015H User program General purpose area End of user program 17F8H 17F9H 1 7FDH Heserved 17FEH 17FFH The ROM includes Reset vector Interrupt vector General purpose area and Reserved area The Reset vector is program beginning address The Interrupt vector is the head of interrupt service routine when any interrupt occurring The General purpose area is main program area including main loop sub routines and data table 0x0000 Reset Vector Program counter points to 0x0000 after any reset events power on reset reset pin reset watchdog reset LVD reset 0 0001 0 0007 General purpose area to process system reset operation 0 0008 0 0014 Multi interrupt vector area Each of interrupt events has a unique interrupt vector 0x0015 0x177F General purpose area for user program and ISP EEPROM function 0x1780 0x17F7 General purpose area for user program Do not execute ISP 0x17F8 0x17FF Reserved area Do not execute ISP ROM security rule is even address ROM data protected and outputs 0x0000 5 TECHNOLOGY CO LTD Page 16 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP 2 1 1 RESET VE
212. o A1POINT OXOOFF JMP A2POINT ACC 2 jump to A2POINT 0X0100 JMP ASPOINT 3 jump to 0X0101 JMP A4POINT ACC 4 jump to A4POINT After compiling program ROM address BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X0100 JMP AOPOINT ACC 0 jump to AOPOINT 0 0101 A1POINT ACC 1 jump to A1POINT 0X0102 JMP A2POINT ACC 2 jump to A2POINT 0 0103 3 jump to 0 0104 A4POINT ACC 4 jump to A4POINT 5 TECHNOLOGY LTD Page 23 Version 1 4 NONA 2 1 5 CHECKSUM CALCULATION SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP The last ROM address are reserved area User should avoid these addresses last address when calculate the Checksum value gt Example The demo program shows how to calculated Checksum from 00H to the end of user s code MOV USER CODE L BOMOV END ADDR1 A Save low end address to end addr1 MOV USER CODE M BOMOV END ADDR2 A Save middle end address to end addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H BOBSET FC Clear C flag ADD DATA1 A Add A to Datat MOV A R ADC DATA2 A Add R to Data2 JMP END CHECK Check if the YZ address the end of code AAA INCMS Z 2 2 1 B If Z calculate to next address JMP Y ADD 1 2 increase Y END CHECK MOV A END
213. o not measure the RC frequency directly from XIN the probe impendence will affect the RC frequency 4 8 SYSTEM CLOCK TIMING Parameter Description Typical Hardware configuration time 2048 Fi nc 128ms Fi gc 16KHz Oscillator start up time The start up time is depended on oscillator s material factory and architecture Normally the low speed oscillator s start up time is lower than high speed oscillator The RC type oscillator s start up time is faster than crystal type oscillator Oscillator warm up time Power On Reset Timing Oscillator warm up time of reset condition 2048 Fhosc Power on reset LVD reset watchdog reset external reset pin active 64ms 32KHz 512us 9 4MHz 128us 9 16MHz Oscillator warm up time of power down mode wake up condition 2048 Fhosc Crystal resonator type oscillator e g 32768Hz crystal 4 2 crystal 16MHz crystal RC type oscillator e g external RC type oscillator internal high speed RC type oscillator X tal 64ms 32KHz 512us 9 4MHz 128us 9 16MHz RC 8us 4MHz 2us Fnos 16MHz Oscillator Tcfg Tost Vdd Power On Reset Flag T 5 Instruction Cycle External Reset Pin Reset Timing 5 TECHNOLOGY CO LTD Page 55 Version 1 4 N N V SN8F27E60 Series 2 NS 8 Bit Flas
214. o system clock Program executing Power on sequence is finished and program executes from ORG 0 3 3 WATCHDOG RESET Watchdog reset is a system protection In normal condition system works well and clears watchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following Watchdog timer status System checks watchdog timer overflow status If watchdog timer overflow occurs the System is reset System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 Watchdog timer application note is as following Before clearing watchdog timer check I O status and check RAM contents can improve system error Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 4 BROWN OUT RESET The brown out reset is a p
215. o trigger T1 timer counting and falling edge to stop T1 timer If set CPTStart bit at high pulse duration the capture timer will measure next high pulse until the rising edge occurrence When the end of measuring high pulse width and T1 timer stops the T1IRQ sets as 1 the T1 interrupt executes as 1 1 and 16 bit counter stores the period of high pulse width 8 6 5 3Low Pulse Width Measurement T1ENB 1 1 CPTG 1 0 10 Input Signal 000 N 0 0000 Initialization Initialization T1 is counting T1 16 bit Counter T1CH T1CL Un know Data 0x 1 n is the low pulse width period Read it by program through CPTStart 1 Falling Edge Rising Edge registers T1 starts to count T1 stops counting CPTStart 0 The low pulse width measurement is using falling edge to start T1 timer counting and rising edge to stop T1 timer If set CPTStart bit at low pulse duration the capture timer will measure next low pulse until the falling edge occurrence When the end of measuring low pulse width and T1 timer stops the sets as 1 the T1 interrupt executes as 1 and T1CH 16 bit counter stores the period of low pulse width SONiX TECHNOLOGY CO LTD Page 117 Version 1 4 N 7 SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 6 5 4Input Cycle Measurement T1ENB 1 CPTEN 1 CPTG 1 0 11
216. on Note After disable open drain function I O mode returns to last I O mode SONiX TECHNOLOGY CO LTD Page 85 Version 1 4 N 7 SN8F27E60 Series S NS E 8 Flash Micro Controller with Embedded ICE and ISP 8 TIMERS 8 1 WATCHDOG TIMER The watchdog timer WDT is a binary up counter designed for monitoring program execution If the program goes into the unknown status by noise interference watchdog timer overflow signal raises and resets MCU Watchdog timer clock source is internal low speed oscillator 16KHz RC type and through programmable pre scaler controlled by code option Watchdog timer interval time 256 1 Internal Low Speed oscillator frequency WDT Pre scalar sec 256 16KHz WDT Pre scaler sec Internal low speed oscillator WDT pre scaler Watchdog interval time Flosc 4 256 16000 4 64ms Flosc 8 256 16000 8 128ms Flosc 16 256 16000 16 256ms Flosc 32 256 16000 32 512ms Flosc 16KHz The watchdog timer has three operating options controlled WatchDog code option Disable Disable watchdog timer function Enable Enable watchdog timer function Watchdog timer actives in normal mode and slow mode In power down mode and green mode the watchdog timer stops X Always On Enable watchdog timer function The watchdog timer actives and not stop in power down mode and green mode Note In high noisy
217. on The MSPIRQ will be set on the ninth clock of SCL Clear MSPIRQ by software MSPSTAT register can monitor the status of data transmission In Slave transmission mode an ACK_ signal from master receiver is latched on rising edge of ninth clock of SCL If ACK_ high transmission is complete Slave device will reset logic and waiting another START signal If ACK_ low slave must load MSPBUF which also MSPSR and set CKP 1 to start data transmission again 5 TECHNOLOGY CO LTD Page 149 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP R W 0 Receiving Address R W 1 Transmission Data _ BF 1 Cleared by Software 1 5 is writing by Software interrupt Service Routine Set CKP after writing to MSPBUF MSP Slave Transmission Timing Diagram 12 7 4 General Call Address In MSP bus the first 7 byte is the Slave address Only the address match MSPADR the Slave will response an ACK The exception is the general call address which can address all slave devices When this address occur all devices should response an acknowledge The general call address is a special address which is reserved as all 0 of 7 bytes address The general call address function is control by GCEN bit Set this bit will enable general call address and clear it will disable When GECN 1 following a START signal 8 bit will shift into MSPSR and the address is
218. on WO W7 are reserved for C compiler and recommend not to access W0 W7 by program strongly 5 TECHNOLOGY CO LTD Page 37 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 2 3 ADDRESSING MODE 2 3 1 IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM gt Example Move the immediate data 12H to ACC MOV A 12 To set an immediate data 12H into ACC gt Example Move the immediate data 12H to register BOMOV 12 To set an immediate data 12H into register In immediate addressing mode application the specific RAM must be 0x80 0x8F working register 2 3 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC gt Example Move 0x12 RAM location data into ACC BOMOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC gt Example Move ACC data into 0x12 RAM location BOMOV 12H A To get a content of ACC and save in RAM location 12H of bank 0 2 3 3 INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to access the memory by the data pointer registers H L Y Z Example Indirectly addressing mode with OHL register BOMOV H 0 To clear H register to access RAM bank 0 BOMOV 12 To set an immediate data 12H into L register BOMOV A
219. on the is stalled although peripherals Timers WDT PWM etc remain active When PECMD register is set to execute ISP program and erase operations the program counter stops op code can t be dumped from flash ROM instruction stops operating and program execution is hold not to active At this time hardware depends on ISP operation configuration to do flash ROM erasing and flash ROM programming automatically After ISP operation is finished hardware releases system clock to make program counter running system returns to last operating mode and the next instruction is executed Recommend to add two instructions after ISP operations ISP flash ROM erase time 25ms 1 page 128 word ISP flash ROM program time 28us 1 word ISP flash ROM program time 56us 2 word ISP flash ROM program time 448us 16 word ISP flash ROM program time 896us 32 word X Note 1 Watch dog timer should be clear before the Flash write program or erase operation or watchdog timer would overflow and reset system during ISP operating 2 Besides program execution all functions keep operating during ISP operating e g timer ADC SIO UART MSP interrupt events still active and latch interrupt flags automatically If any interrupt request occurs during ISP operating the interrupt request will be process by program after ISP finishing 5 TECHNOLOGY CO L
220. ondition of bit test instruction is true the PC will add 2 steps to skip next instruction 51 skip if Carry flag 1 JMP COSTEP Else jump to COSTEP COSTEP NOP BOMOV A BUFO Move BUFO value to ACC BOBTSO FZ To skip if Zero flag 0 JMP C1STEP Else jump to C1STEP If the is equal to immediate data or memory the PC will 2 steps to skip next instruction CMPRS A 12 To skip if ACC 12H JMP COSTEP Else jump to COSTEP COSTEP NOP 5 TECHNOLOGY CO LTD Page 31 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Flash Micro Controller with Embedded ICE and ISP If the destination increased by 1 which results overflow of OxFF to 0x00 the PC will add 2 steps to skip next instruction INCS instruction INCS BUFO JMP COSTEP Jump to COSTEP if ACC is not zero COSTEP NOP INCMS instruction INCMS BUFO JMP COSTEP Jump to COSTEP if BUFO is not zero COSTEP NOP If the destination decreased by 1 which results underflow of 0x01 to 0x00 the PC will add 2 steps to skip next instruction DECS instruction DECS BUFO JMP COSTEP Jump to COSTEP if ACC is not zero COSTEP NOP DECMS instruction DECMS BUFO JMP COSTEP Jump to COSTEP if BUFO is not zero COSTEP NOP 5 TECHNOLOGY CO LTD Page 32 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Bit Flash Micro Controller with Embedded ICE and ISP A MULTI ADDRESS J
221. one 8 bit data transferring The duration from SIO transfer end to SIOIRQ START active is about 1 2 SIO clock means the SIO end indicator doesn t active immediately X Note The first step of SIO operation is to setup the SIO pins mode Enable SENB select CPOL bits These bits control SIO pins mode SIO builds in chip selection function to implement SIO multi device mode One master communicating with several slave devices in SIO bus and the chip selection decides the pointed device The chip selection pin is SCS pin and controlled by SCSEN bit The SCS function only supports salve mode SCKMD 1 The SCS includes two phases which are high active and low active controlled by SCSP bit SCSP 1 SCS pin idle mode is high and low active SCSP 0 SCS pin idle mode is low and high active SIO operation is controlled by START bit In SCS enable mode set START bit doesn t mean SIO active The SCS condition is a necessary condition If the SCS status doesn t exist the SIO bus keeps idle status until SCS status meets configuration SIO builds SIOBZ bit to indicate SIO processing status SIOBZ 1 means SIO is processing SIOBZ 0 means SIO is in idle status or the end of SIO processing When SIO bus starts to execute the SIOBZ bit changes to logic high status When SIO bus finishes transmitting the SIOBZ bit changes to logic low status SIOBZ operation of different modes is as below diagram Set START 1 SI
222. ow speed clock is from internal low speed oscillator controlled by CLKMD bit of OSCM register Both high speed clock and low speed clock can be system clock source through a divider to decide the system clock rate High speed oscillator Internal high speed oscillator is 16MHz RC type called IHRC and External high speed oscillator includes crystal ceramic 4MHz 12MHz 32KHz and RC type Low speed oscillator Internal low speed oscillator is 16KHz RC type called ILRC System clock block diagram STPHX HOSC High Fcpu Code Option CLKMD Fcpu Fhosc 1 Fhosc 128 XIN XOUT Fcpu Low Code Option Fcpu Flosc 1 Flosc 8 HOSC High code option Fhosc External high speed clock Internal high speed RC clock Flosc Internal low speed RC clock about 16KHz 93V and 95V Fosc System clock source Fcpu Instruction cycle 4 2 FCPU INSTRUCTION CYCLE The system clock rate is instruction cycle called Fcpu which is divided from the system clock source and decides the system operating rate Fcpu rate is selected by High Fcpu code option and the range is Fhosc 1 Fhosc 128 under system normal mode If the system high clock source is external 4MHz crystal and the High Fcpu code option is Fhosc 4 the Fcpu frequency is 4MHz 4 1MHz Under system slow mode the Fcpu range is Flosc 1 Flosc 8 controlled by Low code option If Low code option is Flosc 4 the
223. ower dropping condition The power drops from normal voltage to low voltage by external factors e g EFT interference or external loading changed The brown out reset would make the system not work well or executing program error VDD System Work Well Area Brown Out Reset Diagram 5 TECHNOLOGY CO LTD Page 45 Version 1 4 N N M SN8F27E60 Series 5 NS 8 Bit Flash Micro Controller with Embedded ICE and ISP The power dropping might through the voltage range that s the system dead band The dead band means the power range can t offer the system minimum operation power requirement The above diagram is a typical brown out reset diagram There is a serious noise under the VDD and VDD voltage drops very deep There is a dotted line to separate the system working area The above area is the system work well area The below area is the system work error area called dead band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC application The power source of DC application is usually using battery When low battery condition and MCU drive any loading the power drops and keeps in dead band Under the situation the power won t drop deeper and not touch the system reset voltage That makes the system under dead band AC application In AC power application
224. p Programmable open drain structure EIDA Embedded ICE data pin P1 2 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change lO wake up Programmable open drain structure SDA MSP data pin 1 3 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up Programmable open drain structure SCL MSP clock pin P1 4 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change Programmable open drain structure SDO SIO data output pin P1 5 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up Programmable open drain structure SDI SIO data input pin P1 6 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change 1 6 5 lO wake up Programmable open drain structure SCK SIO clock pin P1 7 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change P1 7 SCS wake up Programmable open drain structure SCS SIO bus control pin 4 0 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters vo 40 ADC channel 0 input pin P4 1 AIN1 lO 4 1 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters AIN1 ADC channel 1 input pin P4 2 Bi direction pin
225. pply voltage Vdd SN8F27E60L 0 3V 3 6V Input in Voltage VIN Vss 0 2V Vdd 0 2V Operating ambient temperature Topr SN8F27E65 SN8F27E64 5 8 27 62 40 85 C SN8F27E65L SN8F27E64L 5 8 27 62 40 85 Storage ambient temperature he nnne 40 125 C 15 2 ELECTRICAL CHARACTERISTIC SN8F27E60 Series DC CHARACTERISTIC All of voltages refer to Vss Vdd 5 0V Fosc 16MHz ambient temperature is 25 C unless otherwise note PARAMETER DESCRIPTION MIN TYP MAX UNIT Operating vele L40 C 85 C 16MHz ISP is inactive 18 55 v 40 85 Fcpu 16 2 ISP actives 25 55 RAM Data Retention voltage 115 V Vddriserate Vpor Vddriseratetoensureinternal poweronreset 005 V ms Input Low Voltage Allinputports Reset pins vss O 3Vdd V ViH All input ports Reset pin XIN XOUT pins jo7Vdd vdd v VoL Vss 5405 V VoH Vdd 0 5 vdd V 2 uA Vin Vss Vdd XIN XOUT pins 120 Vin Vss Vdd 5V XIN XOUT pins Vin Vss Vdd 1 4 pins 100 Vin Vss Vdd 5V PO P1 P4 P5 pins 50 op Vdd 0 5V XIN XOUT pins
226. r This operation will set the Buffer Full flag BF and allow MSP rate generator start counting After write to MSPBUF each bit of address will be shifted out on the falling edge of SCL until 7 bit address and R W_ bit are complete On the failing edge of eighth clock the master will pull low SDA fort slave device respond with an acknowledge On the ninth clock falling edge SDA is sampled to indicate the address already accept by slave device The status of the ACK bit is load into ACKSTAT status bit Then MSPIRQ bit is set the BF bit is clear and the MRG is hold off until another write to the MSPBUF occurs holding SCL low and allow SDA floating 12 8 8 1BF Status Flag In transmission mode the BF bit is set when user writes to MSPBUF and is cleared automatically when all 8 bit data are shift out 12 8 8 2WCOL Flag If user write to MSPBUF during Transmission sequence in progress the WCOL bit is set and the content of MSPBUF data will unchanged 12 8 8 3ACKSTAT Status Flag In transmission mode the ACKSTAT bit is cleared when the slave has sent an acknowledge _ 0 and is set when slave does not acknowledge ACK 1 A slave send an acknowledge when it has recognized its address including general call or when the slave has properly received the data Write SEN 1 START condition begins From Slave Clear ACKSTAT ACKSTAT 1 SEN 0 SDA Y Transmit Address v Transmission Data
227. r interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next interrupts request The interrupt request signals are stored in INTRQ register INTEN Interrupt Enable Register POOIRQ TOIRQ T1IRQ TCO Time Out Interrupt INTRO TC1IRQ Interrupt Vector Address TC1 Time Out 13 Bit 0008 0014 TC Time Out TC2IRQ Enable Lachs SIO Transmitter End SIOIRQ Gating Global Interrupt Request Signal UTXIRQ URXIRQ MSPIRQ ADCIRQ WAKEIRQ INTO Trigger INT1 Trigger TO Time Out T1 Time Out UART Transmit End UART Receive End MSP ADC Converting End WAKE Note The GIE bit must enable during all interrupt operation 6 2 INTERRUPT OPERATION Interrupt operation is controlled by IRQ and IEN bits The IRQ is interrupt source event indicator no matter what interrupt function status enable or disable The control the system interrupt execution If IEN 0 the system won t jump to interrupt vector to execute interrupt routine If IEN 1 the system executes interrupt operation when each of interrupt IRQ flags actives IENz1andIRQ 1 the program counter points to interrupt vector and execute interrupt service routine When any interrupt requests occurs the system provides to jump to interrupt vector and execute interrupt routine The first procedure is PUSH operation The end proce
228. r with Embedded ICE and ISP 7 3 VO REGISTER pecu 81 T4VO POR DPA REGISTER iie ra aD M Dim enu REM RM 82 7 5 PORT 4 PORTS ADC uM eH mI eid 83 7 6 OPEN DRAIN REGISTER xin ba Rx 85 oec HM 86 1 WATCHDOG TIMER S 86 8 2 TO 8 BIT BASIC TIMER 88 8 21 OVERVIEW aoe 88 6 2 2 Timer Operation C AD 89 8 2 3 TOM MODE REGISTER icio 90 8 2 4 TOC COUNTING REGISTER 55 ail 90 8 2 5 IO TIMER OPERA TION BERXPIZAMIE E rav 91 BO TCOS BIT TIMER COUNTER 92 ex PENCC O 92 8 5 2 TCO TIMER OPERATION 93 8 3 3 TCOM MODE REGISTER Fox a o E TENTI aa re aa 94 8 3 4 TCOC COUNTING REGISTER iara a mut 94 8 3 5 TCOR AUTO RELOAD 95 85 50 TCOD PWM DUTY REGISTER NEE 95 Bo TCO EVENT COUNTER ak aaia ea aE 96 8 3 8 PULSE WIDTH MODULATION 96 8 3 9 TCO TIMER OPERATION EXPLAME 97 Sd TCI TIMER COUNTER Pei ah 99 8 4 OVERVIEW a A aa A ETA 99 642 TCT TIMER OPERATION voi DEA rE
229. ransmit interrupt request 1 UART transmit interrupt request Bit 4 MSPIRQ MSP interrupt request flag 0 None MSP interrupt request 1 MSP interrupt request 5 TECHNOLOGY LTD Page 67 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 5 GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit All interrupts start work after the GIE 1 It is necessary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 14 and the stack add 1 level Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE LVD24 LVD33 STKPB2 STKPB1 STKPBO Read Write R W R R R W RAN R W After reset 0 1 1 1 Bit 7 GIE Global interrupt control bit 0 Disable global interrupt 1 Enable global interrupt Example Set global interrupt control bit GIE BOBSET FGIE Enable GIE Note The GIE bit must enable during all interrupt operation 5 TECHNOLOGY CO LTD Page 68 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 6 EXTERNAL INTERRUPT OPERATION INTO INT1 Sonix provides 2 sets external interrupt sources in the micro controller INTO and INT1 are external interrupt trigger sources and build in edge trigger configuration function When th
230. register gt ADB 9 0 In 10 bit ADC mode the ADC data is stored in ADB and ADR registers 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADB ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 Read Write R R R R R R R R After reset 1 E E Bit 7 0 ADB 7 0 8 bit ADC data buffer and the high byte data buffer of 10 bit ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADR ADCKS1 ADLEN ADCKSO ADB1 ADBO Read Write R W R W R W R R After reset 0 0 0 Bit 3 0 3 0 12 bit low nibble ADC data buffer The AIN input voltage v s ADB output data AIN n 0 1024 VREFH 1 1024 VREFH 1022 1 024 VREFH 1023 1024 VREFH For different applications users maybe need more than 8 bit resolution but less than 10 bit To process the ADB and ADR data can make the job well First the ADC resolution must be set 10 bit mode and then to execute ADC converter routine Then delete the LSB of ADC data and get the new resolution result The table is as following ADC Resolution 8 bit 9 bit 10 bit The initial status of ADC data buffer including ADB register and ADR low nibble after the system reset is unknown 5 TECHNOLOGY CO LTD Page 124 Version 1 4 N N M SN8F27E60 Series 5 NS
231. registers 085H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X XBIT7 XBIT6 XBIT5 XBIT4 2 XBIT1 XBITO Read Write R W R W R W R W R W R W R W R W After reset 5 2 2 7 2 REGISTERS The Y 2 registers are the 8 bit buffers There are three major functions of these registers Can be used as general working registers Can be used as RAM data pointers with YZ register Can be used as ROM data pointer with the MOVC instruction for look up table 084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Y YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBITO Read Write R W R W R W R W R W R W R W R W After reset 5 5 5 5 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBITO Read Write R W R W R W R W R W R W R W R W After reset z Example Uses Y Z register as the data pointer to access data the RAM address 025H of BOMOV Y 00 To set RAM bank 0 for Y register BOMOV Z 25 To set location 25H for Z register BOMOV A 2 To read a data into ACC Example Uses the Y Z register as data pointer to clear the RAM data BOMOV Y 0 Y 0 bank 0 BOMOV Z 07FH Z the last address of the data memory area CLR YZ BUF CLR YZ Clear YZ to be zero DECMS Z Z 1 if Z 0 finish the routine JMP CLR_YZ_BUF Not zero CLR YZ END_CLR 5 TECHNOLOGY LTD End of clear general purpose data memory
232. ries 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 8 4 3 TC1M MODE REGISTER TC1M is TC1 timer mode control register to configure TC1 operating mode including TC1 pre scalar clock source PWM function These configurations must be setup completely before enabling TC1 timer 0B8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1M TC1ENB TC1rate2 1 1 TC1CKS1 TC1CKSO PWM1OUT Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 0 PWM10OUT PWM output control bit 0 Disable PWM output function and P5 2 is GPIO mode 1 Enable PWM output function and P5 2 outputs PWM signal Bit 2 TC1CKSO TC1 clock source select bit Bit 3 Bit 6 4 Bit 7 0 1 TC1CKS1 TC1 clock source select bit 0 Internal clock and Fhosc controlled by TC1CKSO bit 1 External input pin PO 1 INT1 and enable event counter function TCOrate 2 0 bits are useless TC1RATE 2 0 TC1 timer clock source select bits 1 50 0 gt 000 Fcpu 128 001 64 010 32 011 Fcpu 16 100 8 101 4 110 Fcpu 2 111 Fcpu 1 TC1CKS0 1 gt 000 Fhosc 128 001 Fhosc 64 010 Fhosc 32 011 Fhosc 16 100 Fhosc 8 101 Fhosc 4 110 Fhosc 2 111 Fhosc 1 TC1ENB TC1 counter control bit 0 Disable TC1 timer 1 Enable TC1 timer 8 4 4 TC1C COUNTING RE
233. rogress Set RSEN will take no effect 2 Abus collision during the Repeat Start condition occurs SDA is sampled low when SCL goes from low to high 12 8 4 1WCOL Status Flag If user write to MSPBUF when Repeat START condition processing then WCOL is set and the content of MSPBUF data is un changed the writer doesn t occur Complete of Start bit SDA 1 Set S bit Hardare clear ESEN bit Write RSEN here land set MSPIRQ Y V SDA 1 J Tec gt P SDA SCL no change 1 1st bit SCL Write to MSPBUF here lt Tuc gt A MRG z Falling edge of ninth clock Repeat Start End of transmission Repeat Start Condition Timing Diagram 5 TECHNOLOGY CO LTD Page 154 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 12 8 5 Acknowledge Sequence Timing An acknowledge sequence is enabled when set ACKEN MSPM2 4 SCL is pulled low when set ACKEN and the content of the acknowledge data bit is present on SDA pin If user whished to reply a acknowledge ACKDT bit should be cleared If not set ACKDT bit before starting a acknowledge sequence SCL pin will be release brought high when MSP rate generator overflow MSP rate generator start a period down counter when SCL is sampled high After this period SCL is pulled low and ACKEN bit is clear automatically by hardware When next MRG overflow again
234. rol bit 0 Disable wakeup interrupt function 1 Enable wakeup interrupt function Bit 1 SIOIEN SIO interrupt control bit 0 Disable SIO interrupt function 1 Enable SIO interrupt function Bit 2 URXIEN UART receive interrupt control bit 0 Disable UART receive interrupt function 1 Enable UART receive interrupt function Bit 3 UTXIEN UART transmit interrupt control bit 0 Disable UART transmit interrupt function 1 Enable UART transmit interrupt function Bit 4 MSPIEN MSP interrupt control bit 0 Disable MSP interrupt function 1 Enable MSP interrupt function 5 TECHNOLOGY CO LTD Page 66 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 6 4 INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register The register includes all interrupt request indication flags Each one of the interrupt requests occurs the bit of the INTRQ register would be set 1 The INTRQ value needs to be clear by programming after detecting the flag In the interrupt vector of program users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request 097H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQO ADCIRQ T1IRQ TC2IRQ TC1IRQ TCOIRQ TOIRQ PO1IRQ POOIRQ Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 POOIRQ External i
235. rt up time is very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master terminal requirement The reset timing diagram is as following Power External Reset VDD LVD Detect Level vss VDD VSS External Reset External Reset High Detect Low Detect Watchdog Overflow Ng Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal System Status system Stop PowerOn External Watchdog Delay Time Reset Delay Reset Delay Time Time 5 TECHNOLOGY CO LTD Page 44 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 3 2 POWER ON RESET The power on reset depend no LVD operation for most power up situations The power supplying to system is a rising curve and needs some time to achieve the normal voltage Power on reset sequence is as following Power up System detects the power voltage up and waits for power stable External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply t
236. s bi direction edge BOBSET FPOOIEN Enable INTO interrupt service BOBCLR FPOOIRQ Clear INTO interrupt request flag BOBSET FGIE Enable GIE Example INTO interrupt service routine ORG 9 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FPOOIRQ Check POOIRQ JMP EXIT INT POOIRQ 0 exit interrupt vector BOBCLR FPOOIRQ Reset POOIRQ 252 INTO interrupt service routine EXIT INT is Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector 5 TECHNOLOGY CO LTD Page 69 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 7 TO INTERRUPT OPERATION When the TOC counter occurs overflow the TOIRQ will be set to 1 however the TOIEN is enable or disable If the TOIEN 1 the trigger event will make the TOIRQ to be 1 and the system enter interrupt vector If the TOIEN 0 the trigger event will make the TOIRQ to be 1 but the system will not enter interrupt vector Users need to care for the operation under multi interrupt situation gt Example TO interrupt request setup BOBCLR FTOIEN Disable TO interrupt service BOBCLR FTOENB Disable TO timer MOV A 20H Set TO clock 64 7 Set TOC initial value 74H BOMOV TOC A Set TO interval 10 ms BOBSET FTOIEN Enable TO interrupt service BOBCLR FTOIRQ Clear TO interrup
237. s high to low edge change and the duration is one bit period The start bit is easily recognized by the receiver 8 bit Data The data format is 8 bit length and LSB transfers first following start bit The one bit data duration is the unit of UART baud rate controlled by register Parity Bit The parity bit purpose is to detect data error condition It is an extra bit following the data stream The parity bit includes odd and even check methods controlled by URXPS UTXPS bits After receiving data and parity bit the parity check executes automatically The URXPC bit indicates the parity check result The parity bit function is controlled by URXPEN UTXPEN bits If the parity bit function is disabled the UART transfer contents remove the parity bit and the stop bit follows the data stream directly Stop Bit The stop bit is like start bit using a simple format to indicate the end of UART transfer The stop bit format is low to high edge change and the duration is one bit period 10 5 BREAK POCKET The break pocket is an empty stream to reset UART bus Break pocket is like a long time zero pocket and the period is 88us 1s Break 88us 1s TX Break Pocket UART builds in a UTXBRK bit to transmit Break pocket When UTXEN 1 enable UART TX function set UTXBRK bit to transmit Break pocket When Break pocket finishes transmitting UTXIRQ is set as 1 and UTXBRK is cleared automatically The period of transmitted break pocket is 25 UART
238. scillator 16M The system high speed clock source is internal high speed 16MHz RC type oscillator In the mode XIN and XOUT pins are bi direction GPIO mode and not to connect any external oscillator device The system high speed clock source is internal high speed 16MHz RC type oscillator The RTC clock source is external low speed 32768Hz crystal The XIN and XOUT pins are defined to drive external 32768Hz crystal and disables GPIO function system high speed clock source is external low cost RC type oscillator The RC oscillator circuit only connects to XIN pin and the XOUT pin is bi direction GPIO mode e 32K X tal The system high speed clock source is external low speed 32768Hz crystal The option only supports 32768Hz crystal and the RTC function is workable 12M X al The system high speed clock source is external high speed crystal ceramic The oscillator bandwidth is 10MHz 16MHz 4M X tal The system high speed clock source is external high speed crystal resonator The oscillator bandwidth is 1MHz 10MHz For power consumption under mode the internal high speed oscillator and internal low speed oscillator stops and only external 32KHz crystal actives under green mode The condition is the watchdog timer can t be Always option or the internal low speed oscillator actives 4 4 2 INTERNAL HIGH SPEED OSCILLATOR RC TYPE IHRC The internal high speed oscilla
239. set 0 0 0 0 0 0 0 Bit 0 PWMOOUT PWM output control bit 0 Disable PWM output function and P5 1 is GPIO mode 1 Enable PWM output function and P5 1 outputs PWM signal Bit 2 TCOCKSO TCO clock source select bit 0 1 Fhosc Bit 3 TCOCKS1 TCO clock source select bit 0 Internal clock Fcpu and Fhosc controlled by TCOCKSO bit 1 External input pin and enable event counter function TCOrate 2 0 bits are useless Bit 6 4 2 01 TCO timer clock source select bits 50 0 gt 000 Fcpu 128 001 64 010 Fcpu 32 011 Fcpu 16 100 8 101 4 110 Fcpu 2 111 Fcpu 1 TCOCKS0 1 gt 000 Fhosc 128 001 Fhosc 64 010 Fhosc 32 011 Fhosc 16 100 Fhosc 8 101 Fhosc 4 110 Fhosc 2 111 Fhosc 1 Bit 7 TCOENB TCO counter control bit 0 Disable TCO timer 1 Enable TCO timer 8 3 4 TCOC COUNTING REGISTER TCOC is TCO 8 bit counter When TCOC overflow occurs the TCOIRQ flag is set as 1 and cleared by program The TCOC decides interval time through below equation to calculate a correct value It is necessary to write the correct value to TCOC register and TCOR register first time and then enable TCO timer to make sure the fist cycle correct After one TCO overflow occurs the TCOC register is loaded a correct value from TCOR register automatically not program 0 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B
240. sh Micro Controller with Embedded ICE and ISP 1 High speed mode T1ENB 1 CPTEN 1 CPTG 1 0 00 Un know Data 0 16 bit Capture Timer Set initial value by program CPTStart 1 T1 16 bit Timer ER 2 TI timer is overflow Capture Timer stops counting CPTStart 0 H Rising edge trigger to count 0 0000 Initialization Input signal rate T1 timer rate Set a unique timer by T1 timer to measure input signal counts Set T1 timer initial value T1CH m and clear capture timer counter CPTCH CPTCL 0x0000 by program Set CPTSatrt bit 1 to start capture timer counting Capture timer and T1 start counting at the first rising edge of input signal When T1 timer overflow occurs OxFFFF to 0x0000 capture timer stops counting CPTStart is cleared 0 automatically and the T1IRQ sets as 1 The capture timer 16 bit counter value CPTCH is the continuous signal s counts 8 6 5 2High Pulse Width Measurement T1ENB 1 CPTEN 1 CPTG 1 0 01 Input Signal T1 16 bit Counter 0x0000 0x0000 XC T1 is counting n is the high pulse width period Read it by program through T1CH T1CL SETS Rising Edge Falling Edge registers T1 starts to count T1 stops counting CPTStart 0 The high pulse width measurement is using rising edge t
241. t s Flag M 157 12 8 9 2 MSPOV Fla 157 157 13 IN SYSTEM PROGRAM FLASH 0 0 2 0 00 158 13 OVERVIEW f 158 13 2 ISP FLASH ROM ERASE 159 13 3 ISP FLASH ROM PROGRAM OPERATION 160 13 4 ISP PROGRAM ERASE CONTROL 163 13 5 ISP ROM ADDRESS REGISTER ter re Ue 163 13 6 ISP RAM ADDRESS 163 13 7 ISP ROM PROGRAMMING LENGTH nennen nennen nennen 164 14 INSTRUCTION TABLE 165 15 ELECTRICAL CHARACTERISTIC c sccccssssscsosessscsccsssecccesrscccesersscsvesssssecesrescsesersecscesesecccessesesessesses 167 15 1 ABSOLUTE MAXIMUM RATING 167 15 2 ELECTRICAL 167 15 3 CHARACTERISTIC GRAPHS iets 169 16 DEVELOPMENT reete cca t ead De er 170 16 1 SMART DEVELOPMENT 1 2 2 40 0 10000 000000000000000000000000000000000000000 00 171 16 2 SNSF27E65 STARTER KIT 172 16 3 EMULATOR DEBUGGER 173 16 4 PROGRAMMER
242. t circuit is a simple low voltage detector and can improve brown out reset condition completely Use zener voltage to be the active level When VDD voltage level is above Vz 0 7V the C terminal of the PNP transistor outputs high voltage and operates normally When VDD is below Vz 0 7V the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by zener specification Select the right zener voltage to conform the application 5 TECHNOLOGY CO LTD Page 50 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 3 6 4 Voltage Bias Reset Circuit The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely The operating voltage is not accurate as zener diode reset circuit Use R1 R2 bias voltage to be the active level When VDD voltage level is above or equal to 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs high voltage and operates normally When VDD is below 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by R1 R2 resistances Select the right R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage low
243. t request flag BOBSET FTOENB Enable TO timer BOBSET FGIE Enable GIE Example TO interrupt service routine ORG OBH Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTOIRQ Check TOIRQ JMP EXIT_INT TOIRQ 0 exit interrupt vector BOBCLR FTOIRQ Reset TOIRQ MOV A 74H BOMOV TOC A Reset interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector mode don t reset TOC in interrupt service routine 5 TECHNOLOGY CO LTD Page 70 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 6 8 TCO INTERRUPT OPERATION When the TCOC counter overflows the TCOIRQ will be set to 1 no matter the TCOIEN is enable or disable If the TCOIEN and the trigger event TCOIRQ is set to be 1 As the result the system will execute the interrupt vector If the TCOIEN 0 the trigger event TCOIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the TCOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation gt Example TCO interrupt request setup BOBCLR FTCOIEN Disable TCO interrupt service BOBCLR FTCOENB Disable TCO timer MOV A 10H TCOM A Set TCO clock Fcpu 64 MOV A 74H Set TCOC ini
244. ta 51H 1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H Note The Y register will not increase automatically when Z register crosses boundary from OxFF to 0x00 Therefore user must take care such situation to avoid look up table errors If Z register is overflow Y register must be added one The following INC YZ macro shows a simple method to process Y and Z registers automatically gt Example INC YZ macro INC YZ MACRO INCMS Z 7 1 Not overflow INCMS Y 1 Not overflow ENDM 5 TECHNOLOGY LTD Page 20 Version 1 4 N SN8F27E60 Series D D 6 Bit Flash Micro Controller with Embedded ICE and ISP gt Example Modify above example by YZ macro BOMOV Y TABLE1 M __ set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data 00H ACC 35H INC_YZ Increment the index address for next address lookup data 51H 1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen gt Example Increase Y and 7 register by BOADD ADD instruction BOMOV Y TABLE1 M __ set lookup table s middle address BOMOV Z TABLE1 L To set lookup table s low addr
245. ta Transfer on SCL Falling Edge 2 In Slave Receiver mode Address and Data Received depended on setting Bit 5 D A Data Address bit O Indicates the last byte received or transmitted was address 12 Indicates the last byte received or transmitted was data Bit 4 P Stop bit 0 Stop bit was not detected 1 Indicates that a stop bit has been detected last Note It will be cleared when Start bit was detected Bit 3 S Start bit 0 Start bit was not detected 1 Indicates that a start bit has been detected last Note It will be cleared when STOP bit was detected 5 TECHNOLOGY CO LTD Page 145 Version 1 4 SN8F27E60 Series 8 Flash Micro Controller with Embedded ICE and ISP Bit 2 Bit 0 RED WRT Read Write bit information This bit holds the R W bit information following the last address match This bit is only valid from the address match to the next start bit stop bit or not ACK bit In slave mode 0 Write 1 Read In master mode 0 Transmit is not in progress 1 Transmit is in progress Or this bit with SEN RSEN PEN or ACKEN will indicate if the MSP is in IDLE mode BF Buffer Full Status bit Receive 1 Receive complete MSPBUF is full 0 Receive not complete MSPBUF is empty Transmit 1 Data Transmit in progress does not include the and stop bits MSPBUF is full 0 Data
246. ta byte is loaded into MSPBUF from MSPSR It is cleared automatically when MSPBUF is read 12 8 9 2MSPOV Flag In receive operation the MSPOV bit is set when another 8 bit are received into MSPSR and the BF bit is already set from previous reception 12 8 9 3WCOL Flag If user write to MSPBUF when a receive is already progress the WCOL bit is set and the content of MSPBUF data will unchanged Write ACKEN 1 Start Acknowledge sequence Write ACKEN 1 SDA ACKDT 0 Start Acknowledge sequence SDA ACKDT 1 Write SEN 1 from Master START condition begins From Slave Clear ACKSTAT SDA ACKDT 0 i s pes Seared Write 1 RCEN cleared Write 1 here SEN 0 Write RCEN 1 atomas t y Start next receive Transmit Address to Slave R W 1 Y Receiving Data from Slave Receiving Data from Slave spa Ml 5 aay 1 29575855462 m Y YG Gd ead Voay v Write address and R W to MSPBUF Start transmit ACK_is not 111 sent 1 SCL d Al 117217 31 41 51 61 71 8 9 PI Data shifted in failing edgeof E a eee et MSPIRQ __ Master terminal transfer Set MSPIRQ at the end of receive Set MSPIRQ at the end of v P the ehd of receive MSP RQ Acknowledge sequence I A P bit and MSPIRQ bit is set Cleared
247. ter SDA Embedded ICE interface MP Pro writer Plug on SN8F27E60 MCUs directly e MP III writer For L version the bias circuit must be set on the writer transition board 17 1 WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT MP III Writer Transition Board Pin 1 48 J a 2 e 2 2 2 2 2 2 2 2 e 2 2 2 gt 2 2 1 14 2 al S EDT STET Pin 25 Pin 24 JP3 Mapping to 48 pin text tool DIP 1 1 48 DIP48 DIP 2 2 47 DIP47 DIP 3 3 46 DIP46 DIP 4 4 45 DIP45 DIP 5 5 44 DIP44 DIP 6 6 43 DIP43 DIP 7 7 42 DIP42 DIP 8 8 41 DIP41 DIP 9 9 40 DIP40 DIP10 10 39 DIP39 DIP11 11 38 DIP38 DIP12 12 37 DIP37 DIP13 13 36 DIP36 DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 DIP33 DIP17 17 32 DIP32 DIP18 18 31 DIP31 DIP19 19 30 DIP30 DIP20 20 29 DIP29 DIP21 21 28 DIP28 DIP22 22 27 DIP27 DIP23 23 26 DIP26 DIP24 24 25 DIP25 5 TECHNOLOGY CO LTD Bias Circuit VDD Connect to the VDD pin of MP III transition board 750 Bias Voltage 1500 Connect to the GND pin GND gt ot MP III transition board Writer JP1 JP2 VDD 1 19 20 ALSB PDB JP1 for Writer transition board JP2 for dice and gt 48 pin package Page 175 Version 1 4 SN8F27E60 Series 8 F
248. terrupt service routine first and then processes TO interrupt routine Until finishing processing all interrupt requests gt Example Interrupt Request Occurrence Sequence 2 8 interrupt requests occur during WAKE interrupt service routine execution 1 2 3 4 5 6 7 8 WAKE ADC TC1 TO SIO INTO T1 UART RX Interrupt Processing Sequence 1 2 3 4 5 6 7 8 WAKE INTO TO TC1 T1 ADC SIO UART RX 5 TECHNOLOGY CO LTD Page 18 Version 1 4 NONA SN8F27E60 Series 8 Bit Flash Micro Controller with Embedded ICE and ISP gt Example Defining Interrupt Vector The interrupt service routine is following user program CODE ORG JMP ORG JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP ORG START JMP ISR_WAKE RETI ISR_INTO RETI ISR UART TX RETI ENDP 0 START 8 ISR WAKE ISR INTO ISR ISR TO ISR TCO ISR TC1 ISR TC2 ISR T1 ISR_ADC ISR_SIO ISR_MSP ISR_UART_RX ISR_UART_TX 15H START 0000H Jump to user program address Interrupt vector 0008H Jump to interrupt service routine address 0015 The head of user program User program End of user program The head of interrupt service routine Save and 0x80 0x8F register to buffers Load and 0x80 0x8F register from buffers End of interrupt service routine Save and 0x80 0x8F register to buffers Load
249. tial value 74H BOMOV TCOC A Set TCO interval 10 ms BOBSET FTCOIEN Enable TCO interrupt service BOBCLR FTCOIRQ Clear TCO interrupt request flag BOBSET FTCOENB Enable TCO timer BOBSET FGIE Enable GIE gt Example interrupt service routine ORG OCH Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTCOIRQ Check TCOIRQ JMP EXIT_INT TCOIRQ 0 exit interrupt vector BOBCLR FTCOIRQ Reset TCOIRQ MOV 74H Reset 244 interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 71 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 6 9 TC1 INTERRUPT OPERATION When TC1C counter overflows the TC1IRQ will be set to 1 no matter the TC1IEN is enable or disable If the TC1IEN and the trigger event TC1IRQ is set to be 1 As the result the system will execute the interrupt vector If the TCAIEN 0 the trigger event TC1IRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the TC1IEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example TC1 interrupt request setup BOBCLR FTC1IEN Disable TC1 interrupt service BOBCLR FTC1ENB Disable TC1 timer MOV A 10H
250. ting set TC21RQ and outputs PWM but can t wake up system Clock Source 1 0 00 Ce TC2IRQ TC2 timer overflows 2 set as 1 Reload TC2C from TC2R automatically TC2IRQ is cleared by program TC2 provides different clock sources to implement different applications and configurations TC2 clock source includes Fcpu instruction cycle Fhosc high speed oscillator and external input pin P0 2 controlled by TC2CKS 1 0 bits 20 50 bit selects the clock source is from or Fhosc If 20 50 0 TCO clock source is Fcpu through TC2rate 2 0 pre scalar to decide Fcpu 1 Fcpu 128 If TC2CKS0 1 TC2 clock source is Fhosc through TC2rate 2 0 pre scalar to decide 1 128 TC2CKS1 bit controls the clock source is external input pin or controlled by 20 50 bit If TC2CKS120 TC2 clock source is selected by TC2CKSO bit If TC2CKS1 1 TC2 clock source is external input pin that means to enable event counter function TC2rate 2 0 pre scalar is unless when TC2CKS0 1 or TC2CKS1 1 conditions TC2 length is 8 bit 256 steps and the one count period is each cycle of input clock TC2 Interval Time Fhoscz16MHz Fhosc 4MHz Fcopu Fhosc 4 FcpuzFhosc 4 max ms Unit us ms Unit us 000b Fcpu 128 8 192 32 32 768 001b Fcpu 64 4 096 16 16 384 010b Fcpu 32 2 048 8 8 192 011b Fcpu 16 1 024 4 4 096 100b Fcpu 8 0 512 2 2 048 101b Fcpu 4 0 256 1 1 024 110b Fcpu 2 0 1
251. tive All active All active All inactive External interrupt All active All active All active All inactive Wakeup source PO P1 TO Reset P1 MSP Reset ExtOsc External high speed oscillator XIN XOUT IHRC Internal high speed oscillator RC type ILRC Internal low speed oscillator RC type 1 SIO MSP and UART inactive in slow mode and green mode because the clock source doesn t exist Use firmware to disable SIO MSP UART function before inserting slow mode and green mode 2 InIHRC RTC mode STPHX only controls IHRC not Ext 32K 5 0 IHRC actives STPHXz1 IHRC stops 5 2 NORMAL MODE The Normal Mode is system high clock operating mode The system clock source is from high speed oscillator The program is executed After power on and any reset trigger released the system inserts into normal mode to execute program When the system is wake up from power down mode the system also inserts into normal mode In normal mode the high speed oscillator actives and the power consumption is largest of all operating modes The program is executed and full functions are controllable The system rate is high speed The high speed oscillator and internal low speed RC type oscillator active Normal mode can be switched to other operating modes through register Power down mode is wake up to normal mode Slow mode is s
252. tor is 16MHz RC type The accuracy is 2 under commercial condition When the High code option is 16M or the internal high speed oscillator is enabled 16M The system high speed clock is internal 16MHz oscillator RC type XIN XOUT pins are general purpose 1 pins IHRC RTC The system high speed clock is internal 16MHz oscillator RC type and the real time clock is external 32768Hz crystal XIN XOUT pins connect with external 32768Hz crystal 4 4 3 EXTERNAL HIGH SPEED OSCILLATOR The external high speed oscillator includes 4MHz 12MHz 32KHz and RC type 4MHz 12MHz and 32KHz oscillators support crystal and ceramic types connected to XIN XOUT pins with 20pF capacitors to ground The RC type is a low cost RC circuit only connected to XIN pin The capacitance is not below 100pF and use the resistance to decide the frequency 4 4 4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT CRYSTAL CERAMIC RC Type XIN CRYSTAL 20pF T Note Connect the Crystal Ceramic and as near as possible 10 the XIN XOUT VSS pins of micro controller Connect the R and C as near as possible to the VDD pin of micro controller 5 TECHNOLOGY LTD Page 53 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 4 5 SYSTEM LOW SPEED CLOCK The system
253. truction RETI is executed 09AH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTENO ADCIEN T1IEN TC2IEN TC1IEN TCOIEN TOIEN PO1IEN POOIEN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 POOIEN External interrupt INTO control bit 0 Disable INTO interrupt function 1 Enable INTO interrupt function Bit 1 PO1IEN External PO 1 interrupt INT1 control bit 0 Disable INT1 interrupt function 1 Enable INT1 interrupt function Bit 2 TOIEN TO timer interrupt control bit 0 Disable TO interrupt function 1 Enable TO interrupt function Bit 3 TCOIEN TCO timer interrupt control bit 0 Disable TCO interrupt function 1 Enable TCO interrupt function Bit 4 TC1IEN TC1 timer interrupt control bit 0 Disable TC1 interrupt function 1 Enable TC1 interrupt function Bit 5 TC2IEN 2 timer interrupt control bit 0 Disable TC2 interrupt function 1 Enable TC2 interrupt function Bit 6 T1IEN T1 timer interrupt control bit 0 Disable T1 interrupt function 1 Enable T1 interrupt function Bit 7 ADCIEN ADC interrupt control bit 0 Disable ADC interrupt function 1 Enable ADC interrupt function 09BH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN1 MSPIEN UTXIEN URXIEN SIOIEN WAKEIEN Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 WAKEIEN Wakeup interrupt cont
254. u 4MHz 4 1MHz Select 001 Fcpu 128 TO interval time 10ms TO clock rate 4MHz 4 128 TOC initial value 256 TO interval time input clock 256 10ms AMHz 4 128 256 10 2 4 106 4 128 B2H Note RTC mode TOC is 256 counts 0 5 sec interval time Don t change TOC value RTC mode 5 TECHNOLOGY CO LTD Page 90 Version 1 4 N N M SN8F27E60 Series 5 NS a X 8 Bit Flash Micro Controller with Embedded ICE and ISP 8 2 5 TO TIMER OPERATION EXPLAME TO TIMER CONFIGURATION Reset TO timer MOV A 0x00 Clear TOM register BOMOV TOM A Set TO clock source and rate MOV A 0nnn0000b BOMOV TOM A Set TOC register for TO Interval time MOV A value BOMOV TOC A Clear TOIRQ BOBCLR FTOIRQ Enable TO timer and interrupt function BOBSET FTOIEN Enable TO interrupt function BOBSET FTOENB Enable TO timer TOworks in RTC mode Reset TO timer MOV A 0x00 Clear TOM register BOMOV TOM A Set TO RTC function BOBSET FTOTB Clear TOC CLR TOC Clear TOIRQ BOBCLR FTOIRQ Enable TO timer and interrupt function BOBSET FTOIEN Enable TO interrupt function BOBSET FTOENB Enable TO timer 5 TECHNOLOGY CO LTD Page 91 Version 1 4 N 7 SN8F27E60 Seri 6 x 8 Bit Flash Micro Controller with Embedded ICE 8 3 8 TIMER COUNTER 8 3 1
255. uction lt 1 M 1 f M b 0 then skip next instruction f M b 1 then skip next instruction f M bank 0 b 0 then skip next instruction f M bank 0 b 1 then skip next instruction M A OR _ o Ke o ojojo 0 7 1 Else Z 0 4 15 14 lt RomPages1 0 13 0 d 1 1 1 CALL d Stack lt 15 15 14 RomPages1 0 13 lt d 2 CALLHL Stack lt 15 PC15 PC8 lt H register 7 lt L register 5 5 2 SONiX TECHNOLOGY CO LTD Page 165 Version 1 4 S NN SN8F27E60 Series 8 Flash Micro Controller with Embedded ICE and ISP CALLYZ Stack lt 15 PC15 PC8 Y register 7 Z register M PC lt Stack lt Stack and to enable global interrupt S RETLW PC lt Stack and load to ACC Note 1 is system register RAM If M is system registers then 0 otherwise 1 2 If branch condition is true then S 1 otherwise S 0 5 TECHNOLOGY CO LTD Page 166 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 1 5 ELECTRICAL CHARACTERISTIC 15 1 ABSOLUTE MAXIMUM RATING Supply voltage Vdd SN8F27E60 eene ehe menie 0 3 6 0V Su
256. under dead band The external reset information is described in the next section 5 TECHNOLOGY CO LTD Page 48 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 3 5 EXTERNAL RESET External reset function is controlled by Reset Pin code option Set the code option as Reset option to enable external reset function External reset pin is Schmitt Trigger structure and low level active The system is running when reset pin is high level voltage input The reset pin receives the low voltage and the system is reset The external reset operation actives in power on and normal running mode During system power up the external reset pin must be high level input or the system keeps in reset status External reset sequence is as following External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 The external reset can reset the system during power on duration and good external reset circuit can protect the system to avoid working at unusual power condition e g brown out reset in AC power
257. urce is from Fcpu or Fhosc If TC1CKS0 20 TC1 clock source is through TC1rate 2 0 pre scalar to decide Fcpu 1 Fcpu 128 If TC1CKS0 1 TCO clock source is Fhosc through TC1rate 2 0 pre scalar to decide 1 128 TC1CKS1 bit controls the clock source is external input pin or controlled by TC1CKSO bit If TC1CKS120 TC1 clock source is selected by TC1CKSO bit If 1 1 1 TCO clock source is external input pin that means to enable event counter function TC1rate 2 0 pre scalar is unless when TC1CKS0 1 or TC1CKS1 1 conditions TC1 length is 8 bit 256 steps and the one count period is each cycle of input clock TC1 Interval Time Fhoscz16MHz Fhosc 4MHz Fcopu Fhosc 4 FcpuzFhosc 4 max ms Unit us ms Unit us 000b Fcpu 128 8 192 32 32 768 001b Fcpu 64 4 096 16 16 384 010b Fcpu 32 2 048 8 8 192 011b Fcpu 16 1 024 4 4 096 100b Fcpu 8 0 512 2 2 048 101b 4 0 256 1 1 024 1106 2 0 128 0 5 0 512 1110 Fcpu 1 0 064 0 25 0 256 000b Fhosc 128 2 048 8 8 192 001b Fhosc 64 1 024 4 4 096 010b Fhosc 32 0 512 2 2 048 011b Fhosc 16 0 256 1 1 024 100b Fhosc 8 0 128 0 5 0 512 101b Fhosc 4 0 064 0 25 0 256 110b Fhosc 2 0 032 0 125 0 128 111b Fhosc 1 0 016 0 0625 0 064 TC1CKSO TCirate 2 0 TC1 Clock 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 5 TECHNOLOGY CO LTD Page 100 Version 1 4 N N M SN8F27E60 Se
258. val time 10ms So the PWM cycle is 100Hz In 1 3 duty condition the high pulse width is about 3 33ms TCOD initial value B2H PWM high pulse width period clock rate B2H 3 33ms 16MHz 16 128 B2H 5 TECHNOLOGY CO LTD Page 95 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 8 3 7 EVENT COUNTER TCO event counter is set the TCO clock source from external input pin P0 0 When TCOCKS1 1 TCO clock source is switch to external input pin P0 0 TCO event counter trigger direction is falling edge When one falling edge occurs TCOC will up one count When TCOC counts from OxFF to 0x00 TCO triggers overflow event The external event counter input pin s wake up function of GPIO mode is disabled when TCO event counter function enabled to avoid event counter signal trigger system wake up and not keep in power saving mode The external event counter input pin s external interrupt function is also disabled when TCO event counter function enabled and the POOIRQ bit keeps 0 status The event counter usually is used to measure external continuous signal rate e g continuous pulse R C type oscillating signal These signal phase don t synchronize with MCU s main clock Use TCO event to measure it and calculate the signal rate in program for different applications External Input Signel m 0x00
259. verified without debugger platform en 5 TECHNOLOGY CO LTD Page 170 Version 1 4 N N 7 SN8F27E60 Series 5 NS E 8 Flash Micro Controller with Embedded ICE and ISP 16 1 SMART DEVELOPMENT ADAPTER Smart Development Adapter is a high speed emulator for Sonix Embedded ICE type flash MCU It debugs and programs Sonix flash MCU and transfers MCU s system status RAM data and system register between M2IDE and Sonix flash MCU through USB interface The other terminal connected to SN8F27E65 Starter kit or Target board is a 4 wire serial interface In addition to debugger functions the Smart Starter Kit system also may be used as a programmer to load firmware from PC to MCU for engineering production even mass production Smart Development Adapter communication with SN8F27E65 flash MCU is through a 4 wire bus The pin definition of the Modular cable is as following VSS EIDA EICK VDD The modular cable can be inserted into SN8F27E65 Starter Kit plugged into the target board or inserted into a matching socket at the target device on the target board Application SN8F27E65 E F 2 Starter kit USB Cable to PC Modular Cable Target Board Socket connectors connect to Sonix Embedded ICE IC Socket of target Smart Development Adapter If the target board of application is designed and ready the modular cable can be inserted into the target directly to replace SN8F27E65 Starter Kit Design the 4 wire i
260. witched to normal mode Green mode from normal mode is wake up to normal mode 5 TECHNOLOGY CO LTD Page 59 Version 1 4 N N M SN8F27E60 Series 5 NS E 8 Bit Flash Micro Controller with Embedded ICE and ISP 5 3 SLOW MODE The slow mode is system low clock operating mode The system clock source is from internal low speed RC type oscillator The slow mode is controlled by CLKMD bit of OSCM register When CLKMD 0 the system is in normal mode When 1 the system inserts into slow mode The high speed oscillator won t be disabled automatically after switching to slow mode and must be disabled by SPTHX bit to reduce power consumption In slow mode the system rates are Flosc 1 Flosc 2 Flosc 4 Flosc 8 Flosc is internal low speed RC type oscillator frequency controlled by code option The program is executed and full functions are controllable The system rate is low speed Flosc 1 Flosc 2 Flosc 4 Flosc 8 controlled by code option The internal low speed RC type oscillator actives and the high speed oscillator is controlled by STPHX 1 In slow mode to stop high speed oscillator is strongly recommendation Slow mode can be switched to other operating modes through OSCM register Power down mode from slow mode is wake up to normal mode Normal mode is switched to slow mode Green mode from slow mode is wake up to slow mode 5 4 POWER DOWN MDOE The power down mode is the system ideal status No program execution
261. y in interrupt procedure T1 timer can works in normal mode slow mode and green mode Clock Source ES En 0x0000 or 0x0001 0x0002 0x0002 0 0000 or n by program ur re E T1IRQ 1 timer overflows T1IRQ set as 1 Reload T1CH by program T1IRQ is cleared by program 5 TECHNOLOGY CO LTD Page 113 Version 1 4 N SN8F27E60 Series E 8 Bit Flash Micro Controller with Embedded ICE and ISP T1 provides different clock sources to implement different applications and configurations T1 clock source includes Fcpu instruction cycle and Fhosc high speed oscillator controlled by T1CKS bit T1CKS bit selects the clock source is from Fcpu or Fhosc If T1CKS 0 T1 clock source is Fcpu through T1rate 2 0 pre scalar to decide Fcpu 1 128 If T1CKS 1 T1 clock source is Fhosc through T1rate 2 0 pre scalar to decide Fcpu 1 Fcpu 128 T1 length is 16 bit 65536 steps and the one count period is each cycle of input clock T1 Interval Time Fhoscz16MHz Fhosc 4MHz 5 4 FcpuzFhosc 4 2 0 T1 Clock max ms Unit us max ms Unit us 000b Fcpu 128 2097 152 32 8388 608 001b 64 1048 576 16 4194 304 0100 Fcpu 32 524 288 8 2097 152 011b Fcpu 16 262 144 1048 576 100b Fcpu 8 131 072 524 288 101b Fcpu 4 65 536 262 144

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