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W741E260 - SeekDataSheet

1. Winbond Electronics Corp BitO 2 0 RB 0 works as output pin Bit0 1 RB 0 works as input pin Bit 1 20 1 works as output pin 1 RB 1 works as input pin Bit2 20 RB 2 works as output pin Bit 2 1 RB 2 works as input pin Bit 3 20 RB 3 works as output pin Bit 1 RB 3 works as input pin At initial reset the port RB is input mode PM2 1111B Input Ports RC amp RD Port RC consists of pins 0 to RC 3 and port RD consists of pins 0 to RD 3 Each pin of port RC and port RD can be connected to a pull up resistor which is controlled by the port mode 0 register PMO When the PEF HEF and IEF corresponding to the RC port are set a signal change on the specified pins of port RC will execute the hold mode release or interrupt subroutine Port status register 0 PSRO records the status of ports RC i e any signal changes on the pins that make up the port PSRO can be read out and cleared by the MOV R PSRO and CLR PSRO instructions In addition the falling edge signal on the pin of port RC specified by the instruction MOV SEF 1 will cause the device to exit the stop mode Refer to and the instruction table for more details The RD port is used as input port only it has no hold mode release wake up stop mode or interrupt functions Port Status Register 0 PSRO Port status register 0 is organized as 4 bit binary register PSRO 0 to PSRO 3 PSRO can be read cleared by the MOVA R P
2. Winbond Electronics Corp Interrupts W741E260 provides four internal interrupt sources Divider 0 Divider 1 Timer 0 Timer 1 and one external interrupt source port RC for W741C260 body or three internal interrupt sources Divider 0 Timer 0 Timer 1 and two external interrupt sources RC INT pin for W741C250 body Vector addresses for each of the interrupts are located in the range of program memory ROM addresses 004H to 020H The flags IEF PEF and EVF are used to control the interrupts When EVF is set to 1 by hardware and the corresponding bits of IEF and PEF have been set by software an interrupt is generated When an interrupt occurs all of the interrupts are inhibited until the EN INT or MOV IEF 7H instruction is invoked The interrupts can also be disabled by executing the DIS INT instruction When an interrupt is generated in hold mode the hold mode will be released momentarily and interrupt subroutine will be executed After the instruction is executed in interrupt subroutine the will enter hold mode again The operation flow chart is shown in Figure 1 The control diagram is shown below Initial R EN INT nitial Reset MOV IEF 1 Enable Divider 0 overflow signal EVF 0 4 IEF 0 Timer 0 underflow signal IEEA ze si v Interrupt Interrupt 008 L Process e Vector
3. Note R means read only HCF 0 1 Hold mode was released by overflow from the divider 0 HCF 1 1 Hold mode was released by underflow from the timer 0 HCF 2 1 Hold mode was released by a signal change at port RC HCF 3 is reserved HCF 4 1 Hold mode was released by overflow from the divider 1 for W741C260 body Hold mode was released by a falling edge signal at the INT pin for W741C250 body HCF 5 1 Hold mode was released by underflow from the timer 1 HCF 6 and HCF 7 are reserved Publication Release Date March 1998 25 Revision A2 W741E260 Winbond Electronics Corp Event Flag EVF The event flag is organized as 8 bit binary register to EVF 7 It is set by hardware and reset by CLR 1 instruction or the occurrence of an interrupt The bit descriptions are as follows 7 6 5 4 3 2 1 0 R means read only EVF 0 1 Overflow from divider 0 occurred EVF 1 1 Underflow from timer 0 occurred EVF 2 1 Signal change at port RC occurred EVF 3 is reserved EVF 4 1 Overflow from divider 1 occurred for W741C260 body Falling edge signal at the INT pin occurred for W741C250 body EVF 5 amp EVF 6 are reserved EVF 721 Underflow from Timer 1 occurred Reset Function The W741E260 is reset either by a power on reset or by using the external RES pin The initial state of the W741E260 after the reset function is execu
4. Circuit 014H QL L 6 IEF 2 Divider 1 V LET L 020H overflow signal M 1 underflow IEF 7 Initial Reset Disable f CLR EVF l instruction X DIS INT instruction Figure 10 Interrupt Event Control Diagram Interrupt Enable Flag IEF The interrupt enable flag is organized as 8 bit binary register IEF 0 to IEF 7 These bits are used to control the interrupt conditions It is controlled by the MOV IEF l instruction When one of these interrupts is accepted the corresponding to the bit of the event flag will be reset but the other bits are unaffected In interrupt subroutine these interrupts will be disabled till the instruction MOV or EN INT is executed again Otherwise these interrupts can be disabled by executing DIS INT instruction The bit descriptions are as follows 22 W741E260 Winbond Electronics Corp 7 6 5 4 3 2 1 0 e Note W means write only IEF 02 1 Interrupt O is accepted by overflow from the Divider O IEF 121 Interrupt 1 is accepted by underflow from the Timer IEF 2 1 Interrupt 2 is accepted by a signal change at port RC IEF 3 is reserved IEF 4 1 Interrupt 4 is accepted by overflow from the Divider 1 for W741C260 body Interrupt 4 is accepted by a fall
5. Publication Release Date March 1998 57 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Increment R content Machine Cycle 1 Operation ACC lt 1 Description Increment the data memory content and load the result into the ACC and the data memory Flag Affected CF amp ZF Jump when bit 0 of ACC is 1 1 Machine Cycle Operation PC10 PCO L10 LO if ACC 0 1 Description If bit 0 of the ACC is 1 PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If bit 0 of the ACC is 0 the program counter PC is incremented Jump when bit 1 of ACC is 1 4 Machine Cycle Operation PC10 PCO L10 LO if ACC 1 1 Description If bit 1 of the ACC is 1 PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If bit 1 of the ACC is 0 the program counter PC is incremented 58 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Jump when bit 2 of ACC is 1 Machine Cycle 1 Operation PC10 PCO lt L10 LO if ACC 2 1 Description If bit 2 of the ACC is 1 PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If bit 2 of the ACC is 0 the program counter PC is incremented Jump w
6. R MOV TM1 l Timer 1 set Subroutine CALL STACK lt PC 1 PC10 PCO amp L10 LO RTN STACK Other 1 These instructions are available W741C260 body but inhibited in W741C250 body 2 The bitO bit and bit2 of PMF are reserved W741C250 and W741C260 body Publication Release Date March 1998 47 Revision A2 W741E260 Winbond Electronics Corp INSTRUCTION SET TABLE 2 ACC Add R to ACC with CF Machine Cycle Operation lt CF Description The contents of the data memory location addressed by R6 to RO ACC and CF are binary added and the result is loaded into the ACC Flag Affected CF amp ZF ADC WR Add immediate data to WR with CF 1 Machine Cycle Operation lt WR 1 CF Description The contents of the Working Register WR and CF are binary added and the result is loaded into the ACC Flag Affected CF amp ZF ADCR R ACC Add R to ACC with CF Machine Cycle Operation lt ACC CF Description The contents of the data memory location addressed by R6 to RO ACC and CF are binary added and the result is placed in the ACC and the data memory Flag Affected amp ZF 48 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued ADCR WR 1 Add immediate data to WR with CF 1 Machine
7. after of instruction EVFO caused by overflow from the divider 0 is reset EVF1 caused by underflow from the timer 0 is reset 10 17 EVF4 caused by overflow from the divider 1 is reset for W741C260 body EVF4 caused by the falling edge signal on INT pin is reset for W741C250 body LE EVF7 caused by underflow from the timer 1 is reset CLR PSRO Clear Port Status Register 0 RC port signal change flag Machine Code Machine Cycle Operation Description Machine Code Machine Cycle Operation Description 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 Clear Port Status Register 0 RC port signal change flag When this instruction is executed the RC port signal change flag PSRO is cleared Reset the last 4 bits of the WatchDog Timer 4 Reset the last 4 bits of the watchdog timer When this instruction is executed the last 4 bits of the watchdog timer are reset Publication Release Date March 1998 55 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Decrement R content 4 Machine Cycle Operation lt 1 Description Decrement the data memory content and load result into the ACC and the data memory Flag Affected CF amp ZF DIS INT Disable Interrupt function 4 Operation Disable interrupt function Description Interrupt function is inhibited by executing th
8. 32 seas s2420 2160 69 38970 21410 so waz zw 40 W741E260 Winbond Electronics Corp TYPICAL APPLICATION CIRCUIT LCD PANEL Output Signal 1 3 Bias 1 4 Duty Connect to capacitor and VDD to generate LCD voltage Publication Release Date March 1998 4I Revision A2 W741E260 Winbond Electronics Corp INSTRUCTION SET TABLE Symbol Description ACC Accumulator ACC n Accumulator bit n WR Working Register PAGE Page Register MRO Mode Register 0 Mode Register 1 Port Mode 0 Port Mode 1 PM2 Port Mode 2 PSRO Port Status Register 0 PSR1 Port Status Register 1 R Memory RAM of address R LCDR LCD data RAM of address LDR R n Memory bit n of address R I Constant parameter L Branch or jump address CF Carry Flag ZF Zero Flag PC Program Counter TMOL Low nibble of the Timer 0 counter TMOH High nibble of the Timer 0 counter TM1L Low nibble of the Timer 1 counter TM1H High nibble of the Timer 1 counter TABL Low nibble of the look up table address buffer TABH High nibble of the look up table address buffer IEF n Interrupt Enable Flag n HCF n HOLD mode release Condition Flag n HEF n HOLD mode release Enable Flag n SEF n
9. Selector XOUT2 Single Dual Clock Single Dual Clock enable disable gt Divider1 X INT4 HCF 4 SCR 3 14 13 bit Figure 4 The Dual Clock Operation Mode Control Diagram 3 2 1 0 w Note W means write only Bit0 0 Main oscillator is selected Fosc Fm 1 Sub oscillator is selected Fosc Fs Bit1 20 Enable Fm 1 Disable Fm Bit 2 Reserved Bit320 14 bit Divider1 is selected 1 13 bit Divider1 is selected Publication Release Date March 1998 IH Revision A2 W741E260 Winbond Electronics Corp Dual clock operation mode Sub oscillator enable SCR 0 0 Fosc Fm Flcd Fs in STOP mode LCD work continue Single clock operation mode Sub oscillator disable SCR not use Main oscillator enable Fosc Fm Flcd Fosc Fosc 32 in STOP mode LCD off Divider Each divider is organized as a 14 bit binary up counter designed to generate periodic interrupts When the main oscillator starts action the is incremented by each clock Fosc When an overflow occurs the DividerO event flag is set to 1 EVF 0 1 The interrupt is executed if the DividerO interrupt enable flag has been set IEF 0 1 and the hold state is terminated if the hold release enable flag has been set HEF 0 1 The last 4 stage of the DividerO can be reset by executing a CLR DIVRO in
10. ode LCD driver outputsforal seg 1 2 sides being unlit LCD driver ae outputs for only T seg on COMO 5 side being lit LCD driver E outputs for only oe seg on COM1 side being lit MN LCD driver s outputs for seg EE on COM0 2 5 sides being lit 32 W741E260 Winbond Electronics Corp 1 3 Bias 1 3 duty Lighting System Example Normal Operating Mode continued LCD driver us outputs for seg 1 2 us sides being lit LCD driver outputs for seg n on 1 2 sides being lit ED 1 3 Bias 1 4 duty Lighting System Example Normal Operating Mode LCD driver outputs for only seg on COMO side being lit LCD driver outputs for only seg on COMI side being lit Publication Release Date March 1998 33 Revision A2 W741E260 Winbond Electronics Corp 1 3 Bias 1 4 duty Lighting System Example Normal Operating Mode continued LCD driver outputs for seg on COMO COM1 sides being lit LCD driver outputs for seg on COM2 3 sides being lit LCD driver outputs for seg on COM1 sides being lit LCD driver outputs for seg on COMO COM2 3 sides being lit LCD driver outputs for seg on COMO COM1 2 3 sides being lit 34 W741E260 Winbond Electronics Corp The power co
11. Falling edge detector Falling edge detector gt Wake up from STOP mode Falling edge 9 detector Falling detector Figure 9 Architecture of Input RC Output Port RE When the MOV RE R instruction is executed the data in the RAM will be output to port RE and it provides a high sink current to drive LEDs MFP Output Pin MFP The MFP output pin can output the Timer 1 clock or the modulation frequency the output of the pin is determined by mode register 1 MR1 The configuration of MFP is shown in Figure 9 When bit 2 of MR1 is reset to 0 the MFP output can deliver a modulation output in any combination of one signal from among DC 4096Hz 2048Hz and one or more signals from among 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz or 1 Hz when using a 32 768 KHz crystal The MOV l instruction is used to specify the 2 W741E260 Winbond Electronics Corp modulation output combination The data specified by the 8 bit operand and the MFP output pin are shown below Fosc 32 768 KHz 2 T C Tt m _ 0 _ 0 _ 0 9 EAEN EATE kare EAEN 6 EMEN an ofi oo Lee _ 0 9 _ 0 9 EATA EARS ESRA 4 Publication Release Date March 1998 2l Revision A2 W741E260
12. clock input is Fosc 1024 When the corresponding option code bit of the WDT is set to 0 and the WDT function is disabled The organization of the and watchdog timer is shown in Figure 5 12 W741E260 Winbond Electronics Corp Divider0 HEF 0 Hold mode release HCF 0 IEF 0 DividerO interrupt INTO L 1 Reset 2 CLR EVF 01H 3 CLR DIVRO WDT Fosc 16384 Overflow signal 024 1 m Sm ds i R R R R Enable LR Disable Reset Mask Option 2 CLR WDT Figure 5 Organization of Divider0 and Watchdog Timer Parameter Flag PMF The parameter flag is organized as a 4 bit binary register PMF 0 to PMF 3 The PMF is controlled by the SET PMF 1 or CLR PMF 1 instruction The bit descriptions are as follows 3 2 1 0 pee W means write Bit 0 Bit2 Reserved Bit320 Thefundamental frequency of the watchdog timer is Fosc 1024 1 The fundamental frequency of the watchdog timer is FOSC 16384 Timer Counter 1 Timer 0 TMO Timer 0 TMO is a programmable 8 bit binary down counter The specified value can be loaded into by executing the MOV TMOL TMOH or MOV instructions When the MOV TMOL TMOH R instructions are executed the TMO will stop down counting if the TMO is down counting the MRO 3 will be reset to 0 and the specified value
13. l Set Reset Hold mode release Enable Flag Machine Cycle Operation Hold mode release enable flag control Description The HEFO is set so that overflow from the divider 0 caused I0 1 tne HOLD mode to be released H 1 The HEF1 is set so that underflow from the Timer 0 caused the HOLD mode to be released The HEF2 is set so that signal change at port RC caused I2 the HOLD mode to be released The HEF4 is set so that overflow from the divider 1 caused I4 1 the HOLD mode to be released for W741C260 body B The HEF4 is set so that the falling edge signal at the INT pin caused the HOLD mode to be released for W741C250 bogy 17 21 The is set so that underflow from the Timer 1 caused the HOLD mode to be released Publication Release Date March 1998 63 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV IEF 1 Set Reset Interrupt Flag Machine Cycle Operation Interrupt Enable flag Control Description The interrupt enable flag corresponding to the data specified by 17 10 is controlled o The IEFO is set so that interrupt O overflow from the divider 0 is accepted The IEF1 is set so that interrupt 1 underflow from the Timer 0 is accepted The IEF2 is set so that interrupt 2 signal change at port RC is accepted Reserved The IEF4 is set so that interrupt 4 overflow from the divider 1 is ac
14. 2 or 1 3 bias 1 4 duty 1 3 bias driving mode can be selected LCD driver output pins can be used as DC output port by code option Clock source can be main oscillator clock in the single clock operation mode or sub oscillator clock in the dual clock operation mode operation mode is selected by code option MFP output pin Output is software selectable as modulating or nonmodulating frequency Works as frequency output specified by Timer 1 Two built in 14 bit frequency dividers DividerO the clock source is the output of the main oscillator Divider1 the clock source is the output of the sub oscillator Two built in 8 bit programmable countdown timers Timer 0 one of two internal clock frequencies Fosc 4 or Fosc 1024 can be selected Timer 1 includes an auto reload function and one of two internal clock frequencies FOSC or Fosc 64 can be selected or falling edge of pin 0 can be selected output through MFP pin Built in 18 14 bit watchdog timer selectable for system reset Enable Disable the watchdog timer can be controlled by command or by option code the control source command or option code can be determined by another option code Powerful instruction set 118 instructions for W741C260 body 116 instructions for W741C250 body 8 level subroutine include interrupt nesting Up to 1 uS instruction cycle with 4 MHz operating frequency Packaged 80 pin QFP Pub
15. 25 C LCD on unless otherwise specified No load Ext V In dual clock normal operation No load Ext V In dual clock normal operation No load Ext V In dual clock slow operation and Fm is stopped Hold Current Crystal Hold mode No load Ext V type In dual clock normal operation Hold Current RC type Hold mode No load Ext V In dual clock normal operation Hold Current Crystal Hold mode No load Ext V type In dual clock slow operation and Fm is stopped Stop Current Crystal Stop mode No load Ext V type In dual clock normal operation Stop Current Crystal Stop mode No load Ext V type In single clock operation Input Low Voltage Publication Release Date March 1998 37 Revision A2 W741E260 eW nbond Electronics Corp DC Characteristics continued PARAMETER CONDITIONS WIN TYP max Input High Voltage VIH 0 7 VDD V VDD oe MEP Ouput High Votage Wer masa V Port RA RB Output Low VABL IoL 2 0mA V Voltage All Seg ON SEGO SEG31 Sink loL1 VoL 0 4 Current VLCD 0 0V Used as LCD output SEGO SEG31 Drive loH1 VOH 2 4 Current VLCD 3 0V Used as LCD output Segment output low voltage VSL IOL 0 6 mA Segment output high 2 4 voltage Used as DC output Port RE Sink Current Port RE Source Current 0 4 1 2 Input Port Pull up Resistor 100 INT Pulup Resistor ANT RES Pull up Resisto
16. Cycle Operation ACC WR lt WR I CF Description The contents of the Working Register WR CF are binary added and the result is placed in the ACC and the WR Flag Affected CF amp ZF ADD to Machine Cycle Operation lt ACC Description The contents of the data memory location addressed by R6 to RO and are binary added and the result is loaded into the ACC Flag Affected CF amp ZF ADD WR l Add immediate data to WR Machine Code 0 0 0 1 1 1 0 0 I3 12 W3 W2 W1 WO 1 Machine Cycle Operation lt WR Description The contents of the Working Register WR and the immediate data are binary added and the result is loaded into the ACC Flag Affected CF amp ZF Publication Release Date March 1998 49 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued ADDR ACC Add R to ACC Machine Cycle Operation lt ACC Description The contents of the memory location addressed by R6 to RO and are binary added and the result is placed in the ACC and the data memory Flag Affected CF amp ZF ADDR WR Add immediate data to WR 4 Machine Cycle Operation ACC WR lt WR I Description The contents of the Working Register WR and the immediate data are binary added and the result is placed in the ACC and th
17. If bit 3 of R is equal to 1 then skip Machine Cycle 1 Operation PC lt PC 2 3 1 1 Description If bit 3 of R is equal to 1 the program counter is incremented by 2 and skip is produced If bit 3 of R is not equal to 1 the program counter PC is incremented Publication Release Date March 1998 69 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued STOP Enter the STOP mode Machine Cycle 1 Operation STOP oscillator Description Device enters STOP mode When the falling edge signal of RC port is accepted the uC will wake up and execute the next instruction SUB ACC Subtract ACC from R Machine Cycle 1 Operation lt ACC Description The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to RO and the result is loaded into the ACC Flag Affected CF amp ZF SUB WR I Subtract immediate data from WR Machine Cycle 1 Operation lt WR 1 Description The immediate data are binary subtracted from the contents of the WR and the result is loaded into the ACC Flag Affected CF amp ZF 90 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued SUBR ACC Subtract ACC from R Machine Cycle 1 Operation lt ACC Description The contents of the ACC a
18. RD port pull high resistor is enabled 70 W741E260 Winbond Electronics Corp Instruction set table 2 continued MOV PM1 RA port independent Input Output control Machine Cycle 1 Operation RA port 4 pins input output control is independent Description 10 0 RA O is output pin 10 1 RA O is input pin 11 0 RA 1 is output 11 1 RA 1 is input 2 0 RA2 is output pin I2 1 RA 2 is input pin 0 RA 3 is output pin 1 RA 3 is input pin Default condition RA port is input mode PM 1111B MOV 2 RB port independent Input Output control Machine Cycle 1 Operation RB port 4 pins input output control is independent Description 10 0 is output pin 10 1 0 is input pin 11 0 RB 1 is output pin 11 1 RB 1 is input 2 0 2 is output I2 1 RB 2 is input pin 0 RB 3 is output pin 1 RB 3 is input pin Default condition RB port is input mode PM2 1111B Publication Release Date March 1998 71 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued ACC Move ACC content to Machine Cycle 1 Operation lt ACC Description The contents of the ACC are loaded to the data memory location addressed by R6 to RO MOVA R RA Input RA port data to ACC amp R Machine Cycle 1 Opera
19. System Example Normal Operating Mode Unlit LCD driver outputs Lit LCD driver outputs 1 2 Bias 1 2 duty Lighting System Example Normal Operating Mode COMI LCD driver outputs for seg on COMO COMI sides being unlit LCD driver outputs for only seg on COMO side being lit 30 W741E260 Winbond Electronics Corp 1 2 Bias 1 2 duty Lighting System Example Normal Operating Mode continued LCD driver E outputs for um only seg on om COM1 side being lit LCD driver S outputs for eus COM sides being lit 1 2 Bias 1 3 duty Lighting System Example Normal Operating Mode LCD driver outputs for all seg on 1 2 sides being unlit LCD driver outputs for only seg on COMO side being lit LCD driver outputs for only seg on 1 side being lit LCD driver outputs for only seg on 1 sides being lit Publication Release Date March 1998 31 Revision A2 W741E260 Winbond Electronics Corp 1 2 Bias 1 3 duty Lighting System Example Normal Operating Mode continued LCD driver 03 outputs for only NT seg on COM2 ID side being lit LCD driver e outputs for only e seg on 2 E sides being lit 1 3 Bias 1 3 duty Lighting System Example Normal Operating Mode
20. ZF Rotate Right R with CF Machine Cycle 1 Operation ACC n lt R n 1 3 lt CF lt Description The contents of the ACC and the data memory location addressed by R6 to RO are rotated right one bit bit O is rotated into CF and CF is rotated into bit 3 MSB The same contents are loaded into the ACC Flag Affected CF amp ZF Return from subroutine Machine Cycle 1 Operation lt STACK Description The program counter PC10 to PCO is restored from the stack A return from a subroutine occurs Publication Release Date March 1998 65 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued SBC Subtract with Borrow Machine Cycle 1 Operation lt ACC CF Description The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to RO and the result is loaded into the ACC Flag Affected CF amp ZF SBC WR Subtract immediate data from WR with Borrow Machine Cycle 1 Operation lt WR I CF Description The immediate data and CF are binary subtracted from the contents of the WR and the result is loaded into the ACC Flag Affected CF amp ZF SBCR ACC Subtract ACC from R with Borrow 1 Machine Cycle Operation lt CF Description The
21. is loaded into TMO If MRO 3 is set to 1 the event flag 1 EVF 1 is reset and the TMO starts to count When it decrements to FFH Timer 0 stops operating and generates an underflow EVF 1 1 The interrupt is executed if the Timer O interrupt enable flag has been set IEF 1 2 1 and the hold state is terminated if the hold release enable flag 1 has been set HEF 1 1 The Timer 0 clock input can be set as Fosc 1024 or Fosc 4 by setting to 1 or by resetting MRO 0 to 0 The default timer value is Fosc 4 The organization of Timer 0 is shown in Publication Release Date March 1998 I3 Revision A2 W741E260 Winbond Electronics Corp If the Timer 0 clock input is Fosc 4 Desired time interval preset value 1 x 4 x 1 FOSC If the Timer 0 clock input is Fosc 1024 Desired time interval preset value 1 x 1024 x 1 Fosc Preset value Decimal number of Timer 0 preset value and Fosc Clock oscillation frequency 1 Reset 2 CLR EVF 02 3 Reset MRO 3 to 0 4 MOV TMOL R or MOV TMOH R MR0 0 Disable 1 Fosc 1024 8 bit _ o p Hold mode release HCF 1 Fosc A 9o T Down Counter Q gt reci Timer 0 EVF 1L gt Timer 0 interrupt INT1 Enable 1 Set MRO 3 to 1 2 MOV 1 1 Reset 2 CLR EVF 02 MOV TMOH R MOV TMOL R 3 Set 3 to 1 4 MOV 1 MOV T
22. mode is released by overflow from the Divider O Bit 1 HCF1 1 when the HOLD mode is released by underflow from Timer O Bit 2 HCF2 1 when the HOLD mode is released by a signal change on port RC Flag Affected MOVA R PAGE Move Page Register content to ACC amp R Machine Cycle 1 Operation ACC lt Page Register Description The contents of the Page Register PR are loaded to the data memory location addressed by R6 to RO and the ACC Flag Affected ZF 80 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOVA R PSRO Move Port Status Register 0 content to amp 1 Machine Cycle Operation lt RC port signal change flag PSRO Description The contents of the RC port signal change flag PSRO are loaded to the data memory location addressed by R6 to RO and the ACC When the signal changes on any pin of the RC port the corresponding signal change flag should be set to 1 Otherwise it should be 0 Flag Affected ZF MOVA R WR Move WR content to ACC amp R 1 Machine Cycle Operation lt WR Description The contents of the WR are loaded to the ACC and the data memory location addressed by R6 to RO Flag Affected ZF MOVA WR R Move R content to ACC amp WR 1 Machine Cycle Operation ACC WR lt Description The contents of the data memory location addressed by R6 to RO are loaded
23. specified by cause a wake up from the STOP mode The falling edge signal on port RC can be specified independently 10 17 Falling edge signal at port RC Publication Release Date March 1998 75 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Machine Cycle 1 Operation Timer 0 set Description The data specified by 17 to 10 is loaded to the Timer 0 to start the timer MOV TMOL R Move R content to TMOL 4 Machine Cycle Operation TMOL lt Description The contents of the data memory location addressed by R6 to RO are loaded into the TMOL MOV TMOH R Move R content to TMOH Machine code 0 0 0 1 0 1 0 0 1 R6 R5 R2 RO 1 Machine Cycle Operation TMOH lt Description The contents of the data memory location addressed by R6 to RO are loaded into the TMOH Machine Cycle 1 Operation Timer 1 set Description The data specified by I7 to IO is loaded to the Timer 1 to start the timer 76 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV TMI1L R Move R content to TM1L 4 Machine Cycle Operation TM1L lt Description The contents of the data memory location addressed by R6 to RO are loaded into the TM1L MOV TM1H R Move R content to TM1H Machine Cycle Operation TM1H lt Description The contents of the data memo
24. to the WR and the ACC Flag Affected ZF Publication Release Date March 1998 6l Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV TABL R Move R content to TABL Machine Cycle 1 Operation TABL lt R Description The contents of the data memory location addressed by R6 to RO are loaded into the TABL MOV Move content to Machine Cycle 1 Operation TABH lt Description The contents of the data memory location addressed by R6 to RO are loaded into the TABH MOVC R Move look up table ROM addressed by TABL and TABH to R Machine code Machine Cycle 2 Operation WR lt TABH x 10H TABL Description The contents of the look up table ROM location addressed by TABH and TABL are loaded to R 82 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOVC WR 1 Move look up table ROM addressed by l and ACC to WR Machine Cycle 2 Operation WR lt 16 10 x 10H ACC Description The contents of the look up table ROM location addressed by 16 to 10 and the ACC are loaded to R Machine Cycle 1 Operation No Operation ORL OR Rto ACC Machine Code Machine Cycle 1 Operation lt ACC Description The contents of the data memory location addressed by R6 to RO and the ACC are ORed and the re
25. 400 KHz to 4 MHz or low frequency 32 768 KHz oscillation should be selected by code option RC mode attention must be paid to the high low frequency oscillation option because the LCD driver frequency and the ROM code emulation time are related to this option Sub oscillator Connect to 32768 Hz crystal only Used in dual clock operation Memory 2048 x 16 bit program flash EEPROM including 2K x 4 bit look up table 128 x 4 bit data RAM including 16 working registers 32 x 4LCD data RAM 21 input output pins Ports for input only 2 ports 8 pins Input output ports 2 ports 8 pins High sink current for LED driving 1 port 4 pins MFP output pin 1 pin MFP Power down mode Hold function no operation excluding main oscillator and sub oscillator Stop function no operation excluding sub oscillator W741E260 Winbond Electronics Corp Dual clock slow operation mode system is operated by the sub oscillator Fosc Fs and Fm is stopped Five types of interrupts Four internal interrupts Divider0 Divider1 Timer0 Timer1 for W741C260 body three internal interrupts DividerO TimerO Timer1 for W741C250 body One external interrupt RC Port for W741C260 body two external interrupts RC port and INT pin for W741C250 body LCD driver output 32 segment x 4 common Static 1 2 duty 1 2 bias 1 3 duty 1
26. CF content to ACC 0 amp R 0 Machine Cycle 1 Operation lt CF Description The content of CF is loaded to bit 0 of the data memory location addressed by R6 to RO and the ACC The other bits of the data memory and ACC are reset to 0 Flag Affected ZF MOVA R HCFH Move HCF4 7 to ACC amp Machine Cycle 1 Operation R lt HCF4 7 Description The contents of HCF bit 4 to bit 7 HCF4 to HCF7 are loaded to the data memory location addressed by R6 to RO and the ACC The ACC contents and the meaning of the bits after execution of this instruction are as follows HCF4 1 when the HOLD mode is released by overflow from Divide r 1 for Bit 0 the W741C260 body HCF4 1 when the HOLD mode is released by the falling edge signal at the INT pin for the W741C250 bogy HCF7 1 when the HOLD mode is released by underflow from Timer 1 Bit2 Reserved Flag Affected Publication Release Date March 1998 79 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOVA R HCFL Move HCF0 3 to amp Machine Cycle 1 Operation lt HCF0 3 Description The contents of HCF bit 0 to bit HCFO to HCF3 are loaded to the data memory location addressed by R6 to RO and the ACC The ACC contents and the meaning of the bits after execution of this instruction are as follows Bit 0 1 when the HOLD
27. Description If the bit 2 of MR1 is 0 the waveform specified by 17 to IO is delivered at the MFP output pin MFP The relation between the waveform and immediate data is as follows Signal Fose Fosc Fose Fosc Fosc Fosc 256 512 4096 8192 16384 32768 66 W741E260 Winbond Instruction Set Table 2 continued MOV MRO Load immediate data to Mode Register 0 MRO Machine Cycle 1 Operation lt I Description The immediate data are loaded to the MRO MRO bits description 0 The fundamental frequency of Timer 0 is Fosc 4 1 The fundamental frequency of Timer 0 is Fosc 1024 bit 1 Reserved bit 0 Timer 0 stop down counting 1 Timer 0 start down counting Publication Release Date March 1998 67 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV 1 1 Load immediate data to Mode Register 1 MR1 Machine Cycle 1 Operation lt I Description The immediate data are loaded to the MR1 MR1 bit description 0 The internal fundamental frequency of Timer 1 is Fosc 1 The internal fundamental frequency of Timer 1 is Fosc 64 0 The fundamental frequency source of Timer 1 is internal clock 1 The fundamental frequency source of Timer 1 is external clock via RC 0 input 0 The specified waveform of the MFP generator is delivered a
28. EX I XRLR Re_ R EX ACC XRLIR ZF 10 0 lt 10 10 if ACC 1 1 10 0 lt 10 10 if ACC 2 1 NIN PC10 PC0 lt L10 LO if ACC 0 PC10 PCO0 L10 LO if CF 1 ACC 1 PC10 PCO lt L10 LO if ACC 0 DSKZ R ACC lt 1 skip if ACC 0 ZF CF DSKNZ R ACC Re R 1 skip if ACC 0 ZF CF 44 W741E260 Winbond Electronics Corp Instruction Set Table 1 continued Mnemonic Data Move OV WR WR R OV R WR WR WRe R WR ACC Re WR OV R ACC Re ACC MOV ACC R MOV 1 Re MOV WR R WR PR bit2 bit1 bit0 x10H R MOV R WR PR bit2 bitt bit0 x10H lt MOV TABL R TABL lt R MOV MOVC x 10H TABL MOVC WR 1 WR lt 6 10 x 10H ACC Input amp Output MOVA R RA MOVA R RB MOVA R RC ACC Re RC MOVA R RD ACC Re RD MOV RA R RA lt R MOV RBR RB lt R MOV RE R RE lt R MOV 1 MFP lt Flag amp Register ACC R PAGE Page Register PAGEc R OV OV Affected lt mim ACC Mova RRA ACCReA F mova accReRB mova RRC mova RRD E
29. Enable Flag HEF The hold mode release enable flag is organized as an 8 bit binary register to HEF 7 The HEF is used to control the hold mode release conditions It is controlled by the MOV HEF l instruction The bit descriptions are as follows 7 6 5 4 3 2 1 0 Note W means write only HEF 0 1 Overflow from the Divider 0 causes Hold mode to be released 1 1 Underflow from Timer 0 causes Hold mode to be released HEF 2 1 Signal change at port RC causes Hold mode to be released HEF 3 is reserved HEF 4 1 Overflow from the Divider 1 causes Hold mode to be released for W741C260 body Falling edge signal at the INT pin causes Hold mode to be released for W741C250 body HEF 5 amp HEF 6 are reserved 7 1 Underflow from Timer 1 causes Hold mode to be released Hold Mode Release Condition Flag HCF The hold mode release condition flag is organized as a 8 bit binary register HCF 0 to HCF 7 It indicates by which interrupt source the hold mode has been released and is loaded by hardware The HCF can be read out by the MOVA HCFL and MOVA HCFH instructions When any of the HCF bits is 1 the hold mode will be released and the HOLD instruction is invalid The HCF can be reset by the CLR EVF or MOV HEF HEF 0 instructions When EVF and HEF have been reset the corresponding bit of HCF is reset simultaneously The bit descriptions are as follows 7 6 5 4 3 2 1 0 Seres ess ees
30. M 000H to 5FFH are used to store instruction codes only but the last quarter 600 to 7FFH can store both instruction codes and the look up table Each look up table element is composed of 4 bits so the look up table can be addressed up to 2048 elements There are two registers TABL and TABH to be used in look up table addressing and they are controlled by MOV TABH R and MOV TABL R instructions When the instruction MOVC R is executed the contents of the look up table location address specified by TABH TABL and ACC will be read and transferred to the data RAM Refer to the instruction table for more details The organization of the program memory is shown in Figure 1 Publication Release Date March 1998 7 Revision A2 W741E260 Winbond Electronics Corp TABH TABL X X IX X X X X 2048 lt ff address Ofset address 600 Offset 4 This area used to store both instruction code and look up table Each element 4 bits of the look up table 2048 x 16 bit Figure 1 Program Memory Organization Data Memory RAM 1 Architecture The static data memory RAM used to store data is arranged as 128 x 4 bits The data memory can be addressed directly or indirectly The organization of the data memory is shown in Working Register 128 ad
31. MO 1 Figure 6 Organization of Timer 0 2 Timer 1 TM1 Timer 1 TM1 is also a programmable 8 bit binary down counter as shown in Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin The input clock of Timer 1 can be one of three sources FOSC 64 FOSC or an external clock from the 0 input pin The source can be selected by setting bit 0 and bit 1 of mode register 1 MR1 At initial reset the Timer 1 clock input is FOSC If an external clock is selected as the clock source of Timer 1 the content of Timer 1 is decreased by 1 at the falling edge of RC 0 When the MOV TM1L or MOV TM1H instruction is executed the specified data are loaded into the auto reload buffer and the TM1 down counting will be disabled i e MR1 3 is reset to 0 If the bit 3 of MR1 is set MR1 3 1 the contents of the auto reload buffer will be loaded into the TM1 down counter Timer 1 starts to down count and the event flag 7 is reset EVF 7 0 When the MOV TM1 1 instruction is executed the event flag 7 EVF 7 and MR1 3 are reset and the specified value is loaded into auto reload buffer and TM1 by the internal hardware then the MR1 3 is set that is the TM1 starts to count by the hardware When the timer decrements to FFH it will generate an underflow EVF 7 1 and be auto reloaded with the specified data after which it will continue to count down An interrupt is executed if the interr
32. SRO and CLR PSRO instructions The bit descriptions are as follows 3 2 1 0 means read BitO 1 Signal change at 0 1 1 Signal change at RC 1 Bit2 1 Signal change at RC 2 Bit3 1 Signal change at RC 3 Port Enable Flag PEF The port enable flag is organized as 4 bit binary register PEF 0 to PEF 3 Before port RC may be used to release the hold mode or perform interrupt function the content of the PEF must be set first The PEF is controlled by the MOV PEF 1 instruction The bit descriptions are as follows 3 2 1 0 Note W means write only Publication Release Date March 1998 19 Revision A2 W741E260 Electronics PEF 0 Enable disable the signal change at to release hold mode or perform interrupt PEF 1 Enable disable the signal change at pin RC 1 to release hold mode or perform interrupt PEF 2 Enable disable the signal change at pin RC 2 to release hold mode or perform interrupt PEF 3 Enable disable the signal change at pin RC 3 to release hold mode or perform interrupt DATA BUS Signal change detector Signal change detector Signal change E CLR EVF 1 detector Reset Signal change detector Reset MOV PEF 1 L CLR PSRO
33. STOP mode wake up Enable Flag n PEF n Port Enable Flag n EVF n Event Flag n Not equal amp OR EX Exclusive OR Transfer direction result PAGE 10H X Contents of address PAGE bit2 bit1 bit0 10H P0 Contents of port P 42 W741E260 Winbond Electronics Corp INSTRUCTION SET TABLE 1 Arithmetic lt ACC ACC ACC ACC lt ACC CF ACC WR CF ACC WRe WR I CF ACC lt R ACCe WR ACC Re R ACC W Re WR ACC lt R ACC WR I lt ACC ACC WRe WR ACCe R CF ACCe_ WR 1 CF CF ACC WRe WR 1 CF ACC 1 INC R DEC R ACC R lt R 1 Publication Release Date March 1998 43 Revision A2 W741E260 eW nbond Electronics Corp Instruction Set Table 1 continued Mnemonic Function Fiaa Affected Cvole NL RACC ZF NL ZF ANLR ACC ZF ANLR W R l WRe WR amp RL ACC R ACC ZF ORL ACC WR AI ORLR ZF ORLR ACC WR WR AI XRL ACC lt R EX ACC XRL WR 1 ACC WR
34. W741E260 Winbond Electronics Corp 4 BIT FLASH EPROM MICROCONTROLLER Table of Contents Publication Release Date March 1998 1 Revision A2 W741E260 Winbond Electronics Corp GENERAL DESCRIPTION The W741E260 is a high performance 4 bit microcontroller uC that provides an LCD driver and the flash EEPROM for the program memory The device contains a 4 bit ALU two 8 bit timers two dividers for two oscillators in dual clock operation a 32 x 4 LCD driver and five 4 bit I O ports including 1 output port for LED driving There are also five interrupt sources and 8 level subroutine nesting for interrupt applications The W741E260 operates on very low current and has three power reduction modes hold mode and stop mode in single clock operation and the dual clock slow operation which help to minimize power dissipation This chip is available for W741C250 and W741C260 bodies which can be selected by option code The W741E260 is suitable for end product manufacturer engineering testing and earlier samples before mass production FEATURES Operating voltage 2 4V to 5 5V LCD drive voltage 3 0V or 4 5V Crystal Ceramic oscillator up to 4 MHz RC oscillator up to 4 MHz Dual clock operation is selected by code option e Main oscillator Crystal or RC oscillation circuit can be selected by code option In crystal mode high frequency
35. WR Machine Cycle 1 Operation ACC WR lt WR EX I Description The contents of the Working Register WR and the immediate data are exclusive ORed and the result is placed in the WR and the ACC Flag Affected ZF 92 Winbond Electronics Corp W741E260 PACKAGE DIMENSIONS 80 Lead QFP Seating Plane See Detail F Dimension in inches Dimension in mm Min Nom Max Min Nom Max 0 130 3 30 0 004 0 10 0 107 0 117 2 73 2 97 0 012 0 018 0 30 0 45 0 004 0 010 0 10 0 25 0 546 0 556 13 87 14 13 0 782 0 792 19 87 20 13 0 025 0 037 0 65 0 95 0 728 0 752 18 49 19 10 0 964 0 988 24 49 25 10 0 039 0 055 1 00 1 40 0 087 0 103 2 21 2 62 0 004 0 10 12 93 12 Detail F Publication Release Date March 1998 Revision A2 W741E260 Winbond Electronics Corp NOTES Winbond Electronics Corp Headquarters Winbond Electronics H K Ltd Winbond Electronics North America Corp No 4 Creation Rm 803 World Trade Square Tower Il Winbond Memory Lab Science Based Industrial Park 123 Hoi Bun Rd Kwun Tong Winbond Microelectronics Corp Hsi
36. ata memory location addressed by R6 to RO MOV Output content to port 1 Machine Cycle Operation RA R Description The data in the data memory location addressed by R6 to RO are output to the port RA MOV RB R Output R content to RB port Machine Code 0 1 0 1 1 0 1 0 1 R6 R5 R2 RO 6 Machine Cycle 1 Operation Description Ee The contents of the data memory location addressed by R6 to RO are output to the port RB MOV RE R Output R content to port RE 1 Machine Cycle Operation RE R Description The contents of the data memory location addressed by R6 to RO are output to port RE 74 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV SCR 1 System Clock Register control Machine Cycle 1 Operation System clock control Description If the operation mode is the dual clock operation selected by the option codes the system clock and oscillator can be arranged by controlling the system clock register This command is just for the W741C260 body SCR bits decription 0 Fosc Fm 1 Fosc Fs 1 0 main oscillator is enabled 1 main oscillator is disabled Bit 3 0 divider 1 14 stage 1 divider 1 is 13 stage MOV SEF 1 Set Reset STOP mode waked up Enable Flag for port RC Machine Cycle 1 Operation Set reset STOP mode wake up enable flag for port RC Description The data
37. cepted for W741C260 body the IEF4 is set so that interrupt 4 falling edge signal at the INT pin is accepted for the W741C250 body The IEF7 is set so that interrupt 7 underflow from the Timer 1 is accepted MOV 1 Select LCD output Mode type Machine Cycle 1 Operation Select LCD output mode type Description When LCD output pins are set to DC output mode user can select CMOS or NMOS as output type 10 17 0 gt CMOS type 10 17 1 gt NMOS type 64 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV LCDR ACC Move ACC content LCDR Machine Cycle 1 Operation LCDR lt ACC Description The contents of the ACC are loaded to the LCD data RAM LCDR location addressed by D4 to DO MOV LCDR WR Load WR content to LCDR Machine Cycle 1 Operation LCDR lt WR Description The contents of the WR are loaded to the LCD data RAM LCDR location addressed by D4 to DO MOV LCDR Load immediate data to LCDR Machine Cycle 1 Operation LCDR Description The immediate data are loaded to the LCD data RAM LCDR location addressed by D4 to DO Publication Release Date March 1998 65 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV MFP 1 Modulation Frequency Pulse Machine Cycle 1 Operation lt
38. contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to RO and the result is placed in the ACC and the data memory Flag Affected CF amp ZF 86 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued SBCR WR Subtract immediate data from WR with Borrow Machine Cycle 1 Operation lt WR l CF Description The immediate data and CF are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR Flag Affected CF amp ZF Set CF 1 Machine Cycle Operation Set CF Description Set Carry Flag to 1 Flag Affected CF SET Set Flag Machine Cycle 1 Operation Set Parameter Flag Description Description of each flag 10 12 Reserved 13 1 The input clock of the watchdog timer is Fosc 16384 Publication Release Date March 1998 87 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued SHLC SHift Left R with CF and LSB 0 Machine Cycle 1 Operation lt 1 0 lt 0 lt R 3 Description The contents of the ACC and the data memory location addressed by R6 to RO are shifted left one bit but bit 3 is shifted into CF and bit 0 LSB is replaced with 0 The same contents are loade
39. cs Corp Instruction Set Table 2 continued And R to ACC Machine Cycle Operation lt amp ACC Description The contents of the data memory location addressed by R6 to RO and the ACC are ANDed and the result is loaded into the ACC Flag Affected ZF ANL WR immediate data to WR Machine Cycle Operation ACC lt WR amp Description The contents of the Working Register WR and the immediate data are ANDed and the result is loaded into the ACC Flag Affected ZF ANLR ACC And R to ACC Machine Code 0 0 1 0 1 0 1 1 0 R6 R5 R4 R3 R2 RO 1 Machine Cycle Operation lt amp ACC Description The contents of the data memory location addressed by R6 to RO and the ACC are ANDed and the result is placed in the data memory and the ACC Flag Affected ZF 3 52 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued WR l And immediate data to WR 4 Machine Cycle Operation ACC WR lt WR amp I Description The contents of the Working Register WR and the immediate data are ANDed and the result is placed in the WR and the ACC Flag Affected ZF CALL L Call subroutine 1 Machine Cycle Operation STACK lt PC 1 PC10 PCO lt 110 LO Description The next program counter PC10 to PCO is saved in the STACK and then the direct address L10 to LO
40. d into the ACC Flag Affected CF amp ZF SHRC SHift Right R with CF and MSB 0 Machine Cycle Operation lt 1 ACC 3 lt 0 lt R 0 Description The contents of the ACC and the data memory location addressed by R6 to RO are shifted right one bit but bit 0 is shifted into CF and bit 3 MSB is replaced with 0 The same contents are loaded into the ACC Flag Affected CF amp ZF SKBO R If bit 0 of R is equal to 1 then skip 4 Cycle Operation lt 2 if R 0 1 1 Description If bit O of R is equal to 1 the program counter is incremented by 2 and a skip is produced If bit of R is not equal to 1 the program counter PC is incremented 88 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued SKB1 R If bit 1 of R is equal to 1 then skip Machine Cycle 1 Operation PC PC 2 1 1 1 Description If bit 1 of R is equal to 1 the program counter is incremented by 2 and a skip is produced If bit 1 of R is not equal to 1 the program counter PC is incremented SKB2 R 2 of R is equal to 1 then skip Machine Cycle 1 Operation lt 2 if R 2 1 1 Description If bit 2 of R is equal to 1 the program counter is incremented by 2 and a skip is produced If bit 2 of R is not equal to 1 The program counter PC is incremented SKB3 R
41. d waveform of the MFP generator is delivered at the MFP output pin 1 The specified frequency of Timer 1 is delivered at the MFP output pin Bit320 Timer 1 stops down counting 1 Timer 1 starts down counting Input Output Ports RA RB Port RA consists of pins RA 0 to RA 3 and Port RB consists of pins RB O to RB 3 At initial reset input output ports RA and RB are both in input mode When RA and RB are used as output ports CMOS or NMOS open drain output type can be selected by the PMO register Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers The MOVA R RA or MOVA R RB instructions operate the input functions and the MOV RA R or MOV RB R operate the output functions For more details refer to the instruction table and Figure 8 Input Output Pin of the RA RB Vdd PM0 0 or PMO 1 0 0 or gt Output Buffer O PIN RA n RB n Enabid MOV RA R PMi n L or MOV RB R or PM2 n Instruction Enable MOVA R RA or MOVA instruction Figure 8 Architecture of Input Output Pins Publication Release Date March 1998 I7 Revision A2 W741E260 Winbond Electronics Corp Port Mode 0 Register The port mode 0 register is organized as 4 bit binary register PM0 0 to PMO 3 PMO can be used to determine the structure of the input
42. dress 128 x 4 bit Figure 2 Data Memory Organization W741E260 Winbond Electronics Corp The first sixteen addresses OOH to OFH in the data memory are known as the working registers WR The other data memory is used as general memory and cannot operate directly with immediate data The relationship between data memory locations and the page register PAGE in indirect addressing mode is described in the next section 2 Page Register PAGE The page register is organized as a 4 bit binary register The bit descriptions are as follows 3 2 1 0 pace rw RW RW Note R W means read write available Bit 3 is reserved Bit 2 Bit 1 Bit 0 Indirect addressing mode preselect bits 000 Page 0 00H OFH 001 Page 1 10H 1FH 010 Page 2 20H 2FH 011 Page 3 30H 3FH 100 Page 4 40H 4FH 101 Page 5 50H 5FH 110 Page 6 60H 6FH 111 Page 7 70H 7FH Accumulator ACC The accumulator ACC is a 4 bit register used to hold results from the ALU and transfer data between the memory I O ports and registers Arithmetic and Logic Unit ALU This is a circuit which performs arithmetic and logic operations The ALU provides the following functions Logic operations ANL XRL ORL e Branch decisions JBO JB1 JB2 JNZ JZ JC DSKZ DSKNZ SKBO SKB1 SKB2 SKB3 e Shift operations RRC SHLC Binary addition
43. e WR Flag Affected CF amp ZF ADU Add to ACC and Carry Flag unchange 1 Machine Cycle Operation lt ACC Description The contents of the data memory location addressed by R6 to and ACC are binary added and the result is loaded into the ACC Flag Affected ZF 50 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued ADU WR 1 Add immediate data to WR and Carry Flag unchange 4 Machine Cycle Operation lt WR Description The contents of the Working Register WR and the immediate data are binary added and the result is loaded into the ACC Flag Affected ZF ADUR R ACC Add R to ACC and Carry Flag unchange 1 Machine Cycle Operation lt ACC Description The contents of the data memory location addressed by R6 to RO and ACC are binary added and the result is placed in the ACC and the data memory Flag Affected ZF ADUR Add immediate data to WR and Carry Flag Machine Code 0 0 1 0 1 1 0 1 2 HM W3 W2 Wi WO 1 Machine Cycle Operation WR lt WR I Description The contents of the Working Register WR and the immediate data are binary added and the result is placed in the WR and the ACC Flag Affected ZF Publication Release Date March 1998 51 Revision A2 W741E260 Winbond Electroni
44. he program counter are replaced with the data specified by L10 to LO and a jump occurs If the ACC is zero the program counter PC is incremented 60 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Jump when ACC is zero Machine Cycle 1 Operation PC10 PCO 110 LO if ACC 0 Description If the ACC is zero PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If the ACC is not zero the program counter PC is incremented LCDON LCD ON Machine Cycle 1 Operation LCD ON Description Turn on LCD display LCDOFF LCD OFF Machine Cycle 1 Operation LCD OFF Description Turn off LCD display Publication Release Date March 1998 61 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV ACC R Move R content to ACC Machine Cycle 1 Operation ACC lt R Description The contents of the data memory location addressed by R6 to RO are loaded into the ACC Flag Affected ZF MOV Move 0 content CF Machine Cycle 1 Operation CF lt Description The bit 0 content of the data memory location addressed by R6 to RO is loaded into CF Flag Affected CF 62 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV HEF
45. hen bit 3 of ACC is 1 Machine Cycle 1 Operation PC10 PCO lt 110 LO if ACC 3 1 Description If bit 3 of the ACC is 1 PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If bit 3 of the ACC is 0 the program counter PC is incremented Jump when CF is 1 Machine Code 1 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 LO Machine Cycle 1 Operation PC10 PCO lt 110 10 if CF 1 Description If CF is 1 PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If the CF is 0 the program counter PC is incremented Publication Release Date March 1998 59 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Jump absolutely Machine Cycle 1 Operation PC10 PCO lt 110 LO Description PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and an unconditional jump occurs Jump when is not 1 Machine Cycle 1 Operation PC10 PCO lt L10 LO if CF 0 Description If CF is 0 PC10 to PCO of the program counter are replaced with the data specified by L10 to LO and a jump occurs If CF is 1 the program counter PC is incremented Jump when ACC is not zero Machine Cycle 1 Operation PC10 PCO amp L10 LO if ACC 20 Description If the ACC is not zero PC10 to PCO of t
46. igh resistor EN interrupt pin with pull high resistor This pin is bonding option for EN W741C250 body LANE to LCD segment output pins SEG31 Also can be used as DC output ports specified by option codes COMO to LCD common signal output pins ve Toy Too The LCD alternating frequency can be selected by code option DH1 DH2 Connection terminals for voltage doubler halver capacitor VDD1 Positive supply voltage terminal VDD2 Refer to Functional Description VDD3 Publication Release Date March 1998 5 Revision A2 W741E260 Winbond Electronics Corp Pin description continued SYMBOL FUNCTION VDD Positive power supply VSS Negative power supply VPP p Voltage control pin for the flash EEPROM programming erasing and verifying This pin has a built in pull low resistor MODE Mode selection pin for the flash EEPROM programming erasing and verifying This pin has a built in pull low resistor Data I O pin for the flash EEPROM programming and verifying This pin has a built in pull low resistor BLOCK DIAGRAM SEGO to SEG31 VDDito3 LCD DRIVER lt PORT RA RAO to 3 Flash EEPROM ONE 2K x 4 4 PORT RC RCO to 3 PORT RD RDO to 3 ni PORT RE REO to 3 8 Levels Modulation Frequency Divider 1 id 13 14 bit T
47. iming Generator Watchdog Timer Divider 0 4 bit 14 bit XIN1 XOUT1 XIN2 XOUT2 W741E260 Winbond Electronics Corp FUNCTIONAL DESCRIPTION Program Counter PC Organized as an 11 bit binary counter PCO to PC10 the program counter generates the addresses ofthe 2048 x 16 on chip flash EEPROM containing the program instruction When the jump or subroutine call instructions or the interrupt or initial reset conditions are to be executed the address corresponding to the instruction will be loaded into the program counter The format used is shown below INT 3 Divider1 for W741C260 014H 4th INT Pin for W741C250 INT 4 Timer 1 020H 5th Stack Register STACK The stack register is organized as 11 bit x 8 levels first in last out When either a call subroutine or an interrupt is executed the program counter will be pushed onto the stack register automatically At the end of a call subroutine or an interrupt service subroutine the instruction must be executed to pop the contents of the stack register into the program counter When the stack register is pushed over the eighth level the contents of the first level will be lost In other words the stack register is always eight levels deep Program Memory flash EEPROM The flash EEPROM is used to store program codes the look up table is arranged as 2048 x 4 bits The first three quarters of flash EEPRO
48. ing edge signal at the INT pin for W741C250 body IEF 5 amp IEF 6 are reserved IEF 721 Interrupt 7 is accepted by underflow from Timer 1 Stop Mode Operation In stop mode all operations of the uC cease excluding the operation of the sub oscillator and divider 1 when the dual clock operation mode is selected The uC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated by a falling signal on the RC port for W741C260 body or by a falling signal on the RC port or a low level on the INT pin for W741C250 body When the designated signal is accepted the awakens and executes the next instruction if the corresponding bits of IEF and PEF have been set It will enter the interrupt service routine after stop mode released To prevent erroneous execution the NOP instruction should follow the STOP command But In the dual clock slow operation mode the STOP instruction will disable the main oscillator oscillating the system is still operated by the sub oscillator Stop Mode Wake up Enable Flag for RC Port SEF The stop mode wake up flag for port RC is organized as an 4 bit binary register SEF 0 to SEF 3 Before port RC may be used to make the device exit the stop mode the content of the SEF must be set first The SEF is controlled by the MOV SEF 1 instruction The bit descriptions are as follows 3 1 0 2 Note W means write only SEF 0 1 Device will exit stop mode
49. is instruction DSKNZ R Decrement content then skip if ACC 0 Machine Cycle Operation lt R 1 lt PC 2if ACC 0 Description Decrement the data memory content and load result into the ACC and the data memory If ACC 0 the program counter is incremented by 2 and produces a skip Flag Affected CF amp ZF 56 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued DSKZ R Decrement R content then skip if ACC is zero 4 Machine Cycle Operation lt 1 lt PC 2if ACC 0 Description Decrement the data memory content and load result into the ACC and the data memory If ACC 0 the program counter is incremented by 2 and produces a skip Flag Affected CF amp ZF Enable Interrupt function 4 Machine Cycle Operation Enable interrupt function Description This instruction enables the interrupt function HOLD Enter the HOLD mode 1 Machine Cycle Operation Enter the HOLD mode Description The following two conditions cause the HOLD mode to be released 1 An interrupt is accepted 2 The HOLD release condition specified by the HEF is met In HOLD mode when an interrupt is accepted the HOLD mode will be released and the interrupt service routine will be executed After completing the interrupt service routine by executing the RTN instruction the uC will enter HOLD mode again
50. is loaded into the program counter A subroutine is called Clear CF 1 Machine Cycle Operation Clear CF Description Clear Carry Flag to 0 Flag Affected CF Publication Release Date March 1998 53 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued CLR DIVRO Reset the last 4 bits of the DIVideR 0 4 Machine Cycle Operation Reset the last 4 bits of the divider 0 Description When this instruction is executed the last 4 bits of the divider O 14 bits are reset CLR DIVR1 Reset the last 4 bits of the DIVideR 1 4 Machine Cycle Operation Reset the last 4 bits of the divider 1 Description When this instruction is executed the last 4 bits of the divider 1 14 bits are reset This instruction is available in W741C260 body but it is inhibited in W741C250 body CLR Clear ParaMeter Flag 4 Machine Cycle Operation Clear Parameter Flag Description Description of each flag 10 12 Reserved 1 The input clock of the watchdog timer is Fosc 1024 54 Winbond Electronics Corp W741E260 Instruction Set Table 2 continued CLR EVF Clear EVent Flag Machine Code Machine Cycle Operation Description 0 1 0 0 0 0 0 0 7 16 5 2 10 1 Clear event flag The condition corresponding to the data specified by I7 to IO is controlled 10 17
51. lication Release Date March 1998 Revision A2 W741E260 Winbond Electronics Corp PIN CONFIGURATION Nm COxo mooz oz NIO 00 lt lt lt oogmo 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W741E260 Winbond Electronics Corp PIN DESCRIPTION SYMBOL FUNCTION XIN1 Input pin for main oscillator Connected to crystal or resistor to generate system clock by code option XOUT1 Output pin for main oscillator Connected to crystal or resistor to generate system clock by code option XIN2 Input for sub oscillator Connected to 32 768 KHz crystal XOUT2 Output pin for sub oscillator with internal oscillation capacitor Connected to 32 768 KHz crystal RAO to RA3 Input Output port Input output mode specified by port mode 1 register PM1 RBO to RB3 Input Output port Input output mode specified by port mode 2 register PM2 RCO to RC3 4 bit port for input only Each pin has an independent interrupt capability RDO to NN 4 bit port for input only REO to RES Output port only This port provides high sink current to drive LEDs MFP Output pin only This pin can output modulating or nonmodulating frequency or Timer 1 clock output specified by mode register 1 1 p System reset pin with pull h
52. nchu Taiwan Kowloon Hong Kong TEL 886 3 5770066 TEL 852 27513100 Winbond Systems Lab FAX 886 3 5792766 FAX 852 27552064 2727 N First Street San Jose http www winbond com tw CA 95134 U S A Voice amp Fax on demand 886 2 27197006 TEL 408 9436666 FAX 408 5441798 Taipei Office 11F No 115 Sec 3 Min Sheng East Rd Taipei Taiwan TEL 886 2 27190505 FAX 886 2 27197502 Note All data and specifications are subject to change without notice 94
53. ncy and the preset value of TM1 is shown in the table below Publication Release Date March 1998 15 Revision A2 W741E260 Winbond Electronics Corp wo ao frequency MFP frequency frequency MFP frequency frequency MFP frequency 22140 us seno 6284 Note Central tone is A4 440 Hz Mode Register 0 MRO Mode Register 0 is organized as a 4 bit binary register 0 to MRO 3 MRO can be used to control the operation of Timer 0 The bit descriptions are as follows 3 2 1 0 w Note W means write only Bit0 0 The fundamental frequency of Timer 0 is Fosc 4 21 The fundamental frequency of Timer 0 is Fosc 1024 Bit 1 amp Bit 2 are reserved Bit320 Timer 0 stops down counting 1 Timer 0 starts down counting Mode Register 1 MR1 Mode Register 1 is organized as a 4 bit binary register MR1 0 to MR1 3 MR1 can be used to control the operation of Timer 1 The bit descriptions are as follows 3 2 1 0 Note W means write only 16 W741E260 Winbond Electronics Corp BitO 20 The internal fundamental frequency of Timer 1 is FOSC 1 The internal fundamental frequency of Timer 1 is FOSC 64 Bit1 20 The fundamental frequency source of Timer 1 is the internal clock 1 The fundamental frequency source of Timer 1 is the external clock from RC 0 input pin Bit2 0 The specifie
54. nnections for each LCD driving mode which are determined by a mask option are shown below Static LCD Configuration 1 2 Bias LCD Configuration DH1 DH2 floating VDD1 1 2 VDD VDD2 VDD VDD3 3 2 VDD Publication Release Date March 1998 35 Revision A2 W741E260 Winbond Electronics Corp LCD Configuration continued 1 3 Bias LCD Configuration VDD1 1 3 VDD VDD2 2 3 VDD VDD3 VDD EEPROM Program Erase Description The built in program code memory of the W741E260 is the EEPROM structure This memory can be programmed erased and verified through the VPP MODE and DATA pins The on board program erase connection is shown below WHC4403 58 57 55 51 Xin Xout Vdd Mode W741E260 Vss VPP Data 5 6 T Figure 14 The W741E260 Program Erase Configuration 36 W741E260 Winbond Electronics Corp ABSOLUTE MAXIMUM RATINGS PARAMETER RATING Supply Voltage to Ground Potential 0 3 to 7 0 Applied Input Output Voltage 0 3 to 7 0 Ambient Operating Temperature 0 to 70 Storage Temperature 55 to 150 Note Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device DC CHARACTERISTICS 88 3 0V Fm 4 19 MHz Fs 32 768 KHz
55. ode Therefore in single clock mode the clock source of the system clock generator is the main oscillator clock FOSC Fm When the SCR is set or reset we must pay attention to the following 1 X000B X011B Disable the main oscillator Fm should not be done simultaneously with changing the system clock source FOSC from Fm to Fs The Fosc should be changed first from Fm to Fs before the main oscillator Fm is disabled The correct sequence is X000B X001B X01 1B 10 W741E260 Winbond Electronics Corp 2 X011B X000B Enabling the main oscillator Fm should not be done simultaneously with changing the Fosc from Fs into Fm The main oscillator Fm should be enabled first before a delay subroutine is called to allow the main oscillator to oscillate stably The Fosc can now be changed from Fs into Fm The correct sequence is therefore X011B gt X001B gt delay subroutine 00 The suggested delay for Fm is 20 mS for 455 KHz ceramic resonator and 10 mS for 4 MHz crystal We must remember that the X010B state is inhibitive because it will induce a system shutdown The organization of the dual clock operation mode is shown below Mask Option High Low Freq SCR 0 Fm Main llator ain Oscillato System Clock Generator enable disable Divider 0 Mask Option High Low Freq Fosc 32 XIN2 Fosc requency FLCD Sub oscillator
56. output ports it is controlled by the MOV 1 instruction The bit descriptions are as follows 3 2 1 0 Note W means write only Bit 0 RA port is CMOS output type Bit 0 1 RA port is NMOS open drain output type Bit 1 2 0 RB port is CMOS output type Bit 12 1 RB port is NMOS open drain output type Bit 2 2 0 RC port pull high resistor is disabled Bit 2 1 RC port pull high resistor is enabled Bit 3 20 RD port pull high resistor is disabled Bit 3 1 RD port pull high resistor is enabled Port Mode 1 Register PM1 The port mode 1 register is organized as 4 bit binary register PM1 0 to PM1 3 PM1 can be used to control the input output mode of port RA is controlled by the MOV 1 instruction The bit descriptions are as follows 3 2 1 0 Note W means write only Bit 2 0 RA 0 works as output pin Bit 1 RA O works as input pin Bit 1 20 RA 1 works as output pin Bit 1 1 RA 1 works as input pin Bit2 20 RA 2 works as output pin Bit 2 1 RA 2 works as input pin Bit 3 20 RA 3 works as output pin Bit 1 RA 3 works as input pin At initial reset port RA is input mode PM1 1111B Port Mode 2 Register PM2 The port mode 2 register is organized as 4 bit binary register PM2 0 to PM2 3 2 can be used to control the input output mode of port RB PM2 is controlled by the MOV PM2 1 instruction The bit descriptions are as follows 3 2 1 0 Note W means write only 18 W741E260
57. ow com COM LCDDataRAM OutputPin bit2 01 0 1 0 1 0 1 0 1 0 1 0 1 LCDR1E SEG30 0 1 LCDR1F SEG31 0 1 The LCDON instruction turns the LCD display on even in HOLD mode and the LCDOFF instruction turns the LCD display off At initial reset all the LCD segments are lit When the initial reset state ends the LCD display is turned off automatically To turn on the LCD display the instruction LCDON must be executed When the drive output pins are used as DC output ports setting by option codes please refer the user s manual of ASM741S assembler for more detail CMOS output type or NMOS output type can be selected by executing the instruction MOV LCDM 1 The relationship between the LCD data RAM and segment common pins is shown below The data in LCDROO are transferred to the corresponding segment output port SEG3 to SEGO by a direct memory access The other LCD data RAM segments can be used as normal data RAM to store data LCDDataRAM OutputPin Bits Bit2 Bit BitO LcDROs LCDROt p cpR7LCDRS LCDRIF LCDRID 28 W741E260 Winbond Electronics Corp The relationship between the LCD drive mode and the maximum number of drivable LCD segments is shown below LCD Segment Power Input WsBasisDuy 2 LCD Outpu
58. p T TM PAGE ACC 0 0 CFe R 0 ACC ACC 7 1 a Publication Release Date March 1998 45 Revision A2 W741E260 eW nbond Electronics Corp Instruction Set Table 1 continued Mnemonic Function FlaaAffected Cvcle PME GlearParameterFlagifin t ser Pura SetParameter Fagitinet mov wo MOV 1 Set Reset HOLD mode release Enable Flag MOV SEF Set Reset STOP mode wake up Enable Flag for RC port OV SCR 1 SCR T dures MOVA PSRO LR__PSRO CF R CD m 4 O E 1 NorE 1 CLR WDT Clear WatchDog Timer Shift amp Rotate 1 SHRC R ACC n lt 1 CF 1 3 R 3 0 CF R 0 RRC R 1 1 F F F ACC n lt 1 ZF CF ACC n lt 1 ZF CF ACC n lt 1 ZF CF 1 46 W741E260 eW nbond Electronics Corp Instruction Set Table 1 continued Flaa Affected LCDR 1 LCDR WR LCDR WR c LCDR OV LCDR WR LCDRe WR MOV LCDR LCDR ACC MOV LCDM 1 Select LCD output mode type LCDON LCD ON LCDOFF LCD OFF Timer MOV TMOL R TMOL lt R MOV TMOH R TMOH R MOV 1 0 MOV TM1L R TM1L lt R MOV TM1H TM1H
59. r VPP Pull down Resistor 1 5 MODE Pull down Resistor 5 DATA Pull down Resistor 100 38 W741E260 Winbond Electronics Corp AC CHARACTERISTICS VDD VSS 3 0V 25 C unless otherwise specified PARAMETER CONDITIONS RC type Op Frequency Fosc Crystal type 1 Option low speed type Crystal type 2 Option high speed type f Oscillator Instruction Cycle Time One machine cycle Reset Active Width Fosc 32 768 KHz Interrupt Active Width TIAW FOSC 32 768 KHz 1 PAD ASSIGNMENT AND POSITIONS 2870 um gt 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 Deviation by f 3V f 2 4V Voltage Drop for RC ra f 3V 00000000 4840 hm 000000 1 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Y DIXIE TETTE YET TET TETETI Note The chip substrate must be connected to system ground Vss Publication Release Date March 1998 39 Revision A2 W741E260 Winbond Electronics Corp vs 12780 155050 4 SEGG0 122620 165380 6 12780 3620 48 vone 122620 126980 s 12270 2 45 122620 100980 12780 3580 46 122620 87380 28 secs 84580 21630 0 Reo 78030 21410 29 seco 6580 2160 6 030 e214170 secat 19420 21630 6 Roo 25970 214170
60. re binary subtracted from the contents of the data memory location addressed by R6 to RO and the result is placed in the ACC and the data memory Flag Affected CF amp ZF SUBR WR Subtract immediate data WR Machine Cycle 1 Operation ACC WR lt WR Description The immediate data are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR Flag Affected CF amp ZF XRL Exclusive to 1 Machine Cycle Operation ACC lt EX ACC Description The contents of the data memory location addressed by R6 to RO and the ACC are exclusive ORed and the result is loaded into the ACC Flag Affected ZF Publication Release Date March 1998 91 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued XRL WR Exclusive OR immediate data to WR Machine Cycle 1 Operation ACC lt WR Description The contents of the Working Register WR and the immediate data are exclusive ORed and the result is loaded into the ACC Flag Affected ZF XRLR Exclusive OR to ACC Machine Cycle 1 Operation lt EX ACC Description The contents of the data memory location addressed by R6 to RO and the ACC are exclusive ORed and the result is placed in the data memory and the ACC Flag Affected ZF XRLR WR Exclusive OR immediate data
61. ry location addressed by R6 to RO are loaded into the TM1H MOV WR LCDR Load LCDR content to WR Machine Code 0 1 0 0 0 1 1 03 02 Di DO W3 W2 W1 WO 1 Machine Cycle Operation WR lt LCDR Description The contents of the LCD data RAM location addressed by D4 to DO are loaded to the WR MOV WR R Move R content to WR 4 Operation WR lt Description The contents of the data memory location addressed by R6 to RO are loaded to the WR Publication Release Date March 1998 77 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV WR R Indirect load from R to WR Machine Cycle 2 Operation WR lt bit2 bitO x 10H R Description The data memory contents of address PR bit2 bit x 10H R are loaded to the WR MOV R WR Indirect load from WR to R Machine Cycle 2 Operation PR bit2 bit1 bitO x 10H lt WR Description The contents of the WR are loaded to the data memory location addressed by PR bit2 bit1 bitO x 10H R MOV PAGE R Move R content to Page Register Machine Cycle 1 Operation PR lt Description The contents of the data memory location addressed by R6 to RO are loaded to the PR 78 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOVA CF Move
62. rystal Crystal 32 KHz or 32 KHz 400K to 4MHz d XOUT2 Figure 3 System Clock Oscillator Configuration Dual clock operation This operation mode is selected by code option In the dual clock mode the clock source of the LCD frequency selector should be the sub oscillator clock 32768 Hz only But in the single clock mode the clock source of the LCD frequency selector will be Fm or Fm 32 Fm main oscillator clock So when the STOP instruction is executing the LCD will be turned off in the single clock mode but the LCD will keep working in the dual clock mode In this dual clock mode the normal operation is performed by generating the system clock from the main oscillator clock Fm As required the slow operation can be performed by generating the system clock from the sub oscillator clock Fs The exchange of the normal operation and the slow operation is performed by resetting or setting the bit 0 of the system clock control register SCR If the SCR 0 is reset to 0 the clock source of the system clock generator is the main oscillator clock if the SCR 0 is set to 1 the clock source of the system clock generator is the sub oscillator clock In the dual clock mode the main oscillator can stop oscillating when the STOP instruction is executing or the SCR 1 is set to 1 But in the single clock mode only the STOP instruction can stop the main oscillator oscillating because the SCR would be disabled in the single clock m
63. s subtractions ADC SBC ADD SUB ADU DEC INC After any of the above instructions are executed the status of the carry flag CF and zero flag ZF is stored in the internal registers Otherwise CF can be stored or be read out by executing MOVA R CF or MOV CF R Publication Release Date March 1998 9 Revision A2 W741E260 Winbond Electronics Corp Clock Generator The W741E260 provides two oscillation circuits main oscillator and sub oscillator The main oscillator can select the crystal or RC oscillation circuit by option codes to generate the system clock through external connections If a crystal oscillator is used a crystal or a ceramic resonator must be connected to XIN1 and XOUT1 and a capacitor must be connected if an accurate frequency is needed When the oscillator is used a high frequency clock 400 KHz to 4 MHz or low frequency clock 32 KHz can be selected for the system clock by means of option codes If the RC oscillator is used a resistor must be connected to XIN1 and XOUT1 and the high low frequency clock option must be selected to suit the operation frequency The sub oscillator must be connected to a 32 768 KHz crystal through XIN2 and XOUT2 external pins when the dual clock operation mode is selected by option code The connection is shown in Figure 3 One machine cycle consists of a four state system clock sequence and can run up to 1 uS with a 4 MHz system clock C
64. struction If the main oscillator is connected to the 32768 Hz crystal the EVF O will be set to 1 periodically at each 500 mS interval If the sub oscillator is enabled the Divider1 is incremented by each clock Fs When an overflow occurs the Divider1 event flag is set to 1 EVF 4 1 The interrupt is executed if the Divider1 interrupt enable flag has been set IEF 4 1 and the hold state is terminated if the hold release enable flag has been set HEF 4 1 There are two time periods 250 mS amp 500 mS that can be selected by setting the SCR 3 bit When SCR 3 0 default the 500 mS period time is selected when SCR 3 1 the 250 mS period time is selected Watchdog Timer WDT The watchdog timer WDT is organized as a 4 bit up counter and is designed to protect the program from unknown errors The WDT is enabled when the corresponding option code bit of the WDT is set to 1 If the WDT overflows the chip will be reset At initial reset the input clock of the WDT is Fosc 1024 The input clock of the WDT can be switched to Fosc 16384 or Fosc 1024 by executing the SET PMF 08H or CLR PMF 08H instruction The contents of the WDT can be reset by the instruction CLR WDT In normal operation the application program must reset WDT before it overflows A WDT overflow indicates that the operation is not under control and the chip will be reset The WDT minimun overflow period is 468 75 mS when the system clock Fosc is 32 KHz and WDT
65. sult is loaded into the ACC Flag Affected ZF Publication Release Date March 1998 63 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued ORL WR 1 OR immediate data to WR Machine Cycle 1 Operation lt WR Description The contents of the Working Register WR and the immediate data are ORed and the result is loaded into the ACC Flag Affected ZF ORLR ACC OR R to ACC Machine Cycle 1 Operation lt ACC Description The contents of the data memory location addressed by R6 to RO and the ACC are ORed and the result is placed in the data memory and the ACC Flag Affected ZF ORLR WR l OR immediate data to WR Machine Cycle 1 Operation WR lt WR 1 Description The contents of the Working Register WR and the immediate data are ORed and the result is placed in the WR and the ACC Flag Affected ZF 84 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Rotate Left R with CF Machine Cycle 1 Operation lt 1 0 lt CF CF lt Description The contents of the ACC and the data memory location addressed by R6 to RO are rotated left one bit bit 3 is rotated into CF and CF rotated into bit O LSB The same contents are loaded into the ACC Flag Affected CF amp
66. t Mode Type Flag LCDM The LCD output mode type flag is organized as an 8 bit binary register to LCDM 7 These bits are used to control the LCD output pins architecture When LCD output pins are set to DC output mode by option codes the architecture of these output pins segment 0 to segment 31 can be selected as CMOS or NMOS type It is controlled by the MOV LCDM instruction The bit descriptions are as follows 7 6 5 4 3 2 1 0 Note W means write only LCDM 0 0 SEGO to SEG3 work as CMOS output type 1 SEGO to SEG3 work as NMOS output type LCDM 1 0 SEGA to SEG7 work as CMOS output type 1 SEGA SEG7 work as NMOS output type LCDM 2 0 SEG8 to SEG11 work as CMOS output type 1 SEG8 to SEG11 work as NMOS output type LCDM 3 0 SEG12 to SEG15 work as CMOS output type 1 SEG12 to SEG15 work as NMOS output type LCDM 4 0 SEG16 to SEG19 work as CMOS output type 1 SEG16 to SEG19 work as NMOS output type LCDM 5 0 SEG20 to SEG23 work as CMOS output type 1 SEG20 to SEG23 work as NMOS output type LCDM 6 0 SEG24 to SEG27 work as CMOS output type 1 SEG24 to SEG27 work as NMOS output type LCDM 7 0 SEG28 to SEG31 work as CMOS output type 1 SEG28 to SEG31 work as NMOS output type The output waveforms for the five LCD driving modes are shown below Publication Release Date March 1998 29 Revision A2 W741E260 Winbond Electronics Corp Static Lighting
67. t the MFP output pin 1 The specified frequency of the Timer 1 is delivered at the MFP output pin bia 0 Timer 1 stop down counting 1 Timer 1 start down counting 68 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV PAGE 1 Load immediate data to Page Register Machine Cycle 1 Operation Page Register Description The immediate data are loaded to the PR Bit 3 is reserved Bit 0 bit 1 and bit 2 indirect addressing mode preselect bits Co Frage or 05 oe arr TF rage C 3 s Frage oro Page 7 70H 7FH Publication Release Date March 1998 69 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOV PEF 1 Set Reset Port Enable Flag Machine Cycle 1 Operation Port enable flag control Description The data specified by can cause HOLD mode to be released or an interrupt to occur The signal change on port RC is specified MOV 1 Set Reset Port Mode 0 register Machine Cycle 1 Operation Set Reset Port mode 0 register Description RA port is CMOS type 10 1 RA port is NMOS type RB port is CMOS type 11 1 RB port is NMOS type RC port pull high resistor is disabled RC port pull high resistor is enabled RD port pull high resistor is disabled
68. ted is described below Program Counter PC TMO TM MRO MR1 PAGE registers Reset PSPO registers Reset HEF HCF PEF EVF SEF flags Heset SCR register Reset Timer 0 input cock Foso4 Timer 1 input cock OSC MFP output ftw ports RA Inputmode _RA amp RB ports output type CMOS type RC amp RD ports pull high resistors Disable Input clock of the watchdog timer Foso 1024 Segment output mode LCD drive output _ 26 W741E260 Winbond Electronics Corp LCD Controller Driver The W741E260 can directly drive an LCD with 32 segment output pins and 4 common output pins for a total of 32 x 4 dots Option codes can be used to select one of five options for the LCD driving mode static 1 2 Bias 1 2 duty 1 2 Bias 1 3 duty 1 3 Bias 1 3 duty or 1 3 Bias 1 4 duty see Figure 3 The alternating frequency of the LCD can be set as Fw 64 Fw 128 Fw 256 or Fw 512 In addition option codes can also be used to set up four of the LCD driver output pins segment 0 to segment 31 as a DC output port The structure of the LCD alternating frequency FLCD is shown in 2 Fosc or Fosc 32 Q1 oa o4 os or Q9 Fw 64 Fw 128 Mask Option Fw 256 Single Dual Clock Fw 512 oO Selector Figure 12 LCD Alternating Freq
69. tion ACC lt RA Description The data on port RA are loaded into the data memory location addressed by R6 to RO and the ACC Flag Affected ZF MOVA R RB Input RB port data to ACC amp R Machine Cycle 1 Operation ACC lt RB Description The data on port RB are loaded into the data memory location addressed by R6 to RO and the ACC Flag Affected ZF 2922 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued MOVA R RC Input RC port data to amp Machine Cycle 1 Operation lt RC Description The input data on the input RC are loaded into the data memory location addressed by R6 to RO and the ACC Flag Affected ZF MOVA R RD Input RD port data to ACC amp R Machine Cycle 1 Operation ACC R lt RD Description The input data on the input port RD are loaded into the data memory location addressed by R6 to RO and the ACC Flag Affected ZF MOV R WR Move WR content to R Machine Cycle 1 Operation R lt WR Description The contents of the WR are loaded to the data memory location addressed by R6 to RO Publication Release Date March 1998 73 Revision A2 W741E260 Winbond Electronics Corp Instruction Set Table 2 continued Load immediate data to R 4 Machine Cycle Operation Rel Description The immediate data are loaded to the d
70. uency Circuit Diagram Data Bus LCD frequency selection Option Codes LCD drive LCD DATA RAM Fw Clock LCD Mode mode 32 x 4 bits Generator Controller selection MOV LCD duty amp bias instruction gt LCD DH1 LCD Voltage Commom waveform Segment DH2 Controller Driver Driver Controller VDD gt VSS h vDD1to3 COMO to 3 SEGO to 31 Figure 13 LCD Driver Controller Circuit Diagram Publication Release Date March 1998 27 Revision A2 W741E260 Winbond Electronics Corp When Fw 32 768 KHz the LCD frequency is as shown in the table below LCD Frequency 1 2 Duty 1 3 Duty 1 4 Duty Fw512 64Hz 3 a 256 128 128 4 32 Fw 128 256 Hz Fw64 512 Hz Corresponding to the 32 LCD drive output pins there are 32 LCD data RAM segments LCDROO to LCDR1F Instructions such as MOV LCDR 1 MOV WR LCDR MOV LCDR WR and MOV LCDR ACC are used to control the LCD data RAM The data in the LCD data RAM are transferred to the segment output pins automatically without program control When the bit value of the LCD data RAM is 1 the LCD is turned on When the bit value of the LCD data RAM is 0 LCD is turned off The contents of the LCD data RAM LCDR are sent out through the segmentO to segment31 pins by a direct memory access The relation between the LCD data RAM and segment common pins is shown bel
71. upt enable flag 7 has been set to 1 IEF 7 1 and the hold state is terminated if the hold mode release enable flag 7 is set to 1 HEF 7 1 The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1 Bit 3 of MR1 can be used to make Timer 1 stop or start counting If the Timer 1 clock input is FT then I4 W741E260 Winbond Electronics Corp Desired timer interval preset value 1 FT Desired frequency for MFP output pin FT preset value 1 2 Hz Preset value Decimal number of Timer 1 preset value and Fosc Clock oscillation frequency MOV TM1 1 MOV TM1H R MOV TMI1L 8 Underflow 1 MH1 3 1 signal 2 MOV TM1 S 4 4 R Q EVF 7 Auto reload buffer 1 Reset 2 INT 7 accept via 0 4 Set MR1 3 to 1 5 MOV TM1 External clock s 3 CLR EVF 80H 8 bits Enable M iem 8 bit Fosc 64 t gt Down 22 Timer 1 00 9279 ai Disable Reset i Set MR1 3to 1 Output pin MOV TM1 gt MR1 2 MFP signal Figure 7 Organization of Timer 1 For example when FT equals 32768 Hz depending on the preset value of TM1 the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz The relation between the tone freque
72. when falling edge signal is applied to pin RC O 1 1 Device will exit stop mode when falling edge signal is applied to pin RC 1 SEF 2 1 Device will exit stop mode when falling edge signal is applied to pin RC 2 SEF 3 1 Device will exit stop mode when falling edge signal is applied to pin RC 3 Publication Release Date March 1998 23 Revision A2 W741E260 Winbond Electronics Corp Hold Mode Operation In hold mode all operations of the uC cease except for the operation of the oscillator Timer Divider and LCD driver The uC enters hold mode when the HOLD instruction is executed The hold mode can be released in one of five ways by the action of timer 0 timer 1 divider 0 divider 1 the RC port Before the device enters the hold mode the HEF PEF and IEF flags must be set to define the hold mode release conditions For more details refer to the instruction set table and the following flow chart Divider 0 Divider 1 Timer 0 Timer 1 Signal Change at RC Port Interrupt Interrupt Enable Enable Reset EVF Flag Reset EVF Flag Execute Execute Interrupt Service Interrupt Service Routine Routine Disable interrupt Disable interrupt HOLD PC lt PC 1 Note The bit of EVF corresponding to the interrupt signal will be reset Figure 11 Hold Mode and Interrupt Operation Flow Chart 24 W741E260 Winbond Electronics Corp Hold Mode Release

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