Digital Communications
Contents
1. 9 Variables RPS PROCEDURE 1 Switch ON the experimental kit shown in Fig P4 1 2 Observe the clock generator output and AF signal outputs 3 Connect clock generator output to the clock input point of PWM modulator and observe the same clock on channel of a dual trace CRO 4 Trigger the CRO with respect to CHI 5 Apply a variable DC voltage of 8 to 12 volts from any external regulated power supply 6 Observe the PWM output on CH2 7 If we obtain the PWM output its width varies according to the DC input voltage 8 Now observer PPM output on CH2 its position changes according to the DC input voltage 9 A variable amplitude AF signal is given to observe how the PWM signals are varying for AC modulating voltages 10 For this observe AF signal on CH1 and PWM output on CH2 11 Observe PPM on CH2 Note Generally we have to store PWM and PPM signals with respect to the modulating signals to get better results Real time CRO also useful but triggering for AC modulating voltages is difficult 12 During the demodulation apply PWM and PPM signal to the input of demodulator and observe its output al ee xoc B om pugmig mod UP oy jnpoutaq 10101 POR VET i ont XIX D ie 4 000 3 0001 Tum elo guau d o iine sea t L a at ganein BUGS AV O 8 ud uyo Wd qv OM 01 seg up qui Lm 1202 adn zoo yuding Aiid z t iulio ddMt E Your du JV BAC2. E os r n ra pol i p re e a ar 5l n i Tm mm e i aie a em p F F P p fr at Tt ET i m iili p Nl J ania Le aia _ n EN 7 z c Z Y OF FA 7 Ere ta b oz 7 ne 7 t 1 IL c on P m X m C m l N is M fa O07 mit p d RESULT PSK Modulation PSK Demodulation PSK Modulated Signal PSK Demodulated Signal PSK Modulated Signal
3. pd 9d POLL Jt LOO gy I P EXPERIMENT NO 4 Pulse Code Modulation and Demodulation AIM To study PCM modulation and demodulation and observing the waveforms THEORY Pulse Code Modulation PCM is different from Amplitude Modulation AM and Frequency Modulation FM because those two are continuous forms of modulation Pulse Code Modulation PCM is used to convert analog signals into binary form In the absence of noise and distortion it is possible to completely recover continuous analog modulated signals But in real time they suffer from transmission distortion and noise to an appreciable extent In the PCM system groups of pulses or codes are transmitted which represent binary number corresponding to Modulating Signal Voltage levels Recovery of the transmitter information does not depend on the height width or energy content of the individual pulses but only on their presence or absence Since it is relatively easy to recover pulses under these conditions even in the presence of large amounts of noise and distortion PCM systems tend to be very immune to interference and noise Regeneration of the pulse enroute 1s also relatively easy resulting in system that produces excellent result for long distance communication The decoding process reshapes the incoming pulses and eliminates most of the transmission noise A serial to parallel circuit passes the bits 1n parallel groups to a digital to analog converter D A for de
4. sec and OV peak to peak amplitude 3 Apply a sine wave carrier signal of 50 kHz of 5V peak to peak amplitude 4 Observe ASK waveform at point A 5 Demodulate the ASK signal using the envelope detector The error in the demodulated wave form can be minimized by adjusting the Vref using 10 KQ POT 6 To find minimum frequency of carrier signal for proper detection i After step No 5 start reducing the freq2uency of the sine wave carrier signal from 50 kHz gradually il At a particular frequency of the carrier signal the demodulated signal does not tally with the modulating square wave signal The minimum frequency of the carrier sine wave signal is that frequency when demodulated signal tally with the modulating signal for the first time SLIOO ASK Signal Demodulated evo Hz Bes 15 Y 15 V Comparator 4 y i afol ASK Moculatoi 4 Envelop Detecto Fig P9 1 Design Specification Vc 5V Vm 10V fm 500Hz and fe 50KHz Assume h 30 VBE sat 0 7V Vce sat 0 3V k ImA k Ic Biasing V epek V sat ERE 1 5 1 0 3 ImA Ry therefore Rp 2 2KQ V moedk Rplp Vpp 4 HERE j Rals 410 7 4 22 Then Rgmx 63KO choose Rg 22K Envelope Detector 1 fm gt RpCp gt l fc Sms gt RpCp gt 20us Let RpCp 500 f Ims AssumeCp 0 01uF then Rp LOOKQ choose Rp 100KQ Rp 100KQ Rg 22KQ Re 22K O Cp 0 0luF Check Points 1 Check the OP AMP Transistor and D
5. LABORATORY EXPERIMENTS DIGITAL COMMUNICATION INDEX Name of the Program rn eee Study of Pulse Amplitude Modulation PAM and Demodulation i ee Study of Pulse Width Modulation PWM and Demodulation a ee ee Study of Pulse Position Modulation PPM and Demodulation rr eee 4 To study Pulse Code Modulation PCM and demodulation and observe the waveforms NEN eee 5 Study of Amplitude Shift Keying ASK Modulator and Demodulator Bd eee 6 Study of Phase Shift Keying PSK Modulator and Demodulator EXPERIMENT NO 1 Pulse Amplitude Modulation AIM To study PAM generator and detector and observe the waveforms THEORY Pulse Modulation may be used to transmit analoginformation such as continuous speech or data It is a system in which continuous waveforms are sampled at regular intervals Information regarding the signal is transmitted only at the sampling times together with any information Pulse that may be required At the receiving end the original waveforms may be reconstructed from the information regarding the samples if these are taken frequently enough Despite the fact that information about the signal is not supplied continuously as in Amplitude Modulation and frequency modulation the resulting receiver output can have negligible distortion Pulse Modulation may be subdivided broadly into two categories Analog and Digital In the former the indication of sample Amplitude may be infinitely variable while in
6. coding Thus decoded signal passes through a sample and hold amplifier which maintains the pulse level for the duration of the sampling period recreating the staircase waveform approximation of the modulating signal A low pass filter may be used to reduce the quantization noise APPARATUS REQUIRED 1 ADC 0800 U1 ADC 0800 is 8 bit monolithic Analog to Digital converter using P channel ion implanted MOS technology It contains a high input impedance comparator 256 series resistors and analog switches control logic and output latches Conversion is performed using a successive approximation technique where the unknown analog switches When the approximate tie point approximation technique where the unknown analog switches When the appropriate tie point voltage matches the unknown voltage conversion is complete and the digitaloutputs containa 8 bit complementary binary word corresponding to the unknown The binary output 1s TRI STATE to permit bussing on common data lines The ADC 0800 PD is specified over 55C to 125Cand the ADC 0800 PCD is specified over 0 C to 70 C FEATURES Low cost 10V No Missing Codes Ratio meter conversion Tri State outputs Fast T 50us Contains output latches TTL compatible Supply voltages 5 VDC and 12 VDC Resolution 8 Bits Linearity 1 LSB Conversion speed 40 Clock periods Clock Range 50 to 800 kHz 74163 U8 Synchronous pre settable binary counter The74161 and 74163 are hig
7. for full scale trims in most applications while the non linearity s of better than 0 1 over temperature minimizes system error accumulations The noise immune inputs of the DAC 0800 series will accept TL levels with the logic threshold pin VLC potential will allow direct interface to other logic families The performance and characteristics of the device are essentially uncharged over the full 4 5V to 18 V power supply range power dissipation is only 33nW with the 5 V supplied and is independent of the logic input states The DAC 0800 DAC 0808 DAC 0800C DAC 0801C and DAC 0802C are a direct replacement for DAC 08 DAC 08A DAC 08A DAC O8E and DAC 08H respectively PROCEDURE STEP 1 PCM MODULATION WITH D C INPUT l Switch ON the experimental kit 2 Observe the Basic clock generator output and sampling pulse output 2 zi ve Connect the sampling pulse generator output to the CHI of the CRO and trigger CRO w r t CHI only Observe the output of the parallel to serial converter output PCM data on the CH2 of the CRO Make sure that CRO is triggered with the positive going edge of the sample pulse generator Now connect the variable DC output to the input of the PCM Modulator Adjust the Time div Switch of the CRO such that two samples can be seen at a time on the screen Now vary the D C voltage from its minimum to the maximum At each step observe the parallel data displayed by the LEDsat the ADC outp
8. g xej UN y a mii T Tr talos Q EL W Ju a a a AM 0001 AM 0001 Ti ded ZISL ZLGL Aqdding somod AZI F IL aus l JU I Au DO jndin AV yndut AVI CO INVd UY 092 O 01 qui MAOI d OIN EZ V80 1I T T 103010031 P Jn vo RUuSIG ay T OM OI XE UIN E C Fig P2 6 Circuit Diagram EXPERIMENT NO 2 Pulse Width Modulation PWM AIM To study PWM modulator and demodulator and observe the waveforms THEORY A monostable multivibrator often called a one shot multivibrator is a Pulse generating circuit in which the duration of the pulse is determined by the Rc network connected externally to the 555 timer In a stable or stand by state the output of the circuit 1s approximately zero or at logic low level When an external trigger pulse is applied the output is forced to go high 2 Vcc The time the output remains high 1s determined by the external RC network connected to the timer At the end of the timing interval the output automatically reverts back to its logic low stable state The output stays low until the trigger pulse is again applied Then the cycle repeats The mono stable circuit has only one stable state output low hence the name mono stable Normally the output of the mono stable multivibrator is low The demodulation of the pulse width modulation is quite simple process PWM output is given to a two state RC integrator low pass filter and amplified t
9. gh impedance state the output neither load nor drive the bus lines significantly The output control does not affect the internal operation of the flip flops That is the old data can be retained or new data can be entered even while the outputs are OFF 741 IC U6 Operational Amplifier The mA 141 is a high performance monolithic operational Amplifier connected using the Fair child planar epitaxial process It 1s intended for a wide range of analog applications High common mode voltage range and absence of latch up tendencies make the mA 741 ideal for use as a voltage follower The high gain and wide range of operating voltage provides superior performance integrator summing amplifier and general feedback applications No frequency compensation required Short circuit protected Offset voltage null capability Large common mode and differential voltage ranges Low power consumption No latch up DAC 08 u5 5 bit digital to analog converter DAC 0800 TJ5 series are monolithic 8 bit high speed current output digital to analog converters DAC featuring typical setting times of 100ns When used as 4 multiplying DAC monolithic performance over a 40 to 1 reference current range is possible The DAC 0800 series also features high compliance complementary current outputs to allow differential output voltages of 20Vp p with simple resistor loads The reference to full scale current matching of better than 1 LSB eliminates the need
10. h speed synchronous modulo 16 binarycounters They are synchronously pre settable for application in programmable dividers and have two types of count Enable inputsplus a terminal count output for versatility in forming synchronous multistage counters The 161 has an asynchronous multistage MasterReset input that overrides all other inputs and forces the outputsLOW The 163 has a synchronous Reset input that overrides countingand parallel loading and allows the outputs to be simultaneously reseton the rising edge of the clock 74164 U3 Serial in parallel out shift register The 74164 is a high speed 8 bit serial in parallel out shift register Serial data is entered through a 2 inputs and gate synchronous with the LOW to HIGH transition of the clock The device features as asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock It utilizes the schottky diode clamped process to achieve high speeds 74165 U2 8 Bit parallel to Serial Converter 74165 is an 8 bit parallel load or serial in register with complementary outputs available from the last stage Parallel inputting occurs asynchronously when the parallel load PL input is LOW With PL HIGH serial shifting occurs on the rising edge of the clock new data enters via the serial DATA Ds input The 2 input outlock can be used to combine two independent clock sources or one input can act as an active LOW clock enable 8038 U7 Waveform Genera
11. ing times are not equal In fig 2 capacitor C is charged through R and R2while discharged through R2 If Riis made very small compared to Rothen both time constant will be reduced so that they essentially depend on C and C The frequency of operation f is approximately 0 7 R2C The frequency is of course independent to the supply voltage 3 PAM Modulation circuit arrangement 4 PAM Demodulator circuit arrangement 5 Circuit arrangement 6 AFD Signal Generator di Built in DC Power supply 12 V 350mA 8 Set of Patch chords and User s Manual PROCEDURE Switch on experimental kit Observe the AF signal and carrier clock generators outputs Adjust the AF signal generator O P to 1 Vp p amplitude Apply the AF signal generator output and clock generators output to the PAM modulator Following figure P2 4 shows the testing procedure Sg So pe rs CH1 of CRO CH2 of C RO Modulating Signal Generator Clock seperate By varying the amplitude of the modulating signal depth of modulation changes During demodulation connect PAM output to the input of the PAM demodulator and observe the output of PAM demodulator Following Fig P2 5 shows the testing procedure CH1 of CRO Modulating CH2 of CRO Signal senerator F PAM Modulator Clock Generator RESULT PAM Modulation PAM Demodulation PAM Modulated Signal PAM Demodulated Signal PAM Modulated Signal d LOOF NI x A u
12. iodes 2 My Waveforms of ASK AMAIA ALLA UVU VUV UU AAA MM wo WW RESULT ASK Modulation ASK Demodulation ASK Demodulated Signal ASK Modulated Signal EXPERIMENT NO 6 Phase Shift Keying AIM To study Phase Shift Keying Modulation and Demodulation APPRATUS l IC 1548 2 Transistor SL 100 3 Diode OA79 4 5 2 2kQ 10kQ EE EN NN Lee ll Resistors 100 kQ 22K Q E 3 il Capacitor PROCEDURE 1 Connections are made as shown in the circuit diagram as in Fig P11 1 Apply a square wave modulating signal of 500 Hz 1 kHz 100 kHz bits a 5 V peak to peak amplitude Apply a sine wave carrier signal of 50 kHz of 5V peak to peak amplitude Observe BPSK wave form at point A 5 Demodulate the BPSK signal using the coherent detection Adder Envelope Detector The error in the demodulated wave form can be minimized by adjusting the Vref using 10 kQ POT 25099 Design Specification Vc 5V p Vm 10V fm 500Hz and fe 50KHz Assume h 30 VBE sat 0 7V Vce sat 0 3V Ic ImA k Ic Biasing Voepeak VCE sat IrRg 1 5 0 3 ImA Rg therefore Rgz 2 2KQ Vimpek Relp VBE sa HERE 5 Ralp 4047 2 2 Then Repmx 63KQ choose Rp 22KQ Envelope Detector l fm gt RpCp l fc Sms gt RpCp gt 20us Let RpCp 500 f Ims AssumeCp 0 01uF then Rp LOOKQ choose Rp 100KQ Rp 100KQ Rai Rg 22KQ Re Re 22K O Cp 0 0
13. luF Cc 0 01 uF CHECK POINT 1 Check the OP AMP Transistors and Diodes 2 VrepShould be between the voltage swings of envelope detector output at point A Design Specification Vc 5V V 10V fm 500Hz and fo SOKHz fio SOKHz Assume hy 30 Vg sat 0 7V Vcg sat 0 3V Ic 1mA Ig Ic Biasing Vepeak Vesa IRE 2 5 0 3 ImA Rg therefore Rp 2 2KQ Vimpeak Rplp Vpp a tleRe 9e Ralp 407 22 Then Rgmx 63KQ choose Rp 22KQ EE EN Um END CMM C Ilo qme e M I UPC cori PER Dx to EU ON PSE Y nveforms bas ix E irr A X NC e Ly C ree ede THAT MEAT TM AHFUUU UU UU T DAT AU UU TTT 1 Envelope Detector l fm gt RpCp gt l fc Sms gt RpCp gt 20us Let RpCp 500 f Ims Assume Cp 0 01uF then Rp LOOKQ choose Rp 100KQ Rei Ro 22KQ Re Re 2 2KQ Cp 0 0luF Cc 0 01 uF CHECK POINT 1 Check the OP AMP Transistors and Diodes 2 VrerShould be between the voltage swings of envelope detector output at point A Signal Demod ulated 415 V Comparater e L E _ mh bor hdi e c z oak CL FS c a ou a E e z z C eb r Pu Pa os EA a NN m a Bai 3 J r ij a oO e m 9 M e j E T L m a a r3 p r Ta C zi a zu H a zd ai L z f i ad F E t Jj J C a T f T ei mh J
14. nput PCM Modulation with AC Input E d E po 7 e ES PCM Output Signal PCM Demodulated Signal H i nd PCM Output for sine wave I P 22 13 36 26 11 96 Time of capture CH 1 22 13 36 26 11 96 Time of capture CH 2 22 25 11 26 11 96 Time of print Input lating signal IEEE Ferki 44444 Hair FFH MENEE A eo HIHHH D TO A Converter Cutput 22 30 40 26 11 96 Time of capture CH 1 22 30 40 26 11 96 Time of capture CH 2 sampling Frequency 08 26 11 96 Time of Capture CH 1 08 26 11 96 Time of Capture CH 1 27 26 11 96 Time of Print Modulating Signal Input HHHHHHHHHEHEHHBHEEHE HH HH EH HH i H E i Ern a i t f 1 F Demodulated Output 22 44 41 26 11 96 Time of Capture CH 1 22 44 41 26 11 96 Time of Capture CH 1 22 44 56 26 11 96 Time of Print Digital Data Equivalent To 2V D C Modulating D C VP Sampling Clock Digital Data Equivalent to 2V D C Serical Data O P Demodulated Output EXPERIMENT NO 5 Amplitude Shift Keying AIM To study Amplitude Shift Keying modulation and demodulation APPARATUS Apparatus Range Quantity IC 741 Transistor SI 100 Diode OA79 Resistors POT Capacitor PROCEDURE l Connections are made as shown in the circuit diagrams shown in Fig P9 1 2 Apply a square wave modulating signal of 500 Hz 1000 bits
15. o get the voltage level equal to the AF signal given to the PWM modulator APPARATUS REQUIRED PWM Modulator PWM Demodulator Clock generator AF signal generator Variable amplitude 2V 350 mA fixed dc power supply PWM Modulation and Demodulation kit Trinity Micro systems or any other kit Dual trace oscilloscope Variable RPS power supply pe d NDA cp SX qM Tes PROCEDURE l Switch ON the experiment kit shown in Fig P3 1 Observe the clock generator output and AF signal outputs 3 Connect clock generator output to the clock input point of PWM modulator and observe the same clock on channel 1 of a dual trace CRO 4 Trigger the CRO with respect to CHI 5 Apply a variable DC voltage of 8 to 12 volts from any external regular power supply 6 Observe the PWM output on CH2 7 If we observe the PWM output its width varies according to the DC input voltage 8 A variable amplitude AF signal is given to observe how the PWM signals are varying for AC modulation voltages 9 For this observe AF signal on CHI and PWM output on CH2 NOTE Generally we have to store PWM signals with respect to the modulating signals to get better results Real time CRO also useful but triggering for AC modulating voltages is difficult 10 During the demodulation apply PWM signal to the output of demodulator and Observe its output 11 Output of the demodulator almost coincides with the modulating signal but having some phase difference d
16. operational amplifier fabricated on a signal modulation It is specified over a temperature range from 40 C to 85 C They have finite differential inputs and remain in the linear mode with an input common mode voltage of OV dc Both NPN and PNP external current boost transistors can be used to extend the power capability of the basic amplifiers Application areas include AC amplifiers RC active filters low frequency triangle Square wave and pulse waveform generation circuits techno meters and low speed high voltage digital logic gates Fig 1 shows the pin out diagram of the IC TLO84 PRINCIPAL FEATURES e Internally frequency Compensated for unity gain wide band width unity gain is 1 MHz e Power supply range supply 3 26 volts e Low input offset voltage of 2 milli volts e Input common mode voltage range includes ground The solution is represented by sinusoidal oscillation of frequency f 1 2aRC In practice the resistor Riis made slightly larger than the other resistor to ensure a sufficient positive feedback for oscillations The Zener Diodes V2 used to bound the output of the inverting integration integrator serve to stabilize the amplitude of oscillations 2 Clock generator using 555 IC A conventional astable circuit using a 555 IC Square wave can be obtained by circuit shown in Fig P2 2 5 680 KO 470 PF in The asymmetry of a conventional astable circuit is a result of the fact that charging and discharg
17. the latter a code which indicates the sample Amplitude to the nearest predetermined level is sent Pulse Amplitude modulation PAM is an analog communication whichis discussed in the following section In PAM we have a fixed width of each pulse but the amplitude of each pulse is made proportional to the amplitude of the modulating signal at that instant Pulse Amplitude Modulation generation circuit is shown in Fig Panel layout diagram Sampling clock is applied to the base of the Transistor Modulating signal is given in the collector of the transistor So that the output of the transistor collector current varies according to the modulating signal voltage Sampling clock given at the base of the transistor will appear at the collector same frequency of clock but its amplitude is proportional to the modulating voltage This is Pulse Amplitude Modulation output The Demodulation of the Pulse Amplitude Modulation is quite a sample process Pulse Amplitude Modulation is fed to an integration RC circuit Low Pass Filter from which the Demodulating signal emerges whose amplitude at any time is proportional to the pulse amplitude modulation at that time This signal is given to an inverting amplifier to amplify its level So that the demodulated output is having almost equal amplitude with the modulating signal but it is having some phase difference APPRATUS REQUIRED 1 Modulating signal generator using TL084 LM324 The TLO084 is a quadruple
18. tor ICL 8038 waveform generator is monolithic integrated circuit capable of producing high accuracy since wave forms with a minimum of external components The frequency can be selected externally from QO01 Hz to more than 300KHz using either resistors or capacitors and frequency modulation and sweeping can be accomplished with an external voltage the ICL 8038 is fabricated with advanced monolithic technology using schottky barrier diode and thin film resistors and the output is stable over a wide range of temperature and supply variations as shown in fig 2 74LS374 U4 OCTAL Transparent latch These 8 bit registers feature totem pole TRI STATE output designed specifically for driving highly capacitive or relatively low impedance loads The high impedance state and increased high logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus organised without need for interface or pull up components They are particularly attractive for implementing buffer registers I O ports bi directional bus drivers and working registers The eight flip flops of the LB374 are edge triggered D typeflipflops On the positive transition of the clock the Q output will be set to the logic states that were set up at the D inputs A buffered output control input can be used to place the eight outputs in either a normal logic state high or low logic levels or a high impedance state In the hi
19. ue to RC networks and amplifier are in the demodulator m m dd PWM Modulator AF Input P3 1 Circuit Diagram of PWM Modulation Demodulation i Trinity Microsystems kit RESULT PWM Modulation PWM Demodulation PWM Demodulated Signal PWM Modulated Signal EXPERIMENT NO 3 Pulse Position Modulation PPM AIM To study PPM modulation and demodulation and observe the relevant waveforms THEORY Pulse width modulated signal is given to one more mono stable multivibrator to generate PPM signal Operation is very simple 1 e the width of each pulse of PWM signal varies according to the AF signal amplitude level at that instant The second mono stable multivibrator generates one pulse for each PWM pulse input But the mono stable triggers to the falling edge of the trigger signal PWM the falling edge 1s under the control of AF signal i e so the second mono stable generates on the level of the AF signal input During demodulation in general PPM is converted back to PWM and then gives to RC networks to demodulate In this kit we are demodulating the PPM signal directly by RC networks and amplifier APPARATUS REQUIRED 1 PWM Modulator 2 PPM Modulator 3 PPM Demodulator 4 Clock generator 5 AF signal generator Variable amplitude 6 12 V 350 mA fixed dc power supply 7 PPM Modulation amp Demodulation kit Trinity Micro systems or any other kit 8 Dual trace oscilloscope
20. ut and compare the PCM output Parallel to serial converter which is the same ofthe ADC output but is in serial form Note Between two samples 8 bit serial data will be transmitted STEP 2 PCM DEMODULATION WITH DC INPUT l gt Connect the PCM output to the input of the PCM demodulator Output of the serial to parallel converter displayed by the LEDs is the same with is displayed by the ADC output LEDs Observe the output of the D A converter Observe the output of the low pass filter and adjust the potentiometer such that the output D C voltage is equal to the D C input at the PCM modulator Note Output D C output is 180 out of phase to the input because D to A converter introduces 180 out of phase and low pass filter also introduces some delay because in all practical PCM systems negative logic 1s used to reduce the noise in transmission STEP 3 PCM MODULATION WITH AC INPUT l 2 X Now remove DC and connect the AC voltage to the input of the PCM modulator Observe the PCM output with follows the sequence of the AC input Here one has to make sure that like DC input we cannot see the stable digital output at the PCM modulator output Because this is a dynamic process and with the AC input we cannot send same PCM data between successive samples But in the DC input case at any sample same data will transmitted because at any sample same voltage 1s available not like AC input RESULT PCM Modulation with DC I
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