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1. LBTERM 5 single word read 1 single word write single word read 2 7 Note 227 ADM XRC SDK 4 9 3 User Guide Win32 Direct slave transfers 1 The red lines indicate signals that the master may drive 2 The blue lines indicate signals that the currently addressed slave may drive A slave must not drive these signals unless it has been addressed in the cycle when LADS was asserted 3 It is recommended that the slave actively drive LREADY and LBTERM high for one cycle at the end of a burst because resistive pullups on these lines may not cause them to transition high in time for the next burst which may address a different slave Cycles where this should be done are indicated by the t symbols 4 It is recommended that a slave keeps its LREADY and LBTERM pins tristated in the cycle following LADS to avoid the possibility of contention with a previous slave that is slow to tristate its LREADY and LBTERM pins 5 Some models may assert LBLAST in the same cycle as LADS when a single word transfer is being performed Applications should avoid being sensitive to this behavior 6 With a nonmultiplexed address bus the same master may a new cycle marked by the assertion of LADS immediately after the current cycle terminates Compare with multiplexed address data bus Burst read normal termination The following diagram illustrates a burst read terminated normally
2. No error An error in the API logic occurred Couldn t allocate memory required to complete operation Failed to open the card with specified CardID Failed to open bitstream file The bitstream file appears to be corrupt The bitstream file does not match the FPGA on the card The handle to the card passed was invalid The operation was not completed within the timeout period Card could not be opened because it was already open An invalid parameter was supplied to the call The card was closed before th completed A hardware error occurred on the card An operation was requested which is not supported or implemented The requested devic use The DMA descriptor passed was invalid No free DMA descriptors left The operation failed he operation is still in progress he operation failed for reasons unknown A null pointer was supplied in the call The operation was cancelled becaus requesting thread terminated T is too low operation was or resource was in 1 n he driver revision level A variable of the enumerated type ADMXRC STATUS holds a code indicating the success or failure of a call to an ADM API function 568 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC SYNCMODE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC SYNCMODE D
3. Signal is owned by master m Signalis owned by a save z Suggested tumaround ADM XRC SDK 4 9 3 User Guide Win32 Direct slave transfers LaDs a Jj FO Key Signal is owned LA by master Si li da LER BU 2 J BES z Suggested RIE TAAS CQ LRE AD Y SN t LBTERM t 5 yo y 02 03 f 55 burst write terminated by LBTERM Note 1 LBTERM overrides LREADY and LBLAST Multiplexed address data bus The following diagram illustrates the difference in the local bus protocol on models with a multiplexed address data bus Key Signal is owned by master m Signalis owned by a dave SRR Opes tumaround LBLAST LREAD Yi if t0 if 0 LBTERM double word read double word Note 1 LAD replaces LA and LD The slave must internally track the local bus address as each word of data is transferred 230 ADM XRC SDK 4 9 3 User Guide Win32 Direct slave transfers 2 When a master performs a burst read the slave must not drive LAD in the cycle following the assertion of LADS and must not assert LBTERM or LREADY in that cycle 3 In order to allow LAD to turn around a master must not attempt to begin a new burst by asserting LADS and driving LAD in the cycl
4. 4 Hierarchical primitive instance naming in netlist XST names certain types of primitive for example clock buffers according to their hierarchy level their label and their type Synplify Synplify Pro names an instance strictly according to its label and hierarchy level 205 ADM XRC SDK 4 9 3 User Guide Win32 FPGA Express issues ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data FPGA Express issues There are two several issues that affect users of FPGA Express when building the example designs in the SDK 1 Hierarchical separator character XST uses the _ underscore character as a hierarchy separator whereas FPGA Express uses a forward slash character It is possible to work around this problem as far as constraints in UCF files go by using the wildcard match any single character in the UCF file 2 Hierarchical net naming in netlist XST names nets that are not at the top level differently to FPGA Express A full description of the XST naming convention can be found in the XST user guide FPGA Express names a net strictly according to its name and the highest hierarchy level in which that net is found Fortunately it is often possible to avoid needing to reference nets that are not in the top level in a UCF file 3 Hierarchical primitive instance naming in netlist XST names certain types of primitive for example clock buffers according to their hierarchy level their label and their t
5. Copyright 2001 2009 Alpha Data ADMXRC DMA WIDTH Declaration typedef enum ADMXRC DMA WIDTH ADMXRC DMAWIDTH 8 0 ADMXRC DMAWIDTH 16 ADMXRC DMAWIDTH 32 2 ADMXRC DMA WIDTH ll p Description The ADMXRC_DMA_WIDTH enumerated type determines the width of a DMA transfer in the ADMXRC_BuildDMAModeWord function The ADM XRC and ADM XRC P cards support BYTE WORD and DWORD wide transfers Value Meaning ADMXRC DMAWIDTH 8 BYTE wide 8 bit transfers ADMXRC DMAWIDTH 16 WORD wide 16 bit transfers DMAWIDTH 32 DWORD wide 32 bit transfers 563 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC FPGA TYPE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC FPGA TYPE Declaration typedef enum ADMXRC FPGA TYPE RC FPGA 4085XL RC FPGA 40150XV RC FPGA 40200XV RC FPGA 40250XV RC FPGA V1000 RC FPGA V400 RC FPGA V600 RC FPGA V800 RC FPGA V2000E RC FPGA V1000E RC FPGA V1600E RC FPGA V3200E RC FPGA V812E RC_FPGA_V405E ADMXRC FPGA UNKNOWN ADMXRC FPGA TYPE M lt lt lt lt lt M lt lt X X X X X X X X X X X X X X p gt gt gt gt gt gt lt Description This type represents the FPGA device fitted to a card Certain API functions require knowledge of what FPGA device is fitted in order
6. Replicate for additional demand mode DMA channels see note 4 below LBLAST LATERM ready stop control note 2 Iready oe plxdssm There are a couple of things to note about the above example 1 The generation of qlads causes the plxddsm instance to ignore local bus cycles for which the FPGA is not the target or for which are not demand mode DMA cycles This generally requires only the simplest of address decoders and an expression such as dd qlads 0 lt not lads 1 and not ldack 1 0 and not fholda not 1 23 268 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm deprecated often suffices The above example uses bit 0 of LDACK to qualify LADS implying that DMA channel 0 is being used If DMA channel 1 were being used the following expression could be used instead dd qlads 1 lt not lads 1 and not ldack l 1 and not fholda not 1 23 In other words each plxddsm instance requires its own glads signal which should not be same as the glads signal for the plxdssm instance 2 The control logic for generating the ready and stop inputs should be that of the plxdssm instance The ready and stop signals should be same ones that are input to the plxdssm instance 3 The logic for generating request depends on whether a given demand mode DMA channel is being used to a read or b write the FPGA o For reads the FPGA must typically determine whether or not sufficient data is availabl
7. The value of zbtsram pinout t passed in the pinout parameter of a zbtsram port determines the proper value to pass for the rc width parameter The relevant formula is A rd width 8 B 1 if has_ce2 else 0 Cz1ifhas ce2 l else 0 D 1 if has_cke_l else 0 rc_width A B C D 4 293 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 2 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The arbiter 2 component Overview HDL source code Parameters Signals Performance Overview The arbiter 2 component is part of the memif package and enables a memory port to be shared by two clients The component follows the generic user interface for memory ports so that as far each client is concerned it appears to be communicating with a memory port 294 to from dient 0 to from dient 1 a a width 1 0 vw tag tag width 1 beO d_wieth 8 1 0 d d width 1 0 width 1 0 ctagO tag width 1 0 di1 d width 1 0 q1 d width 1 0 qtaq1 tag_vidth 1 0 valid1 readwyl a a width 1 taa tag width 1 be d width 8 1 pall did width 1 pad width 1 ctaa d width 1 valid ready arbiter 2 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 2 The arbiter 2 module requires a client to assert its request signal reqi when the client wishes to access the memory port In response the arbiter 2 ev
8. Using a Makefile to build all VHDL bitstreams m Using a Makefile to build all Verilog bitstreams o Using a Makefile to build all bitstreams for a specific VHDL or Verilog design 6 Using a Makefile to build a bitstream for a specific VHDL or Verilog design model and device combination Using ISE Project Navigator to build a bitstream ISE Project Navigator files can be generated after installation of the SDK for all supported lt design gt lt model gt lt device gt combinations Once the project files have been generated navigate to the appropriate directory and double click the project file to open it in Project Navigator The following examples illustrate where the project files are located Language Design For model Device Project file located at Verilog DLL ADM XPL 2VP20 fpga verilog dll projnav xpl 2vp20 VHDL Simple ADM XRC II 2V3000 fpga vhdl simple projnav xrc2 2v3000 Note that Xilinx Project Navigator generally gives the bitstreams it generates the same filename as the top level entity in the project but with a BIT extension In order to use the rebuilt bitstream with the example applications it must be copied to the bit lt design gt directory and renamed to the form lt design gt lt model gt lt device gt bit Using a Makefile to build all VHDL and Verilog bitstreams A Makefile in the fpga directory is provided for building all of the bitstreams in the SDK in both Verilog and VHDL versions S
9. When data is written to a memory bank the port repl module takes 64 bit data words from the local bus interface on mem d and and assembles them into words suitable for the memory ports in this case DDR II SDRAM ports whose logical data with is 128 A set of async port instances bridge the local bus clock domain and the memory clock domain In the memory clock domain a set of arbiter 2 instances connect together both the preceding async port instances and the user application to the memory ports ddr2sdram port instances When data is read from a memory bank logical data words flow from the memory ports through the arbiter 2 instances and through the async port instances A multiplexor selects the data from a particular async port according to the current value of the BANK register Finally the port mux instance performs width conversion from logical data words 128 bits to the local bus data width 64 bits outputting the data on mem q Explanation of memory banks module inbound datapath Continuing with the ADM XRC 4FX version as an example the following figure shows detail for the data path from the local bus interface to the memory banks pf async potg s 0 signas sel bank 1h i port pce D mem ce zi LL pe port pterm D cw T other ports _ 31 1 _ Lp port repl A mem d adi rep d async porta port s 3 rep he mpbe l 1 s T8 signals m
10. e The ADM XRC II has six physical 36 bit SSRAM banks The 4 parity bits are dropped and the 32 data bits are mapped to one 32 bit logical SSRAM bank This results in six logical SSRAM banks e The ADM XRC II Lite uses 18 bit SSRAMs Two physical banks are put together to form a 36 bit bank The 4 parity bits are then dropped and the 32 data bits are mapped to one 32 bit logical SSRAM bank This results in two logical SSRAM banks e The ADM XPL has a single 64 bit SSRAM device The low 32 bits are mapped to one 32 bit logical SSRAM bank This results in a single logical SSRAM bank e The ADM XRC 4LX has six physical 32 bit SSRAM banks This results in six logical SSRAM banks e The ADM XRC 4SX has four physical 32 bit SSRAM banks This results in four logical SSRAM banks The design also contains a register that selects the number of address bits in the logical SSRAM banks Address lengths of 17 18 19 and 20 bits are accomodated The page register augments the limited address space 2MB allotted to accessing the SSRAM The following figure illustrates this for an ADM XRC II with six 512k x 36 ZBT SSRAM devices fitted 160 ADM XRC SDK 4 9 3 User Guide Win32 ZBT P AGE 7 0 0x3 Ox400000 Local bus byte address LA 21 0 0x200000 Register region 2MB FPGA Space Usage SSR AM window 2MB 0x400000 No bank Returns zeroes No bank Returns zeroes Bank 5 2MB Bank 4 2MB Bank 3 2
11. ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v4 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sram port v4 component Virtex 4 Virtex 5 only Overview HDL source code Parameters Signals Performance Overview The ddr2sram port v4 component is part of the memif package and implements an interface to a bank of DDR II SSRAM memory This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure ala width 1 0 toram w width 1 0 tag tag width 1 0 refre width 1 0 memory beld width 8 1 0 raed width 1 0 device s did midh 1 0 dall off ad width 1 0 wrth 1 0 valid port v 349 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v4 HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif cmd fifo vhd fpga vhdl common memif ddr2sram v4 ddr2sram iserdes dq vhd fpga vhdl common memif ddr2sram v4 ddr2sram oserdes dq vhd fpga vhdl common memif ddr2sram v4 ddr2sram bwe vhd fpga vhdl common memif ddr2sram v4 ddr
12. ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note 1 If logic revision from INFO utility is 1 2 or greater maximum LCLK frequency is 80MHz otherwise 66 67MHz 462 Clock index 0 O O O eo O O 0D 0 0 0 0 0 0 Qo LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK LCLK LCLK MCLK LCLK MCLK LCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK LCLK MCLK Range 400kHz 40MHz 400kHz 100MHz 400kHz 40MHz 400kHz 100MHz 400kHz 40MHz 400kHz 100MHz 400kHz 66MHz 400kHz 100MHz 6MHz 80MHz See note 1 below 6MHz 80MHz 400kHz 66MHz 400kHz 100MHz 400kHz 66MHz 400kHz 100MHz 6MHz 80MHz 400kHz 66MHz 33MHz 500MHz 400kHz 66MHz 33MHz 500MHz 32MHz 80MHz 31MHz 640MHz 6MHz 80MHz 33MHz 500MHz 32MHz 80MHz 33MHz 500MHz 32MHz 80MHz 31MHz 640MHz 32MHz 80MHz 31MHz 640MHz 32MHz 80MHz 31MHz 640MHz 32MHz 80MHz 31MHz 640MHz 32MHz 80MHz 31MHz 640MHz Function Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock Note that MCLK 2 LCLK Local bus clock Note that MCLK 2 LCLK Local bus clock General purpose Local bus clock General purpose Local bus clock Note that M
13. Flag Meaning ADMXRC2 SPACE SET WIDTH The bus width for the local bus space is specified must be accompanied by one of the ADMXRC2 SPACE WIDTH XXX flags ADMXRC2 SPACE WIDTH DEFAULT The model specific default bus width is requested equates to one of the other ADMXRC2 SPACE WIDTH XXX flags depending on the model ADMXRC2 SPACE WIDTH 8 8 bit local bus width is requested ADMXRC2 SPACE WIDTH 16 16 bit local bus width is requested 463 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_SetSpaceConfig ADMXRC2 SPACE WIDTH 32 32 bit local bus width is requested ADMXRC2 SPACE WIDTH 64 64 bit local bus width is requested ADMXRC2 SPACE SET PREFETCH The prefetch behaviour for the local bus space is specified must be accompanied by one of the ADMXRC2 SPACE PREFETCH XXX flags ADMXRC2 SPACE PREFETCH DEFAULT The model specific default prefetch behaviour is requested corresponds to one of the other ADMXRC2 SPACE PREFETCH XXX flags depending on the model ADMXRC2 SPACE PREFETCH MINIMUM The minimum amount of prefetching is requested on some models this equates to no prefetching ADMXRC2 SPACE PREFETCH NORMAL nominal amount of prefetching is requested ADMXRC2 SPACE PREFETCH MAXIMUM The maximum amount of prefetching is requested on some models this may equate to unlimited prefetching ADMXRC2 SPACE SET BURST The bursting behaviour for the local bus space is specified must be accompanied by one of the ADMXRC2 SPACE BURST XXX flags ADMXRC2 SPA
14. LBTERM multi burst bus tenure Note 1 A master may perform an arbitrary number of bursts during its bus tenure A master voluntarily gives up the bus when it has finished with the bus by deasserting its HOLD signal 2 On some models sideband signals connected between agents can cause an agent to relinquish the bus at the request of another agent 3 Strictly speaking since the master retains ownership of the bus between the bursts that make up its tenure it could drive LADS LBLAST etc between bursts with no possibility of contention Two bus tenures The following timing diagram illustrates two bus tenures by the same master 255 ADM XRC SDK 4 9 3 User Guide Win32 Arbitration wek UUUUUUUUUUUUUUUUUUUUUUUUU HOLD SCT Key Signal is driven HOLD A _ a ae by arbiter m Signal is driven LADS ae by master LBLAST m Signal driven by a dave LRE AD Y 1 LBTERM multiple bus tenures by the same master Note 1 After an agent transitions HOLD it must wait for the arbiter to acknowledge the change via HOLDA before transitioning HOLD again 256 ADM XRC SDK 4 9 3 User Guide Win32 Direct master transfers ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Direct master transfers Direct master transfers will be documented in a future release of the SDK 257 ADM XRC SDK 4 9 3 User Guide Win32 Tips for local bus
15. NOT OK ADM XRC SDK 4 9 3 User Guide Win32 byte t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference byte t Declaration Synopsis Description Declaration subtype byte t is std logic vector 7 downto 0 Synopsis A byte t holds a single byte value Description The type byte t is used to construct the byte vector t type Since it is a subtype of std logic vector many standard VHDL functions can be used to manipulate values of this type 364 ADM XRC SDK 4 9 3 User Guide Win32 byte vector t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference byte vector t Declaration Synopsis Description Declaration type byte vector t is array natural range lt gt of byte t Synopsis byte vector tis a vector type used to hold data for a local bus transfer Description Use this vector type to hold the data for a local bus transfer in a call to one of the following functions e plxsim read e plxsim read const e plxsim read demand e plxsim read const demand e plxsim write e plxsim write const e plxsim write demand e plxsim write const demand Each element of the vector is a byte of data and normally the length of a byte vector t value should be same as the length of the byte enable t value it is associated with For writes each element of the vector will be driven onto one of the byte lanes of the local bus LD or LAD sign
16. The RearlO example application configures the target FPGA with a bitstream that outputs a walking 1 bit on the rear panel I O connector As soon as the bitstream has been loaded the application terminates Syntax reario options Options Option Type Meaning card base 10 integer ID of card to open index base 10 integer Index of card to open FPGA Design 71 ADM XRC SDK 4 9 3 User Guide Win32 RearIO The RearlO example application uses the RearlO sample FPGA design Verilog VHDL 72 ADM XRC SDK 4 9 3 User Guide Win32 Simple ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Simple sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview The Simple sample application demonstrates how to implement registers in the FPGA that are accessible from the host using direct slave cycles Syntax simple options Options Option Type Meaning card base 10 integer ID of card to open index base 10 integer Index of card to open 64 Operate local bus in 32 bit mode default 64 Operate local bus in 64 bit mode 73 ADM XRC SDK 4 9 3 User Guide Win32 Simple Description The user enters hexadecimal values which the application writes t
17. User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but refer to the section below for a discussion of how to maximize performance Capture edge 10 This signal is normally driven directly by an instance of the component ddrsdram training v2 and contains information instructing ddrsdram port v2 how to retime the data captured from the SSRAM device using clkcO and clkc180 into the clkO domain Clock for user interface 7 All other signals except rst are synchronous to clkO High speed clock phase 90 7 This clock must be the same frequency as clkO but lagging by 90 degrees High speed clock phase 180 7 This clock must be the same frequency as clkO but lagging by 180 degrees High speed clock phase 270 7 This clock must be the same frequency as clkO but lagging by 270 degrees ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 clkcO clkc180 col pbank qtag ready regd row 328 in in out out
18. arbiter component e A local bus agent component for a nonmultiplexed 32 bit local bus e A local bus agent component for a multiplexed 32 bit local bus e A local bus agent component for a multiplexed 64 bit local bus Some example testbenches are provided with the sample FPGA designs Example Modelsim scripts that compile and run these testbenches are also provided Please refer to the documentation for the individual sample FPGA designs for details A simple testbench A simple testbench using the plxsim package consists of the unit under test FPGA design a stimulus process a local bus agent and the arbiter The following figure illustrates this 360 ADM XRC SDK 4 9 3 User Guide Win32 PLXSIM package VHDL FPGA design unit under test Arbiter rocess locbus in t p ocbus in 1 LOCAL reset agent BUS Ibe lholda lt 0 gt Ihold 02 Here the stimulus process might represent the Host CPU performing Direct Slave reads and writes of the FPGA This process is not provided by the plxsim package rather it must be written by the user of the plxsim package in order to drive the local bus agent The stimulus process uses the procedures provided by the plxsim package and this enables it to be written in a logical procedural way The local bus agent is a component provided by the plxsim package There are several types of local bus agent For example a simulation targetting the ADM XRC I
19. 541 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC SyncDirectMaster e Call ADMXRC SyncDirectMaster specifying ADMXRC SYNC FPGATOCPU for Mode after the FPGA has operated on an application buffer and before the CPU examines the data in the buffer By the time ADMXRC SyncDirectMaster returns modifications made to an application buffer will be visible to the FPGA and vice versa The Offset and Length parameters identify a region within the application buffer which DmaDesc refers to This region should cover the parts of the user buffer which have been operated upon by the CPU or FPGA The Mode parameter should be one of members of the ADMXRC_SYNCMODE enumerated type NOTE This function is not required by an application which uses only direct slave transfers programmed I O and DMA transfers via ADMXRC_DoDMA and ADMXRC_DoDMAImmediate 542 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC_UnloadFpgaFile ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC UnloadFpgaFile Prototype ADMXRC STATUS ADMXRC UnloadFpgaFile ADMXRC IMAGE Image Arguments Argument Type Purpose Image In Bitstream file to remove from memory Return value Value Meaning ADMXRC SUCCESS The bitstream file was successfully unloaded Description This function frees the memory used to hold the SelectMap data of an FPGA bitstream Image should be a value of type ADMXRC IMAGE obtained from an earlier call to ADMXRC LoadFpgaF
20. Declaration procedure plxsim wait demand signal bus in gt in locbus in t signal dd in gt in locbus ddma in t Synopsis Waits for the FPGA unit under test to request a demand mode DMA local bus transfer Description Call this procedure in order to wait for the FPGA unit under test to assert LDREQ before calling one of the following procedures e plxsim read const demand e plxsim read demand e plxsim write const demand e plxsim write demand 394 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim write Declaration Synopsis Description Declaration procedure plxsim write order e OU natural multiburst in boolean address in std logic vector be in byte enable t data 25 suh byte vector t nxfered out natural signal bus in in locbus in t signal bus out out locbus out t Synopsis Performs a basic local bus write transfer with incrementing local bus address Description This procedure uses the bus in and bus out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim write FPGA design under tes t aut Stimulus rocess mete iy d p achbus in 1 Local bus LOCAL agent BUS ike J The order parameter specifies the width of the local data bus Valid values are e 2 for a 32
21. Direct master transfers Tips on local bus interface design 209 ADM XRC SDK 4 9 3 User Guide Win32 Generic local bus signals ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Generic local bus signals The FPGA and the local bus bridge on an ADM XRC series card are connected by a local bus This bus consists of signals in two categories e Bussed signals which can be driven by either the FPGA or the local bus bridge e Sideband signals which provide a means for the FPGA to generate interrupts and make use of demand mode DMA While the underlying protocol is the same for each model in the XRC range there are some differences in the names and number of local bus signals due to the different devices used for the local bus bridge The following topic provides details about the differences between models Model specific signals 210 ADM XRC SDK 4 9 3 User Guide Win32 Bussed signals ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Local bus signals The table below lists the signals that comprise the local bus There are some variations between models in the ADM XRC range in the naming and number of signals Refer to the notes for each signal for details Note 211 Signal HOLD HOLDA Driven by a local bus agent bus arbiter Description Hold HOLD is asserted by a local bus agent in order to arbitrate for ownership of the local bus It is not a b
22. Function Value that specifies the number of address bits in a logical SSRAM bank 0 gt 17 128k words 1 2 18 256k words 2 gt 19 512k words 3 gt 20 1M words Augmented quadword address P amp GE 7 0 LA 20 3 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 Information register INFO local bus address 0x10 Bits Mnemonic Type Function 23 0 BANKSIZE RO Returns size in words of each logical SSRAM bank 31 24 NUMBANK RO Number of logical SSRAM banks in the design Status register STATUS local bus address 0x14 Bits Mnemonic Type Function 0 LCLK LOCKED RO Returns 1 if the local bus clock LCLK DCM DLL is currently locked RAMCLK LOCKED RO If nis the number of SSRAM clock signals in the design this register returns 1 in a particular bit if the DCM DLL for that clock signal is currently locked Bit 1 corresponds to SSRAM clock 0 31 1 Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XPL Zbt64 xpl v2p scr Zbt64 xpl v2p prj zbt64 xpl ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XPL projnav xpl lt device gt Modelsim scripts Example Modelsim compatible script files for simulating this design are provided Refer to the following table for the a
23. In the above figure only the logic for a single memory bank is shown but each memory bank has an identical set of logic consisting of an async port an arbiter 2 and a ddr2sdram port There are a number of generic signals that work in the same way regardless of the type of memory to which the memory port interfaces These signals work as follows e The ce signal instructs the memory port to perform an access to the memory devices In each clock cycle that ce is asserted one command is issued to the memory port e The w signal is qualified by ce and specifies whether a memory access should be a read 0 or a write 1 144 e The a signal is qualified by ce and specifies the word of memory that should be accessed This address is not a byte address rather it should be considered to be an index into an array of words whose width is the native memory width for example 128 bits for a DDR II SDRAM port in the ADM XRC 4FX e The tag signal is qualified by the logical AND of ce and not w and is a value to be associated with a particular read command The tag value and width is at the discretion of the designer and can be whatever he or she wants When the memory port asserts valid for a given read command i e assertion of ce in a particular clock cycle the qtag signal reflects the tag value that was present on the tag input when ce was asserted One application of the tag signal is in the async port module it uses the tag to avoid returning
24. LO ACH3 1 0 LORE Gaf1 0 ADM XRC II Lite The following figure shows the connections between the PCI9080 local bus bridge and the FPGA in an ADM XRC II Lite card 219 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals LHOLD A FHOLDA central resource LCLK LINTI FIM Tl LRE SET LADS 3 0 LATE RM LETER MOH LRE amp D 12 LREAD Yos LO ACH3 1 0 LORE Gaf1 0 ADM XRC II The following figure shows the connections between the PCI9656 local bus bridge and the FPGA in an ADM XRC II 220 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals LHOLD A FHOLDA central resource LIM Tl FIM Tl LRE SET La 31 2 LaDs 9656 LBLAST LATE Fiti LO 31 0 LREADY CC LYWRITE LO ACH3 1 0 LORE G3f1 0 ADM XPL ADM XP and ADP XPI The following figure shows the connections between the local bus bridge and the FPGA in an ADM XPL ADM XP or ADP XPI card note that the local bus is capable of operating in 32 bit or 64 bit mode 221 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals LHOLD A FHOLDA central resource LIM Tl FIM Tl LRE SET LAD 63 0 1 31 0 LADS local bus bridge LBE 47 0 LBE2 3 0 LBL ASTE 4 o LATE Fihi LRE ADY LO ACH3 1 0 LORE G3f1 0 ADP WRC II and ADP DRC II The following figure shows the connections between the PCI9656 local bus bridge and the FPGA in an ADP
25. Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga vhdl master Synopsis The Master FPGA design demonstrates direct master access by the FPGA to host memory FPGA Space Usage 106 ADM XRC SDK 4 9 3 User Guide Win32 Master The design implements several registers for generating Direct Master transfers to and from host memory Address register ADDR local bus address 0 0 Bits Mnemonic Type Function 1 0 MBZ 31 2 ADDR WO This field holds the local bus address to be used for the next Direct Master transfer Writing to bits 31 24 initiates a Direct Master transfer so this register should be written after the other registers have been initialized Write data register WDATA local bus address 0x4 Bits Mnemonic Type Function 31 0 VAL WO For Direct Master write transfers this register holds the 32 bit data value that should be written Configuration register CFG local bus address 0x8 Bits Mnemonic Type Function 0 WRITE WO When this field is 1 the next Direct Master transfer is a write otherwise it is a read 31 1 MBZ Read data register RDATA local bus
26. Other values should not be used 557 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC CLOCK TYPE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC CLOCK TYPE Declaration typedef enum ADMXRC CLOCK TYPE ADMXRC CLOCKTYPE 16 0 ADMXRC CLOCKTYPE 14 1 ADMXRC CLOCK TYPE Description This type indicates the frequency of the reference oscillator fitted to a card as returned by ADMXRC_GetClockType and is one of the following values Value Meaning ADMXRC CLOCKTYPE 16 16 667MHz ADMXRC CLOCKTYPE 14 14 318MHz 558 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DEVICE NUM ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC DEVICE NUM Declaration typedef unsigned long ADMXRC DEVICE NUM Description A value of type ADMXRC DEVICE NUM identifies a particular card in a system and is used primarily with the ADMXRC OpencCard function 559 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DMADESC ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC DMADESC Declaration typedef unsigned long ADMXRC DMADESC Description A value of type ADMXRC_DMADESC is a DMA descriptor representing a locked down non swappable application buffer DMA descriptors are allocated and freed by ADMXRC SetupDMA and ADMXRC UnsetupDMA They are used with the ADMXRC DoDMA ADMXRC_DoDMAImmediate ADMXRC MapbDirectMaste
27. This bus carries address information to from the memory port to the memory device s This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together into the rc bus so that for the most part the user application need not care what they Refer to note 2 for the mapping of the rc bus to device pins inout Memory device control bus are inout Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via ce one word is transferred on rd which determines the relationship between the rd width and d with parameters Refer to note 3 for details ADM XRC SDK 4 9 3 User Guide Win32 PLXSIM package VHDL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The plxsim package Overview A simple testbench A multithreaded testbench Overview plxsim is a package of HDL datatypes constants functions procedures and components designed to speed up development of a testbench centered around the local bus interface of an FPGA design It is currently implemented only for VHDL 93 or later but a Verilog 2001 version is on the roadmap PLXSIM provides e Datatypes representing bytes and arrays of bytes e Procedures for performing various types of transfer on the local bus e Functions for converting between datatypes e A local bus protocol checker component e
28. XRC or ADM XRC P models The ADMXRC2_OpenCardByIndex function not present in the ADMXRC interface can open a card based on its index within the system as opposed to its Card ID Functions the ADMXRC2 interface that require a parameter that specifies the DMA channel to use accept an unsigned int value for the DMA channel whereas the ADMXRC interface functions used an enumerated type The following functions from the ADMXRC2 interface are affected o ADMXRC2 ConfigureFromBufferDMA o ADMXRC2 ConfigureFromFileDMA o ADMXRC2 DoDMA o ADMXRC2 DoDMAImmediate There is no function equivalent to ADMXRC_GetClockType in the ADMXRC2 interface This is because applications should not rely on a particular reference oscillator being fitted to a card there may not be one at all and the API takes care of programming the clock generators on a card The ADMXRC ReadReg and ADMXRC_WriteReg functions are not present in the ADMXRC2 interface as ADMXRC2 Read and ADMXRC2 Write with the appropriate parameters achieve the same effect The ADMXRC2 ReadConfig and ADMXRC2 WriteConfig functions are new to the ADMXRC2 interface and allow the configuration EEPROM on a card to be read and written The ADMXRC2 GetSpacelnfo function is equivalent to ADMXRC GetBaseAddress from the ADMXRC interface The ADMXRC CARD INFO structure of the ADMXRC interface has been replaced by the ADMXRC2 CARD INFO ADMXRC2 SPACE INFO and ADMXRC2 BANK INFO structures of the ADMXRC
29. fpga vhdl chipscope src ilap pkg vhd fpga vhdl chipscope src ilacombo sim vhd fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif cmd fifo vhd fpga vhdl common memif ddr2sram ddr2sram port vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the port logical address a 4 d width natural Width in bits of the port data in and out d and q 3 respectively pinout ddr2sram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants ra width natural Width in bits of the memory device address bus ra 1 rc width natural Width in bits of the memory device control bus rc 2 rd width natural Width in bits of the memory device data bus rd 3 tag width natural Width in bits of the tag in and out tag and qtag respectively Notes 1 The ra width parameter is a property of the printed circuit board indicating how many wires are physically present rather than indicating how many of the ra lines are used by a particular DDR II SSRAM device 2 The memory device control bus rc is composed of various fields in this
30. is one of the sample FPGA designs for example ddma Because this process may create dozens of ISE files it may take a few minutes to run to completion and may consume up to 40 MB of disk space 77 ADM XRC SDK 4 9 3 User Guide Win32 Building ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Building the sample FPGA designs Bitstreams for all supported combinations of design model and device are supplied prebuilt in the bit directory of the SDK This directory is to the sample FPGA designs what the bin directory is to the sample applications All of the sources from which the bitstreams were built are supplied in the fpga directory so these bitstreams can be rebuilt from sources if necessary Note that after rebuilding a particular bitstream it will not automatically be picked up by the sample applications the bitstream must be manually copied to the appropriate directory namely bit design relative to the root directory of the SDK If built using Xilinx Project Navigator the bitstream must be renamed to the form lt design gt lt model gt lt device gt bit For serious work it is recommended that the user set up his own directory structure and naming convention for bitstreams in order to avoid the need to copy files The ADM XRC SDK provides several ways to build the sample FPGA designs 1 Using ISE Project Navigator to build a bitstream Using a Makefile to build all VHDL and Verilog bitstreams
31. repeat base 10 integer ESIC IE Ey usedma usedma usepio tusepio 64 64 Description Specifies optional mask to be applied during memory tests default all ones Memory clock frequency to use in MHz default depends upon type of card Do not measure host memory acess throughput Measure host memory acess throughput default Do not enable Virtex 5 IDELAYCTRL reference clock workaround default Enable Virtex 5 IDELAYCTRL reference clock workaround Number of times to perform tests default 1 Do not retry reads if data verification errors occur default Retry reads if data verification errors occur can be used to gather evidence about whether errors are occurring when reading or when writing Do not perform tests using DMA transfers Perform tests using DMA transfers default Do not perform tests using programmed I O transfers default Perform tests using programmed I O transfers Operate local bus in 32 bit mode default Operate local bus in 64 bit mode The Memory sample application tests all banks of on board memory on a reconfigurable computing card Unlike the Memtest application that it supersedes the Memory sample application tests all banks of memory on a card regardless of the type of memory and whether or not a mixture of memory types are present When run the Memory sample application performs a memory test consisting of the following phases 1 0x55 OxAA patter
32. tco p2p 5 xm time 5 ns n arb natural priority in integer vector t port lreset 1 std logic lclk in std logic lhold in std logic vector n arb 1 downto 0 lholda 2 Out std logic vector n arb 1 downto 0 end component Synopsis Non synthesizable testbench component that performs access arbitration on the local bus ta fram local Ihalda bus agents Ihald lochus ark Description This component can be instantiated in a testbench to arbitrate between several local bus agents for access to the local bus The arbitration scheme works as follows e An agent of a given priority can always preempt an agent of lower priority no matter how long ago the lower priority agent was granted access to the bus e Given two agents of the same priority the one that was least recently granted access to the bus can preempt the other The generics should be mapped as follows 417 ADM XRC SDK 4 9 3 User Guide Win32 locbus arb Generic tco p2p n arb priority Map to A value of type time that represents the desired local bus clock to output delay for signals such as LDACK This parameter has a suitable default value so it need not be specified An integer whose value is the number of local bus agents in the testbench This value is also the length of the vectors Ihold and Iholda since there must be one pair of signals per local bus agent An integer vector type integer vector t that spe
33. the basic unit of data transfer is a burst of variable length e Word addressed byte granularity is achieved via byte enables e Asynchronous to host I O bus the clock frequency of the local bus can be varied to a suit a particular FPGA design independent of host PCI PCI X bus interface The differences between the models in the ADM XRC range can be summarized by the following table Feature ADM XRC ADM XRC II Lite ADM XRC II ADM XRC P FPGA technology Virtex Virtex ll Virtex ll Virtex E Virtex EM Memory technology ZBT SSRAM ZBT SSRAM ZBT SSRAM Max local bus frequency 40 0MHz 40 0MHz 66 67MHz Multiplexed address data on No No No local bus Supported data widths on 32 bits 32 bits 32 bits local bus PCI to local bus bridge PCI9080 PCI9080 PCI9656 Feature ADP DRC II ADP WRC II ADM XPL FPGA technology Virtex ll Virtex ll Virtex Il Pro Memory technology DDR SDRAM DIMM DDR SDRAM DDR SDRAM DDR II SSRAM ZBT SSRAM Max local bus frequency 66 67MHz 66 67MHz 80 0MHz see note 1 below Multiplexed address data on No No Yes local bus Supported data widths on 32 bits 32 bits 32 bits local bus 64 bits PCI to local bus bridge PCI9656 PCI9656 Virtex ll Feature ADM XP ADP XPI ADM XRC 4LX FPGA technology Virtex Il Pro Virtex Il Pro Virtex 4 LX Memory technology DDR SDRAM DDR SDRAM DIMM ZBT SSRAM DDR II SSRAM DDR II SSRAM Max local bus frequency 80 0MHz 80 0MHz 66 67MHz 208 ADM XRC SDK 4 9 3 User Guide Win32 Introd
34. v5fxt 4banks prj memory xrc5t2 v5fxt 6banks prj memory xrc5t2 v5sxt 6banks prj memory xrc5tz vblxt prj memory xrc5tz vblxt prj memory xrcbtz vbfxt prj memory xrcbtz vbfxt prj xrcAlx memory xrc4lx ucf xrc4sx memory xrc4sx ucf xrcAfx memory xrc4fx 4vfx100 ucf xrcAfx memory xrc4fx 4vfx140 ucf xrce4fx memory xrce4fx 4vfx100 ucf xrce4fx memory xrce4fx 4vfx140 ucf xrcblx memory xrcb5lx ucf xrcbt1 memory xrcbt1 5vfxt ucf xrcbt1 memory xrcbt1 ucf xrcbt1 memory xrcbt1 ucf xrcbt2 memory xrcbt2 5vlx1 10t ucf xrcbt2 memory xrcbt2 5vIx330t ucf xrcbt2 memory xrcbt2 5vfx100t ucf xrcbt2 memory xrcbt2 5vfx130t ucf xrcbt2 memory xrcbt2 5vfx200t ucf xrcbt2 memory xrcbt2 5vsx240t ucf xrcbt2 memory xrcbtz 5vlx110t ucf xrcbt2 memory xrcbtz 5vIx330t ucf Xrcbt2 memory xrcbtz 5vfx100t ucf xrcbt2 memory xrcbtz 5vfx130t ucf ADM XRC SDK 4 9 3 User Guide Win32 Memory ADM XRC 5TZ memory xrcbtz vbfxt scr memory xrcbtz vbfxt prj xrcbt2 memory xrcbtz with V5FX200T 5vfx200t ucf ADM XRC 5TZ memory xrcbtz v5sxt scr memory xrc5tz v5sxt prj xrcbt2 memory xrcbtz with V5SX240T 5vsx240t ucf ADM XRC 5T memory xrcbtda1 vbfxt scr memory xrcbtdal1 v5fxt prj xrc5tda1 memory DA1 with V5FXT xrcbtda1 5vfxt ucf ADM XRC 5T memory xrcbtdal1 v5lxt scr 5 1 v5lxt prj xrcbtda1 memory DA1 with V5LXT xrcbtda1 ucf ADM XRC 5T memory xrc5tdai v5sxt scr memory xrcb
35. 13 3 10 7 6 BANKS R W This field selects the number of bank address bits in the DDR II SDRAM devices 0x0 gt no bank bits 1 internal bank 0x1 gt 1 bank bit 2 internal banks 0 2 gt 2 bank bits 4 internal banks 0x3 gt 3 bank bits 8 internal banks 9 8 PBANKS R W This field selects the number of chip select pins in the memory bank 0x0 gt 1 physical bank 0x1 gt 2 physical banks 0x2 gt 4 physical banks 0x3 gt 8 physical banks 31 10 MBZ USER registers USERO USER63 local bus address 0x100 0x1FF There are a total of 64 USER registers occupying local bus addresses 0x100 to Ox1FF inclusive The interpretation of the USER registers depends upon the logic within the user app module and the description below applies only to the unmodified user app module that ships with this SDK USERO USEH15 The first 16 user registers specify the starting addresses counting in logical data words where the chip driven memory test should begin testing each memory bank Bits Mnemonic Type Function 31 0 OFFSET R W Specifies the starting address at which to begin testing a particular memory bank USER16 USER31 The next 16 user registers specify the number of logical data words that the chip driven memory test should test in each bank Bits Mnemonic Type Function 31 0 LENGTH R W Specifies the number of logical data words to test in a particular memory bank minus 1 For example to test 1 megaword write th
36. ADM XRC 5T1 with V5LXT ADM XRC 5T1 with V5SXT ADM XRC 5T2 or ADM XRC 5T2 ADV with V5LX110T V5LX155T or V5LX220T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5LX330T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5FX100T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5FX130T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5FX200T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5SX240T ADM XRC 5TZ with V5LX110T V5LX155T or V5LX220T ADM XRC 5TZ with V5LX330T ADM XRC 5TZ with V5FX100T ADM XRC 5TZ with V5FX130T 128 memory xrc4lx v4lx scr memory xrc4sx v4sx scr memory xrc4fx v4fx scr memory xrc4fx v4fx scr memory xrce4fx v4fx scr memory xrce4fx v4fx scr memory xrcblx v5lx scr 511 v5fxt scr memory xrcbt1 v5lxt scr memory xrcbt1 v5sxt scr memory xrcbt2 v5lxt 4banks scr memory xrcbt2 v5lxt 6banks scr memory xrcot2 vbfxt 4banks scr memory xrc5t2 vbfxt 4banks scr memory xrcbt2 vbfxt 6banks scr memory xrc5t2 v5sxt_6banks scr memory xrcdtz v5Ixt scr memory xrc5tz vblxt scr memory xrcbtz vbfxt scr memory xrcbtz vbfxt scr memory xrc4lx v4lx prj memory xrc4sx v4sx pr memory xrc4fx v4fx prj memory xrc4fx v4fx prj memory xrce4fx v4fx prj memory xrce4fx v4fx prj memory xrc5lx v5lx prj memory xrcbt1 vbfxt prj memory xrcbt1 vb5lxt prj memory xrcbt1 v5sxt prj memory xrc5t2 v5lxt 4banks prj memory xrc5t2 v5lxt 6banks prj memory xrc5t2 v5fxt 4banks prj memory xrc5t2
37. ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC WriteReg Prototype ADMXRC STATUS ADMXRC WriteReg ADMXRC HANDLE unsigned char Index unsigned char Value Arguments Argument Type Purpose Card In Handle of card on which the write is to take place Index In Index of control register to write Value In Byte to write to control register Return value Value Meaning ADMXRC SUCCESS The data was written successfully ADMXRC INVALID HANDLE Card is not a valid card handle ADMXRC INVALID PARAMETER Index was out of range Description The ADMXRC WriteReg function writes to the byte wide control registers on an ADM XRC or ADM XRC P card The Index parameter specifies the index of the register to write to Please refer to the user manual for your card for a map of the control registers The Value parameter is the value to write to the specified register 548 ADM XRC SDK 4 9 3 User Guide Win32 Structures ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC interface structures This section describes the composite datatypes of the ADMXRC interface Name Purpose ADMXRC BUFFERMAP Contains a physical page map of an application buffer ADMXRC CARD INFO Information about a card ADMXRC VERSION INFO Information about the API and driver version 549 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC BUFFERMAP ADM XRC SDK 4 9 3 User Guide Win32 Copyrigh
38. ADMXRC2_GetSpaceConfig ADMXRC2_HANDLE Card unsigned int SpaceIndex DWORD Flags Arguments Argument Type Purpose Card In Handle of card Spacelndex In The index of the space whose configuration is to be returned Flags Out Flags indicating configuration Return value Value ADMXRC2 SUCCESS ADMXRC2 INVALID HANDLE ADMXRC2 NOT SUPPORTED Description Meaning The space configuration was successfully retrieved The Card handle was not valid An invalid space was specified via Spacelndex This function returns the current configuration of a local bus space The Spacelndex parameter is a zero based index that specifies the local bus space whose configuration is to be returned The Flags parameter returns the current following table Flag ADMXRC2 SPACE WIDTH 8 ADMXRC2 SPACE WIDTH 16 ADMXRC2 SPACE WIDTH 32 ADMXRC2 SPACE WIDTH 64 ADMXRC2 SPACE PREFETCH MINIMUM ADMXRC2 SPACE PREFETCH NORMAL configuration for the local bus space and is constructed from the flags in the Meaning 8 bit local bus width 16 bit local bus width 32 bit local bus width 64 bit local bus width The minimum amount of prefetching on the local bus on some models this equates to no prefetching A nominal amount of prefetching on the local bus ADMXRC2 SPACE PREFETCH MAXIMUM The maximum amount of prefetching on the local bus on some 443 models this may equate to unlimited prefetching ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 Get
39. Host interrupt handler executes and samples ISTAT determining that interrupt source 0 is active FPGA interrupt source 1 becomes active Host interrupt handler takes whatever action is necessary to make interrupt source 0 inactive and finishes a A WO Im FINTI does NOT transition high because interrupt source 1 is still active Unfortunately the host did not see interrupt source 1 become active As far as it is concerned no more interrupts have arrived yet interrupt source 1 is now active and will not be handled as FINTI is still low Note that FINTI is an edge triggered signal The solution is simply for the host s interrupt handler to write to ARM just before exiting 1 FPGA interrupt source 0 becomes active FINTI transitions low 2 Host interrupt handler executes and samples ISTAT determining that interrupt source 0 is active 3 FPGA interrupt source 1 becomes active 180 ADM XRC SDK 4 9 3 User Guide Win32 ITest 4 Host interrupt handler takes whatever action is necessary to make interrupt source 0 inactive 5 Host interrupt handler writes a dummy value to IARM and finishes 6 FINTI transitions high for one cycle then low again since interrupt source 1 is still active At this point the host will be interrupted again and notice that interrupt source 1 is active Interrupt Test register TEST local bus address OxC Bits Mnemonic Type Function 31 0 TEST WO Writing a 1 to a particular bit of t
40. Note that these registers cannot be inadvertantly overwritten by demand mode DMA transfers as the design qualifies FPGA register accesses using LDACK 1 0 Inbound count register ICOUNT local bus address 0x0 Bits Mnemonic Type Function 2 0 MBZ 31 3 N WO Inbound DMA transfer count in 64 bit words The inbound count register ICOUNT specifies how many words will be transferred in the next DMA transfer in channel 0 in order to transfer data into the FPGA s FIFO When ICOUNT N is zero the FPGA will not assert LDREQ 0 The FPGA decrements ICOUNT N whenever a word of data is transferred on DMA channel 0 Outbound count register OCOUNT local bus address 0x4 Bits Mnemonic Type Function 2 0 MBZ 31 3 N WO Outbound DMA transfer count in 64 bit words The outbound count register OCOUNT specifies how many words will be transferred in the next DMA transfer in channel 1 in order to transfer data into the FPGA s FIFO When OCOUNT N is zero the FPGA will not assert LDREQ 1 The FPGA decrements OCOUNT N whenever a word of data is transferred on DMA channel 1 Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table 92 ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 Model XST script file ADM XPL ddma64 xpl v2p scr ADM XP ddma64 xp v2p scr ADP XPI ddma64 xpi v2p scr ADM XRC 4FX ddma64 xrc4fx v4fx scr with 4vfx100 ADM XRC 4FX ddma64 xrc4fx v4fx scr
41. a E length register em lenath 1 T3 Cn ho 2017 cone 1 2033 error 1 155111544 ephase 1 1087 1056 E 1 Implementation of chip driven memory test in user app module The end user can remove modify and add logic as desired in order to create a customized user app module In doing so a few points to remember are e The ports a be ce d q qtag ready tag valid and w are a bundle of vectors where a particular slice through this 126 ADM XRC SDK 4 9 3 User Guide Win32 Memory bundle forms an interface to a memory bank and functions as in the generic memory interface For example q 2 qtag 2 and valid 2 are part of the interface to memory bank 2 Because each slice is independent of the other slices some or all of the memory banks may be operated simultaneously if desired e Because the memory banks are shared with the local bus interface user code must drive the req vector Asserting a particular bit of this vector indicates that the user app module wishes to access the corresponding memory bank For example assering req 3 causes the arbiter for memory bank 3 within the memory banks module to eventually assert ready 3 Once the user app module sees ready 3 asserted it may assert the ce 3 signal in order to access memory bank 3 e The chip driven memory test logic in the user app module as shipped in this SDK runs entirely within the memory clock do
42. and increment it when a word of data is transferred AND the current burst is known use an incrementing address The following circuit illustrates this technique 243 ADM XRC SDK 4 9 3 User Guide Win32 Constant address mode LA 23 2 LAD 31 2 la mirrare d LADS word transferred INCREMENT constant address Loadable Caunter The output of the circuit is the current local bus address ie a mirror of LA with the advantage of having far better timing margins associated with it It does however require that the application software running on the host and the FPGA design agree about how to distinguish between a constant address mode burst and an incrementing address mode burst For a 64 bit wide local bus instead of loading the counter with LA 23 2 or LAD 31 2 simply use LA 23 3 or LAD 31 3 244 ADM XRC SDK 4 9 3 User Guide Win32 Demand mode ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Demand mode DMA transfers The DMA engines on the local bus bridge of an ADM XRC series card are capable of operating in demand mode In demand mode instead of transferring data to or from the FPGA as fast as possible a DMA engine will transfer data on demand of the FPGA For example in a design which contains a FIFO whose data is read out via the local bus the FPGA can request that the DMA engine transfer some data only when the FIFO is not empty To use demand mode DMA the host must sp
43. because the ZBT SSRAM ports do not require training Reserved This field always returns 1 because the ZBT SSRAM port does not require training This field returns 1 if the DDR SDRAM has completed training successfully otherwise 0 Reserved This field returns a 1 in a bit position if the corresponding DDR II SSRAM port has completed training successfully otherwise 0 This field returns a 1 in a bit position if the corresponding DDR SDRAM port has completed training successfully otherwise 0 Reserved This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 Reserved Bits Mnemonic Type ADM XRC ADM XRC P and ADM XRC 4SX 3 0 ZBT RO 31 4 RO MBZ ADM XRC II Lite 1 0 ZBT RO 31 2 RO MBZ ADM XRC Il ADM XRC 4LX and ADM XRC 5TZ 5 0 ZBT RO 31 6 RO MBZ ADM XPL 0 ZBT RO 1 SDRAM RO 31 2 RO MBZ ADM XP 3 0 SSRAM RO 5 4 SDRAM RO 31 6 RO MBZ ADM XRC 4FX ADPE XRC 4FX and ADM XRC 5LX 3 0 SDRAM RO 31 4 RO MBZ ADM XRC 5T1 113 ADM XRC SDK 4 9 3 User Guide Win32 Memory 1 0 SDRAM RO 2 SSRAM RO 31 3 RO MBZ ADM XRC 5T2 and ADM XRC 5T2 ADV 3 0 SDRAM RO 5 4 SSRAM RO 31 6 RO MBZ ADM XRC 5T DA1 1 0 SDRAM RO 3 2 SSRAM RO 31 4 RO MBZ This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 This field returns 1 if the DDR II SSRAM port has comple
44. chunk of DMA transfer On all supported platforms the Alpha Data ADM XRC driver attempts to make this chunk limit at least 64kB The driver splits large DMA transfers into chunks and performs each chunk sequentially which means that there may be a short gap in the data transfer between chunks where the driver is setting up the next chunk 237 ADM XRC SDK 4 9 3 User Guide Win32 What happens during a DMA transfer e Onthe first chunk the driver performs steps 1 to 6 e On second and subsequent chunks except the final chunk the driver performs steps 2 to 6 e On the final chunk the driver performs steps 2 to 7 Steps 1 and 7 not performed if ADMXRC2 DoDMA is used Because of this applications must not rely on DMA transfers being continuous from start to finish In any case there are other latencies besides the inter chunk gap that can affect DMA transfers and these arise from both the hardware and the operating system The inter chunk gap is merely one of the larger latencies even if it were not present the other latencies would remain and thus an application could still fail should it rely upon DMA transfers being continuous 238 ADM XRC SDK 4 9 3 User Guide Win32 Caveats of DMA transfers ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Caveats of DMA transfers This section details a few practices regarding DMA that should be avoided or used with care DMA write to host memory may not u
45. lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt ADP WRC II projnav wrc2 lt device gt ADP DRC II projnav drc2 lt device gt 189 ADM XRC SDK 4 9 3 User Guide Win32 Simple64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Simple64 sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL 2 20 2VP30 only ADM XP a ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga verilog simple64 Synopsis The Simple64 FPGA design demonstrates how to implement host accessible registers in an FPGA design with a 64 bit local data bus It is a 64 bit version of the Simple FPGA design 190 ADM XRC SDK 4 9 3 User Guide Win32 Simple64 The registers described below are located at addreses 0 0 and 0 4 respectively on the local bus This means that they are visible in the lower and upper 32 bit halves of the local bus data LAD 63 0 Because the design uses the local bus byte enables LBE 7 0 to qualify direct slave writes these registers can be written independently of each other even though they are packed into a single 64 bit
46. ready whereas other types of memory port may sometimes deassert ready depending on several factors For example a DDR SDRAM port is capable of buffering a certain number of commands internally but if its command buffer is filled while it executes a refresh cycle it will deassert ready Registered unregistered select sideband signal 6 8 This input selects whether the memory port expects registered DDR SDRAM memory or unregistered DDR SDRAM memory 0 2 unregistered 1 2 registered Row address width select sideband signal 6 8 This input selects the number of row address bits to use Along with the col input it specifies the row column geometry of the DDR SDRAM device as defined here ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 rst in Sr in tag in tstcomp in training signal tstdo training in signal tstdone out training signal tstok training out signal valid out w in x4 in Notes 329 Asynchronous reset for memory port May be tied to logic if not required Synchronous reset for memory port May be tied to logic if not required Tag in When user code asserts ce with w deasserted it must also place a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each
47. unsigned long SerialNum unsigned long Timeout ADMXRC CARD INFO Description The ADMXRC CARD INFO structure is returned by ADMXRC GetCardiInfo and contains information about a card Some applications may require this information in order for example to load the correct bitstream for the FPGA fitted to the card The CardID member of type DEVICE NUM is the ID of the card This value returned is read from an EEPROM on the card Each element of the RAMBankFitted array bitmap indicates the size of particular RAM bank on the card in words A size of zero indicates that the bank is not fitted The memory on an ADM XRC or ADM XRC P card is 36 bit wide flow through ZBT synchronous SRAM The FPGAType member of the enumerated type ADMXRC_FPGATYPE identifies the type of FPGA fitted to the card The FPGA package is BG560 on ADM XRC and ADM XRC P cards The PhysicalMemoryBase member is the address of the FPGA space in the physical address space of the bus on which the card resides For example an ADM XRC card is a PCI Mezzanine Card so this value would represent the PCI address of the beginning of FPGA space The MemoryBase member is the address in the application s address space by which the FPGA may be accessed using pointers as a memory mapped device The BoardRevision member is the revision of the board as a two digit number OxAB where A is the major revision and B is the minor revision The LogicRevision member i
48. 1 taa tag width 1 0 m beO d width 8 1 0 781 0 id d d width 1 0 d d width 1 0 port width 1 0 qd width 1 0 ctagO tag width 1 0 ctad d width 1 0 valid valid ready ready req ce1 al a width 1 0 wl tag tag width 1 bet d width 8 1 0 di d width 1 0 qi d width 1 0 qtaq tag_vidth 1 0 valid readwyl req2 2 300 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 a2 a width 1 0 v2 tag2 tad Width 1 be2 d Width 8 1 0 d2 d width 1 0 qa d width 1 0 ctad2 tag width 1 0 valid2 ready2 arbiter 3 The arbiter 3 module requires a client to assert its request signal reqi when the client wishes to access the memory port In response the arbiter 3 eventually grants access to the memory port by asserting ready Once the client sees ready asserted it is permitted to issue commands to the memory port by asserting cei subject to the timing rules for readyi and cei as described in note 5 below HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif arbiter 4 vhd fpga vhdl
49. 17 0 Note that ra width and pinout are properties of the printed circuit board indicating how many wires are physically present On the other hand the DDR II SDRAM devices actually fitted to the printed circuit board may have less pins connected The purpose of the row col bank and pbank signals is to specify at runtime the properties of the DDR II SDRAM devices actually in use 2 The memory device control bus rc is composed of various fields in this memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates this for the case where pinout is 316 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port mapped to the predefined constant ddr2sdram pinout admxrcb5lx and rd width is 32 which puts rc width at 22 Width of these fields is Width of thee fields is pinaut ck width rd width 8 M M N 21 2 1413 1211 10 S 765 4 3 2 1 D pos DM width pinaut cke wath ODT width width width 1 CASH width 1 RASH width 1 CS width pinout num phys bank The order of the fields within rc is always the same only the field widths may differ from one model to another 3 The rd width parameter is the number of physical DQ wires making up the data bus of the DDR II SDRAM bank This memory port transfers four words of data on the DQ wires for each command entered
50. 2 failed 31 24 EPHASES RO If ERROR S is 1 indicates on which phase the memory test for bank 3 failed USER49 The USER48 registers indicates on which phase the memory test failed for banks 4 to 7 Bits Mnemonic Type Function 7 0 EPHASE4 RO If ERROR 4 is 1 indicates on which phase the memory test for bank 4 failed 15 8 5 RO If ERROR 5 is 1 indicates on which phase the memory test for bank 5 failed 116 ADM XRC SDK 4 9 3 User Guide Win32 Memory 23 16 EPHASE6 RO If ERROR 6 is 1 indicates on which phase the memory test for bank 6 failed 31 24 EPHASE7 RO If ERROR 7 is 1 indicates on which phase the memory test for bank 7 failed USER50 The USERBO register indicates on which phase the memory test failed for banks 8 to 11 Bits Mnemonic Type Function 7 0 EPHASE8 RO If ERROR 8 is 1 indicates on which phase the memory test for bank 8 failed 15 8 EPHASE9 RO If ERROR 9 is 1 indicates on which phase the memory test for bank 9 failed 23 16 EPHASE10 RO If ERROR 10 is 1 indicates on which phase the memory test for bank 10 failed 31 24 EPHASE11 RO If ERROR 11 is 1 indicates on which phase the memory test for bank 11 failed USER51 The USERBO register indicates on which phase the memory test failed for banks 12 to 15 Bits Mnemonic Type Function 7 0 EPHASE12 RO If ERROR 12 is 1 indicates on which phase the memory test for bank 12 failed 15 8 EPHASE13 RO If ERROR 13 is 1 indicates on which p
51. 2001 2009 Alpha Data Running the sample applications ADMXRC SDKA environment variable Some of the sample applications for example memtest require bitstreams from the sample FPGA designs in order to run In order that these applications can locate any required bitstreams the environment variable ADMXRC_SDK4 must be correctly set to point to the base directory of where the SDK has been installed For example set ADMXRC_SDK4 C ADMXRC_SDK4 9 3 Normally this variable is set automatically during installation of the SDK but users may wish to set it manually if for example it is desirable to have more than one version of the SDK installed Command line invocation Binaries for the sample applications are provided prebuilt in the bin directory of the SDK and can be invoked from the command line For example Cs cd C ADMXRC_SDK4 9 3 bin memtest 38 ADM XRC SDK 4 9 3 User Guide Win32 Building the sample applications ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Rebuilding the sample applications The sample applications are supplied in source code form in the apps directory of the SDK They may be compiled using the MSVC command line tools the MSVC IDE or the Borland command line tools Building the sample applications using MSVC Building the sample applications using Borland command line tools 39 ADM XRC SDK 4 9 3 User Guide Win32 MSVC ADM XRC SDK 4 9 3 User Guide Win3
52. 3 User Guide Win32 DLL FPGA Space Usage Count register COUNT local bus address 0 0 Bits 31 0 Mnemonic Type RAN Function Number of elapsed cycles of 2X multiple of LCLK The COUNT register returns the number of elapsed cycles of the 2X multiple of LCLK It can be preset to a particular value by writing to it Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model ADM XRC with Virtex ADM XRC with Virtex E ADM XRC P with Virtex ADM XRC P with Virtex E ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II XST script file dll xrc v scr dll xrc ve scr dll xrcp v scr dll xrcp ve scr dll xrc2l v2 scr dll xrc2 v2 scr dil xpl v2p scr dll xp v2p scr dll wrc2 v2 scr dli drc2 v2 scr Project Navigator files XST project file UCF file dll xrc v prj dll xrc ucf dll xrc ve prj dll xrc ucf dll xrcp v prj dil xrcp ucf dll xrcp ve prj dil xrcp ucf dll xrc2l v2 prj dll xrc2l ucf dll xrc2 v2 prj dll xrc2 ucf dll xpl v2p prj dll xpl ucf dll xp v2p prj dll xp ucf dll wrc2 v2 prj dll wrc2 ucf dll drc2 v2 prj dll drc2 ucf Project Navigator projects can be found in the projnav directory as follows Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II 176 Project Navigator project file projnav xrc lt device gt projnav xrcp lt device gt projnav
53. 4 9 3 User Guide Win32 Memtest index base 10 integer Index of card to open lclk real number Local bus clock frequency to use in MHz default 33 0 repeat base 10 integer Number of times to perform tests default 1 speed Do not test SSRAM access speed speed Test SSRAM access speed default usedma Use programmed I O for tests usedma Use DMA for tests default 64 Operate local bus in 32 bit mode default 64 Operate local bus in 64 bit mode Description The Memtest sample application supports only models that use ZBT SSRAM memory It tests the ZBT SSRAM memory in several phases 1 0x55 pattern written to entire memory for detecting data bits stuck at 1 or 0 or shorted to other signals OxAA pattern written to entire memory for detecting data bits stuck at 1 or 0 or shorted to other signals Own address pattern written to entire memory for detecting address bits stuck at 1 or 0 or shorted to other signals a Inm Bit reversed own address pattern written to entire memory for detecting address bits stuck at 1 or 0 or shorted to other signals Writes individual bytes in order to detect incorrect handling of byte enables or faulty byte enable signals 6 Measures throughput for data transfer in the two possible directions CPU memory to ZBT SSRAM and ZBT SSRAM to CPU memory Depending on whether the usedma option or the usedma option is specified on the command line Memtest uses either
54. 97 ADMXRC2_FPGA_4VLX40 98 ADMXRC2 FPGA A4VLX60 99 ADMXRC2_FPGA_4VLX100 ADMXRC2_FPGA_4VLX160 101 ADMXRC2_FPGA_4VLX200 102 ADMXRC2_FPGA_4VLX80 103 ADMXRC2_FPGA_4VSX25 104 ADMXRC2_FPGA_4VSX35 105 ADMXRC2_FPGA_4VSX55 106 493 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 FPGA TYPE DMXRC2 FPGA RESVD107 107 DMXRC2 FPGA RESVD108 108 DMXRC2_FPGA_RESVD109 109 DMXRC2_FPGA_RESVD110 110 DMXRC2_FPGA_RESVD111 11 DMXRC2_FPGA_4VFX12 112 DMXRC2_FPGA_4VFX20 113 DMXRC2_FPGA_4VFX40 114 DMXRC2 FPGA AVFX60 X115 DMXRC2 FPGA AVFX100 116 DMXRC2 FPGA AVFX140 117 DMXRC2 FPGA RESVD118 118 DMXRC2 FPGA RESVD119 119 DMXRC2 FPGA RESVD120 120 DMXRC2 FPGA RESVD121 121 DMXRC2 FPGA RESVD122 122 DMXRC2 FPGA RESVD123 123 DMXRC2 FPGA RESVD124 124 DMXRC2 FPGA RESVD125 125 DMXRC2 FPGA RESVD126 126 DMXRC2 FPGA RESVD127 127 DMXRC2 FPGA 5VLX30 128 DMXRC2 FPGA 5VLX50 129 DMXRC2 FPGA 5VLX85 1 PS Q FPGA 5VLX110 1 _FPGA_5VLX220 1 Q N og g gt ggg gt gt gt gt gt gt gt gt 2 og gt ggg gt gt gt gt gt gt gt gt X X X X X X X X X X X X X X X X X X X X X X X X X MX X X X X X X X X X X X X X X X X X X X X X X X
55. A value of type time that represents the desired local bus clock to output delay for point to point signals such as LHOLD This parameter has a suitable default value so it need not be specified The first group of ports must be mapped to signals driven or used by the stimulus process associated with the local bus agent Port bus in bus out Map to A signal of type locbus in t used by the stimulus process A signal of type locbus out t driven by the stimulus process The second group of ports must be mapped to signals driven or input by the local bus arbiter Port 409 Map to ADM XRC SDK 4 9 3 User Guide Win32 locbus agent mux32 Ihold Iholda A signal corresponding to LHOLD that is input by the bus arbiter There should be one such signal per local bus agent A signal corresponding to LHOLDA that is driven by the bus arbiter There should be one such signal per local bus agent The remaining ports should be mapped to local bus signals as follows Port lads lad Ibe Iclk Iblast_ Ibterm_ Ireset Iwrite 410 Map to The signal corresponding to LADS in the testbench The signal corresponding to LAD 31 0 in the testbench The signal corresponding to LBEZ 3 0 in the testbench The signal corresponding to LCLK in the testbench The signal corresponding to LBLAST in the testbench The signal corresponding to LBTERM in the testbench The signal corresponding to LREAD
56. API library is implemented a set of dynamic link libraries DLLs that are part of the installable driver package 486 ADM XRC SDK 4 9 3 User Guide Win32 Types ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 interface types This section describes the atomic datatypes of the ADMXRC2 interface Name Purpose ADMXRC2 CARDID A value that identifies a particular card in a system ADMXRC2 DMADESC A DMA descriptor identifying a locked application buffer ADMXRC2 DMADIR A value that indicates in which direction a DMA transfer should transfer data ADMXRC2 ERROR HANDLER A pointer to an application defined error handler function ADMXRC2 FPGA TYPE A value representing the type of an FPGA fitted to a card ADMXRC2 HANDLE A handle to an ADM XRC series card ADMXRC2 IMAGE A FPGA bitstream image containing SelectMap data ADMXRC2 IOWIDTH A value that specifies the byte width of IO and DMA transfers ADMXRC2 STATUS A value that indicates the success or failure of a call to an API function ADMXRC2 SYNCMODE A value specifying what kind of memory coherency synchronisation to perform 487 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BOARD TYPE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 BOARD TYPE Declaration typedef enum ADMXRC2 BOARD TYPE ADMXRC2 BOARD ADMXRC 0 ADM XRC i ADMXRC2 BOARD ADMXRC
57. APl import libraries ADM XRC SDK 4 9 3 User Guide Win32 Hardware supported ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Hardware supported in this version of the SDK This version of the SDK supports the following models in Alpha Data s reconfigurable computing range e ADM XRC e ADM XRC P e ADM XRCHI Lite e ADM XRC II e ADM XPL e ADM XP e ADP WRC II e ADP DRC II e ADP XPI e ADM XRC 4LX e ADM XRC 4SX e ADM XRC 4FX and ADM XMC 4FX e ADPE XRC 4FX e ADM XRC 5LX e ADM XRC 5T1 e ADM XRC 5T2 e ADM XRC 5T2 ADV e ADM XRC 5TZ e ADM XRC 5T DA1 This version of the SDK supports the above cards fitted with any of the following FPGAs e Virtex family o XCV400BG560 o XCV600BG560 o XCV800BG560 o XCV1000BG560 e Virtex E family o XCV1000EBG560 o XCV1600EBG560 23 ADM XRC SDK 4 9 3 User Guide Win32 Hardware supported o XCV2000EBG560 e Virtex EM family o XCV405EBG560 o XCV812bEBG560 e Virtex Il family o XC2V1000FG456 o XCV2V3000FF1152 o XCV2V4000FF1152 o XCV2V6000FF1152 o XCV2V8000FF1152 o XCV2V6000FF1517 o XCV2V8000FF1517 e Virtex Il Pro family o XC2VP7FF896 o XC2VP20FF896 o XC2VP30FF896 o XC2VP70FF1704 o XC2VP100FF1704 e Virtex 4 family o XCAVLX6OFF1 148 o XC4VLX80FF1148 o XC4VLX100FF1148 o XCAVLX160FF1148 o XC4VSX55FF1148 o XCAVFX100FF1517 o XC4VFX140FF1517 e Virtex 5 family o XC5VLX110FF1153 o XC5VFXTOTFF1136 o XC5VFX10
58. DMA cycle 1 0 Requesting a demand mode DMA cycle but after the demand mode DMA cycle begins pause the DMA transfer as early as possible by deasserting Idreq o l 1 1 Requesting a demand mode DMA cycle and keep Idreq_o_ asserted so as not to pause the DMA transfer The purpose of request and burst is to enable a data source or sink within the target FPGA to exercise control over the burst length This is necessary when for example data is being sourced onto the local bus from a FIFO and the FIFO is almost empty FIFO underflow must be prevented by limiting the burst length of the next demand mode DMA cycle For a typical application where a FIFO sources data that is being read by demand mode DMA cycles the request and burst signals might work as follows e request is asserted when the FIFO contains data e burst is asserted when the FIFO level is above a certain threshold Another way that the target FPGA can control burst length is via the stop signal of the plxdssm component That signal can be used to terminate a demand mode DMA local bus cycle although it doesn t necessarily pause a demand mode transfer and together with request and burst offers the most flexibility in controlling a demand mode DMA transfer For each DMA channel that is to be used in demand mode there must be one instance of plxddsm 2 Each instance of plxddsm2 is associated with one bit of the LDACK and LDREQ busses Regardless of how many instances of plxdd
59. Data Simple64 sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL 2vP20 2VP30 only ADM XP a ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location ADMXRC_SDK4 fpga vhdl simple64 Synopsis 156 ADM XRC SDK 4 9 3 User Guide Win32 Simple64 The Simple64 FPGA design demonstrates how to implement host accessible registers in an FPGA design with a 64 bit local data bus It is a 64 bit version of the Simple FPGA design The registers described below are located at addresses 0 0 and 0x4 respectively on the local bus This means that they are visible in the lower and upper 32 bit halves of the local bus data LAD 63 0 Because the design uses the local bus byte enables LBE 7 0 to qualify direct slave writes these registers can be written independently of each other even though they are packed into a single 64 bit word From the host s point of view the registers in the FPGA are the same as in the Simple FPGA design They can be accessed via the ADMXRC2 Re
60. Description This function undoes a call to ADMXRC_SetupDMA When a DMA descriptor is no longer required it should be freed using ADMXRC UnsetupDMA Provided that no other DMA descriptors exist for the buffer the application buffer associated with the DMA descriptor is returned to an unlocked swappable state The DMADesc parameter specifies the DMA descriptor to free 545 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC Write ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC Write Prototype ADMXRC STATUS ADMXRC Write ADMXRC HANDLE Card Width unsigned long unsigned long DWORD void unsigned long Flags Local Data ength Arguments Argument Type Card In Width In Flags In Local In Buffer In Length In Return value Value ADMXRC SUCCESS ADMXRC INVALID HANDLE Purpose Handle of card on which the write is to take place Width of operation Miscellaneous flags Local bus address at which to begin writing Buffer containing data to write Number of bytes to write ADMXRC INVALID PARAMETER Description Meaning The data was written successfully Card is not a valid handle to a card An invalid parameter was passed The ADMXRC Write function writes a number of bytes from an application buffer to the local bus using direct slave cycles or to the PLX registers The local bus space encompasses FPGA space the FPGA flash memory and the control registe
61. Generic Map to multiplexed e irue if the local bus has multiplexed address data e false if the local bus has nonmultiplexed address data wide e true if the local data bus is to 64 bits wide e false if the local data bus is 32 bits wide The ports should be mapped to local bus signals as follows Port Map to Iclk The signal corresponding to LCLK in the testbench Ireset The signal corresponding to LRESET in the testbench lads The signal corresponding to LADS in the testbench l64 e The signal corresponding to L64 if the wide generic is true e Anything if the wide generic is false The port will be ignored 404 ADM XRC SDK 4 9 3 User Guide Win32 lbpcheck la lad lo lad hi Ibe Ibe hi Iwrite Iblast lready_ lbterm 405 e The signal corresponding to LA 31 2 in the testbench if the multiplexed generic is false e The signal corresponding to LAD 31 2 in the testbench if the multiplexed generic is true e The signal corresponding to LD 31 0 in the testbench if the multiplexed generic is false e The signal corresponding to LAD 31 0 in the testbench if the multiplexed generic is true e Anything typically a vector of constant zeroes if the wide generic is false The port will be ignored e The signal corresponding to LD 63 32 in the testbench if the wide generic is true and the multiplexed generic is false note currently no model in the ADM XRC ran
62. IDE global options This section assumes that that the ADM XRC SDK has been installed in the default location namely NADMXRC SDK4 9 3 The search paths that are applied when building any application in MSVC can be changed If you decide to use this method of configuring MSVC bear in mind that the ADM XRC header files and import libraries will become visible for inclusion to all applications that you subsequently build using the IDE 1 Select Tools Options from the menu within the MSVC IDE 2 In the Options dialogue box select the C C tab and then select Include files from the Show directories for list Add this path C NADMXRC SDK4 9 3Ninclude 3 Select Library files from the Show directories for list Add this path C ADMXRC_SDK4 9 3 lib msvc 4 Click OK to apply the changes The new include and library search paths will apply to any project subsequently built with the MSVC IDE Note that you will need to specify the API library to the linker on a per project basis To do this follow these steps 1 Select Project Settings from the menu Ensure that the correct project is highlighted on the left hand side of the Project Settings dialog box 2 Select the configuration s you want to change Win32 Debug Win32 Release or All Configurations from the Settings for list 3 Select the Link tab and add the library to the list of lib files in the Object Library modules field 4 Add either admxrc lib Releas
63. LADS signal by simple address decoding which may also include FHOLDA Data ready The user application should assert this signal when it is ready to transfer data during a local bus cycle As a result of asserting ready the plxdssm module asserts the Iready o 1 output in the next clock cycle The ready input may be pulsed for as little as one cycle cycle Ilready o 1 however remains asserted until the end of the current local bus cycle Asserting ready also permits the plxdssm module to assert o according to the following rules given in the description for stop Asynchronous reset This port may be driven by an asynchronous reset for the local bus interface or tied to logic 0 if not required Synchronous reset This port may be driven by a synchronous reset for the local bus interface or tied to logic 0 if not required ADM XRC SDK 4 9 3 User Guide Win32 plxdssm Stop in transfer out write out Usage Terminate local bus cycle The user application should assert this signal when it wishes to terminate the current local bus cycle If stop is asserted the plxdssm module may or may not assert lbterm o l in the next clock cycle according to the following rules 1 If the user application asserts or pulses stop on or before the cycle in which ready is asserted Ibterm o 1 will be asserted coincident with o 1 In this case it is ready that determines the precise moment at which Ibterm o l is a
64. LBLAST and LREADY are both asserted LADS j t Key Signal is owned LA by master m Signalis owned LE BET y BE2 Y BET Y BES bya dave t Suggested L WRITE WA ANN tumarcund OM LREADVE CEN c LETERM f 003 J D4 55 f 06 burst read normal termination Burst write normal termination The following diagram illustrates a burst write terminated normally LBLAST and LREADY are both asserted 228 ADM XRC SDK 4 9 3 User Guide Win32 Direct slave transfers ek FA FA FA FA FAFAFATAFAFATATATA LADS 1 PO LA LBE LARITE LBLAST uM nn LRE AD Y LETERM 2 f LD C per yw p burst wite nomal termination Burst read terminated by LBTERM The following diagram illustrates a burst read terminated by LBTERM _ LA LBE LWWRITE SS LBLAST Wy LRE AD Y P XR y 0 E pega orones nc burst read terminated by LBTERMZ LBTERM Note 1 LBTERM overrides LREADY and LBLAST Burst write terminated by LBTERM The following diagram illustrates a burst write terminated by LBTERM 229 Key Signal is owned by master m Signalis owned by a dave t1 Suggested tumaround Key
65. P 1 ADM XRC P ADMXRC2 BOARD ADMXRC2 LITE 2 ADM XRC II Lite ADMXRC2 BOARD ADMXRC2 3 ADM XRC II ADMXRC2 BOARD ADMXP 4 ADM XP ADMXRC2 BOARD ADMXPL D ADM XPL ADMXRC2 BOARD ADPWRC2 6 ADP WRC II ADMXRC2 BOARD ADPDRC2 7 ADP DRC II ADMXRC2 BOARD ADPXPI 8 ADP XPI TE ADMXRC2 BOARD ADMXRCALS 9 ADM XRCALS ADMXRC2 BOARD ADMXRCALX 10 ADM XRCALX ADMXRC2 BOARD ADMXRCA4SX 11 ADM XRCASX ADMXRC2 BOARD ADPEXRCAFX 12 ADPE XRC 4FX m ADMXRC2 BOARD ADMXRCAFX 13 ADM XRC 4FX ADMXRC2 BOARD ADMXRC5LX 14 ADM XRC 5LX ADMXRC2 BOARD ADMXRCS5T1 15 ADM XRC 5T1 ADMXRC2 BOARD ADMXRC5T2 16 ADM XRC 5T2 T ADMXRC2 BOARD ADCPXRCALX 17 ADCP XRC 4LX ADMXRC2 BOARD ADMAMC5A2 18 ADM AMC 5A2 ADMXRC2 BOARD ADMXRCS5TZ 19 ADM XRC 5TZ ADMXRC2 BOARD ADCBBP 20 ADC BBP ADMXRC2 BOARD ADMXRC5T2ADV 21 ADM XRC 5T2 ADV ADMXRC2 BOARD ADMXRC5TDA1 22 ADM XRC 5T DA1 ADMXRC2 BOARD UNKNOWN 23 ADMXRC2 BOARD TYPE Description This type enumerates the models types of boards supported by the API and certain API functions require knowledge of which model is being used in order to operate The type of a board can be obtained from the ADMXRC2 CARD INFO structure returned by ADMXRC2 GetCardlnfo 488 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 CARDID ADM XRC SDK 4 9 3 User G
66. PLX registers The local bus space encompasses FPGA space the FPGA flash memory and the control registers The Width parameter specifies the width of the operation and must be one of the following values Value ADMXRC IOBYTE ADMXRC IOWORD ADMXRC IOLONG Meaning BYTE 8 bit width WORD 16 bit width DWORD 32 bit width The Flags parameter modifies the semantics of the operation Normally the read is performed in local bus space with an 532 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC Read incrementing address but this behavior can be modified by any combination of the following Flag Meaning ADMXRC IOFIXED The local bus address is not incremented during the transfer ADMXRC_IOPLX The read is performed from the card s PCI interface registers rather than the local bus If the ADMXRC IOPLX flag is not specified the Local parameter specifies the starting local bus address from which the data will be read Otherwise the Local parameter specifies the starting PLX register offset from which the data will be read If the ADMXRC_IOFIXED flag was specified this address will not increment as the data is read Otherwise the address is incremented as the data is read The Buffer parameter specifies the buffer to receive the data read The Length parameter specifies how many bytes are to be read and should be a multiple of the width specified by the Width parameter For example if Width is ADMXRC_IOWORD the Length parameter should b
67. RO MBZ ADM XRC 4LX and ADM XRC 4SX Bits Mnemonic Type 8 MEMCLK RO 9 ZBT RO 15 10 RO MBZ ADM XRC 4FX and ADPE XRC 4FX Bits Mnemonic Type 8 MEMCLK RO 9 IDELAY RO 15 10 RO MBZ Function When 1 indicates that the DLL that deskews the clock for all memory banks is locked Reserved Function When 1 indicates that the DCM that doubles the frequency of MCLK is locked When 1 indicates that the DCM that deskews the SSRAM clocks for physical banks 0 and 1 is locked When 1 indicates that the DCM that deskews the SSRAM clocks for physical banks 2 and 3 is locked Reserved Function When 1 indicates that the DCM that doubles the frequency of MCLK is locked When 1 indicates that the DCM that deskews the SSRAM clocks for physical banks 0 1 and 2 is locked When 1 indicates that the DCM that deskews the SSRAM clocks for physical banks 3 4 and 5 is locked Reserved Function When 1 indicates that the DCM that generates the clock for the memory clock domain is locked When 1 indicates that the DCM that deskews the ZBT SSRAM clock is locked Reserved Function When 1 indicates that the DCM that generates the clock for the memory clock domain is locked Reserved Function When 1 indicates that the DCM that generates the clock for the memory clock domain is locked When 1 indicates that the DCM that deskews the clock for the ZBT SSRAMs is locked Reserved Function When 1
68. Return value Value Meaning ADMXRC SUCCESS The event was successfully registered ADMXRC INVALID HANDLE The Card handle or Event handle was not valid Description This function registers a Win32 event for capturing interrupts from the FPGA Event must be a valid Win32 event handle The type of the event can be manual or auto reset depending on the needs of the application After an event is registered using ADMXRC_RegisterlnterruptEvent it is signalled by the driver whenever an FPGA interrupt occurs Applications can thus be notified of interrupts from the FPGA by waiting on a registered event Any number of events can be registered this way but typically only one is ever required by an application To unregister an event specify the same event in a call to ADMXRC UnregisterlnterruptEvent 535 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ReverseBytes ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC ReverseBytes Prototype void ADMXRC ReverseBytes Arguments Argument Image Offset Length Return value ADMXRC IMAG LONG LONG U U Type In out In In E Image Offset Length This function has no return value Description Purpose The bitstream image containing the SelectMap data to reverse The position within Image at which the SelectMap data is located The length of the SelectMap data within Image This function reverses the bit order of the bytes that com
69. The Info parameter must point to the ADMXRC2 CARD INFO stucture which is to receive the information 441 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_GetSpaceInfo ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 GetSpacelnfo Prototype ADMXRC2 STATUS ADMXRC2 GetSpaceInfo ADMXRC2 HANDLE Card unsigned int Index ADMXRC2 SPACE INFO Info Arguments Argument Type Purpose Card In Handle of card about which to return space information Index In Specifies the local bus space about which to return information Info Out Structure to be filled in with information about the specified local bus Space Return value Value Meaning ADMXRC2 SUCCESS The information was obtained successfully ADMXRC2 INVALID HANDLE Card is not a valid handle to a card ADMXRC2 INVALID PARAMETER Index was not valid Description This function returns information about a region of local bus space in an ADMXRC2 SPACE INFO stucture The Index parameter specifies the region of local bus space about which to return information An Index of 0 always refers to the FPGA space the region of local bus space for the FPGA The Info parameter must point to the ADMXRC2 SPACE INFO stucture which is to receive the information 442 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 GetSpaceConfig ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 GetSpaceContig Prototype ADMXRC2 STATUS
70. XRC P with Virtex E ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with FXT ADM XRC 5T1 with LXT ADM XRC 5T1 with SXT ADM XRC 5T2 or ADM XRC 5T2 ADV with 5VFX100T ADM XRC 5T2 or ADM XRC 5T2 ADV with 5VFX130T ADM XRC 5T2 or ADM XRC 5T2 ADV with 5VFX200T ADM XRC 5T2 or ADM XRC 5T2 ADV with 5VLX110T 5VLX155T or 5VLX220T ADM XRC 5T2 or ADM XRC 5T2 ADV with 5VLX330T ADM XRC 5T2 or ADM XRC 5T2 ADV with 5VSX240T 83 clock xrcp v scr clock xrcp ve scr clock xrc2l v2 scr clock xrc2 v2 scr clock xpl v2p scr clock xp v2p scr clock wrc2 v2 scr clock drc2 v2 scr clock xpi v2p scr clock xrc4lIx v4Ix scr clock xrc4sx v4sx scr clock xrc4fx v4fx scr clock xrc4fx v4fx scr clock xrce4fx v4fx scr clock xrce4fx v4fx scr clock xrcblx v5blx scr clock xrcbt1 vbfxt scr clock xrcbt1 v5lxt scr clock xrcbt1 v5sxt scr clock xrc5t2 v5fxt ser clock xrc5bt2 vbfxt scr clock xrcbt2 vbfxt scr clock xrcbt2 vb5lxt scr clock xrcbt2 vb5lxt scr clock xrc5t2 v5sxt scr clock xrcp v prj clock xrcp ve prj clock xrc2l v2 prj clock xrc2 v2 prj clock xpl v2p prj clock xp v2p prj clock wrc2 v2 prj clock drc2 v2 prj clock xpi v2p prj clock xrc4lx v4lx prj clock xrc4sx v4sx prj clock xrc4fx v4fx prj cl
71. XRC SDK 4 9 3 User Guide Win32 ADMXRC2 CARD INFO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 CARD INFO Declaration typedef struct ADMXRC2 CARD INFO ADMXRC2 CARDID CardID DWORD SerialNum ADMXRC2 BOARD TYPE BoardType ADMXRC2 FPGA TYPE FPGAType unsigned long NumClock unsigned long NumDMAChan unsigned long NumRAMBank unsigned long NumSpace DWORD RAMBanksFitted BYTE BoardRevision BYTE LogicRevision ADMXRC2 CARD INFO Description The ADMXRC2 CARD INFO structure is returned by ADMXRC2 and contains information about a card Some applications may require this information in order for example to load the correct bitstream for the FPGA fitted to the card The CardID member of type ADMXRC2 CARDID is the ID of the card This value returned is read from an EEPROM on the card The SerialNum member is the serial number of the card The BoardType member identifies the model ADM XRC ADM XRC P ADM XRC II Lite etc and is of the enumerated type ADMXRC2 BOARD TYPE BoardType also implicitly defines the package of the FPGA fitted to the card Model FPGA package ADM XRC BG560 ADM XRC P BG560 ADM XRC II Lite FG456 ADM XRC II FF1152 ADM XPL FF896 ADP WRC II FF1517 ADP DRC II FF1152 ADP XPI FF1704 ADM XRC 4LX FF1148 ADM XRC 4SX FF1148 ADM XRC 4FX FF1517 482 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 CARD INFO A
72. XST project file UCF file ADM XRC P with reario xrcp v scr reario xrcp v prj reario xrcp ucf Virtex ADM XRC P with reario xrcp ve scr reario xrcp ve prj reario xrcp ucf Virtex E ADM XRC II reario xrc2 v2 scr reario xrc2 v2 prj reario xrc2 ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC I Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt 187 ADM XRC SDK 4 9 3 User Guide Win32 Simple ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Simple sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog simple Synopsis The Simple FPGA design demonstrates how to implement host accessible registers in an FPGA design The registers can be accessed via the ADMXRC2_Read and ADMXRC2_Write API calls or via a memory mapped region The latter method is demonstrated by the Simple sample application 188 ADM XRC SDK 4 9 3 User Guide Win32 Simple FPGA Space Usage Nibbl
73. a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but refer to the section below for a discussion of how to maximize performance Clock for user interface 7 All other signals except rst are synchronous to High speed clock phase 0 7 This clock must be in phase with 1 0 but double the frequency High speed clock phase 90 7 This clock must the same frequency as clk2x0 but must its phase must be 90 degrees ahead of cIk2x0 Auxilliary clock phase 45 7 This clock must the same frequency as clkO but must its phase must be 45 degrees ahead of Column address width select sideband signal 6 8 This input selects the number of column address bits to use Along with the row input it specifies the row column geometry of the DDR I SDRAM device as defined here ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port d pbank qtag ready row rst Sr tag trained 319 in out out out out Data to memory User code must place valid data on d whenever a write command is entered ce and w both
74. a zero means that the corresponding byte will not be written to memory 312 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 ce qtag ready tag valid 313 out out in out out Memory port command entry The arbiter_4 module asserts this signal when it must access the memory port on behalf of a client When arbiter_4 asserts ce it also drives valid values on a and w Depending on whether or not w is asserted along with ce arbiter_4 also drives either tag or be and d with valid values Memory port write data The arbiter_4 module drives this signal with a valid set of byte enables when it asserts ce and w together in order to perform a write to the memory port on behalf of a client Memory port read data This signal carries the data read from the memory port as a result of arbiter 4 reading the memory port on behalf of a client It is qualified by the valid signal Memory port returned tag This signal carries the tag that accompanies data read from the memory port as a result of arbiter 4 reading the memory port on behalf of a client It is qualified by the valid signal Memory port ready When ready is asserted the memory port is ready to accept commands The arbiter 4 module uses this signal in generating the readyO ready1 ready2 and ready3 signals for the clients Memory port tag The arbiter 4 module drives this signal with a valid tag when it asserts ce with w deasserted in order to perf
75. address bits in a logical SSRAM bank 0 gt 17 128k words 1 2 18 256k words 2 gt 19 512k words 3 gt 20 1M words ADM XRC SDK 4 9 3 User Guide Win32 ZBT Information register INFO local bus address 0x10 Bits Mnemonic Type Function 23 0 BANKSIZE RO Returns size in words of each logical SSRAM bank 31 24 NUMBANK RO Number of logical SSRAM banks in the design Status register STATUS local bus address 0x14 Bits Mnemonic Type Function 0 LCLK LOCKED RO Returns 1 if the local bus clock LCLK DCM DLL is currently locked RAMCLK LOCKED RO If nis the number of SSRAM clock signals in the design this register returns 1 in a particular bit if the DCM DLL for that clock signal is currently locked Bit 1 corresponds to SSRAM clock 0 31 1 RAX Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with Zbt xrc v scr Zbt xrc v prj zbt xrc v ucf Virtex ADM XRC with zbt xrc ve scr Zbt xrc ve prj zbt xrc ve ucf Virtex E EM ADM XRC P with zbt xrcp v scr zbt xrcp v prj zbt xrcp v ucf Virtex ADM XRC P with zbt xrcp ve scr zbt xrcp ve prj zbt xrcp ve ucf Virtex E EM ADM XRC IlI Lite zbt xrc2l v2 scr Zbt xrc2l v2 prj zbt xrc2l ucf ADM XRC II Zbt xrc2 v2 scr Zbt xrc2 v2 prj zbt xrc2 ucf ADM XPL zbt xpl v2p scr zbt xpl v2p prj zbt xpl ucf Project Navigator fil
76. an instance of the training module ddr2sram training v2 and an instance of ddr2sram port v2 form a private communication channel The information carried by this channel is generally not of interest to the user but brief descriptions of each signal in the channel are provided for information only Training of ddr2sram port v2 from deassertion of reset to completion of training tstcomp asserted takes no more than 1 millisecond at a clkO frequency of 133MHz When it is known that burst length 2 devices are being used driving the burst len input with O results in fewer cycles being wasted when random reads and writes are performed in quick succession However driving the burst len with 1 is safe in that it enables SSRAM devices of burst length 2 or 4 to be used interchangeably Alpha Data recommends driving burst len with 1 unless the application demands the maximum possible bandwidth from the SSRAM devices The ddr2sram training v2 component works by varying the phase of the capture clocks clkcO and clkc180 in order to find a window in which data from the SSRAM device s DQ pins can be reliably captured Hence these clocks are the same frequency as clkO etc but the required phase relationship is discovered during the training sequence The signals of this interface to and from the memory device s are as follows Signal ra 343 Type Function in Memory device address bus This bus carries address information to from the memory por
77. and width for each supported card Card Number of locations Bit width of locations ADM XRC 64 16 ADM XRC P 64 16 ADM XRC II Lite 64 16 ADM XRC II 256 16 ADM XPL 256 32 475 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 WriteConfig ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 476 256 256 256 256 256 256 256 256 256 256 256 256 256 256 32 16 16 32 16 16 32 32 32 32 32 32 32 32 ADM XRC SDK 4 9 3 User Guide Win32 Structures ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 interface structures This section describes the composite datatypes of the ADMXRC2 interface Name Purpose ADMXRC2 BANK INFO Information about a bank of memory ADMXRC2 BUFFERMAP Contains a physical page map of an application buffer ADMXRC2 CARD INFO Information about a card ADMXRC2 SPACE INFO Information about local bus region ADMXRC2 VERSION INFO Information about the API and driver version 477 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BANK INFO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 BANK INFO Declaration typedef struct ADMXRC2 BANK INFO unsigned long Type unsigned long Width unsigned long Size BOOLEAN Fitted ADMXRC2 BANK INFO Description The ADMXRC2 BANK INFO struct
78. as it is possible to modify the configuration in such a way that recovery is not possible using EPTest The output from this form of the command is Selected card ID is 109 0x6d Warning this will write the value 1376277 0x150015 to EEPROM location Are you sure you want to continue y n y The application will ask you to confirm that you really want to modify the configuration memory and entering y will cause EPTest to proceed and update the configuration memory ADM XRC SDK 4 9 3 User Guide Win32 Flash ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Flash utility WARNING Care should be exercised when using the Flash utility Storing an invalid bitstream in the Flash memory may cause a card to be damaged when the FPGA loads from Flash on power up Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview Flash is a utility that allows programming verification and erasing of the Flash memory on a reconfigurable computing card The utility can be used to blank check the Flash erase the Flash program a bitstream into the Flash or verify that a particular bitstream has been programmed into the Flash Syntax flash options chkblank flash options erase f
79. asserted Physical bank select sideband signal 6 8 This input selects the number of physical banks chip selects in use for the DDR II SDRAM devices 00 gt 1 physical bank 1 CS 01 gt 2 physical bank 2 CS 10 gt 4 physical bank 4 CS 11 gt 8 physical bank 8 5 Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a read command gtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Certain types of memory port may unconditionally assert ready whereas other types of memory port may sometimes deassert ready depending on several factors For example a DDR II SDRAM port is capable of buffering a certain number of commands internally but if its command buffer is filled while it executes a refresh cycle it will deassert ready Row address width select sideband signal 6 8 This input selects the number of row address bits to use Along with the col input it specifies the row column geometry of the DDR II SDRAM device as defined here Asynchronous reset for memory port May be tied to logic if not required Synchronous reset for memory port May be tied to logic if not required Tag in When user code asserts ce with w deasserted it must als
80. bit local data bus 395 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write e for a 64 bit local data bus The multiburst parameter specifies the action taken if the target of the transfer terminates the burst before the desired number of bytes has been transferred e When false the procedure will return if the burst is terminated and nxfered will reflect the actual number of bytes transferred e When true the procedure will perform transfers on the local bus until the desired number of bytes has been transferred In this case nxfered will be set to the length of data The address parameter specifies the starting local bus byte address of the transfer which will be incremented during the transfer It need not be aligned to the word size of the local data bus The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address The be parameter specifies the byte enables to be used for the transfer They are active high and so a 1 i
81. by the local bus interface for one clock cycle at the beginning of a burst when the local bus interface wants to access a memory bank whether for a read or for a write e mem a qualified by mem ce and carries the starting address in terms of 32 bit words in memory that the local bus interface wishes to access e mem cw qualified by mem ce and is asserted by the local bus interface for a write access 121 ADM XRC SDK 4 9 3 User Guide Win32 Memory e mem term pulsed by the local bus interface for one clock cycle to terminate the burst e mem wr when asserted by the local bus interface indicates that mem d and mem be carry 32 bit data and byte enables to be written to memory May be asserted for multiple consecutive clock cycles during a burst e mem d carries data from the local bus interface to be written to memory e mem be byte enables that accompany mem d e mem wnpf asserted by the memory banks module when the async port instance selected by sel bank 1h cannot accept more data to be written to memory The local bus interface uses this signal to hold off the local bus LREADY signal during a burst so that the FIFOs within the async port instances cannot overflow Explanation of memory banks module outbound datapath port pre D mem re port pre 3 port prpe D mem me port prpe 3 it 0 port MI port pa D port muxed mem q x 128 38 _ 3 by i 3 EAE m
82. can be found in the projnav directory as follows Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Modelsim scripts Example Modelsim compatible script files for simulating this design are provided Project Navigator project file projnav re device projnav rcp device projnav xrc2l lt device gt projnav xrc2 lt device gt projnav xpl lt device gt projnav xp lt device gt projnav wrc2 lt device gt projnav drc2 lt device gt projnav xpi lt device gt projnav xrc4lx lt device gt projnav xrc4sx lt device gt projnav xrc4fx lt device gt projnav xrce4fx lt device gt projnavrcbbo device projnav xrc5t1 lt device gt projnav xrc5t2 lt device gt projnav xrc5tz lt device gt projnav xrc5tda1 lt device gt appropriate command line for a particular model Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX 89 Shell command vsim do do ddma do vsim do do ddma do vsim do do ddma xrc2l do vsim do do ddma xrc2 do vsim do do ddma xpl do vsim do do ddma xpl do vsim do do ddma wrc2 do vsim do do ddma wrc2 do vsim do do ddma xpi do vsim do do ddma xrc4lx do vsim do do d
83. clock xrc5tz v5Ixt prj clock xrcbtz v5lxt prj clock xrcbtz 5vsx240t ucf clock xrc5tz v5sxt prj ADM XRC 5T clock xrcbtda1 vbfxt scr clock xrc5tda1 v5fxt prj clock xrc5tda1 5vfxt ucf DA1 with FXT ADM XRC 5T clock xrcbtda1 v5lxt scr clock xrcbtda1 v5lxt prj clock xrc5tda1 ucf DA1 with LXT ADM XRC 5T clock xrc5tda1 v5sxt scr clock xrc5tda1 v5sxt prj clock xrc5tda1 ucf DA1 with SXT Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav xrc lt device gt ADM XRC P projnav xrcp lt device gt ADM XRC I Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt ADP WRC II projnav wrc2 lt device gt ADP DRC II projnavdrc2 device ADP XPI projnav xpi lt device gt ADM XRC 4LX projnav xrc4lx lt device gt ADM XRC 4SX projnav xrc4sx lt device gt ADM XRC 4FX projnav xrc4fx lt device gt ADPE XRC 4FX projnav xrce4fx lt device gt ADM XRC 5LX projnav xrc5 x lt device gt ADM XRC 5T1 projnav xrc5t1 lt device gt ADM XRC 5T2 projnav xrc5t2 lt device gt ADM XRC 5T2 ADV ADM XRC 5TZ projnav xrc5tz lt device gt ADM XRC 5T DA1 Modelsim scripts projnav xrc5tda1 lt device gt clock xrcbtz 5vIx330t ucf Example Modelsim compatible script files for simulating this design are provided Refer to the following table for the appropria
84. constants of type ddrsdram_timing_t However should it be necessary to create a new value the members are defined as follows Member cas_latency t_refresh t_mrd t_dllr t rp t rfc t act t wtr t rtw t rtp 291 Type natural natural natural natural natural natural natural natural natural natural Function CAS latency in half clock cycles The only supported value is 5 representing CL2 5 Average periodic refresh interval in clkO cycles Mode register set command period in cIkO cycles Minimum number of clkO cycles between DLL reset deasserted to first memory access Minimum number of cIkO cycles between PRE precharge and ACT row activation or REF refresh commands Number of cIkO cycles for completion of a REF refresh operation Minimum number of clk0 cycles between ACT row activate and a read or write command Minimum number of cIkO cycles between a write and a read command Minimum number of clkO cycles between a read and a write command Minimum number of clkO cycles between a read and a PRE precharge command ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram timing t t wtp natural Minimum number of clkO cycles between a write and PRE precharge command t ras natural Minimum number of cIkO cycles between ACT row activate and PRE precharge command All values in the above table are numbers of clkO cycles Thus e For parameters that are specified as delays in nano
85. conv string tant val in tring conv string tant val in tring conv string tant val in tring conv string tant val in tring time integer real boolean Overloaded function for converting values of various types to string values Description These functions return string values in a format appropriate to the type of val e A time value is returned as a string such as 44 0 ns e An integer value is returned as a string such as 27 e A real value is returned as a string such as 3 14159265 e A boolean value is returned as the string true or false 382 ADM XRC SDK 4 9 3 User Guide Win32 conv string hex ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference conv string hex Declaration Synopsis Description Declaration function conv string hex constant val in byte vector t return string function conv string hex constant val in integer return string function conv string hex constant val in std logic vector return string Synopsis Overloaded function for converting values of various types to string values Description These functions return string values in a hexadecimal format A prefix such as Ox is not prepended In the case of a byte vector t val 0 appears as the leftmost two digits of the returned string assuming that val 0 has an ascending range In the case of a std logic vector
86. device as defined here Asynchronous reset for memory port May be tied to logic if not required Synchronous reset for memory port May be tied to logic if not required Tag in When user code asserts ce with w deasserted it must also place a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags ADM XRC SDK User Guide Common Memory Ports trained sideband signal valid x4 14 Notes out Training success flag When the memory port asserts trained it indicates that training of the memory port was successful When deasserted either training is not yet complete or training was unsuccessful out Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid in Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command in X4 device select sideband signal 9 This input selects whether devices with 8 or 16 bit data or devices with 4 bit data are in use Generally applicable to DIMM DDR SDRAM memory In this version of
87. do I specify advanced command line options in the Project Navigator GUI An attribute or option is not available in the GUI 201 ADM XRC SDK 4 9 3 User Guide Win32 Running the Xilinx tools 202 This answer can be summarised as follows N Oo C A CQ ars eo In Windows create or set the environment variable PROJNAV BITGEN OPTION whose value is 1 Start Project Navigator Select Edit 2 Preferences from the Project Navigator main menu In the Preferences dialog click on the Processes tab Set Property Display Level to Advanced Click Ok to dismiss the Preferences dialog Right click on Generate Programming File in the Processes for Current Source panel Select Properties Click on the General Options tab You should now see a text field entitled Other Bitgen Command Line Options Enter g drivedone yes in the Other Bitgen Command Line Options field ADM XRC SDK 4 9 3 User Guide Win32 FPGA constraints files ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data FPGA constraints files Master constraints files for each supported board can be found in the ucf directory of the SDK These files contain e Mandatory constraints eg pin location constraints and IOB pullup constraints e Recommended constraints eg IOB slew rate constraints e Suggested constraints eg how to constrain a DLL to a particular location When
88. enables that accompany mem d e mem wnpf asserted by the memory banks module when the async port instance selected by sel bank 1h cannot accept more data to be written to memory The local bus interface uses this signal to hold off the local bus LREADY signal during a burst so that the FIFOs within the async port instances cannot overflow Explanation of memory banks module outbound datapath CS an port pre Q mem re port pre 3 port prpe Q mem me port prpe 3 it 0 mux port pa D ort muxed s mem q CTS 4 8 54 E port pa 3 E 3 EAE mem a 0 g gt 5 port plast 2 e x async portg nd mem adv 2 pO pre 0 prpe port pce D mem ce E pterm sa pady stad E Er 0 sqtag port padw Q TD ha swalid sready other ports mem tem to arbiter 2 instances async porta pre sreq prpe sce pce Sw pterm sa pady gag pq 5 pow stag pa svalid steady sel hank 1h 142 f other norte ADM XRC SDK 4 9 3 User Guide Win32 Memory64 sready sel bank 1h other ports cvv mem a 31 1 Detail of outbound datapath in the memory banks module As in the inbound datapath the one hot bank select vector sel bank 1h is used to ensure that at most one set of port p signals can be active at a given moment in turn ensuring that at most one async port instance can be active a
89. engines for the rapid transfer of data to and from the FPGA using API functions such as ADMXRC2 DoDMA and ADMXRC2 DoDMAImmediate The local bus protocol of a DMA initiated burst is the same as that of a direct slave burst Assuming demand mode DMA is not used a DMA initiated burst is indistinguishable from a direct slave burst This can be a useful property as it often permits an FPGA design to be tested first using direct slave transfers for convenience and later on with DMA transfers for throughput The following figure illustrates the differences between Direct Slave transfers CPU initiated and DMA transfers 232 ADM XRC SDK 4 9 3 User Guide Win32 DMA transfers data flow read re ad Host FCl to local FPGA bus bridge Direct Slave CPU initiated read of FPGA data flow re ad write E Host PCl to local FPGA bus bridge b DMA read of FPGA In a and b above the flow of data is from the host to the FPGA in both cases but they differ with respect to which entity initiates the transfers on the PCI bus 233 ADM XRC SDK 4 9 3 User Guide Win32 DMA transfers data flow write write Host PC to lacal FPGA bus bridge c Direct Slave CPL initiated write of FPGA data flow read write Hast PCl to local FPGA bus bridge d OMA write of FPGA In c and d above the flow of data is from the FPGA to the host in both cases but they differ with respect to which entity initiate
90. fall within different pages of the same bank or within different banks e Inthe order of 8 20 cIkO cycles for an access that occurs while the memory port is performing a refresh Latency for read commands is nondeterministic due to the penalties described above particularly because of the need to refresh but the best case latency from entry of a read command ce asserted with w deasserted to valid asserted is approximately 13 clkO cycles This can be modified somewhat by tightening or relaxing the timing as specified by the timing parameter Worst case latencies may be computed by adding the above penalties to the best case latency The optimal usage pattern for this memory port is blocks of accesses of the same type read or write to the same bank and page A linearly incrementing address is an example of an optimal usage pattern When used optimally this memory port with 32 physical data bits rd is 32 operating at a clkO frequency of 133MHz can sustain approximately 2GB s 322 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddrsdram port v2 component Overview HDL source code Parameters Signals Row column address selection Performance Overview The ddrsdram port v2 component is part of the memif package and implements an interface to a bank of DDR SDRAM memory related component is the ddrsdram training v2 component which provides i
91. files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location SADMXRC_SDK4 fpga vhdl clock Synopsis 81 ADM XRC SDK 4 9 3 User Guide Win32 Clock The Clock FPGA design can be used to approximately measure the frequencies of the signals present at the standard clock pins of the target FPGA It consists of a number of cycle counters that can be read via the local bus interface of the target FPGA FPGA Space Usage The following registers are accessible via the FPGA space READ read count command register local bus address 0x0 Bits Mnemonic Type Function 31 0 DO WO RAX Writing a 1 to a particular bit of this field initiates a read of the corresponding cycle counter STATUS status register local bus address 0x4 Bits Mnemonic Type Function 31 0 DONE RO A 1 in a particular bit of this field indicates that either no read command has been issued to the corresponding cycle counter or that the last read command issues to the corresponding cycle counter has been completed COUN
92. given type of memory device is discussed in the documentation for that type of memory port Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together into the rc bus so that for the most part the user application need not care what they are The correspondence between bits of rc and the various pins found on a given type of memory device is discussed in the documentation for that type of memory port Memory device data bus This bus carries data between the memory port and the memory device s ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram pinout t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sdram pinout t datatype The ddr2sdram pinout t datatype is exported by the memif package and is used to specify the physical configuration of an instance of ddr2sdram port It is a record type defined as follows type ddr2sdram pinout record family Ck width Cke width odt width num bank bits num addr bits end record t is family t na na na num phys bank na na na tural tural tural tural tural M 09 Ne Ne Ne Ne tural This datatype can normally treated as an abstract datatype since the user application need typically only use one of the predefined constants of type ddr2sdram_pinout_t However should it be necessary to create
93. indicates that the DCM that generates the clock for the memory clock domain is locked When 1 indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock Reserved ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV and ADM XRC 5T DA1 Bits Mnemonic Type 112 Function ADM XRC SDK 4 9 3 User Guide Win32 Memory 8 MEMCLK 9 IDELAY 15 10 ADM XRC 5TZ Bits Mnemonic 8 MEMCLK 9 RAMCLK 10 IDELAY 15 11 RO RO RO MBZ Type RO RO RO RO MBZ When 1 indicates that the PLL that generates the clocks for the memory clock domain is locked When 1 indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock Reserved Function When 1 indicates that the DCM that buffers the clock for the memory clock domain is locked When 1 indicates that the DCM that deskews the clocks driven to the ZBT SSRAM devices is locked When 1 indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock Reserved Memory status register MEMSTAT local bus address 0x18 This register indicates whether or not training of memory banks has been successful The precise bit field definitions depend upon the model in use Function This field always returns Oxf because the ZBT SSRAM ports do not require training Reserved This field always returns 0x3 because the ZBT SSRAM ports do not require training Reserved This field always returns Ox3F
94. into the rc bus so that for the most part the user application need not care what they are Refer to note 2 for the mapping of the rc bus to device pins rd inout Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via ce two words are transferred on rd which determines the relationship between the rd width and d with parameters Refer to note 3 for details Performance This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal Most of the time the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application Certain usage patterns however may result in a accumulated backlog in the command buffer A DDR II SSRAM device has a burst length of two or four i e two or four words on transferred on the rd bus This component supports burst length four BL4 devices but is compatible with burst length 2 devices without modification to see why this is so one must understand the signalling protocol used by generic DDR II SSRAM devices There are two potential performance penalties in this memory port e Every access to a BLA DDR II SSRAM device must transfer 4 physical words whose addresses are consecutive on the rd bus Because this takes two cIkO cycles random accesses to unrelated addresses when burst len is driven with 1
95. locations are the same width as the physical memory locations 20 is also the minimum value of a width When a width is larger than actually required the top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory devices are in use Signals The signals of this interface to and from the user application are as follows Signal Type Function Note a in Logical address User code must place a valid address on a when it asserts ce Unlike certain other types of memory where the address driven on ra is some function of what is entered via a for ZBT SSRAM devices the logical address can be observed on the ra bus delayed by a few clk cycles be in Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory ce in Command entry User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single c
96. memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates the fields that comprise the rc bus Width ofthis field is rd width 8 Erg a porreces ca ce c ke K wf Present if pinout has cistrue Present if pinout has_oy istrue The order of the fields within rc is always the same but some models may lack certain fields ADM XRC SDK User Guide Common Memory Ports 3 The rd width parameter is the number of physical DQ wires making up the data bus of the DDR II SSRAM bank This memory port transfers two words of data on the DQ wires for each command entered via the ce signal Accordingly the d width parameter which is the width of d and q is typically specified by the user application as being two times rd width However other values can be passed for d width If d width gt 2 rd width then the memory port simply truncates d internally so that its width is 2 rd width Data read from the memory devices is zero extended so that its width is d width before being returned on q o d width 2 rd width is the optimal usage case o If d width lt 2 rd width then the memory port zero extends d internally so that its width is 2 rd width 4 Thea width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a DDR II SSRAM bank Hence the requi
97. memory64 xrce4fx v4fx scr memory64 xrce4fx v4fx scr memory64 xrcb5lx v5lx scr memory64 xrc5t1 v5fxt scr memory64 xrc5t1 v5Ixt scr memory64 xrc5t1 v5sxt scr XST project file memory64 xrc4fx v4fx prj memory64 xrc4fx v4fx prj memory64 xrce4fx v4fx prj memory64 xrce4fx v4fx prj memory64 xrc5lx v5lx prj memory64 xrcbt1 v5fxt prj memory64 xrcbt1 v5lxt prj memory64 xrcbt1 v5sxt prj UCF file xrcAfx memory64 xrc4fx 4vfx100 ucf xrcAfx memory64 xrc4fx 4vfx140 ucf xrce4fx memory64 xrce4fx Avfx100 ucf xrce4fx memory64 xrce4fx Avfx140 ucf xrcblx memory64 xrcblx ucf xrcbt1 memory64 xrcbt1 5vixt ucf xrc5t1 memory64 xrcbt1 ucf xrc5t1 memory64 xrcbt1 ucf ADM XRC SDK 4 9 3 User Guide Win32 Memory64 ADM XRC 5T2 or ADM XRC 5T2 ADV with V5LX110T V5LX155T or V5LX220T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5LX330T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5FX100T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5FX130T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5FX200T ADM XRC 5T2 or ADM XRC 5T2 ADV with V5SX240T memory64 xrcb5t2 v5lxt 4banks scr memory64 xrcb5t2 v5lxt 6banks scr memory64 xrcb5t2 vb5fxt Abanks scr memory64 xrcb5t2 vbfxt Abanks scr memory64 xrcb5t2 vbfxt 6banks scr memory64 xrcbt2 v5sxt_6banks scr memory64 xrc5t2 v5lxt 4banks prj memory64 xrcbt2 v5lxt 6banks prj memory64 xrc5t2 vdfxt_4banks prj memory64 xrc5t2 vdfxt_4banks prj memory64 xrc5t2 v5f
98. memorylike region on the local bus is defined to be a range of the local bus address space where reads and writes have side effects For example an FPGA design may implement a FIFO whose read and or write ports are mapped to a particular local bus addresses Reading or writing these ports causes the FIFO s internal state to change which is considered to be a side effect When performing DMA transfers to non memorylike regions unaligned DMA transfers should be used with great care An unaligned DMA transfer is one where the host memory buffer for the DMA transfer does not begin at an aligned address If a 32 bit wide local bus is being used then an aligned address is one whose lower two bits are zero If a 64 bit wide local bus is being used then an aligned address is one whose lower three bits are zero First consider the following DWORD aligned DMA transfer assuming that the local bus has 32 bit wide data e There is a 32 bit wide FIFO mapped to local bus address 0x100 e he application performs a DMA write into this FIFO from a 28 byte long buffer in host memory whose address is DWORD 4 byte aligned and just happens to cross a physical page boundary 239 ADM XRC SDK 4 9 3 User Guide Win32 Caveats of DMA transfers Word LD 31 0 LAD 31 0 LBE3 3 0 7 27 26 25 24 0000 0000 elere ww page boundary 4 0000 EZB 8 0000 2 0000 user space address IE EOS CS 1 ER ET 0000 DWORD al
99. mode by the FPGA design An FPGA design that does not use demand mode DMA need not include any demand DMA agents This multithreaded approach is demonstrated by the testbench for the DDMA sample FPGA design 362 ADM XRC SDK 4 9 3 User Guide Win32 byte enable t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference byte enable t Declaration Synopsis Description Declaration type byte enable t is array natural range lt gt of std logic Synopsis byte enable t is a vector type used to hold byte enables for a local bus transfer Description Use this vector type to hold the byte enables for a local bus transfer in a call to one of the following functions e plxsim read e plxsim read const e plxsim read demand e plxsim read const demand e plxsim write e plxsim write const e plxsim write demand e plxsim write const demand Each element of the vector corresponds to one byte of data and normally the length of the vector should be same as the length of the byte vector t it is associated with A 1 results in the corresponding bit of the local bus signal LBE being asserted low To avoid confusion and problems related to ascending vs descending ranges the range of any objects of type byte enable t should always be ascending for example variable data variable data 363 byte enabl byte enabl e t 0 to 15 Ok e t 9 downto 3
100. not required knowledge of the reference clock oscillator in order to program the clocks The ClockType parameter points to a variable of type ADMXRC CLOCK TYPE that is filled in with the type of clock oscillator fitted 522 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC GetsStatusString ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC GetsStatusString Prototype const char ADMXRC GetStatusString ADMXRC STATUS Code Arguments Argument Type Purpose Code In The error code to convert to a string Return value Unlike most API functions ADMXRC_GetStatusSiring returns a pointer to a NULL terminated string that describes the error code Description This function returns a textual description of the error code passed in the Code parameter The returned string should be treated as read only since it is statically allocated If the Code parameter contains a code that is not one of the members of the enumerated type ADMXRC STATUS the string returned will be unknown ADMXRC2 STATUS code 523 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC GetVersionInfo ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC GetVersionlnfo Prototype ADMXRC STATUS ADMXRC GetVersionInfo ADMXRC HANDLE Card ADMXRC VERSION INFO Info Arguments Argument Type Purpose Card In Handle of card about which to obtain information Info Out Structure to be filled in with version
101. o 1 are deasserted This ensures that LREADY and LBTERM are driven high for one cycle at the end of each transfer 2 For convenience the stop signal need only be pulsed for a single clock cycle even when the user application has not yet asserted ready The state machine remembers that stop has been asserted via the stopping signal that is internal to the machine PLXDSSM timing diagrams Here a read and a write are shown In the case of the write ready is used to insert two extra wait cycles 261 ADM XRC SDK 4 9 3 User Guide Win32 PLXDSSM a practical example ek SVL LULA UU US LN LDSR X o m Local Bus signals LA Derived from Local LBE BEO Bus signals LWRITE SN RAW Rr m Driven by PLXDSSM LBLAST Driven by user application LBTERME ff alads f Ig decode i VA lready oe JG lready_o_ _ J oe I f bermol y f eld oe Ho Of transfer ready SESS RTE sop Mg yy IQ WA ESSA AMA STATE IDLE decoog XFER IDLE decoog WAIT XFER IDLE Notes 1 Asserting stop coincident with or earlier than ready always results in the transfer being terminated by LBTERM with exactly one word of data transferred 2 ready and siop are ignored until PLXDSSM asserts decode 3 In the read transfer ready and stop are asserted coincident
102. of LREADY by the slave LD is present only on cards that have a nonmultiplexed address bus Local Ready LREADYZ is asserted by the slave to indicate that the word of data currently on the LD or LAD bus has been transferred If LBLAST is also asserted the current burst ends Local Bus Reset LRESET is asserted asynchronously by the local bus bridge in order to cause all agents on the local bus to return to a known state where they are not driving the local bus Local Write LWRITE indicates whether the current burst is a read or a write If it is asserted then the cycle is a write the master drives data onto LD or LAD LWRITE is valid for every cycle of a burst ADM XRC SDK 4 9 3 User Guide Win32 Bussed signals 5 L64 master Local bus 64 bits L64 indicates whether the current burst is a 32 bits or 64 bits wide If it is asserted then the cycle is a 64 bit burst where the master drives data onto LD 63 0 or LAD 63 0 If it is deasserted then the cycle is 32 bit burst where the master drives data onto LD 31 0 or LAD 31 0 L64 is valid for every cycle of a burst This signal is not present in all models of the ADM XRC range Note 1 LA LD amp LAD The ADM XPL ADM XP ADP XPI ADM XRC 4FX ADM XRC 5LX and ADM XRC 5T1 do not have the LA or LD busses Instead they have the LAD bus which carries multiplexed address and data Note 2 LBTERM amp LBTERMO Models featuring a PCI9080 as the
103. one clock cycle The IARM register must be used to rearm the edge sensitive FINTI signal Writing to IARM forces FINTI high for one cycle Consider the following sequence of events 1 FPGA interrupt source 0 becomes active FINTI transitions low Host interrupt handler executes and samples ISTAT determining that interrupt source 0 is active FPGA interrupt source 1 becomes active Host interrupt handler takes whatever action is necessary to make interrupt source 0 inactive and finishes a amp CO I FINTI does NOT transition high because interrupt source 1 is still active Unfortunately the host did not see interrupt source 1 become active As far as it is concerned no more interrupts have arrived yet interrupt source 1 is now active and will not be handled as FINTIZ is still low Note that FINTI is an edge triggered signal The solution is simply for the host s interrupt handler to write to IARM just before exiting 102 ADM XRC SDK 4 9 3 User Guide Win32 ITest 1 FPGA interrupt source 0 becomes active FINTI transitions low Host interrupt handler executes and samples ISTAT determining that interrupt source 0 is active FPGA interrupt source 1 becomes active Host interrupt handler takes whatever action is necessary to make interrupt source 0 inactive Host interrupt handler writes a dummy value to IARM and finishes o oa A C FINTI transitions high for one cycle then low again since i
104. out Capture clock phase 0 7 11 This clock is normally driven directly by the component ddrsdram training v2 and is used by ddrsdram port v2 to capture data read from the SDRAM device in the FPGA s IOBs Capture clock phase 180 7 11 This clock is normally driven directly by the component ddrsdram training v2 and is used by ddrsdram port v2 to capture data read from the SDRAM device in the FPGA s IOBs Column address width select sideband signal 6 8 This input selects the number of column address bits to use Along with the row input it specifies the row column geometry of the DDR SDRAM device as defined here Data to memory User code must place valid data on d whenever a write command is entered ce and w both asserted Physical bank select sideband signal 6 8 This input selects the number of physical banks chip selects in use for the DDR SDRAM devices 00 gt 1 physical bank 1 CS 01 gt 2 physical bank 2 CS 10 gt 4 physical bank 4 5 11 gt 8 physical bank 8 CS Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a read command gtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Certain types of memory port may unconditionally assert
105. out of data in its FIFO This signal is used by the local bus interface to terminate the current burst on the local bus in order to avoid undefined data being read by the CPU Explanation of memory banks module memory arbitration The final figure in this discussion shows how each memory port is shared between the local bus interface represented by an async port and the user app module with reference to the ADM XRC 4FX 143 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 Loca bus dock domain Memory user dock domain memory configuration and status registers in local bus interface MODE register for memory bank i 32 asynd port arbiter 2 ort sredi port USE _ port s ddr2sdram port pieds port L P 1 port_stag i port pti 45 a 31 1 128 port port mercik 2x0 00841 rep d memelk 2x90 SDRAM rep be 55 TE pins port pa i por svidi arb ce i ray port pw posee port papfti rd port pre i T arb Tag i port prpe i arb d i J T5 arb 90 128 arb dtag user ew arb TE n arb ready uera user tad to from user di client 1 meo user app 28 use bei port 8 _ 16 use di 128 user qtag i 0 user validi user ready trained Detail of logic for sharing a memory bank within the memory banks module
106. out t e plxsim read e plxsim read const e plxsim read const demand 373 ADM XRC SDK 4 9 3 User Guide Win32 locbus out t e plxsim read demand e plxsim write e plxsim write const e plxsim write const demand e plxsim write demand Since it is an opaque datatype the members of locbus ddma out t should not be accessed as they are subject to change in future versions of the PLXSIM package 374 ADM XRC SDK 4 9 3 User Guide Win32 init locbus ddma out ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference init locbus ddma out Declaration Synopsis Description Declaration constant init locbus ddma out locbus ddma out t Synopsis init locbus ddma out t is a constant that can be used to initialize a value of type locbus ddma out tto its initial inactive state Description This constant may assigned to a value of type init locbus out t in order to set it to an initial inactive state This initialization is required somewhere in the testbench in order to prevent undefined values being driven onto the FPGA s demand mode DMA pins Typically init locbus ddma out t is applied at the declaration of a signal for example Signal out0 ddma outl locbus ddma out t init locbus out Since locbus ddma out t is an opaque datatype the members of init locbus ddma out t should not be accessed as they are subject to change in future versions of t
107. plxddsm2 Notes 1 Both the request and burst signals are used to generate Idreq o l but which one is used at a given moment depends on whether or not there is a demand mode DMA local bus cycle in progress If no cycle is in progress Idreq o lis generated from request If a cycle is in progress Idreq o l is generated from burst 2 The purpose of the request signal is different to that of the ready signal The ready signal permits data transfer to occur in a local bus cycle that has already started The request signal on the other hand is used to control whether or not the PCI to local bus Bridge generates demand mode DMA local bus cycles Deasserting request prevents plxddsm2 from asserting Idreq o 1 which in turn prevents the PCI to local bus Bridge from generating further demand mode DMA cycles for a given DMA channel Asserting request causes plxddsm to assert o which in turns allows the PCI to local bus Bridge to generate demand mode DMA cycles for a given DMA channel Usage This component works by snooping on demand mode DMA local bus cycles When no demand mode DMA local bus cycle is in progress plxddsm2 asserts o 1 and only if its request input is asserted During a demand mode local bus cycle plxddsm 2 asserts Idreq o lif and only if its burst input is asserted Thus the possible values of request and burst yield the following behaviour request burst Behavior 0 X Not requesting a demand mode
108. rd width ium Tre prea oer Er ines Present if pinout has ce2 istrue Present if pinout has_ce is true Present if pinout has listre The order of the fields within re is always the same but some models may lack certain fields 3 The rd width parameter is the number of physical DQ wires making up the data bus of the DDR II SSRAM bank This memory port transfers one word of data on the DQ wires for each command entered via the ce signal Accordingly the d width parameter which is the width of d and q is typically specified by the user application as being the same as rd width However other values can be passed for d width o lf d width gt rd width then the memory port simply truncates d internally so that its width is rd width Data read from the memory devices is zero extended so that its width is d width before being returned on q 356 ADM XRC SDK 4 9 3 User Guide Win32 zbtsram port o d width rd width is the optimal usage case o If d width lt rd width then the memory port zero extends d internally so that its width is width 4 Thea width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a ZBT SSRAM bank Hence the required value of a width depends on what memory devices are actually in use As an example consider a ZBT SSRAM device with 20 address bits Since logical memory
109. result of the read command the memory port asserts validi the qtagi output reflects the tag value originally passed Client read data valid note 9 When validi is asserted by the memory port it is as a result of a read command client asserted cei with wi deasserted When validi is asserted both qi and qtagi are valid Client write select When a client asserts cei it must place either a logic 1 the wi signal in order to select a write command or 0 in order to select a read command can be confused for client 1 s reads and vice versa 9 The validO and valid1 outputs are always asserted together by arbiter 2 If one of the validi signals is asserted then all must be asserted This is because it is the responsibility of each client to recognize its own tags The arbiter 2 module does not attempt to decode the qtag signal see below in order to determine which client issued the corresponding read command The following figure illustrates a read command issued by client 1 All validi signals are always asserted together ADM XRC SDK 4 9 3 User Guide Win32 arbiter 2 With reference to the above figure client 1 issues the read and recognizes its own data by decoding qtag1 However clients 0 must also decode qtag0 and determine that the data does not belong to it Depending on how many clients there are decoding a tag may be as simple as checking the top bit or top couple of bits of a qtag value The interface presente
110. same as the qlads signal for the plxdssm instance 4 The control logic for generating the ready should be that of the plxdssm instance The ready signal should be the same one that is input to the plxdssm instance 5 The logic for generating request depends on whether a given demand mode DMA channel is being used to a read or b write the FPGA o For reads the FPGA must typically determine whether or not sufficient data is available in a FIFO or some other 273 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm2 buffer in order to allow demand mode DMA to proceed If there is the FPGA asserts request o For writes the FPGA must typically determine whether or not there is sufficient space for further data in some FIFO or buffer in order to allow demand mode DMA to proceed If there is the FPGA asserts request 6 To add an additional demand mode DMA channel everything within the shaded area of the above figure should be replicated and a different LDACK and LDREQ pair chosen 274 ADM XRC SDK 4 9 3 User Guide Win32 plxdssm ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The plxdssm component Overview HDL source code Signals Usage Overview The plxdssm component is part of the localbus package and provides the control mechanism for a local bus interface within an FPGA design HDL source code qlads Iblast Ibterm to from user eld_oe pee 2 Bus application Id oe pi
111. simple64 xpl do ADM XP vsim do do simple64 xpl do ADM XPI vsim do do simple64 xpi do ADM XRC 4FX vsim do do simple64 xrc4fx do ADPE XRC 4FX vsim do do simple64 xrce4fx do ADM XRC 5LX vsim do do simple64 xpl do ADM XRC 5T1 vsim do do simple64 xpl do ADM XRC 5T2 vsim do do simple64 xpl do ADM XRC 5T2 ADV 158 ADM XRC SDK 4 9 3 User Guide Win32 ZBT ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ZBT sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga vhdl zbt Synopsis Note this FPGA design has been effectively superseded by the Memory sample FPGA design VHDL since the latter is more general and supports a larger number of models and types of memory 159 ADM XRC SDK 4 9 3 User Guide Win32 ZBT The ZBT FPGA design demonstrates how to implement a host interface to the SSRAM in an FPGA design The design divides the 4MB FPGA space into a lower 2MB region for register and an upper 2MB window for accessing the SSRAM A page register is provided so that all of the SSRAM on a card is
112. source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location ADMXRC_SDK4 fpga vhdl dll Synopsis 95 ADM XRC SDK 4 9 3 User Guide Win32 DLL The DLL FPGA design demonstrates the clock doubling capability of Virtex DLLs and Virtex ll Virtex IIPro Virtex 4 Virtex 5 The local bus clock LCLK is input through a clock and doubled using a DLL Virtex E EM or DOM Virtex ll Virtex IIPro Virtex 4 or Virtex 5 A 32 bit host readable counter is clocked by a 2X multiple of LCLK FPGA Space Usage Count register COUNT local bus address 0x0 Bits Mnemonic Type Function 31 0 N R W Number of elapsed cycles of 2X multiple of LCLK The COUNT register returns the number of elapsed cycles of the 2X multiple of LCLK It can be preset to a particular value by writing to it Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model ADM XRC with Virtex ADM XRC with Virtex E ADM XRC P with Virtex ADM XRC P with Virtex E ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with FXT ADM XRC 5T1 with LXT ADM XRC 5T1 with SXT 96 XST script file dll xrc v scr dll xrc ve scr dll
113. stale data to the local bus clock domain when one read ends and another one begins e The d signal is qualiied by the logical AND of ce and w and carries the data for a write command ADM XRC SDK 4 9 3 User Guide Win32 Memory64 The be signal is qualiied by the logical AND of ce and w and carries the active high byte enables for a write command When bit of beis 1 byte will be written When bit i of beis 0 byte will not be written The q signal is the data read from the memory devices for a particular read command and is qualified by valid The qtag signal is the tag value associated with a particular read command and is qualified by valid The valid signal indicates that data read from the memory devices is present on q along with the associated tag value on qtag The ready signal indicates that the memory port is able to accept commands When ready is zero the ce signal must be deasserted In addition to the generic memory port signals a particular type of memory port may have one or more sideband signals that are specific to that particular type of memory port In the above figure the ddr2sdram port module has four sideband signals that specify the paramters of the memory devices that it is controlling They are row col bank and pbank and their values are determined by the bit fields in the MODE register that is described above for the case of a DDR II SDRAM memory bank Explanation of user app module The user
114. test for banks 0 1 and 3 only Writing a 1 to a bit that corresponds to a nonexistent or unused bank has no effect 31 16 ERROR RO Returns a 1 for a particular bit if one or more errors occurred during the memory test for the corresponding memory bank Valid only when the corresponding bit of the DONE field is 1 For each bit of ERROR indicates that failure the corresponding EPHASE field may be inspected in order to discover the phase of the memory test in which the first failure occurred Explanation of design At the highest level of abstraction the design consists of 3 logical blocks e Local bus dock Memory clock domain domain Local Bus Interface Ports User Application Local Bus Chip driven Memory T est To from memory banks High level view of the MEMORY reference design The local bus interface enables the CPU to read and write the memory banks At the same time the user application module can also read and write the memory banks The local bus interface and the user application also communicate with each other via a set of registers The user application as supplied in this SDK is in fact a chip driven memory test which can test all memory banks simultaneously on command from the host The user can rewrite the user application replacing the memory test logic with whatever processing logic he or she requires Because the FPGA space is limited to 4MB on most models the local bus interface of th
115. the Card parameter The Buffer parameter should point to a buffer containing the configuration data for the FPGA The data must be supplied in a form directly writable to the FPGA s SelectMap port and care should be taken to ensure that the bit ordering of the data is correct The ADMXRC2 LoadBitstream function can be used to obtain SelectMap data in the correct form The Length parameter specifies the number of bytes of configuration data to be written to the FPGA s SelectMap port 430 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ConfigureFromBufferDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 ConfigureFromBufferDMA Prototype ADMXRC2 STATUS ADMXRC2 ConfigureFromBufferDMA ADMXRC2 HANDLE Card const void Buffer unsigned long ength unsigned int Channel HANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure Buffer In FPGA configuration data Length In Length of FPGA configuration data Channel In DMA channel to use for the operation Event In Event to use to wait for completion Return value Value Meaning ADMXRC2 SUCCESS ADMXRC2 INVALID HANDLE ADMXRC2 INVALID PARAMETER ADMXRC2 NO DMADESC Description The FPGA was successfully configured Card is not a valid handle to a card An invalid parameter was passed A DMA descriptor could not be allocated This function is used to configure the FPGA on a card from a buffer of SelectMap data u
116. the data flow within xrc4fx memory_banks xrc4fx vhd This is the ADM XRC 4FX specific version of the memory banks module local bus dock domain memory user dock domain arbiter 2g to from user app ddr2sdram portg control address data tag etc for bank 0 128 16 port repl async port arb 0 rc mem d data byte enables cmd tag data byte prie mem be etc to memory enables etc to bank 0 32 128 128 4 16 16 port_p signals 128 port s 0 signals data tag valid etc from bank 0 128 arbiter 24 port mux to from mem aq user app ddr2sdram porta 32 128 l control address data tag etc for bank 3 128 16 as ort rc3 CHO tag data byte pris enables etc to bank 3 rd3 128 port s 3 signals data tag valid etc from bank 3 128 128 Data flow within the memory banks module When data is written to a memory bank the port repl module takes 32 bit data words from the local bus interface on mem d and and assembles them into words suitable for the memory ports in this case DDR II SDRAM ports whose logical data with is 128 A set of async port instances bridge the local bus clock domain and the memory clock domain In the 120 ADM XRC SDK 4 9 3 User Guide Win32 Memory memory clock domain a set of arbiter 2 instances connect together both the preceding async port instances and the user ap
117. the desired number of bytes has been transferred e When false the procedure will return if the burst is terminated and nxfered will reflect the actual number of bytes transferred e When true the procedure will perform transfers on the local bus until the desired number of bytes has been transferred In this case nxfered will be set to the length of data The address parameter specifies the local bus byte address of the transfer which will not be incremented during the transfer The address need not be aligned to the word size of the local data bus although an unaligned address generally makes little sense when using constant addressing The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address After the first word of data has been transferred LBE will revert to being determined by the be parameter and on the last word of the transfer also determined by any residual bytes that do not comprise a full word of data The be param
118. the user to specify a NULL value for the PHANDLE In that case the API creates and returns a manual reset event on the calling thread s behalf This is intended simply as a shortcut to remove the need for the above code fragment It is good practice for a thread to close its event using the Win32 CloseHandle function before terminating although any open handles that remain are closed automatically when the parent process of the thread terminates 505 ADM XRC SDK 4 9 3 User Guide Win32 Functions ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC interface functions The ADMXRC interface can be divided into the following function groups Group Consists of Initialization ADMXRC CloseCard ADMXRC OpenCard Information ADMXRC GetBaseAddress ADMXRC GetClockType ADMXRC GetVersionlnfo FPGA configuration ADMXRC ConfigureFromBuffer ADMXRC ConfigureFromBufferDMA ADMXRC ConfigureFromFile ADMXRC ConfigureFromFileDMA ADMXRC FindlmageOffset ADMXRC LoadFpgaFile ADMXRC ReverseBytes ADMXRC UnloadFpgaFile Clock generation ADMXRC SetClockRate Data transfer ADMXRC BuildDMAModeWord ADMXRC DoDMA ADMXRC_DoDMAImmediate ADMXRC MapbDirectMaster ADMXRC Read ADMXRC ReadReg ADMXRC SetupDMA ADMXRC SyncDirectMaster ADMXRC UnsetupDMA ADMXRC Write ADMXRC WriteReg Interrupt handling ADMXRC RegisterlnterruptEvent ADMXRC UnregisterInterruptEvent Error handling ADMXRC GetStatusString ADMXRC InstallErrorHandler A
119. transferred on DMA channel 1 Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table 87 ADM XRC SDK 4 9 3 User Guide Win32 DDMA Model ADM XRC with Virtex ADM XRC with Virtex E ADM XRC P with Virtex ADM XRC P with Virtex E ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with FXT ADM XRC 5T1 with LXT ADM XRC 5T1 with SXT ADM XRC 5T2 or ADM XRC 5T2 ADV with FXT ADM XRC 5T2 or ADM XRC 5T2 ADV with LXT ADM XRC 5T2 or ADM XRC 5T2 ADV with SXT ADM XRC 5TZ with FXT ADM XRC 5TZ with LXT ADM XRC 5TZ with SXT ADM XRC 5T DA1 with FXT ADM XRC 5T DA1 with LXT 88 XST script file ddma xrc v scr ddma xrc ve scr ddma xrcp v scr ddma xrcp ve scr ddma xrc2l v2 scr ddma xrc2 v2 scr ddma xpl v2p scr ddma xp v2p scr ddma wrc2 v2 scr ddma drc2 v2 scr ddma xpi v2p scr ddma xrc4lx v4lx scr ddma xrc4sx v4sx scr ddma xrc4fx v4fx scr ddma xrc4fx v4fx scr ddma xrce4fx v4fx scr ddma xrce4fx v4fx scr ddma xrcblx v5lx scr ddma xrcbt1 v5fxt ser ddma xrcbt1 v5lxt scr ddma xrcbt1 v5sxt scr ddma xrc5t2 vbfxt scr ddma xrc5t2 vblxt scr ddma xrc5t2 v5sxt scr ddma xrcbtz vbfxt scr ddma xrcbtz v5lxt scr ddma
120. tstok indicate experiment was successful for all memory ports then if not in window then Start of window detected window start phase in window true end if else if in window then End of window detected window stop phase window length window stop window start if window length some minimum window and window length best window This is the new best window best window window length best cedge cedg best phase window stop window start 2 end if in window false end if end if end if if in window then wh re still r Ww Handle special cas inside window at end of phase sweep window_stop 180 window_length window stop window start if window length some minimum window and window length best window This is the new best window best window window length best cedge cedg best phase window stop window start 2 end if end if end loop Training completed tstcomp 1 if best window gt 0 then trained 1 Training completed and successful set phase of clkcO to best phase cedge best cedg end if HDL source code SO Set operating parameters Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif_pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim
121. used for CardlD the first card found that is not in use will be opened regardless of its ID The handle returned in the Card parameter should be used in all further API calls that need to access this card When access to the card is no longer required call ADMXRC2 CloseCard to close the handle and free the card 454 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_OpenCardByIndex ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 OpenCardByiIndex Prototype ADMXRC2 STATUS ADMXRC2 OpenCardByIndex unsigned int Index ADMXRC2 HANDLE Card Arguments Argument Type Purpose Index In Index of card to open Card Out Handle to opened card Return value Value Meaning ADMXRC2 SUCCESS The card was successfully opened ADMXRC2 CARD NOT FOUND The card was in use or not physically present Description This function is used to open and obtain a handle to an ADM XRC card The particular card to open is identified by the Index parameter The cards in a system are enumerated in a system dependent order and the order of enumeratation may vary depending upon the system s bus topology Applications should not rely upon a particular order of enumeration The handle returned in the Card parameter should be used in all further API calls that need to access this card When access to the card is no longer required call ADMXRC2 CloseCard to close the handle and free the card 455 ADM XRC SDK 4 9 3 User Gui
122. which is also the number CS pins present in the rc bus Specifies the number of BA bits internal bank bits on the devices being driven by the memory port Specifies the number of A bits row column address bank bits on the devices being driven by the memory port The value of ddrsdram pinout t passed in the pinout parameter of a ddrsdram port determines the proper values to pass for the ra width and rc width parameters The relevant formulae are ra width num bank bits num addr bits 288 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram pinout t rc width 2 rd width 8 2 num ck width num phys bank 289 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram pinout t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sram pinout t datatype The ddr2sram pinout t datatype is exported by the memif package and is used to specify the physical configuration of an instance of ddr2sram port It is a record type defined as follows type ddr2sram pinout t is record family Family ts has_c boolean has cq boolean capture 180 boolean end record This datatype can normally treated as an abstract datatype since the user application need typically only use one of the predefined constants of type ddr2sram pinout t However should it be necessary to create a new value the members are defined as follows Member Type Function family family t Specifies the
123. with constant local address on the local bus A procedure for performing a basic demand mode DMA read transfer on the local bus A procedure for requesting or relinquishing access to the local bus A procedure for delaying execution for a particular number of local bus clock cycles A procedure for waiting until the FPGA requests a demand mode DMA transfer A procedure for performing a basic write transfer on the local bus A procedure for performing a basic write transfer with constant local address on the local bus A procedure for performing a basic demand mode DMA write transfer with constant local address on the local bus A procedure for performing a basic demand mode DMA write transfer on the local bus Purpose A component that can be instantiated in a testbench in order to flag local bus protocol violations A component that can be instantiated in order to connect a stimulus process to the demand mode DMA signals for a particular DMA channel A component that can be instantiated in order to connect a stimulus process to a 32 bit multiplexed address data local bus A component that can be instantiated in order to connect a stimulus process to a 64 bit multiplexed address data local bus A component that can be instantiated in order to connect a stimulus process to a 32 bit nonmultiplexed address data local bus ADM XRC SDK User Guide PLXSIM Package locbus arb A component that can be instantiated in order to arbitrate between st
124. with each other at the earliest possible time namely when decode is asserted 4 In the write transfer stop is asserted early and PLXDSSM remembers until ready is asserted It is not necessary to keep stop asserted until ready is asserted Here a burst read is shown ready is used to insert one extra wait cycle and stop is asserted sometime after ready in order to terminate the burst 262 ADM XRC SDK 4 9 3 User Guide Win32 PLXDSSM a practical example Last LA LBE BEO j BE2 J BES BES SOQ ESS LREADYRE ef LD DO Y D2 03 y D4 Y ps qlads EE EE idle E decode MEN blast lready oe transfer j ready Mn sop SESS STATE IDLE de cong walt XFER IDLE Notes Key W Local Bus signals Derived from Local Bus signals m Driven byPLXDSSM Driven by user application 1 Once ready has been asserted it is not necessary to keep it asserted for the remainder of the burst LREADY cannot be deasserted except by ending the burst 263 ADM XRC SDK 4 9 3 User Guide Win32 Common HDL components ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Common HDL components This section documents the common HDL components that are used by the sample FPGA designs e Local bus interface package VHDL for making an FPGA design accessible by a
125. would build the Verilog version of the ZBT design for an ADM XRC II fitted with a 2V6000 device cd d ADMXRC_SDK4 fpga verilog zbt make bit xrc2 2v6000 The full path and filename of bitstreams built this way will be relative to the root directory of the SDK e fpga verilog lt design gt output lt design gt lt model gt lt device gt bit for Verilog designs e fpga vhdl lt design gt output lt design gt lt model gt lt device gt bit for VHDL designs 79 ADM XRC SDK 4 9 3 User Guide Win32 VHDL designs ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Sample VHDL FPGA designs A number of sample VHDL FPGA designs are included with the SDK The purpose of these designs is to demonstrate functionality available on the ADM XRC series of cards and also to serve as customisable starting points for user developed applications The designs are intentionally trivial so that code that implements the functionality being demonstrated can easily be seen The sample FPGA designs are used by the sample applications which demonstrate how software running on the host CPU can interact with an FPGA design The table below lists the sample FPGA designs and the sample applications that use them Design name Used by application s Clock Clock DLL DLL DDMA DMA DDMA64 DMA FrontlO FrontlO ITest ITest Master Master Memory Memory Memory64 Memory RearlO RearlO Simple Simple Simple64 Simple ZBT Memtes
126. wrc2 v2 prj itest drc2 v2 prj Project Navigator project file itest xrcp ucf itest xrcp ucf itest xrc2l ucf itest xrc2 ucf itest xpl ucf itest xp ucf itest wrc2 ucf itest drc2 ucf ADM XRC SDK 4 9 3 User Guide Win32 ITest ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II 182 projnav re device projnav rcp device projnavxrc2 device projnav xrc2 lt device gt projnav xpl lt device gt projnav xp lt device gt projnav wrc2 lt device gt projnav drc2 lt device gt ADM XRC SDK 4 9 3 User Guide Win32 Master ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Master sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog master Synopsis The Master FPGA design demonstrates direct master access by the FPGA to host memory FPGA Space Usage 183 ADM XRC SDK 4 9 3 User Guide Win32 Master The design implements several registers for generating Direct Master transfers to and from host memory Address register ADDR local bus address 0 0 Bits Mnemonic
127. xpl lt device gt projnav xp lt device gt projnav xpi lt device gt projnav xrc4fx lt device gt projnav xrce4fx lt device gt projnav xrc5 x lt device gt projnav xrc5t1 lt device gt projnav xrc5t2 lt device gt ADM XRC 5T2 ADV Modelsim scripts Example Modelsim compatible script files for simulating this design are provided Refer to the following table for the appropriate command line for a particular model Model 93 Shell command ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 ADM XPL vsim do do ddma64 xpl do ADM XP vsim do do ddma64 xpl do ADP XPI vsim do do ddma64 xpi do ADM XRC 4FX vsim do do ddma64 xrc4fx do ADPE XRC 4FX vsim do do ddma64 xrce4fx do ADM XRC 5LX vsim do do ddma64 xrc5 do ADM XRC 5T1 vsim do do ddma64 xrc5 do ADM XRC 5T2 vsim do do ddma64 xrc5 do ADM XRC 5T2 ADV 94 ADM XRC SDK 4 9 3 User Guide Win32 DLL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DLL sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same
128. 0 commands before deasserting the ready signal Most of the time the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application Certain usage patterns however may result in a accumulated backlog in the command buffer A specific DDR II SSRAM device from a given vendor is one of two varieties burst length two BL2 or burst length four BL4 This is the number of words that are be transferred on the device s DQ pins from a single command entered via the device s LD pin This component supports burst length four BL4 devices but is also compatible with burst length two BL2 devices without modification which is a consequence of the signalling protocol used by DDR II SSRAM devices There is one performance penalty in this memory port e Turning the rd bus around when a read command and a write command are entered in consecutive clock cycles requires one clkO cycle Thus it incurs a one cycle performance penalty This penalty occurs only if a write command is entered in the one cycle window following entry of a read command Latency for read commands is fairly deterministic since the penalties described above are limited to one cycle although these penalties may be accumulated by successive commands The best case latency from entry of a read command ce asserted with w deasserted to valid asserted is approximately 10 cIkO cycles Worst case latencies may be computed by a
129. 0TFF1136 XC5VFX100TFF1738 XC5VFX130TFF1738 XC5VFX200TFF1738 XC5VLX110TFF1136 XC5VLX110TFF1738 XC5VLX155TFF1136 XC5VLX155TFF1738 24 ADM XRC SDK 4 9 3 User Guide Win32 Hardware supported o XC5VLX220TFF1738 o XC5VLX330TFF1738 o XC5VSX95TFF1136 o XC5VSX240TFF1738 25 ADM XRC SDK 4 9 3 User Guide Win32 Changes ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data List of changes For a detailed list of changes please refer to the file changes txt in the base directory of the SDK 26 ADM XRC SDK 4 9 3 User Guide Win32 Upgrades to the SDK ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Upgrades to the ADM XRC SDK From time to time newer versions of the SDK will become available on the Alpha Data FTP site at ftp ftp alpha data com in the pub admxrc windows directory Backwards source and binary compatibility will be maintained in the API whenever possible Alpha Data reserves the right to change the sample applications and FPGA designs as part of a policy of continual improvement 27 ADM XRC SDK 4 9 3 User Guide Win32 Sales and support ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data How to get support Alpha Data s FTP site containing resources for customers is ftp alpha data com Alpha Data technical personnel may be contacted by phone fax or e mail US Rest of World Phone 40
130. 0x3 gt rows 1 For example if ROWS 0x1 and COLS 0x1 then the number of column address bits is 13 3 10 7 6 BANKS RAN This field selects the number of bank address bits in the DDR SDRAM devices 0x0 gt no bank bits 1 internal bank 0x1 gt 1 bank bit 2 internal banks 0x2 gt 2 bank bits 4 internal banks 0x3 gt 3 bank bits 8 internal banks 9 8 PBANKS R W This field selects the number of chip select pins in the memory bank 0x0 gt 1 physical bank 0x1 gt 2 physical banks 0 2 gt 4 physical banks 0x3 gt 8 physical banks 31 10 MBZ DDR II SDRAM Bits Mnemonic Type Function 0 R W This field is reserved for implementing registered DDR I SDRAM support must be zero in this release of the SDK 1 MBZ This field is reserved for implementing X4 DDR II SDRAM device support must be zero in this release of the SDK 135 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 3 2 ROWS R W This field specifies the number of row address bits in the DDR II SDRAM devices 0 0 gt 12 bits 0x1 gt 13 bits 0x2 gt 14 bits 0x3 gt 15 bits 5 4 COLS R W This field specifies the number of column address bits in the DDR II SDRAM devices The number of column address bits depends on this field and also the ROWS field as follows 0x0 gt rows 4 0x1 gt rows 3 0x2 gt rows 2 0x3 gt rows 1 For example if ROWS 0x1 and COLS 0x1 then the number of column address bits is
131. 101 0110 0111 then there is no risk that client O s reads can be confused for client 1 s reads and vice versa ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 9 The validO valid1 and valid2 outputs are always asserted together by arbiter 3 If one of the validi signals is asserted then all must be asserted This is because it is the responsibility of each client to recognize its own tags The arbiter 3 module does not attempt to decode the qtag signal see below in order to determine which client issued the corresponding read command The following figure illustrates a read command issued by client 1 All validi signals are always asserted together With reference to the above figure client 1 issues the read and recognizes its own data by decoding qtag1 However clients 0 and 2 must also respectively decode qtag0 and qtag2 and determine that the data does not belong to them Depending on how many clients there are decoding a tag may be as simple as checking the top bit or top couple of bits of a qtagi value The interface presented to the shared memory port by the arbiter 3 module is as follows Signal Type Function Note a out Memory port logical address The arbiter 3 module drives this signal with a valid address when asserts ce in order to access the memory port on behalf of a client be out Memory port byte enables The arbiter 3 module drives this signal with a valid set of byte enables when it asserts ce and w togeth
132. 2 Copyright 2001 2009 Alpha Data Building the sample applications with MSVC The workspace apps apps dsw contains all of the sample applications In order to build all of the applications follow these Steps 1 Open the workspace apps apps dsw 2 Select Build gt Batch Build from the menu and click Build All This will build both the Debug and Release versions of the applications The executables for each application are found in the Debug and Release folders Normally one runs the Release version and by way of example the executables for the DMA application are located as follows Executable file Configuration apps dma debug dma exe MSVC Debug version apps dma release dma exe MSVC Release version 40 ADM XRC SDK 4 9 3 User Guide Win32 Borland command line tools ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Building the sample applications with Borland command line tools To build all of the sample applications Borland C command line users can change directory to the apps directory of the SDK and then invoke MAKE as follows make fmakefile bcc This will build the Borland versions of all the applications located in the Borland subdirectory For example the Borland compiled executable for the DMA application will be located as follows Executable file Configuration apps dma borland dma exe Borland C command line version 41 ADM XRC SDK 4 9 3 User Guide Win32
133. 2 After installation ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data After installation tasks After installation of the ADM XRC SDK in order to start developing applications you will need to configure your C compiler to use the API header files and libraries Configuring the MSVC IDE Configuring the Borland command line tools This release of the SDK does not provide Xilinx Project Navigator files because as of ISE 7 1i Xilinx adopted a binary file format that stores absolute pathnames However a script is provided that creates project files for all sample FPGA designs and this can be executed after installing the SDK For further information see Generating ISE Project Navigator files for sample FPGA designs 31 ADM XRC SDK 4 9 3 User Guide Win32 Configuring the MSVC IDE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Configuring the MSVC IDE In order to build applications using the ADM XRC SDK the compiler must be able to locate the API header file and the linker must be able to locate the appropriate version of the API library There are two ways to accomplish this with the Microsoft Visual C Integrated Development Environment MSVC IDE MSVC IDE global options MSCV IDE per project options 32 ADM XRC SDK 4 9 3 User Guide Win32 MSVC IDE global options ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Configuring the MSVC
134. 2 lt device gt projnav drc2 lt device gt projnav xpi lt device gt projnav xrc4lx lt device gt projnav xrc4sx lt device gt projnav xrc4fx lt device gt projnav xrce4fx lt device gt projnav xrc5 x lt device gt projnav xrc5t1 lt device gt projnav xrc5t2 lt device gt projnav xrc5tz lt device gt projnav xrc5tda1 lt device gt ADM XRC SDK 4 9 3 User Guide Win32 Simple Modelsim scripts Example Modelsim compatible script files for simulating this design are provided Refer to the following table for the appropriate command line for a particular model Model Shell command ADM XRC vsim do do simple do ADM XRC P vsim do do simple do ADM XRC II Lite vsim do do simple do ADM XRC II vsim do do simple do ADM XPL vsim do do simple xpl do ADM XP vsim do do simple xpl do ADP WRC II vsim do do simple wrc2 do ADP DRC II vsim do do simple wrc2 do ADP XPI vsim do do simple xpi do ADM XRC 4LX vsim do do simple xrc4lIx do ADM XRC 4SX vsim do do simple xrc4lIx do ADM XRC 4FX vsim do do simple xrc4fx do ADPE XRC 4FX vsim do do simple xrce4fx do ADM XRC 5LX vsim do do simple xpl do ADM XRC 5T1 vsim do do simple xpl do ADM XRC 5T2 vsim do do simple xpl do ADM XRC 5T2 ADV ADM XRC 5TZ vsim do do simple xpl do ADM XRC 5T DA1 155 vsim do do simple xpl do ADM XRC SDK 4 9 3 User Guide Win32 Simple64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha
135. 2 interface The latter two ADM XRC SDK 4 9 3 User Guide Win32 Differences between ADMXRC2 and ADMXRC interfaces structures offer an increased level of abstraction of hardware features The virtual address of the FPGA space must now be obtained using ADMXRC2 GetSpacelnfo e ADMXRC2 SetClockRate function differs from ADMXRC SetClockRate in two ways 1 The Clock parameter is now an integer as opposed to a member of an enumerated type The value 0 always represents the local bus clock 2 A parameter Actual has been added which can return the actual clock frequency programmed 425 ADM XRC SDK 4 9 3 User Guide Win32 Functions ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 interface functions The ADMXRC2 interface can be divided into the following function groups Group Consists of Initialization ADMXRC2 CloseCard ADMXRC2 OpenCard ADMXRC2_OpenCardByIndex ADMXRC2 SetSpaceConfig Information ADMXRC2 GetBanklnfo ADMXRC2 GetCardlnfo ADMXRC2 GetSpaceConfig ADMXRC2 GetSpacelnfo ADMXRC2_GetVersionInfo FPGA configuration ADMXRC2_ConfigureFromBuffer ADMXRC2_ConfigureFromBufferDMA ADMXRC2_ConfigureFromFile ADMXRC2 ConfigureFromFileDMA ADMXRC2 LoadBitstream ADMXRC2 UnloadBitstream Clock generation ADMXRC2 SetClockRate Data transfer ADMXRC2 BuildDMAModeWord ADMXRC2 DoDMA ADMXRC2 DoDMAlmmediate ADMXRC2 MapbDirectMaster ADMXRC2 Read ADMXRC2 ReadConfig ADMXRC2 SetupDMA ADMXRC2
136. 2 v2 scr frontio xrc2 v2 prj frontio xrc2 ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC I Lite projnavrc2l device ADM XRC II projnav xrc2 lt device gt 178 ADM XRC SDK 4 9 3 User Guide Win32 ITest ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ITest sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga verilog itest Synopsis The ITest FPGA design implements logic for generating FPGA interrupts on the host The scheme used is explained in application note AN XRCO6 which can be found the doc directory of this SDK The ITest sample application shows how to capture and handle FPGA interrupts on the host 179 ADM XRC SDK 4 9 3 User Guide Win32 ITest FPGA Space Usage The design implements several registers for generating and acknowledging interrupts Interrupt Mask register IMASK local bus address 0x0 Bits Mnemonic Type Function 31 0 MASK R W Bit vector that unmasks
137. 2sram dq in vhd fpga vhdl common memit ddr2sram v4 ddr2sram dq out vhd fpga vhdl common memif ddr2sram v4 ddr2sram training vhd fpga vhdl common memif ddr2sram v4 ddr2sram port v4 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the port logical address a 4 d width natural Width in bits of the port data in and out d and q 3 respectively pinout ddr2sram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants ra width natural Width in bits of the memory device address bus ra 1 rc width natural Width in bits of the memory device control bus rc 2 rd width natural Width in bits of the memory device data bus rd 3 tag width natural Width in bits of the tag in and out tag and qtag respectively Notes 1 The ra width parameter is a property of the printed circuit board indicating how many wires are physically present rather than indicating how many of the ra lines are used by a particular DDR II SSRAM device 2 The memory device control bus rc is composed of various fields in this memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates the fields that comprise t
138. 3 User Guide Win32 ADMXRC2 FPGA TYPE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 FPGA TYPE Declaration typedef enum ADMXRC2 FPGA TYPE ADMXRC2 FPGA RESVDO 0 ADMXRC2_FPGA_RESVD1 e ds ADMXRC2 FPGA RESVD2 Emu ADMXRC2 FPGA RESVD3 EU ADMXRC2 FPGA V1000 ADMXRC2_FPGA_V400 5 ADMXRC2_FPGA_V600 6 ADMXRC2_FPGA_V800 S75 ADMXRC2_FPGA_V2000E zi ADMXRC2 FPGA V1000E 9 ADMXRC2 FPGA V1600E ADMXRC2 FPGA V3200E 211 ADMXRC2 FPGA V812E D ADMXRC2_FPGA_V405E EE ADMXRC2 FPGA RESVD14 14 ADMXRC2 FPGA RESVD15 25 ADMXRC2 FPGA RESVD16 16 ADMXRC2 FPGA RESVD17 17 ADMXRC2 FPGA RESVD18 2 18 ADMXRC2 FPGA RESVD19 19 ADMXRC2 FPGA RESVD20 20 ADMXRC2 FPGA RESVD21 21 ADMXRC2_FPGA_RESVD22 20 ADMXRC2 FPGA RESVD23 223 ADMXRC2 FPGA RESVD24 24 ADMXRC2 FPGA RESVD25 25 ADMXRC2 FPGA RESVD26 26 ADMXRC2 FPGA RESVD27 27 ADMXRC2 FPGA RESVD28 28 ADMXRC2 FPGA RESVD29 29 ADMXRC2 FPGA RESVD30 2305 ADMXRC2 FPGA RESVD31 31 ADMXRC2_FPGA_2V1000 323 ADMXRC2_FPGA_2V1500 33 ADMXRC2_FPGA_2V2000 34 ADMXRC2_FPGA_2V3000 E35 ADMXRC2 FPGA 2V4000 36 ADMXRC2 FPGA 2V6000 7 ADMXRC2 FPGA 2V8000 38 ADMXRC2 FPGA 2V10000 39 ADMXRC2_FPGA_RESVD40 40 ADMXRC2_FPGA_RESVD41 Al ADMXRC2_FPGA_RESVD42 Bu ADMXRC2 FPGA RESVD43 43 ADMXRC2_FPGA_RESVD44 44 ADMXRC2_FPGA_RESVD45 45 492 ADM XRC SDK 4 9 3 User Guide W
139. 8 916 5713 44 131 558 2600 Fax 408 436 5524 44 131 558 2700 E mail support alpha data com support alpha data com Web www alpha data com www alpha data com 28 ADM XRC SDK 4 9 3 User Guide Win32 Installation ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Installation Please choose one of the following topics Before installation After installation 29 ADM XRC SDK 4 9 3 User Guide Win32 Before installation ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Before installation Beginning with release 4 5 1 the ADM XRC SDK for Windows package installs by default to a folder that contains the release number The default installation folder for this release is sSystemDrive ADMXRC_SDK4 9 3 In many cases SysitemDrive simply equates to C Since the SDK release number forms a part of the name of the installation folder it is possible to keep several versions of the SDK on one system A folder at the root of the system drive is chosen rather than a folder such as Program Files because as of writing some of the Xilinx ISE tools do not permit spaces in filenames It is not necessary to install the ADM XRC driver before installing the SDK although it will not be possible to run any applications until you have done so The recommended ADM XRC driver version for this version of the SDK is 3 16 or later After installation 30 ADM XRC SDK 4 9 3 User Guide Win3
140. ADM XRC SDK User Guide family t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The family t datatype The family t datatype is used to symbolically represent a particular Xilinx FPGA family and is defined as follows type family t is family virtex Virtex Virtex E Virtex EM family virtex2 Virtex II family virtex2p Virtex II Pro family virtex4 Virtex 4 family virtex5 Virtex 5 ADM XRC SDK User Guide Common Memory Ports ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sram port component Overview HDL source code Parameters Signals Performance Overview The ddr2sram port component is part of the memif package and implements an interface to a bank of DDR II SSRAM memory This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure ala width 1 0 toram w width 1 0 tag tag width 1 0 refre width 1 0 memory beld width 8 1 0D width 1 0 device s d d width 1 0 burst len dil atf ed with 1 0 qtag tag_ wrth 1 0 valid ready dearzsram port ADM XRC SDK User Guide Common Memory Ports HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation
141. ADMXRC SyncDirectMaster ADMXRC HANDLE Card ADMXRC DMADESC DMADesc unsigned long Offset unsigned long Length DWORD Syncmode Arguments Argument Type Purpose Card In Handle of card DMADesc In A DMA descriptor identifying a buffer Offset In Offset of region within buffer to sync Length In Region within buffer to sync Mode In The kind of synchronisation to perform Return value Value Meaning ADMXRC SUCCESS The buffer region was successfully synchronized ADMXRC INVALID HANDLE Card was not valid ADMXRC INVALID DMADESC DMADesc was not a valid DMA descriptor ADMXRC INVALID PARAMETER Mode was not valid or Offset and Length were out of bounds Description The ADMXRC SyncDirectMaster function serves the purpose of ensuring that coherency is maintained in hardware level buffers and caches when the FPGA accesses host memory in direct master mode Proper use of this function ensures that e data written to memory by the CPU has propagated through all caches write buffers and bridges so that the changes are visible to the FPGA and e data written to memory by the FPGA using Direct Master access has propagated through all caches write buffers and bridges so that the changes are visible to the CPU In practice this means observing the following rules e Call ADMXRC SyncDirectMaster specifying ADMXRC SYNC CPUTOFPGA for Mode after the CPU has set up an application buffer and before signalling the FPGA to operate on the buffer
142. ANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure Buffer In Pointer to application buffer Length In Number of bytes to transfer Local In Address of beginning of transfer on local bus Direction In Direction of DMA transfer Channel In DMA channel to use for the transfer DMAModeWord In Mode word to use for the DMA transfer Flags In Miscellaneous flags Timeout In out Timeout for DMA transfer Event In out Event to use to wait for completion Return value Value Meaning ADMXRC_SUCCESS The DMA transfer was performed successfully ADMXRC INVALID HANDLE Card is not a valid handle to a card ADMXRC INVALID PARAMETER An invalid parameter was passed ADMXRC DEVICE BUSY Could not begin DMA immediately as requested ADMXRC NO DMADESC A DMA descriptor could not be allocated Description This function behaves as a call to ADMXRC_SetupDMA followed by a call to ADMXRC DoDMA followed by a call to ADMXRC UnsetupDMA 517 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DoDMAImmediate The Buffer and Length parameters effectively replace the DmaDesc Offset and Length parameters from ADMXRC_DoDMA in specifying the region of application memory over which the DMA transfer takes place The other parameters Local Direction Channel DMAModeWord Flags Timeout and Event all function in the same way as in ADMXRC DoDMA This function cannot guarantee deterministic runtime as the process of locking down a user buffer using ADMXRC_SetupD
143. ANY to be delayed indefinitely if all DMA channels are kept busy by other threads The Event parameter should be a valid manual reset Win32 event handle See multithreading issues for further information 432 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ConfigureFromFile ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 ConfigureFromFile Prototype ADMXRC2 STATUS ADMXRC2 ConfigureFromFile ADMXRC2 HANDLE Card const char Filename Arguments Argument Type Purpose Card In Handle of card to configure Filename In Name of BIT file Return value Value Meaning ADMXRC2 SUCCESS The FPGA was successfully configured ADMXRC2 FILE NOT FOUND The file Filename could not be opened ADMXRC2 INVALID FILE The file Filename appears not to be a valid bitstream ADMXRC2 NO MEMORY There is not enough free memory to temporarily load the bitstream into memory ADMXRC2 FPGA MISMATCH The device targetted by the bitstream file did not match the device fitted to the card ADMXRC2 INVALID HANDLE is not a valid handle to a card Description This function is used to configure the FPGA on a card from a Xilinx bitstream file BIT using programmed I O If deterministic runtime is required the ADMXRC2 ConfigureFromBuffer or ADMXRC2 ConfigureFromBufferDMA functions should be used instead since ADMXRC2 ConfigureFromFile performs file I O in order to load the bitstream into memory The card to be configured is
144. ATOCPU ADMXRC2 SYNCMCDE Ox1 0x2 Description The ADMXRC2 SYNCMODE type is used with the ADMXRC2 SyncDirectMaster function to specify the direction in which changes made to a buffer must be propagated across any hardware level caches or write buffers Value Meaning ADMXRC2 SYNC CPUTOFPGA Indicates that the CPU has modified a buffer that the FPGA is expected to access ADMXRC2 SYNC FPGATOCPU Indicates that the FPGA has modified a buffer that the CPU is expected to access 503 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC legacy interface ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC legacy interface The ADMXRC interface is included in the SDK for backwards compatibility with older applications It is not recommended for new applications This interface has been depreciated because it contains implicit assumptions specific to the ADM XRC and ADM XRC P models which do not hold for other models Calls to the ADMXRC interface must not be mixed with calls to the ADMXRC2 interface interface using the same card handle A card handle obtained using the legacy ADMXRC_OpenCard function should not be used in any calls to the ADMXRC2 interface Applications should assume that the API will enforce this rule Only ADM XRC or ADM XRC P cards may be opened by ADMXRC OpencCard This is a safeguard to allow applications designed for the ADM XRC or ADM XRC P cards to fail gracefully in the event for exa
145. BE 3 0 There are a couple of things to note about the above example 1 The primary address decoding causes the plxdssm module to ignore local bus cycles for which the FPGA is not the target This generally requires only the simplest of address decoders and an expression such as glads lt not lads 1 and not fholda and not 1 23 often suffices 2 The control logic for generating the ready and stop inputs to the plxdssm module may be as simple as tying one or both of these two signals high ready can be tied to a static logic 1 if the FPGA never need insert any waitstates and stop can be tied to a static logic 1 if the FPGA must always prevent bursting during local bus cycles However in a nontrivial FPGA design the generation of ready and stop might depend upon the latched local bus address current FIFO levels current operating mode etc 278 ADM XRC SDK 4 9 3 User Guide Win32 Memory interface package VHDL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The memif package Overview of this package Components Datatypes Constants Generic memory port user interface Overview The memif package consists of a number of components providing memory ports for several types of memory device The purpose of the memif package is twofold 1 To hide any complexity present in a given memory type from the user application so that the user application may treat it as a array of randomly accessible memo
146. Bank 02 RAM Bank 03 RAM Bank 04 RAM Bank 05 4 14 3 14 ADM XP 115 0x0073 115 0x00000073 2 0 1 5 Virtex II Pro 2VP100 1 2 2 0xDA400000 0x00000000 Ox003FFFFF OxOOCFFFFF 0x00900000 0xD9400000 0x00800000 0x00D00000 6 0x0000003F DDR II SRAM 256kword DDR II SRAM 256kword DDR II SRAM 256kword DDR II SRAM 256kword FF1704 OxOOBFFFFF OxOl10FFFFF x x x x 64bits 64bits 64bits 64bits DDR SDRAM 8192kword x 64bits DDR SDRAM 8192kword x 64bits 65536kB 65536kB 2048kB 2048kB 2048kB 2048kB ADM XRC SDK 4 9 3 User Guide Win32 ITest ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ITest sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview The ITest sample application demonstrates how to handle interrupts from the FPGA in at application level Syntax itest options Options Option Argument type Meaning card base 10 integer ID of card to open index base 10 integer Index of card to open Description On startup the ITest sample application performs the following steps 59 ADM XRC SDK 4 9 3 User Guide Win32 ITest 1 A Win32 event is created and registere
147. C 5T DA1 DDR II SDRAM bank Pinout for an ADM XPL DDR SDRAM bank Pinout for an ADM XP DDR SDRAM bank Pinout for an ADM XP DDR II SSRAM bank Pinout for an ADM XRC 5T1 DDR II SSRAM bank Pinout for an ADM XRC 5T2 ADM XRC 5T2 ADV DDR I SSRAM bank Pinout for an ADM XRC 5T DA1 DDR II SSRAM bank Pinout for an ADM XRC ZBT SSRAM bank Pinout for an ADM XRC P ZBT SSRAM bank Pinout for an ADM XRC II Lite ZBT SSRAM bank Pinout for an ADM XRC II ZBT SSRAM bank Pinout for an ADM XPL ZBT SSRAM bank Pinout for an ADM XRC 4LX ZBT SSRAM bank ADM XRC SDK 4 9 3 User Guide Win32 Memory interface package VHDL zbtsram pinout admxrc4sx zbtsram pinout t zbtsram pinout admxrcbtz zbtsram pinout t ddr2sdram timing 266 ddr2sdram timing t ddrsdram timing cl25 133 ddrsdram timing t Generic user interface In general the memory ports can be represented as a black box as in the following figure to from User application Pinout for an ADM XRC 4SX ZBT SSRAM bank Pinout for an ADM XRC 5TZ ZBT SSRAM bank Timing for a generic 266MHz DDR II SDRAM device also known as DDR533 This corresponds to a clkO frequency of 133MHz Timing for a generic CL2 5 133MHz DDR SDRAM device also known as DDR266 or PC2100 This corresponds to a clkO frequency of 133MHz ra ra width 1 0 rdrc width 1 0 rd rd width 1 0 idth 1 0 vy width 1 0 be d widt
148. C SDK 4 9 3 User Guide Win32 ADMXRC2 IOWIDTH ADM XRC 5T1 no no yes yes ADM XRC 5T2 no no yes yes ADM XRC 5T2 ADV no no yes yes ADM XRC 5TZ no no yes no ADM XRC 5T DA1 no no yes no For performance reasons use ADMXRC2 IOWIDTH 32 or ADMXRC2 IOWIDTH 64 wherever possible when using DMA transfers 500 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 STATUS ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 STATUS Declaration typedef enum ADMXRC2 STATUS 501 ADMX ADMX ADMX ADMX ADMX ADMX RC2 INVA RC2 CLOSI RC2 NOT SUPPORTI RC2 SUCCESS RC2 INTERNAL ERRO RC2 NO MEMORY RC2 CARD NOT FOUN RC2 FILE NOT FOUN RC2 INVALID FILE RC2 INVALID HANDILI RC2 TIMEOUT RC2 CARD BUSY PARAM GI D RC2_CARD_ERROR Gl RC2 DEVICE BUSY RC2 INVALID DMADE RC2 NO DMADESC RC2 FAIL ED RC2 PENDING RC2 UNKNOWN ERROR 0 R 0x1000 D D RC2 FPGA MISMATCH FJ ETER JK 7 8 A ps No error An error in the API logic occurred Couldn t allocate memory required to complete operation Failed to open the card with specified CardID Failed to open bitstream file 5 i on the card Ihe handle to the card passed
149. C2 NO MEMORY There was insufficient free memory to load the bitstream ADMXRC2 FPGA MISMATCH The device targetted by the bitstream file did not match the device fitted to the card ADMXRC2 INVALID HANDLE Card is not a valid handle to a card Description This function loads the SelectMap data from a Xilinx bitstream BIT file into memory and returns a pointer to it The data returned is in correct bit order for sending to an FPGA s SelectMap port The Card parameter specifies the card that the bitstream targets This information is used to check that the bitstream matches the FPGA fitted to the card The bitstream file to load into memory is specified by the Filename parameter The Image parameter must point to a variable of type ADMXRC2 IMAGE A pointer to the buffer that contains the loaded SelectMap data allocated by ADMXRC2 LoadBitstream is returned The ADMXRC2 UnloadBitstream function should be used to free the memory used by the SelectMap data when no longer required 449 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 LoadBitstream The ImageSize parameter must point to an unsigned long variable which receives the length of the SelectMap data 450 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 MapbDirectMaster ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 MapbDirectMaster Prototype ADMXRC2 STATUS ADMXRC2 MapDirectMaster ADMXRC2 HANDLE Card ADMXRC2 DMADESC Buffer u
150. C2_DoDMA and ADMXRC2_DoDMAImmediate returns the host can inspect this register to determine how much data was transferred What happens to any data that might be remaining ina DMA engine s FIFOs when the DMA transfer is terminated using LEOT This depends upon the direction of the DMA transfer e If the direction of the DMA transfer is PCl to local there may be data remaining the inbound DMA FIFO for that DMA channel This data is discarded e If the direction of the DMA transfer is local to PCl then all of the data that has been read on the local bus up to and including the final burst in which LEOT is asserted is guaranteed to be written on the PCI bus When a DMA transfer whose direction is PCI to local bus is terminated using LEOT there may be data remaining the inbound DMA FIFO for that DMA channel This data is discarded To use LEOT mode e The host must specify ADMXRC2 DMAMODE USEEOT in a call to ADMXRC2 BuildDMAModeWord The mode word that includes LEOT mode can then be supplied in a call to ADMXRC2 DoDMA and ADMXRC2_DoDMAImmediate e The FPGA design must drive the LEOT signal and assert it at the appropriate moment during a local bus burst If LEOTE is asserted during a non DMA burst or when LEOT mode has not been specified by the host it will have no effect This following topics illustrate the local bus protocol when LEOT mode is used LEOT Z not bursting LEOT bursting 250 ADM XRC SDK 4 9 3 User Guide W
151. CAL Local bus address does not increment ADMXRC DMAMODE DEMAND Operate in demand mode 507 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC CloseCard ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC CloseCard Prototype ADMXRC STATUS ADMXRC CloseCard ADMXRC HANDLE Card Arguments Argument Type Purpose Card In Handle to card to be closed Return value Value Meaning ADMXRC SUCCESS The card was successfully closed ADMXRC INVALID HANDLE Card is not a valid handle to a card Description This function closes a handle to a card freeing the card for use by other applications Card must be a valid handle returned by ADMXRC_OpenCard 508 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ConfigureFromBuffer ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC ConfigureFromBuffer Prototype ADMXRC STATUS ADMXRC ConfigureFromBuffer ADMXRC HANDLE Card void Buffer DWORD Length Arguments Argument Type Purpose Card In Handle of card to configure Buffer In FPGA configuration data Length In Length of FPGA configuration data Return value Value Meaning ADMXRC SUCCESS The FPGA was successfully configured ADMXRC INVALID HANDLE Card is not a valid handle to a card ADMXRC INVALID PARAMETER An invalid parameter was passed Description This function is used to configure the FPGA on a card from a buffer of SelectMap data using programmed I O Since there is no
152. CE BURST DEFAULT The model specific default burst behaviour is requested corresponds to one of the other ADMXRC2 SPACE BURST XXX flags depending on the model ADMXRC2 SPACE BURST DISABLED Non bursting single word transfer behaviour is requested ADMXRC2 SPACE BURST ENABLED Bursting multiword transfer behaviour is requested 464 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SetupDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 SetupDMA Prototype ADMXRC2 STATUS ADMXRC2 SetupDMA ADMXRC2 HANDLE Card const void Buffer unsigned long Size DWORD Flags ADMXRC2 DMADESC DMADesc Arguments Argument Type Purpose Card In Handle of card Buffer In The application buffer to lock down Size In The size of the application buffer Flags In Miscellaneous flags DMADesc Out The DMA descriptor returned Return value Value Meaning ADMXRC2 SUCCESS The application buffer was successfully locked down and a DMA descriptor returned ADMXRC2 INVALID HANDLE The Card handle was not valid ADMXRC2 INVALID PARAMETER Flags was not valid ADMXRC2 NO DMADESC All DMA descriptors were in use Description This function locks down and maps an application buffer returning a descriptor which can subsequently be used to identify the buffer to the DMA API functions such as ADMXRC2 DoDMA and ADMXRC2 DoDMAlmmediate The Buffer parameter must point to the application buffer to be mapped The Size paramet
153. CLK 2 LCLK Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose Local bus clock General purpose ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_SetSpaceConfig ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2_SetSpaceConfig Prototype ADMXRC2_STATUS ADMXRC2_SetSpaceConfig ADMXRC2_HANDLE Card unsigned int SpaceIndex DWORD Flags Arguments Argument Type Purpose Card In Handle of card Spacelndex In The index of the space to be configured Flags In Flags specifying configuration Return value Value Meaning ADMXRC2 SUCCESS The space was successfully configured ADMXRC2 INVALID HANDLE The Card handle was not valid ADMXRC2 INVALID PARAMETER Flags did not consist entirely of valid flags ADMXRC2 NOT SUPPORTED An invalid space was specified via Spacelndex or the requested configuration specified via Flags is not supported on the card Description This function configures a local bus space The Spacelndex parameter is a zero based index that specifies the local bus space to configure The Flags parameter specifies the desired configuration for the local bus space and should be constructed by bitwise ORing together flags from the following table
154. DM XRC 5T DA1 Modelsim scripts projnav xpi lt device gt projnav xrc4lx lt device gt projnav xrc4sx lt device gt projnav xrc4fx lt device gt projnav xrce4fx lt device gt projnav xrce4fx lt device gt projnav xrc5 x lt device gt projnav xrc5t1 lt device gt projnav xrc5t2 lt device gt projnav xrc5tz lt device gt projnav xrc5tda1 lt device gt Example Modelsim compatible script files for simulating this design are provided appropriate command line for a particular model Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 105 Shell command vsim do do itest do vsim do do itest do vsim do do itest do vsim do do itest do vsim do do itest xpl do vsim do do itest xpl do vsim do do itest wrc2 do vsim do do itest wrc2 do vsim do do itest xpi do vsim do do itest xrc4lx do vsim do do itest xrc4lx do vsim do do itest xrc4fx do vsim do do itest xrce4fx do vsim do do itest xpl do vsim do do itest xpl do vsim do do itest xpl do vsim do do itest xpl do vsim do do itest xpl do Refer to the following table for the ADM XRC SDK 4 9 3 User Guide Win32 Master ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Master sample VHDL FPGA design
155. DMA is to be performed a value of the enumerated type ADMXRC2 BOARD TYPE The Width parameter should be one value of the enumerated type ADMXRC2 IOWIDTH The WaitStates parameter should be in the inclusive range 0 to 15 for the ADM XRC ADM XRC P ADM XRC II Lite ADM XRC Il ADP WRC Il ADP DRC Il ADM XRC 4LX and ADM XRC 4SX cards For other cards it must be 0 For portability reasons Alpha Data recommends always specifying 0 for WaitStates and designing local bus interface logic into the FPGA that uses the LREADY and or LBTERM signals to implement a waitstate mechanism The MiscFlags parameter can be any combination of 427 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BuildDMAModeWord Flag ADMXRC2 DMAMODE USEREADY ADMXRC2 DMAMODE USEBTERM ADMXRC2 DMAMODE BURSTENABLE ADMXRC2 DMAMODE FIXEDLOCAL ADMXRC2 DMAMODE DEMAND ADMXRC2 DMAMODE USEEOT 428 Meaning Use local bus READYI signal Use local bus BTERM signal Allow bursting on local bus Operate in constant address mode Operate in demand mode Operate in LEOT mode ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 CloseCard ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 CloseCard Prototype ADMXRC2 STATUS ADMXRC2 CloseCard ADMXRC2 HANDLE Card Arguments Argument Type Purpose Card In Handle to card to be closed Return value Value Meaning ADMXRC2 SUCCESS The card was successfully closed ADMXRC2 INVALID HANDL
156. DMADESC DMADesc Arguments Argument Type Purpose Card In Handle of card DMADesc In The DMA descriptor to free Return value Value Meaning ADMXRC2 SUCCESS The DMA descriptor was successfully freed ADMXRC2 INVALID HANDLE Card was not a valid handle to card ADMXRC2 INVALID DMADESC DMADesc was not a valid DMA descriptor Description This function undoes a call to ADMXRC2 SetupDMA When a DMA descriptor is no longer required it should be freed using ADMXRC2 UnsetupDMA Provided that no other DMA descriptors exist for the buffer the application buffer associated with the DMA descriptor is returned to an unlocked swappable state The DMADesc parameter specifies the DMA descriptor to free 472 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 Write ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 Write Prototype ADMXRC2 STATUS ADMXRC2 Write ADMXRC2 HANDLE Card ADMXRC2 IOWIDTH Width DWORD Flags DWORD Local const void Buffer unsigned long Length Arguments Argument Type Purpose Card In Handle of card on which the write is to take place Width In Width of operation Flags In Miscellaneous flags Local In Local bus address at which to begin writing Buffer In Buffer containing data to write Length In Number of bytes to write Return value Value Meaning ADMXRC2 SUCCESS The data was written successfully ADMXRC2 INVALID HANDLE Card is not a valid handle to a card A
157. DMXRC StatusToString 506 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC BuildDMAModeWord ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC BuildDMAModeWord Prototype DWORD ADMXRC BuildDMAModeWord DWORD Width DWORD WaitStates DWORD MiscFlags Arguments Argument Type Purpose Width In Width of operation on local bus WaitStates In Number of wait states to be introduced by PCI9080 MiscFlags In Miscellaneous mode flags Return value If the parameters are valid a DMA mode word is returned If the parameters supplied are not valid the invalid mode word OxFFFFFFFF is returned Description This function differs from most API functions in that no card handle parameter is required and the return value is not of type ADMXRC STATUS ADMXRC BuildDMAModeWord constructs a DWORD value that may later be passed to the DMA functions such as ADMXRC DoDMA and ADMXRC DoDMAlmmediate Provided that the DMA mode does not need to be changed the DMA mode word can be pre computed and used for many DMA transfers The Width parameter should be one value of the enumerated type ADMXRC DMA WIDTH The WaitStates parameter should be in the inclusive range 0 to 15 The MiscFlags parameter can be any combination of Flag Meaning ADMXRC_DMAMODE_USEREADY Use local bus READYI signal ADMXRC DMAMODE USEBTERM Use local bus BTERME signal ADMXRC DMAMODE BURSTENABLE Allow bursting on local bus ADMXRC DMAMODE FIXEDLO
158. DMXRC2 INVALID PARAMETER An invalid parameter was passed Description The ADMXRC2 Write function writes a number of bytes from an application buffer to the local bus using direct slave cycles or to the PLX registers The local bus space encompasses FPGA space the FPGA flash memory and the control registers The Width parameter specifies the width of the operation and must be one of the values from the enumerated type ADMXRC2 IOWIDTH The Flags parameter modifies the semantics of the operation Normally the write is performed to local bus space with an incrementing address but this behavior can be modified by any combination of the following Flag Meaning ADMXRC2 IOFIXED The local bus address is not incremented during the transfer 473 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 Write ADMXRC2 IOADAPTER The read is performed from the card s PCI interface registers rather than the local bus If the ADMXRC2 IOADAPTER flag is not specified the Local parameter specifies the starting local bus address to which the data will be written Otherwise the Local parameter specifies the starting adapter register PCI9080 PCI9656 offset to which the data will be written If the ADMXRC2 IOFIXED flag was specified this address will not increment as the data is written Otherwise the address is incremented as the data is written The Buffer parameter specifies the buffer containing the data to be written The Length parameter specifies how many
159. DPE XRC 4FX FF1517 ADM XRC 5LX FF1153 ADM XRC 5T1 FF1136 ADM XRC 5T2 FF1738 ADM XRC 5T2 ADV FF1738 ADM XRC 5T DA1 FF1136 The FPGAType member of the enumerated type ADMXRC2 FPGA TYPE identifies the type of FPGA fitted to the card To be precise it identifies the FPGA family and size but not the package The NumClock member is the number of programmable clock generators available on the card The NumDMAChan member is the number of DMA channels provided by the card The NumRAMBank member is the number of RAM banks on the card whether fitted or not This value is obtained by reading the EEPROM on the card This value can be also be implied from the model The NumSpace member is the regions of local bus space that the card provides The RAMBanksFitted is a bitmap indicating which RAM banks are fitted on the card A 1 bit indicates fitted and a 0 bit indicates not fitted RAMBanksFitted n corresponds to bank n This value is obtained by reading the EEPROM on the card The BoardRevision member is the revision of the board as a two digit number OxAB where A is the major revision and B is the minor revision The LogicRevision member is the revision of the control logic on the board as a two digit number OxAB where A is the major revision and B is the minor revision Although the number of clock generators the number of RAM banks and the number of spaces provided by a card can be obtained from the NumClock and NumRAMBank they can als
160. DR II SSRAM device to be a burst length 2 or 4 device Reserved When this field is 0 the memory port enables the DLL delay locked loop within the DDR II SDRAM device this is the normal mode of operation When this field is 1 the memory port disables the DLL not recommended Reserved Function When this field is 0 the memory port expects the DDR SDRAM to be unregistered When this field is 1 the memory port expects the DDR SDRAM to be registered ADM XRC SDK 4 9 3 User Guide Win32 Memory 1 MBZ Reserved for implementing X4 DDR SDRAM device support must be zero in this release of the SDK 3 2 ROWS R W This field specifies the number of row address bits in the DDR SDRAM devices 0 0 gt 12 bits 0x1 gt 13 bits 0 2 gt 14 bits 0x3 gt 15 bits 5 4 COLS R W This field specifies the number of column address bits in the DDR SDRAM devices The number of column address bits depends on this field and also the ROWS field as follows 0x0 gt rows 4 0x1 gt rows 3 0x2 gt rows 2 0x3 gt rows 1 For example if ROWS 0x1 and COLS 0x1 then the number of column address bits is 13 3 10 7 6 BANKS RAN This field selects the number of bank address bits in the DDR SDRAM devices 0x0 gt no bank bits 1 internal bank 0x1 gt 1 bank bit 2 internal banks 0 2 gt 2 bank bits 4 internal banks 0x3 gt 3 bank bits 8 internal banks 9 8 PBANKS R W This field selects the n
161. Data support 204 ADM XRC SDK 4 9 3 User Guide Win32 Synplify Synplify Pro issues ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Synplify Synplify Pro issues There are several issues that affect users of Synplify Synplify Pro when rebuilding the example FPGA designs in the SDK 1 Bus nomenclature in netlist XST names busses as signal lt n gt whereas Synplify names busses by default as signal n This causes ngdbuild to fail if the UCF files supplied with the SDK are used Users of Synplify Synplify Pro include the file synpro bus sdoc in the directory ADMXRC_SDK4 vhdl common in their projects to make Synplify Synplify Pro use a signal lt n gt nomenclature 2 Hierarchical separator character XST uses the _ underscore character as a hierarchy separator whereas Synplify Synplify Pro uses a forward slash character It is possible to work around this problem as far as constraints in UCF files go by using the wildcard match any single character in the UCF file 3 Hierarchical net naming in netlist XST names nets that are not at the top level differently to Synplify Synplify Pro A full description of the XST naming convention can be found in the XST user guide Synplify Pro names net strictly according to their name and the highest hierarchy level in which that net is found Fortunately it is often possible to avoid needing to reference nets that are not in the top level in a UCF file
162. E Card is not a valid handle to a card Description This function closes a handle to a card freeing the card for use by other applications Card must be a valid handle returned by ADMXRC2 OpencCard 429 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ConfigureFromBuffer ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 ConfigureFromBuffer Prototype ADMXRC2 STATUS ADMXRC2 ConfigureFromBuffer ADMXRC2 HANDLE Card const void Buffer unsigned long Length Arguments Argument Type Purpose Card In Handle of card to configure Buffer In FPGA configuration data Length In Length of FPGA configuration data Return value Value Meaning ADMXRC2 SUCCESS The FPGA was successfully configured ADMXRC2 INVALID HANDLE Card is not a valid handle to a card ADMXRC2 INVALID PARAMETER An invalid parameter was passed Description This function is used to configure the FPGA on a card from a buffer of SelectMap data using programmed I O Since there is no file I O to be performed this is a deterministic method of configuring the FPGA This routine does not allow the FPGA to be partially configured on each call all of the data necessary to configure the FPGA must be supplied in a single call Warning Ensure that Buffer contains valid configuration data for the target FPGA as data transferred this way to the FPGA s SelectMap port cannot be validated by the API The card to be configured is specified by
163. FFF 0x34 OxFFFFFFFF 0x15 OxFFFFFFFF 0x35 OxFFFFFFFF 0x16 OxFFFFFFFF 0x36 OxFFFFFFFF 0x17 OxFFFFFFFF 0x37 OxFFFFFFFF 0x18 OxFFFFFFFF 0x38 OxFFFFFFFF 0x19 OxFFFFFFFF 0x39 OxFFFFFFFF Ox1A OxFFFFFFFF OxFFFFFFFF Ox1B OxFFFFFFFF Ox3B OxFFFFFFFF Ox1C OxFFFFFFFF 0 3 OxFFFFFFFF 0 1 OxFFFFFFFF Ox3D OxFFFFFFFF OxlE OxFFFFFFFF Ox3E OxFFFFFFFF OxlF OxFFFFFFFF Ox3F OxFFFFFFFF 51 ADM XRC SDK 4 9 3 User Guide Win32 EPTest 52 Running EPTest this way is unconditionally safe and does not modify any of the configuration data The second way to run EPTest is to read a specific location by specifying the location to read as the first argument For example the command line eptest 0 4 will display the following assuming the same card is used as above Selected card ID is 109 0x6d 0x4 0x0bebc200 This is also unconditionally safe because it does not modify any of the configuration data The third way to run EPTest is to write a specific location specifying the location to write as the first argument and the data as the second argument eptest OxA 0x00150015 The above command modifies the word whose index is OxA whose value is 0x00140014 according to the above example to have the new value 0x00150015 This form of the command line is NOT unconditionally safe and should be used only when the expected result is known and understood
164. FPGA family that the memory port targets has c boolean If true the rc bus of the memory port includes the C C pins has cq boolean If true the rc bus of the memory port includes the CQ CQ pins capture 180 boolean If true the memory port uses the clk180 clock phase to capture DQ for reads If false the memory port uses the clk90 The value of ddr2sram pinout t passed in the pinout parameter of a ddr2sram port determines the proper value to pass for the rc width parameter The relevant formula is A rd width 8 B 2 if has_c else 0 C 2 if has_cq else 0 rc_widh A B C 5 290 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram timing t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddrsdram timing t datatype The ddrsdram timing t datatype is exported by the memif package and is used to specify the timing parameters of an instance of ddrsdram port It is a record type defined as follows type ddrsdram timing t is record cas latency na na na na na na na na na na na ref _mrd _dil rp PEG _ wtr _rtw _rtp _wtp _ras end recor Ct er CP oct ocr o rF gt r1 resh E d na tural tural tural tural tural tural tural tural tural tural tural tural This datatype can normally treated as an abstract datatype since the user application need typically only use one of the predefined
165. GA depending on which is the master Note 4 LRESET In models featuring a PCI9080 ADM XRC ADM XRC P ADM XRC II Lite this signal is connected to the LRESETO pin of the PCI9080 In all other this signal is connected to the LRESET pin of the PCI9656 Note 5 L64 214 ADM XRC SDK 4 9 3 User Guide Win32 Bussed signals Only the following models are capable of 64 bit local bus operation and have the L64 signal ADM XPL ADM XP ADP XPI ADM XRC 4FX ADM XRC 5LX and ADM XRC 5T1 215 ADM XRC SDK 4 9 3 User Guide Win32 Sideband signals ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Local bus sideband signals The table below lists the sideband signals available to the FPGA on an ADM XRC series card for special functions such as Demand mode DMA and interrupt generation Note 216 Signal FINTI LDACK LDREQ Driven by FPGA PCI to local bus bridge FPGA Description FPGA interrupt line The FINTI signal allows the FPGA to generate an interrupt on the host It is negative edge sensitive If FINTIZ remains asserted after the initial high to low transition further interrupts will cannot be generated until FINTI transitions high again DMA acknowledge One bit of LDACK is asserted in a one hot manner by the PCl to local bus bridge at the same time as LADS in order to indicate that the current burst is a Demand mode DMA burst It remains asserted until the end o
166. HANDLE unsigned int Index ADMXRC2 BANK INFO Info Arguments Argument Type Card In Index In Info Out Return value Value ADMXRC2 SUCCESS ADMXRC2 INVALID HANDLE Purpose Handle of card about which to return bank information Specifies the bank about which to return information Structure to be filled in with information about the specified bank Meaning The information was obtained successfully Card is not a valid handle to a card ADMXRC2 INVALID PARAMETER Index was not valid Description This function returns information about a bank of memory in an ADMXRC2 BANK INFO stucture The Index parameter specifies the bank about which to return information and the Info parameter must point to the ADMXRC2 BANK INFO stucture which is to receive the information 440 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 GetCardInfo ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 GetCardlnfo Prototype ADMXRC2 STATUS ADMXRC2_GetCardInfo ADMXRC2_HANDLE Card ADMXRC2_CARD_INFO Info Arguments Argument Type Purpose Card In Handle of card about which to return information Info Out Structure to be filled in with information about card Return value Value Meaning ADMXRC2_SUCCESS The information was obtained successfully ADMXRC2 INVALID HANDLE Card is not a valid handle to a card Description The ADMXRC2 GetCardlnfo function returns information about card
167. I card requires the locbus agent nonmux agent while a simulation targetting the ADM XPL requires the locbus agent mux32 agent or the locbus agent mux64 agent depending on whether your design expects a 32 bit or 64 bit local bus The purpose of a local bus agent is threefold e Tobundle the local bus signals together so that manually and repeatedly typing the names of numerous local bus signals can be avoided This is done on grounds of convenience e To drive the local bus in a tristatable manner so that multiple local bus agents can be connected to the local bus Although the example above shows only one agent the next example see below shows multiple local bus agents connected to the local bus e To hide the details of the local bus from the stimulus process In other words a stimulus process need not know or care whether it is driving an multiplexed or nonmultiplexed address data style local bus for example Note the signals connecting the stimulus process to the local bus agent there are four types locbus ddma in t locbus ddma out t locbus in t and locbus out t These are in fact bundles of signals that enable the stimulus process to drive the local bus agent The arbiter is another component provided by the plxsim package Its job is to ensure that no more than one local bus agent drives the local bus at a given moment Since there is only one local bus agent in the above example the arbiter s job is trivial However the next examp
168. IDELAYCTRL reference clock workaround default refclk220 Enable Virtex 5 IDELAYCTRL reference clock workaround repeat base 10 integer Number of times to perform tests default 1 64 Operate local bus in 32 bit mode default 64 Operate local bus in 64 bit mode Description 67 The MemoryF sample application tests all banks of on board memory on a reconfigurable computing card Unlike the Memory application MemoryF performs a chip driven memory test The CPU initiates the test and waits for completion but does not actively participate in the memory test This reduces the runtime for the test by at least one order of magnitude compared to the Memory application When run the MemoryF sample application commands the target FPGA to perform a consisting of the following phases 1 Constant 0x55 pattern written to memory for detecting data bits stuck at 0 1 or shorted to other signals 2 Constant OxAA pattern written to memory for detecting data bits stuck at 0 1 or shorted to other signals 3 Alternating 0x55 OxAA pattern written to memory for detecting data bits stuck at 0 1 or shorted to other signals The pattern is designed to toggle all of the data lines for a given bank at the maximum possible frequency during a burst of memory accesses 4 Own address pattern written to memory for detecting address bits stuck at 0 1 or shorted to other signals 5 Bit reversed own address pattern written to memory for detecting address bits
169. IkO cycles or asserted for many 1 0 cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous 357 ADM XRC SDK 4 9 3 User Guide Win32 zbtsram port clkO pipeline qtag ready rst sr tag 358 in out out out command but refer to the section below for a discussion of performance Clock for user interface All other signals except rst are synchronous to clkO Data to memory User code must place valid data on d whenever a write command is entered ce and w both asserted Pipelined mode select sideband signal User code should drive this input in order to select the expected operating mode of the ZBT SSRAM device 0 gt flowthrough mode 1 gt pipelined mode Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a read command qtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce This memory port unconditionally asserts ready Asynchronous reset for memory port May be tied to logic 0 if not required Synchronous reset for memory port May be tied to logic 0 if not required Tag in When user code asserts ce with w deasserted it must also pla
170. K 4 9 3 User Guide Win32 LEOT mode ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data LEOT mode DMA transfers LEOT mode offers a way for the FPGA on an ADM XRC series card to terminate a DMA transfer before the programmed number of bytes of data has been transferred Normally calls ADMXRC2 DoDMA and ADMXRC2 DoDMAlmmediate do not return until the requested number of bytes has been transferred In some applications this is undesirable since an application may not know in advance how many bytes of data to transfer to or from the FPGA In LEOT mode the FPGA can assert the LEOT signal along with LREADY and or LBTERM during a local bus burst in order to prematurely terminate a DMA transfer The DMA engine that is performing the current local bus burst will complete the burst as quickly as possible and then terminate the DMA transfer The status of the DMA transfer will be that it was completed without error and the host will receive a DMA interrupt as normal this DMA interrupt should not be confused with the FPGA interrupt However less than the programmed number of bytes will have been transferred LEOT mode may be freely mixed with the other DMA modes such as constant address mode and demand mode In order for the host to know how many bytes of data were transferred it is recommended that a host readable register be implemented within the FPGA indicating the number of bytes transferred After the call to ADMXR
171. M XRC 5T2 so separate files are not included within this SDK Location SADMXRC_SDK4 fpga vhdl simple Synopsis 152 ADM XRC SDK 4 9 3 User Guide Win32 Simple The Simple FPGA design demonstrates how to implement host accessible registers in an FPGA design The registers can be accessed via the ADMXRC2 Read and ADMXRC2 Write API calls or via a memory mapped region The latter method is demonstrated by the Simple sample application FPGA Space Usage Nibble reversed data register REVDATA local bus address 0 0 Bits Mnemonic Type Function 31 0 VAL RAN When read this register returns the nibble reversed version of the last value written to it Nibble reversed data register DATA local bus address 0x4 Bits Mnemonic Type 31 0 VAL R W Source files Function When read this register returns the last value written to it For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model ADM XRC with Virtex ADM XRC with Virtex E ADM XRC P with Virtex ADM XRC P with Virtex E ADM XRC I Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with FXT 153 XST script file simple xrc v scr simple xrc ve scr simple xrcp v scr simple xrcp ve scr simple xrc2l v2 s
172. M devices on the card operating at 210 MHz DDR 420 and the memory clock domain within the target FPGA operating at 105 MHz With an ADM XRC 4LX card passing the option mclk 140 on the command line would result in the ZBT SSRAM devices on the card operating at 140 MHz and the memory clock domain within the target FPGA also operating at 140 MHz ADM XRC SDK 4 9 3 User Guide Win32 MemoryF FPGA Design The MemoryF sample application normally uses the Memory sample FPGA design VHDL but when the 64 option is specified it uses the Memory64 sample FPGA design VHDL 68 ADM XRC SDK 4 9 3 User Guide Win32 Memtest ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Memtest sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview Note this application has been effectively superseded by the Memory sample application since the latter is more general and works on a larger number of models The Memtest sample application tests the ZBT SSRAM on a reconfigurable computing card Syntax memtest options Options Option Type Meaning banks hexadecimal integer Bitmask of banks to test default OxFFFFFFFF card base 10 integer ID of card to open 69 ADM XRC SDK
173. MA may require disk I O for the operating system to make all pages of a user buffer resident in physical memory 518 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC FindImageOffset ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC_FindImageOffset Prototype ADMXRC_STATUS ADMXRC_FindImageOffset ADMXRC_FPGA_TYPE FpgaType ADMXRC_IMAGE Image ULONG Size ULONG Offset Arguments Argument Type Purpose FPGAType In The FPGA device expected in the bitstream Image In A buffer containing the bitstream file loaded into memory Size In The length of the bitstream file in bytes Offset In out Filled in with the offset of the SelectMap data Return value Value Meaning ADMXRC_SUCCESS The offset of the SelectMap data was returned successfully ADMXRC_INVALID_FILE The bitstream appears not to be valid ADMXRC_FPGA_MISMATCH The bitstream does not target the expected device Description This function scans a bitstream file that has been loaded into memory and determines the offset from the beginning of the buffer of the SelectMap data The FPGAType parameter of the enumerated type ADMXRC_FPGA_TYPE should be the FPGA that the bitstream targets Typically the value used is obtained from the FPGAType member of the ADMXRC_CARD_INFO structure The Image parameter should point to a variable of type ADMXRC IMAGE which was obtained from an earlier call to ADMXRC LoadFpgaFile The Length parameter sh
174. MB Bank 2 2MB Bank 1 2MB Bank 0 2MB 0 380000 Augmented lonqword address P amp GE 7 0 LA 20 2 0 300000 0 280000 0 200000 0 180000 0 100000 0 080000 Ox000000 The following registers exist in the 2MB register region Page register PAGE local bus address 0 0 Bits Mnemonic Type 7 0 PAGE R W 31 8 MBZ Mode register MODE local bus address 0x4 Bits Mnemonic Type 0 PIPELINED R W 31 1 MBZ Size register SIZE local bus address 0 8 Bits Mnemonic Type 1 0 SIZE R W 31 2 MBZ 161 Function Value that augments bits 20 2 of the local bus address when accessing the SSRAM Function Value that selects the mode in which to operate the ZBT SSRAM devices 0 gt flowthrough 1 gt pipelined Function Value that specifies the number of address bits in a logical SSRAM bank 0 gt 17 128k words 1 2 18 256k words 2 gt 19 512k words 3 gt 20 1M words ADM XRC SDK 4 9 3 User Guide Win32 ZBT Information register INFO local bus address 0x10 Bits Mnemonic Type Function 23 0 BANKSIZE RO Returns size in words of each logical SSRAM bank 31 24 NUMBANK RO Number of logical SSRAM banks in the design Status register STATUS local bus address 0x14 Bits Mnemonic Type Function 0 LCLK LOCKED RO Returns 1 if the local bus clock LCLK DCM DLL is currently locked RAMCLK LOCKED RO If nis the number of SSRAM clock si
175. MXRC2 Read ADMXRC2 IOADAPTER The read is performed from the card s PCI interface registers rather than the local bus If the ADMXRC2 IOADAPTER flag is not specified the Local parameter specifies the starting local bus address from which the data will be read Otherwise the Local parameter specifies the starting adapter register PCI9080 PCI9656 offset from which the data will be read If the ADMXRC2 IOFIXED flag was specified this address will not increment as the data is read Otherwise the address is incremented as the data is read The Buffer parameter specifies the buffer to receive the data read The Length parameter specifies how many bytes are to be read and should be a multiple of the width specified by the Width parameter For example if Width is ADMXRC2 IOWIDTH 16 the Length parameter should be a multiple of 2 457 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ReadConfig ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2_ReadConfig Prototype ADMXRC2_STATUS ADMXRC2_ReadConfig ADMXRC2_HANDLE Card unsigned long Index DWORD Value Arguments Argument Type Purpose Card In Index In Value Out Return value Value ADMXRC2_SUCCESS ADMXRC2 INVALID HANDLE ADMXRC2 INVALID PARAMETER Description Handle of card on which the read is to take place Index of EEPROM location to read Value read from EEPROM location The data was read successfully Card is not a valid card handl
176. Ms Virtex ll IIPro This technique is used to ensure that the ZBT SSRAM devices and the FPGA operate using the same clock The design accomodates pipelined or flowthrough JEDEC compliant ZBT SSRAM devices Some ZBT devices are capable of operating in either pipelined or flowthrough mode depending on the level on a mode select pin The FPGA design therefore contains a register that selects pipelined or flowthrough operation The design maps the data pins of each physical SSRAM bank to the 32 bit local data bus The manner in which this is done depends upon the number and width of the physical SSRAM banks on a card The ADM XRC and ADM XRC P have four physical 36 bit SSRAM banks The 4 parity bits are dropped and the 32 data bits are mapped to one 32 bit logical SSRAM bank This results in four logical SSRAM banks The ADM XRC II has six physical 36 bit SSRAM banks The 4 parity bits are dropped and the 32 data bits are mapped to one 32 bit logical SSRAM bank This results in six logical SSRAM banks The ADM XRC II Lite uses 18 bit SSRAMs Two physical banks are put together to form a 36 bit bank The 4 parity bits are then dropped and the 32 data bits are mapped to one 32 bit logical SSRAM bank This results in two logical SSRAM banks The ADM XPL has a single 64 bit SSRAM device The low 32 bits are mapped to one 32 bit logical SSRAM bank This results in a single logical SSRAM bank The design also contains a register that selects the numbe
177. RC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC MapbDirectMaster Prototype ADMXRC STATUS ADMXRC MapDirectMaster ADMXRC HANDLE Card ADMXRC DMADESC DMADesc unsigned long Offset unsigned long Length ADMXRC BUFFERMAP Map Arguments Argument Type Purpose Card In Handle of card that the bitstream targets Buffer In Specifies application buffer to map Offset In Where to begin mapping within the application buffer Length In Size of region of application buffer to map Map In Out Structure to receive map information Return value Value Meaning ADMXRC SUCCESS The bitstream file was successfully loaded ADMXRC INVALID HANDLE The Card parameter did not refer to an open card ADMXRC INVALID DMADESC The DMA descriptor representing the application buffer was not valid ADMXRC INVALID PARAMETER The Offset or Length parameters were outside the bounds of the application buffer Description This function builds an array of PCI addresses of the pages of memory that comprise a buffer in the application s address space The Card parameter should be the handle of the card that was used to create the DMA descriptor DmaDesc DMA descriptors are obtained via the ADMXRC_SetupDMA call The Offset and Length parameters identify a region within the buffer that DmaDesc refers to The Map parameter must point to an ADMXRC BUFFERMAP structure If the call to ADMXRC_MapDireciMasier is successful th
178. Sample application list ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Sample application list The table below lists the sample applications and the FPGA bitstream required for each if applicable Name FPGA design FPGA design Bitstream Purpose Verilog VHDL directory Clock Clock bit clock Utility to program clock generators and measure clock frequencies DLL DLL DLL bit dll Demonstrates using Delay locked loops DLLs in Virtex Virtex E Virtex EM devices and Digital Clock Managers DCMs in Virtex ll Virtex IIPro Virtex 4 and Virtex 5 devices DMA DDMA DDMA bit ddma Demonstrates using the DMA engines on DDMA64 DDMA64 bit ddma64 the ADM XRC series of cards EPTest A utility to read and write the configuration EEPROM on the ADM XRC series of cards Flash A utility for programming the Flash memory on the ADM XRC FrontlO FrontlO FrontlO bit frontio Demonstrates use of the front panel I O connector Info A utility to display information about a card ITest ITest ITest bit itest Demonstrates generation and handling of FPGA interrupts on the host Masier Master Master bit master Demonstrates direct master access by FPGA to host memory Memory Memory bitmemory Demonstrates host access to memories Memory64 bitmemory64 MemoryF Memory bitmemory Demonstrates host access to memories Memory64 bitmemory64 Memtest ZBT ZBT bit zbt Demonstrates host access to ZBT ZBT64 ZBT64 bit zbt64 SSRAM RearlO RearlO R
179. SpaceConfig ADMXRC2 SPACE BURST DISABLED Non bursting local bus behaviour ADMXRC2 SPACE BURST ENABLED Bursting local bus behaviour 444 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_GetStatusString ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2_GetStatusString Prototype const char ADMXRC2_GetStatusString ADMXRC2_STATUS Code Arguments Argument Type Purpose Code In The error code to convert to a string Return value Unlike most API functions ADMXRC2 GetStatusString returns a pointer to a NULL terminated string that describes the error code Description This function returns a textual description of the error code passed in the Code parameter The returned string should be treated as read only since it is statically allocated If the Code parameter contains a code that is not one of the members of the enumerated type ADMXRC2_STATUS the string returned will be unknown ADMXRC2_STATUS code 445 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_GetVersionInfo ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 GetVersionlnfo Prototype ADMXRC2 STATUS ADMXRC2 GetVersionInfo ADMXRC2 HANDLE Card ADMXRC2 VERSION INFO Info Arguments Argument Type Purpose Card In Handle of card about which to return information Info Out Structure to be filled in with version information Return value Value Meaning ADMXRC2 SUCCESS The informatio
180. SyncDirectMaster ADMXRC2 UnsetupDMA ADMXRC2 Write ADMXRC2 WriteConfig Interrupt handling ADMXRC2 RegisterlnterruptEvent ADMXRC2 UnregisterlnterruptEvent Error handling ADMXRC2 GetStatusString ADMXRC2_InstallErrorHandler ADMXRC2_StatusToSiring 426 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BuildDMAModeWord ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 BuildDMAModeWord Prototype DWORD ADMXRC2_BuildDMAModeWord ADMXRC2 BOARD TYPE BoardType ADMXRC2 IOWIDTH Width unsigned int WaitStates DWORD MiscFlags Arguments Argument Type Purpose BoardType In Type of card being used Width In Width of operation on local bus WaitStates In Number of wait states to be introduced by PCI9080 PCI9656 MiscFlags In Miscellaneous mode flags Return value If the parameters are valid a DMA mode word is returned If the parameters supplied are not valid the invalid mode word OxFFFFFFFF is returned Description This function differs from most API functions in that no card handle parameter is required and the return value is not of type ADMXRC2 STATUS ADMXRC2 BuildDMAModeWord constructs a value that may later be passed to the DMA functions such as ADMXRC2 DoDMA and ADMXRC2 DoDMAlImmediate Provided that the DMA mode does not need to be changed the DMA mode word can be pre computed and used for many DMA transfers The BoardType parameter should correspond to the type of the board on which
181. T cycle count registers local bus addresses 0x80 OxFC Each 32 bit register in the range 0x80 OxFC returns the number of elapsed cycles for the corresponding cycle counter Bits Mnemonic Type Function 31 0 N RO Returns the number of cycles that have elapsed for a particular clock input To read a cycle counter the following procedure should be used 1 Issue a command to read the cycle counter for the clock input of interest via the READ register For example to read the cycle counter for the LCLK input which is the first cycle counter on all models write the value 0x00000001 to the READ register 2 Poll the STATUS register until the bit corresponding to the clock input of interest returns 1 This should be the same bit as in step 1 above For example when bit 0 of the STATUS register returns 1 the read of the cycle counter corresponding to the LCLK input has been completed 3 Read the cycle counter corresponding to the clock input of interest For the LCLK input this is the first cycle counter at local bus address 0x80 Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with clock xrc v scr clock xrc v prj clock xrc ucf Virtex ADM XRC with clock xrc ve scr clock xrc ve prj clock xrc ucf Virtex E 82 ADM XRC SDK 4 9 3 User Guide Win32 Clock ADM XRC P with Virtex ADM
182. TH ADMXRC FPGA TYPE ADMXRC HANDLE ADMXRC HANDLER FUNCTION ADMXRC IMAGE ADMXRC STATUS ADMXRC SYNCMODE 556 Purpose A value that identifies a particular programmable clock A value that specifies the frequency of the reference oscillator A value that identifies a particular card in a system A DMA descriptor identifying a locked application buffer A value that indicates upon which DMA channel a DMA transfer should take place A value that indicates in which direction a DMA transfer should transfer data A value that indicates the width in bytes of a DMA transfer A value representing the type of an FPGA fitted to a card A handle to an ADM XRC or ADM XRC P card A pointer to an application defined error handler function A FPGA bitstream image containing SelectMap data A value that indicates the success or failure of a call to an API function A value specifying what kind of memory coherency synchronisation to perform ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC CLOCK ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC_CLOCK Declaration typedef enum _ADMXRC_CLOCK ADMXRC_MCLK ADMXRC_VCLK ADMXRC_PCICLK ADMXRC_VCLK1 ADMXRC_VCLK2 ADMXRC_VCLK3 ADMXRC CLOCK Description This type specifies which clock generator should be programmed in a call to ADMXRC_SetClockRate It should be one of Value Meaning ADMXRC VCLK1 Local bus clock ADMXRC MCLK General purpose clock
183. The ADMXRC2 interface is recommended for new applications This interface offers a higher level of abstraction of hardware features compared to the depreciated ADMXRC interface Note that the ADMXRC2 interface supports all models in the ADM XRC range e ADM XRC e ADM XRC P e ADM XRCHI Lite e ADM XRC II e ADM XPL e ADM XP e ADP DRC II e ADP WRC II e ADP XPI e ADM XRC 4LX e ADM XRC 4SX e ADM XRC 4FX e ADPE XRC 4FX e ADM XRC 5LX e ADM XRC 5T1 e ADM XRC 5T2 Calls to the ADMXRC2 interface must not be mixed with calls to the ADMXRC interface using the same card handle A card handle obtained using the ADMXRC2 OpencCard function should not be used in any calls to the legacy ADMXRC interface Applications should assume that the API will enforce this rule Cards of any model in the ADM XRC range may be opened by the ADMXRC2 OpencCard function In general applications designed for the ADMXRC2 interface should include appropriate code to check what type of card they have opened and take appropriate action such as loading the correct bitstream ADMXRC2 functions by group ADMXRC2 structures ADMXRC2 datatypes 422 ADM XRC SDK 4 9 3 User Guide Win32 Multithreading issues ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Multithreading issues ADMXRC2 interface The ADM XRC API is thread safe except for any error handler function installed The ADMXRC2 interface functions can be divided into two grou
184. This clock must be the same frequency as clkO but 270 degrees behind Data to memory User code must place valid data on d whenever a write command is entered ce and w both asserted DLL disable sideband signal User code should drive this input with 0 for normal operation but driving it with 1 causes the DOFF field within rc to be asserted Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a read command gtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Certain types of memory port may unconditionally assert ready whereas other types of memory port may sometimes deassert ready depending on several factors For example a DDR II SDRAM port is capable of buffering a certain number of commands internally but if its command buffer is filled while it executes a refresh cycle it will deassert ready ADM XRC SDK User Guide Common Memory Ports rst in Asynchronous reset for memory port May be tied to logic if not required Sr in Synchronous reset for memory port May be tied to logic if not required tag in Tag in When user code asserts ce with w deasserted it must also place a valid tag on the tag signal When as a result of the read command the memory por
185. Type Function 1 0 MBZ 31 2 ADDR WO This field holds the local bus address to be used for the next Direct Master transfer Writing to bits 31 24 initiates a Direct Master transfer so this register should be written after the other registers have been initialized Write data register WDATA local bus address 0x4 Bits Mnemonic Type Function 31 0 VAL WO For Direct Master write transfers this register holds the 32 bit data value that should be written Configuration register CFG local bus address 0x8 Bits Mnemonic Type Function 0 WRITE WO When this field is 1 the next Direct Master transfer is a write otherwise it is a read 31 1 MBZ Read data register RDATA local bus address 0xC Bits Mnemonic Type Function 31 0 VAL RO This register contains the 32 bit value read on the last Direct Master read Status register STAT local bus address 0x10 Bits Mnemonic Type Function 0 BUSY RO When this field returns 1 it indicates that a Direct Master transfer is in progress 31 1 MBZ Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with master xrc v scr master xrc v prj master xrc ucf Virtex ADM XRC with master xrc ve scr master xrc ve prj master xrc ucf Virtex E ADM XRC P with master xrcp v scr master xrcp v prj master xrcp ucf Virtex ADM XRC P with master xrcp ve scr mas
186. User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but refer to the section below for a discussion of how to maximize performance Clock for user interface 7 All other signals except rst are synchronous to clk0 High speed clock phase 90 7 This clock must be the same frequency as clkO but lagging by 90 degrees High speed clock phase 180 7 This clock must be the same frequency as but lagging by 180 degrees High speed clock phase 270 T This clock must be the same frequency as clkO but lagging by 270 degrees Column address width select sideband signal 6 8 This input selects the number of column address bits to use Along with the row input it specifies the row column geometry of the DDR SDRAM device as defined here ADM XRC SDK User Guide Common Memory Ports d pbank qtag ready regd row rst Sr tag 13 in in out out out Data to memory User code must place valid data on d wh
187. WRC II or ADP DRC II card 222 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals LHOLD A FHOLDA central resource LINTI FIMTI LELE LELE COSE FOCS LRE LA 31 2 PCI9656 ae LBE 3 0 LETE RMI LRE AD aii M M LL LY WRITE LO 1 0 LORE Gaq1 0 ADM XRC 4LX and ADM XRC 4SX The following figure shows the connections between the PCI9656 local bus bridge and the FPGA in an ADM XRC 4LX or ADM XRC 4SX card 223 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals LHOLDA FHOLDA central LCLK FESUNMIEE LCLK FIM Tl Cast PCI93656 LBE 3 0 LBLASTR LETE RM 31 0 LRE AD t LARI TE LO ACH3 1 0 LORE 2 a 1 0 ADM XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 and ADM XRC 5T2 ADV The following figure shows the connections between the local bus bridge and the FPGA in an ADM XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 or ADM XRC 5T2 ADV card note that the local bus is capable of operating in 32 bit or 64 bit mode 224 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals FHOLD FHOLD A LCLK FINTIx LRE SET LAD B3 0 LAD 31 0 LADS PCLto Local Bus Bridg 2 0 3 0 FPGA LBLAST LATE Fihi LRE ADY LO ACK 3 0 LORE as 0 ADM XRC 5TZ and ADM XRC 5T DA1 The following figure shows the connections between the local
188. When the error handler is called FunctionName will point to a NULL terminated string containing the name of the API function which failed and Code will contain the error code An installed error handler may itself make calls to the ADM XRC API However it is the application programmer s responsibility to ensure that e Installation uninstallation of the error handler routine is correctly synchronized to other ADM XRC API calls that may fail e If the error handler is called reentrantly as a result of the error handler routine itself making calls to the ADM XRC API 447 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_InstallErrorHandler infinite recursion stack overflow does not occur 448 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 LoadBitstream ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 LoadBitstream Prototype ADMXRC2 STATUS ADMXRC2 LoadBitstream ADMXRC2 HANDLE Card const char Filename ADMXRC2 IMAGE Image unsigned long ImageSize Arguments Argument Type Purpose Card In Handle of card that the bitstream targets Filename In Name of bitstream file to load Image Out Loaded bitstream data ImageSize Out Size in bytes of loaded bitstream data Return value Value Meaning ADMXRC2 SUCCESS The bitstream file was successfully loaded ADMXRC2 FILE NOT FOUND The file could not be opened ADMXRC2 INVALID FILE The file appeared not to be a valid bitstream ADMXR
189. Win32 ZBT64 The ZBT64 FPGA design demonstrates how to implement a 64 bit host interface to the SSRAM in an FPGA design The design divides the 4MB FPGA space into a lower 2MB region for register and an upper 2MB window for accessing the SSRAM A page register is provided so that all of the SSRAM on a card is available to the host This example demonstrates the following e A bursting local bus interface in the FPGA e Interfacing of ZBT SSRAMs to the FPGA e Bursting if supported need not be supported over the entire FPGA space In this design only the 2MB SSRAM window supports bursting e Since the FPGA does not distinguish between a direct slave burst initiated by the host CPU and a burst initiated by a DMA engines the local bus bridge the host can use programmed 1 or DMA to transfer data e Generation of deskewed copies of the local bus clock LCLK that are driven off chip to the SSRAMs using DLLs Virtex E EM or DCMs Virtex II IIPro This technique is used to ensure that the ZBT SSRAM devices and the FPGA operate using the same clock The design accomodates pipelined or flowthrough JEDEC compliant ZBT SSRAM devices Some ZBT devices are capable of operating in either pipelined or flowthrough mode depending on the level on a mode select pin The FPGA design therefore contains a register that selects pipelined or flowthrough operation The design maps the data pins of each physical SSRAM bank to the 64 bit local data
190. X X 30 31 32 DMXRC2 FPGA 5VLX330 133 DMXRC2 FPGA RESVD134 134 DMXRC2 FPGA RESVD135 35 DMXRC2 FPGA 5VLX30T 136 DMXRC2 FPGA 5VLX50T 137 DMXRC2 FPGA 5VLX85T 138 DMXRC2 FPGA 5VLX110T 139 DMXRC2 FPGA 5VLX330T 140 DMXRC2 FPGA 5VLX220T 141 DMXRC2 FPGA 5VLX155T 142 DMXRC2 FPGA RESVD143 143 DMXRC2 FPGA 5VSX35T 144 DMXRC2 FPGA 5VSX50T 145 DMXRC2 FPGA 5VSX95T 146 DMXRC2 FPGA 5VSX240T 147 DMXRC2 FPGA RESVD148 148 DMXRC2_FPGA_RESVD149 149 DMXRC2_FPGA_RESVD150 150 DMXRC2_FPGA_RESVD151 15l DMXRC2_FPGA_5VFX100T 152 DMXRC2_FPGA_5VFX130T 153 DMXRC2_FPGA_5VFX200T 154 DMXRC2_FPGA_5VFX30T DMXRC2_FPGA_5VFX70T 156 DMXRC2_FPGA_UNKNOWN 157 ADMXRC2_FPGA_FORCE32BITS Ox7FFFFFFFU ADMXRC2 FPGA TYPE Description This type represents the FPGA device fitted to a card Certain API functions require knowledge of what FPGA device is fitted in order to operate The type of FPGA fitted to a card can be obtained from the ADMXRC2 CARD INFO structure returned by ADMXRC2 GetCardlnfo 494 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 FPGA TYPE This type contains no information about the FPGA package The FPGA package is inferred from the BoardType member of the ADMXRC2 CARD INFO structure 495 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 HANDLE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 HANDLE Declaratio
191. XDSSM a practical example qlads 0 lbterm oe 1 lready 1 o 1 ready o lt 1 ld oe 21 stopping 0 write lt write qlads 1 lkterm_oe_ 1 lready_oe 1 _ 1 ready 0 Ibterm_oe_ 0 0 Id 21 lready 1 lt stopping lt 0 Ibterm_o_ lt 1 Iblast 1 or Ibterm 1 ate so ain Iready 0 lt 1 lbterm oe 0 ld oe write ready 0 stopping stop o write lt write ready 0 readyz1 oe lt 0 Ikterm oe 1 0 iready oe 0 lready oe 1 0 lt not stop Iready o 0 Id oe lt wite stopping 0 ite wite stopping stop or stopping write lt wite lbterm oe 0 lready oe 0 Ibterm o not stop or stopping lready o 0 ld oe lt write stopping lt stop or stopping write lt write blast 0 and Ibterm 0 Ibtenn_oe 0 Iready oe 0 Ibtenn o T lt not stop or stopping Iready o 0 Id oe T lt write stopping lt stop or stopping write lt wite As indicated in the state diagram e Ibterm_o_l Ibterm_oe_l 1 oe Iready_o_l Iready_oe_l stopping and write are generated Mealy style e decode idle and transfer are generated Moore style A couple of points should be noted about this implementation 1 In the transition from XFER to IDLE Iready oe I remains asserted while Iready o and Ibterm
192. XRC2 HANDLE Card HANDLE Event Arguments Argument Type Purpose Card In Handle of card for which to register the event Event In Specifies the event to register for interrupts Return value Value Meaning ADMXRC2 SUCCESS The event was successfully registered ADMXRC2 INVALID HANDLE The Card handle or Event handle was not valid Description This function registers a Win32 event for capturing interrupts from the FPGA Event must be a valid Win32 event handle The type of the event can be manual or auto reset depending on the needs of the application After an event is registered using ADMXRC2 RegisterlnterruptEvent it is signalled by the driver whenever an FPGA interrupt occurs Applications can thus be notified of interrupts from the FPGA by waiting on a registered event Any number of events can be registered this way but typically only one is ever required by an application To unregister an event specify the same event in a call to ADMXRC2 UnregisterInterruptEvent 460 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SetClockRate ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 SetClockRate Prototype ADMXRC2 STATUS ADMXRC2 SetClockRate ADMXRC2 HANDLE Card unsigned int Index double Rate double Actual Arguments Argument Type Purpose Card In Handle of card for which to program the clock Index In The index of the clock generator to program Rate In The desired fre
193. Y in the testbench The signal corresponding to LRESET in the testbench The signal corresponding to LWRITE in the testbench ADM XRC SDK 4 9 3 User Guide Win32 locbus agent mux64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus agent mux64 Declaration Synopsis Description Declaration component 1 _ agent mux64 generic tco_bussed in tco_p2p in port lreset in lclk in lad inou lads 1 inou lbe inou 164 inou lblast 1 inou lbterm l inou lready inou lwrite inou lhold out lholda in bus in out bus out in end component Synopsis CT CF CT CF CT CF CF CI time 5 ns time 5 ns std logic std logic std logic vector 63 downto 0 std logic std logic vector 7 downto 0 std logic std logic std logic std logic std logic std logic std logic locbus in t locbus out t Non synthesizable testbench component that drives the local bus 411 ADM XRC SDK 4 9 3 User Guide Win32 locbus agent mux64 Description totom stimulus process tco bussed ico p2p reset lad lada I I54 Iblast Ibtem I Ireadwy lite Ihalda Ihald locbuz agent muxb4 totor local bhus ta fram arbiter This local bus agent component can be instantiated in a testbench to drive a local bus that has a 64 bit multiplexed address data bus Ea
194. Z ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog ddma64 Synopsis The DDMA64 FPGA design demonstrates demand mode DMA with local bus bursting in 64 bit mode Data is read from an application buffer in host memory and then simply written back to another application buffer unchanged a loopback operation In order to use demand mode DMA the host must specify the appropriate mode when performing DMA transfers This is demonstrated by the DMA sample application 172 ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 e Data is read from host memory using DMA channel 0 in demand mode An instance of the PLXDDSM module controls the DMA channel e Data is written to host memory using DMA channel 1 in demand mode An instance of the PLXDDSM module controls the DMA channel e Two 512 word by 32 bit FIFOs are used to obtain a 64 bit wide FIFO for buffering data e Bursting is allowed on the local bus e Flow control is implemented by holding off the demand mode DMA request signals LDREQ 1 0 when the FIFO is nearly full or nearly empty FPGA Space Usage The design assumes that any DMA transfer on DMA channel 0 is transferring data into the FIFO hence any direct slave write where LDACK 0 is asserted will fill the FIFO with data Similarly any DMA transfer on DMA channel 1 is assumed to tbe emptying the FIFO hence any read where LDACK3 1 is asserted will empty the FIFO of data The local bus address is ignored during these demand mod
195. a Data ADMXRC DoDMA Prototype ADMXRC STATUS ADMXRC DoDMA ADMXRC HANDLE Card ADMXRC_DMADESC DmaDesc unsigned long Offset unsigned long ength DWORD Local DWORD Direction DWORD Channel DWORD DMAModeWord DWORD Flags DWORD Timeout PHANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure DmaDesc In Handle to DMA descriptor representing application buffer Offset In Offset within application buffer Length In Number of bytes to transfer Local In Address of beginning of transfer on local bus Direction In Direction of DMA transfer Channel In DMA channel to use for the transfer DMAModeWord In Mode word to use for the DMA transfer Flags In Miscellaneous flags Timeout In out Timeout for DMA transfer Event In out Event to use to wait for completion Return value Value ADMXRC_SUCCESS ADMXRC_INVALID_HANDLE ADMXRC INVALID DMADESC ADMXRC INVALID PARAMETER ADMXRC DEVICE BUSY Description 515 Meaning The DMA transfer was performed successfully Card is not a valid handle to a card DMADesc is not a valid DMA descriptor An invalid parameter was passed Could not begin DMA immediately as requested ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DoDMA This function is used to perform a DMA transfer from an application buffer to the FPGA or from the FPGA to an application buffer DMA transfers are queued in a first come first served manner unless the Flags p
196. a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XPL ddma64 xpl v2p scr ddma64 xpl v2p prj ddma64 xpl ucf ADM XP ddma64 xp v2p scr ddma64 xp v2p prj ddma64 xp ucf 173 ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt 174 ADM XRC SDK 4 9 3 User Guide Win32 DLL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DLL sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog dll Synopsis The DLL FPGA design demonstrates the clock doubling capability of Virtex DLLs and Virtex Il The local bus clock LCLK is input through a clock and doubled using a DLL Virtex E EM or DCM Virtex Il or Virtex IIPro A 32 bit host readable counter is clocked by a 2X multiple of LCLK 175 ADM XRC SDK 4 9
197. a new value the members are defined as follows Member Type family family_t ck_width natural cke_width natural odt_width natural num_phys_bank natural num_bank_bits natural num addr bits natural Function Specifies the FPGA family that the memory port targets Number of CK CK pairs present in the rc bus Number of pins present in the rc bus Number of ODT pins present in the rc bus Specifies the number of physical banks being driven by the memory port which is also the number CS pins present in the rc bus Specifies the number of BA bits internal bank bits on the devices being driven by the memory port Specifies the number of A bits row column address bank bits on the devices being driven by the memory port The value of ddr2sdram pinout t passed in the pinout parameter of a ddr2sdram port determines the proper values to pass for the ra width and rc width parameters The relevant formulae are ra width num bank bits num addr bits rc width 3 rd width 8 2 num ck width odt width num phys bank 3 285 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram timing t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The dd The r2sdram timing t datatype ddr2sdram timing t datatype is exported by the memif package and is used to specify the timing parameters of an instance of ddr2sdram port It is a record type defined as follows This t
198. a vhdl common memif memif_def_sim vhd must be included instead Parameters Name Type Function Note a_width natural Width in bits of the logical address busses a a0 a1 a2 and a3 1 bias natural If unfair is true specifies which client 0 to 3 to favor otherwise 2 ignored d width natural Width in bits of the logical data busses d d0 d1 d2 d3 q q0 3 q1 q2 and q3 latency natural Specifies the number of consecutive clock cycles for which a 4 client is granted access to the memory port before access can be granted to a different client ready delay natural Specifies both the maximum number of clock cycles of delay 5 permitted between the deassertion of readyi and the deassertion of cei and the minimum number of clock cycles of delay permitted between the assertion of ready and the assertion of cei 308 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 registered boolean Specifies whether or not the memory port signals ce w etc are 6 registered in order to improve timing tag width natural Width in bits of the tag values tag tag0 tag1 tag2 tag3 qtag qtag0 qtag1 qtag2 and qtag3 respectively unfair boolean If true specifies that the client identified by bias should be given 7 absolute priority over the other clients Notes 1 The a width parameter is the width of the logical address busses a a0 a1 a2 and a3 Generally it must be sufficiently wide to be able to address all of the memory in a memory ban
199. a2 Generally it must be sufficiently wide to be able to 301 address all of the memory in a memory bank Hence the required value of a width depends on what type of memory devices are in use and their density ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 2 Assuming that the unfair parameter is true the bias parameter specifies the favored client i e which client is given priority access to the memory port The favored client can interrupt a burst of memory accesses by one of the unfavored clients regardless of the value of latency A value of 0 represents client 0 and a value of 2 represents client 2 If the unfair parameter is false however bias is ignored and there is no favored client 3 Thed width parameter is the width of the logical data busses d d0 d1 d2 q q0 q1 and q2 It is generally determined by the physical data width of the memory bank and the type of memory devices in use DDR memory devices in particular generally have a logical data width that is 2 or 4 times the physical data width 4 The latency parameter is the minimum number of consecutive clock cycles that a particular client is awarded access to the memory port without being interrupted by another unfavored client The purpose of this parameter is to enable a reasonable efficiency to be achieved for memory types that benefit from bursting and locality of access for example DDR and DDR II SDRAM Note however that if unfair is true and the favored client req
200. able operation these signals must not change unless the memory port is idle The purpose of these signals should not be confused with that of the pinout parameter The pinout parameter specifies properties of the circuit board on which the FPGA and DDR SDRAM devices are mounted In general the number of physical wires on the circuit board provided for addressing the DDR SDRAM devices can be greater than the number actually used by a particular DDR SDRAM device The phase and frequency relationships between the four clock phases are illustrated by the following figure n clkO cika clk180 clk270 aL Tne CK i CK Tne dk 60 Also shown are the related clocks the DDR II SDRAM clock pair CK and CK and the capture clock pair clkcO and clkc180 Their frequencies are the same as clkO but their phases are indeterminate with respect to clkO For correction operation all sideband inputs must be static while the memory port is not idle In this version the x4 sideband input must be driven with a constant The connections between an instance of the training module ddrsdram training v2 and an instance of ddrsdram port v2 form a private communication channel The information carried by this channel is generally not of interest to the user but brief descriptions of each signal in the channel are provided for information only Training of ddrsdram port v2 from deassertion of reset to completion of training tst
201. ad and ADMXRC2 Write API calls or via a memory mapped region The latter method is demonstrated by the Simple sample application FPGA Space Usage Nibble reversed data register REVDATA local bus address 0x0 Bits Mnemonic Type 31 0 VAL R W Function When read this register returns the nibble reversed version of the last value written to it Nibble reversed data register DATA local bus address 0x4 Bits Mnemonic Type 31 0 VAL R W Source files Function When read this register returns the last value written to it For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file ADM XPL simple64 xpl v2p scr ADM XP simple64 xp v2p scr ADP XPI simple64 xpi v2p scr ADM XRC 4FX J simple64 xrc4fx v4fx scr with 4VFX100 ADM XRC 4FX J simple64 xrc4fx v4fx scr with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 simple64 xrce4fx v4fx scr simple64 xrce4fx v4fx scr ADM XRC 5LX simple64 xrcblx v5lx scr ADM XRC 5T1 simple64 xrc5t1 v5fxt scr with FXT ADM XRC 5T1 simple64 xrc5t1 v5Ixt scr with LXT ADM XRC 5T1 simple64 xrcbt1 v5sxt scr with SXT 157 XST project file simple64 xpl v2p prj simple64 xp v2p prj simple64 xpi v2p prj simple64 xrc4fx v4fx prj simple64 xrc4fx v4fx prj simple64 xrce4fx v4fx prj simple64 xrce4fx v4fx prj simple64 xrcblx v5lx prj simple64 xrcbt1 v5fxt prj simple64 xrcbt1 v5Ixt pr
202. address 0xC Bits Mnemonic Type Function 31 0 VAL RO This register contains the 32 bit value read on the last Direct Master read Status register STAT local bus address 0x10 Bits Mnemonic Type Function 0 BUSY RO When this field returns 1 it indicates that a Direct Master transfer is in progress 31 1 MBZ Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with master xrc v scr master xrc v prj master xrc ucf Virtex ADM XRC with master xrc ve scr master xrc ve prj master xrc ucf Virtex E ADM XRC P with master xrcp v scr master xrcp v prj master xrcp ucf Virtex ADM XRC P with master xrcp ve scr master xrcp ve pr master xrcp ucf Virtex E ADM XRC Il Lite master xrc2l v2 scr master xrc2l v2 prj master xrc2l ucf ADM XRC II master xrc2 v2 scr master xrc2 v2 prj master xrc2 ucf 107 ADM XRC SDK 4 9 3 User Guide Win32 Master Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC P projnav rcp device ADM XRC II Lite projnavrc2l device ADM XRC II projnav xrc2 lt device gt 108 ADM XRC SDK 4 9 3 User Guide Win32 Memory ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data MEMORY sample VHDL FPGA design Model support Lo
203. ady2 signals for the clients Memory port tag The arbiter 3 module drives this signal with a valid tag when it asserts ce with w deasserted in order to perform a read of the memory port on behalf of a client Memory port data valid When valid is asserted it is as a result of arbiter 3 performing a read of the memory port on behalf of a client The signals q and qtag are both qualified by valid Memory port write select The arbiter 3 module asserts this signal along with ce when it performs a write to the memory port on behalf of a client ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The arbiter 4 component Overview HDL source code Parameters Signals Performance Overview The arbiter 4 component is part of the memif package and enables a memory port to be shared by up to four clients The component follows the generic user interface for memory ports so that as far each client is concerned it appears to be communicating with a memory port 0 width 1 0 a a width 1 0 vw vv tadgO tag width 1 0 taa tac width 1 0 m beO d width 8 1 0 8 1 0 dO d width 1 0 d d width 1 0 port q d width 1 0 ad vidth 1 0 ctadgO tag width 1 0 ctaa d width 1 0 valid valid ready ready req cel a1 a width 1 0 wl tag1 tag width 1 bet d widt
204. agesPci 1 n start Pagesopanned 2 BytesSpanned n Init Offset 0 e MaxPages is less than the actual number of pages spanned by the region in the user buffer specified by Length and Offset The function will only map the first MaxPages In this case PagesSpanned will be equal to MaxPages and BytesSpanned will be less than the Length parameter 452 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 MapbDirectMaster Physical memory 5 Application buffer T Pagel amolh en PagesPci 1 start Pagesopanned 4 PagesPci 2 BytesSpanned Init ffset PagesPci 0 453 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 OpenCard ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 OpenCard Prototype ADMXRC2 STATUS ADMXRC2 OpenCard ADMXRC2_CARDID CardID ADMXRC2 HANDLE Card Arguments Argument Type Purpose CardID In ID of card to open Card Out Handle to opened card Return value Value Meaning ADMXRC2 SUCCESS The card was successfully opened ADMXRC2 CARD NOT FOUND The card was in use or not physically present Description This function is used to open and obtain a handle to an ADM XRC card The particular card to open is identified by its card ID passed via the CardID parameter If there is more than one card in the system with the same ID the function will open the first free card found with the specified ID If the special value 0 is
205. al dd in C Zn locbus ddma in t signal dd out out locbus ddma out t Synopsis Performs a demand mode DMA local bus read transfer with incrementing local bus address Description This procedure uses the bus in bus out dd in and dd out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim read demand lachus ddma out t Idack 1 lt 02 gt lacbuz dama in t Idreg 1 0 gt Stimulus process n Local bus FPGA design unit under test agent LOCAL BUS 0 390 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read demand Before calling this procedure a stimulus process should ensure that the FPGA ie the unit under test has asserted LDREQXx This can be accomplished by calling plxsim wait demand before calling plxsim read demand When called plxsim read demand will continue to perform transfers until one of two conditions is met 1 The FPGA unit under test deasserts LDREQ in order to pause the DMA transfer or 2 All of the data has been transferred the length of the data vector specifies how many bytes must be transferred During the transfer s LDACK will be asserted with the proper timing with respect to LADS etc The order parameter specifies the width of the local data bus Valid values are e 2 for a 32 bit local data bus e fora 64 bit local data bus The address parameter specifies the starting local bus byte address of t
206. al from the local bus LDREQ out This output must drive one of the LDREQ pins on the local bus Qualified address strobe This input should be pulsed for one clock cycle when a local bus cycle begins This signal is typically generated by qualifying the LADS signal by simple address decoding along with the corresponding LDACK signal In most cases the FHOLDA signal is also used Data ready The user application should assert this signal when it is ready to transfer data during a local bus cycle This signal should be the same as the ready signal that is input to the associated plxdssm instance Request demand mode DMA local bus cycle from PCI to local bus Bridge The user application should assert this signal when it wishes to initiate a demand mode DMA cycle request may be pulsed for as little as one clock cycle such a pulse will result in Idreq o remaining asserted until the PCI to local bus Bridge initiates the desired demand mode DMA local bus cycle Alternatively should the FPGA wish to perform many demand mode DMA local bus cycles request may be held asserted for an arbitary period The purpose of this signal is different to that of the ready signal The ready signal permits data transfer to occur in a local bus cycle that has already started The request signal on the other hand is used to control whether or not the PCI to local bus generates demand mode DMA local bus cycles Deasserting request prevents the PCI to lo
207. als during a transfer For reads each element of the vector is obtained from one of the byte lanes of the local bus LD or LAD signals during a transfer To avoid confusion and problems related to ascending vs descending ranges the range of any objects of type byte vector t should always be ascending for example variable data byte vector t 0 to 15 Ok variable data byte vector t 9 downto 3 NOT OK 365 ADM XRC SDK 4 9 3 User Guide Win32 integer vector t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference integer vector t Declaration Synopsis Description Declaration type integer vector t is array natural range lt gt of integer Synopsis integer vector tis a vector of integers Description Use this type to specify the priorities for the arbiter component 366 ADM XRC SDK 4 9 3 User Guide Win32 locbus ddma in t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus ddma in t Declaration Synopsis Description Declaration type locbus ddma in t is record end record Synopsis locbus ddma in t is an opaque record type used to bundle together the signals required for demand mode DMA local bus transfers Description Alocbus agent ddma component is connected to the demand mode DMA pins of the FPGA unit under test and outputs a signal of type locbus ddma in t The stimulus process then us
208. am file did not match the device fitted to the card ADMXRC INVALID HANDLE Card is not a valid handle to a card ADMXRC INVALID PARAMETER An invalid parameter was passed ADMXRC NO DMADESC A DMA descriptor could not be allocated Description This function is used to configure the FPGA on a card from a Xilinx bitstream file BIT using DMA If deterministic runtime is required the ADMXRC ConfigureFromBuffer or ADMXRC ConfigureFromBufferDMA functions should be used instead since ADMXRC ConfigureFromFileDMA performs file I O in order to load the bitstream into memory The card to be configured is specified by the Card parameter The bitstream file to load into the FPGA is specified by the Filename parameter 513 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ConfigureFromFileDMA The Channel parameter specifies which DMA channel should be used for the operation If ADMXRC DMACHAN ANY is specified the DMA transfer will be performed on the first available DMA channel However pending DMA transfers on a specific a DMA channel will always be given priority It is possible for a DMA transfer that specifies ADMXRC DMACHAN ANY to be delayed indefinitely if all DMA channels are kept busy by other threads The Event parameter should be a pointer to a Win32 event handle See multithreading issues for further information 514 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DoDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alph
209. an ADM XRC 5T2 card running Clock with no arguments produces the following output Clock pins available on specified card Clock input Programmable Clock generator index 1 iCLK Yes 0 2 MCLKA Yes 1 3 MCLKB Yes 1 4 REFCLK No N A 5 CLKIN No N A 6 MGTREF No N A 7 PCIE100A No N A This indicates that of the seven clock inputs only LCLK 1 MCLKA 2 and MCLKB 3 are programmable LCLK corresponds to clock generator 0 and MCLKA and MCLKB are copies of the output of clock generator 1 To measure the frequency of a particular clock input specify the index of the clock input as the first argument For example to measure the local bus clock frequency run Clock as follows clock 1 This produces output in the following form actual measured values may vary depending on what LCLK frequency has previously been programmed if any Measuring frequency of clock input 1 LCLK Initial counter value 625869 Final counter value 40624672 delta 39998803 In this case the delta value indicates that the frequency of the local bus clock LCLK is approximately 40 MHz Note that since the above command line only measures the local bus clock frequency without programming the clock generator the measured frequency depends upon whatever the current local bus clock frequency happens to be The final mode in which Clock can be run both programs a clock generator and measures the resulting frequency F
210. app module is intended to be a starting point for the end user to add his or her own logic to perform some useful data processing function As shipped in this SDK it contains logic to perform a chip driven memory test of all banks of on board memory See the MemoryF example application for details on how to run the chip driven memory test 145 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 reg out 048 reg vw offset registerg memory testy reg in F 4 31 0 offsat 0 req leo x 30 0 length registerg 2 xU 5 length 0 fa 400 be 0 128 be 0 valid O 252 ready mak 2016 done 0 2032 error 0 1543 1536 ephase 0 to arbiter 2 instances in 1055 1024 s eadcr 0 memory banks f ho offset register memory test 53 32 offse 1 req t ce 1 7 4 wt a 1 length register tag 1 be 1 m a t valid 1 252 ready 1 2017 done 1 2033 error 1 1551 1544 ephase t 1087 1055 eadcr 1 Implementation of chip driven memory test in user app module The end user can remove modify and add logic as desired in order to create a customized user app module In doing so a few points to remember are 146 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 e The ports a be ce d q qtag ready tag valid and w are a bundle of vectors where a particular slice through this bundle forms an interface to a memory ba
211. arameter see below specifies otherwise When a thread calls ADMXRC_DoDMA it is blocked until the DMA transfer has been completed The DmaDesc parameter must be a valid DMA descriptor obtained via a call to ADMXRC SetupDMA This along with Offset implicitly specifies the application buffer that is the source or destination of data for the DMA transfer The Offset parameter is the offset into the user buffer at where the DMA transfer is to begin transferring data This permits one DMA descriptor to map a large buffer DMA transfers can then be performed on subregions of the large buffer by specifying appropriate Offset and Length values The Length parameter specifies the number of bytes of data to transfer The Local parameter specifies the starting local bus address of the transfer The DMAModeWord parameter may specify that the local bus address is invariant for the duration of the DMA transfer see ADMXRC BuildDMAModeWord The Direction parameter specifies whether the transfer is from application buffer to FPGA or FPGA to application buffer and should be a value from the enumerated type ADMXRC DIRECTION The Channel parameter is a zero based index that specifies which DMA channel should be used for the operation The number of DMA channels provided by a card is given by the NumDMAChan member of the ADMXRC CARD INFO structure Unless ADMXRC ANY is specified the maximum legal value of Channel is NumDMAChan 1 I
212. ata read from the memory port as a result of arbiter_2 reading the memory port on behalf of a client It is qualified by the valid signal ready in Memory port ready When ready is asserted the memory port is ready to accept commands The arbiter_2 module uses this signal in generating the readyO and ready1 signals for the clients tag out Memory port tag The arbiter 2 module drives this signal with a valid tag when it asserts ce with w deasserted in order to perform a read of the memory port on behalf of a client valid in Memory port data valid When valid is asserted it is as a result of arbiter 2 performing a read of the memory port on behalf of a client The signals q and qtag are both qualified by valid w out Memory port write select The arbiter 2 module asserts this signal along with ce when it performs a write to the memory port on behalf of a client 299 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The arbiter 3 component Overview HDL source code Parameters Signals Performance Overview The arbiter 3 component is part of the memif package and enables a memory port to be shared by up to three clients The component follows the generic user interface for memory ports so that as far each client is concerned it appears to be communicating with a memory port a a width 1 0 a a width 1 0 vw vv tag tag width
213. atible script files for simulating this design are provided Refer to the following table for the appropriate command line for a particular model Some warnings may be emitted by memory models DCMs DLLs and PLLs These relate to startup and can safely be ignored as the design is held in reset until clocks have stabilized Model Shell command ADM XRC vsim do do zbt xrc do ADM XRC P vsim do do zbt xrcp do ADM XRC II Lite vsim do do zbt xrc2l do ADM XRC II vsim do do zbt xrc2 do ADM XPL vsim do do zbt xpl do ADM XRC 4LX vsim do do zbt xrc4lx do ADM XRC 4SX vsim do do zbt xrc4sx do 163 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ZBT64 sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL 2vP20 2VP30 only ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga vhdl zbt64 Synopsis Note this FPGA design has been effectively superseded by the Memory64 sample FPGA design VHDL since the latter is more general and supports a larger number of models and types of memory 164 ADM XRC SDK 4 9 3 User Guide
214. atterns of addressing or to avoid frequently changing from a read command to a write command on every ADM XRC SDK 4 9 3 User Guide Win32 Memory interface package VHDL clkO qtag ready rst sr tag valid out out out out cycle Performance issues are discussed in detail for each type of memory port Clock for user interface All other signals except rst are synchronous to clkO Data to memory User code must place valid data on d whenever a write command is entered ce and w both asserted Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a read command qtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Certain types of memory port may unconditionally assert ready whereas other types of memory port may sometimes deassert ready depending on several factors For example a DDR II SDRAM port is capable of buffering a certain number of commands internally but if its command buffer is filled while it executes a refresh cycle it will deassert ready Asynchronous reset for memory port May be tied to logic 0 if not required Synchronous reset for memory port May be tied to logic 0 if not required Tag in When user code asserts ce with w d
215. available to the host This example demonstrates the following e A bursting local bus interface in the FPGA e Interfacing of ZBT SSRAMs to the FPGA e Bursting if supported need not be supported over the entire FPGA space In this design only the 2MB SSRAM window supports bursting e Since the FPGA does not distinguish between a direct slave burst initiated by the host CPU and a burst initiated by a DMA engines the local bus bridge the host can use programmed l O or DMA to transfer data e Generation of deskewed copies of the local bus clock LCLK that are driven off chip to the SSRAMs using DLLs Virtex E EM or DCMs Virtex II IIPro This technique is used to ensure that the ZBT SSRAM devices and the FPGA operate using the same clock The design accomodates pipelined or flowthrough JEDEC compliant ZBT SSRAM devices Some ZBT devices are capable of operating in either pipelined or flowthrough mode depending on the level on a mode select pin The FPGA design therefore contains a register that selects pipelined or flowthrough operation The design maps the data pins of each physical SSRAM bank to the 32 bit local data bus The manner in which this is done depends upon the number and width of the physical SSRAM banks on a card e The ADM XRC and ADM XRC P have four physical 36 bit SSRAM banks The 4 parity bits are dropped and the 32 data bits are mapped to one 32 bit logical SSRAM bank This results in four logical SSRAM banks
216. bank takes a finite number of clock cycles In this memory port the following performance penalties exist for memory accesses falling into the following patterns e Several clkO cycles for changing from read to write or write to read within the same page and bank e In the order of 8 clkO cycles for consecutive accesses that fall within different pages of the same bank or within different banks e In the order of 8 20 cIkO cycles for an access that occurs while the memory port is performing a refresh Latency for read commands is nondeterministic due to the penalties described above particularly because of the need to refresh but the best case latency from entry of a read command ce asserted with w deasserted to valid asserted is approximately 11 cIkO cycles This can be modified somewhat by tightening or relaxing the timing as specified by the timing parameter Worst case latencies may be computed by adding the above penalties to the best case latency The optimal usage pattern for this memory port is blocks of accesses of the same type read or write to the same bank and page A linearly incrementing address is an example of an optimal usage pattern When used optimally this memory port with 32 physical data bits rd is 32 operating at a clkO frequency of 133MHz can sustain approximately 1GB s 332 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram training v2 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data T
217. be used to obtain SelectMap data in the correct form The Length parameter specifies the number of bytes of configuration data to be written to the FPGA s SelectMap port The Channel parameter specifies which DMA channel should be used for the operation If ADMXRC DMACHAN ANY is specified the DMA transfer will be performed on the first available DMA channel However pending DMA transfers on a specific a DMA channel will always be given priority It is possible for a DMA transfer that specifies ADMXRC DMACHAN ANY to be delayed indefinitely if all DMA channels are kept busy by other threads The Event parameter should be a pointer to a Win32 event handle See multithreading issues for further information 511 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ConfigureFromFile ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC ConfigureFromFile Prototype ADMXRC STATUS ADMXRC ConfigureFromFile ADMXRC HANDLE Card char Filename Arguments Argument Type Purpose Card In Handle of card to configure Filename In Name of BIT file Return value Value Meaning ADMXRC SUCCESS The FPGA was successfully configured ADMXRC FILE FOUND The file Filename could not be opened ADMXRC INVALID FILE The file Filename appears not to be a valid bitstream ADMXRC NO MEMORY There is not enough free memory to temporarily load the bitstream into memory ADMXRC FPGA MISMATCH The device targetted by the bitstream file di
218. before being output This adds one cycle of latency but is recommended for ease of timing closure This parameter has no effect on the timing relationship between ready and cei 7 If the unfair parameter is true the client identified by the bias parameter is given priority access to the memory port This overrides the latency parameter meaning that the favored client can interrupt a burst of memory accesses by one of the unfavored clients Signals The arbiter 3 module has the following infrastructure ports Signal Type Function Note clk in Clock All other signals except rst are synchronous to clk rst in Asynchronous reset This port should be mapped to the asynchronous reset signal if there is one or to a constant logic 0 signal if an asynchronous reset is not required sr in Synchronous reset This port should be mapped to the synchronous reset signal if there is one or to a constant logic 0 signal if a synchronous reset is not required The interface presented to clients by the arbiter_3 module is as follows Signal Type Function Note a0 in Client logical address al a2 A client must place a valid address on ai when it asserts cei bed in Client byte enables to memory be1 be2 A client must place valid byte enables on bei whenever a write command is entered cei and wi both asserted A logic 1 ina given bit of be means that the corresponding byte within be will be written to memory while a zero means that t
219. btz do cd xrc5tda1 vsim do do memory xrcbtda1 do ADM XRC SDK 4 9 3 User Guide Win32 Memory64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data MEMORY64 sample VHDL FPGA design Model support Location Synopsis FPGA space usage Explanation of design Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC I ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location ADMXRC_SDK4 fpga vhdl memory 131 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 Synopsis The MEMORY64 FPGA design is a reference design demonstrating how to implement an interface to the on board memory on a reconfigurable computing card so that it is effectively dual ported Thus a program running on the host can access the memory and at the same time a user application block can also access the memory This example demonstrates the following e A bursting local bus interface in the FPGA e Bursting if supported need not be supported over the entire FPGA space In this design only the 2MB SSRAM window supports bursting e Im
220. bus Currently only the ADM XPL is capable of operating with a 64 bit local bus The ADM XPL has a single 64 bit SSRAM device and so this device s data bits can be mapped one to one to the local data bus bits The design also contains a register that selects the number of address bits in the logical SSRAM banks Address lengths of 17 18 19 and 20 bits are accomodated The page register augments the limited address space 2MB allotted to accessing the SSRAM The following figure illustrates this on an ADM XPL with a 1M x 64 ZBT SSRAM device fitted 165 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 0 200000 Ox1 C0000 No bank Returns zeroes Ox1 80000 0x1 40000 Ox1 00000 Ox0C 0000 0080000 0040000 P AGE 7 0 0x2 Qx400000 Local bus byte address SSR AM window 2MB LA 21 0 0 200000 Register region 2MB 0 000000 FPGA Space Usage Ox000000 The following registers exist in the 2MB register region Page register PAGE local bus address 0 0 Bits Mnemonic Type 7 0 PAGE R W 31 8 MBZ Mode register MODE local bus address 0x4 Bits Mnemonic Type 0 PIPELINED R W 31 1 MBZ Size register SIZE local bus address 0 8 Bits Mnemonic Type 1 0 SIZE R W 31 2 MBZ 166 Function Value that augments bits 20 3 of the local bus address when accessing the SSRAM Function Value that selects the mode in which to operate the ZBT SSRAM devices 0 gt flowthrough 1 gt pipelined
221. bus bridge and the FPGA in an ADM XRC 5TZ or ADM XRC 5T DA1 card 225 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals FHOLD FHOLD A LCLK FINTIx LRE SET LAD 21 0 LaDs PCLto Local Bus LBLAST 4 LATE Fihi LRE ADY LO ACK 3 0 LORE as 0 226 ADM XRC SDK 4 9 3 User Guide Win32 Direct slave transfers ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Direct slave transfers Direct slave transfers are the basic method of transferring data to and from the FPGA on an ADM XRC series card The local bus bridge is the master and the FPGA is the slave Direct slave transfers are normally the result of calling functions from the API such as ADMXRC2 Read and ADMXRC2 DoDMA This section contains timing diagrams that illustrate the local bus protocol Single word read and write Burst read normal termination Burst write normal termination Burst read terminated by LBTERM Burst write terminated by LBTERM Multiplexed address data bus Single word read and write The following timing diagram illustrates a single word read followed by a single word write followed by another single word read all terminated normally LBLAST and LREADY are both asserted LCLK LADS Key Signal is owned LA by master m Signal is owned LBE bya dave fj Suggested ITE tumaround LBLAST _
222. bytes are to be written and should be a multiple of the width specified by the Width parameter For example if Width is ADMXRC2 IOWIDTH 16 the Length parameter should be a multiple of 2 474 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 WriteConfig ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 WriteConfig Prototype ADMXRC2 STATUS ADMXRC2 WriteConfig ADMXRC2 HANDLE Card unsigned long Index DWORD Value Arguments Argument Type Purpose Card In Handle of card on which the write is to take place Index In Index of EEPROM location to write Value In Value to write to EEPROM location Return value Value Meaning ADMXRC2 SUCCESS The data was written successfully ADMXRC2 INVALID HANDLE Card is not a valid card handle ADMXRC2 INVALID PARAMETER Index was out of range Description The ADMXRC2 WriteConfig function writes to the configuration EEPROM on an ADM XRC series card This function is intended for advanced users who need to change the configuration of their card from the factory defaults The Index parameter specifies the index of the EEPROM location to write The Value parameter is the value to write to the specified EEPROM location The number of EEPROM locations and the width in bits of each location is dependent on the board type The actual value written to the specified EEPROM location is Value truncated by removing MSBs to the width of the EEPROM The table below shows EEPROM size
223. c5t2 v5sxt scr ADM XRC 5T2 ADV with SXT ADM XRC 5TZ simple xrc5tz v5fxt scr with FXT ADM XRC 5TZ simple xrcbtz v5lxt scr with LXT ADM XRC 5TZ simple xrcbtz v5bsxt scr with SXT ADM XRC 5T simple xrc5tda1 v5fxt scr DA1 with FXT ADM XRC 5T simple xrc5tda1 v5Ixt scr DA1 with LXT ADM XRC 5T simple xrc5tda1 v5sxt scr simple xrc5tda1 v5sxt prj DA1 with SXT Project Navigator files simple xrcbt1 v5lxt prj simple xrcbt1 ucf simple xrcbt1 v5sxt prj simple xrcbt1 ucf simple xrc5t2 v5fxt prj simple xrc5t2 5vfxt ucf simple xrc5t2 v5lxt prj simple xrc5t2 ucf simple xrc5t2 v5sxt prj simple xrc5t2 ucf simple xrc5tz v5fxt prj simple xrcbtz 5vfxt ucf simple xrc5tz v5Ixt prj simple xrcbtz ucf simple xrc5tz v5sxt prj simple xrcbtz ucf simple xrc5tda1 vbfxt prj simple xrcbtda1 5vixt ucf simple xrc5tda1 v5Ixt prj simple xrc5tda1 ucf simple xrc5tda1 uct Project Navigator projects can be found in the projnav directory as follows Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADM ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 154 Project Navigator project file projnav xrc lt device gt projnav xrcp lt device gt projnav xrc2l lt device gt projnav xrc2 lt device gt projnav xpl lt device gt projnav xp lt device gt projnav wrc
224. cal bus Bridge from generating further demand mode DMA cycles for a given DMA channel while asserting request allows the PCI to local bus Bridge to generate demand mode DMA cycles for that DMA channel Asynchronous reset This port may be driven by an asynchronous reset for the local bus interface or tied to logic O if not required Synchronous reset This port may be driven by a synchronous reset for the local bus interface or tied to logic O if not required ADM XRC SDK 4 9 3 User Guide Win32 plxddsm deprecated stop in Terminate local bus cycle The user application should assert this signal when it wishes to terminate the current local bus cycle This signal should be the same as the stop signal that is input to the associated plxdssm instance Usage For each DMA channel that is to be used in demand mode there must be one instance of plxddsm Each instance of plxddsm is associated with one bit of the LDACK and LDREQ busses Regardless of how many instances of plxddsm are required exactly one instance of plxdssm is also required in order to complete the local bus interface The following figure illustrates a plxddsm instance connected to the one and only plxdssm instance along with connections to the local bus and backend CLK RESET gt 2 Ls HOLDA gt gt gt e decodng ADS note 1 DACK lt 0 gt request cortrol note 3 o zu m I
225. cal data bus Valid values are e 2 for a 32 bit local data bus 397 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write const e for a 64 bit local data bus The multiburst parameter specifies the action taken if the target of the transfer terminates the burst before the desired number of bytes has been transferred e When false the procedure will return if the burst is terminated and nxfered will reflect the actual number of bytes transferred e When true the procedure will perform transfers on the local bus until the desired number of bytes has been transferred In this case nxfered will be set to the length of data The address parameter specifies the local bus byte address of the transfer which will not be incremented during the transfer The address need not be aligned to the word size of the local data bus although an unaligned address generally makes little sense when using constant addressing The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively enc
226. can remain asserted It can be pulsed for single clkO cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but refer to the section below for a discussion of how to maximize performance 351 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v4 clkO clk2x0 clk2x90 clk45 dll off qtag ready rst sr tag trained valid 352 in in in out out out out out Clock for user interface All other signals except rst are synchronous to clkO High speed clock phase 0 This clock must be in phase with clkO but double the frequency High speed clock phase 90 This clock must the same frequency as 2 0 but must its phase must be 90 degrees ahead of cIk2x0 Auxilliary clock phase 45 This clock must the same frequency as clkO but must its phase must be 45 degrees ahead of Data to memory User code must place valid data on d whenever a write command is entered ce and w both asserted DLL disable sideband signal User code should drive this input with 0 for normal operation but driving it with 1 causes the DOFF field within rc to be asserted Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a
227. carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e For a multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address After the first word of data has been transferred LBE will revert to being determined by the be parameter and on the last word of the transfer also determined by any residual bytes that do not comprise a full word of data The data parameter returns the data read from the local bus For a nonmultiplexed address data bus the data comes from the LD signal whereas for a multiplexed address data bus the data comes from the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes read from the local bus 389 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read demand ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim read demand Declaration Synopsis Description Declaration procedure plxsim read demand order natural address EN std logic vector be c pi byte enable t data out byte vector t nxfered sut natural signal bus in gt in locbus in t signal bus out out locbus out t sign
228. cation Synopsis FPGA space usage Explanation of design Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC I ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location ADMXRC_SDK4 fpga vhdl memory 109 ADM XRC SDK 4 9 3 User Guide Win32 Memory Synopsis The MEMORY FPGA design is a refernce design demonstrating how to implement an interface to the on board memory on a reconfigurable computing card so that it is effectively dual ported Thus a program running on the host can access the memory and at the same time a user application block can also access the memory This example demonstrates the following A bursting local bus interface in the FPGA Bursting if supported need not be supported over the entire FPGA space In this design only the 2MB SSRAM window supports bursting Implementing a local bus interface that is compatible with both Direct Slave transfers and DMA transfers Use of the port common VHDL modules for interfacing various types of memory to the FPGA Use of the arbiter 2 common VHDL module for sharing a
229. cation s address space by which the region may be accessed using pointers This member may be NULL meaning that the region is not mapped into the application s address space The VirtualSize member is the size in bytes of the region in the application s address space When LocalSize is very large eg 256MB LocalSize may differ from VirtualSize indicating that the driver was unable to map all of the region into the application s address space If VirtualBase is NULL then VirtualSize is 0 Only the local bus space is mapped into the application s address space In other words any call to ADMXRC2 GetSpacelnfo with an index other than 0 will return an ADMXRC2 SPACE INFO structure whose VirtualBase member is NULL and VirtualSize member is O 485 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 VERSION INFO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 VERSION INFO Declaration typedef struct ADMXRC2 VERSION INFO BYTE DriverMinor BYTE DriverMajor BYTE APIMinor BYTE APIMajor ADMXRC2 VERSION INFO Description The ADMXRC2 VERSION INFO structure is returned by ADMXRC2_GetVersionInfo and indicates the API library revision level and the driver revision level DriverMajor and DriverMinor respectively indicate the ADM XRC device driver major and minor revision levels APIMajor and APIMinor respectively indicate the API library major and minor revision levels The
230. cbus out t driven by the stimulus process The second group of ports must be mapped to signals driven or input by the local bus arbiter Port 415 Map to ADM XRC SDK 4 9 3 User Guide Win32 locbus agent nonmux Ihold Iholda A signal corresponding to LHOLD that is input by the bus arbiter There should be one such signal per local bus agent A signal corresponding to LHOLDA that is driven by the bus arbiter There should be one such signal per local bus agent The remaining ports should be mapped to local bus signals as follows Port lads 1 la Ibe Iclk Iblast_ lbterm_ ld lready_ Ireset Iwrite 416 Map to The signal corresponding to LADS in the testbench The signal corresponding to LA 31 2 in the testbench The signal corresponding to LBEZ 3 0 in the testbench The signal corresponding to LCLK in the testbench The signal corresponding to LBLAST in the testbench The signal corresponding to LBTERM in the testbench The signal corresponding to LD 31 0 in the testbench The signal corresponding to LREADY in the testbench The signal corresponding to LRESET in the testbench The signal corresponding to LWRITE in the testbench ADM XRC SDK 4 9 3 User Guide Win32 locbus arb ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus arb Declaration Synopsis Description Declaration component locbus arb generic
231. ce a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags 5 ADM XRC SDK 4 9 3 User Guide Win32 zbtsram port valid out Notes 5 For correction operation all sideband inputs must be static while the memory port is not idle The signals of this interface to and from the memory device s are as follows Signal ra Performance There are no performance penalties in this memory port for any particular pattern of usage Latency from entry of a read command ce asserted with w deasserted to valid asserted depends upon the current mode e 4 clkO cycles in flowthrough mode pipeline driven with 0 e 5 clk0 cycles in pipelined mode pipeline driven with 1 A 32 bit wide ZBT SSRAM port with clkO frequency of 133MHz can sustain approximately 533MB s 359 Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command Type Function In Memory device address bus
232. ch local bus agent is normally associated with a stimulus process In the figure above the signals on the right comprise the local bus while the signals on the left are driven by the stimulus process The generics should be mapped as follows Generic tco bussed tco p2p Map to A value of type time that represents the desired local bus clock to output delay for the bussed signals such as LADS This parameter has a suitable default value so it need not be specified A value of type time that represents the desired local bus clock to output delay for point to point signals such as LHOLD This parameter has a suitable default value so it need not be specified The first group of ports must be mapped to signals driven or used by the stimulus process associated with the local bus agent Port bus in bus out Map to A signal of type locbus in t used by the stimulus process A signal of type locbus out t driven by the stimulus process The second group of ports must be mapped to signals driven or input by the local bus arbiter Port 412 Map to ADM XRC SDK 4 9 3 User Guide Win32 locbus agent mux64 Ihold Iholda A signal corresponding to LHOLD that is input by the bus arbiter There should be one such signal per local bus agent A signal corresponding to LHOLDA that is driven by the bus arbiter There should be one such signal per local bus agent The remaining ports should be mapped to l
233. cifies the priorities for each local bus agent where a numerically higher value represents higher priority The length of this vector must be equal to n arb The ports must be mapped to signals as follows Port Iclk Ihold Iholda Ireset 418 Map to A signal equivalent to the local bus clock LCLK A vector that carries the bus request signals for all of the local bus agents in the design Each element of the vector corresponds to the HOLD signal for a particular local bus agent A vector that carries the bus grant signals for all of the local bus agents in the design Each element of the vector corresponds to the HOLDA signal for a particular local bus agent A signal equivalent to the local bus signal LRESET ADM XRC SDK 4 9 3 User Guide Win32 API reference ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADM XRC API reference The ADM XRC API exposes a number of functions to software running on the host To use the API an application must include the API header file and be linked with the appropriate API import library Two revisions of the API exist e he current ADMXRC2 interface e he legacy ADMXRC interface Alpha Data recommends use of the ADMXRC2 interface in all new applications The ADMXRC interface is supported for backwards compatibility with older applications 419 ADM XRC SDK 4 9 3 User Guide Win32 API header files ADM XRC SDK 4 9 3 User Guide Win32 Co
234. ck cycles of delay permitted between the assertion of ready and the assertion of cei registered boolean Specifies whether or not the memory port signals ce w etc are 6 registered in order to improve timing tag width natural Width in bits of the tag values tag tag0 tag qtag qtag0 and qtag1 unfair boolean If true specifies that the client identified by bias should be given 7 absolute priority over the other clients Notes 1 The a width parameter is the width of the logical address busses a a0 and a1 Generally it must be sufficiently wide to be able to address all of the memory in a memory bank Hence the required value of a width depends on what type of memory devices are in use and their density 2 Assuming that the unfair parameter is true the bias parameter specifies the favored client i e which client is given priority access to the memory port The favored client can interrupt a burst of memory accesses by one of the unfavored clients regardless of the value of latency A value of 0 represents client 0 and a value of 1 represents client 1 If the unfair parameter is false however bias is ignored and there is no favored client 3 Thed width parameter is the width of the logical data busses d d0 d1 q q0 and q1 It is generally determined by the physical data width of the memory bank and the type of memory devices in use DDR memory devices in particular generally have a logical data width that is 2 or 4 times th
235. col 1 0 No of row bits used No of column bits used 00 00 12 8 00 01 12 9 00 10 12 10 00 11 12 11 01 00 13 2 01 01 13 ue 01 10 13 11 01 11 13 12 10 00 14 10 10 01 14 11 10 10 14 12 10 11 14 13 11 00 15 11 11 01 15 12 11 10 15 13 11 11 15 14 Performance 321 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal Most of the time the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application Periodically however the memory port must refresh the DDR II SDRAM devices it is controlling which may result in an accumulated backlog of buffered commands and deassertion of the ready signal Certain usage patterns such as alternating between read and write commands may also have the same effect The architecture of DDR II SDRAM device consists of a number of internal banks which are in turn divided into a number of pages At any moment a given bank may be closed or may have a given page open Opening or closing a bank takes a finite number of clock cycles In this memory port the following performance penalties exist for memory accesses falling into the following patterns e Several clkO cycles for changing from read to write or write to read within the same page and bank e In the order of 8 clkO cycles for consecutive accesses that
236. common memif arbiter 3 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name a width bias d width latency ready delay registered tag width unfair Notes Type natural natural natural natural natural boolean natural boolean Function Note Width in bits of the logical address busses a a0 a1 and a2 1 If unfair is true specifies which client 0 to 2 to favor otherwise 2 ignored Width in bits of the logical data busses d d0 d1 d2 q q0 q1 3 and q2 Specifies the number of consecutive clock cycles for which a 4 client is granted access to the memory port before access can be granted to a different client Specifies both the maximum number of clock cycles of delay 5 permitted between the deassertion of readyi and the deassertion of cei and the minimum number of clock cycles of delay permitted between the assertion of ready and the assertion of cei Specifies whether or not the memory port signals ce w etc are 6 registered in order to improve timing Width in bits of the tag values tag tag0 tag1 tag2 qtag qtag0 qtag1 and qtag2 respectively If true specifies that the client identified by bias should be given 7 absolute priority over the other clients 1 The a width parameter is the width of the logical address busses a a0 a1 and
237. comp asserted takes no more than 1 millisecond at a clkO frequency of 133MHz The ddrsdram training v2 component works by varying the phase of the capture clocks clkcO and clkc180 in order to find a window in which data from the SSRAM device s DQ pins can be reliably captured Hence these clocks are the same frequency as clkO etc but the required phase relationship is discovered during the training sequence ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 The signals of this interface to and from the memory device s are as follows Signal Type Function ra in Memory device address bus This bus carries address information to from the memory port to the memory device s For devices with a nontrivial addressing scheme this address may be composed of various fields These fields are bundled together into the ra bus so that for the most part the user application need not care what they are Refer to note 1 for the mapping of the ra bus to device pins rc inout Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together into the rc bus so that for the most part the user application need not care what they are Refer to note 2 for the mapping of the rc bus to device pins rd inout Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via c
238. cr simple xrc2 v2 scr simple xpl v2p scr simple xp v2p scr simple wrc2 v2 scr simple drc2 v2 scr simple xpi v2p scr simple xrc4lx v4lx scr simple xrc4sx v4sx scr simple xrc4fx v4fx scr simple xrc4fx v4fx scr simple xrce4fx v4fx scr simple xrce4fx v4fx scr simple xrcblx v5lx scr simple xrc5t1 v5fxt scr XST project file simple xrc v prj simple xrc ve prj simple xrcp v prj simple xrcp ve prj simple xrc2l v2 prj simple xrc2 v2 prj simple xpl v2p prj simple xp v2p prj simple wrc2 v2 prj simple drc2 v2 prj simple xpi v2p prj simple xrc4lx v4lx prj simple xrc4sx v4sx prj simple xrc4fx v4fx prj simple xrc4fx v4fx prj simple xrce4fx v4fx prj simple xrce4fx v4fx prj simple xrc5lIx v5lx prj simple xrcbt1 vbfxt prj UCF file simple xrc ucf simple xrc ucf simple xrcp ucf simple xrcp ucf simple xrc2l ucf simple xrc2 ucf simple xpl ucf simple xp ucf simple wrc2 ucf simple drc2 ucf simple xpi ucf simple xrc4lx ucf simple xrc4sx ucf simple xrc4fx 4vfx100 ucf simple xrc4fx 4vfx140 ucf simple xrce4fx 4vfx100 ucf simple xrce4fx 4vfx140 ucf simple xrcblx ucf simple xrcbt1 5vfxt ucf ADM XRC SDK 4 9 3 User Guide Win32 Simple ADM XRC 5T1 simple xrcbt1 v5lxt scr with LXT ADM XRC 5T1 simple xrcbt1 v5sxt scr with SXT ADM XRC 5T2 simple xrc5t2 v5fxt scr ADM XRC 5T2 ADV with FXT ADM XRC 5T2 simple xrc5t2 v5lxt scr ADM XRC 5T2 ADV with LXT ADM XRC 5T2 simple xr
239. d e When false the procedure will return if the burst is terminated and nxfered will reflect the actual number of bytes transferred e When true the procedure will perform transfers on the local bus until the desired number of bytes has been transferred In this case nxfered will be set to the length of data The address parameter specifies the starting local bus byte address of the transfer which will be incremented during the transfer It need not be aligned to the word size of the local data bus The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address The be parameter specifies the byte enables to be used for the transfer They are active high and so a 1 in a particular element of be results in a 0 in the corresponding bit of LBE The length of be must be the same as the length of data The data parameter returns the data read from the local bus For a nonmultiplexed address data bus the data comes from the LD signal wh
240. d instead since ADMXRC2 ConfigureFromFileDMA performs file I O in order to load the bitstream into memory The card to be configured is specified by the Card parameter The bitstream file to load into the FPGA is specified by the Filename parameter 434 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ConfigureFromFileDMA The Channel parameter specifies which DMA channel should be used for the operation If ADMXRC2 DMACHAN ANY is specified the DMA transfer will be performed on the first available DMA channel However pending DMA transfers on a specific a DMA channel will always be given priority It is possible for a DMA transfer that specifies ADMXRC2 DMACHAN ANY to be delayed indefinitely if all DMA channels are kept busy by other threads The Event parameter should be a valid manual reset Win32 event handle See multithreading issues for further information 435 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 DoDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 DoDMA Prototype ADMXRC2 STATUS ADMXRC2 DoDMA ADMXRC2 HANDLE ADMXRC2 DMADESC DmaDesc unsigned long Offset unsigned long Length DWORD Local ADMXRC2 DMADIR Direction unsigned int Channel DWORD DMAModeWord DWORD Flags unsigned long Timeout HANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure DmaDesc In Handle to DMA descriptor represent
241. d passing the option mclk 140 on the command line would result in the ZBT SSRAM devices on the card operating at 140 MHz and the memory clock domain within the target FPGA also operating at 140 MHz FPGA Design 65 The Memory sample application normally uses the Memory sample FPGA design VHDL but when the 64 option is specified it uses the Memory64 sample FPGA design VHDL ADM XRC SDK 4 9 3 User Guide Win32 MemoryF ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data MEMORYF sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview The MemoryF sample application performs a fast chip driven memory test that verifies the memories on a reconfigurable computing card Syntax memoryf options Options Option Type Meaning banks hexadecimal integer Bitmask of banks to test default OxFFFFFFFF Card base 10 integer ID of card to open index base 10 integer Index of card to open 66 ADM XRC SDK 4 9 3 User Guide Win32 MemoryF 1 real number Local bus clock frequency to use in MHz default depends upon type of card mclk real number Memory clock frequency to use in MHz default depends upon type of card refclk220 Do not enable Virtex 5
242. d for FPGA interrupts using the ADMXRC2_RegisterlnterruptEvent API call 2 An interrupt thread is started The interrupt thread waits in a loop for the event to be signalled Each time the event is signalled the interrupt thread wakes up and performs the following 1 Reads the ISTAT FPGA register to discover which of the 32 FPGA interrupts are pending 2 Clears all pending FPGA interrupts by writing to the ISTAT FPGA register 3 Rearms FPGA interrupts by writing a dummy value to the IARM FPGA register 4 Increments a count of FPGA interrupts received 3 Interrupts are enabled by writing to the IMASK FPGA register Once initialized the application waits for input from the user o When the user enters something other than q the application writes to a register in the FPGA which simulates some event occurring within the FPGA that generates an interrupt The interrupt thread maintains a count of how many interrupts it has handled o When the user enters q the application cleans up and displays the number of FPGA interrupts that were handled which should be equal to the number of interrupts generated The application then terminates Output from a typical run might look like Enter q to quit or anything else to generate an interrupt Interrupt thread started Enter q to quit or anything else to generate an interrupt Enter q to quit or anything else to generate an inte
243. d not match the device fitted to the card ADMXRC INVALID HANDLE is not a valid handle to a card Description This function is used to configure the FPGA on a card from a Xilinx bitstream file BIT using programmed I O If deterministic runtime is required the ADMXRC_ConfigureFromBuffer or ADMXRC_ConfigureFromBufferDMA functions should be used instead since ADMXRC ConfigureFromFile performs file I O in order to load the bitstream into memory The card to be configured is specified by the Card parameter The bitstream file to load into the FPGA is specified by the Filename parameter 512 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ConfigureFromFileDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC ConfigureFromFileDMA Prototype ADMXRC STATUS ADMXRC ConfigureFromFileDMA ADMXRC HANDLE Card char Filename DWORD Channel PHANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure Filename In Name of BIT file Channel In DMA channel to use for the operation Event In out Event to use to wait for completion Return value Value Meaning ADMXRC SUCCESS The FPGA was successfully configured ADMXRC FILE NOT FOUND The file could not be opened ADMXRC INVALID FILE The file appeared not to be a valid bitstream ADMXRC NO MEMORY There was not enough free memory to temporarily load the bitstream into memory ADMXRC FPGA MISMATCH The device targetted by the bitstre
244. d on which the FPGA and DDR SDRAM devices are mounted In general the number of physical wires on the circuit board provided for addressing the DDR SDRAM devices can be greater than the number actually used by a particular DDR SDRAM device The phase and frequency relationships between the four clock phases are illustrated by the following figure ADM XRC SDK User Guide Common Memory Ports dak dkau dk1 80 dkzru Tne E CK Also shown is the DDR SDRAM clock CK Its frequency is the same as clkO but its phase is indeterminate 8 For correction operation all sideband inputs must be static while the memory port is not idle 9 In this version the x4 sideband input must be driven with a constant The signals of this interface to and from the memory device s are as follows Signal Type ra in rc inout rd inout Row column address selection Function Memory device address bus This bus carries address information to from the memory port to the memory device s For devices with a nontrivial addressing scheme this address may be composed of various fields These fields are bundled together into the ra bus so that for the most part the user application need not care what they are Refer to note 1 for the mapping of the ra bus to device pins Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bun
245. d to the shared memory port by the arbiter 2 module is as follows Signal Type Function Note a out Memory port logical address The arbiter 2 module drives this signal with a valid address when asserts ce in order to access the memory port on behalf of a client be out Memory port byte enables The arbiter 2 module drives this signal with a valid set of byte enables when it asserts ce and w together in order to perform a write to the memory port on behalf of a client A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory ce out Memory port command entry The arbiter 2 module asserts this signal when it must access the memory port on behalf of a client When arbiter 2 asserts ce it also drives valid values on a and w Depending on whether or not W is asserted along with ce arbiter 2 also drives either tag or be and d with valid values d out Memory port write data The arbiter 2 module drives this signal with a valid set of byte enables when it asserts ce and w together in order to perform a write to the memory port on behalf of a client q in Memory port read data This signal carries the data read from the memory port as a result of arbiter 2 reading the memory port on behalf of a client It is qualified by the valid signal qtag in Memory port returned tag This signal carries the tag that accompanies d
246. d to the word size of the local data bus although an unaligned address generally makes little sense when using constant addressing The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e For a multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address After the first word of data has been transferred LBE will revert to being determined by the be parameter and on the last word of the transfer also determined by any residual bytes that do not comprise a full word of data The data parameter holds the data to be written on the local bus For a nonmultiplexed address data bus the data is output on the LD signal whereas for a multiplexed address data bus the data is output on the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes written on the local bus 400 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write demand ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference pl
247. data from memory qi When validi is asserted is asserted by the memory port as a result of a read command qi reflects the data read from memory qtagO out Client tag out qtag1 When validi is asserted by the memory port as a result of a read command qtag reflects the tag value that was assocated with that read command 297 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 2 readyO ready1 req tag0 tag validO valid1 wO out out Notes 298 8 In order for a client to be able to correctly identify data from its own read commands a client must use a set of tags that is completely disjoint from the set of tags used by another client For example if client 0 uses the set of 4 bit tags 0000 0001 0010 then no other client may use those tags If client 1 uses the set of tags 0100 0101 0110 0111 then there is no risk that client O s reads Client ready When readyi is asserted a client is permitted to assert cei The readyi signal for a client is asserted when two conditions are met the arbiter grants access to the memory port for that client and the memory port itself is asserting ready Client request A client asserts reqi in order to request access to the memory port When the arbiter grants access to the client it will assert readyi Client tag in note 8 When a client asserts cei with wi deasserted it must also place a valid tag on the tagi signal When as a
248. dding the above penalties to the best case latency The optimal usage pattern for this memory port is blocks of accesses of the same type read or write with addresses that increment by one on each successive access When used optimally this memory port with 32 physical data bits rd is 32 operating at a clkO frequency of 133MHz can sustain approximately 2GB s 354 ADM XRC SDK 4 9 3 User Guide Win32 zbtsram port ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The zbtsram port component Overview HDL source code Parameters Signals Performance Overview The zbtsram port component is part of the memif package and implements an interface to a bank of DDR II SSRAM memory This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure a a width 1 0 My tagtag idth 1 0 width 1 0 annlicati be d width a 1 rc rc width 1 0 memary pplication did idth 1 0 re rd aith 1 0 exice s pipeline gid width 1 0 ntac tag width 1 0 valid ready zbtsram port HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation 355 ADM XRC SDK 4 9 3 User Guide Win32 zbtsram port fpga vhdl common memif memif pkg vhd fpga vhdl common memif me
249. ddma out t Idack 1 lt 02 gt lacbuz dama in t Idreg 1 0 gt Stimulus process n Local bus FPGA design unit under test agent LOCAL BUS 0 388 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read const demand Before calling this procedure a stimulus process should ensure that the FPGA ie the unit under test has asserted LDREQ3 This can be accomplished by calling plxsim wait demand before calling plxsim read const demand When called the procedure will continue to perform transfers until one of two conditions is met 1 The FPGA unit under test deasserts LDREQ in order to pause the DMA transfer or 2 All of the data has been transferred the length of the data vector specifies how many bytes must be transferred During the transfer s LDACK will be asserted with the proper timing with respect to LADS etc The order parameter specifies the width of the local data bus Valid values are e 2 for a 32 bit local data bus e for a 64 bit local data bus The address parameter specifies the local bus byte address of the transfer which will not be incremented during the transfer The address need not be aligned to the word size of the local data bus although an unaligned address generally makes little sense when using constant addressing The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2
250. de Win32 ADMXRC2 Read ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 Read Prototype ADMXRC2 STATUS ADMXRC2 Read ADMXRC2 HANDLE Card ADMXRC2 IOWIDTH Width DWORD Flags DWORD Local void Buffer unsigned long Length Arguments Argument Type Purpose Card In Handle of card from which the read is to take place Width In Width of operation Flags In Miscellaneous flags Local In Local bus address at which to begin reading Buffer Out Buffer to receive data read Length In Number of bytes to read Return value Value Meaning ADMXRC2 SUCCESS The data was read successfully ADMXRC2 INVALID HANDLE Card is not a valid handle to a card ADMXRC2 INVALID PARAMETER An invalid parameter was passed Description The ADMXRC2 Read function reads a number of bytes from the local bus using direct slave cycles or from the PLX registers The local bus space encompasses FPGA space the FPGA flash memory and the control registers The Width parameter specifies the width of the operation and must be one of the values from the enumerated type ADMXRC2 IOWIDTH The Flags parameter modifies the semantics of the operation Normally the read is performed in local bus space with an incrementing address but this behavior can be modified by any combination of the following Flag Meaning ADMXRC2 IOFIXED The local bus address is not incremented during the transfer 456 ADM XRC SDK 4 9 3 User Guide Win32 AD
251. der test The arrangement is shown here in simplified form lachus out t Demand Idack_ lt 0 gt me ni pA Stimulus process 0 Local bus FPGA design agent LOCAL BUS 0 unit under test The following procedures output a signal of type locbus ddma out t e plxsim read const demand 369 ADM XRC SDK 4 9 3 User Guide Win32 locbus ddma out t e plxsim read demand e plxsim write const demand e plxsim write demand Since it is an opaque datatype the members of locbus ddma out t should not be accessed as they are subject to change in future versions of the PLXSIM package 370 ADM XRC SDK 4 9 3 User Guide Win32 locbus in t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus in t Declaration Synopsis Description Declaration type locbus in t is record end record Synopsis locbus in t is an opaque record type used to bundle together the signals required for local bus transfers Description 371 Alocbus agent nonmux locbus agent mux32 or locbus agent mux64 component connected to the local bus outputs a signal of type locbus in t The stimulus process then uses this signal in calls to the procedures provided by the PLXSIM package in order to perform local bus transfers The arrangement is shown here in simplified form locbus nut FPGA design jj unit under tes t St
252. dled together into the rc bus so that for the most part the user application need not care what they are Refer to note 2 for the mapping of the rc bus to device pins Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via ce two words are transferred on rd which determines the relationship between the rd width and d width parameters Refer to note 3 for details The row and col sideband inputs together determine the number address bits used for row and column addresses as in the following table row 1 0 col 1 0 15 of row bits used No of column bits used ADM XRC SDK User Guide Common Memory Ports 00 00 12 8 00 01 12 9 00 10 12 10 00 11 12 11 01 00 13 9 01 01 13 10 01 10 13 11 01 11 13 12 10 00 14 10 10 01 14 11 10 10 14 12 10 11 14 13 11 00 15 11 11 01 15 12 11 10 15 13 11 11 15 14 Performance 16 This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal Most of the time the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application Periodically however the memory port must refresh the DDR SDRAM devices it is controlling which may result in an accumulated backlog of buffered commands and deassertion of the ready signal Certain usage patterns such as alternating between read and wri
253. dling a local bus cycle It may be asserted for two reasons 1 There is no cycle in progress on the local bus 2 There is a cycle in progress on the local bus but the qlads signal was not asserted at the beginning of the cycle meaning that the FPGA determined that it was not the target of the local bus cycle LBLAST in This input must be driven by an active high version of the LBLAST signal from the local bus LBTERM in This input must be driven by an active high version of the LBTERM signal from the local bus LBTERM out This output must drive the LBTERM signal on the local bus whenever Ibterm oe l is asserted LBTERM output enable Whenever this output is asserted logic 0 the FPGA must drive the LBTERM pin with the current value of the Ibterm_o_ output LD LAD output enable This is an active low output enable signal for the LAD LD pins When asserted logic 0 the LAD LD pins should be driven by the FPGA LREADY out This output must drive the LREADY signal on the local bus whenever the oe l is asserted LREADY output enable Whenever this output is asserted logic 0 the FPGA must drive the LREADY5 pin with the current value of the Iready 1 output LWRITE in This input must be driven by the LWRITE signal from the local bus Qualified address strobe This input should be pulsed for one clock cycle when a local bus cycle begins This signal is typically generated by qualifying the
254. dma xrc4lx do vsim do do ddma xrc4fx do vsim do do ddma xrce4fx do vsim do do ddma xrc5 do Refer to the following table for the ADM XRC SDK 4 9 3 User Guide Win32 ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 90 vsim do do ddma xrc5 do vsim do do ddma xrc5 do vsim do do ddma xrc5 do vsim do do ddma xrc5 do ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DDMA64 sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL 2vP20 2VP30 only ADM XP a ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location ADMXRC_SDK4 fpga vhdl ddma64 Synopsis 91 ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 The DDMA64 FPGA design demonstrates demand mode DMA with local bus bursting in 64 bit mode Data is read from an application buffer in host memory and then simply written back to another application buffer unchanged a loopback o
255. dress 0x18 This register indicates whether or not training of memory banks has been successful The precise bit field definitions depend upon the model in use Bits Mnemonic Type Function ADM XRC 4FX ADPE XRC 4FX and ADM XRC 5LX 3 0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 31 4 RO MBZ Reserved ADM XRC 5T1 1 0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 2 SSRAM RO This field returns 1 if the DDR II SSRAM port has completed training successfully otherwise 0 31 3 RO MBZ Reserved ADM XRC 5T2 and ADM XRC 5T2 ADV 3 0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 5 4 SSRAM RO This field returns 1 in a bit position if the corresponding DDR II SSRAM port has completed training successfully otherwise 0 31 6 RO MBZ Reserved Memory bank mode registers MODEO MODE15 local bus address 0x40 0x7C There are a total of 16 MODE registers occupying local bus addresses 0x40 to 0x7C inclusive The interpretation of the fields in a mode register depends upon the type of memory that the register corresponds to ZBT SSRAM Bits Mnemonic Type Function 0 PIPELINE R W When this field is 0 the memory port expects the ZBT SSRAM to be operating in f
256. e Index was out of range The ADMXRC2 ReadConfig function reads the EEPROM on an ADM XRC series card This function is intended for advanced users who need to change the configuration of their card from the factory defaults The Index parameter specifies the index of the EEPROM location to read The Value parameter must point to the variable that is to receive the value read from the specified location The number of EEPROM locations and the width in bits of each location is dependent on the board type The value returned is the data read from the specified EEPROM location zero extended by adding MSBs to 32 bits The table below shows EEPROM size and width for each supported card Card Number of locations ADM XRC 64 ADM XRC P 64 ADM XRC II Lite 64 ADM XRC II 256 ADM XPL 256 458 Bit width of locations 16 16 16 16 32 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ReadConfig ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 459 256 256 256 256 256 256 256 256 256 256 256 256 256 256 32 16 16 32 16 16 32 32 32 32 32 32 32 32 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 RegisterInterruptEvent ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 RegisterlnterruptEvent Prototype ADMXRC2 STATUS ADMXRC2 RegisterInterruptEvent ADM
257. e in a FIFO or some other buffer in order to allow demand mode DMA to proceed If there is the FPGA asserts request o For writes the FPGA must typically determine whether or not there is sufficient space for further data in some FIFO or buffer in order to allow demand mode DMA to proceed If there is the FPGA asserts request 4 To add an additional demand mode DMA channel everything within the shaded area of the above figure should be replicated and a different LDACK and LDREQ pair chosen 269 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm2 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The plxddsm2 component Overview HDL source code Signals Usage Overview NOTE this component supersedes the plxddsm component The plxddsm2 component is part of the localbus package and provides the control mechanism for a demand mode DMA channel in a local bus interface within an FPGA design This component cannot be used in isolation it cooperates with the plxdssm component in order to provide a complete local bus interface with the capability to perform demand mode DMA qlads Iblast to from to from Ibterm Local Bus user ready pins application Idreq_o_l plxddsm2 HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common localbus localbus pkg vhd fpga vhdl common localbus plxddsm2 vhd Signals Th
258. e met the arbiter grants access to the memory port for that client and the memory port itself is asserting ready Client request A client asserts reqi in order to request access to the memory port When the arbiter grants access to the client it will assert readyi Client tag in note 8 When a client asserts cei with wi deasserted it must also place a valid tag on the tag signal When as a result of the read command the memory port asserts validi the qtagi output reflects the tag value originally passed Client read data valid note 9 When validi is asserted by the memory port it is as a result of a read command client asserted cei with wi deasserted When validi is asserted both qi and qtagi are valid Client write select When a client asserts cei it must place either a logic 1 on the wi signal in order to select a write command or 0 in order to select a read command 8 In order for a client to be able to correctly identify data from its own read commands a client must use a set of tags that is completely disjoint from the set of tags used by another client For example if client 0 uses the set of 4 bit tags 0000 0001 0010 then no other client may use those tags If client 1 uses the set of tags 0100 0101 0110 0111 then there is no risk that client O s reads ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 can be confused for client 1 s reads and vice versa 9 The validO valid1
259. e two words are transferred on rd which determines the relationship between the rd width and d width parameters Refer to note 3 for details Row column address selection The row and col sideband inputs together determine the number address bits used for row and column addresses as in the following table row 1 0 col 1 0 No of row bits used No of column bits used 00 00 12 8 00 01 12 9 00 10 12 10 00 11 12 11 01 00 13 01 01 13 us 01 10 13 11 01 11 13 12 10 00 14 10 10 01 14 11 10 10 14 12 10 11 14 13 11 00 15 11 11 01 15 12 11 10 15 13 11 11 15 14 331 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 Performance This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal Most of the time the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application Periodically however the memory port must refresh the DDR SDRAM devices it is controlling which may result in an accumulated backlog of buffered commands and deassertion of the ready signal Certain usage patterns such as alternating between read and write commands may also have the same effect The architecture of DDR SDRAM device consists of a number of internal banks which are in turn divided into a number of pages At any moment a given bank may be closed or may have a given page open Opening or closing a
260. e DMA transfers In other words the FIFO is visible over the entire FPGA space during demand mode DMA transfers There are two write only registers that reside in the FPGA direct slave space These registers must be written by the host with a DMA transfer count that matches the size of the DMA transfer being performed prior to the host starting the DMA transfer Note that these registers cannot be inadvertantly overwritten by demand mode DMA transfers as the design qualifies FPGA register accesses using LDACK 1 0 Inbound count register ICOUNT local bus address 0x0 Bits Mnemonic Type Function 1 0 MBZ 31 2 N WO Inbound DMA transfer count in 32 bit words The inbound count register ICOUNT specifies how many words will be transferred in the next DMA transfer in channel 0 in order to transfer data into the FPGA s FIFO When ICOUNT N is zero the FPGA will not assert LDREQ 0 The FPGA decrements ICOUNT N whenever a word of data is transferred on DMA channel 0 Outbound count register OCOUNT local bus address 0x4 Bits Mnemonic Type Function 1 0 MBZ 31 2 N WO Outbound DMA transfer count in 32 bit words The outbound count register OCOUNT specifies how many words will be transferred in the next DMA transfer in channel 1 in order to transfer data into the FPGA s FIFO When OCOUNT N is zero the FPGA will not assert LDREQ 1 The FPGA decrements OCOUNT N whenever a word of data is transferred on DMA channel 1 Source files For
261. e In Bitstream image to unload Return value Value Meaning ADMXRC2 SUCCESS The bitstream file was successfully unloaded Description This function frees the memory used to hold the SelectMap data of an FPGA bitstream Image should be a value of type ADMXRC2 IMAGE obtained from an earlier call to ADMXRC2_LoadBitstream 470 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 UnregisterInterruptEvent ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 UnregisterlnterruptEvent Prototype ADMXRC2 STATUS ADMXRC2 UnregisterInterruptEvent ADMXRC2 HANDLE Card HANDLE Event Arguments Argument Type Purpose Card In Handle of card to which Event is registered Event In Specifies the event to unregister Return value Value Meaning ADMXRC2 SUCCESS The event was successfully unregistered ADMXRC2 INVALID HANDLE Card is not a valid handle to a card or Event is not a valid Win32 event handle Description This function unregisters a Win32 event previously registered with ADMXRC2 RegisterlnterruptEvent so that the event will no longer be signaled when an FPGA interrupt occurs The Event parameter should be the handle of the Win32 event to unregister 471 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 UnsetupDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 UnsetupDMA Prototype ADMXRC2 STATUS ADMXRC2_UnsetupDMA ADMXRC2_HANDLE Card ADMXRC2
262. e LDREQ pins on the local bus LREADY in This input must be driven by an active high version of the LREADY signal from the local bus Qualified address strobe This input should be pulsed for one clock cycle when a local bus cycle begins This signal is typically generated by qualifying the LADS signal by simple address decoding along with the corresponding LDACK signal In most cases the FHOLDA signal is also used Data ready The user application should assert this signal when it is ready to transfer data during a local bus cycle This signal should be the same as the ready signal that is input to the associated plxdssm instance Request demand mode DMA local bus cycle 1 2 This signal is ignored when a demand mode DMA local bus cycle is in progress The user application should assert this signal when it wishes to initiate a demand mode DMA cycle If request is asserted while no demand mode DMA local bus cycle is in progress plxddsm2 will assert o request should be held asserted until the requested demand mode DMA cycle occurs and may be held asserted over multiple demand mode DMA cycles if desired Asynchronous reset This port may be driven by an asynchronous reset for the local bus interface or tied to logic O if not required Synchronous reset This port may be driven by a synchronous reset for the local bus interface or tied to logic O if not required ADM XRC SDK 4 9 3 User Guide Win32
263. e a bundle of the local bus signals that are driven by a stimulus process Purpose A constant that can be used to initialize variables signals of type locbus ddma out t A constant that can be used to initialize variables signals of type locbus out t ADM XRC SDK User Guide PLXSIM Package Name conv byte vector conv integer conv integer signed conv integer unsigned conv std logic vector conv string conv string hex plxsim read plxsim read const plxsim read const demand plxsim read demand plxsim request bus plxsim wait cycles plxsim wait demand plxsim write plxsim write const plxsim write const demand plxsim write demand Components Name Ibpcheck locbus agent ddma locbus agent mux32 locbus agent mux64 locbus agent nonmux 18 Purpose A function for converting values to the byte vector t type A function for converting values to the integer type A function for converting signed binary values to the integer type A function for converting unsigned binary values to the integer type A function for converting values to the std logic vector type A function for converting values to the string type A function for converting values to the string type in hexadecimal form A procedure for performing a basic read transfer on the local bus A procedure for performing a basic read transfer with constant local address on the local bus A procedure for performing a basic demand mode DMA read transfer
264. e a multiple of 2 533 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ReadReg ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC ReadReg Prototype ADMXRC STATUS ADMXRC ReadReg ADMXRC HANDLE unsigned char Index unsigned char Value Arguments Argument Type Purpose Card In Handle of card on which the read is to take place Index In Index of control register to read Value Out Byte read from control register Return value Value Meaning ADMXRC SUCCESS The data was read successfully ADMXRC INVALID HANDLE Card is not a valid card handle ADMXRC INVALID PARAMETER Index was out of range Description The ADMXRC ReadReg function reads the byte wide control registers on an ADM XRC or ADM XRC P card The Index parameter specifies the index of the register to read Please refer to the user manual for your card for a map of the control registers The Value parameter must point to the variable that is to receive the value read from the specified register 534 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC RegisterInterruptEvent ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC RegisterlnterruptEvent Prototype ADMXRC STATUS ADMXRC RegisterInterruptEvent ADMXRC HANDLE Card HANDLE Event Arguments Argument Type Purpose Card In Handle of card for which to register the event Event In Specifies the event to register for interrupts
265. e array of page addresses may used by the FPGA in order to 528 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC MapbDirectMaster allow the FPGA to perform direct master access to the user buffer represented by DmaDesc It is up to the application programmer to provide a mechanism by which the returned PCI page addresses are transferred to the FPGA A simple mechanism is a bank of registers within the FPGA the host simply writes the PCI page addresses to these registers using direct slave transfers Prior to calling ADMXRC MapDirectMaster the MaxPages and PagesPci members must be initialized by the application PagesPci should point to an application allocated buffer that will receive the PCI addresses of the pages comprising the specified region of the application buffer This region is specified by the Offset and Length parameters MaxPages should be initialized to the number of unsigned long elements in the array that PagesPci points to If ADMXRC MapbDirectMaster succeeds the PageLength PagesSpanned BytesSpanned and InitOffset members of the ADMXRC_BUFFERMAP that Map points to will be filled in with valid values It is possible that the number of pages in the array Map gt PagesPci will not be sufficient to map the entire region specified by Length and Offset There are two cases e MaxPages is equal to or greater than the actual number of pages spanned by the region in the user buffer specified by Length and Offset The function will map a
266. e current transfer Assuming that a Direct Slave transfer is in progress asserting stop may or may not cause Ibterm o 1 to be asserted on the next cycle depending on whether or not ready has already been asserted This signal indicates that the state machine is currently idle idle is never asserted at the same time as decode or transfer This signal indicates that a new Direct Slave transfer has started and that the user application should perform address decoding based upon a registered version of the local bus address It is a single cycle pulse that occurs one cycle after qlads is asserted decode also indicates that PLXDSSM is now sensitive to the ready and stop signals This signal indicates whether the current Direct Slave transfer is a read 0 or a write 1 It changes only on cycles when qlads is asserted This signal indicates that data is being transferred in the current cycle and mirrors Iready 1 except that it is active high whereas o lis active low Clock enables for data registers are typically derived from this signal Further explanation of the relationship between the ready stop Iready o and Ibterm o 1 signals is warranted The following rules govern their behavior ready and stop are ignored by PLXDSSM when no Direct Slave transfer is in progress The earliest that ready and stop are checked is when decode is asserted If a Direct Slave transfer is in progress asserting ready will result in t
267. e design divides the FPGA space into a lower 2MB region for registers and an upper 2MB window for accessing the memory A bank register selects which bank is currently being accessed and a page register is provided so that all of a large memory bank can be accessed even though the window through which it is accessed is 2MB in size The user application on the other hand has no such restrictions It can access all banks of memory simultaneously without need for page or bank selection Explanation of memory_main module 138 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 The following is a block diagram of the memory main module which is not specific to any model and has been written in such a way that it expects to be wrapped up by a model specific wrapper It implements the local bus interface and the FPGA registers It also contains the one and only instance of the memory banks module as well as the one and only instance of the user app module local bus dock domain memory fuser dock domain LADS LBLAST etc LREAD Y LBETERM plxdssm user cortrol cortrol user app control address data tag etc for all banks data from memories bank register page register Registers memory config LBE in Q EBENEN byte enablesto memories Z memory main The memory main module As a brief aside the wrapper for the module memory main is model specific and is also the top level of the des
268. e following the final cycle of a read For simplicity a master may elect to also apply this rule to writes 231 ADM XRC SDK 4 9 3 User Guide Win32 DMA transfers ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DMA transfers DMA Direct Memory Access is an efficient way to transfer a block of data into the host computer s memory with as little burden on the CPU as possible Bus mastering PCI devices contain dedicated logic for performing DMA transfers To perform a DMA transfer the CPU first programs the PCI device s registers where to transfer the data how much data to transfer and which direction the data should travel in It then kicks off the DMA transfer and typically the CPU is interrupted by the device once the transfer has been completed The advantage of DMA then is that the CPU can perform other tasks while the PCI device performs the data transfer Alpha Data recommends using DMA transfers that is performed by the PCI device for large blocks of data and using Direct Slave transfers that is performed by the CPU for random access or for access to FPGA registers On many platforms having the CPU perform bulk data transfer is highly inefficient For example most x86 chipsets do not perform bursting at all when the CPU performs reads of a PCI device The local bus bridge PCI9080 PCI9656 etc in an ADM XRC series card contains one or more DMA engines Software running on the host can use these DMA
269. e memory port is able to accept commands When ready is zero the ce signal must be deasserted In addition to the generic memory port signals a particular type of memory port may have one or more sideband signals that are specific to that particular type of memory port In the above figure the ddr2sdram port module has four sideband signals that specify the paramters of the memory devices that it is controlling They are row col bank and pbank and their values are determined by the bit fields in the MODE register that is described above for the case of a DDR II SDRAM memory bank Explanation of user app module The user app module is intended to be a starting point for the end user to add his or her own logic to perform some useful data processing function As shipped in this SDK it contains logic to perform a chip driven memory test of all banks of on board memory See the MemoryF example application for details on how to run the chip driven memory test 125 ADM XRC SDK 4 9 3 User Guide Win32 Memory out 038 reg 256 offset registero memory testa 0 m 0 B i 0 length registerg RUN length O aro 7 64 16 128 be 0 vaid 0 252 ready 0 2016 done 0 2032 error 0 1543 1536 ephase 0 to arbiter_2 instances in 1055 1024 d eaddr memory banks offset register memory test offset 1 rea ce 1 we a 1 taa 1 91 be 1 a1 valid 1 ready
270. e physical data width 4 The latency parameter is the minimum number of consecutive clock cycles that a particular client is awarded access to the memory port without being interrupted by another unfavored client The purpose of this parameter is to enable a reasonable efficiency to be achieved for memory types that benefit from bursting and locality of access for example DDR and DDR II SDRAM Note however that if unfair is true and the favored client requests access to the memory port the favored client will be granted access to the memory port regardless of the value of latency and regardless of any unfavored clients 5 The ready delay parameter specifies the timing relationship between a client s readyi signal and its cei signal ready delay must be at 295 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 2 least 0 and no greater than 4 The following figures illustrate this relationship req access granted here by erbiter access lost here readyO earliest possible assertion latest possible deassertion of cel of ce Relationship between readyO and ce0 when ready delay 0 req access granted here by erbiter access lost here readyO earliest possible assertion latest possible deassertion of ce of cel Relationship between readyO and when ready delay 1 0 granted he
271. e reversed data register REVDATA local bus address 0x0 Bits Mnemonic Type Function 31 0 VAL R W When read this register returns the nibble reversed version of the last value written to it Nibble reversed data register DATA local bus address 0x4 Bits Mnemonic Type Function 31 0 VAL R W When read this register returns the last value written to it Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with simple xrc v scr simple xrc v prj simple xrc ucf Virtex ADM XRC with simple xrc ve scr simple xrc ve prj simple xrc ucf Virtex E ADM XRC P with simple xrcp v scr simple xrcp v prj simple xrcp ucf Virtex ADM XRC P with simple xrcp ve scr simple xrcp ve prj simple xrcp ucf Virtex E ADM XRC II Lite simple xrc2l v2 scr simple xrc2l v2 prj simple xrc2l ucf ADM XRC II simple xrc2 v2 scr simple xrc2 v2 prj simple xrc2 ucf ADM XPL simple xpl v2p scr simple xpl v2p prj simple xpl ucf ADM XP simple xp v2p scr simple xp v2p prj simple xp ucf ADP WRC II simple wrc2 v2 scr simple wrc2 v2 prj simple wrc2 ucf ADP DRC II simple drc2 v2 scr simple drc2 v2 prj simple drc2 ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC P projnav rcp device ADM XRC I Lite projnav xrc2l
272. e signals of this interface to and from the user application are as follows Signal Type Function Note burst in Allow bursting during demand mode DMA local bus cycle 1 This signal is ignored unless a local bus cycle is in progress If this signal is asserted while a demand mode DMA local bus cycle is in progress Idreq o 1 remains asserted If this signal is deasserted while a demand mode DMA local bus cycle is in progress Idreq o lis deasserted 270 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm2 clk idle Iblast Ibterm Idreq o lready qlads ready request rst sr 271 in out in in Local bus clock This port must be driven by the clock that drives the local bus interface of the FPGA design Interface idle This status output indicates whether or not the plxddsm2 instance is currently handling a demand mode DMA local bus cycle It may be asserted for two reasons 1 There is no cycle in progress on the local bus 2 There is a cycle in progress on the local bus but the qlads signal was not asserted at the beginning of the cycle meaning that the FPGA determined that it was not the target of a demand mode DMA local bus cycle LBLAST in This input must be driven by an active high version of the LBLAST signal from the local bus LBTERM in This input must be driven by an active high version of the LBTERM signal from the local bus LDREQ out This output must drive one of th
273. e tag value that was assocated with that read command Client ready When readyi is asserted a client is permitted to assert cei The readyi signal for a client is asserted when two conditions are met the arbiter grants access to the memory port for that client and the memory port itself is asserting ready Client request A client asserts reqi in order to request access to the memory port When the arbiter grants access to the client it will assert readyi Client tag in note 8 When a client asserts cei with wi deasserted it must also place a valid tag on the tagi signal When as a result of the read command the memory port asserts validi the qtagi output reflects the tag value originally passed Client read data valid note 9 When validi is asserted by the memory port it is as a result of a read command client asserted cei with wi deasserted When validi is asserted both qi and qtagi are valid Client write select When a client asserts cei it must place either a logic 1 on the wi signal in order to select a write command or 0 in order to select a read command 8 In order for a client to be able to correctly identify data from its own read commands a client must use a set of tags that is completely disjoint from the set of tags used by another client For example if client 0 uses the set of 4 bit tags 0000 0001 0010 then no other client may use those tags If client 1 uses the set of tags 0100 0
274. e the current local bus cycle 252 ADM XRC SDK 4 9 3 User Guide Win32 LEOT mode terminates immediately also ending the DMA transfer This is the simplest way to guarantee that no extra data is transferred after the assertion of LEOT 253 ADM XRC SDK 4 9 3 User Guide Win32 Arbitration ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Local bus arbitration The local bus protocol permits multiple master capable agents to reside on the local bus The bus arbiter on an ADM XRC series card permits at most one master capable agent on the local bus to be a master at any time This section describes the arbitration protocol Each master capable agent on the local bus has a pair of signals HOLD and HOLDA These are not bussed to other agents each agent has its own pair These signals work as follows e HOLD is driven by a local bus agent to the arbiter and must be asserted when that agent wishes to initiate one or more bursts on the local bus e HOLDA is driven by the bus arbiter to a local bus agent and is asserted when ownership of the bus is granted to that agent e The length of its tenure on the local bus is at the discretion of an agent and a local bus agent must voluntarily give up the bus by deasserting its HOLD signal when it has finished On some models sideband signals connected between agents can cause a master to relinquish the bus at the request of another agent e Once an agent deassert
275. e top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory devices are in use Signals The signals of this interface to and from the user application are as follows Signal Type Function Note 317 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port a bank be ce clkO clk2x0 clk2x90 clk45 col 318 in in Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as a linear array of words of width d_width this address is a logical address rather than anything resembling what one might see on the ra bus Bank address width select sideband signal 6 8 This input selects number of internal bank address bits for the DDR II SDRAM devices in use 00 gt no internal bank address bits 01 gt 1 internal bank address bits 10 gt 2 internal bank address bits 11 gt 3 internal bank address bits Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory Command entry User code asserts this signal to enter a new read or write command into the memory port When asserted
276. e value OXFFFFF USER48 The USER48 register indicates on which phase the memory test failed for banks 0 to Bits Mnemonic Type Function 7 0 EPHASEO RO If ERROR O0 is 1 indicates on which phase the memory test for bank 0 failed 136 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 15 8 EPHASE1 RO If ERROR 1 is 1 indicates on which phase the memory test for bank 1 failed 23 16 EPHASE2 RO If ERROR 2 is 1 indicates on which phase the memory test for bank 2 failed 31 24 EPHASES RO If ERROR S is 1 indicates on which phase the memory test for bank 3 failed USER49 The USER48 registers indicates on which phase the memory test failed for banks 4 to 7 Bits Mnemonic Type Function 7 0 EPHASE4 RO If ERROR 4 is 1 indicates on which phase the memory test for bank 4 failed 15 8 5 RO If ERROR 5 is 1 indicates on which phase the memory test for bank 5 failed 23 16 EPHASE6 RO If ERROR 6 is 1 indicates on which phase the memory test for bank 6 failed 31 24 EPHASE7 RO If ERROR 7 is 1 indicates on which phase the memory test for bank 7 failed USER50 The USERBO register indicates on which phase the memory test failed for banks 8 to 11 Bits Mnemonic Type Function 7 0 EPHASE8 RO If ERROR 8 is 1 indicates on which phase the memory test for bank 8 failed 15 8 EPHASE9 RO If ERROR 9 is 1 indicates on which phase the memory test for bank 9 failed 23 16 EPHASE10 RO If ERROR 10 is 1 indicates on which p
277. e version or admxrcd lib Debug version 5 Click OK to apply the changes 33 ADM XRC SDK 4 9 3 User Guide Win32 MSVC IDE per project options ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Configuring the MSVC IDE per project options This section assumes that that the ADM XRC SDK has been installed in the default location namely C NADMXRC SDK4 9 3 Altering the global MSVC options may not desirable In this case the ADM XRC API header and library files may be added to the search paths on a per project basis To do this follow these steps 1 Select Project Settings from the menu Ensure that the correct project is highlighted on the left hand side of the Project Settings dialog box 2 Select the configuration s you want to change Win32 Debug Win32 Release or All Configurations from the Settings for list 3 Select the tab and then select Preprocessor from the Category list 4 Add the path C NADMXRC SDK4 9 3Ninclude to the Additional include directories field 5 Select the Link tab and then select Input from the Category list 6 Add the path C ADMXRC_SDK4 9 3 lib msvec to the Additional library path field 7 Add the API library to the list of lib files in the Object Library modules field This must be admxrc lib to use the Release version or admxrcd lib to use the Debug version 8 Click OK to apply the changes which will require the project to be compl
278. ead commands is fairly deterministic since the penalties described above are limited to one cycle although these penalties may be accumulated by successive commands The best case latency from entry of a read command ce asserted with w deasserted to valid asserted is approximately 10 cIkO cycles Worst case latencies may be computed by adding the above penalties to the best case latency The optimal usage pattern for this memory port is blocks of accesses of the same type read or write with addresses that increment by one on each successive access When used optimally this memory port with 32 physical data bits rd is 32 operating at a clkO frequency of 133MHz can sustain approximately 1GB s 344 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram training v2 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sram training v2 component Overview HDL source code Parameters Signals Performance Overview The ddr2sram training v2 component is part of the memif package and implements the training algorithm for one or more instances of the ddr2sram port v2 component torom infrastructure trained totom or more memory ports ddr2sram_training_v2 This module works by sweeping the phase of a capture clock clkc0 which clocks data from the memory devices into the FPGA s IOBs from 180 degrees to 180 degrees During the sweep the associated memory ports that are being trained are instruct
279. eady and cei 7 If the unfair parameter is true the client identified by the bias parameter is given priority access to the memory port This overrides the latency parameter meaning that the favored client can interrupt a burst of memory accesses by one of the unfavored clients Signals The arbiter 4 module has the following infrastructure ports Signal Type Function Note clk in Clock All other signals except rst are synchronous to clk rst in Asynchronous reset This port should be mapped to the asynchronous reset signal if there is one or to a constant logic 0 signal if an asynchronous reset is not required sr in Synchronous reset This port should be mapped to the synchronous reset signal if there is one or to a constant logic 0 signal if a synchronous reset is not required The interface presented to clients by the arbiter_4 module is as follows Signal Type Function Note a0 in Client logical address al a2 A client must place a valid address on ai when it asserts cei a3 bed in Client byte enables to memory be1 be2 A client must place valid byte enables on bei whenever a write be3 command is entered cei and wi both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory 310 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 ce0 2 ce3 reqo req1
280. earlO bit reario Demonstrates use of the rear panel I O connector Simple Simple Simple bit simple Demonstrates direct slave access by host Simple64 Simple64 bit simple64 registers in the FPGA ADM XRC SDK 4 9 3 User Guide Win32 Clock ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Clock utility Model support Overview Command line syntax Description FPGA design Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview The Clock utility serves two purposes e Programming the onboard clock generators on a reconfigurable computing card with an arbitrary clock frequency e Measuring the approximate frequencies of the clocks present at the various clock inputs on a reconfigurable computing card Syntax 43 ADM XRC SDK 4 9 3 User Guide Win32 Clock clock options clock input frequency Options Option Argument type Meaning card base 10 integer ID of card to open index base 10 integer Index of card to open measure Disables measurement of approximate frequency measure Enables measurement of approximate frequency default Description 44 When run with no arguments the Clock utility displays a list of clock inputs and their 1 based indices For example on
281. easserted it must also place a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command The signals of this interface to and from the memory device s are as follows Signal 283 Type Function ADM XRC SDK 4 9 3 User Guide Win32 Memory interface package VHDL ra 284 in inout inout Memory device address bus This bus carries address information to from the memory port to the memory device s For devices with a nontrivial addressing scheme this address may be composed of various fields These fields are bundled together into the ra bus so that for the most part the user application need not care what they are For example with SDRAM devices this bus may sometimes carry a column address and at other times row and bank addresses The correspondence between bits of ra and the various pins found on a
282. ecify demand mode in the mode word for a DMA transfer This is done using the ADMXRC2 BuildDMAModeWord function The mode word that includes demand mode can then be supplied in a call to ADMXRC2 DoDMA for example Demand mode may be freely mixed with the other DMA modes such as constant address mode and LEOT mode To use demand mode e The host must specify ADMXRC2 DMAMODE DEMAND in a call to ADMXRC2 BuildDMAModeWord The mode word that includes demand mode can then be supplied in a call to ADMXRC2 DoDMA and ADMXRC2_DoDMAImmediate e The FPGA must drive the LDREQ signals and monitor the LDACK signals The LDREQ and LDACK signals actually comprise pairs of request acknowledge signals one pair per DMA engine in the PCI to local bus bridge on an ADM XRC series card They work as follows 1 Asserting a particular bit of LDREQ requests that the corresponding DMA engine transfer some data 2 When the local bus bridge performs a burst in response to that request it asserts the corresponding bit of LDACK 3 The FPGA can stop the transfer pausing the DMA engine by deasserting LDREQ Once paused the DMA engine will not attempt to transfer more data until the FPGA reasserts LDREQ This following topics illustrate the local bus protocol when demand mode DMA is used Demand mode DMA burst read LDREQ kept asserted Demand mode DMA burst read LDREQ deasserted to pause transfer Demand mode DMA single word read LDREQ deasserted ear
283. eclaration typedef enum ADMXRC SYNCMODE ADMXRC SYNC CPUTOFPGA 0 1 ADMXRC SYNC FPGATOCPU 0x2 ADMXRC2 SYNCMCDE Description The ADMXRC_SYNCMODE type is used with the ADMXRC SyncDirectMaster function to specify the direction in which changes made to a buffer must be propagated across any hardware level caches or write buffers Value Meaning ADMXRC SYNC CPUTOFPGA Indicates that the CPU has modified a buffer that the FPGA is expected to access ADMXRC SYNC FPGATOCPU Indicates that the FPGA has modified a buffer that the CPU is expected to access 569
284. ectly to the clkcO ports of one or more instances of ddrsdram port v2 and is used to clock data read from the DDR SDRAM devices into the FPGA s IOBs clkc180 out Capture clock phase 180 4 This clock is the same frequency as clkcO but 180 degrees out of phase and should be connected directly to the clkc180 ports of one or more instances of ddrsdram_port_v2 It is used to clock data read from the DDR SDRAM devices into the FPGA s IOBs rst in Asychronous reset Asserting this signal returns the module to its default state so that it will begin the training sequence when rst is deasserted This port may be tied to logic 0 if not required Sr in Sychronous reset Asserting this signal returns the module to its default state so that it will begin the training sequence when sr is deasserted This port may be tied to logic 0 if not required 335 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram training v2 tstcomp tstdo tstdone tstok trained Notes out Training complete to memory port This signal should be connected directly to the tstcomp ports of one or more instances of ddrsdram port v2 and notifies those ports that training is complete and normal operation should begin out Do readback experiment This signal should be connected directly to the tstdo ports of one or more instances of ddrsdram port v2 and instructs those ports to perform a readback experiment as part of the training sequence in Done readbac
285. ed ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog zbt Synopsis Note this FPGA design has been effectively superseded by the Memory sample FPGA design VHDL since the latter is more general and supports a larger number of models and types of memory 192 ADM XRC SDK 4 9 3 User Guide Win32 ZBT The ZBT FPGA design demonstrates how to implement a host interface to the SSRAM in an FPGA design The design divides the 4MB FPGA space into a lower 2MB region for register and an upper 2MB window for accessing the SSRAM A page register is provided so that all of the SSRAM on a card is available to the host This example demonstrates the following A bursting local bus interface in the FPGA Interfacing of ZBT SSRAMs to the FPGA Bursting if supported need not be supported over the entire FPGA space In this design only the 2MB SSRAM window supports bursting Since the FPGA does not distinguish between a direct slave burst initiated by the host CPU and a burst initiated by a DMA engines in the local bus bridge the host can use programmed I O or DMA to transfer data Generation of deskewed copies of the local bus clock LCLK that are driven off chip to the SSRAMs using DLLs Virtex E EM or DC
286. ed to perform readback experiments in order to find a window where data can be reliably captured from the memory devices A number of sweeps are performed because as well as varying the phase the amount of coarse grained delay must also be varied in order to determine the delay between issuing a command to the memory devices and valid data being captured The training algorithm can be expressed in pseudocode as trained 0 tstcomp 0 best cedge invalid best window 0 best phase invalid for cedge in 0 to 7 loop window start invalid window stop invalid in window false 345 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram training v2 for phase in 180 to 180 do set phase of 1 0 to phase instruct memory ports to perform readback experiment via tstdo signal if tstdone and tstok indicate experiment was successful for all memory ports then if not in window then Start of window detected window start phase in window true end if else if in window then End of window detected window stop phase window length window stop window start if window length some minimum window and window length best window This is the new best window best window window length best cedge cedg best phase window stop window start 2 end if in window false end if end if end if if in window then wh re still r Ww Handle special cas inside wi
287. egion of the user buffer The following figures illustrate the relationship between the members of the ADMXRC BUFFERMAP structure in two possible cases e Here when ADMXRC MapbDirectMaster is called the MaxPages member of the ADMXRC BUFFERMAP structure passed is greater than or equal to the number of pages spanned by the application buffer 550 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC BUFFERMAP Physical memory PagesPci s 1 PageLength PagesPci 1 Application buffer n start Pagesopanned 4 PagesPci 2 BytesSpanned Init Offset 0 e when ADMXRC MapbDirectMaster is called the MaxPages of the ADMXRC BUFFERMAP structure passed is 2 less than the number of pages spanned by the application buffer 551 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC BUFFERMAP Physical memory Application buffer T PageL en ath PagesPci 1 E start Pagesopanned 2 BytesSpanned n Init Offset PagesPci 0 552 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC CARD INFO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC CARD INFO Declaration typedef struct ADMXRC CARD INFO ADMXRC DEVICE NUM unsigned long RAMBankFitted 4 ADMXRC FPGA TYPE FPGAType unsigned long PhysicalMemoryBase unsigned long MemoryBase unsigned long BoardRevision unsigned long LogicRevision
288. em a 1 0 E 55 port plast z e x async portg m mem adv 29 pre prpe mem_ce ae port_ptenm 0 tt ety pq E pow _ 0 svalid sready other ports mem ten to arbiter 2 instances sel bank 1h other ports mem cw mem a 31 2 122 ADM XRC SDK 4 9 3 User Guide Win32 Memory Detail of outbound datapath in the memory banks module As in the inbound datapath the one hot bank select vector sel bank 1h is used to ensure that at most one set of port p signals can be active at a given moment in turn ensuring that at most one async port instance can be active at any time When the local bus interface reads a memory bank the mem signals work as follows mem ce pulsed by the local bus interface for one clock cycle at the beginning of a burst when the local bus interface wants to access a memory bank whether for a read or for a write mem a qualified by mem ce and carries the starting address in terms of 32 bit words in memory that the local bus interface wishes to access mem cw qualified by mem ce and is deasserted by the local bus interface for a read access mem term pulsed by the local bus interface for one clock cycle to terminate the burst mem adv when asserted by the local bus interface indicates that the next 32 bit word of data should be presented on mem q This signal enters the port instance For the case of the ADM XRC 4FX por
289. em be 2 ili ILH D port pce 3 _ Xr rep final a mem ce NS yum E DR D 128 15 tem mem vw a 0 other ports Detail of inbound datapath in the memory banks module The currently selected bank is available as a one hot vector sel bank 1h This is used to ensure that at most one set of port p signals can be active at a given moment in turn ensuring that at most one async port instance can be active at any time The port p signals are generated in a fairly trivial manner from the mem signals which work as follows e mem ce pulsed by the local bus interface for one clock cycle at the beginning of a burst when the local bus interface wants to access a memory bank whether for a read or for a write 141 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 e mem a qualified by mem ce and carries the starting address in terms of 64 bit words in memory that the local bus interface wishes to access e mem cw qualified by mem ce and is asserted by the local bus interface for a write access e mem term pulsed by the local bus interface for one clock cycle to terminate the burst e mem wr when asserted by the local bus interface indicates that mem d and mem be carry 64 bit data and byte enables to be written to memory May be asserted for multiple consecutive clock cycles during a burst e mem d carries data from the local bus interface to be written to memory e mem be byte
290. ements and then chopped up at 8 element intervals Each 8 element segment becomes one element of the returned byte vector t 377 ADM XRC SDK 4 9 3 User Guide Win32 conv integer ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference conv integer Declaration Synopsis Description Declaration function conv integer constant bv in byte vector t return natural Synopsis Converts a byte vector t vector of bytes to an integer Description The bv parameter is converted to a natural treating the vector as an unsigned multibyte value where bv 0 is the least significant byte It is the caller s responsibility to ensure that the result does not overflow a natural value 378 ADM XRC SDK 4 9 3 User Guide Win32 conv integer signed ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference integer signed Declaration Synopsis Description Declaration function conv integer constant slv in std logic vector return integer Synopsis Converts a std logic vector to an integer Description The slv parameter is converted to an integer treating it as a two s complement signed value It is the caller s responsibility to ensure that the result does not overflow an integer 379 ADM XRC SDK 4 9 3 User Guide Win32 conv integer unsigned ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alp
291. emory port with 32 physical data bits rd is 32 operating at a clkO frequency of 133MHz can sustain approximately 1GB s ADM XRC SDK User Guide PLXSIM Package ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference Datatypes Constants Functions and procedures Components This section documents the VHDL implementation of the PLXSIM package This package consists datatypes constants functions procedures and components designed to speed up development of a VHDL testbench centered around the local bus interface of an FPGA design Datatypes Name byte enable t byte t byte vector t integer vector t locbus ddma in t locbus ddma out t locbus in t locbus out t Constants Name init locbus ddma out init locbus out Functions and procedures 17 Purpose A vector type used to pass the byte enables for a local bus transfer A type that can hold a single byte of data A vector type used to hold the data for a local bus transfer A vector type used to hold an array of integers A record type used to make a bundle of the demand mode DMA signals for a particular DMA channel that are input by a stimulus process A record type used to make a bundle of the demand mode DMA signals for a particular DMA channel that are driven by a stimulus process A record type used to make a bundle of the local bus signals that are input by a stimulus process A record type used to mak
292. enables to be assembled before it is actually committed to memory o For outbound data that is reads from the memory a multiplexor called port mux selects a 64 bit word from the logical memory data depending on the low couple of local bus address bits 5 To share the memory ports between the local bus interface and the user application by instantiating one arbitration module arbiter 2 per memory port The following figure illustrates the data flow within 4 banks xrc4fx vhd This is the ADM XRC 4FX specific version of the memory banks module local bus dock domain memory user dock domain arbiter 2g to from user app ddr2sdram portg control address data tag etc for bank 0 128 16 0 port i async port arb 0 rc mem d data byte enables and tag data byte pals mem be etc to memory enables etc to bank 0 64 128 128 8 16 16 port p signals 128 port s 0 signals data tad valid etc from bank 0 128 i arbiter 24 port mux to from mem q _ ddr2sdram ports 64 128 control address data tag etc for bank 3 128 i 16 ra3 as ort b 3 rc3 yo pora end tag data byte hele enables etc to bank 3 rd3 128 16 128 port s 3 signals data tag valid etc from bank 3 128 128 140 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 Data flow within the memory banks module
293. enever a write command is entered ce and w both asserted Physical bank select sideband signal 6 8 This input selects the number of physical banks chip selects in use for the DDR SDRAM devices 00 gt 1 physical bank 1 CS 01 gt 2 physical bank 2 CS 10 gt 4 physical bank 4 5 11 gt 8 physical bank 8 5 Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid is asserted by the memory port as a result of a read command gtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Certain types of memory port may unconditionally assert ready whereas other types of memory port may sometimes deassert ready depending on several factors For example a DDR SDRAM port is capable of buffering a certain number of commands internally but if its command buffer is filled while it executes a refresh cycle it will deassert ready Registered unregistered select sideband signal 6 8 This input selects whether the memory port expects registered DDR SDRAM memory or unregistered DDR SDRAM memory 0 gt unregistered 1 2 registered Row address width select sideband signal 6 8 This input selects the number of row address bits to use Along with the col input it specifies the row column geometry of the DDR SDRAM
294. entually grants access to the memory by asserting ready Once the client sees ready asserted it is permitted to issue commands to the memory port by asserting cei subject to the timing rules for readyi and cei as described in note 5 below HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif arbiter 4 vhd fpga vhdl common memif arbiter 2 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the logical address busses a a0 and a1 1 bias natural If unfair is true specifies which client 0 or 1 to favor otherwise 2 ignored d width natural Width in bits of the logical data busses d d0 d1 q q0 and q1 3 latency natural Specifies the number of consecutive clock cycles for which a 4 client is granted access to the memory port before access can be granted to a different client ready delay natural Specifies both the maximum number of clock cycles of delay 5 permitted between the deassertion of readyi and the deassertion of cei and the minimum number of clo
295. er in order to perform a write to the memory port on behalf of a client A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory ce out Memory port command entry The arbiter 3 module asserts this signal when it must access the memory port on behalf of a client When arbiter 3 asserts ce it also drives valid values on a and w Depending on whether or not w is asserted along with ce arbiter 3 also drives either tag or be and d with valid values 305 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 qtag ready tag valid 306 out out out Memory port write data The arbiter_3 module drives this signal with a valid set of byte enables when it asserts ce and w together in order to perform a write to the memory port on behalf of a client Memory port read data This signal carries the data read from the memory port as a result of arbiter 3 reading the memory port on behalf of a client It is qualified by the valid signal Memory port returned tag This signal carries the tag that accompanies data read from the memory port as a result of arbiter 3 reading the memory port on behalf of a client It is qualified by the valid signal Memory port ready When ready is asserted the memory port is ready to accept commands The arbiter 3 module uses this signal in generating the readyO ready1 and re
296. er is to begin transferring data This permits one DMA descriptor to map a large buffer DMA transfers can then be performed on subregions of the large buffer by specifying appropriate Offset and Length values The Length parameter specifies the number of bytes of data to transfer The Local parameter specifies the starting local bus address of the transfer The DMAModeWord parameter may specify that the local bus address is invariant for the duration of the DMA transfer see ADMXRC2 BuildDMAModeWord The Direction parameter specifies whether the transfer is from application buffer to FPGA or FPGA to application buffer and should be a value from the enumerated type ADMXRC2 DMADIR The Channel parameter is a zero based index that specifies which DMA channel should be used for the operation The number of DMA channels provided by a card is given by the NumDMAChan member of the ADMXRC2 CARD INFO structure Unless ADMXRC2 DMACHAN ANY is specified the maximum legal value of Channel is NumDMAChan 1 If ADMXRC2 DMACHAN ANY is specified for Channel the DMA transfer will be performed on the first available DMA channel However pending DMA transfers on a specific a DMA channel will always be given priority It is possible for a DMA transfer that specifies ADMXRC2 DMACHAN ANY to be delayed indefinitely if all DMA channels are kept busy by other threads The DMAModeWord parameter is a word that is programmed into the DMA hardware to specify the mode
297. er specifies the size in bytes of the application buffer to be mapped The Flags parameter must currently be O The DMADesc parameter must point to a variable of type ADMXRC2 DMADESC If ADMXRC2 SetupDMA succeeds this variable will contain a DMA descriptor on return 465 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SetupDMA The application buffer is locked down made non swappable so that the system cannot swap any page of physical memory spanned by the buffer out to disk Locking down a very large region of memory under low memory conditions should be avoided There are a limited number of DMA descriptors and each successful call to ADMXRC2 SetupDMA commits a descriptor until freed by a matching call to ADMXRC2 UnsetupDMA 466 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 StatusToString ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 StatusToString Prototype ADMXRC2 STATUS ADMXRC2 StatusToString ADMXRC STATUS Status char Buffer unsigned long Max Arguments Argument Type Purpose Status In Error code Buffer In Buffer to receive textual description Max In The size of Buffer in bytes Return value Value Meaning ADMXRC2 SUCCESS A description of the error was successfully returned ADMXRC2 NULL POINTER Buffer was NULL ADMXRC2 INVALID PARAMETER Status was not a valid error code Description This function returns in a textual description of an error in Buffer At mo
298. ereas for a multiplexed address data bus the data comes from the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes read from the local bus 385 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read const ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim read const Declaration Synopsis Description Declaration procedure plxsim read order i GUN natural multiburst in boolean address gt in std logic vector be in byte enable t data out byte vector t nxfered out natural signal bus in dun locbus in t signal bus out out locbus out t Synopsis Performs a basic local bus read transfer with constant local bus address Description This procedure uses the bus in and bus out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim read const FPGA design under tes t aut Stimulus rocess achbus in 1 Local bus LOCAL agent BUS ike J The order parameter specifies the width of the local data bus Valid values are e 2 for a 32 bit local data bus 386 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read const e for a 64 bit local data bus The multiburst parameter specifies the action taken if the target of the transfer terminates the burst before
299. es Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC P projnav rcp device ADM XRC II Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt 195 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ZBT64 sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL 2 20 2VP30 only ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog zbt 64 Synopsis Note this FPGA design has been effectively superseded by the Memory64 sample FPGA design VHDL since the latter is more general and supports a larger number of models and types of memory 196 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 The ZBT64 FPGA design demonstrates how to implement a 64 bit host interface to the SSRAM in an FPGA design The design divides the 4MB FPGA space into a lower 2MB region for register and an upper 2MB window for accessing the SSRAM A page register is provided so that all of the SSRAM on a card is avai
300. es write buffers and bridges so that the changes are visible to the CPU In practice this means observing the following rules e Call ADMXRC2 SyncDirectMaster specifying ADMXRC2 SYNC CPUTOFPGA for Mode after the CPU has set up an application buffer and before signalling the FPGA to operate on the buffer 468 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SyncDirectMaster e Call ADMXRC2 SyncDirectMaster specifying ADMXRC2 SYNC FPGATOCPU for Mode after the FPGA has operated on an application buffer and before the CPU examines the data in the buffer By the time ADMXRC2 SyncDirectMaster returns modifications made to an application buffer will be visible to the FPGA and vice versa The Offset and Length parameters identify a region within the application buffer which DmaDesc refers to This region should cover the parts of the user buffer which have been operated upon by the CPU or FPGA The Mode parameter should be one of members of the ADMXRC2 SYNCMODE enumerated type NOTE This function is not required by an application which uses only direct slave transfers programmed I O and DMA transfers via ADMXRC2 DoDMA and ADMXRC2_DoDMAImmediate 469 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_UnloadBitstream ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 UnloadBitstream Prototype ADMXRC2 STATUS ADMXRC2 UnloadBitstream ADMXRC2 IMAGE Image Arguments Argument Type Purpose Imag
301. es this signal in calls to the procedures provided by the PLXSIM package in order to perform demand mode DMA local bus transfers The arrangement is shown here in simplified form lacus dama out t jemand Idack D locbus ddma int DMA agent 0 Idreg Ix Stimulus process 0 Local bus FPGA design agent LOCAL BUS unit under test 0 The following procedures input a signal of type locbus in t 367 ADM XRC SDK 4 9 3 User Guide Win32 locbus ddma in t e plxsim read const demand e plxsim read demand e plxsim wait demand e plxsim write const demand e plxsim write demand Since it is an opaque datatype the members of locbus ddma in t should not be accessed as they are subject to change in future versions of the PLXSIM package 368 ADM XRC SDK 4 9 3 User Guide Win32 locbus ddma out t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus ddma out t Declaration Synopsis Description Declaration type locbus ddma out t is record end record Synopsis locbus ddma out t is an opaque record type used to bundle together the signals required for demand mode DMA local bus transfers Description The stimulus process uses the functions provided by the PLXSIM package to drive a signal of type locbus ddma out t This signal is then input by a locbus agent ddma component which is in turn connected to the demand mode DMA pins of the FPGA unit un
302. ess lengths of 17 18 19 and 20 bits are accomodated The page register augments the limited address space 2MB allotted to accessing the SSRAM The following figure illustrates this on an ADM XPL with a 1M x 64 ZBT SSRAM device fitted 0 200000 Ox1 C0000 No bank Augmented 04180000 quadword address Returns zeroes papiri 0x1 40000 P AGE 7 0 0x2 0x400000 0 100000 Local bus byte address SSR AM window 2MB LA 21 0 Ox0C 0000 0200000 0080000 Register region 2MB 0040000 Ox000000 0x000000 197 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 FPGA Space Usage The following registers exist in the 2MB register region Page register PAGE local bus address 0 0 Bits Mnemonic Type Function 7 0 PAGE R W Value that augments bits 20 3 of the local bus address when accessing the SSRAM 31 8 MBZ Mode register MODE local bus address 0x4 Bits Mnemonic Type Function 0 PIPELINED RAN Value that selects the mode in which to operate the ZBT SSRAM devices 0 gt flowthrough 1 gt pipelined 31 1 MBZ Size register SIZE local bus address 0x8 Bits Mnemonic Type Function 1 0 SIZE R W Value that specifies the number of address bits in a logical SSRAM bank 0 gt 17 128k words 1 gt 18 256k words 2 gt 19 512k words 3 gt 20 1M words 31 2 MBZ Information register INFO local bus address 0x10 Bits Mnemonic Type Function 23 0 BANKSIZE RO Returns size in words o
303. etely rebuilt in order to take effect 34 ADM XRC SDK 4 9 3 User Guide Win32 Configuring Borland command line tools ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Configuring the Borland command line tools This section assumes that that the ADM XRC SDK has been installed in the default location namely C NADMXRC SDK4 9 3 In order to build applications using the ADM XRC SDK the compiler must be able to locate the API header file and the linker must be able to locate the appropriate version of the API library The Borland C command line tools allow the library and include file search paths to be customized via the BCC32 CFG and ILINK32 CFG files which are usually located in the bim directory of the Borland C tools installation Add this line to BCC32 CFG I C NADMXRC SDK4 9 3Ninclude Add this line to ILINK32 CFG 1 ADMXRC_SDK4 9 3 lib Borland Important note there appears to be a bug in the Borland C command line tools manifested when specifying a quoted paths with spaces in configuration files such as BCC32 CFG In order for the tools to correctly pick up these paths there must be at least one space at the end of such lines in the configuration file To illustrate this let denote a space character A BCC32 CFG file including this workaround would look like IC borland bcec55 include I C somet path include ji10 35 ADM XRC SDK 4 9 3 User Guide Win32 I
304. eter specifies the byte enables to be used for the transfer They are active high and so a 1 in a particular element of be results in a 0 in the corresponding bit of LBE The length of be must be the same as the length of data The data parameter returns the data read from the local bus For a nonmultiplexed address data bus the data comes from the LD signal whereas for a multiplexed address data bus the data comes from the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes read from the local bus 387 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read const demand ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim read const demand Declaration Synopsis Description Declaration procedure plxsim read const demand order GU natural address std logic vector be c p byte enable t data out byte vector t nxfered sut natural signal bus in gt in locbus in t signal bus out out locbus out t signal dd in C Zn locbus ddma in t signal dd out out locbus ddma out t Synopsis Performs a demand mode DMA local bus read transfer with constant local bus address Description This procedure uses the bus in bus out dd in and dd out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim read const demand lachus
305. ether devices with 8 or 16 bit data or devices with 4 bit data are in use Generally applicable only to DIMM DDR SDRAM memory In this version of the memory port it must be zero ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 330 5 T 11 The delay from deassertion of reset to completion of training trained asserted may be as long as 350ms This is because a large post reset delay is used in order to ensure that the memory port properly initializes the DDR SDRAM devices that it is controlling after power on For simulation however the memory port uses a much smaller post reset delay with the result that the delay from deassertion of reset to completion of training is dominated by the time spent training This is in the order of 150 microseconds of simulation time at a clkO frequency of 133MHz Certain properties of a DDR SDRAM device such as number of row and column address bits might not be known at the time of building an FPGA design Therefore this memory port allows certain properties to be specified at runtime An application might interrogate some Vital Product Data in order to determine the proper values to drive on the row col bank and pbank signals Alternatively if the designer can guarantee that the properties of the DDR SDRAM devices are known when building the FPGA design these signals can be driven with constant values This has the advantage of lower slice utilization In any case for reli
306. ether with the local bus address from LA or LAD LBE permits addressing of individual bytes LBE is qualified by the following events e Assertion of LBTERM by the slave e Assertion of LREADY by the slave If the current transfer is 32 bits wide L64 does not exist on the bus or is deasserted then only LBE 3 0 carry data If the current transfer is 64 bits wide L64 exists on the bus ADM XRC SDK 4 9 3 User Guide Win32 Bussed signals 213 LBLAST LBTERM LCLK LD LREADY LRESET LWRITE master slave central resources master slave slave local bus bridge master and is asserted then LBE 7 0 carry data Local Burst Last LBLAST is asserted by the master to indicate that the current word is the final word of the burst When LREADY is asserted along with LBLAST the current burst ends LBLAST is valid for every cycle of a burst Local Burst Terminate LBTERM is asserted by the slave to terminate the current burst immediately The word of data on the LD or LAD bus is transferred and the current burst ends regardless of LREADY and LBLAST Local Bus Clock LCLK is the local bus clock All other local bus signals with the exception of LRESET are synchronous to LCLK The frequency of LCLK is normally under the control of an application running on the host Local Data LD is qualified by the following events e Assertion of LBTERM by the slave e Assertion
307. f ADMXRC DMACHAN ANY is specified for Channel the DMA transfer will be performed on the first available DMA channel However pending DMA transfers on a specific a DMA channel will always be given priority It is possible for a DMA transfer that specifies ADMXRC DMACHAN ANY to be delayed indefinitely if all DMA channels kept busy by other threads The DMAModeWord parameter is a word that is programmed into the DMA hardware to specify the mode of operation for the DMA channel specified by the Channel parameter The ADMXRC_BuildDMAModeWord function should be used to obtain a suitable value for this parameter The Flags parameter may be any combination of the following Flag Meaning ADMXRC DMAFLAG DONOTQUEUE If the DMA operation cannot be started immediately the error ADMXRC DEVICE BUSY is returned rather than queuing the DMA operation The Timeout parameter must currently be NULL as timeouts on DMA operations are not yet supported The Event parameter should be a pointer to a Win32 event handle See multithreading issues for further information 516 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC_DoDMAImmediate ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC_DoDMAImmediate Prototype ADMXRC_STATUS ADMXRC_DoDMAImmediate ADMXRC_HANDLE Card void Buffer unsigned long Length DWORD Local DWORD Direction DWORD Channel DWORD ode DWORD Flags DWORD Timeout PH
308. f each logical SSRAM bank 31 24 NUMBANK RO Number of logical SSRAM banks in the design Status register STATUS local bus address 0x14 Bits Mnemonic Type Function 0 LCLK LOCKED RO Returns 1 if the local bus clock LCLK DCM DLL is currently locked RAMCLK LOCKED RO If nis the number of SSRAM clock signals in the design this register returns 1 in a particular bit if the DCM DLL for that clock signal is currently locked Bit 1 corresponds to SSRAM clock 0 31 n 1 RAX Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file 198 ADM XRC SDK 4 9 3 User Guide Win32 ZBT64 ADM XPL Zbt64 xpl v2p scr zbt64 xpl v2p prj zbt64 xpl ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XPL projnav xpl lt device gt 199 ADM XRC SDK 4 9 3 User Guide Win32 Running the Xilinx tools ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Running the Xilinx ISE tools When building an FPGA bitstream that targets an ADM XRC series card certain options must be passed to the Xilinx tools The following table describes the options that should be used with the ISE 10 1i SP3 toolset Tool Command line option Project Navigator option When to apply MAP prb This option is available v
309. f the burst Each bit of LDACK corresponds to a DMA channel in the PCl to local bus bridge At most one DMA channel may be performing a burst on the local bus at any time hence at most one bit of LDACK may be asserted at any time DMA request Any bit or all bits of LDREQ may be asserted by the FPGA to request a Demand mode DMA burst Each bit of LDREQ corresponds to a DMA channel in the PCI to local bus bridge Provided that the host has started via the driver a demand mode DMA operation on a particular channel asserting LDREQ for that DMA channel will eventually result in the DMA engine in the PCI to local bus bridge performing a burst with LDACK for that channel asserted While a demand mode DMA burst is in progress ie a bit of LDACKx is asserted the burst can be terminated by deasserting the corresponding bit of LDREQ This is known as pausing the demand mode and will cause the PCI to local bus bridge to assert LBLAST as soon as possible When a demand mode DMA burst has completed and either e the PCI to local bus bridge has transferred all data in its FIFO or e the demand mode DMA was paused ADM XRC SDK 4 9 3 User Guide Win32 Sideband signals 217 LEOT FPGA then the PCI to local bus bridge will not initiate another burst on the local bus for that DMA channel until the corresponding bit of LDREQX is reasserted End of transfer This signal may be asserted during a burst
310. fer typically moves onto some other task or goes to sleep When the PCI device interrupts the CPU the CPU may need to make its data caches coherent with memory again This step is not required on all platforms particularly those that automatically maintain cache coherency during DMA transfers On platforms that use bounce buffers the system may need to copy data out of bounce buffers into the user space buffer if the direction of the DMA transfer was PCI to memory The system now unlocks the pages of the user space buffer so that its pages become swappable again In operating systems which do not use virtual memory this step is a no op Cache coherent DMA can be implemented by having the chipset invalidate the cache lines involved in a DMA transfer as it actually happens via signals that are brought out on the CPU Note that steps 1 and 7 are not performed by the Alpha Data ADM XRC driver when the ADMXRC2 DoDMA API function is used This is because applications typically call ADMXRC2 SetupDMA during initialization which effectively performs step 1 Similarly applications typically call ADMXRC2 UnsetupDMA as they wind down which effectively performs step 7 If you know you will reuse a buffer for several DMA transfers use of ADMXRC2 DoDMA can remove the nondeterminism and latency associated with steps 1 and 7 Even with these potential overheads DMA transfers are still a far better choice than Direct Slave transfers for bu
311. file I O to be performed this is a deterministic method of configuring the FPGA This routine does not allow the FPGA to be partially configured on each call all of the data necessary to configure the FPGA must be supplied in a single call Warning Ensure that Buffer contains valid configuration data for the target FPGA as data transferred this way to the FPGA s SelectMap port cannot be validated by the API The card to be configured is specified by the Card parameter The Buffer parameter should point to a buffer containing the configuration data for the FPGA The data must be supplied in a form directly writable to the FPGA s SelectMap port and care should be taken to ensure that the bit ordering of the data is correct The functions ADMXRC LoadFpgaFile ADMXRC FindlmageOffset and ADMXRC ReverseBytes can be used to obtain SelectMap data in the correct form The Length parameter specifies the number of bytes of configuration data to be written to the FPGA s SelectMap port 509 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ConfigureFromBufferDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC ConfigureFromBufferDMA Prototype ADMXRC STATUS ADMXRC ConfigureFromBufferDMA ADMXRC HANDLE Card void Buffer DWORD Length DWORD DmaChan PHANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure Buffer In FPGA configuration data Length In Length of FPGA config
312. following source files relative to root of SDK installation totom User application a a width 1 0 tag tag_wrdth 1 0 be d width 8 1 Of d d wet 1 0 ra ra width 1 0 burst len rc rc width 1 0 dll atf rafed width 1 0 clkc clkc1an cedge 2 n tatcomp tado width 1 0 wrath 1 0 valid ready tatdone tatok v2 fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif cmd fifo vhd fpga vhdl common memif ddr2sram v2 ddr2sram port v2 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead 338 ta fram memory devi cels ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 Parameters Name a width d width pinout ra width rc width rd width tag width Notes 339 Type Function Note natural Width in bits of the port logical address a 4 natural Width in bits of the port data in and out d and q 3 respectively ddr2sram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants natural Width in bits of the memory device address bus ra 1
313. ga vhdl common memif ddrsdram ddrsdram port vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the port logical address a 4 auto train boolean If true the memory port automatically trains itself after reset is deasserted If false the memory port does not train itself This parameter has a default value of true and in normal usage an application should rely on the default value and not map it to any particular value d width natural Width in bits of the port data in and out d and q 3 respectively pinout ddrsdram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants ra width natural Width in bits of the memory device address bus ra 1 rc width natural Width in bits of the memory device control bus rc 2 rd width natural Width in bits of the memory device data bus rd 3 tag width natural Width in bits of the tag in and out tag and qtag respectively timing ddrsdram timing t This value specifies the timing of the memory port For convenience an application may map it to one of the predefined constants Notes 1 The memory device address bus ra is composed of two fields in this memory port with the widths of each field specif
314. ge supports such a configuration e The signal corresponding to LAD 63 32 in the testbench if the wide generic is true and the multiplexed generic is true The signal corresponding to LBEZ 3 0 in the testbench e Anything typically a vector of constant zeroes if the wide generic is false The port will be ignored e The signal corresponding to LBEZ 7 4 in the testbench if the wide generic is true The signal corresponding to LWRITE in the testbench The signal corresponding to LBLAST in the testbench The signal corresponding to LREADY in the testbench The signal corresponding to LBTERM in the testbench ADM XRC SDK 4 9 3 User Guide Win32 locbus agent ddma ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus agent ddma Declaration Synopsis Description Declaration component locbus agent ddma generic tco_p2p in time 5 ns port ldreq 1 std logic ldack out std logic dd in out locbus ddma in t dd out in locbus ddma out t end component Synopsis Non synthesizable testbench component that connects a stimulus process to a set of demand mode DMA pins on the FPGA unit under test to from stimulus ek process lochus agent Description This demand mode DMA agent component can be instantiated in a testbench to provide demand mode DMA stimulus to the FPGA One instance of locbus ddma agent
315. gn does not have a local bus interface thus there are no registers defined in the FPGA space 150 ADM XRC SDK 4 9 3 User Guide Win32 RearlO Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC P with reario xrcp v scr reario xrcp v prj reario xrcp ucf Virtex ADM XRC P with reario xrcp ve scr reario xrcp ve prj reario xrcp ucf Virtex E ADM XRC II reario xrc2 v2 scr reario xrc2 v2 prj reario xrc2 ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC I Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt 151 ADM XRC SDK 4 9 3 User Guide Win32 Simple ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Simple sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the AD
316. gnals in the design this register returns 1 in a particular bit if the DCM DLL for that clock signal is currently locked Bit 1 corresponds to SSRAM clock 0 31 1 RAX Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with Zbt xrc v scr Zbt xrc v prj zbt xrc v ucf Virtex ADM XRC with zbt xrc ve scr Zbt xrc ve prj zbt xrc ve ucf Virtex E EM ADM XRC P with zbt xrcp v scr zbt xrcp v prj zbt xrcp v ucf Virtex ADM XRC P with zbt xrcp ve scr zbt xrcp ve prj zbt xrcp ve ucf Virtex E EM ADM XRC II Lite zbt xrc2l v2 scr zbt xrc2l v2 prj zbt xrc2l ucf ADM XRC II Zbt xrc2 v2 scr Zbt xrc2 v2 prj zbt xrc2 ucf ADM XPL zbt xpl v2p scr Zbt xpl v2p prj zbt xpl ucf ADM XRC 4LX zbt xrc4lx v4lx scr Zbt xrcAlx v4lx prj zbt xrc4lx ucf ADM XRC 4SX zbt xrc4sx v4sx scr zbt xrc4sx v4sx prj zbt xrc4sx uct Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav xrc lt device gt ADM XRC P projnav xrcp lt device gt ADM XRC I Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt ADM XRC 4LX projnav xrc4 x lt device gt ADM XRC 4SX projnav xrc4sx lt device gt Modelsim scripts 162 ADM XRC SDK 4 9 3 User Guide Win32 ZBT Example Modelsim comp
317. gt 4 physical banks 0x3 gt 8 physical banks 31 10 MBZ USER registers USERO USER63 local bus address 0x100 0x1FF There are a total of 64 USER registers occupying local bus addresses 0x100 to 0x1FF inclusive The interpretation of the USER registers depends upon the logic within the user_app module and the description below applies only to the unmodified user_app module that ships with this SDK USERO USER15 The first 16 user registers specify the starting addresses counting in logical data words where the chip driven memory test should begin testing each memory bank Bits Mnemonic Type Function 31 0 OFFSET RAN Specifies the starting address at which to begin testing a particular memory bank USER16 USER31 The next 16 user registers specify the number of logical data words that the chip driven memory test should test in each bank Bits Mnemonic Type Function 31 0 LENGTH R W Specifies the number of logical data words to test in a particular memory bank minus 1 For example to test 1 megaword write the value OxFFFFF USER48 The USER48 register indicates on which phase the memory test failed for banks 0 to Bits Mnemonic Type Function 7 0 EPHASEO RO If ERROR O is 1 indicates on which phase the memory test for bank O failed 15 8 EPHASE1 RO If ERROR 1 is 1 indicates on which phase the memory test for bank 1 failed 23 16 EPHASE2 RO If ERROR 2 is 1 indicates on which phase the memory test for bank
318. guration should be at least 25 When a width is larger than actually required the top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory devices are in use The signals of this interface to and from the user application are as follows Signal 326 Type Function Note ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 a bank be ce in in cedge training in signal clkO clk90 clk180 clk270 327 in in Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as a linear array of words of width d_width this address is a logical address rather than anything resembling what one might see on the ra bus Bank address width select sideband signal 6 8 This input selects number of internal bank address bits for the DDR SDRAM devices in use 00 gt no internal bank address bits 01 2 1 internal bank address bits 10 gt 2 internal bank address bits 11 gt 3 internal bank address bits Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory Command entry
319. h 8 1 Of d d width 1 0 other inputs gid width 1 0 wrath 1 0 valid ready other outputs port The parameters of this interface are as follows Name Type ra_width natural 281 Function Width in bits of the memory device address bus ra tatom memory devices Refer to the documentation for a specific type of memory port for the details of the the relationship between ra_width and a_width ADM XRC SDK 4 9 3 User Guide Win32 Memory interface package VHDL rc width natural rd width natural a width natural d width natural tag width natural Width in bits of the memory device control bus rc Refer to the documentation for a specific type of memory port for details of how to specify a legal value for width Width in bits of the memory device data bus rd Refer to the documentation for a specific type of memory port for the details of the the relationship between rd width and d width Width in bits of the port logical address a Refer to the documentation for a specific type of memory port for the details of the the relationship between ra width and a width Width in bits of the port data in and out d and q respectively Also determines the width of the byte enables be Refer to the documentation for a specific type of memory port for the details of the the relationship between rd width and d width Width in bits of the tag in and out
320. h 8 1 0 d1 d width 1 0 qi d width 1 0 width 1 0 valid1 ready req2 ce2 a2 a width 1 0 307 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 cez a2 a width 1 0 v2 tad2 tag width 1 0 to from client 2 be2 d width 8 1 0 d2 d width 1 0 qa d width 1 0 qtag2 tag width 1 0 a3 a width 1 0 8 tag3 tag width 1 0 to from client 3 be3 d width 8 1 0 d3 d width 1 0 q3 d width 1 0 ctad3 tag width 1 0 valid ready3 arbiter_4 The arbiter 4 module requires a client to assert its request signal req when the client wishes to access the memory port In response the arbiter 4 eventually grants access to the memory port by asserting ready Once the client sees ready asserted it is permitted to issue commands to the memory port by asserting cei subject to the timing rules for readyi and cei as described in note 5 below HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif_pkg vhd fpga vhdl common memif memif_int_pkg vhd fpga vhdl common memif memif_def_synth vhd OR fpga vhdl common memif memif_def_sim vhd fpga vhdl common memif arbiter_4 vhd If synthesizing the file fpga vhdl common memif memif_def_synth vhd must be included If simulating the file fpg
321. ha Data PLXSIM VHDL reference conv integer unsigned Declaration Synopsis Description Declaration function conv integer unsigned constant slv in std logic vector return natural Synopsis Converts a std logic vector to an natural Description The slv parameter is converted to a natural treating it as a unsigned value It is the caller s responsibility to ensure that the result does not overflow a natural 380 ADM XRC SDK 4 9 3 User Guide Win32 conv std logic vector ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference conv std logic vector Declaration Synopsis Description Declaration function conv std logic vector constant bv in byte vector t return std logic vector Synopsis Converts a byte vector t vector of bytes to a std logic vector Description The bv parameter whose length is n is converted to a std logic vector with a range n 8 1 downto 0 where each 8 element slice of the result is obtained from the corresponding element of bv The slice 7 downto 0 of the result is obtained from bv 0 381 ADM XRC SDK 4 9 3 User Guide Win32 conv string ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference conv string Declaration Synopsis Description Declaration function cons return s function cons return s function cons return s function cons return s Synopsis
322. harge and ACT row activation or REF refresh commands t rfc natural Number of clkO cycles for completion of a REF refresh operation t act natural Minimum number of cIkO cycles between ACT row activate and a read or write command t wtr natural Minimum number of clkO cycles between a write and a read command t natural Minimum number of cIkO cycles between a read and a write command t rtp natural Minimum number of cIkO cycles between a read and PRE precharge command t wtp natural Minimum number of clkO cycles between a write and a PRE precharge command t ras natural Minimum number of cIkO cycles between ACT row activate and PRE precharge command All values in the above table are numbers of clkO cycles Thus 286 assuming same row assuming same row ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram timing t e For parameters that are specified as delays in nanoseconds on a DDR II SDRAM datasheet the values should be computed by dividing the datasheet parameters by the clkO period e g 7 5 ns and rounding up to the nearest integer An example of such a parameter is t rp e For parameters that are specified in numbers of DDR II memory clock cycles the datasheet values should simply be divided by 2 and rounded up An example of such a parameter is t dllr 287 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram pinout t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr
323. hase the memory test for bank 10 failed 31 24 EPHASE11 RO If ERROR 11 is 1 indicates on which phase the memory test for bank 11 failed USER51 The USERBO register indicates on which phase the memory test failed for banks 12 to 15 Bits Mnemonic Type Function 7 0 EPHASE12 RO If ERROR 12 is 1 indicates on which phase the memory test for bank 12 failed 15 8 EPHASE13 RO If ERROR 13 is 1 indicates on which phase the memory test for bank 13 failed 23 16 EPHASE14 RO If ERROR 14 is 1 indicates on which phase the memory test for bank 14 failed 31 24 EPHASE15 RO If ERROR 11 is 1 indicates on which phase the memory test for bank 15 failed USER63 The USER68 register is used to initiate the chip driven memory test as well as check the status of the memory test When one of the low 16 bits is written with 1 it initiates the memory test for the corresponding memory bank using the parameters in the USERO USER31 registers To initiate the memory test on several banks simultaneously write a number of 1s to USER63 15 0 at the same time Bits Mnemonic Type Function 137 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 15 0 DONE R R W When read returns 1 for a particular bit if the memory GO W test for the corresponding bank is not running Banks that are nonexistent or unused always return 1 When written with 1 initiates the memory test for the corresponding memory bank For example writing OxB would initiate the memory
324. hase the memory test for bank 13 failed 23 16 EPHASE14 RO If ERROR 14 is 1 indicates on which phase the memory test for bank 14 failed 31 24 EPHASE15 RO If ERROR 11 is 1 indicates on which phase the memory test for bank 15 failed USER63 The USER6S register is used to initiate the chip driven memory test as well as check the status of the memory test When one of the low 16 bits is written with 1 it initiates the memory test for the corresponding memory bank using the parameters in the USERO USER31 registers To initiate the memory test on several banks simultaneously write a number of 1s to USER63 15 0 at the same time Bits Mnemonic Type Function 15 0 DONE R RAN When read returns 1 for a particular bit if the memory GO W test for the corresponding bank is not running Banks that are nonexistent or unused always return 1 When written with 1 initiates the memory test for the corresponding memory bank For example writing would initiate the memory test for banks 0 1 and 3 only Writing a 1 to a bit that corresponds to a nonexistent or unused bank has no effect 31 16 ERROR RO Returns a 1 for a particular bit if one or more errors occurred during the memory test for the corresponding memory bank Valid only when the corresponding bit of the DONE field is 1 For each bit of ERROR indicates that failure the corresponding EPHASE field may be inspected in order to discover the phase of the memory test in which the f
325. he PLXSIM package 375 ADM XRC SDK 4 9 3 User Guide Win32 init locbus out ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference init locbus out Declaration Synopsis Description Declaration constant init locbus out locbus out t Synopsis init locbus out t is a constant that can be used to initialize a value of type locbus out t to its initial inactive state Description This constant may assigned to a value of type init locbus out t in order to set it to an initial inactive state This initialization is required somewhere in the testbench in order to prevent undefined values being driven onto the local bus Typically init locbus out t is applied at the declaration of a signal for example Signal bus out locbus out t init locbus out Since locbus out t is an opaque datatype the members of init locbus out t should not be accessed as they are subject to change in future versions of the PLXSIM package 376 ADM XRC SDK 4 9 3 User Guide Win32 byte vector ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference conv byte vector Declaration Synopsis Description Declaration function conv byte vector constant slv in std logic vector return byte vector t Synopsis Converts a std logic vector to a byte vector t vector of bytes Description The slv parameter is left padded to a multiple of 8 el
326. he assertion of Iready l on the next clock cycle Once Iready o lis asserted by PLXDSSM it cannot be asserted until the current Direct Slave transfer ends Thus ready can be pulsed or held asserted If a Direct Slave transfer is in progress and stop is asserted before ready is asserted PLXDSSM will remember that stop has been asserted even if stop is deasserted before ready is subsequently asserted Once ready is asserted PLXDSSM will assert both Iready o 1 and Ibterm o lon the next cycle stop can be pulsed or held asserted cycle If a Direct Slave transfer is in progress and stop is asserted coincident with or after ready PLXDSSM will assert Ibterm o on the next It follows from these rules that when using PLXDSSM LREADY cannot be asserted and then deasserted in the middle of a transfer the proper way to make the local bus master wait is to terminate the burst rather than attempt to hold it off by deasserting LREADY In some applications this has the advantage of giving other local bus masters a chance to utilise the bus instead of wasting cycles increasing bus efficiency In very simple applications ready and stop may simply be tied high so that the application never permits bursting on the local bus and all local bus transfers last for exactly 3 clock cycles PLXDSSM state diagram The implementation of the PLXDSSM module is a hybrid Mealy Moore state machine 260 ADM XRC SDK 4 9 3 User Guide Win32 PL
327. he corresponding byte will not be written to memory 303 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 ce0 2 do di d2 q0 q2 qtagO qtag1 qtag2 readyO ready1 ready2 req1 req2 tag0 tag1 tag2 validO valid1 valid2 wO w1 w2 in out out out out Notes 304 Client command entry A client asserts this signal to enter a new read or write command into the memory port When asserted ai and wi must be valid When asserted along with wi tagi must also be valid A client must observe the rules for assertion of cei with respect to readyi as illustrated by note 5 above Other than that there are no restrictions on how few or how many clock cycles cei can remain asserted It can be pulsed for single clk cycles or asserted for many clk cycles readyi permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but the performance of certain types of memory for example DDR SDRAM benefits from locality of access Client data to memory A client must place valid data on d whenever a write command is entered cei and wi both asserted Client data from memory When validi is asserted is asserted by the memory port as a result of a read command qi reflects the data read from memory Client tag out When validiis asserted by the memory port as a result of a read command qtag reflects th
328. he ddrsdram training v2 component Overview HDL source code Parameters Signals Performance Overview The ddrsdram training v2 component is part of the memif package and implements the training algorithm for one or more instances of the ddrsdram port v2 component torom infrastructure trained totom or more memory ports ddrsdram_training_v2 This module works by sweeping the phase of a capture clock clkc0 which clocks data from the memory devices into the FPGA s IOBs from 180 degrees to 180 degrees During the sweep the associated memory ports that are being trained are instructed to perform readback experiments in order to find a window where data can be reliably captured from the memory devices A number of sweeps are performed because as well as varying the phase the amount of coarse grained delay must also be varied in order to determine the delay between issuing a command to the memory devices and valid data being captured The training algorithm can be expressed in pseudocode as trained 0 tstcomp 0 best_cedge invalid best_window 0 best_phase invalid for cedge in 0 to 7 loop window_start invalid window_stop invalid in_window false 333 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram training v2 for phase in 180 to 180 do set phase of 1 0 to phase instruct memory ports to perform readback experiment via tstdo signal if tstdone and
329. he rc bus Width ofthis field is rd width 8 porraca cr c WF K WE Present if pinout has cistrue Present if pinout has_oy istrue 350 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v4 The order of the fields within rc is always the same but some models may lack certain fields 3 The rd width parameter is the number of physical DQ wires making up the data bus of the DDR II SSRAM bank This memory port transfers four words of data on the DQ wires for each command entered via the ce signal Accordingly the d width parameter which is the width of d and q is typically specified by the user application as being four times rd width However other values can be passed for d width o lf d width gt 4 rd width then the memory port simply truncates d internally so that its width is 4 rd width Data read from the memory devices is zero extended so that its width is d width before being returned on q o d width 4 rd width is the optimal usage case o If d width lt 4 rd width then the memory port zero extends d internally so that its width is 4 rd width 4 Thea width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a DDR II SSRAM bank Hence the required value of a width depends on what memory devices are actually in use As an example consider a DDR II SSRAM device with 21 add
330. he transfer which will be incremented during the transfer It need not be aligned to the word size of the local data bus The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address The be parameter specifies the byte enables to be used for the transfer They are active high and so a 1 in a particular element of be results in a 0 in the corresponding bit of LBE The length of be must be the same as the length of data The data parameter returns the data read from the local bus For a nonmultiplexed address data bus the data comes from the LD signal whereas for a multiplexed address data bus the data comes from the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes read from the local bus 391 ADM XRC SDK 4 9 3 User Guide Win32 plxsim request bus ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsi
331. hen written with 1 this field is cleared to 0 Reserved Each bit of this field represents a DCM DLL or PLL A 1 indicates that lock has been achieved Depending on the model in use not all 8 bits may be used For the precise meaning of the bits in this field refer to the table below describing differences between models for this design Sticky loss of lock training flags Each bit of this field returns 1 if the corresponding DCM DLL or PLL lost lock Note that unused bits of this field because there is no corresponding DCM DLL or PLL will always return 1 Reserved Status register MLOCK field STATUS local bus address 0x10 This table describes the STATUS MLOCK field for each supported model ADM XRC 4FX and ADPE XRC 4FX Bits Mnemonic Type 8 MEMCLK RO 9 IDELAY RO 15 10 RO MBZ Function When 1 indicates that the DCM that generates the clock for the memory clock domain is locked When 1 indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock Reserved ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 and ADM XRC 5T2 ADV Bits Mnemonic Type 133 Function ADM XRC SDK 4 9 3 User Guide Win32 Memory64 8 MEMCLK RO When 1 indicates that the PLL that generates the clocks for the memory clock domain is locked 9 IDELAY RO When 1 indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock 15 10 RO MBZ Reserved Memory status register MEMSTAT local bus ad
332. his register makes the corresponding interrupt source active The TEST register can be used to test the interrupt handler on the host By writing a 1 to a particular bit position the corresponding interrupt source is set active Count register COUNT local bus address Ox10 Bits Mnemonic Type Function 31 0 NCYCLE RAN This register counts local bus clock LCLK cycles when ISTAT 0 is 1 When ISTAT O0 is 0 it may be written in order to initialize its value The COUNT register can be used to measure interrupt response time It can be initialized to zero when ISTAT 0 is 0 and increments when ISTAT 0 is 1 Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with itest xrc v scr itest xrc v prj itest xrc ucf Virtex ADM XRC with itest xrc ve scr itest xrc ve prj itest xrc ucf Virtex E ADM XRC P with Virtex ADM XRC P with Virtex E ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II itest xrcp v scr itest xrcp ve scr itest xrc2l v2 scr itest xrc2 v2 scr itest xpl v2p scr itest xp v2p scr itest wrc2 v2 scr itest drc2 v2 scr Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model 181 itest xrcp v prj itest xrcp ve prj itest xrc2l v2 prj itest xrc2 v2 prj itest xpl v2p prj itest xp v2p prj itest
333. ia the Use this to achieve best IOB setup properties for the Map process time and clock to output times by allowing MAP to pack eligible flip Pack I O Registers Latches into flops into IOBs In rare cases IOBs For Inputs and Outputs where this is not desirable this behaviour can be overriden by attributes embedded in a design or by IOB FALSE constraints in a UCF file Virtex E EM This option is available via the This option causes MAP to k 6 properties for the Map process generate functions of the maximum number of variables when Virtex Il Il Pro Virtex E EM possible Although it increases the k 8 Map To Input Functions 6 runtime of MAP it generally improves quality of results Virtex 4 Virtex Il Il Pro k8 Map To Input Functions 8 Note that this option is disabled in versions of the Xilinx ISE tools Virtex 5 Virtex 4 later than 10 11 and thus Alpha do not use Map To Input Functions 8 Data no longer recommends applying it for Virtex 5 devices MAP timing This option is available via the This option causes MAP to use properties for the Map process timing constraints from the UCF file or those embedded in a design Perform Timing Driven Packing when mapping a design It and Placement True increases the runtime of MAP but generally improves quality of results significantly Note that this option does not apply to the Virtex E EM architecture ol high This option is avai
334. ication 520 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC GetCardInfo ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC GetCardlnfo Prototype ADMXRC STATUS ADMXRC GetCardInfo ADMXRC HANDLE Card ADMXRC CARD INFO Info Arguments Argument Type Purpose Card In Handle of card about which to return information Info Out Structure to be filled in with information about card Return value Value Meaning ADMXRC SUCCESS The information was obtained successfully ADMXRC INVALID HANDLE Card is not a valid handle to a card Description The ADMXRC GetCardlnfo function returns information about a card The Info parameter must point the ADMXRC CARD INFO stucture which is to receive the information 521 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC GetClockType ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC GetClockType Prototype ADMXRC STATUS ADMXRC GetClockType ADMXRC HANDLE Card ADMXRC CLOCK TYPE ClockType Arguments Argument Type Purpose Card In The handle of the card whose reference clock type is required ClockType Out Variable to receive the reference clock type Return value Value Meaning ADMXRC SUCCESS The reference clock type was returned successfully ADMXRC INVALID HANDLE Card was not a valid card handle Description This function returns the type of reference clock oscillator fitted to the card An application does
335. ied by the num addr bits and num bank bits of the pinout parameter Therefore ra width is the sum of these two values The following figure illustrates this for the case where num addr bits 13 and num bank bits 2 Bank address Rowe calumn address BA pins A pins a oh vO 2 7 615 54 3 2 t 0 1 4 0 Note that ra width and pinout are properties of the printed circuit board indicating how many wires are physically present On the other hand the DDR SDRAM devices actually fitted to the printed circuit board may have less pins connected The purpose of the row col bank and pbank signals is to specify at runtime the properties of the DDR SDRAM devices actually in use 2 The memory device control bus rc is composed of various fields in this memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates an example that puts rc width at 17 10 ADM XRC SDK User Guide Common Memory Ports Signals Widths are Widths are pinost ck width rd erth 3 Oo 161514151211 6 6 4 3 2 7 0 PET ere DW width pinaut cke width width 1 CASH width 1 RASH width 1 CSE width pinout oum_phys_bank The order of the fields within rc is always the same only the field widths may differ from one model to another The rd width parameter is the number of physical DQ wires mak
336. ign For example there is an an ADM XRC 4FX specific wrapper module in the source file xrc4fx memory64 xrc4fx vhd that instantiates the one and only instance of the memory main module and takes care of some details specific to the ADM XRC 4FX such as inputting global clocks Explanation of memory banks module As mentioned above the memory main module encloses one instance of the memory banks module The memory banks module is entirely model specific and comes in several versions one per model Its job is fourfold 1 To present a uniform interface in the local bus clock domain to the memory main module no matter what type of memory devices are present for a given model 2 To decouple the local bus clock domain from the memory clock domain as the two clock domains are generally independent in phase and frequency 3 To instantiate memory ports that are appropriate to the model For example the ADM XRC 4FX version of the memory banks module instantiates four DDR II SDRAM ports 4 To handle any difference in the width of the local bus data 64 bits and the width of the logical data written to and read from the memory ports o Forinbound data that is writes to the memory the port repl module is instantiated for some models 139 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 since a logical memory data word may be wider than a 64 bit local bus data word This is effectively a latch that enables a complete memory word plus byte
337. igned a buffer in user space b linked list DMA c data written to FIFO on local bus blocks in host memory In this case the data will be transferred correctly The 7 DWORDS in the user space buffer resulted in 7 DWORDs written into the FIFO Now consider the following unaligned DMA transfer again assuming that the local bus has 32 bit wide data e here is a 32 bit wide FIFO mapped to local bus address 0x100 e he application performs a DMA write into this FIFO from a 28 byte long buffer in host memory whose address is not DWORD 4 byte aligned and just happens to cross a physical page boundary Word LD 31 0 LAD 31 0 LBE2 3 0 8 0000 7 0000 B 0000 5 0011 page boundary 4 1100 3 0000 2 0000 user space address LED 1 0000 not DWORD aligned a buffer in user space b linked list DMA c data written to FIFO on local bus blocks in host memory The required 28 bytes are written into the FIFO but 8 rather than 7 DWORDs in total are written into the FIFO Two of those DWORDS have partial byte enables and this may represent a problem There are a couple of ways in which to address this issue 1 Ensure that DMA transfers are performed using buffers that are aligned to a DWORD 4 byte boundary This may not be possible for instrance if the application does not control how memory is allocated 2 A better solution assuming that the length of block of data in a DMA transfer
338. ile 543 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC UnregisterInterruptEvent ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC UnregisterlnterruptEvent Prototype ADMXRC STATUS ADMXRC UnregisterInterruptEvent ADMXRC HANDLE Card HANDLE Event Arguments Argument Type Purpose Card In Handle of card to which Event is registered Event In Specifies the event to unregister Return value Value Meaning ADMXRC SUCCESS The event was successfully unregistered ADMXRC INVALID HANDLE Card is not a valid handle to a card or Event is not a valid Win32 event handle Description This function unregisters a Win32 event previously registered with ADMXRC_RegisterlnterruptEvent so that the event will no longer be signaled when an FPGA interrupt occurs The Event parameter should be the handle of the Win32 event to unregister 544 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC UnsetupDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC UnsetupDMA Prototype ADMXRC STATUS ADMXRC UnsetupDMA ADMXRC HANDLE Card ADMXRC DMADESC DMADesc Arguments Argument Type Purpose Card In Handle of card DMADesc In The DMA descriptor to free Return value Value Meaning ADMXRC SUCCESS The DMA descriptor was successfully freed ADMXRC INVALID HANDLE Card was not a valid handle to card ADMXRC INVALID DMADESC DMADesc was not a valid DMA descriptor
339. imulus process lochus_in_t Local bus LOCAL Lr agent BUS ihe n The following procedures input a signal of type locbus in t e plxsim read e plxsim read const e plxsim read const demand ADM XRC SDK 4 9 3 User Guide Win32 locbus in t e plxsim read demand e plxsim wait demand e plxsim write e plxsim write const e plxsim write const demand e plxsim write demand Since it is an opaque datatype the members of locbus in t should not be accessed as they are subject to change in future versions of the PLXSIM package 372 ADM XRC SDK 4 9 3 User Guide Win32 locbus out t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus out t Declaration Synopsis Description Declaration type locbus out t is record end concede Synopsis locbus out t is an opaque record type used to bundle together the signals required for local bus transfers Description The stimulus process uses the functions provided by the PLXSIM package to drive a signal of type locbus out t This signal is then input by a locbus agent nonmux locbus agent mux32 or locbus agent mux64 component which is in turn connected to the local bus itself The arrangement is shown here in simplified form lacbus nut FPGA design jj unit under tes t Stimulus process lochus in t ocbus in LOCAL hours agent BUS ihe T The following procedures output a signal of type locbus
340. imulus processes for local bus access 19 ADM XRC SDK 4 9 3 User Guide Win32 ADM XRC SDK 4 9 3 User Guide Win32 Document version 4 9 3 1 O Copyright 2001 2009 Alpha Data ADM XRC SDK 4 9 3 User Guide Win32 Introduction ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Introduction Please choose one of the following topics About the ADM XRC SDK Hardware supported List of changes Upgrades to the SDK Sales and support 21 ADM XRC SDK 4 9 3 User Guide Win32 About the ADM XRC SDK ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data About the ADM XRC SDK 22 The ADM XRC SDK is a set of resources including an application programming interface API intended to assist the user in creating an application using one of Alpha Data s range of reconfigurable computing cards The API is a thin layer in user space that makes the necessary open close and device I O control calls to a kernel mode device driver provided by Alpha Data as a related package The ADM XRC SDK consists of the following components e ADM XRC SDK documentation this document e Documentation for PLX Technology s PCI9080 and PCI9656 e Sample applications in source and binary form e Sample FPGA designs in source and bitstream form e primer on the local bus used by Alpha Data s reconfigurable computing cards e FPGA pinouts in the form of constraints UCF files e API header files e
341. in32 ADMXRC2 FPGA TYPE ADMXRC2 FPGA RESVD46 46 ADMXRC2_FPGA_RESVD47 47 ADMXRC2_FPGA_RESVD48 48 ADMXRC2_FPGA_RESVD49 49 ADMXRC2_FPGA_RESVD50 50 ADMXRC2_FPGA_RESVD51 oL ADMXRC2_FPGA_RESVD52 52 ADMXRC2_FPGA_RESVD53 553 ADMXRC2 FPGA RESVD54 54 ADMXRC2 FPGA RESVD55 DO ADMXRC2 FPGA RESVD56 06 ADMXRC2_FPGA_RESVD57 Duk ADMXRC2_FPGA_RESVD58 58 ADMXRC2 FPGA RESVD59 59 ADMXRC2 FPGA RESVD60 60 ADMXRC2 FPGA RESVD61 61 ADMXRC2 FPGA RESVD62 62 ADMXRC2 FPGA RESVD63 63 ADMXRC2 FPGA 2VP2 64 ADMXRC2 FPGA 2VP4 65 ADMXRC2 FPGA 2VP7 66 ADMXRC2 FPGA 2VP20 67 ADMXRC2 FPGA 2VP30 2 68 ADMXRC2 FPGA 2VP40 69 ADMXRC2 FPGA 2VP50 70 ADMXRC2 FPGA 2VP100 ADMXRC2 FPGA 2VP125 72 ADMXRC2 FPGA 2VP70 73 ADMXRC2 FPGA RESVD74 74 ADMXRC2 FPGA RESVD75 muss ADMXRC2 FPGA RESVD76 76 ADMXRC2 FPGA RESVD77 TT ADMXRC2_FPGA_RESVD78 78 ADMXRC2_FPGA_RESVD79 79 ADMXRC2_FPGA_RESVD80 80 ADMXRC2_FPGA_RESVD81 81 ADMXRC2_FPGA_RESVD82 82 ADMXRC2_FPGA_RESVD83 903 ADMXRC2 FPGA RESVD84 84 ADMXRC2 FPGA RESVD85 5385 ADMXRC2 FPGA RESVD86 286 ADMXRC2 FPGA RESVD87 87 ADMXRC2 FPGA RESVD88 88 ADMXRC2 FPGA RESVD89 89 ADMXRC2 FPGA RESVD90 2 90 ADMXRC2 FPGA RESVD91 91 ADMXRC2_FPGA_RESVD92 92 ADMXRC2_FPGA_RESVD93 5 93 ADMXRC2 FPGA RESVD94 94 ADMXRC2 FPGA RESVD95 95 ADMXRC2_FPGA_4VLX15 96 ADMXRC2_FPGA_4VLX25
342. in32 LEOT mode LEOT and LBTERM LEOT in nonburst transfer In this example LEOT is asserted during a nonburst local bus cycle LADS Key m Signal is owned LAD by master m Signal is owned LBE adus LYVRITE i LBLAST LRE AD Y LBTERM LEOT Note 1 In this example since LBLAST is asserted when LEOT is asserted the current local bus cycle ends immediately When the cycle in which LEOT is asserted ends so does the DMA transfer LEOT in burst transfer In this example LEOT is asserted during a burst local bus cycle 251 ADM XRC SDK 4 9 3 User Guide Win32 LEOT mode ex PILLAI LADS Key m Signal is owned Lap A y OT y pz y 94 oy master us BED BES BET M byasee LWRITE LBLAST LRE AD Y LBTERM LEOT Note 1 When LEOT is sampled asserted by the bridge the bridge asserts LBLAST and the current local bus cycle terminates also ending the DMA transfer after one extra word has been transferred LEOT asserted with LBTERM In this example LEOT is asserted coincident with LBTERM during a burst local bus cycle LADS Key m Signal is owned LAD y Y 02 y 03 hy master Les BE Y 882 LWRITE LBLAST LRE AD LBTERM LEOT Note 1 In this example LEOT is sampled asserted by the bridge along with LBTERM Henc
343. ince this generates hundreds of bitstreams the runtime may be several hours The following commands would rebuild all of the bitstreams in the SDK 78 ADM XRC SDK 4 9 3 User Guide Win32 Building cd d ADMXRC SDK4 Nfpga make clean all Using a Makefile to build all VHDL bitstreams The Makefile in the fpga vhdl directory is provided for building all of the VHDL bitstreams from sources Since this generates hundreds of bitstreams the runtime may be several hours cd d ADMXRC_SDK4 fpga vhdl make clean all Using a Makefile to build all Verilog bitstreams The Makefile in the fpga verilog directory is provided for building all of the Verilog bitstreams from sources Since this generates hundreds of bitstreams the runtime may be several hours cd d ADMXRC_SDK4 fpga verilog make clean all Using a Makefile to build all bitstreams for a specific VHDL or Verilog design The Makefile in each design directory may be used to build all bitstreams for that design For example to build the bitstreams for all model device combinations of the VHDL version of the SIMPLE design issue the following commands cd d ADMXRC SDK4 NfpgaNvhdlNsimple make clean all Using a Makefile to build a bitstream for a specific VHDL or Verilog design model and device combination The Makefile in each design directory may also be used to build a bitstream specifically for a certain design model device combination For example the following commands
344. include all of the following source files relative to root of SDK installation fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif cmd_fifo vhd fpga vhdl common memif ddr2sdram ddr2sdram_iserdes_dq vhd fpga vhdl common memif ddr2sdram ddr2sdram_oserdes_dq vhd fpga vhdl common memif ddr2sdram ddr2sdram oserdes dqs vhd fpga vhdl common memif ddr2sdram ddr2sdram_clkfw vhd fpga vhdl common memif ddr2sdram ddr2sdram_ctrl vhd fpga vhdl common memif ddr2sdram ddr2sdram_dm vhd fpga vhdl common memif ddr2sdram ddr2sdram_dq_in vhd fpga vhdl common memif ddr2sdram ddr2sdram_dq_in_dc vhd fpga vhdl common memif ddr2sdram ddr2sdram_dq_out vhd 315 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port fpga vhdl common memif ddr2sdram ddr2sdram_dqs_in vhd fpga vhdl common memif ddr2sdram ddr2sdram_dqs_out vhd fpga vhdl common memit ddr2sdram ddr2sdram training dc vhd fpga vhdl common memif ddr2sdram ddr2sdram init vhd fpga vhdl common memif ddr2sdram ddr2sdram odt vhd fpga vhdl common memif ddr2sdram ddr2sdram port vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the port logical address a 4 auto train boolean If t
345. information Return value Value Meaning ADMXRC SUCCESS The information was obtained successfully ADMXRC INVALID HANDLE Card is not a valid handle to a card Description This function returns version information about the API library and driver A pointer to an ADMXRC VERSION INFO structure should be passed in the Info parameter 524 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC InstallErrorHandler ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC JInstallErrorHandler Prototype ADMXRC STATUS ADMXRC InstallErrorHandler ADMXRC HANDLER FUNCTION Routine Arguments Argument Type Purpose Routine In The error handler routine to install Return value Value Meaning ADMXRC SUCCESS The error handler routine was successfully installed or uninstalled ADMXRC FAILED The error handler routine could not be installed because another thread held the error Mutex for an excessive period of time Description This function is used to install a user defined error handler function that will be called whenever the ADM XRC function must return an error condition The error handler function should be of type ADMXRC HANDLER FUNCTION void MyErrorHandler const char FunctionName ADMXRC STATUS Code If Routine is non NULL it must point to a function of the same type as MyErrorHandler above If Routine is NULL any error handler function currently installed will be uninstalled A failed call to
346. ing application buffer Offset In Offset within application buffer Length In Number of bytes to transfer Local In Address of beginning of transfer on local bus Direction In Direction of DMA transfer Channel In DMA channel to use for the transfer DMAModeWord In Mode word to use for the DMA transfer Flags In Miscellaneous flags Timeout In out Timeout for DMA transfer Event In Event to use to wait for completion Return value Value Meaning ADMXRC2 SUCCESS The DMA transfer was performed successfully ADMXRC2 INVALID HANDLE Card is not a valid handle to a card ADMXRC2 INVALID DMADESC DMADesc is not a valid DMA descriptor ADMXRC2 INVALID PARAMETER An invalid parameter was passed ADMXRC2 DEVICE BUSY Could not begin DMA immediately as requested Description 436 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 DoDMA This function is used to perform a DMA transfer from an application buffer to the FPGA or from the FPGA to an application buffer DMA transfers are queued in a first come first served manner unless the Flags parameter see below specifies otherwise When a thread calls ADMXRC2 DoDMA it is blocked until the DMA transfer has been completed The DmaDesc parameter must be a valid DMA descriptor obtained via a call to ADMXRC2 SetupDMA This along with Offset implicitly specifies the application buffer that is the source or destination of data for the DMA transfer The Offset parameter is the offset into the user buffer at where the DMA transf
347. ing of a DDR SDRAM port ddr2sram pinout t Record type that describes the physical configuration of a DDR II SSRAM port family t Enumerated type that represents an FPGA family zbtsram pinout t Record type that describes the physical configuration of a ZBT SSRAM port Constants Name Datatype ddr2sdram pinout admxrc4fx ddr2sdram pinout t ddr2sdram pinout adpexrc4fx ddr2sdram pinout t ddr2sdram pinout admxrcblx ddr2sdram pinout t ddr2sdram pinout admxrcbt1 ddr2sdram pinout t ddr2sdram pinout admxrcbt2 ddr2sdram pinout t ddr2sdram pinout admxrcbtda1 ddr2sdram pinout t ddrsdram pinout admxpl ddrsdram pinout t ddrsdram pinout admxp ddrsdram pinout t ddr2sram pinout admxp ddr2sram pinout t ddr2sram pinout admxrcbt1 ddr2sram pinout t ddr2sram pinout admxrcbt2 ddr2sram pinout t ddr2sram pinout admxrcbtda1 ddr2sram pinout t zbtsram pinout admxrc zbtsram pinout t zbtsram pinout admxrcp zbtsram pinout t zbtsram pinout admxrc2l zbtsram pinout t zbtsram pinout admxrc2 zbtsram pinout t zbtsram pinout admxpl zbtsram pinout t zbtsram pinout admxrc4lx zbtsram pinout t 280 Function Pinout for an ADM XRC 4FX DDR II SDRAM bank Pinout for an ADPE XRC 4FX DDR II SDRAM bank Pinout for an ADM XRC 5LX DDR II SDRAM bank Pinout for an ADM XRC 5T1 DDR II SDRAM bank Pinout for an ADM XRC 5T2 ADM XRC 5T2 ADV DDR II SDRAM bank Pinout for an ADM XR
348. ing up the data bus of the DDR SDRAM bank This memory port transfers two words of data on the DQ wires for each command entered via the ce signal Accordingly the d width parameter which is the width of d and q is typically specified by the user application as being twice rd width However other values can be passed for d width o If d width gt 2 rd width then the memory port simply truncates d internally so that its width is 2 rd width Data read from the memory devices is zero extended so that its width is d width before being returned on q o d width 2 rd width is the optimal usage case o If d width lt 2 rd width then the memory port zero extends d internally so that its width is 2 rd width The a width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a DDR SDRAM bank Hence the required value of a width depends on what memory devices are actually in use As an example consider two physical banks of DDR SDRAM devices that use 13 row bits 10 column bits and 2 internal bank address bits The number of address bits is 13 row address bits 10 column address bits 2 internal bank address bits 1 2 physical banks CS pins 26 We must now subtract 1 because logical memory locations are twice as wide as the physical memory locations due to transferring two words on the DQ pins for every command en
349. initiate another burst on the local bus until LDREQ n is reasserted Demand mode DMA single word read LDREQ deasserted early In this example LDREQ n is deasserted early in order to perform a single word demand mode DMA burst 247 ADM XRC SDK 4 9 3 User Guide Win32 Demand mode LADS if t Key m Signal is driven LA by bus bridge m Signal is driven by LBE FPGA mE SSSSSSSSSSSSSNNSNNNSNNNNNNNNNSNNNMO AN 0 Sueste turnaround LBLAST LRE AD Y LBETERM LD LDREG n LDACK n f demand mode DMA read LDRE G3 deasserted early for single word transfer Note 1 In order to make a DMA engine perform a single word demand mode DMA burst and then pause LDREQ n must be deasserted on or before the cycle in which LDACK n is asserted Demand mode DMA write LBTERM breaks up bursts In this example LBTERM breaks up the demand mode DMA bursts 248 ADM XRC SDK 4 9 3 User Guide Win32 Demand mode LADS FF tf FF Ld Ld Key m Signal is driven LA c by local bus bridge LBE BED Beg Signals driven by 7 T Suggested turnaround LBLASTR sss LRE AD Y tj t LBTERMZ 0 ti ty LD DO D3 LDREG n LDACK3 n demand mode DM A write bursts broken up by LBTE RM Note 1 Asserting LBTERM does not in itself pause a DMA engine it merely breaks up the bursts 249 ADM XRC SD
350. interface design ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Tips for local bus interface design The following tips may help designers new to the local bus protocol 258 Beware of unintentionally permitting bursting in your FPGA design Some platforms can generate PCI reads and writes that result in bursts on the local bus while others cannot If your FPGA design cannot handle bursting on the local bus it must prevent bursting or risk failing unexpectedly on certain platforms See tip 2 below The simplest way to prevent your FPGA design bursting on the local bus is to always assert LBTERM along with LREADY It is not unnecessary to support bursting over the entire region of local bus space that your design uses For instance if you have implemented a a set of registers in one region and b a memory region it may not be worthwhile going to the effort of supporting bursting in the register region as typically the host is performing random accesses to the registers rather than performing bulk data transfer However designing the memory region to support bursting is probably worthwhile as it is likely to be used for bulk data transfer See tip 2 above Latch the local bus address on the rising edge of LCLK when LADS is asserted and then increment the address internally within the FPGA each time you assert LREADY Use of an address generated within the FPGA as opposed to taking the addres
351. interrupts on the host FPGA Space Usage The design implements several registers for generating and acknowledging interrupts Interrupt Mask register IMASK local bus address 0x0 Bits Mnemonic Type Function 31 0 MASK RAN Bit vector that unmasks or masks one of 32 interrupt sources in the FPGA A 1 in a bit position masks disables the corresponding interrupt source The IMASK register allows individual interrupt sources to be enabled unmasked or disabled masked A disabled masked interrupt source cannot generate a local bus interrupt via the FINTI signal Interrupt Status register ISTAT local bus address 0x4 Bits Mnemonic Type Function 31 0 STAT R W1C When read returns a bit vector that indicates which of the 32 interrupt sources within the FPGA are active A 1 in a particular bit position indicates that the corresponding interrupt source is active When written 1 in a particular bit position sets the corresponding interrupt source to inactive The ISTAT register indicates which of 32 interrupt sources in the FPGA are active If an interrupt is active 1 will be read in the corresponding bit position of ISTAT regardless of whether it is enabled or disabled via IMASK Writing to a 1 to a particular bit position sets the corresponding interrupt to inactive Interrupt Arm register IARM local bus address 0x8 Bits Mnemonic Type Function 31 0 n a WO Writing to this register forces the FINTI signal high for
352. ions Options Option Argument type Meaning card base 10 integer ID of card to open index base 10 integer Index of card to open FPGA Design 55 ADM XRC SDK 4 9 3 User Guide Win32 FrontlO The FrontlO sample application uses the FrontlO sample design Verilog VHDL 56 ADM XRC SDK 4 9 3 User Guide Win32 Info ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Info utility Model support Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview Info is a utility that displays information including the Vital Product Data for a reconfigurable computing card Syntax info options Options Option Argument type card base 10 integer index base 10 integer Description The Info utility produces output in the following form 57 Supported Meaning ID of card to open Index of card to open ADM XRC SDK 4 9 3 User Guide Win32 Info 58 API ver Driver ver Board Type Card ID Serial Number Board Logic Rev FPGA Number of clock generators Number of DMA channels Number of spaces Space 0 FPGA Physical base Local range Virtual range Space 1 control Physical base Local range Virtual range Number of RAM banks Bank presence bitmap RAM Bank 00 RAM Bank 01 RAM
353. ions targetting models that use DDR II SDRAM memory may require as much as 200 microseconds of simulated time for DLL DCM PLL locking and memory bank training to complete This may result in long periods of inactivity on the local bus Such periods of inactivity do not necesary indicate that the simulation is not working as expected Some warnings may be emitted by memory models DCMs DLLs and PLLs These relate to startup and can safely be ignored as the design is held in reset until clocks have stabilized Model Shell command ADM XRC 4FX cd xrc4fx vsim do do memory64 xrc4fx do ADPE XRC 4FX cd xrce4fx vsim do do memory64 xrce4fx do ADM XRC 5LX cd xrc5lx vsim do do memory64 xrcb5lx do ADM XRC 5T1 cd xrcbt1 vsim do do memory64 xrcbt1 do ADM XRC 5T2 cd xrc5t2 ADM XRC 5T2 ADV vsim do do memory64 xrc5t2 do 149 ADM XRC SDK 4 9 3 User Guide Win32 RearIO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data RearlO sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga vhdl reario Synopsis FPGA Space Usage The RearlO desi
354. irst failure occurred Explanation of design At the highest level of abstraction the design consists of 3 logical blocks 117 ADM XRC SDK 4 9 3 User Guide Win32 Memory ls Local bus dock Memory clock domain domain Local Bus Interface Ports User Application Local Bus Chip driven Memory T est To from memory banks High level view of the MEMORY reference design The local bus interface enables the CPU to read and write the memory banks At the same time the user application module can also read and write the memory banks The local bus interface and the user application also communicate with each other via a set of registers The user application as supplied in this SDK is in fact a chip driven memory test which can test all memory banks simultaneously on command from the host The user can rewrite the user application replacing the memory test logic with whatever processing logic he or she requires Because the FPGA space is limited to 4MB on most models the local bus interface of the design divides the FPGA space into a lower 2MB region for registers and an upper 2MB window for accessing the memory A bank register selects which bank is currently being accessed and a page register is provided so that all of a large memory bank can be accessed even though the window through which it is accessed is 2MB in size The user application on the other hand has no such restrictions It can access all ban
355. is always a multiple of 4 bytes is to use LBE 3 see the LBE local bus signal to qualify actually committing the data to the FIFO When word is written to the FPGA with LBE 3 deasserted the FPGA latches the data for those byte enables that are asserted but does not yet commit the data to the FIFO Eventually the DMA transfer will pick up where it left off and assert LBE 3 along with the data when it begins the next block in the linked list DMA transfer At this point the FPGA commits the completed word to the FIFO This does not result in any restrictions on the alignment of buffers in host memory Unaligned DMA transfer to from non memorylike local bus region assuming 64 bit local data bus 240 ADM XRC SDK 4 9 3 User Guide Win32 Caveats of DMA transfers If the local bus has 64 bit wide data then an aligned host memory buffer is one that begins at an address whose lower 3 bits are zero By a similar process of reasoning to the 32 bit case above the issues related to unaligned DMA transfers can be addressed in the following ways 241 1 Ensure that DMA transfers are performed using buffers that are aligned to a QWORD 8 byte boundary This may not be possible for instance if the application does not control how memory is allocated A better solution assuming that the length of block of data in a DMA transfer is always a multiple of 8 bytes is to use LBE 7 see the LBE local bus signal to qualify actually comm
356. is normally required per demand mode DMA channel used by the FPGA and each instance is normally associated with a stimulus process In the figure above the signals on the right should be connected to the FPGA while the signals on the left are driven by the stimulus process The generics should be mapped as follows Generic Map to tco p2p A value of type time that represents the desired local bus clock to output delay for signals such as LDACK This parameter has a suitable default value so it need not be specified 406 ADM XRC SDK 4 9 3 User Guide Win32 locbus agent ddma The first group of ports must be mapped to signals driven or used by the stimulus process associated with the local bus agent Port Map to dd in A signal of type locbus ddma in t used by the stimulus process dd out A signal of type locbus ddma out t driven by the stimulus process The second group of ports must be mapped to signals driven or input by the local bus arbiter Port Map to Idack 1 A signal in the testbench that is input by the FPGA corresponding to LDACK Idreq I A signal in the testbench that is driven by the FPGA corresponding to LDREQ 407 ADM XRC SDK 4 9 3 User Guide Win32 locbus agent mux32 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus agent mux32 Declaration Synopsis Description Declaration component locbus agent mux32 ge
357. ister reading the same or another USER register is not guaranteed to return a value that reflects what was just written until approximately 12 local bus clock cycles have elapsed Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file ADM XRC with memory xrc v scr Virtex ADM XRC with memory xrc ve scr Virtex E EM ADM XRC P with memory xrcp v scr Virtex ADM XRC P with memory xrcp ve scr Virtex E EM ADM XRC Il Lite memory xrc2l v2 scr ADM XRC II memory xrc2 v2 scr ADM XPL with memory xpl v2p scr 2VP7 ADM XPL with memory xpl v2p scr 2VP20 or 2VP30 ADM XP with memory xp v2p scr 2VP70 ADM XP with memory xp v2p scr 2VP100 127 XST project file memory xrc v prj memory xrc ve prj memory xrcp v prj memory xrcp ve prj memory xrc2l v2 prj memory xrc2 v2 prj memory xpl v2p prj memory xpl v2p prj memory xp v2p prj memory xp v2p prj UCF file xrc memory xrc v ucf xrc memory xrc ve ucf xrcp memory xrcp v ucf xrcp memory xrcp ve ucf xrc2el memory xrc2l ucf xrc2 memory xrc2 ucf xpl memory xpl 2vp7 ucf xpl memory xpl 2vp20 ucf xp memory xp 2vp70 ucf xp memory xp 2vp100 ucf ADM XRC SDK 4 9 3 User Guide Win32 Memory ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with VSFXT
358. it may take from minutes to hours to run to completion The user should also verify that at least 550MB of disk space are available before entering these commands 2 Generate Project Navigator files for all sample VHDL designs To generate project files for all sample VHDL designs in the SDK start a shell and issue the following commands cd d ADXMRC SDK4 M fpga vhdl projnav mkproj Because this process creates hundreds of ISE files it may take from minutes to hours to run to completion The user should also verify that at least 400MB of disk space are available before entering these commands 3 Generate Project Navigator files for all sample Verilog designs 76 ADM XRC SDK 4 9 3 User Guide Win32 Generating ISE project files To generate project files for all sample Verilog designs in the SDK start a shell and issue the following commands cd d ADXMRC_SDK4 fpga verilog projnav mkproj Because this process creates hundreds of ISE files it may take from minutes to hours to run to completion The user should also verify that at least 150MB of disk space are available before entering these commands 4 Generate Project Navigator files for a specific VHDL or Verilog design To generate project files for a specific sample VHDL or Verilog design start a shell and issue the following commands cd d ADXMRC_SDK4 fpga lt language gt lt design gt projnav mkproj where language is either vhdl or verilog and design
359. it mode Description On startup the application performs the following steps 1 Loads the DDMA bitstream into the FPGA using a DMA transfer 2 Creates two user space buffers one for the send direction CPU memory to FPGA and one for the receive direction FPGA to CPU memory The API call ADMXRC2_SetupDMA is used to lock down the user space buffers in physical memory 3 Creates a sender thread which performs demand mode DMA transfers from the host to the FPGA using the host to FPGA DMA buffer 4 Creates a receiver thread which performs demand mode DMA transfers from the FPGA to the host using the FPGA to host DMA buffer This thread also performs some simple checks for correctness on the received data Once initialized the application enters a loop where it expects a string to be entered by the user Entering anything but q including an empty string causes the current data transfer counts to be displayed and entering q causes the application to clean up and then terminate Clean up consists of terminating the threads created on startup unlocking the user space buffers using the ADMXRC2_UnsetupDMA API call and frees the user space buffers FPGA Design Normally this application uses the DDMA sample FPGA design Verilog VHDL However if the 64 option is specified on the command line the DDMA64 sample FPGA design Verilog VHDL is used instead It is important to note that when the 64 bit version is used
360. itest xrc2 v2 prj itest xrc2 ucf ADM XPL itest xpl v2p scr itest xpl v2p prj itest xpl ucf ADM XP itest xp v2p scr itest xp v2p prj itest xp ucf ADP WRC II itest wrc2 v2 scr itest wrc2 v2 prj itest wrc2 ucf ADP DRC II itest drc2 v2 scr itest drc2 v2 prj itest drc2 ucf ADP XPI itest xpi v2p scr itest xpi v2p prj itest xpi ucf ADM XRC 4LX itest xrc4lx v4lx scr itest xrc4lx v4lx prj itest xrc4Ix ucf 103 ADM XRC SDK 4 9 3 User Guide Win32 ITest ADM XRC 4SX ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with FXT ADM XRC 5T1 with LXT ADM XRC 5T1 with SXT ADM XRC 5T2 or ADM XRC 5T2 ADV with FXT ADM XRC 5T2 or ADM XRC 5T2 ADV with LXT ADM XRC 5T2 or ADM XRC 5T2 ADV with SXT ADM XRC 5TZ with FXT ADM XRC 5TZ with LXT ADM XRC 5TZ with SXT ADM XRC 5T DA1 with FXT ADM XRC 5T DA1 with LXT ADM XRC 5T DA1 with SXT itest xrc4sx v4sx scr itest xrcAfx v4fx scr itest xrcAfx v4fx scr itest xrce4fx v4fx scr itest xrce4fx v4fx ser itest xrcblx v5blx scr itest xrcbt1 vbfxt scr itest xrcbt1 vblxt scr itest xrcbt1 v5bsxt scr itest xrcbt2 vbfxt scr itest xrcbt2 vblxt scr itest xrcbt2 v5sxt scr itest xrcbtz vbfxt scr itest xrcbtz vblxt scr itest xrc5tz v5sxt scr itest xrcbtda1 vbfxt scr itest xrcbtda1 vblxt scr itest xrcbtda1 vbsxt scr Project Navigator files Project Navigator projects ca
361. its 3 0 31 4 110 Mnemonic Type Function BANK RAN Selects which bank is currently available via the memory access window at local bus address 0x200000 RO MBZ Reserved ADM XRC SDK 4 9 3 User Guide Win32 Memory Page register PAGE local bus address 0x4 Bits Mnemonic Type 12 0 PAGE R W 31 13 RO MBZ Function Value that selects which 2MB page of memory is currently available via the memory access window at local bus address 0x200000 Reserved Memory control register MEMCTL local bus address 0x8 Bits Mnemonic Type 0 RST R W 31 1 RO MBZ Status register STATUS local bus address 0x10 Function While this field is 1 the entire memory subsystem is held in reset An application should NOT attempt to access memory while this field is 1 When 0 the memory subsystem is not held in reset Reserved This register indicates the general health of the FPGA in the form of lock flags from DLL DCMs and PLLs as well as training flags from any self training memory banks Bits Mnemonic Type 0 LLOCK RO 0 SLLOCK R W1C 7 2 RO MBZ 15 8 MLOCK RO 23 16 SMLOCK R W1C 31 24 RO MBZ Function When 1 indicates that the DLL or DCM that distributes LCLK within the FPGA is locked If 500ms or later after configuration of the FPGA this field is not 1 the application should consider this a fatal error Sticky loss of lock flag When 1 indicates that the DLL or DCM that distributes LCLK within the FPGA has
362. itting the data to the FIFO When a word is written to the FPGA with LBE 7 deasserted the FPGA latches the data for those byte enables that are asserted but does not yet commit the data to the FIFO Eventually the DMA transfer will pick up where it left off and assert LBE 7 along with the data when it begins the next block in the linked list DMA transfer At this point the FPGA commits the completed word to the FIFO This does not result in any restrictions on the alignment of buffers in host memory ADM XRC SDK 4 9 3 User Guide Win32 Constant address mode ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Constant address mode DMA transfers In a constant address mode DMA transfer the local bus address that is presented on LA or LAD is held constant for the entire DMA transfer This is useful for accessing a register that is actually the head or tail of a FIFO memory that is mapped at a particular local bus address Instead of the local bus address incrementing automatically it remains constant both during a burst and from one local bus burst to the next Note that this is completely unrelated to PCI addressing as the PCI specification does not allow for constant PCI addressing Constant address mode may be freely mixed with the other DMA modes such as demand mode and LEOT mode To use LEOT mode the host must specify ADMXRC2 DMAMODE FIXEDLOCAL in a call to ADMXRC2 BuildDMAModeWord The mode word that include
363. j simple64 xrcbt1 v5sxt prj UCF file simple64 xpl ucf simple64 xp ucf simple64 xpi ucf simple64 xrc4fx 4vfx100 ucf simple64 xrc4fx 4vfx140 ucf simple64 xrce4fx 4vfx100 ucf simple64 xrce4fx 4vfx140 ucf simple64 xrcb5lx ucf simple64 xrcbt1 5vixt ucf simple64 xrc5t1 ucf simple64 xrc5t1 ucf ADM XRC SDK 4 9 3 User Guide Win32 Simple64 ADM XRC 5T2 simple64 xrc5t2 v5fxt scr ADM XRC 5T2 ADV with FXT ADM XRC 5T2 simple64 xrcbt2 v5lxt scr ADM XRC 5T2 ADV with LXT ADM XRC 5T2 simple64 xrcbt2 v5sxt scr ADM XRC 5T2 ADV with SXT simple64 xrcbt2 vb5fxt prj simple64 xrc5t2 v5Ixt prj simple64 xrc5t2 v5sxt prj Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt ADP XPI projnav xpi lt device gt ADM XRC 4FX projnav xrc4fx lt device gt ADPE XRC 4FX projnav xrce4fx lt device gt ADM XRC 5LX projnav xrc5 x lt device gt ADM XRC 5T1 projnav xrc5t1 lt device gt ADM XRC 5T2 projnav xrc5t1 lt device gt ADM XRC 5T2 ADV Modelsim scripts simple64 xrc5t2 5vfxt uct simple64 xrc5t2 ucf simple64 xrcbt2 ucf Example Modelsim compatible script files for simulating this design are provided Refer to the following table for the appropriate command line for a particular model Model Shell command ADM XPL vsim do do
364. k Hence the required value of a width depends on what type of memory devices are in use and their density 2 Assuming that the unfair parameter is true the bias parameter specifies the favored client i e which client is given priority access to the memory port The favored client can interrupt a burst of memory accesses by one of the unfavored clients regardless of the value of latency A value of 0 represents client 0 and a value of 3 represents client 3 If the unfair parameter is false however bias is ignored and there is no favored client 3 Thed width parameter is the width of the logical data busses d d0 d1 d2 d3 q q0 q1 q2 and q3 It is generally determined by the physical data width of the memory bank and the type of memory devices in use DDR memory devices in particular generally have a logical data width that is 2 or 4 times the physical data width 4 The latency parameter is the minimum number of consecutive clock cycles that a particular client is awarded access to the memory port without being interrupted by another unfavored client The purpose of this parameter is to enable a reasonable efficiency to be achieved for memory types that benefit from bursting and locality of access for example DDR and DDR II SDRAM Note however that if unfair is true and the favored client requests access to the memory port the favored client will be granted access to the memory port regardless of the value of latency and regardless of any u
365. k experiment This signal is a vector where each bit of the vector should be connected directly to the tstdone port of an instance of ddrsdram port v2 The ddrsdram port v2 instance pulses this signal when it has completed a readback experiment as part of the training sequence in Readback experiment successful This signal is a vector where each bit of the vector should be connected directly to the tstok port of an instance of ddrsdram port v2 The ddrsdram port v2 instance asserts this signal qualified by the corresponding bit of the tstdone vector when a readback experiment is completed without error out Training successful This signal is asserted when training has been completed for all associated ddrsdram port v2 instances and was successful i e a data capture window was found for all memory ports If training is completed but was unsuccessful i e a data capture window could not be found for one or more of the memory ports this signal will remain deasserted even though training has been completed There is no required relationship between clk and the capture clocks clkcO and clkc180 and no required relationship between clk and clkc However depending on the needs of the application clk and clkc may or may not be exactly the same signal The signal used to clock an instance of ddrsdram training v2 via its clk input must be the same or an exact copy of the signal used to clock any associated instances of ddrsdram p
366. ks of memory simultaneously without need for page or bank selection Explanation of memory main module The following is a block diagram of the memory main module which is not specific to any model and has been written in such a way that it expects to be wrapped up by a model specific wrapper It implements the local bus interface and the FPGA registers It also contains the one and only instance of the memory banks module as well as the one and only instance of the user app module 118 ADM XRC SDK 4 9 3 User Guide Win32 Memory local bus dock domain l memory fuser dock domain 4 c LADS LBLAST etc LREAD Yit LETERM plxdssm user cortrol user app cortrol user status control address data tag etc for all banks bank register Registers DQ 55 datato memories 32 LBE in DQ byte enablesto memories Z memory main The memory main module As a brief aside the wrapper for the module memory main is model specific and is also the top level of the design For example there is an an ADM XPL specific wrapper module in the source file xpl memory xpl vhd that instantiates the one and only instance of the memory main module and takes care of some ADM XPL specific details such as inputting global clocks Explanation of memory banks module As mentioned above the memory main module encloses one instance of the memory banks module The memory banks module is entirely mode
367. l specific and comes in several versions one per model Its job is fourfold 1 To present a uniform interface in the local bus clock domain to the memory main module no matter what type of memory devices are present for a given model 2 To decouple the local bus clock domain from the memory clock domain as the two clock domains are generally independent in phase and frequency 3 To instantiate memory ports that are appropriate to the model For example the ADM XRC 4FX version of the memory banks module instantiates four DDR II SDRAM ports 4 To handle any difference in the width of the local bus data 32 bits and the width of the logical data written to and read from the memory ports o For inbound data that is writes to the memory the port module is instantiated for some models since a logical memory data word may be wider than a 32 bit local bus data word This is effectively a latch that enables a complete memory word plus byte enables to be assembled before it is actually committed to memory o For outbound data that is reads from the memory a multiplexor called port mux selects a 32 bit word from the logical memory data depending on the low couple of local bus address bits 119 ADM XRC SDK 4 9 3 User Guide Win32 Memory 5 To share the memory ports between the local bus interface and the user application by instantiating one arbitration module arbiter 2 per memory port The following figure illustrates
368. lable to the host This example demonstrates the following e A bursting local bus interface in the FPGA e Interfacing of ZBT SSRAMs to the FPGA e Bursting if supported need not be supported over the entire FPGA space In this design only the 2MB SSRAM window supports bursting e Since the FPGA does not distinguish between a direct slave burst initiated by the host CPU and a burst initiated by a DMA engines in the local bus bridge the host can use programmed I O or DMA to transfer data e Generation of deskewed copies of the local bus clock LCLK that are driven off chip to the SSRAMs using DLLs Virtex E EM or DCMs Virtex II IIPro This technique is used to ensure that the ZBT SSRAM devices and the FPGA operate using the same clock The design accomodates pipelined or flowthrough JEDEC compliant ZBT SSRAM devices Some ZBT devices are capable of operating in either pipelined or flowthrough mode depending on the level on a mode select pin The FPGA design therefore contains a register that selects pipelined or flowthrough operation The design maps the data pins of each physical SSRAM bank to the 64 bit local data bus Currently only the ADM XPL is capable of operating with a 64 bit local bus The ADM XPL has a single 64 bit SSRAM device and so this device s data bits can be mapped one to one to the local data bus bits The design also contains a register that selects the number of address bits in the logical SSRAM banks Addr
369. lable via the This option causes MAP to spend properties for the Map process extra time mapping a design It increases the runtime of MAP but Map Effort Level High generally improves quality of results significantly Note that this option does not apply to the Virtex E EM architecture 200 ADM XRC SDK 4 9 3 User Guide Win32 Running the Xilinx tools PAR ol high BITGEN g drivedone yes BITGEN g unusedpin pullnone BITGEN g compress Tips for running the Xilinx tools This option is available via the properties for the Place amp Route process Place amp Route Effort Level Overall High This option is available via the properties for the Generate Programming File process Drive Done Pin High z True This option is available via the properties for the Generate Programming File process Unused IOB Pins Float This option is available via the properties for the Generate Programming File process Enable BitStream Compression z True This option causes PAR to spend extra time both on the placement phase and the routing phase It increases the runtime of PAR but generally improves quality of results significantly This option causes the bitstream to be generated such that the DONE pin is driven high as opposed to floating once configuration is completed This option should be used for all bitstreams that target Alpha Data reconfigurable computing cards This option prevents
370. lash options program BIT filename flash options verify BIT filename 53 ADM XRC SDK 4 9 3 User Guide Win32 Flash Options Option card failsafe tfailsafe index Description Argument type base 10 integer n a n a base 10 integer The Flash utility has four commands Meaning ID of card to open Command applies to normal image default see below Command applies to failsafe image see below Index of card to open chkblank Verifies that the image is blank This command has no additional arguments erase Erases the image This command has no additional arguments program Erases the image and then programs a BIT file into it This command requires one additional argument which is the name of the BIT file to be programmed into the image verify Verifies that image contains a particular BIT file and that the image has not been corrupted This command requires one additional argument which is the name of the BIT file against which the image is to be verified An image is defined to be a region of Flash memory designated for holding an FPGA bitstream that is used to configure the target FPGA at power on If the image is empty then the target FPGA is not configured from it at power on unless the failsafe image is non empty see below Some models feature a failsafe image that is automatically loaded at power on should the normal image be blank The failsafe image i
371. le see below shows multiple local bus agents connected to the local bus The Simple sample FPGA design includes a testbench that works in the manner described above A multithreaded testbench Sometimes it is necessary to simulate multiple threads of execution that access the FPGA For example there may be two stimulus processes representing the DMA channels built into the PCI interface of an ADM XRC series card and one stimulus process representing the Host CPU for a total of three threads This arrangement is illustrated by the following figure 361 ADM XRC SDK 4 9 3 User Guide Win32 PLXSIM package VHDL locbus ddma out t DC UI UT Demand Idack I D locbus cima int DMA agent 0 Idreq 1 lt 0 gt Stimulus process Local bus FPGA design agent unit under test 0 Ihalda 02 Ihold 02 locbus ddma out t Demand Idack_I lt 1 gt Arbiter iocbus mma i t DMA agent 1 Idreq 17 Stimulus process Iclk Local bus lreset_ agent lads 1 1 r P Uu C N lholda lt 1 gt Ihold lt 1 gt locbus out t Stimulus process 2 Q4 08s Localbus agent 2 lholda lt 2 gt Ihold lt 2 gt Demand DMA agents which are instances of a component provided by the plxsim package are optional and are used when a stimulus process must perform demand mode DMA transfers on the local bus Generally there is one demand DMA agent per DMA channel that is used in demand
372. le can be used to load a Xilinx bitstream into an ADMXRC_IMAGE variable As ADMXRC2_LoadFpgaFile allocates memory to hold the data it is the application s responsibility to free the memory when no longer required using ADMXRC_UnloadFpgaFile The ADMXRC FindlmageOffset function should be used to find the beginning of SelectMap data within a loaded bitstream and its bit order must be reversed with ADMXRC ReverseBytes before using it to configure the FPGA using ADMXRC ConfigureFromBuffer or ADMXRC ConfigureFromBufferDMA 567 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC STATUS ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC STATUS Declaration typedef enum ADMXRC SUCCESS 0 ADMXRC INTERNAL ERROR 0x1000 ADMXRC NO MEMORY ADMXRC CARD NOT FOUND ADMXRC FILE NOT FOUND ADMXRC INVALID FILE ADMXRC FPGA MISMATCH 14 ADMXRC INVALID HANDLE ADMXRC TIMEOUT ADMXRC CARD BUSY ADMXRC INVALID PARAMETER ADMXRC CLOSED ADMXRC CARD ERROR ADMXRC NOT SUPPORTED ADMXRC DEVICE BUSY ADMXRC INVALID DMADESC ADMXRC NO DMADESC ADMXRC FAILED ADMXRC PENDING ADMX ADMX ADMX RC UNKNOWN ERROR RC NULL POINTER RC CANCELLED ADMXRC BAD DRIVER ADMXRC STATUS Description
373. length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes written on the local bus 402 ADM XRC SDK 4 9 3 User Guide Win32 lbpcheck ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference Ibpcheck Declaration Synopsis Description Declaration component lbpcheck generic multiplexed wide port lclk lreset 1 lads 1l 164 la lad 1o lad hi lbe lo lbe hi 1 lwrite lblast 1 lready 1 lbterm 1 end component Synopsis in in in in in in in in in in in in in in in boolean boolean Qo uoooouoooououucodu td logic td logic td logic td logic td logic vector 31 downto 2 td logic vector 31 downto 0 td logic vector 63 downto 32 td logic vector 3 downto 0 td logic vector 7 downto 4 td logic td logic td logic td logic Non synthesizable testbench component that flags local bus protocol errors 403 d ADM XRC SDK 4 9 3 User Guide Win32 lbpcheck multiplexed wide dk lads 1 64 la lad l lad hi Ibe lao 1 1 Iblazt I Ireadwy 1 lnpoheck Description This component can be instantiated in a testbench to verify the local bus protocol It is fully passive and cannot interfere with the operation of the local bus The generics should be mapped as follows
374. lk data transfer in almost all situations The following figure illustrates a DMA transfer from host memory to a PCI device on a fictitious platform with 8GB of memory requiring the use of bounce buffers 236 ADM XRC SDK 4 9 3 User Guide Win32 What happens during a DMA transfer Physical memory 2 0000 0000 Key to symbols top of memory mem copy operation 4 reference Ox0 C000 0000 3GB boundary Scatter gather table for PCI device 0x0 0000 0000 bottom of memory In this fictitious platform the first 3GB of memory are accessible to PCI devices In the figure above one of the pages of the user buffer falls within the first 3GB of memory Thus that page need not be copied before the DMA transfer is kicked off on the PCI device The other 3 pages however lie above the 3GB boundary and thus are copied to bounce buffers The bounce buffers lie below the 3GB boundary It should be noted that on many platforms a driver is presented with an abstract kernel level DMA programming interface and thus has little choice about whether or not bounce buffers are used Large DMA transfers from the point of view of the user application might not be performed as a single DMA transfer In fact they may be performed in several chunks by the Alpha Data ADM XRC driver The operating system s resources for creating bounce buffers scatter gather tables etc are finite and thus there is a limit on the size of a
375. lkO domain clkO in Clock for user interface 5 All other signals except rst are synchronous to clkO clk90 in Clock phase 90 5 This clock must be the same frequency as but 90 degrees behind in phase 340 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 clk180 clk270 clkcO clkc180 dll off qtag ready rst sr tag 341 in in out out out Clock phase 180 5 This clock must the same frequency as but 180 degrees behind in phase Clock phase 270 5 This clock must the same frequency as but 270 degrees behind in phase Capture clock phase 0 5 9 This clock is normally driven directly by the component ddr2sram_training_v2 and is used by ddr2sram_port_v2 to capture data read from the SSRAM device in the FPGA s IOBs Capture clock phase 180 5 9 This clock is normally driven directly by the component ddr2sram_training_v2 and is used by ddr2sram_port_v2 to capture data read from the SSRAM device in the FPGA s IOBs Data to memory User code must place valid data on d whenever a write command is entered ce and w both asserted DLL disable sideband signal 6 User code should drive this input with 0 for normal operation but driving it with 1 causes the DOFF field within rc to be asserted Data from memory When valid is asserted by the memory port as a result of a read command q reflects the data read from memory Tag out When valid i
376. ll of the specified region In this case the entire region is mapped and BytesSpanned will be equal to Length Physical memory Application buffer 1 PageLength T PagesPci 1 n start Pagesopanned 2 BytesSpanned n Init Offset 0 e MaxPages is less than the actual number of pages spanned by the region in the user buffer specified by Length and Offset The function will only map the first MaxPages In this case PagesSpanned will be equal to MaxPages and BytesSpanned will be less than the Length parameter 529 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC MapbDirectMaster Physical memory 5 Application buffer T Pagel amolh en PagesPci 1 start Pagesopanned 4 PagesPci 2 BytesSpanned Init ffset PagesPci 0 530 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC OpenCard ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC OpenCard Prototype ADMXRC STATUS ADMXRC_OpenCard ADMXRC DEVICE NUM ADMXRC_HANDLE Card Arguments Argument Type Purpose CardID In ID of card to open Card Out Handle to opened card Return value Value Meaning ADMXRC SUCCESS The card was successfully opened ADMXRC CARD NOT FOUND The card was in use or not physically present Description This function is used to open and obtain a handle to an ADM XRC card The particular card to open is identified by its ca
377. ll xrcbt2 ucf ADM XRC 5T2 ADV with SXT Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav xrc lt device gt ADM XRC P projnav xrcp lt device gt ADM XRC II Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt ADP WRC II projnav wrc2 lt device gt ADP DRC II projnavdrc2 device ADP XPI projnav xpi lt device gt ADM XRC 4LX projnav xrc4 x lt device gt ADM XRC 4SX projnav xrc4sx lt device gt ADM XRC 4FX projnav xrc4fx lt device gt ADPE XRC 4FX projnav xrce4fx lt device gt ADM XRC 5LX projnav xrc5 x lt device gt ADM XRC 5T1 projnav xrc5t1 lt device gt ADM XRC 5T2 projnav xrc5t2 lt device gt ADM XRC 5T2 ADV Modelsim scripts Example Modelsim compatible script files for simulating this design are provided Refer to the following table for the appropriate command line for a particular model Model Shell command ADM XRC vsim do do dll do ADM XRC P vsim do do dll do ADM XRC II Lite vsim do do dll xrc2 do ADM XRC II vsim do do dll xrc2 do ADM XPL vsim do do dll xpl do ADM XP vsim do do dll xpl do ADP WRC II vsim do do dll wrc2 do ADP DRC II vsim do do dll wrc2 do ADP XPI vsim do do dll xpi do ADM XRC 4LX vsim do do dll xrc4lx do 97 ADM XRC SDK 4 9 3 User Guide Win32 DLL ADM XRC 4SX vsi
378. local bus bridge ADM XRC ADM XRC P ADM XRC II Lite do not have a bussed LBTERM signal Instead there is a pair of signals LBTERM and LBTERMO whose usage is as follows e When the FPGA is a slave ie the PCI9080 is the master the FPGA drives LBTERM to the PCI9080 e When the PCI9080 is a slave ie the FPGA is the master the PCI9080 drives LBTERMOX to the FPGA This pair of signals therefore performs the same function as a bussed LBTERM signal given that one of them is always unused in any particular cycle In all other models this arrangement has been rationalized into a single LBTERM signal that can be driven by either the local bus bridge or the FPGA depending on which is the master Note 3 LREADY LREADYI amp LREADYO Models featuring a PCI9080 as the local bus bridge ADM XRC ADM XRC P ADM XRC II Lite do not have a bussed LREADY signal Instead there is a pair of signals LREADYI LREADYO whose usage is as follows e When the FPGA is a slave ie the PCI9080 is the master the FPGA drives LREADYI to the PCI9080 e When the PCI9080 is a slave ie the FPGA is the master the PCI9080 drives LREADYO to the FPGA This pair of signals therefore performs the same function as a bussed LREADY signal given that one of them is always unused in any particular cycle In all other models this arrangement has been rationalized into a single LREADY signal that can be driven by either the local bus bridge or the FP
379. lost lock at some point When written with 1 this field is cleared to 0 Reserved Each bit of this field represents a DCM DLL or PLL A 1 indicates that lock has been achieved Depending on the model in use not all 8 bits may be used For the precise meaning of the bits in this field refer to the table below describing differences between models for this design Sticky loss of lock training flags Each bit of this field returns 1 if the corresponding DCM DLL or PLL lost lock Note that unused bits of this field because there is no corresponding DCM DLL or PLL will always return 1 Reserved Status register MLOCK field STATUS local bus address 0x10 This table describes the STATUS MLOCK field for each supported model ADM XRC Bits Mnemonic Type 8 BANKO1 RO 9 BANK23 RO 15 10 RO MBZ ADM XRC P 111 Function When 1 indicates that the DLL that deskews the SSRAM clocks for memory banks 0 and 1 is locked When 1 indicates that the DLL that deskews the SSRAM clocks for memory banks 2 and 3 is locked Reserved ADM XRC SDK 4 9 3 User Guide Win32 Memory Bits Mnemonic Type 8 1 23 RO 15 9 RO MBZ ADM XRC II Lite Bits Mnemonic Type 8 MCLKX2 RO 9 BANKO1 RO 10 BANK23 RO 15 11 RO MBZ ADM XRC II Bits Mnemonic Type 8 MCLKX2 RO 9 BANKO1 RO 10 BANK23 RO 15 11 RO MBZ ADM XPL Bits Mnemonic Type 8 MEMCLK RO 9 BANKO RO 15 10 RO MBZ ADM XP Bits Mnemonic Type 8 MEMCLK RO 15 9
380. lowthrough mode When this field is 1 the memory port expects the ZBT SSRAM to be operating in pipelined mode 31 1 MBZ Reserved DDR II SSRAM Bits Mnemonic Type Function 0 BLEN R W When this field is 0 the memory port expects the DDR II SSRAM device to be a burst length 2 device When this field is 1 the memory port expects the DDR II SSRAM device to be a burst length 2 or 4 device 1 MBZ Reserved 134 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 2 DLLOFF RAN When this field is 0 the memory port enables the DLL delay locked loop within the DDR II SDRAM device this is the normal mode of operation When this field is 1 the memory port disables the DLL not recommended 31 3 MBZ Reserved DDR SDRAM Bits Mnemonic Type Function 0 REG R W When this field is 0 the memory port expects the DDR SDRAM to be unregistered When this field is 1 the memory port expects the DDR SDRAM to be registered 1 MBZ Reserved for implementing X4 DDR SDRAM device support must be zero in this release of the SDK 3 2 ROWS R W This field specifies the number of row address bits in the DDR SDRAM devices 0x0 gt 12 bits 0x1 gt 13 bits 0 2 gt 14 bits 0x3 gt 15 bits 5 4 COLS R W This field specifies the number of column address bits in the DDR SDRAM devices The number of column address bits depends on this field and also the ROWS field as follows 0x0 gt rows 4 0x1 gt rows 3 0x2 gt rows 2
381. ly Demand mode DMA write LBTERM breaks up bursts Demand mode DMA read LDREQ kept asserted In this example LDREQ n is kept asserted 245 ADM XRC SDK 4 9 3 User Guide Win32 Demand mode ust OX Ce m Signal is driven LA 10 by local bus bridge Signal is driven b LBE C o 2 B3 BEA FPGA LWRITE NNNM Es Y 3 Suggested turnaround LBLAST LREAD Yi b Ff KT LBTERM ty t LD DO f D1 LDREG n LDACK3 n demand node DMA read bursts LDREQ kept asserted Note 1 As long as LDREQ n kept asserted DMA engine n continues to generate bursts on the local bus Demand mode DMA read LDREQ deasserted to pause transfer In this example LDREQ n is deasserted mid burst in order to pause the DMA transfer 246 ADM XRC SDK 4 9 3 User Guide Win32 Demand mode LADS t Key m Signalis driven LA by local bus bridge m Signal is driven by LBE C Bo BE 2 BES FPGA LWRITE QQ NIY 2 Sugested turnaround LBLAST LREADY t LBTERM t LD DO D1 j D2 D3 j D4 j DS 1 D i D7 j LDREG LDACK n f demand 4node DMA read LDRE Gt deassertedto pause DMA Note 1 This assumes that the assertion of LBLAST was caused by deassertion of LDREQ n not because the DMA engine temporarily filled its FIFO 2 DMA engine n is paused at the end of the burst It will not
382. m do do dll xrc4lx do ADM XRC 4FX vsim do do dll xrc4fx do ADPE XRC 4FX vsim do do dll xrce4fx do ADM XRC 5LX vsim do do dll xrc5 do ADM XRC 5T1 vsim do do dll xrc5 do ADM XRC 5T2 vsim do do dll xrc5 do ADM XRC 5T2 ADV 98 ADM XRC SDK 4 9 3 User Guide Win32 FrontlO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data FrontlO sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga vhdl frontio Synopsis The FrontlO FPGA design simply outputs a walking 1 bit on the front panel I O pins FPGA Space Usage 99 ADM XRC SDK 4 9 3 User Guide Win32 FrontIO The FrontlO design does not have a local bus interface thus there are no registers defined the FPGA space Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with frontio xrc v scr frontio xrc v prj frontio xrc ucf Virtex ADM XRC with frontio xrc ve scr frontio xrc ve prj frontio xrc ucf Virtex E ADM XRC II Lite fron
383. m request bus Declaration Synopsis Description Declaration procedure plxsim request bus request in boolean signal bus in gt in locbus in t signal bus out out locbus out t Synopsis Performs the local bus arbitration protocol either requesting or relinquishing the bus Description This procedure manipulates the bus in and bus out signals to perform the local bus arbitration protocol via HOLD and HOLDA relinquishing or requesting the local bus according to the request parameter The request parameter should be e true to request access to the local bus e false to relinquish access to the local bus Once the bus has been requested relinquished the procedure returns 392 ADM XRC SDK 4 9 3 User Guide Win32 wait cycles ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim wait cycles Declaration Synopsis Description Declaration procedure plxsim wait cycles n sow natural Signal bus in in locbus in t Synopsis Waits for the specified number of local bus clock cycles Description Call this procedure to wait for a number of local bus clock cycles The parameter n specifies the number of cycles 393 ADM XRC SDK 4 9 3 User Guide Win32 plxsim wait demand ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim wait demand Declaration Synopsis Description
384. m the FIFO The local bus address is ignored during these demand mode DMA transfers In other words the FIFO is visible over the entire FPGA space during demand mode DMA transfers There are registers that reside in the FPGA direct slave space These registers must be written by the host with a DMA transfer count that matches the size of the DMA transfer being performed prior to the host starting the DMA transfer Note that these registers cannot be inadvertantly overwritten by demand mode DMA transfers as the design qualifies FPGA register accesses using LDACK 1 0 Inbound count register ICOUNT local bus address 0x0 Bits Mnemonic Type Function 1 0 MBZ 31 2 N WO Inbound DMA transfer count in 32 bit words The inbound count register ICOUNT specifies how many words will be transferred in the next DMA transfer in channel 0 in order to transfer data into the FPGA s FIFO When ICOUNT N is zero the FPGA will not assert LDREQZ 0 The FPGA decrements ICOUNT N whenever a word of data is transferred on DMA channel 0 Outbound count register OCOUNT local bus address 0x4 Bits Mnemonic Type Function 1 0 MBZ 31 2 N WO Outbound DMA transfer count in 32 bit words The outbound count register OCOUNT specifies how many words will be transferred in the next DMA transfer in channel 1 in order to transfer data into the FPGA s FIFO When OCOUNT N is zero the FPGA will not assert LDREQ 1 The FPGA decrements OCOUNT N whenever a word of data is
385. main If for a custom application the user app logic must run in a different clock domain techniques such as asynchronous FIFOs and handshaking can be used to decouple the custom user app logic from the memory clock domain A facility for the local bus interface to communicate with the user app module and vice versa is provided by the three signals reg in reg wr and reg out Within the local bus address space there is provision for 64 32 bit registers totalling 256 bytes of registers When the CPU writes to a USER register in the range local bus addresses 0x100 to Ox1FF the write is reflected in the values of reg in and reg wr For example if the CPU writes a 16 bit value to the address 0x13e the 16 bit value is reflected in reg in 31 16 while bits 62 and 63 only of reg wr pulse asserted for exactly one memory user clock cycle When such an event occurs the user app module can at its discretion elect to store the value on reg in somewhere The user app module can drive the reg out vector which is 256 bytes in size with arbitrary status information This status information is visible in the USER registers when the CPU reads local bus addresses 0x100 to Ox1FF Note that synchronizing logic in the reg sync module results in a round trip delay of approximately 12 local bus clock cycles whenever some information must be communicated between the local bus interface and the user app module Hence if the CPU writes something to a USER reg
386. may be tied to logic 0 if not required Sr in Sychronous reset Asserting this signal returns the module to its default state so that it will begin the training sequence when sr is deasserted This port may be tied to logic 0 if not required 347 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram training v2 tstcomp tstdo tstdone tstok trained Notes out Training complete to memory port This signal should be connected directly to the tstcomp ports of one or more instances of ddr2sram port v2 and notifies those ports that training is complete and normal operation should begin out Do readback experiment This signal should be connected directly to the tstdo ports of one or more instances of ddr2sram port v2 and instructs those ports to perform a readback experiment as part of the training sequence in Done readback experiment This signal is a vector where each bit of the vector should be connected directly to the tstdone port of an instance of ddr2sram port v2 The ddr2sram port v2 instance pulses this signal when it has completed a readback experiment as part of the training sequence in Readback experiment successful This signal is a vector where each bit of the vector should be connected directly to the tstok port of an instance of ddr2sram port v2 The ddr2sram port v2 instance asserts this signal qualified by the corresponding bit of the tstdone vector when a readback experiment is completed without er
387. memory bank between two clients For models with ZBT memory generation of deskewed copies of the local bus clock LCLK that are driven off chip to the ZBT SSRAMs using DLLs Virtex E EM or Virtex ll IIPro Virtex 4 and Virtex 5 This technique is used to ensure that ZBT SSRAM devices and the logic within the FPGA operate from clocks that are both phase and frequency matched This design currently supports 15 models in Alpha Data s range of reconfigurable computing cards which use a total of five different types of memory Flowthrough ZBT SSRAM on the ADM XRC and ADM XRC P Pipelined ZBT SSRAM on the ADM XRC II Lite ADM XRC Il ADM XPL ADM XRC 4LX ADM XRC 4SX and ADM XRC 5TZ DDR SDRAM on the ADM XPL and ADM XP DDR II SSRAM on the ADM XP ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV and ADM XRC 5T DA1 DDR II SDRAM on the ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV and ADM XRC 5T DA1 FPGA Space Usage The FPGA space is divided into two regions e A 2MB register region beginning at local bus address 0x0 The registers within the FPGA are accessible via this region e A 2MB memory access window beginning at local bus address 0x200000 The currently selected page of the currently selected bank is accessible via this region The following registers exist in the 2MB register region which begins at local bus address 0 0 Bank register BANK local bus address 0 0 B
388. mif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif zbtsram zbtsram port vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the port logical address a 4 d width natural Width in bits of the port data in and out d and q 3 respectively pinout zbtsram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants ra width natural Width in bits of the memory device address bus ra 1 rc width natural Width in bits of the memory device control bus rc 2 rd width natural Width in bits of the memory device data bus rd 3 tag width natural Width in bits of the tag in and out tag and qtag respectively Notes 1 The ra width parameter is a property of the printed circuit board indicating how many wires are physically present rather than indicating how many of the ra lines are used by a particular ZBT SSRAM device 2 The memory device control bus rc is composed of various fields in this memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates the fields that comprise the rc bus VWidth ofthis field is
389. mory devices is zero extended so that its width is d width before being returned on q o d width 2 rd width is the optimal usage case o If d width lt 2 rd width then the memory port zero extends d internally so that its width is 2 rd width The a width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a DDR II SSRAM bank Hence the required value of a width depends on what memory devices are actually in use As an example consider a DDR II SSRAM device with 20 address bits Since logical memory locations are two times as wide as the physical memory locations one must subtract 1 giving a value of 19 for the minimum value of a width When a width is larger than actually required the top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 devices are in use Signals The signals of this interface to and from the user application are as follows Signal Type Function Note a in Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as a linear array of words of width d width this address is a logical address rather than anything resembling what one might see on the ra bus be in Byte enables to memo
390. mple that an inadvertant attempt is made to run them on an ADM XRC II Lite card ADMXRC functions by group ADMXRC structures ADMXRC datatypes 504 ADM XRC SDK 4 9 3 User Guide Win32 Multithreading issues ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Multithreading issues ADMXRC interface The ADM XRC SDK is designed to be thread safe The ADMXRC interface functions can be divided into two groups e Functions that cannot block the calling thread and e Functions that are capable of blocking the calling thread The latter group of functions those which are capable of blocking the calling thread require a pointer to a Win32 event PHANDLE to be passed Unless great care is taken to ensure that no two threads use the same event at the same time this event must be private to each thread using the API The requirement for a per thread event stems from the need to specify an event in overlapped DeviceloControl calls see Win32 API The Microsoft Platform SDK documentation states that events used in an overlapped DeviceloControl call must be manual reset events A code fragment for creating a suitable event for use with the blocking ADM XRC API calls is Create a manual reset Win32 event vent CreateEvent NULL TRUE FALSE NULL if event NULL Error handling A pointer to the event event can then be passed to the blocking API functions The API also allows
391. n 538 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC SetupDMA The application buffer is locked down made non swappable so that the system cannot swap any page of physical memory spanned by the buffer out to disk Locking down a very large region of memory under low memory conditions should be avoided There are a limited number of DMA descriptors and each successful call to ADMXRC SetupDMA commits a descriptor until freed by a matching call to ADMXRC_UnsetupDMA 539 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC StatusToString ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC StatusToString Prototype ADMXRC STATUS ADMXRC StatusToString ADMXRC STATUS Status char Buffer unsigned long Max Arguments Argument Type Purpose Status In Error code Buffer In Buffer to receive textual description Max In The size of Buffer in bytes Return value Value Meaning ADMXRC SUCCESS A description of the error was successfully returned ADMXRC NULL POINTER Buffer was NULL ADMXRC INVALID PARAMETER Status was not a valid error code Description This function returns in a textual description of an error in Buffer At most Max characters including the NULL terminator are written to Buffer 540 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC SyncDirectMaster ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC SyncDirectMaster Prototype ADMXRC STATUS
392. n typedef HANDLE ADMXRC2 HANDLE e Description An ADMXRC2_HANDLE is a handle to a card in a system Most API functions require a parameter of type ADMXRC2_HANDLE in order to identify the card on which the operation is to be performed The ADMXRC2_OpenCard and ADMXRC2_CloseCard functions open and close card handles 496 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ERROR HANDLER ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 ERROR HANDLER Declaration typedef void ADMXRC2 ERROR HANDLER const char FnName ADMXRC2 STATUS Status Description An ADMXRC2 ERROR HANDLER function is an application defined error handler routine called when an API function fails for some reason The routine must be installed or uninstalled using ADMXRC2 InstallErrorHandler 497 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 IMAGE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 IMAGE Declaration typedef void ADMXRC2 IMAGE e Description An ADMXRC2_IMAGE holds data that can be written to an FPGA s SelectMap port ADMXRC2 LoadBitstream and ADMXRC2_UnloadBitstream can be used to load SelectMap data from a file into an ADMXRC2 IMAGE variable As ADMXRC2_LoadBitstream allocates memory to hold the data it is the application s responsibility to free the memory when no longer required using ADMXRC2 UnloadBitstream A variable of type ADMXRC2 IMAGE ca
393. n all sideband inputs must be static while the memory port is not idle The signals of this interface to and from the memory device s are as follows Signal 320 Type Function ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port ra in Memory device address bus This bus carries address information to from the memory port to the memory device s For devices with a nontrivial addressing scheme this address may be composed of various fields These fields are bundled together into the ra bus so that for the most part the user application need not care what they are Refer to note 1 for the mapping of the ra bus to device pins rc inout Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together into the rc bus so that for the most part the user application need not care what they are Refer to note 2 for the mapping of the rc bus to device pins rd inout Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via ce four words are transferred on rd which determines the relationship between the rd_width and d_width parameters Refer to note 3 for details Row column address selection The row and col sideband inputs together determine the number address bits used for row and column addresses as in the following table row 1 0
394. n a particular element of be results in a 0 in the corresponding bit of LBE The length of be must be the same as the length of data The data parameter specifies the data to be written on local bus For a nonmultiplexed address data bus the data is output on the LD signal whereas for a multiplexed address data bus the data is output on the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes written on the local bus 396 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write const ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim write const Declaration Synopsis Description Declaration procedure plxsim write const order GUB natural multiburst in boolean address gt in std logic vector be in byte enable t data 25 suh byte vector t nxfered out natural signal bus in in locbus in t signal bus out out locbus out t Synopsis Performs a basic local bus write transfer with constant local bus address Description This procedure uses the bus in and bus out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim write const FPGA design under tes t aut Stimulus rocess ocbus in 1 Local bus LOCAL agent BUS ike J The order parameter specifies the width of the lo
395. n application running on the host via the local bus e Memory interface package VHDL for using the onboard memory on a reconfigurable computing card e PLXSIM simulation package VHDL for building a testbench for an FPGA design s local bus interface 264 ADM XRC SDK 4 9 3 User Guide Win32 Local bus interface package VHDL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The localbus package Overview of this package Components Overview The localbus package consists of a number of components designed to simplify the task of adding a local bus interface to an FPGA design A local bus interface enables a software application running on the host to communicate and exchange data with the FPGA design using API functions such as ADMXRC2 DoDMA and ADMXRC2 Read Components Name Function plxddsm Demand mode DMA state machine plxdssm Direct slave state machine 265 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm deprecated ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The plxddsm component Overview HDL source code Signals Usage Overview NOTE this component has been superseded by the plxddsm2 component The plxddsm component is part of the localbus package and provides the control mechanism for a demand mode DMA channel in a local bus interface within an FPGA design This component cannot be used in isolation it cooperates with the plxdssm component in order
396. n be found in the projnav directory as follows Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II 104 itest xrc4sx v4sx prj itest xrc4fx v4fx prj itest xrc4fx v4fx prj itest xrce4fx v4fx prj itest xrce4fx v4fx prj itest xrcblx v5lx prj itest xrcbt1 vbfxt prj itest xrcbt1 vblxt prj itest xrcbt1 v5sxt prj itest xrcbt2 vbfxt prj itest xrcbt2 vblxt prj itest xrcbt2 v5sxt prj itest xrcbtz v5bfxt prj itest xrc5tz v5Ixt prj itest xrc5tz v5sxt prj itest xrcbtda1 vb5fxt prj itest xrc5tda1 v5Ixt prj itest xrc5tda1 v5sxt prj Project Navigator project file projnav xrc lt device gt projnav xrcp lt device gt projnav xrc2l lt device gt projnav xrc2 lt device gt projnav xpl lt device gt projnav xp lt device gt projnav wrc2 lt device gt projnav drc2 lt device gt itest xrc4sx ucf itest xrcAfx Avfx100 ucf itest xrcAfx Avfx140 ucf itest xrce4fx 4vfx100 ucf itest xrce4fx 4vfx140 ucf itest xrcblx ucf itest xrcbt1 5vfxt ucf itest xrcbt1 ucf itest xrcbt1 ucf itest xrcbt2 5vfxt ucf itest xrcbt2 ucf itest xrcbt2 ucf itest xrcbtz 5vfxt ucf itest xrcbtz ucf itest xrcbtz ucf itest xrcbtda1 5vfxt ucf itest xrcbtda1 ucf itest xrcbtda1 ucf ADM XRC SDK 4 9 3 User Guide Win32 ITest ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ A
397. n be used directly with ADMXRC2 ConfigureFromBuffer and ADMXRC2 ConfigureFromBufferDMA 498 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 IOWIDTH ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 IOWIDTH Declaration typedef enum ADMXRC2 IOWIDTH ADMXRC2 IOWIDTH 8 ADMXRC2 IOWIDTH 16 ADMXRC2 IOWIDTH 32 ADMXRC2 IOWIDTH 64 ADMXRC2 IOWIDTH ll WN rR Description The ADMXRC2 IOWIDTH enumerated type determines the width of a programmed I O or DMA transfer in the following functions e ADMXRC2 BuildDMAModeWord e ADMXRC2 Read e ADMXRC2 Write When used with ADMXRC2 Read ADMXRC2 Write the ADMXRC2 IOWIDTH type specifies the size of each item of data read or written on the local bus and may be 8 16 or 32 For performance reasons use ADMXRC2 IOWIDTH 32 wherever possible When used with ADMXRC2 BuildDMAModeWord the ADMXRC2 IOWIDTH type specifies the width of the DMA transfer on the local bus The following table shows what values are permissible for DMA transfers Model 8 16 32 64 ADM XRC yes yes yes no ADM XRC P yes yes yes no ADM XRC II Lite yes yes yes no ADM XRC II yes yes yes no ADM XPL no no yes yes ADM XP no no yes yes ADP WRC II yes yes yes no ADP DRC II yes yes yes no ADP XPI no no yes yes ADM XRC 4LX yes yes yes no ADM XRC 4SX yes yes yes no ADM XRC 4FX no no yes yes ADPE XRC 4FX no no yes yes ADM XRC 5LX no no yes yes 499 ADM XR
398. n was obtained successfully ADMXRC2 INVALID HANDLE Card is not a valid handle to a card Description This function returns version information about the API library and driver A pointer to an ADMXRC2 VERSION INFO structure should be passed in the Info parameter 446 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2_InstallErrorHandler ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 InstallErrorHandler Prototype ADMXRC2 STATUS ADMXRC2 InstallErrorHandler ADMXRC2 ERROR HANDLER Routine Arguments Argument Type Purpose Routine In The error handler routine to install Return value Value Meaning ADMXRC2 SUCCESS The error handler routine was successfully installed Description This function is used to install a user defined error handler function that will be called whenever the ADM XRC function must return an error condition The error handler function should be of type ADMXRC2 ERROR HANDLER void MyErrorHandler const char FunctionName ADMXRC2 STATUS Code If Routine is non NULL it must point to a function of the same type as MyErrorHandler above If Routine is NULL any error handler function currently installed will be uninstalled A failed call the ADMXRC2 InstallErrorHandler function does not result in in any currently installed error handler function being called The error handler function is always called just before the API function generating the error returns
399. n written to memory for detecting data bits stuck at 0 1 or shorted to other signals The pattern is designed to result in all of the data lines for a given bank toggling at the maximum possible frequency during a burst of memory accesses a fF CO Inm Own address pattern written to memory for detecting address bits stuck at 0 1 or shorted to other signals Bit reversed own address pattern written to memory for detecting address bits stuck at 0 1 or shorted to other signals Random data written to memory for detecting pattern sensitive failures DMA throughput between each on board memory bank and CPU memory is measured the two directions i CPU memory to on board memory and ii on board memory to CPU memory The 64 option causes the application to operate the local bus in 64 bit mode This is valid only for models that support a 64 bit local bus Using the local bus in 64 bit mode increases the available bandwidth for data transfer generally resulting in higher measured throughput in phase 5 above A subset of the memory banks on a card can be tested by passing a bitmask of banks to test via the banks option For 64 ADM XRC SDK 4 9 3 User Guide Win32 Memory example banks 0xD would specify that only banks 0 2 and 3 should be tested The local bus clock frequency used for the memory test can be specified on the command line using the Iclk option For example Iclk 45 specifies a local bus clock frequency
400. natural Width in bits of the memory device control bus rc 2 natural Width in bits of the memory device data bus rd 3 natural Width in bits of the tag in and out tag and qtag respectively The ra width parameter is a property of the printed circuit board indicating how many wires are physically present rather than indicating how many of the ra lines are used by a particular DDR II SSRAM device The memory device control bus rc is composed of various fields in this memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates the fields that comprise the rc bus Width ofthis field is rd width 8 r TAPER UNES SN porreces ca ce c K wf Present if pinout has cistrue Present if pinout has cq istrue The order of the fields within rc is always the same but some models may lack certain fields The rd width parameter is the number of physical DQ wires making up the data bus of the DDR II SSRAM bank This memory port transfers two words of data on the DQ wires for each command entered via the ce signal Accordingly the d width parameter which is the width of d and q is typically specified by the user application as being two times rd width However other values can be passed for d width o If d width gt 2 rd width then the memory port simply truncates d internally so that its width is 2 rd width Data read from the me
401. nd component Synopsis Non synthesizable testbench component that drives the local bus 414 ADM XRC SDK 4 9 3 User Guide Win32 locbus agent nonmux Description totom stimulus process tco buzsed ico p2p la lad blast 1 Ibtenm _ Id Ireadwy bite holda Ihald lochus agent nanmux ta fram local bus ta fram arbiter This local bus agent component can be instantiated in a testbench to drive a local bus that has 32 bit nonmultiplexed address and data busses Each local bus agent is normally associated with a stimulus process In the figure above the signals on the right comprise the local bus while the signals on the left are driven by the stimulus process The generics should be mapped as follows Generic tco bussed tco p2p Map to A value of type time that represents the desired local bus clock to output delay for the bussed signals such as LADS This parameter has a suitable default value so it need not be specified A value of type time that represents the desired local bus clock to output delay for point to point signals such as LHOLD This parameter has a suitable default value So it need not be specified The first group of ports must be mapped to signals driven or used by the stimulus process associated with the local bus agent Port bus in bus out Map to A signal of type locbus in t used by the stimulus process A signal of type lo
402. nd implements an interface to a bank of DDR SDRAM memory This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure ADM XRC SDK User Guide Common Memory Ports a a width 1 0 tag tag_ wrth 1 0 to fram be d width 8 1 Of rala width 1 0 to from user d d idth 1 0 rc rc width 1 0 memory application regga rd rd width 1 0 devi cerz 4 1 0 ca 1 0 bank 1 t pbank 1 0 gid width 1 0 wrath 1 0 valid ready trained ddrsdram port HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl chipscope src ilap pkg vhd fpga vhdl chipscope src ilacombo sim vhd fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif cmd_fifo vhd fpga vhdl common memif ddrsdram ddrsdram clkfw vhd fpga vhdl common memif ddrsdram ddrsdram ctrl vhd fpga vhdl common memif ddrsdram ddrsdram data vhd fpga vhdl common memif ddrsdram ddrsdram data dqs vhd fpga vhdl common memif ddrsdram ddrsdram_dqs vhd ADM XRC SDK User Guide Common Memory Ports fpga vhdl common memif ddrsdram ddrsdram dm vhd fpga vhdl common memif ddrsdram ddrsdram init vhd fp
403. ndow at end of phase sweep window_stop 180 window_length window stop window start if window length some minimum window and window length best window This is the new best window best window window length best cedge cedg best phase window stop window start 2 end if end if end loop Training completed tstcomp 1 if best window gt 0 then trained 1 Training completed and successful set phase of clkcO to best phase cedge best cedg end if HDL source code SO Set operating parameters Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif_pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd fpga vhdl common memif ddr2sram v2 ddr2sram training v2 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead 346 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram training v2 Parameters Name Type Function Note num port natural This is the width in bits of the tstdone and tstok ports 1 Notes 1 A single instance of ddr2sram training v2 can be used to train more than one instance of ddr2sram port v2 provided that the banks of memory are reasonably well matched When ins
404. neric tco_bussed in time 5 ns tco_p2p in time 5 ns port lreset 1 std logic lclk in std logic lad inout std logic vector 31 downto 0 lads 1 inout std logic lbe 1 inout std logic vector 3 downto 0 lblast inout std logic lbterm 1 inout std logic lready 1 inout std logic lwrite inout std logic lhold out std logic lholda in std logic bus in out locbus in t bus out i oim locbus out t end component Synopsis Non synthesizable testbench component that drives the local bus 408 ADM XRC SDK 4 9 3 User Guide Win32 locbus agent mux32 Description to from Stimulus process tco bussed ico p2p clk lad lads I lblast_ Ibtem I ready ite holda Ihald lochus agent mux32z to from local bus totom arbiter This local bus agent component can be instantiated in a testbench to drive a local bus that has a 32 bit multiplexed address data bus Each local bus agent is normally associated with a stimulus process In the figure above the signals on the right comprise the local bus while the signals on the left are driven by the stimulus process The generics should be mapped as follows Generic tco_bussed tco_p2p Map to A value of type time that represents the desired local bus clock to output delay for the bussed signals such as LADS This parameter has a suitable default value so it need not be specified
405. nfavored clients 5 The ready delay parameter specifies the timing relationship between a client s readyi signal and its cei signal ready delay must be at least 0 and no greater than 4 The following figures illustrate this relationship 0 access granted here by arbiter access lost here readyO f earliest possible assertion latest possible deassertion of ced of ce Relationship between readyO and ce0 when ready delay 0 FA FAFAFAFTATATAFATATATAFAFATA 0 access granted here by arbiter access lost here readyO earliest possible assertion latest possible deassertion of of cel Relationship between readyO and when ready delay 1 309 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 4 req access granted here by arbiter access lost here readyO i earliest possible assertion latest possible deassertion of ce of ce Relationship between readyO and ce0 when ready delay 2 6 If the registered parameter is false the memory port output signals ce w etc are generated combinatorially from the client port input signals 0 w0 ce1 w1 etc If the registered parameter is true the memory port output signals ce w etc are registered before being output This adds one cycle of latency but is recommended for ease of timing closure This parameter has no effect on the timing relationship between r
406. nfrastructure for training one or more instances of ddrsdram port v2 This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure 323 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 a a width 1 0 tag tag_vwidth 1 0 be d width 8 1 Of d d width 1 0 regd ra ra width 1 0 torom x4 refre idth 1 0 memory j devices application 0 1 0 3 col 7 0 bank 1 U pbank 1 0 clkc clkc18 cedeae 2 n wrath 1 0 valid ready tstdone tstok dcrsdram port v2 HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common memif memif pkg vhd fpga vhdl common memif memif int pkg vhd fpga vhdl common memif memif def synth vhd OR fpga vhdl common memif memif def sim vhd 324 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 fpga vhdl common memif cmd fifo vhd fpga vhdl common memif ddrsdram v2 ddrsdram clkfw vhd fpga vhdl common memit ddrsdram v2 ddrsdram ctrl vhd fpga vhdl common memif ddrsdram v2 ddrsdram data vhd fpga vhdl common memit ddrsdram v2 ddrsdram dqs vhd fpga vhdl common memif ddrsdram v2 ddrsdram dm vhd fpga vhdl common memif ddrsdram v2 ddrsdram init vhd fpga vhdl common memit ddrsdram v2 ddrsdram port
407. ng e i meaning initialize the user space buffer to known data e q meaning quit e r meaning command the FPGA to read from a specified location in the user buffer e S meaning show the contents of the user space buffer e w meaning command the FPGA to write specified data to specified a location in the user space buffer FPGA Design The Master sample application makes use of the Master sample FPGA design Verilog VHDL 62 ADM XRC SDK 4 9 3 User Guide Win32 Memory ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data MEMORY sample application Model support Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview Supported The Memory sample application is a host driven memory test that verifies the memories on a reconfigurable computing card Syntax memory options Options Option Type banks hexadecimal integer card base 10 integer index base 10 integer Tiik real number 63 Meaning Bitmask of banks to test default OxFFFFFFFF ID of card to open Index of card to open Local bus clock frequency to use in MHz default depends upon type of card ADM XRC SDK 4 9 3 User Guide Win32 Memory mask Hexadecimal integer mclk real number cis TOSTE el 227 TES REIRA
408. nition PLXDSSM state diagram PLXDSSM timing diagrams This section describes the PLXDSSM state machine that is used in most of the sample FPGA designs It is used as a building block in the implementation of a local bus interface that responds to Direct Slave transfers PLXDSSM module definition PLXDSSM can be visualized as the following module ready stop idle to from application decode Local Bus ready oe 1 us transfer PLXDSSM The upper section of the module shows general signals such as clock asynchronous reset and synchronous reset either or both types of reset may be used Below those on the left hand section of the module are the local bus signals possibly qualified in some manner which is discussed below The signals on the right hand are signals to and from the application logic The functions of the signals are as follows Signal Direction Description clk IN This signal is the local bus clock rst IN Asynchronous reset if used should be derived from the local bus reset signal LRESET sr IN Synchronous reset if used should be derived from the local bus reset signal LRESET qlads IN This signal must be a suitably qualified active high version of the local bus address strobe LADS Typically obtained from a combinatorial function such as qlads lt LADS and LA 23 and FHOLDA Iblast IN This signal should simply be an active high version of the local bus LBLAST signal Iwrite IN This signal should
409. nk This memory port transfers two words of data on the DQ wires for each command entered via the ce signal Accordingly the d_width parameter which is the width of d and q is typically specified by the user application as being twice rd_width However other values can be passed for d width o If d width gt 2 rd width then the memory port simply truncates d internally so that its width is 2 rd width Data read from the memory devices is zero extended so that its width is d width before being returned on q o d width 2 rd width is the optimal usage case o If d width lt 2 rd width then the memory port zero extends d internally so that its width is 2 rd width The a width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a DDR SDRAM bank Hence the required value of a width depends on what memory devices are actually in use As an example consider two physical banks of DDR SDRAM devices that use 13 row bits 10 column bits and 2 internal bank address bits The number of address bits is 13 row address bits 10 column address bits 2 internal bank address bits 1 2 physical banks CS pins 26 We must now subtract 1 because logical memory locations are twice as wide as the physical memory locations due to transferring two words on the DQ pins for every command entered on ce Hence a width for this confi
410. nk and functions as in the generic memory interface For example q 2 qtag 2 and valid 2 are part of the interface to memory bank 2 Because each slice is independent of the other slices some or all of the memory banks may be operated simultaneously if desired e Because the memory banks are shared with the local bus interface user code must drive the req vector Asserting a particular bit of this vector indicates that the user app module wishes to access the corresponding memory bank For example assering req 3 causes the arbiter for memory bank 3 within the memory banks module to eventually assert ready 3 Once the user app module sees ready 3 asserted it may assert the ce 3 signal in order to access memory bank 3 e The chip driven memory test logic in the user app module as shipped in this SDK runs entirely within the memory clock domain If for a custom application the user app logic must run in a different clock domain techniques such as asynchronous FIFOs and handshaking can be used to decouple the custom user app logic from the memory clock domain A facility for the local bus interface to communicate with the user app module and vice versa is provided by the three signals reg in reg wr and reg out Within the local bus address space there is provision for 64 32 bit registers totalling 256 bytes of registers When the CPU writes to a USER register in the range local bus addresses 0x100 to Ox1FF the write is reflected in the
411. nous reset is not required The interface presented to clients by the arbiter_2 module is as follows Signal Type Function Note a0 in Client logical address al A client must place a valid address on ai when it asserts cei bed in Client byte enables to memory be1 A client must place valid byte enables on bei whenever a write command is entered cei and wi both asserted A logic 1 ina given bit of be means that the corresponding byte within bei will be written to memory while a zero means that the corresponding byte will not be written to memory ceo in Client command entry A client asserts this signal to enter a new read or write command into the memory port When asserted ai and wi must be valid When asserted along with wi tagi must also be valid A client must observe the rules for assertion of cei with respect to readyi as illustrated by note 5 above Other than that there are no restrictions on how few or how many clock cycles cej can remain asserted It can be pulsed for single clk cycles or asserted for many clk cycles readyi permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but the performance of certain types of memory for example DDR SDRAM benefits from locality of access do in Client data to memory di A client must place valid data on di whenever a write command is entered cei and wi both asserted q0 out Client
412. now whether or not constant local address mode is in use since the address is presented on LAD only in the address phase However a designer can simply define some conventions that are observed by both the FPGA design and the application software on the host for example e particular local bus address or address range shall always be accessed in constant address mode by the application software running on the host Then in order to determine whether or not a given local bus burst uses a constant address the FPGA need merely decode the address e If using demand mode DMA with a FIFO demand mode shall always be used in constant address mode ie the assertion of LDACK during a local bus burst implies a constant local address Then in order to determine whether or not a given local bus burst uses a constant address the FPGA need merely check whether or not LDACK is asserted at the beginning of a burst This can be implemented selectively on a per DMA channel basis since there is one LDREQ LDACK pair per DMA channel Such conventions are equally applicable to a local bus with nonmultiplexed data Although the local bus address is provided on the LA signal throughout a burst using it within the FPGA is discouraged because it may be difficult to meet timing constraints at higher frequencies of the local bus clock A far better method is to capture the local bus address internally into a loadable counter on the assertion of LADS
413. ns Ibterm ce I o lready pixdssm Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common localbus localbus pkg vhd fpga vhdl common localbus plxdssm vhd Signals The signals of this interface to and from the user application are as follows Signal Type clk in decode out eld_oe out 275 Function Note Local bus clock This port must be driven by the clock that drives the local bus interface of the FPGA design Address decoding pulse This output pulses for exactly one clock cycle in the cycle following the assertion of qlads Typically the address presented on the local bus by the current local bus master is captured in a register whose contents are valid in the cycle following the glads pulse The FPGA can use the decode pulse to as an indication that the captured local bus address is valid so that it may perform further decoding of the address Early LD LAD output enable This output shows the same waveform as Id oe 1 but is active high and one cycle early compared to ld oe ADM XRC SDK 4 9 3 User Guide Win32 plxdssm idle out Iblast in lbterm in Ibterm o out Ipterm oe 1 out ld oe out out out Iwrite in qlads in ready in rst in sr in 276 Interface idle This status output indicates whether or not the plxdssm module is currently han
414. nsigned long Offset unsigned long Length ADMXRC2 BUFFERMAP Map Arguments Argument Type Purpose Card In Handle of card that the bitstream targets Buffer In Specifies application buffer to map Offset In Where to begin mapping within the application buffer Length In Size of region of application buffer to map Map In Out Structure to receive map information Return value Value Meaning ADMXRC2 SUCCESS The bitstream file was successfully loaded ADMXRC2 INVALID HANDLE The Card parameter did not refer to an open card ADMXRC2 INVALID DMADESC The DMA descriptor representing the application buffer was not valid ADMXRC2 INVALID PARAMETER The Offset or Length parameters were outside the bounds of the application buffer Description This function builds an array of PCI addresses of the pages of memory that comprise a buffer in the application s address space The Card parameter should be the handle of the card that was used to create the DMA descriptor DmaDesc DMA descriptors are obtained via the ADMXRC2 SetupDMA API call The Offset and Length parameters identify a region within the buffer that DmaDesc refers to The Map parameter must point to an ADMXRC2 BUFFERMAP structure If the call to ADMXRC2 MapbDirectMaster is successful the array of page addresses may used by the FPGA in order to 451 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 MapbDirectMaster allow the FPGA to perform direct master access to the user buffer
415. nstallable packages ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Installable packages In order to develop applications for an Alpha Data reconfigurable computing card on a Windows platform the package admxrc sdk win32 4 9 3 should be installed Package Platforms supported admxrc sdk win32 4 9 3 Windows 98 Windows ME Windows NT 4 0 Windows 2000 Windows Windows Server 2003 In order to run applications on an Alpha Data reconfigurable computing card on a Windows platform the appropriate driver package should be installed Package Platforms supported admxrc driver win2k 3 16 Windows 2000 Windows XP x86 Windows XP x86 64 Windows Server 2003 x86 Windows Server 2003 x86 64 admxrc driver winnt4 3 16 Windows NT 4 0 Service Pack 6 It is recommended that the most up to date driver version currently available be installed At the time of writing this is version 3 16 36 ADM XRC SDK 4 9 3 User Guide Win32 Sample applications ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Sample applications A number of sample applications written in C are included with the SDK Some of these use the sample FPGA designs included with the SDK Running the sample applications Rebuilding the sample applications Sample application list 37 ADM XRC SDK 4 9 3 User Guide Win32 Running the sample applications ADM XRC SDK 4 9 3 User Guide Win32 Copyright
416. nstrates use of the DMA engines in demand mode with bursting and 64 bit mode on the local bus A trivial design that walks a 1 bit up the front panel I O pins Sample logic for generating FPGA interrupts Demonstrates how to implement a direct master capability in an FPGA design A trivial design that walks a 1 bit up the rear panel I O pins Demonstrates how to implement host readable registers Demonstrates how to implement host readable registers with 64 bit local bus interface Demonstrates host access to the ZBT SSRAM Demonstrates host access to the ZBT SSRAM with 64 bit local bus interface ADM XRC SDK 4 9 3 User Guide Win32 DDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DDMA sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog ddma Synopsis The DDMA FPGA design demonstrates demand mode DMA with bursting Data is read from an application buffer in host memory and then simply written back to another application buffer unchanged a loopback operation In order to use demand mode DMA the hos
417. nter to a Win32 event handle of type PHANDLE which could be NULL If this pointer is NULL a Win32 event is created on the calling thread s behalf This is not the case in the ADMXRC2 interface The ADMXRC2 functions that can block the calling thread always require a valid manual reset Win32 event handle of type HANDLE to be passed The ADMXRC2 InstallErrorHandler function has been simplified in the interests of API reliability The API no longer treats an installed error handler routine as a critical section It is now the application programmer s responsibility to ensure that problems do not occur if the installed error handler function is called from multiple threads The ADMXRC2 LoadBitstream and ADMXRC2 UnloadBitstream functions replace the ADMXRC FindlmageOffset ADMXRC LoadFpgaFile ADMXRC ReverseBytes and ADMXRC UnloadFpgaFile functions The ADMXRC2 LoadBitstream function loads only the SelectMap data into memory reversing its bit order if necessary instead of requiring the application to make several API calls to prepare the SelectMap data The data loaded by ADMXRC2 LoadBitstream can be sent without modification to the FPGA s SelectMap port The ADMXRC2_OpenCard function can open an instance of any of the following models ADM XRC ADM XRC P ADM XRC II Lite ADM XRC Il ADM XPL ADM XP ADP DRC IIl ADP WRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADM XRC 5LX and ADM XRC 5T1 ADMXRC_OpenCard can open only instances of the ADM
418. nterrupt source 1 is still active At this point the host will be interrupted again and notice that interrupt source 1 is active Interrupt Test register TEST local bus address OxC Bits Mnemonic Type Function 31 0 TEST WO Writing a 1 to a particular bit of this register makes the corresponding interrupt source active The TEST register can be used to test the interrupt handler on the host By writing a 1 to a particular bit position the corresponding interrupt source is set active Count register COUNT local bus address Ox10 Bits Mnemonic Type Function 31 0 NCYCLE RAN This register counts local bus clock LCLK cycles when ISTAT 0 is 1 When ISTAT O0 is 0 it may be written in order to initialize its value The COUNT register can be used to measure interrupt response time It can be initialized to zero when ISTAT 0 is 0 and increments when ISTAT 0 is 1 Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with itest xrc v scr itest xrc v prj itest xrc ucf Virtex ADM XRC with itest xrc ve scr itest xrc ve prj itest xrc ucf Virtex E ADM XRC P with itest xrcp v scr itest xrcp v prj itest xrcp ucf Virtex ADM XRC P with itest xrcp ve scr itest xrcp ve prj itest xrcp ucf Virtex E ADM XRC Il Lite itest xrc2l v2 scr itest xrc2l v2 prj itest xrc2l ucf ADM XRC II itest xrc2 v2 scr
419. number of address bits in a page offset For example in the x86 architecture this member is 12 e The PagesSpanned member is the number of pages of physical memory spanned by the PagesPci array e The BytesSpanned member is the number of bytes of physical memory spanned by the PagesPci array and takes InitOffset into account e The InitOffset member is the offset within the first mapped page of the beginning of the region of the user buffer The following figures illustrate the relationship between the members of the ADMXRC2 BUFFERMAP structure in two possible cases e Here when ADMXRC2 MapbDirectMaster is called the MaxPages member of the ADMXRC2 BUFFERMAP structure passed is greater than or equal to the number of pages spanned by the application buffer 479 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BUFFERMAP Physical memory PagesPci s 1 PageLength PagesPci 1 Application buffer n start Pagesopanned 4 PagesPci 2 BytesSpanned Init Offset 0 e when ADMXRC2 MapbDirectMaster is called the MaxPages of the ADMXRC2 BUFFERMAP structure passed is 2 less than the number of pages spanned by the application buffer 480 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BUFFERMAP Physical memory Application buffer T PageL en ath PagesPci 1 E start Pagesopanned 2 BytesSpanned n Init Offset PagesPci 0 481 ADM
420. nx ISE 7 1i project files for Project Navigator ISE extension are binary files Furthermore filenames are stored as absolute paths regardless of whether or not the filenames were added to the project as relative or absolute paths For this reason project files are in general not portable between users or workstations as different users tend do their work in different locations In this release of the SDK Project Navigator files are not supplied but can be generated after installation by running a script requires ISE tools to be in user s PATH There are several choices for the user when deciding how to run this script 1 Generate Project Navigator files for all sample VHDL and Verilog designs 2 Generate Project Navigator files for all sample VHDL designs 3 Generate Project Navigator files for all sample Verilog designs 4 Generate Project Navigator files for a specific Verilog or VHDL design NOTE The scripts used to generate Project Navigator files are known to be compatible with ISE 10 1i They will not work with any ISE version earlier than 10 1i and are not guaranteed to work correctly with any ISE version later than 10 11 1 Generate Project Navigator files for all sample VHDL and Verilog designs To generate project files for all sample designs in the SDK both VHDL and Verilog start a shell and issue the following commands cd d ADXMRC_SDK4 fpga projnav mkproj Because this process creates hundreds of ISE files
421. o a register in the FPGA The application reads the values back from the FPGA and displays them However the FPGA nibble reverses the values before returning them FPGA Design Normally this application uses the Simple sample FPGA design Verilog VHDL However if the 64 option is specified on the command line the Simple64 sample FPGA design Verilog VHDL is used instead It is important to note that when the 64 bit version is used the application does nothing different apart from configuring the FPGA local bus space to operate in 64 bit mode see ADMXRC2 SetSpaceConfig 74 ADM XRC SDK 4 9 3 User Guide Win32 Sample FPGA designs ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Sample FPGA designs The sample FPGA designs are supplied in Verilog versions and VHDL versions e The Verilog versions are located in the fpga verilog directory relative to the base of the SDK e The VHDL versions are located in the fpga vhdl directory relative to the base of the SDK For simulation the PLXSIM package currently in VHDL only provides primitives that allow a testbench to be rapidly constructed e The VHDL version of the PLXSIM source code is located in the fpga vhdl pIxsim directory relative to the base of the SDK 75 ADM XRC SDK 4 9 3 User Guide Win32 Generating ISE project files ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Generating ISE Project files As of Xili
422. o be implied from the model Model NumClock NumRAMBank NumSpace ADM XRC 2 4 2 ADM XRC P 2 4 2 ADM XRC I Lite 2 4 2 ADM XRC II 2 6 2 ADM XPL 1 2 2 ADP WRC II 2 2 2 ADP DRC II 2 5 2 ADP XPI 1 5 2 ADM XRC 4LX 2 6 2 ADM XRC 4SX 2 4 2 ADM XRC 4FX 2 4 2 ADPE XRC 4FX 2 4 2 ADM XRC 5LX 2 4 2 ADM XRC 5T1 2 3 2 ADM XRC 5T2 2 6 2 483 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 CARD INFO ADM XRC 5T2 ADV 2 ADM XRC 5T DA1 2 484 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SPACE INFO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 SPACE INFO Declaration typedef struct ADMXRC2 SPACE INFO void VirtualBase unsigned long VirtualSize DWORD PhysicalBase DWORD ijocalBase unsigned long LocalSize ADMXRC2 SPACE INFO Description The ADMXRC2 SPACE INFO structure is returned by ADMXRC2 GetSpacelnfo and contains information about a region of local bus space on a card The PhysicalBase member is the address of the region in the address space of the bus on which the card resides For example an ADM XRC card is a PCI Mezzanine Card so this value would represent the PCI address of the beginning of the region The LocalBase member is the address of the region in the local bus address space of the card The LocalSize member is the size in bytes of the FPGA space in the local bus address space of the card The VirtualBase member is the address in the appli
423. o place a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags Training success flag sideband signal 5 When the memory port asserts trained it indicates that training of the memory port was successful When deasserted either training is not yet complete or training was unsuccessful ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port valid Notes out Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid in Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command The delay from deassertion of reset to completion of training trained asserted may be as long as 350ms This is because a large post reset delay is used in order to ensure that the memory port properly initializes the DDR II SDRAM devices that it is controlling after power on For simulation however the memory port uses a much smaller post reset delay with the result that the delay from deassertion of reset to completion of training is dominated by the time spen
424. ocal bus signals as follows Port l64 lads 1 lad Ibe Iclk Iblast lbterm 1 Iready Ireset 1 Iwrite 4138 Map to The signal corresponding to L64 in the testbench The signal corresponding to LADS in the testbench The signal corresponding to LAD 63 0 in the testbench The signal corresponding to LBEZ 3 0 in the testbench The signal corresponding to LCLK in the testbench The signal corresponding to LBLAST in the testbench The signal corresponding to LBTERM in the testbench The signal corresponding to LREADY in the testbench The signal corresponding to LRESET in the testbench The signal corresponding to LWRITE in the testbench ADM XRC SDK 4 9 3 User Guide Win32 locbus agent nonmux ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference locbus agent nonmux Declaration Synopsis Description Declaration component locbus agent nonmux generic tco_bussed in time 5 ns tco_p2p in time 5 ns port lreset 1 io am std logic lclk in std logic la inout std logic vector 31 downto 2 lads 1 inout std logic lbe 1 inout std logic vector 3 downto 0 lblast inout std logic lbterm 1 inout std logic ld inout std logic vector 31 downto 0 lready inout std logic lwrite inout std logic lhold out std logic lholda i un std logic bus in out locbus in t bus out in locbus out t e
425. ock xrc4fx v4fx prj clock xrce4fx v4fx prj clock xrce4fx v4fx prj clock xrc5lx v5lx prj clock xrcbt1 vbfxt prj clock xrc5t1 v5Ixt prj clock xrc5t1 v5sxt prj clock xrc5t2 v5fxt prj clock xrc5t2 v5fxt prj clock xrc5t2 v5fxt prj clock xrc5t2 v5Ixt prj clock xrc5t2 v5Ixt prj clock xrc5t2 v5sxt prj clock xrcp ucf clock xrcp ucf clock xrc2l ucf clock xrc2 ucf clock xpl ucf clock xp ucf clock wrc2 ucf clock drc2 ucf clock xpi ucf clock xrc4Ix ucf clock xrc4sx ucf clock xrc4fx Avfx100 ucf clock xrc4fx Avfx140 ucf clock xrce4fx A4vfx100 ucf clock xrce4fx A4vfx140 ucf clock xrcblx ucf clock xrcbt1 5vfxt ucf clock xrcbt1 ucf clock xrcbt1 ucf clock xrcbt2 5vfx100t ucf clock xrcbt2 5vfx130t ucf clock xrce5t2 5vfx200t ucf clock xrcbt2 5vlx1 10t ucf clock xrcbt2 5vIx330t ucf clock xrcbt2 5vsx240t ucf ADM XRC SDK 4 9 3 User Guide Win32 Clock ADM XRC 5TZ with 5VFX100T ADM XRC 5TZ with 5VFX130T ADM XRC 5TZ with 5VFX200T ADM XRC 5TZ clock xrcbtz vbfxt scr clock xrcbtz vbfxt scr clock xrcbtz vbfxt scr clock xrcbtz v5lxt scr clock xrcbtz vbfxt prj clock xrcbtz vbfxt prj clock xrcbtz vbfxt prj clock xrcbtz 5vfx100t ucf clock xre5tz 5vfx1 30t ucf clock xrcbtz 5vfx200t ucf clock xrcbtz 5vlx1 10t ucf with 5VLX110T 5VLX155T or 5VLX220T ADM XRC 5TZ clock xrcbtz vblxt scr with 5VLX330T ADM XRC 5TZ clock xrcbtz v5sxt scr with 5VSX240T
426. odes the low 3 bits of the address After the first word of data has been transferred LBE will revert to being determined by the be parameter and on the last word of the transfer also determined by any residual bytes that do not comprise a full word of data The be parameter specifies the byte enables to be used for the transfer They are active high and so a 1 in a particular element of be results in a 0 in the corresponding bit of LBE The length of be must be the same as the length of data The data parameter specifies the data to be written on the local bus For a nonmultiplexed address data bus the data is output on the LD signal whereas for a multiplexed address data bus the data is output on the LAD signal The length of data must be the same as the length of be The nxfered parameter returns the actual number of bytes written on the local bus 398 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write const demand ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim write const demand Declaration Synopsis Description Declaration procedure plxsim write const demand order S GU natural address i uu std logic vector be 2p byte enable t data in byte vector t nxfered out natural signal bus in gt in locbus in t signal bus out out locbus out t signal dd in C Zn locbus ddma in t signal dd out out locbus ddma out t Synopsis Perfo
427. of 45 MHz If the Iclk option is not specified on the command line the Memory application programs a sensible default frequency for the model on which the application is run into the local bus clock generator For example the default LCLK frequency when running Memory on an ADM XRC II is 66 MHz The mask option enables a specific set of bits within a logical memory word to be tested The mask defaults to all ones but can be overridden on the command line For example to test bits 0 to 29 inclusive while ignoring bits 30 and 31 of the data on an ADM XRC 4SX card the following would suffice mask 3fffffff The mask is applied to all banks tested on a given run of Memory so if different masks must be applied to different banks use the banks option and test each bank separately By default the Memory application programs the MCLK clock generator to an appropriate frequency for the memory clock domain This may be changed on the command line using the mclk option although it is advisable that the user understands the relationship between the freqency at the target FPGA s MCLK pin i e what is programmed into the clock generator and the frequency of the internal clock within the FPGA For example with an ADM XRC 4FX card passing the option mclk 210 on the command line would result in the DDR II SDRAM devices on the card operating at 210 MHz DDR 420 and the memory clock domain within the target FPGA operating at 105 MHz With an ADM XRC 4LX car
428. of operation for the DMA channel specified by the Channel parameter The ADMXRC2 BuildDMAModeWord function should be used to obtain a suitable value for this parameter The Flags parameter may be any combination of the following Flag Meaning ADMXRC2_DMAFLAG_DONOTQUEUE If the DMA operation cannot be started immediately the error ADMXRC_DEVICE_BUSY is returned rather than queuing the DMA operation The Timeout parameter must currently be NULL as timeouts on DMA operations are not yet supported The Event parameter should be a valid manual reset Win32 event handle See multithreading issues for further information 437 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 DoDMAImmediate ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2_DoDMAImmediate Prototype ADMXRC2_STATUS ADMXRC2 DoDMAImmediate ADMXRC2 HANDLE void unsigned long DWORD ADMXRC2 DMADIR unsigned int DWORD DWORD unsigned long HANDLE Arguments Argument Type Card In Buffer In Length In Local In Direction In Channel In DMAModeWord In Flags In Timeout In out Event In Return value Value ADMXRC2 SUCCESS ADMXRC2 INVALID HANDLE ADMXRC2 INVALID PARAMETER ADMXRC2 DEVICE BUSY ADMXRC2 NO DMADESC Description Card Buffer Length Local Direction Channel DMAModeWord Flags Timeout Event Purpose Handle of card to configure Pointer to application buffer Number of bytes
429. ollows Make sure all virtual memory pages of the user space buffer are memory resident and locked down ie cannot be swapped out to disk This is important to ensure that the user space buffer doesn t disappear in the middle of the DMA transfer In operating systems which do not use virtual memory this step is a no op Make sure that the now memory resident and locked down pages can actually be seen by the PCI device On many platforms this step is a no op However with 64 bit platforms becoming more common and allowing more than 4GB of physical memory not all of the memory in a system can be accessed by a PCI device whose addresses are 32 bits long In such cases the operating system maintains a pool of bounce buffers in a region of memory that is guaranteed to be visible to PCI devices If a page of memory can t be seen by a PCI device the operating system uses a bounce buffer for that page of the DMA transfer If the direction of the DMA transfer is memory to PCl the OS copies the user space data into bounce buffers at this point Some platforms do not automatically maintain cache coherence during a DMA transfers Data caches are typically flushed at this point either entirely or selectively for the specific pages of physical memory used in the DMA transfer At last the CPU can program the PCI device with the DMA transfer parameters and kick off the DMA transfer The thread of execution that kicked off the DMA trans
430. ons lt eptest options lt Options Option Argument type Meaning card base 10 integer ID of card to open E n a DO prompt for confirmation when writing default DON T prompt for confirmation when writing index base 10 integer Index of card to open unlock n a Do not allow PCI configuration to be changed default unlock n a Allow PCI configuration to be changed Description The EPTest utility can be run in one of three different ways The first is when no arguments are given which causes the configuration memory to be dumped to the console resulting in output of the form Selected card ID is 109 0x6d 0x00 0x00100000 0x20 OxFFFFFFFF 0x01 0x00000000 0x21 OxFFFFFFFF 0x02 0x00000000 0x22 OxFFFFFFFF 0x03 0x00000000 0x23 OxFFFFFFFF 0x04 OxOBEBC200 0x24 OxFFFFFFFF 0x05 0x017D7840 0x25 OxFFFFFFFF 0x06 0x01954FC4 0x26 OxFFFFFFFF 0x07 0x00000000 0x27 OxFFFFFFFF 0x08 0x00190019 0x28 OxFFFFFFFF 0x09 0x00190019 0x29 OxFFFFFFFF 0 0x00140014 2 OXFFFFFFFF OxOB OxFFFFFFFF Ox2B OxFFFFFFFF 0xOC 0x0000006D Ox2C OxFFFFFFFF 0x0D 0x0000006D Ox2D OxFFFFFFFF OxOE 0x1010008C 0 2 OxFFFFFFFF OxOF OxFFFFFFFF Ox2F OxFFFFFFFF 0x10 OxFFFFFFFF 0x30 OxFFFFFFFF 0x11 OxFFFFFFFF 0x31 OxFFFFFFFF 0x12 OxFFFFFFFF 0x32 OxFFFFFFFF 0x13 OxFFFFFFFF 0x33 OxFFFFFFFF 0x14 OxFFFFF
431. or example to program the MCLKA MCLKB clock generator on an ADM XRC 5T2 card for a frequency of 250 MHz the following command line would suffice ADM XRC SDK 4 9 3 User Guide Win32 Clock clock 2 250 and this produces output in the following form actual measured values may vary slightly Programming clock generator 1 for 250 00 MHz Actual programmed frequency 250000000 00 Hz Measuring frequency of clock input 2 MCLKA Initial counter value 7709995 Final counter value 257703771 delta 249993776 Here the delta value indicates that the measured frequency of MCLKA is as expected approximately 250 MHz FPGA Design This application uses the Clock sample FPGA design VHDL 45 ADM XRC SDK 4 9 3 User Guide Win32 DLL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DLL sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview The DLL sample application demonstrates the clock doubling capability of DLLs and The user specifies a frequency for the local bus clock on the command line The application programs the local bus clock generator to the specified frequency which is doubled and used to clock a 32 bit counter The application reads
432. or masks one of 32 interrupt sources in the FPGA A 1 in a bit position masks disables the corresponding interrupt source The IMASK register allows individual interrupt sources to be enabled unmasked or disabled masked A disabled masked interrupt source cannot generate a local bus interrupt via the FINTI signal Interrupt Status register ISTAT local bus address 0x4 Bits Mnemonic Type Function 31 0 STAT R W1C When read returns a bit vector that indicates which of the 32 interrupt sources within the FPGA are active A 1 in a particular bit position indicates that the corresponding interrupt source is active When written a 1 in a particular bit position sets the corresponding interrupt source to inactive The ISTAT register indicates which of 32 interrupt sources in the FPGA are active If an interrupt is active 1 will be read in the corresponding bit position of ISTAT regardless of whether it is enabled or disabled via IMASK Writing to a 1 toa particular bit position sets the corresponding interrupt to inactive Interrupt Arm register IARM local bus address 0x8 Bits Mnemonic Type Function 31 0 n a WO Writing to this register forces the FINTI signal high for one clock cycle The IARM register must be used to rearm the edge sensitive FINTI signal Writing to IARM forces FINTI high for one cycle Consider the following sequence of events 1 FPGA interrupt source 0 becomes active FINTI transitions low
433. orm a read of the memory port on behalf of a client Memory port data valid When valid is asserted it is as a result of arbiter 4 performing a read of the memory port on behalf of a client The signals q and qtag are both qualified by valid Memory port write select The arbiter 4 module asserts this signal along with ce when it performs a write to the memory port on behalf of a client ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sdram port component Virtex 4 Virtex 5 only Overview HDL source code Parameters Signals Row column address selection Performance Overview The ddr2sdram port component is part of the memif package and implements an interface to a bank of DDR II SDRAM memory This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure 314 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sdram port ala width 1 0 n to fram taa tag wrath 1 0 width 1 0 torton user held width 5 1 rore width 1 0 memory application did midh 1 0 rd rd with 1 0 devices rowH coal 1 0 bank 1 t pbank 1 0 gid width 1 0 wrdth 1 0 valid ready trained ddresdram port HDL source code Projects making use of this component must
434. ort v2 via their cIkO inputs The relationship between clkc and the capture clocks clkcO and hence clkc180 is as follows o clkcO and clkc180 have the same frequency as clkc o The phase of clkcO with respect clk is determined dynamically by the training sequence as detailed above Performance Using this component to train one or more ddrsdram port v2 instances takes no more than 1 5 milliseconds assuming a clk frequency of 133 MHz This time is measured from deassertion of rst or sr to assertion of trained The number of memory ports does not affect the time required to train them 336 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddr2sram port v2 component Virtex Il Virtex Il Pro only Ove 337 Overview HDL source code Parameters Signals Performance rview The ddr2sram port v2 component is part of the memif package and implements an interface to a bank of DDR II SSRAM memory A related component is the ddr2sram training v2 component which provides infrastructure for training or more instances of ddr2sram port v2 This component follows the generic user interface for memory ports but also has a few additional parameters and sideband signals as shown in the following figure ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 HDL source code Projects making use of this component must include all of the
435. ould be the length of the bitstream file returned by an earlier call to ADMXRC_LoadFpgaFile The Offset parameter must point to a ULONG variable which receives the byte offset within Image at which the SelectMap data begins 519 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC GetBaseAddress ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alph a Data ADMXRC_GetBaseAddress Prototype ADMXRC_STATUS ADMXRC_GetBaseAddress ADMXRC_HANDLE Card void Arguments Argument Type Card In Image Out Return value BaseAddress Purpose The handle of the card whose base address is required Variable to receive a pointer to the FPGA space Value Meaning ADMXRC_SUCCESS The address of the FPGA space was returned successfully ADMXRC INVALID HANDLE Card was not a valid card handle Description This function returns a poi nter by which the application may access the FPGA using direct slave local bus cycles The BaseAddress parameter must point to a variable of type void that is filled in with the base address in the application s address space of the FPGA space Closing a card using ADM XRC_CloseCard will cause the FPGA space to be unmapped from the application s address space Any threads attempting to access FPGA space after the call to ADMXRC_CloseCard will subsequently access invalid virtual addresses resulting in an access violation This cannot crash the system but is generally fatal to an appl
436. pdate application buffer until complete Unaligned DMA transfer to from non memorylike local bus region assuming 32 bit local data bus Unaligned DMA transfer to from non memorylike local bus region assuming 64 bit local data bus DMA write to host memory may not update application buffer until complete When a DMA transfer writes data to host memory ie the direction of the transfer is from the local bus to the PCI bus applications must not rely on being able to see the data as it is written by the PCI device byte by byte This is for two reasons 1 On platforms that use bounce buffers the PCI device may in fact be targetting bounce buffers rather than the application s buffer 2 On some platforms CPU cache coherency is not maintained during DMA transfers The CPU s caches may be made coherent at the end of the DMA transfer but not during the DMA transfer In short an application s buffer is guaranteed to contain valid data only after the DMA transfer has completed ie the call to ADMXRC2 DoDMA or ADMXRC2 DoDMAImmediate has returned Unaligned DMA transfer to from non memorylike local bus region assuming 32 bit local data bus A memorylike region on the local bus is defined to be a range of the local bus address space in which reads and writes have no side effects The only effect of performing a write within such a range is to update zero or more byte locations depending on the value of the byte enables LBE with new data A non
437. peration In order to use demand mode DMA the host must specify the appropriate mode when performing DMA transfers This is demonstrated by the DMA sample application e Data is read from host memory using DMA channel 0 in demand mode An instance of the PLXDDSM module controls the DMA channel e Data is written to host memory using DMA channel 1 in demand mode An instance of the PLXDDSM module controls the DMA channel e Two 512 word by 32 bit FIFOs are used to obtain a 64 bit wide FIFO for buffering data e Bursting is allowed on the local bus e Flow control is implemented by holding off the demand mode DMA request signals LDREQ 1 0 when the FIFO is nearly full or nearly empty FPGA Space Usage The design assumes that any DMA transfer on DMA channel 0 is transferring data into the FIFO hence any direct slave write where LDACK 0 is asserted will write data into the FIFO Similarly any DMA transfer on DMA channel 1 is assumed to be reading data out of the FIFO hence any read where LDACK 1 is asserted will remove data from the FIFO The local bus address is ignored during these demand mode DMA transfers In other words the FIFO is visible over the entire FPGA space during demand mode DMA transfers There are registers that reside in the FPGA direct slave space These registers must be written by the host with a DMA transfer count that matches the size of the DMA transfer being performed prior to the host starting the DMA transfer
438. pipelined ZBT SSRAM e MT46V16M16 Micron DDR SDRAM e HY5PS121621F Hynix DDR II SDRAM 129 ADM XRC SDK 4 9 3 User Guide Win32 Memory Note that simulations targetting models that use DDR II SDRAM memory may require as much as 200 microseconds of simulated time for DLL DCM PLL locking and memory bank training to complete This may result in long periods of inactivity on the local bus Such periods of inactivity do not necesary indicate that the simulation is not working as expected Some warnings may be emitted by memory models DCMs DLLs and PLLs These relate to startup and can safely be ignored as the design is held in reset until clocks have stabilized Model Shell command ADM XRC cd xrc vsim do do memory xrc do ADM XRC P cd xrcp vsim do do memory xrcp do ADM XRC I Lite cd xrc2l vsim do do memory xrc2l do ADM XRC II cd xrc2 vsim do do memory xrc2 do ADM XPL cd xpl vsim do do memory xpl do ADM XP cd xp vsim do do memory xp do ADM XRC 4LX cd xrc4lx vsim do do memory xrc4lx do ADM XRC 4SX cd xrc4sx vsim do do memory xrc4sx do ADM XRC 4FX cd xrc4fx ADPE XRC 4FX vsim do do memory xrc4fx do cd xrce4fx vsim do do memory xrce4fx do ADM XRC 5LX cd xrcblx vsim do do memory xrcblx do ADM XRC 5T1 cd xrcbt1 vsim do do memory xrc5t1 do ADM XRC 5T2 cd 5 2 ADM XRC 5T2 ADV vsim do do memory xrc5t2 do ADM XRC 5TZ cd xrcbtz ADM XRC 5T DA1 130 vsim do do memory xrc
439. plementing a local bus interface that is compatible with both Direct Slave transfers and DMA transfers e Use ofthe port common VHDL modules for interfacing various types of memory to the FPGA e Use of the arbiter 2 common VHDL module for sharing a memory bank between two clients e For models with ZBT memory generation of deskewed copies of the local bus clock LCLK that are driven off chip to the ZBT SSRAMs using DLLs Virtex E EM or DCMs Virtex ll IIPro Virtex 4 and Virtex 5 This technique is used to ensure that ZBT SSRAM devices and the logic within the FPGA operate from clocks that are both phase and frequency matched This design currently supports 6 models in Alpha Data s range of reconfigurable computing cards which use various types of memory e DDR II SSRAM on the ADM XRC 5T1 ADM XRC 5T2 and ADM XRC 5T2 ADV e DDR II SDRAM on the ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 and ADM XRC 5T2 ADV FPGA Space Usage The FPGA space is divided into two regions e A 2MB register region beginning at local bus address 0x0 The registers within the FPGA are accessible via this region e A 2MB memory access window beginning at local bus address 0x200000 The currently selected page of the currently selected bank is accessible via this region The following registers exist in the 2MB register region which begins at local bus address 0 0 Bank register BANK local bus address 0 0 Bits Mnemonic Type F
440. plication to the memory ports ddr2sdram port instances When data is read from a memory bank logical data words flow from the memory ports through the arbiter 2 instances and through the async port instances A multiplexor selects the data from a particular async port according to the current value of the BANK register Finally the port mux instance performs width conversion from logical data words 128 bits to the local bus data width 32 bits outputting the data on mem q Explanation of memory banks module inbound datapath Continuing with the ADM XRC 4FX version as an example the following figure shows detail for the data path from the local bus interface to the memory banks pf async potg port s 0 sel bank 1h E port pce D E mem ce 7 DIE NU cw _ 31 2 L port repl d mem d i rep E asnc_pota Port s 3 signas mem be n mem ce rep final mem tem mem vw mem a 1 0 H other ports Detail of inbound datapath in the memory_banks module The currently selected bank is available as a one hot vector sel bank 1h This is used to ensure that at most one set of port p signals can be active at a given moment in turn ensuring that at most one async port instance can be active at any time The port p signals are generated in a fairly trivial manner from the mem signals which work as follows e mem ce pulsed
441. ppropriate command line for a particular model Some warnings may be emitted by memory models DCMs DLLs and PLLs These relate to startup and can safely be ignored as the design is held in reset until clocks have stabilized Model Shell command ADM XPL vsim do do zbt64 xpl do 167 ADM XRC SDK 4 9 3 User Guide Win32 Verilog designs ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Sample Verilog FPGA designs A number of example Verilog FPGA designs are included with the SDK The purpose of these designs is to demonstrate functionality available on the ADM XRC series of cards and also to serve as customisable starting points for user developed applications The designs are intentionally trivial so that code that implements the functionality being demonstrated can easily be seen The sample FPGA designs are used by the sample applications which demonstrate how software running on the host CPU can interact with an FPGA design The table below lists the sample FPGA designs and the sample applications that use them Design name DLL DDMA DDMA64 FrontlO ITest Master RearlO Simple Simple64 ZBT ZBT64 168 Used by application s DLL DMA DMA FrontlO ITest Master RearlO Simple Simple Memtest Memtest Purpose Demonstrates clock doubling using Virtex DLLs and Virtex Il DCMs Demonstrates use of the DMA engines in demand mode with bursting on the local bus Demo
442. prise a bitstream The Xilinx bitgen program outputs a file whose bytes are logically flipped with respect to what is required by a Virtex FPGA s SelectMap port The Image parameter should be a variable of type ADMXRC IMAGE obtained from an earlier call to ADMXRC LoadFpgaFile The Offset parameter should be the offset value returned by an earlier call to ADMXRC FindlmageOffset The Length parameter should be the length of the SelectMap data returned by the call to ADMXRC FindlmageOffset 536 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC SetClockRate ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC SetClockRate Prototype ADMXRC STATUS ADMXRC SetClockRate ADMXRC HANDLE ADMXRC CLOCK Index double Rate Arguments Argument Type Purpose Card In Handle of card for which to program the clock Index In Specifies which clock generator to program Rate In The desired frequency Return value Value Meaning ADMXRC SUCCESS The clock generator was successfully programmed ADMXRC INVALID HANDLE The Card handle was not valid ADMXRC INVALID PARAMETER The Index or Rate parameters were out of range Description This function programs a clock generator on a card to output the specified frequency The Index parameter of type ADMXRC CLOCK specifies which clock generator to program Value Clock name Range Function ADMXRC VCLK1 LCLK 400kHz 40MHz Local bus clock ADMXRC_MCLK MCLK 400kHz 100MHz Gene
443. programmed I O or DMA to transfer data to and from the ZBT SSRAM is efficient for bulk data transfers and hence the default is to use DMA transfers However because DMA transfers carry a certain set up overhead programmed 1 is efficient for very small data transfers or random access to registers within the FPGA A subset of the memory banks on a card can be tested by passing a bitmask of banks to test via the banks option For example banks 0xD would specify that only banks 0 2 and 3 should be tested The 64 option causes the application to operate the local bus in 64 bit mode This is valid only for models that support a 64 bit local bus Using the local bus in 64 bit mode increases the available bandwidth for data transfer generally resulting in higher measured throughput in phase 6 above FPGA Design The Memtest sample application normally uses the ZBT sample FPGA design Verilog VHDL but when the 64 option is specified it uses the ZBT64 sample FPGA design Verilog VHDL 70 ADM XRC SDK 4 9 3 User Guide Win32 RearlO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data RearlO sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview
444. ps e Functions that cannot block the calling thread and e Functions that are capable of blocking the calling thread The latter group of functions those which are capable of blocking the calling thread require a valid Win32 event of type HANDLE to be passed Unless great care is taken to ensure that no two threads use the same event at the same time this event must be private to each thread using the API Note that this is different to the ADMXRC interface which requires a PHANDLE parameter in the blocking functions rather than a HANDLE parameter The requirement for a per thread event stems from the need to specify an event in overlapped DeviceloControl calls see Win32 API The Microsoft Platform SDK documentation states that events used in an overlapped DeviceloControl call must be manual reset events A code fragment for creating a suitable event for use with the blocking ADM XRC API calls is Create a manual reset Win32 event vent CreateEvent NULL TRUE FALSE NULL if event NULL Error handling 423 ADM XRC SDK 4 9 3 User Guide Win32 Differences between ADMXRC2 and ADMXRC interfaces ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Differences between ADMXRC2 and ADMXRC interfaces The major differences between the ADMXRC2 and ADMXRC interfaces are as follows 424 In the ADMXRC interface functions capable of blocking the calling thread require a poi
445. pyright 2001 2009 Alpha Data ADM XRC API header files The header files are located in the include directory of the SDK and are compatible with Microsoft Visual 5 6 and the free Borland command line tools In any source file requiring visibility of the ADM XRC API include a line such as include admxrc2 h or to use the legacy ADMXRC interface include admxrc h In order for the compiler to be able to locate the API header files the compiler must be configured to search the include directory of the SDK Configuring the MSVC IDE Configuring the Borland command line tools 420 ADM XRC SDK 4 9 3 User Guide Win32 API import libraries ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADM XRC API import libraries The API import library files are located in the lib directory of the SDK and are supplied in several versions File Purpose lib msve admxred lib Microsoft Visual C 5 6 Debug lib msve admxrce lib Microsoft Visual C 5 6 Release lib borland admxrc lib Borland C command line tools In order for the compiler to be able to locate the API import libraries the compiler must be configured to search the lib directory of the SDK Configuring the MSVC IDE Configuring the Borland C command line tools 421 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 interface ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 interface
446. quency Actual Out The actual frequency programmed Return value Value Meaning ADMXRC2 SUCCESS The clock generator was successfully programmed ADMXRC2 INVALID HANDLE The Card handle was not valid ADMXRC2 INVALID PARAMETER The Index or Rate parameters were out of range Description This function programs a clock generator on a card to output the specified frequency The Index parameter is a zero based index that specifies which clock generator to program A value of 0 or ADMXRC2 CLOCK LCLK refers to the local bus clock The number of programmable clock generators on a card can be obtained from the NumClock member in the ADMXRC2 CARD INFO structure The maximum legal value of Index is NumClock 1 The Rate parameter specifies the desired clock frequency in Hz This frequency should be within the limits specified in the table below and also within the limits imposed by any bitstream that has been loaded into the FPGA The Actual parameter may either be NULL or point to a variable of type double that is to receive the actual clock frequency programmed in Hz Since a digitally programmable clock generator device is used the actual frequency programmed may not be exactly the same as the desired frequency The clock generators on the various models in the ADM XRC range are as follows 461 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SetClockRate Card ADM XRC ADM XRC P ADM XRC I Lite ADM XRC II ADM XPL ADM XP ADP WRC II
447. r and ADMXRC SyncDirectMaster functions 560 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DMA CHANNEL ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC DMA CHANNEL Declaration typedef enum ADMXRC DMA CHANNEL ADMXRC DMACHAN 0 0 ADMXRC_DMACHAN_1 I ADMXRC DMACHAN ANY OxFFU ADMXRC DMA CHANNEL Description This type specifies which DMA channel should be used to perform a DMA transfer used primarily with the ADMXRC DoDMA and ADMXRC DoDMAlmmediate functions It must be one of the following values Value Meaning DMACHAN 0 Use 9080 channel 0 DMACHAN 1 Use PCI9080 channel 1 ADMXRC DMACHAN ANY Use any available PCI9080 DMA channel 561 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DMA DIRECTION ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC DMA DIRECTION Declaration typedef enum ADMXRC PCI2LOCAL 0 ADMXRC LOCAL2PCI 1 j ADMXRC DMA DIRECTION Description The ADMXRC DIRECTION enumerated type specifies the direction of data transfer in a DMA transfer for the ADMXRC DoDMA and ADMXRC DoDMAlmmediate functions It is one of the following values Value Meaning ADMXRC_PCI2LOCAL Data is transferred from host to FPGA ADMXRC_PCI2LOCAL Data is transferred from FPGA to host 562 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC DMA WIDTH ADM XRC SDK 4 9 3 User Guide Win32
448. r of address bits in the logical SSRAM banks Address lengths of 17 18 19 and 20 bits are accomodated The page register augments the limited address space 2MB allotted to accessing the SSRAM The following figure illustrates this for an ADM XRC II with six 512k 36 ZBT SSRAM devices fitted 193 ADM XRC SDK 4 9 3 User Guide Win32 ZBT P AGE 7 0 0x3 Ox400000 Local bus byte address LA 21 0 0x200000 Register region 2MB FPGA Space Usage SSR AM window 2MB 0x400000 No bank Returns zeroes No bank Returns zeroes Bank 5 2MB Bank 4 2MB Bank 3 2MB Bank 2 2MB Bank 1 2MB Bank 0 2MB 0 380000 Augmented lonqword address P amp GE 7 0 LA 20 2 0 300000 0 280000 0 200000 0 180000 0 100000 0 080000 Ox000000 The following registers exist in the 2MB register region Page register PAGE local bus address 0 0 Bits Mnemonic Type 7 0 PAGE R W 31 8 MBZ Mode register MODE local bus address 0x4 Bits Mnemonic Type 0 PIPELINED R W 31 1 MBZ Size register SIZE local bus address 0 8 Bits Mnemonic Type 1 0 SIZE R W 31 2 MBZ 194 Function Value that augments bits 20 2 of the local bus address when accessing the SSRAM Function Value that selects the mode in which to operate the ZBT SSRAM devices 0 gt flowthrough 1 gt pipelined Function Value that specifies the number of
449. ral purpose The Rate parameter specifies the desired clock frequency in Hz 537 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC SetupDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC SetupDMA Prototype ADMXRC STATUS ADMXRC SetupDMA ADMXRC HANDLE Card void Buffer unsigned long Size DWORD Flags ADMXRC DMADESC DMADesc Arguments Argument Type Purpose Card In Handle of card Buffer In The application buffer to lock down Size In The size of the application buffer Flags In Miscellaneous flags DMADesc Out The DMA descriptor returned Return value Value Meaning ADMXRC SUCCESS The application buffer was successfully locked down and a DMA descriptor returned ADMXRC INVALID HANDLE The Card handle was not valid ADMXRC INVALID PARAMETER Flags was not valid ADMXRC NO DMADESC All DMA descriptors were in use Description This function locks down and maps an application buffer returning a descriptor which can subsequently be used to identify the buffer to the DMA API functions such as ADMXRC DoDMA and ADMXRC DoDMAlmmediate The Buffer parameter must point to the application buffer to be mapped The Size parameter specifies the size in bytes of the application buffer to be mapped The Flags parameter must currently be O The DMADesc parameter must point to a variable of type ADMXRC DMADESC If ADMXRC_SetupDMA succeeds this variable will contain a DMA descriptor on retur
450. ransfer s LDACK will be asserted with the proper timing with respect to LADS etc The order parameter specifies the width of the local data bus Valid values are e 2 for a 32 bit local data bus e fora 64 bit local data bus The address parameter specifies the starting local bus byte address of the transfer which will be incremented during the transfer It need not be aligned to the word size of the local data bus The manner in which the address is output on the local bus depends upon the type of local bus agent being used e Fora nonmultiplexed 32 bit local bus LA 31 2 carries the high 30 bits of the address and LBEZ 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 32 bit local bus LAD 31 2 carries the high 30 bits of the address and LBE 3 0 effectively encodes the low 2 bits of the address e Fora multiplexed 64 bit local bus LAD 31 3 carries the high 29 bits of the address and LBE 7 0 effectively encodes the low 3 bits of the address The be parameter specifies the byte enables to be used for the transfer They are active high and so 1 in a particular element of be results in a 0 in the corresponding bit of LBE The length of be must be the same as the length of data The data parameter holds the data to be written on local bus For a nonmultiplexed address data bus the data is output on the LD signal whereas for a multiplexed address data bus the data is output on the LAD signal The
451. rd ID passed via the CardID parameter If there is more than one card in the system with the same ID the function will open the first free card found with the specified ID If the special value 0 is used for CardlD the first card found that is not in use will be opened regardless of its ID The handle returned in the Card parameter should be used in all further API calls that need to access this card When access to the card is no longer required call ADMXRC_CloseCard to close the handle and free the card 531 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC Read ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC Read Prototype ADMXRC STATUS ADMXRC Read ADMXRC HANDLE Card Width unsigned long unsigned long DWORD void unsigned long Flags Local Buffer ength Arguments Argument Type Card In Width In Flags In Local In Buffer Out Length In Return value Value ADMXRC SUCCESS ADMXRC INVALID HANDLE Purpose Handle of card from which the read is to take place Width of operation Miscellaneous flags Local bus address at which to begin reading Buffer to receive data read Number of bytes to read ADMXRC INVALID PARAMETER Description Meaning The data was read successfully Card is not a valid handle to a card An invalid parameter was passed The ADMXRC Read function reads a number of bytes from the local bus using direct slave cycles or from the
452. rds whose width is the native memory width for example 128 bits for a DDR II SDRAM port in the ADM XRC 4FX e The tag signal is qualified by the logical AND of ce and not w and is a value to be associated with a particular read command The tag value and width is at the discretion of the designer and can be whatever he or she wants When the memory port asserts valid for a given read command i e assertion of ce in a particular clock cycle the qtag signal reflects the tag value that was present on the tag input when ce was asserted One application of the tag signal is in the async port module it uses the tag to avoid returning stale data to the local bus clock domain when one read ends and another one begins e The d signal is qualiied by the logical AND of ce and w and carries the data for a write command ADM XRC SDK 4 9 3 User Guide Win32 Memory The be signal is qualiied by the logical AND of ce and w and carries the active high byte enables for a write command When bit of beis 1 byte will be written When bit i of beis 0 byte will not be written The q signal is the data read from the memory devices for a particular read command and is qualified by valid The qtag signal is the tag value associated with a particular read command and is qualified by valid The valid signal indicates that data read from the memory devices is present on q along with the associated tag value on qtag The ready signal indicates that th
453. re by erbiter access lost here readyO possible assertion latest possible deassertion of ce of ce Relationship between readyO and ce0 when ready delay 2 6 If the registered parameter is false the memory port output signals ce w etc are generated combinatorially from the client port input signals w0 ce1 w1 etc If the registered parameter is true the memory port output signals ce w etc are registered before being output This adds one cycle of latency but is recommended for ease of timing closure This parameter has no effect on the timing relationship between ready and cei 7 If the unfair parameter is true the client identified by the bias parameter is given priority access to the memory port This overrides the latency parameter meaning that the favored client can interrupt a burst of memory accesses by one of the unfavored clients Signals 296 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 2 The arbiter 2 module has the following infrastructure ports Signal Type Function Note clk in Clock All other signals except rst are synchronous to clk rst in Asynchronous reset This port should be mapped to the asynchronous reset signal if there is one or to a constant logic 0 signal if an asynchronous reset is not required sr in Synchronous reset This port should be mapped to the synchronous reset signal if there is one or to a constant logic 0 signal if a synchro
454. read command gtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Asynchronous reset for memory port May be tied to logic 0 if not required Synchronous reset for memory port May be tied to logic 0 if not required Tag in When user code asserts ce with w deasserted it must also place a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags Training success flag sideband signal When the memory port asserts trained it indicates that training of the memory port was successful When deasserted either training is not yet complete or training was unsuccessful Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v4 w in Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command Notes 5 The phase and frequency relationships between the four clock phases are illustrated b
455. red value of a width depends on what memory devices are actually in use As an example consider a DDR II SSRAM device with 20 address bits Since logical memory locations are two times as wide as the physical memory locations one must subtract 1 giving a value of 19 for the minimum value of a width When a width is larger than actually required the top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory devices are in use Signals The signals of this interface to and from the user application are as follows Signal Type Function Note a in Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as a linear array of words of width d width this address is a logical address rather than anything resembling what one might see on the ra bus be in Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory burst len in Burst length select sideband signal 6 This input selects whether the DDR II SSRAM devices are burst length 2 BL2 or burst length 4 BL4 devices 0 gt BL2 1 gt BL2 BL4 If BL2 BL4 is
456. represented by DmaDesc It is up to the application programmer to provide a mechanism by which the returned PCI page addresses are transferred to the FPGA A simple mechanism is a bank of registers within the FPGA the host simply writes the PCI page addresses to these registers using direct slave transfers Prior to calling ADMXRC2 MapbDirectMaster the MaxPages and PagesPci members must be initialized by the application PagesPci should point to an application allocated buffer that will receive the PCI addresses of the pages comprising the specified region of the application buffer This region is specified by the Offset and Length parameters MaxPages should be initialized to the number of unsigned long elements in the array that PagesPci points to If ADMXRC2 MapbDirectMaster succeeds the PageLength PagesSpanned BytesSpanned and InitOffset members of the ADMXRC2 BUFFERMAP that Map points to will be filled in with valid values It is possible that the number of pages in the array Map gt PagesPci will not be sufficient to map the entire region specified by Length and Offset There are two cases e MaxPages is equal to or greater than the actual number of pages spanned by the region in the user buffer specified by Length and Offset The function will map all of the specified region In this case the entire region is mapped and BytesSpanned will be equal to Length Physical memory Application buffer 1 en th T P
457. req2 req3 tag0 tag tag2 tag3 validO valid1 valid2 valid3 wO w1 w2 w3 Notes 311 in out out out out Client command entry A client asserts this signal to enter a new read or write command into the memory port When asserted a and wi must be valid When asserted along with wi tagi must also be valid A client must observe the rules for assertion of cei with respect to readyi as illustrated by note 5 above Other than that there are no restrictions on how few or how many clock cycles cei can remain asserted It can be pulsed for single clk cycles or asserted for many clk cycles readyi permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but the performance of certain types of memory for example DDR SDRAM benefits from locality of access Client data to memory A client must place valid data on d whenever a write command is entered cei and wi both asserted Client data from memory When validi is asserted is asserted by the memory port as a result of a read command qi reflects the data read from memory Client tag out When validi is asserted by the memory port as a result of a read command qtag reflects the tag value that was assocated with that read command Client ready When readyi is asserted a client is permitted to assert cei The readyi signal for a client is asserted when two conditions ar
458. ress bits Since logical memory locations are four times as wide as the physical memory locations one must subtract 2 giving a value of 19 for the minimum value of a width When a width is larger than actually required the top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory devices are in use Signals The signals of this interface to and from the user application are as follows Signal Type Function Note a in Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as a linear array of words of width d width this address is a logical address rather than anything resembling what one might see on the ra bus be in Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory ce in Command entry User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce
459. rms a demand mode DMA local bus write transfer with constant local bus address Description This procedure uses the bus in bus out dd in and dd out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim write const demand lachus ddma out t Idack 1 lt 02 gt lacbuz dama in t Idreg 1 0 gt Stimulus process n Local bus FPGA design unit under test agent LOCAL BUS 0 399 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write const demand Before calling this procedure a stimulus process should ensure that the FPGA ie the unit under test has asserted LDREOX This can be accomplished by calling plxsim wait demand before calling plxsim write const demand When called the procedure will continue to perform transfers until one of two conditions is met 1 The FPGA unit under test deasserts LDREQ in order to pause the DMA transfer or 2 All of the data has been transferred the length of the data vector specifies how many bytes must be transferred During the transfer s LDACK will be asserted with the proper timing with respect to LADS etc The order parameter specifies the width of the local data bus Valid values are e 2 for a 32 bit local data bus e for a 64 bit local data bus The address parameter specifies the local bus byte address of the transfer which will not be incremented during the transfer The address need not be aligne
460. ror out Training successful This signal is asserted when training has been completed for all associated ddr2sram port v2 instances and was successful i e a data capture window was found for all memory ports If training is completed but was unsuccessful i e a data capture window could not be found for one or more of the memory ports this signal will remain deasserted even though training has been completed There is no required relationship between clk and the capture clocks clkcO and clkc180 and no required relationship between clk and clkc However depending on the needs of the application clk and clkc may or may not be exactly the same signal The signal used to clock an instance of ddr2sram training v2 via its clk input must be the same or an exact copy of the signal used to clock any associated instances of ddr2sram port v2 via their cIkO inputs The relationship between clkc and the capture clocks clkcO and hence clkc180 is as follows o clkcO and clkc180 have the same frequency as clkc o The phase of clkcO with respect clk is determined dynamically by the training sequence as detailed above Performance Using this component to train one or more ddr2sram port v2 instances takes no more than 1 5 milliseconds assuming a clk frequency of 133 MHz This time is measured from deassertion of rst or sr to assertion of trained The number of memory ports does not affect the time required to train them 348
461. rototype ADMXRC STATUS ADMXRC LoadFpgaFile UCHAR Filename ADMXRC_IMAGE Image ULONG ImageSize Arguments Argument Type Purpose Filename In Name of bitstream file to load Image Out Loaded bitstream data ImageSize Out Size in bytes of loaded bitstream file Return value Value Meaning ADMXRC_SUCCESS The bitstream file was successfully loaded ADMXRC FILE NOT FOUND The file could not be opened ADMXRC INVALID FILE The file appeared not to be a valid bitstream ADMXRC NO MEMORY There was insufficient free memory to hold the bitstream Description This function loads the SelectMap data from a Xilinx bitstream BIT file into memory and returns a pointer to it The data returned is in correct bit order for sending to an FPGA s SelectMap port The Card parameter specifies the card that the bitstream targets This information is used to check that the bitstream matches the FPGA fitted to the card The bitstream file to load into memory is specified by the Filename parameter The Image parameter must point to a variable of type ADMXRC IMAGE A pointer to the buffer that contains the loaded bitstream file allocated by ADMXRC LoadFpgaFile is returned The ADMXRC_UnloadFpgaFile function should be used to free the memory used by the bitstream when no longer required The ImageSize parameter must point to a ULONG variable which receives the length of the file 527 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC MapbDirectMaster ADM X
462. rrupt Enter q to quit or anything else to generate an interrupt Enter q to quit or anything else to generate an interrupt Enter q to quit or anything else to generate an interrupt Generated 5 interrupts Interrupt thread saw 5 interrupt s FPGA Design The ITest example application uses the ITest sample FPGA design Verilog VHDL 60 ADM XRC SDK 4 9 3 User Guide Win32 Master ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Master sample application Model support Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview Supported The Master sample application demonstrates access to host memory by the target FPGA using direct master cycles Syntax master options Options Option Type card base 10 integer index base 10 integer Description Meaning ID of card to open Index of card to open On startup the application allocates a user space buffer and calls ADMXRC2 SetupDMA to lock it in memory It then 61 ADM XRC SDK 4 9 3 User Guide Win32 Master obtains a scatter gather map of the buffer by calling ADMXRC2_MapDirectMaster It initializes the user space buffer to contain known data and then waits for the user to enter commands which can be the followi
463. rs The Width parameter specifies the width of the operation and must be one of the following values Value ADMXRC IOBYTE ADMXRC IOWORD ADMXRC IOLONG Meaning BYTE 8 bit width WORD 16 bit width DWORD 32 bit width The Flags parameter modifies the semantics of the operation Normally the write is performed to local bus space with an 546 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC Write incrementing address but this behavior can be modified by any combination of the following Flag Meaning ADMXRC IOFIXED The local bus address is not incremented during the transfer ADMXRC_IOPLX The read is performed from the card s PCI interface registers rather than the local bus If the ADMXRC IOPLX flag is not specified the Local parameter specifies the starting local bus address to which the data will be written Otherwise the Local parameter specifies the starting PLX register offset to which the data will be written If the ADMXRC IOFIXED flag was specified this address will not increment as the data is written Otherwise the address is incremented as the data is written The Buffer parameter specifies the buffer containing the data to be written The Length parameter specifies how many bytes are to be written and should be a multiple of the width specified by the Width parameter For example if Width is ADMXRC_IOWORD the Length parameter should be a multiple of 2 547 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC_WriteReg
464. rsion of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location SADMXRC_SDK4 fpga vhdl ddma Synopsis 86 ADM XRC SDK 4 9 3 User Guide Win32 DDMA The FPGA design demonstrates demand mode DMA with bursting Data is read from an application buffer in host memory and then simply written back to another application buffer unchanged a loopback operation In order to use demand mode DMA the host must specify the appropriate mode when performing DMA transfers This is demonstrated by the DMA sample application e Data is read from host memory using DMA channel 0 in demand mode An instance of the PLXDDSM module controls the DMA channel e Data is written to host memory using DMA channel 1 in demand mode An instance of the PLXDDSM module controls the DMA channel e A 512 word by 32 bit FIFO is used to buffer data e Bursting is allowed on the local bus e Flow control is implemented by holding off the demand mode DMA request signals LDREQ 1 0 when the FIFO is nearly full or nearly empty FPGA Space Usage The design assumes that any DMA transfer on DMA channel 0 is transferring data into the FIFO hence any direct slave write where LDACK 0 is asserted will write data into the FIFO Similarly DMA transfer on DMA channel 1 is assumed to be reading data out of the FIFO hence any read where LDACK 1 is asserted will remove data fro
465. rue the memory port automatically trains itself after reset is deasserted If false the memory port does not train itself This parameter has a default value of true and in normal usage an application should rely on the default value and not map it to any particular value d width natural Width in bits of the port data in and out d and q 3 respectively pinout ddr2sdram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants ra width natural Width in bits of the memory device address bus ra 1 rc width natural Width in bits of the memory device control bus rc 2 rd width natural Width in bits of the memory device data bus rd 3 tag width natural Width in bits of the tag in and out tag and qtag respectively timing ddr2sdram timing t This value specifies the timing of the memory port For convenience an application may map it to one of the predefined constants Notes 1 The memory device address bus ra is composed of two fields in this memory port with the widths of each field specified by the num addr bits and num bank bits of the pinout parameter Therefore ra width is the sum of these two values The following figure illustrates this for the case where num addr bits 15 and num bank bits 3 Bank address column address BA pins A pins 1 qe YIOq_q_me nzpensmamsmaptmo s ja 7 8 4 3 2 1 0 ra
466. ry User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory burst len in Burst length sideband signal 8 If this input is 0 then the SSRAM devices being driven must be burst length 2 devices If this input is 1 then the SSRAM devices being driven may be burst length 2 or burst length 4 devices ce in Command entry User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single clkO cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but refer to the section below for a discussion of how to maximize performance cedge training in Capture edge 7 signal This signal is normally driven directly by an instance of the component ddr2sram training v2 and contains information instructing ddr2sram port v2 how to retime the data captured from the SSRAM device using clkcO and clkc180 into the c
467. ry locations 2 To provide memory port components whose user interfaces are as similar as possible From the point of view of client code the above components all present a similar interface to the user This generic user interface is described below The components datatypes and constants exported by the memif package are listed in the sections below Components Name Function arbiter 2 Two port multiplexor for a memory port arbiter 3 Three port multiplexor for a memory port arbiter 4 Four port multiplexor for a memory port ddr2sdram port DDR II SDRAM memory port for Virtex 4 and Virtex 5 ddr2sram port v2 DDR II SSRAM memory port for Virtex 2 and Virtex 2 Pro ddr2sram training v2 DDR II SSRAM training module for Virtex 2 and Virtex 2 Pro ddr2sram port v4 DDR II SSRAM memory port for Virtex 4 and Virtex 5 ddrsdram port v2 DDR SDRAM memory port for Virtex 2 and Virtex 2 Pro ddrsdram training v2 DDR SDRAM training module for Virtex 2 and Virtex 2 Pro zbtsram port ZBT SSRAM memory port for all FPGA families Datatypes Name Function ddr2sdram pinout t Record type that describes the physical configuration of a DDR II SDRAM port 279 ADM XRC SDK 4 9 3 User Guide Win32 Memory interface package VHDL ddr2sdram timing t Record type that describes the timing of a DDR II SDRAM port ddrsdram pinout t Record type that describes the physical configuration of a DDR SDRAM port ddrsdram timing t Record type that describes the tim
468. s a null bitstream that does nothing but configure the DCMs in a Virtex 4 device and on Virtex 4 FX devices also configures the This bitstream is required because of NBTI issues in Virtex 4 On applicable models Alpha Data programs a factory default null bitstream into the failsafe image and overwriting it is not recommended For an overview of the NBTI issue in Virtex 4 refer to Xilinx answer 21127 On such models the normal and failsafe images can be blank checked erased programmed and verified independently of each other In other words performing a blank check erase program or verification on one image has no effect on the other image Therefore in day to day operation end users should not need to use the failsafe option 54 ADM XRC SDK 4 9 3 User Guide Win32 FrontIO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data FrontlO sample application Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview The FrontlO sample application configures the target FPGA with a bitstream that outputs a walking 1 bit on the front panel I O connector As soon as the target FPGA has been configured with the bitstream the application terminates Syntax frontio opt
469. s asserted by the memory port as a result of a read command gtag reflects the tag value that was assocated with that read command Port ready When the memory port asserts ready user code is permitted to assert ce Asynchronous reset for memory port May be tied to logic if not required Synchronous reset for memory port May be tied to logic if not required Tag in When user code asserts ce with w deasserted it must also place a valid tag on the tag signal When as a result of the read command the memory port asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 tstcomp training signal in tstdo training in signal tstdone training signal out tstok training out signal valid out Notes 342 Capture edge 7 This signal is normally driven directly by an instance of the component ddr2sram training v2 and informs the ddr2sram port v2 that training is complete and that normal operation can begin Do readback test 7 This signal is normally driven directly by an instance of the component ddr2sram training v2 and instructs the ddr2sram port v2 to perform a readback experiment during the training sequence Done readback test 7 This signal i
470. s combinatorially from the LA pins can make it easier to meet timing specifications when operating LCLK at a high frequency LBTERM and LREADY should not be continuously driven by the FPGA as on some models in the ADM XRC range there may be other slaves on the local bus These signals should be driven only when the FPGA has positively decoded the address following the assertion of LADS At the end of a cycle ensure that the FPGA drives LBTERM and LREADY high for a cycle or half of a cycle before being tristated This will prevent problems due to these signals being resistively pulled up at too slow a rate The plxdssm module used by many of the sample FPGA designs in the SDK does this LBTERM implies ready In other words assertion of LBTERM serves to transfer the current word of data and terminate the burst Put another way in an application where bursting is not required LREADY need never be asserted while LBTERM can serve as the ready signal The normal termination condition for a burst is LREADY 0 and LBLAST 0 or LBTERM 0 Unlike a PCI bus burst there is no mechanism for terminating a local bus burst without transferring any data When a burst is initiated at least one word of data must be transferred ADM XRC SDK 4 9 3 User Guide Win32 PLXDSSM a practical example ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXDSSM A practical example PLXDSSM module defi
471. s constant address mode can then be supplied in a call to ADMXRC2 DoDMA and ADMXRC2 DoDMAImmediate This following topics illustrate the local bus protocol when constant address mode is used Constant address mode in local bus with nonmultiplexed address data Constant address mode in local bus with multiplexed address data Tracking the local bus address during a burst Constant address mode nonmultiplexed address data LADS Key m Signal is driven LA 0 by local bus bridge Signal is dri b LBE gt BE3 BEA FPGA LYWWRITE LBLAST LRE AD Y LBTERMZ LD DO Di 5 4 D2 D4 Here the local bus address is constant throughout each burst and constant from one burst to the next Constant address mode multiplexed address data 242 ADM XRC SDK 4 9 3 User Guide Win32 Constant address mode eS a O O OG a a LLLI LILBaA LDsR wx fC mm mE m Signalis driven LAD AO d DO y Di d 40 d D2 Y D3 f 04 by local bus bridge B2 ES ses and LBLAST LRE AD Y LBTERMZ Here the local bus address is implicitly constant throughout each burst and constant from one burst to the next Tracking the local bus address during a burst At first glance it would appear that in a local bus with multiplexed address data there is no way to k
472. s its HOLD signal it must wait for the arbiter to deassert its HOLDA signal before reasserting HOLD In an ADM XRC series card the respective HOLD HOLDA pairs are given different names to avoid confusion between the two e The FPGA s pair are named FHOLD and FHOLDA The FPGA should generally use FHOLDA to qualify the assertion of LADS when deciding whether or not to respond to a burst as a slave e he local bus bridge s pair are named LHOLD and LHOLDA The HDL source code samples use this convention The following timing diagrams illustrate the arbitration protocol Single burst bus tenure Multi burst bus tenure Two bus tenures Single burst bus tenure The following timing diagram illustrates a bus tenure that consists of a single burst 254 ADM XRC SDK 4 9 3 User Guide Win32 Arbitration HOLD o ooo TL Key m Signal is driven HOLD A _ by arbiter m Signal is driven LADS by master LBLAST f m Signal is driven by a slave LRE AD Y LBTERMZ single burst bus tenure Multi burst bus tenure The following timing diagram illustrates a bus tenure that consists of a more than one burst xnnruuuuuuuuuuuuuuuuuuuuuUU HOLD bas Signal is driven HOLD A by arbiter a Signal driven LAD S _ Lj by master LBLAST mM 5 m Signal is driven by a slave LRE AD Y __ JT 7
473. s normally connected directly to an instance of the component ddr2sram training v2 and informs the ddr2sram training v2 instance that the ddr2sram port v2 has completed a readback experiment during the training sequence It qualifies the tstok output Readback test OK 7 This signal is normally connected directly to an instance of the component ddr2sram training v2 and informs the ddr2sram training v2 instance whether or not the most recent readback experiment was successful It is qualified by the tstdone output Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command 5 The phase and frequency relationships between the four clock phases are illustrated by the following figure ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 clkg0 clk1 50 Tne m aci L_J LILI LI Also shown are the related clocks the DDR II SSRAM clock pair and K and the capture clock pair clkcO and clkc180 Their frequencies are the same as clkO but their phases are indeterminate with respect to clkO For correction operation all sideband inputs must be static while the memory port is not idle The connections between
474. s the revision of the control logic on the board as a two digit number OxAB where A is the major revision and B is the minor revision The SerialNum member is the serial number of the card 553 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC CARD INFO The Timeout member should be ignored 554 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC VERSION INFO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC VERSION INFO Declaration typedef struct ADMXRC VERSION INFO UCHAR DriverMinor UCHAR DriverMajor UCHAR APIMinor UCHAR APIMajor ADMXRC VERSION INFO Description The ADMXRC VERSION INFO structure is returned by ADMXRC GetVersionlnfo and indicates the API library revision level and the driver revision level DriverMajor and DriverMinor respectively indicate the ADM XRC device driver major and minor revision levels APIMajor and APIMinor respectively indicate the API library major and minor revision levels The API library is implemented a set of dynamic link libraries DLLs that are part of the installable driver package 555 ADM XRC SDK 4 9 3 User Guide Win32 Types ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC interface types This section describes the atomic datatypes of the ADMXRC interface Name ADMXRC CLOCK ADMXRC CLOCK TYPE ADMXRC DEVICE NUM ADMXRC DMADESC ADMXRC DMA CHANNEL ADMXRC DMA DIRECTION ADMXRC DMA WID
475. s the transfers on the PCI bus To sum up the differences between DMA and Direct Slave transfers Direct Slave DMA Local bus master is Bridge PCI9080 PCI9656 etc Bridge PCI9080 PCI9656 etc Local bus slave is FPGA FPGA PCI bus master initiator is Host CPU Bridge PCI9080 PCI9656 etc PCI bus slave target is Bridge PCI9080 PCI9656 etc Host CPU Constant addressing mode implemented by driver yes LEOT mode N A yes Demand mode N A yes The DMA engines are configurable to operate in a variety of modes For a discussion of these modes click on the following topics Constant addressing mode Demand mode LEOT mode 234 ADM XRC SDK 4 9 3 User Guide Win32 DMA transfers The following topics provide further details about the practicalities of DMA transfers on an ADM XRC series card What happens during a DMA transfer Caveats of DMA transfers 235 ADM XRC SDK 4 9 3 User Guide Win32 What happens during a DMA transfer ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data What happens during a DMA transfer Every DMA transfer must be set up by the CPU and when it has finished must also be torn down by the CPU Most operating systems attempt to hide the details of this process from the user and even from drivers but the setup and tear down of a DMA transfer can be fairly involved on some platforms The steps taken by the CPU for a DMA transfer in an idealised operating system are as f
476. scr Virtex E ADM XRC II Lite ddma xrc2l v2 scr ADM XRC II ddma xrc2 v2 scr ADM XPL ddma xpl v2p scr ADM XP ddma xp v2p scr ADP WRC II ddma wrc2 v2 scr ADP DRC II ddma drc2 v2 scr Project Navigator files Project Navigator projects can be found in the projnav directory as follows ddma xrc ve prj ddma xrcp v prj ddma xrcp ve prj ddma xrc2l v2 prj ddma xrc2 v2 prj ddma xpl v2p prj ddma xp v2p prj ddma wrc2 v2 prj ddma drc2 v2 prj Model Project Navigator project file ADM XRC projnav re device ADM XRC P projnav rcp device ADM XRC II Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt ADP WRC II projnav wrc2 lt device gt ADP DRC II projnavdrc2 device 171 ddma xrc ucf ddma xrcp ucf ddma xrcp ucf ddma xrc2l ucf ddma xrc2 ucf ddma xpl ucf ddma xp ucf ddma wrc2 ucf ddma drc2 ucf ADM XRC SDK 4 9 3 User Guide Win32 DDMA64 ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DDMAG64 sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL 2 20 2VP30 only ADM XP a ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5T
477. sdram pinout t datatype The memif ddrsdram pinout t datatype is exported by the memif package and is used to specify the physical configuration of an instance of ddrsdram port It is a record type defined as follows type ddrsdram pinout t is record family flight time dqs dq delay dqs dm delay Ck width width num bank bits num addr bits end record family t na bool bool na na num phys bank na na na tural tural tural tural tural tural ean ean This datatype can normally treated as an abstract datatype since the user application need typically only use one of the predefined constants of type ddrsdram_pinout_t However should it be necessary to create a new value the members are defined as follows Member Type family family_t flight_time natural dqs dq delay boolean dqs dm delay boolean ck width natural cke width natural num phys bank natural num bank bits natural num addr bits natural Function Specifies the FPGA family that the memory port targets Round trip DQ delay in 1 4 clock cycles If true specifies that DQS PCB traces have additional delay with respect to DQ PCB traces If true specifies that DQS PCB traces have additional delay with respect to DM PCB traces Number of CK CK pairs present in the rc bus Number of pins present in the rc bus Specifies the number of physical banks being driven by the memory port
478. seconds on a DDR SDRAM datasheet the values should be computed by dividing the datasheet parameters by the period e g 7 5 ns and rounding up to the nearest integer An example of such a parameter is t rp e For parameters that are specified in numbers of DDR memory clock cycles the datasheet values can be used as is An example of such a parameter is t dllr 292 ADM XRC SDK 4 9 3 User Guide Win32 zbtsram pinout t ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The zbtsram pinout t datatype The zbtsram pinout t datatype is exported by the memif package and is used to specify the physical configuration of an instance of zbtsram port It is a record type defined as follows type zbtsram pinout t is record family family t has ce2 boolean has ce2 1 boolean has 1 boolean end record This datatype can normally treated as an abstract datatype since the user application need typically only use one of the predefined constants of type zbtsram pinout t However should it be necessary to create a new value the members are defined as follows Member Type Function family family t Specifies the FPGA family that the memory port targets has ce2 boolean If true the rc bus of the memory port includes the CE2 pin has ce2 boolean If true the rc bus of the memory port includes the CE2 pin has cke boolean If true the rc bus of the memory port includes the CKE pin
479. selected the memory port will be compatible with BL2 and BL4 devices although a performance penalty may apply depending on how the user application uses the memiry port If BL2 is selected the memory will not be compatible with BL4 devices If the burst length is unknown at build time one should select BL4 Refer to the section below for a discussion of performance ADM XRC SDK User Guide Common Memory Ports ce clkO clk90 clk180 clk270 dll off qtag ready in out out out Command entry User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single clkO cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of acommand need not bear any relationship to that of the previous command but refer to the section below for a discussion of performance Clock for user interface All other signals except rst are synchronous to clkO High speed clock phase 90 This clock must be the same frequency as but 90 degrees behind High speed clock phase 180 This clock must be the same frequency as but 180 degrees behind High speed clock phase 270
480. simply be the local bus LWRITE signal 259 ADM XRC SDK 4 9 3 User Guide Win32 PLXDSSM a practical example Iready o 1 Iready oe 1 Ibterm o Ibterm oe ld oe eld oe ready stop idle decode write transfer OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT This signal should normally be driven onto the local bus as LREADY when oe l is asserted This signal is the active low output enable for the local bus LREADY signal This signal should normally be driven onto the local bus as LTERM when Ibterm oe l is asserted This signal is the active low output enable for the local bus LBTERM signal When this active low signal is asserted the user application should drive the local data bus which is LD on models with a nonmultiplexed local bus and LAD on models with a multiplexed local bus This signal is an active high early version of Id oe I Functionally Id oe I is obtained by inverting this signal and registering it in a flip flop Applications requiring the best possible clock to output time for the LD or LAD bus can generate their own output enables using this signal This signal informs the PLXDSSM module that the user application is ready to transfer data Asserting ready causes o 1 be asserted on the next cycle assuming that a Direct Slave transfer is in progress This signal informs the PLXDSSM module that the user application wishes to terminate th
481. sing DMA Since there is no file I O to be performed this is a deterministic method of configuring the FPGA As DMA is used to configure the FPGA this method is also the fastest This routine does not allow the FPGA to be partially configured on each call all of the data necessary to configure the FPGA must be supplied in a single call Warning Ensure that Buffer contains valid configuration data for the target FPGA as data transferred this way to the FPGA s SelectMap port cannot be validated by the API The card to be configured is specified by the Card parameter 431 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ConfigureFromBufferDMA The Buffer parameter should point to a buffer containing the configuration data for the FPGA The data must be supplied in a form directly writable to the FPGA s SelectMap port and care should be taken to ensure that the bit ordering of the data is correct The ADMXRC2_LoadBitstream function can be used to obtain SelectMap data in the correct form The Length parameter specifies the number of bytes of configuration data to be written to the FPGA s SelectMap port The Channel parameter specifies which DMA channel should be used for the operation If ADMXRC2 DMACHAN ANY is specified the DMA transfer will be performed on the first available DMA channel However pending DMA transfers on a specific a DMA channel will always be given priority It is possible for a DMA transfer that specifies ADMXRC2 DMACHAN
482. sm2 are required exactly one instance of plxdssm is also required in order to complete the local bus interface The following figure illustrates a plxddsm2 instance connected to the one and only plxdssm instance along with connections to the local bus and backend 272 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm2 CLK RESET clk A 2 HOLD A Replicate gray area for additional demand mode DMA channels see note below decodng ADS note 3 DACK lt 0 gt DMA request control fal note 5 EM plxddsm2 gs r 7n rr eee VV VV LBLAST L Ke ftem LBTERM gt ready stop A control 4 There are a couple of things to note about the above example 3 The generation of qlads causes the plxddsm2 instance to ignore local bus cycles for which the FPGA is not the target or for which are not demand mode DMA cycles This generally requires only the simplest of address decoders and an expression such as dd qlads 0 lt not lads 1 and not ldack 1 0 and not fholda and not 1 23 often suffices The above example uses bit 0 of LDACK to qualify LADS implying that DMA channel 0 is being used If DMA channel 1 were being used the following expression could be used instead dd qlads 1 lt not lads 1 and not ldack l 1 and not fholda and not 1 23 In other words each plxddsm2 instance requires its own qlads signal which should not be
483. source or sink recognizes a particular set of tags Capture edge 10 This signal is normally driven directly by an instance of the component ddrsdram_training_v2 and informs the ddrsdram_port_v2 that training is complete and that normal operation can begin Do readback test 10 This signal is normally driven directly by an instance of the component ddrsdram_training_v2 and instructs the ddrsdram_port_v2 to perform a readback experiment during the training sequence Done readback test 10 This signal is normally connected directly to an instance of the component ddrsdram_training_v2 and informs the ddrsdram training v2 instance that the ddrsdram_port_v2 has completed a readback experiment during the training sequence It qualifies the tstok output Readback test OK 10 This signal is normally connected directly to an instance of the component ddrsdram training v2 and informs the ddrsdram training v2 instance whether or not the most recent readback experiment was successful It is qualified by the tstdone output Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command X4 device select sideband signal 9 This input selects wh
484. specified by the Card parameter The bitstream file to load into the FPGA is specified by the Filename parameter 433 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 ConfigureFromFileDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 ConfigureFromFileDMA Prototype ADMXRC2 STATUS ADMXRC2 ConfigureFromFileDMA ADMXRC2 HANDLE Card const char Filename unsigned int Channel HANDLE Event Arguments Argument Type Purpose Card In Handle of card to configure Filename In Name of BIT file Channel In DMA channel to use for the operation Event In Event to use to wait for completion Return value Value Meaning ADMXRC2 SUCCESS The FPGA was successfully configured ADMXRC2 FILE NOT FOUND The file could not be opened ADMXRC2 INVALID FILE The file appeared not to be a valid bitstream ADMXRC2 NO MEMORY There is not enough free memory to temporarily load the bitstream into memory ADMXRC2 FPGA MISMATCH The device targetted by the bitstream file did not match the device fitted to the card ADMXRC2 INVALID HANDLE Card is not a valid handle to a card ADMXRC2 INVALID PARAMETER An invalid parameter was passed ADMXRC2 NO DMADESC A DMA descriptor could not be allocated Description This function is used to configure the FPGA on a card from a Xilinx bitstream file BIT using DMA If deterministic runtime is required the ADMXRC2 ConfigureFromBuffer or ADMXRC2 ConfigureFromBufferDMA functions should be use
485. sserted 2 If the user application asserts or pulses stop after the cycle in which ready is asserted Ibterm o 1 will be asserted in the next clock cycle In this case it is stop that determines the precise moment at which Ibterm o lis asserted As with ready stop need only be pulsed for as little as one clock cycle in order to take effect Transfer indication This output is asserted on every clock cycle in which data is transferred on the local bus For a bursting local bus cycle this output may be asserted for many consecutive clock cycles Write indication This output is asserted to indicate that the current local bus cycle is a write that is the data is transferred from the local bus master to the local bus slave In a typical FPGA design there is exactly one instance of plxdssm It provides the control mechanism that enables the FPGA to respond to local bus cycles but does not provide the datapath A typical usage scenario is presented in the following figure CLK LRESET LA 2 FHOLDA LaDS LBLAST LBTERM LWRITE LRE AD Y 277 latched address Primary address decoding note 1 E a ready stop control Registers outbound local bus data registered inbound local bus data fyc mb mv imis ime lanal hinia bite mole artius leh ADM XRC SDK 4 9 3 User Guide Win32 plxdssm ak registered inbound local bus byte enables active low L
486. st Max characters including the NULL terminator are written to Buffer 467 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SyncDirectMaster ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 SyncDirectMaster Prototype ADMXRC2 STATUS ADMXRC2 SyncDirectMaster ADMXRC2 HANDLE Card ADMXRC2 DMADESC DMADesc unsigned long Offset unsigned long Length ADMXRC2 SYNCMODE Mode Arguments Argument Type Purpose Card In Handle of card DMADesc In A DMA descriptor identifying a buffer Offset In Offset of region within buffer to sync Length In Region within buffer to sync Mode In The kind of synchronisation to perform Return value Value Meaning ADMXRC2 SUCCESS The buffer region was successfully synchronized ADMXRC2 INVALID HANDLE Card was not valid ADMXRC2 INVALID DMADESC DMADesc was not a valid DMA descriptor ADMXRC2 INVALID PARAMETER Mode was not valid or Offset and Length were out of bounds Description The ADMXRC2 SyncDirectMaster function serves the purpose of ensuring that coherency is maintained in hardware level buffers and caches when the FPGA accesses host memory in direct master mode Proper use of this function ensures that e data written to memory by the CPU has propagated through all caches write buffers and bridges so that the changes are visible to the FPGA and e data written to memory by the FPGA using Direct Master access has propagated through all cach
487. stuck at 0 1 or shorted to other signals 6 Random data written to memory for detecting pattern sensitive failures The 64 option causes the application to operate the local bus in 64 bit mode This is valid only for models that support a 64 bit local bus A subset of the memory banks on a card can be tested by passing a bitmask of banks to test via the banks option For example banks 0xD would specify that only banks 0 2 and 3 should be tested The local bus clock frequency used for the memory test can be specified on the command line using the Iclk option For example Iclk 45 specifies a local bus clock frequency of 45 MHz If the Iclk option is not specified on the command line the MemoryF application programs a sensible default frequency for the model on which the application is run into the local bus clock generator For example the default LCLK frequency when running MemoryF on an ADM XRC II is 66 MHz By default the MemoryF application programs the MCLK clock generator to an appropriate frequency for the memory clock domain This may be changed on the command line using the mclk option although it is advisable that the user understands the relationship between the freqency at the target FPGA s MCLK pin i e what is programmed into the clock generator and the frequency of the internal clock within the FPGA For example with an ADM XRC 4FX card passing the option mclk 210 on the command line would result in the DDR II SDRA
488. t asserts the port plast signal once per 4 cycles in which mem adv is asserted This ensures that each 128 bit word of logical memory data corresponds to 4 32 bit words on the local bus mem q carries data read from memory to the local bus interface mem re asserted by the memory banks module when the async port instance selected by sel bank 1h has no data remaining in its FIFO This signal is used by the local bus interface to hold off the local bus LREADY signal until data has been fetched from memory mem rpe asserted by the memory banks module when the async port instance selected by sel bank 1h is running out of data in its FIFO This signal is used by the local bus interface to terminate the current burst on the local bus in order to avoid undefined data being read by the CPU Explanation of memory banks module memory arbitration The final figure in this discussion shows how each memory port is shared between the local bus interface represented by an async port and the user app module with reference to the ADM XRC 4FX 123 ADM XRC SDK 4 9 3 User Guide Win32 Memory Loca bus dock domain Memory user dock domain memory configuration and status registers in local bus interface MODE register for memory bank i 32 asynda porti memclk arbiter 2 ort sredi port USE port pcwi ort ptem i port s ddr2sdram port ort port sat 30 port sto port p
489. t ZBT64 Memtest 80 Purpose Measures approximate frequencies at the clock input pins of a reconfigurable computing card Demonstrates clock doubling using Virtex DLLs and Virtex Il DCMs Demonstrates use of the DMA engines in demand mode with bursting on the local bus Demonstrates use of the DMA engines in demand mode with bursting and 64 bit mode on the local bus A trivial design that walks a 1 bit up the front panel I O pins Sample logic for generating FPGA interrupts Demonstrates how to implement a direct master capability in an FPGA design A reference design featuring an interface to the onboard memories that permits access by both the CPU via a 32 bit local bus and a processing block within the FPGA A reference design featuring an interface to the onboard memories that permits access by both the CPU via a 64 bit local bus and a processing block within the FPGA A trivial design that walks a 1 bit up the rear panel I O pins Demonstrates how to implement host readable registers Demonstrates how to implement host readable registers with 64 bit local bus interface Demonstrates host access to the ZBT SSRAM Demonstrates host access to the ZBT SSRAM with 64 bit local bus interface ADM XRC SDK 4 9 3 User Guide Win32 Clock ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Clock sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source
490. t to the memory device s inout Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together into the rc bus so that for the most part the user application need not care what they are Refer to note 2 for the mapping of the rc bus to device pins ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v2 rd inout Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via ce two words are transferred on rd which determines the relationship between the rd width and d with parameters Refer to note 3 for details Performance This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal Most of the time the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application Certain usage patterns however may result in a accumulated backlog in the command buffer There is one performance penalty in this memory port e Turning the rd bus around when a read command and a write command are entered in consecutive clock cycles requires one clkO cycle Thus it incurs one cycle performance penalty This penalty occurs only if a write command is entered in the one cycle window following entry of a read command Latency for r
491. t 2001 2009 Alpha Data ADMXRC BUFFERMAP Declaration typedef struct ADMXRC BUFFERMAP nsigned long MaxPages nsigned long PagesPci nsigned long PageLength nsigned long PageBits nsigned long PagesSpanned nsigned long BytesSpanned unsigned long InitOffset ADMXRC BUFFERMAP GG o t Gu Description The ADMXRC_BUFFERMAP structure is filled in by ADMXRC MapbDirectMaster with a scatter gather map of an application buffer The first two members are always initialized by the application e The PagesPci member must point to an application supplied array of unsigned long This array is filled in with the PCI addresses of pages making up the application buffer e The MaxPages member must be initialized to the maximum number of pages that the PagesPci member points to The other five members are filled in by ADMXRC_MapDirectMaster e The PageLength member is the length of a page of physical memory for information purposes For the x86 architecture this value is 4096 e The PageBits member is the number of address bits in a page offset For the x86 architecture this value is 12 e The PagesSpanned member is the number of pages of physical memory spanned by the PagesPci array e The BytesSpanned member is the number of bytes of physical memory spanned by the PagesPci array and takes InitOffset into account e The InitOffset member is the offset within the first mapped page of the beginning of the r
492. t any time When the local bus interface reads a memory bank the mem signals work as follows e mem ce pulsed by the local bus interface for one clock cycle at the beginning of a burst when the local bus interface wants to access a memory bank whether for a read or for a write e mem a qualified by mem ce and carries the starting address in terms of 64 bit words in memory that the local bus interface wishes to access e mem cw qualified by mem ce and is deasserted by the local bus interface for a read access e mem term pulsed by the local bus interface for one clock cycle to terminate the burst e mem adv when asserted by the local bus interface indicates that the next 64 bit word of data should be presented on mem q This signal enters the instance For the case of the ADM XRC 4FX port asserts the port plast signal once per 2 cycles in which mem adv is asserted This ensures that each 128 bit word of logical memory data corresponds to 2 64 bit words on the local bus e mem q carries data read from memory to the local bus interface e mem re asserted by the memory banks module when the async port instance selected by sel bank 1h has no data remaining in its FIFO This signal is used by the local bus interface to hold off the local bus LREADY signal until data has been fetched from memory e mem rpe asserted by the memory banks module when the async port instance selected by sel bank 1h is running
493. t asserts valid the qtag output reflects the tag value originally passed This is intended to facilitate sharing of a memory port between several data sources or data sinks where each source or sink recognizes a particular set of tags valid out Read data valid When the memory port asserts valid it does so as a result of a read command user code asserted ce with w deasserted When valid is asserted both q and qtag are valid w in Write select When user code asserts ce it must place either a logic 1 on the w signal in order to select a write command or 0 in order to select a read command Notes 5 The phase and frequency relationships between the four clock phases are illustrated by the following figure P clk45 eiczx dkzxa T Also shown is the DDR II SSRAM clock Its frequency is the same as clkO but its phase is indeterminate 6 For correction operation all sideband inputs must be static while the memory port is not idle The signals of this interface to and from the memory device s are as follows Signal Type Function ra in Memory device address bus This bus carries address information to from the memory port to the memory device s ADM XRC SDK User Guide Common Memory Ports rc inout Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together
494. t be inadvertantly overwritten by demand mode DMA transfers as the design qualifies FPGA register accesses using LDACK 1 0 Inbound count register ICOUNT local bus address 0x0 Bits Mnemonic Type Function 1 0 MBZ 31 2 N WO Inbound DMA transfer count in 32 bit words The inbound count register ICOUNT specifies how many words will be transferred in the next DMA transfer in channel 0 in order to transfer data into the FPGA s FIFO When ICOUNT N is zero the FPGA will not assert LDREQ 0 The FPGA decrements ICOUNT N whenever a word of data is transferred on DMA channel 0 Outbound count register OCOUNT local bus address 0x4 Bits Mnemonic Type Function 1 0 MBZ 31 2 N WO Outbound DMA transfer count in 32 bit words The outbound count register OCOUNT specifies how many words will be transferred in the next DMA transfer in channel 1 in order to transfer data into the FPGA s FIFO When OCOUNT N is zero the FPGA will not assert LDREQ 1 The FPGA decrements OCOUNT N whenever a word of data is transferred on DMA channel 1 Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with ddma xrc v scr ddma xrc v prj ddma xrc ucf Virtex 170 ADM XRC SDK 4 9 3 User Guide Win32 DDMA ADM XRC with ddma xrc ve scr Virtex E ADM XRC P with ddma xrcp v scr Virtex ADM XRC P with ddma xrcp ve
495. t must specify the appropriate mode when performing DMA transfers This is demonstrated by the DMA sample application 169 ADM XRC SDK 4 9 3 User Guide Win32 DDMA e Data is read from host memory using DMA channel 0 in demand mode An instance of the PLXDDSM module controls the DMA channel e Data is written to host memory using DMA channel 1 in demand mode An instance of the PLXDDSM module controls the DMA channel e A 512 word by 32 bit FIFO is used to buffer data e Bursting is allowed on the local bus e Flow control is implemented by holding off the demand mode DMA request signals LDREQ 1 0 when the FIFO is nearly full or nearly empty FPGA Space Usage The design assumes that any DMA transfer on DMA channel 0 is transferring data into the FIFO hence any direct slave write where LDACK 0 is asserted will fill the FIFO with data Similarly any DMA transfer on DMA channel 1 is assumed to tbe emptying the FIFO hence any read where LDACK 1 is asserted will empty the FIFO of data The local bus address is ignored during these demand mode DMA transfers In other words the FIFO is visible over the entire FPGA space during demand mode DMA transfers There are two write only registers that reside in the FPGA direct slave space These registers must be written by the host with a DMA transfer count that matches the size of the DMA transfer being performed prior to the host starting the DMA transfer Note that these registers canno
496. t training This is in the order of 150 microseconds of simulation time at a clkO frequency of 133MHz Certain properties of a DDR II SDRAM device such as number of row and column address bits might not be known at the time of building an FPGA design Therefore this memory port allows certain properties to be specified at runtime An application might interrogate some Vital Product Data in order to determine the proper values to drive on the row col bank and pbank signals Alternatively if the designer can guarantee that the properties of the DDR II SDRAM devices are known when building the FPGA design these signals can be driven with constant values This has the advantage of lower slice utilization In any case for reliable operation these signals must not change unless the memory port is idle The purpose of these signals should not be confused with that of the pinout parameter The pinout parameter specifies properties of the circuit board on which the FPGA and DDR II SDRAM devices are mounted In general the number of physical wires on the circuit board provided for addressing the DDR II SDRAM devices can be greater than the number actually used by a particular DDR II SDRAM device The phase and frequency relationships between the four clock phases are illustrated by the following figure Also shown is the DDR II SDRAM clock CK Its frequency is the same as clk2x0 but its phase is indeterminate 8 For correction operatio
497. tag and qtag respectively The signals of this interface to and from the user application are as follows Signal Type a in be in ce in 282 Function Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as an array of words of width d width this address is a logical address because the address that eventually appears on the ra bus may not necessarily be the same as whatever user code placed on the a bus Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory Command entry User code asserts this signal to enter a new read or write command into the memory port When asserted a and w must be valid When asserted along with w tag must also be valid User code must not assert ce when ready is deasserted Other than that there are no restrictions on how few or how many clock cycles ce can remain asserted It can be pulsed for single cIkO cycles or asserted for many clkO cycles ready permitting The address byte enables tag etc of a command need not bear any relationship to that of the previous command but for some memory types it may be beneficial for performance to avoid certain p
498. tantiating ddr2sram training v2 the value of the num port parameter is the number of instances of ddr2sram port v2 whose training will be controlled by that instance of ddr2sram training v2 Signals The signals of this interface to and from the user application are as follows Signal Type Function Note cedge in Capture edge This should be connected directly to the cedge ports of one or more instances of ddr2sram port v2 and carries information about how to retime data captured using the clkcO and clkc180 clocks into the memory ports user interface clock domain clk in Clock 2 3 All ports except rst clkc clkcO and clkc180 are synchronous to clk clkc in Capture clock in 4 This clock is used to generate the two capture clock phases clkcO and clkc180 clkcO out Capture clock phase 0 4 This clock should be connected directly to the clkcO ports of one or more instances of ddr2sram port v2 and is used to clock data read from the DDR II SSRAM devices into the FPGA s IOBs clkc180 out Capture clock phase 180 4 This clock is the same frequency as clkcO but 180 degrees out of phase and should be connected directly to the clkc180 ports of one or more instances of ddr2sram port v2 It is used to clock data read from the DDR II SSRAM devices into the FPGA s IOBs rst in Asychronous reset Asserting this signal returns the module to its default state so that it will begin the training sequence when rst is deasserted This port
499. tda1 vb5sxt pr xrcbtda1 memory DA1 with V5SXT xrcbtda1 ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav xrc lt device gt ADM XRC P projnav xrcp lt device gt ADM XRC II Lite projnav xrc2l lt device gt ADM XRC II projnav xrc2 lt device gt ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt ADM XRC 4LX projnav xrc4lx lt device gt ADM XRC 4SX projnav xrc4sx lt device gt ADM XRC 4FX projnav xrc4fx lt device gt ADPE XRC 4FX projnav xrce4fx lt device gt ADM XRC 5LX projnav xrc5 x lt device gt ADM XRC 5T1 projnav xrc5t1 lt device gt ADM XRC 5T2 projnav xrc5t2 lt device gt ADM XRC 5T2 ADV ADM XRC 5TZ projnav xrc5tz lt device gt ADM XRC 5T DA1 projnav xrc5tda1 lt device gt Modelsim scripts Example Modelsim compatible script files for simulating this design are provided First change directory to where this design is located and then refer to the following table for the appropriate shell commands for a particular model These simulations make use of behavioural memory models supplied by Micron and Hynix These models are available from the websites of the respective vendors but for legal reasons Alpha Data does not supply these models with this SDK The models in question are e MT55L256L36F Micron flowthrough ZBT SSRAM e MT55L512L18P Micron pipelined ZBT SSRAM e MT55L256L36P Micron
500. te command line for a particular model 84 ADM XRC SDK 4 9 3 User Guide Win32 Clock Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 85 Shell command vsim do do clock xrc do vsim do do clock xrc do vsim do do clock xrc do vsim do do clock xrc do vsim do do clock xpl do vsim do do clock xpl do vsim do do clock wrc2 do vsim do do clock drc2 do vsim do do clock xpi do vsim do do clock xrc4lx do vsim do do clock xrc4lx do vsim do do clock xrc4fx do vsim do do clock xrce4fx do vsim do clock xrc5lx do vsim do do clock xrc5t1 do vsim do do clock xrc5t1 do vsim do do clock xrcbt1 do vsim do do clock xrcbtda1 do ADM XRC SDK 4 9 3 User Guide Win32 DDMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DDMA sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV ve
501. te commands may also have the same effect The architecture of DDR SDRAM device consists of a number of internal banks which are in turn divided into a number of pages At any moment a given bank may be closed or may have a given page open Opening or closing a bank takes a finite number of clock cycles In this memory port the following performance penalties exist for memory accesses falling into the following patterns e Several clkO cycles for changing from read to write or write to read within the same page and bank e In the order of 8 clkO cycles for consecutive accesses that fall within different pages of the same bank or within different banks e In the order of 8 20 cIkO cycles for an access that occurs while the memory port is performing a refresh Latency for read commands is nondeterministic due to the penalties described above particularly because of the need to refresh but the best case latency from entry of a read command ce asserted with w deasserted to valid asserted is approximately 11 cIkO cycles This can be modified somewhat by tightening or relaxing the timing as specified by the timing parameter Worst case latencies may be computed by adding the above penalties to the best case latency The optimal usage pattern for this memory port is blocks of accesses of the same type read or write to the same bank and page A linearly incrementing address is an example of an optimal usage pattern When used optimally this m
502. ted training successfully otherwise 0 Reserved This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 This field returns 1 in a bit position if the corresponding DDR II SSRAM port has completed training successfully otherwise 0 Reserved This field returns a 1 in a bit position if the corresponding DDR II SDRAM port has completed training successfully otherwise 0 This field returns 1 if a bit position if the corresponding DDR II SSRAM port has completed training successfully otherwise 0 Reserved Memory bank mode registers MODEO MODE15 local bus address 0x40 0x7C There are a total of 16 MODE registers occupying local bus addresses 0x40 to 0x7C inclusive The interpretation of the fields in a mode register depends upon the type of memory that the register corresponds to ZBT SSRAM Bits Mnemonic Type 0 PIPELINE R W 31 1 MBZ DDR II SSRAM Bits Mnemonic Type 0 BLEN R W MBZ 2 DLLOFF R W 31 3 MBZ DDR SDRAM Bits Mnemonic Type 0 REG R W 114 Function When this field is 0 the memory port expects the ZBT SSRAM to be operating in flowthrough mode When this field is 1 the memory port expects the ZBT SSRAM to be operating in pipelined mode Reserved Function When this field is 0 the memory port expects the DDR II SSRAM device to be a burst length 2 device When this field is 1 the memory port expects the D
503. ter xrcp ve pr master xrcp ucf Virtex E ADM XRC Il Lite master xrc2l v2 scr master xrc2l v2 prj master xrc2l ucf ADM XRC II master xrc2 v2 scr master xrc2 v2 prj master xrc2 ucf 184 ADM XRC SDK 4 9 3 User Guide Win32 Master Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC P projnav rcp device ADM XRC II Lite projnavrc2l device ADM XRC II projnav xrc2 lt device gt 185 ADM XRC SDK 4 9 3 User Guide Win32 RearIO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data RearlO sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location ADMXRC_SDK4 fpga verilog reario Synopsis FPGA Space Usage The RearlO design does not have a local bus interface thus there are no registers defined in the FPGA space 186 ADM XRC SDK 4 9 3 User Guide Win32 RearlO Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file
504. tered on ce Hence a width for this configuration should be at least 25 When a width is larger than actually required the top few unused bits of a are ignored by the memory port In practice one should determine the value of a width assuming that the largest possible memory devices are in use The signals of this interface to and from the user application are as follows Signal 11 Type Function Note ADM XRC SDK User Guide Common Memory Ports a bank be ce clkO clk90 clk180 clk270 col 12 in in in Logical address User code must place a valid address on a when it asserts ce Since a memory port effectively represents a memory device as a linear array of words of width d_width this address is a logical address rather than anything resembling what one might see on the ra bus Bank address width select sideband signal 6 8 This input selects number of internal bank address bits for the DDR SDRAM devices in use 00 gt no internal bank address bits 01 2 1 internal bank address bits 10 gt 2 internal bank address bits 11 gt 3 internal bank address bits Byte enables to memory User code must place valid byte enables on be whenever a write command is entered ce and w both asserted A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while a zero means that the corresponding byte will not be written to memory Command entry
505. that has been initiated by one of the PCI to local bus bridge s DMA engines in order to prematurely terminate a DMA transfer before the requested number of bytes has been transferred To use LEOT a DMA engine must be operating in LEOT mode ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Model specific signals While the local bus protocol is in general the same in each of the models in Alpha Data s reconfigureable computing range in earlier models such as the ADM XRC some signals in the generic model of the local bus are actually two different signals that driven by the FPGA and the local bus bridge respectively The function of these signals however is the same This section details the differences between the models of the XRC range ADM XRC and ADM XRC P ADM XRC I Lite ADM XRC II ADM XPL ADM XP and ADP XPI ADP WRC II and ADP DRC II ADM XRC 4LX and ADM XRC 4SX ADM XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 and ADM XRC 5T2 ADV ADM XRC 5TZ and ADM XRC 5T DA1 ADM XRC and ADM XRC P The following figure shows the connections between the PCI9080 local bus bridge and the FPGA in an ADM XRC or ADM XRC P card 218 ADM XRC SDK 4 9 3 User Guide Win32 Model specific signals LHOLD A FHOLDA central resource LCLK LINTI FIM Tl LRE SET LADS 3 0 9080 LATE RM LETER MOH LRE amp D 12 LREAD Yos
506. the ADMXRC_InstallErrorHandler function does not result in any currently installed handler function being called The error handler function is always called just before the API function generating the error returns When the error handler is called FunctionName will point to a NULL terminated string containing the name of the API function which failed and Code will contain the error code Due to the multithreaded nature of the API mutual exclusion is enforced when the error handler is installed or called When the error handler is installed the API attempts to take a Win32 Mutex object waiting for at most 1000 milliseconds for the wait to succeed If the mutex wait fails due to timeout ADMXRC InstallErrorHandler returns ADMXRC FAILED 525 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC InstallErrorHandler When the API calls the user specified error handler the API attempts to take the same mutex in order to prevent the error handler being entered in a reentrant fashion Therefore the error handler routine should e Avoid taking an excessive period of time to execute as this will delay the calling of the error handler for other threads e Avoid calling API functions that may result in the error handler routine being called reentrantly as this may cause the thread to hang 526 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC LoadFpgaFile ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC LoadFpgaFile P
507. the application does nothing different apart from configuring the FPGA local bus space to operate in 64 bit mode see ADMXRC2_SetSpaceConfig and specifying 64 bit operation when calling ADMXRC2 BuildDMAModeWord 49 ADM XRC SDK 4 9 3 User Guide Win32 EPTest ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data EPTest utility WARNING Care should be exercised when using EPTest Modifying certain locations may render the card inoperative The utility does not by default allow EEPROM locations used to store the adapter PCI configuration to be changed Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview EPTest is a utility that allows modification of the nonvolatile configuration memory of a reconfigurable computing card Care should be exercised because this memory generally contains Vital Product Data as reported by the Info utility Overwriting the memory with invalid data may render a card inoperable Should you wish to modify the Vital Product Data of your card the format of the configuration memory is available on request from support alpha data com Syntax eptest options 50 ADM XRC SDK 4 9 3 User Guide Win32 EPTest location location value eptest opti
508. the counter once per second displaying the difference between the current and last readings Syntax dll options frequency Options Option Argument type Meaning card base 10 integer ID of card to open index base 10 integer Index of card to open 46 ADM XRC SDK 4 9 3 User Guide Win32 DLL FPGA Design The DLL sample application makes use of the DLL sample FPGA design Verilog VHDL 47 ADM XRC SDK 4 9 3 User Guide Win32 DMA ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data DMA sample application Model support Model ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC I ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Overview Supported The DMA sample application demonstrates demand mode DMA transferring data to the target FPGA and back into CPU memory in a loopback operation Syntax dma options Options Option Argument type card base 10 integer index base 10 integer Telk real number eize base 10 integer 48 Meaning ID of card to open Index of card to open Local bus clock frequency to use in MHz default 33 0 Size of data blocks to transfer in bytes must be a multiple of 4 default 65536 ADM XRC SDK 4 9 3 User Guide Win32 DMA 64 Operate local bus in 32 bit mode default 64 Operate local bus in 64 b
509. the memory port it must be zero The delay from deassertion of reset to completion of training trained asserted may be as long as 350ms This is because a large post reset delay is used in order to ensure that the memory port properly initializes the DDR SDRAM devices that it is controlling after power on For simulation however the memory port uses a much smaller post reset delay with the result that the delay from deassertion of reset to completion of training is dominated by the time spent training This is in the order of 150 microseconds of simulation time at a clkO frequency of 133MHz Certain properties of a DDR SDRAM device such as number of row and column address bits might not be known at the time of building an FPGA design Therefore this memory port allows certain properties to be specified at runtime An application might interrogate some Vital Product Data in order to determine the proper values to drive on the row col bank and pbank signals Alternatively if the designer can guarantee that the properties of the DDR SDRAM devices are known when building the FPGA design these signals can be driven with constant values This has the advantage of lower slice utilization In any case for reliable operation these signals must not change unless the memory port is idle The purpose of these signals should not be confused with that of the pinout parameter The pinout parameter specifies properties of the circuit boar
510. tio xrc2l v2 scr frontio xrc2l v2 prj frontio xrc2l ucf ADM XRC II frontio xrc2 v2 scr frontio xrc2 v2 prj frontio xrc2 ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC projnav re device ADM XRC I Lite projnavrc2l device ADM XRC II projnav xrc2 lt device gt 100 ADM XRC SDK 4 9 3 User Guide Win32 ITest ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ITest sample VHDL FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Modelsim scripts Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Note the ADM XRC 5T2 ADV version of this design uses the same source files and bitstreams as the ADM XRC 5T2 so separate files are not included within this SDK Location SADMXRC_SDK4 fpga vhdl itest Synopsis 101 ADM XRC SDK 4 9 3 User Guide Win32 ITest The ITest FPGA design implements logic for generating FPGA interrupts on the host The scheme used is explained in application note AN XRCO06 which can be found the doc directory of this SDK The ITest sample application shows how to capture and handle FPGA
511. to operate The type of FPGA fitted to a card can be obtained from the ADMXRC CARD INFO structure returned by ADMXRC GetCardlnfo 564 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC HANDLE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC_HANDLE Declaration typedef HANDLE ADMXRC_HANDLE e Description An ADMXRC_HANDLE is a handle to a card in a system Most API functions require a parameter of type ADMXRC_HANDLE in order to identify the card on which the operation is to be performed The ADMXRC_OpenCard and ADMXRC_CloseCard functions open and close card handles 565 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC HANDLER FUNCTION ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC HANDLER FUNCTION Declaration typedef void ADMXRC HANDLER FUNCTION const char FnName ADMXRC STATUS Status Description An ADMXRC HANDLER FUNCTION function is an application defined error handler routine called when an API function fails for some reason The routine must be installed or uninstalled using ADMXRC InstallErrorHandler 566 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC IMAGE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC IMAGE Declaration typedef void ADMXRC IMAGE e Description An ADMXRC_IMAGE variable holds a Xilinx bitstream file BIT loaded from disk ADMXRC_LoadFpgaFile and ADMXRC_UnloadFpgaFi
512. to provide a complete local bus interface with the capability to perform demand mode DMA qlads Iblast to from Local Bus to from Ibterm pins user Idrea o I application plxddsm HDL source code Projects making use of this component must include all of the following source files relative to root of SDK installation fpga vhdl common localbus localbus pkg vhd fpga vhdl common localbus plxddsm vhd Signals The signals of this interface to and from the user application are as follows Signal Type Function Note clk in Local bus clock This port must be driven by the clock that drives the local bus interface of the FPGA design 266 ADM XRC SDK 4 9 3 User Guide Win32 plxddsm deprecated idle Iblast Ibterm Idreq o glads ready request rst Sr 267 out in in Interface idle This status output indicates whether or not the plxddsm instance is currently handling a demand mode DMA local bus cycle It may be asserted for two reasons 1 There is no cycle in progress on the local bus 2 There is a cycle in progress on the local bus but the qlads signal was not asserted at the beginning of the cycle meaning that the FPGA determined that it was not the target of a demand mode DMA local bus cycle LBLAST in This input must be driven by an active high version of the LBLAST signal from the local bus LBTERM in This input must be driven by an active high version of the LBTERM sign
513. to select BL4 incur a one cycle performance penalty However when burst len is driven with 0 to select BL2 this performance penalty does not apply e Turning the rd bus around when a read command and a write command are entered in consecutive clock cycles requires one clkO cycle Thus it incurs a one cycle performance penalty This penalty occurs only if a write command is entered in the one cycle window following entry of a read command Latency for read commands is fairly deterministic since the penalties described above are limited to one cycle although these penalties may be accumulated by successive commands The best case latency from entry of a read command ce asserted with w deasserted to valid asserted is approximately 9 clkO cycles Worst case latencies may be computed by adding the above penalties to the best case latency The optimal usage pattern for this memory port is blocks of accesses of the same type read or write with addresses that increment by one on each successive access When used optimally a 32 bit wide DDR II SSRAM memory port operating at a clkO frequency of 133MHz can sustain approximately 1GB s ADM XRC SDK User Guide Common Memory Ports ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data The ddrsdram port component Overview HDL source code Parameters Signals Row column address selection Performance Overview The ddrsdram port component is part of the memif package a
514. to transfer Address of beginning of transfer on local bus Direction of DMA transfer DMA channel to use for the transfer Mode word to use for the DMA transfer Miscellaneous flags Timeout for DMA transfer Event to use to wait for completion Meaning The DMA transfer was performed successfully Card is not a valid handle to a card An invalid parameter was passed Could not begin DMA immediately as requested A DMA descriptor could not be allocated This function behaves as a call to ADMXRC2 SetupDMA followed by a call to ADMXRC2 DoDMA followed by a call to ADMXRC2 UnsetupDMA 438 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 DoDMAImmediate The Buffer and Length parameters effectively replace the DmaDesc Offset and Length parameters from ADMXRC2 DoDMA in specifying the region of application memory over which the DMA transfer takes place The other parameters Local Direction Channel DMAModeWord Flags Timeout and Event all function in the same way as in ADMXRC2 DoDMA This function cannot guarantee deterministic runtime as the process of locking down a user buffer using ADMXRC2 SetupDMA may require disk I O for the operating system to make all pages of a user buffer resident in physical memory 439 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 GetBankInfo ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha ADMXRC2 GetBanklnfo Prototype ADMXRC2 STATUS Data ADMXRC2 GetBankInfo ADMXRC2
515. ts of the pinout parameter Therefore ra width is the sum of these two values The following figure illustrates this for the case where num addr bits 13 and num bank bits 2 Bank address Rowe calumn address BA pins A pins EM 4 oh vO 2 7 615 4s 2 t 0 1 4 0 Note that ra width and pinout are properties of the printed circuit board indicating how many wires are physically present On the other hand the DDR SDRAM devices actually fitted to the printed circuit board may have less pins connected The purpose of the row col bank and pbank signals is to specify at runtime the properties of the DDR SDRAM devices actually in use 325 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram port v2 Signals 2 The memory device control bus rc is composed of various fields in this memory port with the widths of certain fields specified by the pinout and rd width parameters The following figure illustrates an example that puts rc width at 17 Widths are Widths are pinout ck_vidth rd eith 3 M _ _ 161514151211 6 6 5 4 3 1211 0 pos DW width pinaut cke width width 1 CASH width 1 RASH width 1 CSE width pinout oum_phys_bank The order of the fields within rc is always the same only the field widths may differ from one model to another The rd_width parameter is the number of physical DQ wires making up the data bus of the DDR SDRAM ba
516. ts on each clock cycle For example a DDR memory that is 64 physical bits wide is treated logically as a 128 bit wide memory The Size member gives the number of logical memory locations in the bank counted in words not bytes This value is 2 where n is the number of address lines used by the bank 478 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 BUFFERMAP ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 BUFFERMAP Declaration typedef struct ADMXRC2 BUFFERMAP unsigned long MaxPages DWORD PagesPci nsigned long PageLength nsigned long PageBits nsigned long PagesSpanned nsigned long BytesSpanned unsigned long InitOffset ADMXRC2 BUFFERMAP EGE Description The ADMXRC2_BUFFERMAP structure is filled in by ADMXRC2_MapDirectMaster with a scatter gather map of an application buffer The first two members are always initialized by the application e The PagesPci member must point to an application supplied array of unsigned long This array is filled in with the PCI addresses of pages making up the application buffer e The MaxPages member must be initialized to the maximum number of pages that the PagesPci member points to The other five members are filled in by ADMXRC2 MapbDirectMaster e The PageLength member is the length in bytes of a page of physical memory For example in the x86 architecture this member is 4096 e The PageBits member is the
517. uction to the local bus Multiplexed address data on local bus Supported data widths on local bus PCI to local bus bridge Feature FPGA technology Memory technology Max local bus frequency Multiplexed address data on local bus Supported data widths on local bus PCI to local bus bridge Feature FPGA technology Memory technology Max local bus frequency Multiplexed address data on local bus Supported data widths on local bus PCI to local bus bridge Yes 32 bits 64 bits Virtex ll ADM XRC 4SX Virtex 4 SX ZBT SSRAM 66 67MHz No 32 bits PCI9656 ADM XRC 5LX Virtex 5 LX DDR II SDRAM 80 0MHz Yes 32 bits 64 bits Virtex 4 LX Yes 32 bits 64 bits Virtex ll ADM XRC 4FX Virtex 4 FX DDR II SDRAM 80 0MHz Yes 32 bits 64 bits Virtex 4 LX ADM XRC 5T1 Virtex 5 LXT Virtex 5 SXT DDR II SDRAM DDR II SSRAM 80 0MHz Yes 32 bits 64 bits Virtex 4 LX No 32 bits PCI9656 ADPE XRC 4FX Virtex 4 FX DDR II SDRAM 80 0MHz Yes 32 bits 64 bits Virtex 4 FX PCI Express ADM XRC 5T2 Virtex 5 FXT Virtex 5 LXT Virtex 5 SXT DDR II SDRAM DDR II SSRAM 80 0MHz Yes 32 bits 64 bits Virtex 4 LX Note 1 If logic revision from INFO utility is 1 2 or greater max LCLK frequency is 80MHz otherwise 66 67MHz Click on one of the following topics for more information Local bus signals Direct slave transfers DMA transfers Arbitration
518. uests access to the memory port the favored client will be granted access to the memory port regardless of the value of latency and regardless of any unfavored clients 5 The ready delay parameter specifies the timing relationship between a client s readyi signal and its cei signal ready delay must be at least 0 and no greater than 4 The following figures illustrate this relationship req access granted here by arbiter access lost here readyO earliest possible assertion latest possible deassertion of cel of ce Relationship between readyO and ce0 when ready delay 0 req access granted here by arbiter access lost here readyO earliest possible assertion latest possible deassertion of ce of cel Relationship between readyO and when ready delay 1 302 ADM XRC SDK 4 9 3 User Guide Win32 arbiter 3 req access granted here by arbiter access lost here readyO i earliest possible assertion latest possible deassertion of of ce Relationship between readyO and ce0 when ready delay 2 6 If the registered parameter is false the memory port output signals ce w etc are generated combinatorially from the client port input signals w0 ce1 w1 etc If the registered parameter is true the memory port output signals ce w etc are registered
519. ui 45 mem a 31 2 mercik 2x0 00841 rep d 28 port she port memclk a0 SDRAM tins port pati port seg arb ce i s port svalid ce port pw e seh A ra d port pre i arb tag i t port prpe i arb di J TS arb Gc 128 arb user redi ew arb user wi arb ready ab user tag to from user di client 1 meo user app 28 user be port CA bark 16 use di 128 user qtag i 0 user validi user ready trained Detail of logic for sharing a memory bank within the memory banks module In the above figure only the logic for a single memory bank is shown but each memory bank has an identical set of logic consisting of an async port an arbiter 2 and a ddr2sdram port There are a number of generic signals that work in the same way regardless of the type of memory to which the memory port interfaces These signals work as follows e The ce signal instructs the memory port to perform an access to the memory devices In each clock cycle that ce is asserted one command is issued to the memory port e The w signal is qualified by ce and specifies whether a memory access should be a read 0 or a write 1 124 e The a signal is qualified by ce and specifies the word of memory that should be accessed This address is not a byte address rather it should be considered to be an index into an array of wo
520. uide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 CARDID Declaration typedef unsigned long ADMXRC2 CARDID Description A value of type ADMXRC2 CARDID identifies a particular card a system and is used primarily with the ADMXRC2 OpencCard function 489 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 DMADESC ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 DMADESC Declaration typedef unsigned long ADMXRC2 DMADESC Description A value of type ADMXRC2 DMADESC is a DMA descriptor representing a locked down non swappable application buffer DMA descriptors are allocated and freed by ADMXRC2 SetupDMA and ADMXRC2 UnsetupDMA They are used with the ADMXRC2 DoDMA ADMXRC2_DoDMAImmediate ADMXRC2 MapbDirectMaster and ADMXRC2 SyncDirectMaster functions 490 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 DMADIR ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 DMADIR Declaration typedef enum ADMXRC2 DMADIR ADMXRC2 PCITOLOCAL ADMXRC2 LOCALTOPCI ADMXRC2 DMADIR Description The ADMXRC2 DMADIR enumerated type specifies the direction of data transfer in a DMA transfer for the ADMXRC2 DoDMA and ADMXRC2 DoDMAlImmediate functions It is one of the following values Value Meaning ADMXRC2 PCITOLOCAL Data is transferred from host to FPGA ADMXRC2 LOCALTOPCI Data is transferred from FPGA to host 491 ADM XRC SDK 4 9
521. umber of chip select pins in the memory bank 0x0 gt 1 physical bank 0x1 gt 2 physical banks 0 2 gt 4 physical banks 0x3 gt 8 physical banks 31 10 MBZ DDR II SDRAM Bits Mnemonic Type Function 0 R W This field is reserved for implementing registered DDR II SDRAM support must be zero in this release of the SDK 1 MBZ This field is reserved for implementing X4 DDR II SDRAM device support must be zero in this release of the SDK 3 2 ROWS R W This field specifies the number of row address bits in the DDR II SDRAM devices 0x0 gt 12 bits 0x1 gt 13 bits 0x2 gt 14 bits 0x3 gt 15 bits 5 4 COLS R W This field specifies the number of column address bits in the DDR II SDRAM devices The number of column address bits depends on this field and also the ROWS field as follows 0x0 gt rows 4 0x1 gt rows 3 0x2 gt rows 2 0x3 gt rows 1 For example if ROWS 0x1 and COLS 0x1 then the number of column address bits is 13 3 10 115 ADM XRC SDK 4 9 3 User Guide Win32 Memory 7 6 BANKS R W This field selects the number of bank address bits in the DDR II SDRAM devices 0x0 gt no bank bits 1 internal bank 0x1 gt 1 bank bit 2 internal banks 0x2 gt 2 bank bits 4 internal banks 0x3 gt 3 bank bits 8 internal banks 9 8 PBANKS R W This field selects the number of chip select pins in the memory bank 0x0 gt 1 physical bank 0x1 gt 2 physical banks 0x2
522. unction 3 0 BANK R W Selects which bank is currently available via the memory access window at local bus address 0x200000 31 4 RO MBZ Reserved Page register PAGE local bus address 0x4 Bits Mnemonic Type Function 132 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 12 0 PAGE RAN 31 13 RO MBZ Value that selects which 2MB page of memory is currently available via the memory access window at local bus address 0x200000 Reserved Memory control register MEMCTL local bus address 0x8 Bits Mnemonic Type 0 RST R W 31 1 RO MBZ Status register STATUS local bus address 0x10 Function While this field is 1 the entire memory subsystem is held in reset An application should NOT attempt to access memory while this field is 1 When 0 the memory subsystem is not held in reset Reserved This register indicates the general health of the FPGA in the form of lock flags from DLL DCMs and PLLs as well as training flags from any self training memory banks Bits Mnemonic Type 0 LLOCK RO 0 SLLOCK R W1C 7 2 RO MBZ 15 8 MLOCK RO 23 16 SMLOCK R W1C 31 24 RO MBZ Function When 1 indicates that the DLL or DCM that distributes LCLK within the FPGA is locked If 500ms or later after configuration of the FPGA this field is not 1 the application should consider this a fatal error Sticky loss of lock flag When 1 indicates that the DLL or DCM that distributes LCLK within the FPGA has lost lock at some point W
523. unused pins from being pulled up or pulled down and should be used for all bitstreams that target Alpha Data reconfigurable computing cards This option enables compression of the bitstream which generally reduces the size of a BIT file It can be applied to Virtex and later architectures 1 When running PAR in ISE 4 2i or later check that PAR reports the expected number of LOC ed IOBs Early on during the execution of PAR you should see a message of the form Device utilization summary Number of External GCLKIOBs 1 out of 4 25 Number of External IOBs 45 out of 404 11 Number of LOCed External IOBs 45 out of 45 100 Number of SLICEs 2612 out of 6912 38 Number of GCLKs 1 out of 4 25 Number of TBUFs 320 out of 7104 5 Generally Number of LOCed External IOBs should be 100 If not it implies that or more IOBs will be placed on arbitrary pins which may cause problems The PAD file which is produced along with the routed NCD file can be used to find out which I O signals do not have location constraints 2 The following Xilinx answer explains that Project Navigator in ISE 5 1i does not display the Active pullup option in the properties for Generate Programming File Answer Record 15812 5 1i Project Navigator The DriveDone startup option for Virtex Il devices is not present A workaround for this issue is given by the following Xilinx answer Answer Record 11088 5 1i ISE How
524. uration data Channel In DMA channel to use for the operation Event In out Event to use to wait for completion Return value Value Meaning ADMXRC_SUCCESS The FPGA was successfully configured ADMXRC_INVALID_ HANDLE Card is not a valid handle to a card ADMXRC_INVALID_ PARAMETER An invalid parameter was passed ADMXRC_NO_DMADESC A DMA descriptor could not be allocated Description This function is used to configure the FPGA on a card from a buffer of SelectMap data using DMA Since there is no file I O to be performed this is a deterministic method of configuring the FPGA As DMA is used to configure the FPGA this method is also the fastest This routine does not allow the FPGA to be partially configured on each call all of the data necessary to configure the FPGA must be supplied in a single call Warning Ensure that Buffer contains valid configuration data for the target FPGA as data transferred this way to the FPGA s SelectMap port cannot be validated by the API The card to be configured is specified by the Card parameter The Buffer parameter should point to a buffer containing the configuration data for the FPGA The data must be supplied in 510 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC ConfigureFromBufferDMA a form directly writable to the FPGA s SelectMap port and care should be taken to ensure that the bit ordering of the data is correct The functions ADMXRC LoadFpgaFile ADMXRC FindlmageOffset and ADMXRC ReverseBytes can
525. ure is returned by ADMXRC2 GetBanklnfo and contains information about a bank of memory fitted to a card Some applications may require this information in order for example to make the correct decisions when programming FPGA registers that deal with memory access Simpler applications may do nothing more than check that the memory configuration on a card is as expected The Fitted member indicates whether devices are physically present on the card If TRUE the other three members of the structure are valid If FALSE the other three members of the structure are not valid and should be ignored The Type member identifies the type of memory comprising the bank It is a bitmask of flags and a memory bank may be capable of operating in more than one mode depending on the devices fitted Flag Meaning ADMXRC2 RAM ZBTFT The bank is ZBT SSRAM capable of operating in flowthrough mode ADMXRC2 RAM ZBTP The bank is ZBT SSRAM capable of operating in pipelined mode ADMXRC2 RAM SDRAM SDR The bank is SDR SDRAM ADMXRC2 RAM SDRAM DDR The bank is DDR SDRAM ADMXRC2 RAM SRAM DDR2 The bank is DDR II SSRAM ADMXRC2 RAM SDRAM DDR2 The bank is DDR II SRAM The Width member gives the width of the bank in bits The bank width can also be inferred from the BoardType member in the ADMXRC2 CARD INFO structure as it is constant for a given type of board For DDR memory types the width is given in logical bits where one physical wire carries two logical data bi
526. ussed signal each local bus agent that is capable of becoming a bus master has its own HOLD signal which is an input to the local bus arbiter When the arbiter grants ownership of the local bus it asserts HOLDA An agent should not assert HOLD unless it intends to perform a burst as a master and once it asserts HOLD it should not deassert it until it has finished with the bus for example by completing a burst On an ADM XRC series card there are two local bus agents capable of performing local bus bursts as masters e The HOLD signal for the local bus bridge is named LHOLD e The HOLD signal for the FPGA is named FHOLD Hold Acknowledge HOLDA is asserted by the bus arbiter to indicate that the bus has been granted to a particular local bus agent It is not a bussed signal each local bus agent that is capable of becoming a bus master has its own HOLDA signal which is driven by the local bus arbiter The arbiter will not deassert a master s HOLDA until that master indicates that it has finished with the bus by deasserting its HOLD signal An agent must not attempt to perform a local bus cycle as a master unless it has sampled its own HOLDA signal asserted On an ADM XRC series card there are two local bus agents capable of performing local bus bursts as masters e The HOLDA signal for the local bus bridge is named LHOLDA e The HOLDA signal for the FPGA is named ADM XRC SDK 4 9 3 User Guide Win32 B
527. ussed signals 212 LADS LA LAD LBE master master master slave master FHOLDA Local Address Strobe LADS is asserted for exactly one cycle to mark the beginning of a burst When LADS is asserted the local bus address is guaranteed to be valid on LA for a nonmultiplexed address bus or LAD for a multiplexed address data bus Local Address LA carries the local bus address of the current word of the current burst It is valid for all cycles of a burst When a word of data is transferred the master normally increments LA although a master may choose not to increment LA is present only on cards that have a nonmultiplexed address bus Local Address Data LAD is qualified by the following events e Assertion of LADS by the master LAD 31 0 carries the byte address of first word of burst If the L64 signal exists on the bus and is asserted then LAD 2 0 will be zero Otherwise LAD 1 0 will be zero e Assertion of LBTERM by the slave e Assertion of LREADY by the slave If the current transfer is 32 bits wide L64 does not exist on the bus or is deasserted then only LAD 31 0 carry data If the current transfer is 64 bits wide L64 exists on the bus and is asserted then LAD 63 0 carry data LAD is present only on cards that have a multiplexed address data bus Local Byte Enables LBE accompanies the LD or LAD signal indicating which bytes of the data are valid Tog
528. v2 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead Parameters Name Type Function Note a width natural Width in bits of the port logical address a 4 auto train boolean If true the memory port automatically trains itself after reset is deasserted If false the memory port does not train itself This parameter has a default value of true and in normal usage an application should rely on the default value and not map it to any particular value d width natural Width in bits of the port data in and out d and q 3 respectively pinout ddrsdram pinout t This value specifies the physical configuration of the memory port For convenience an application may map it to one of the predefined constants ra width natural Width in bits of the memory device address bus ra 1 rc width natural Width in bits of the memory device control bus rc 2 rd width natural Width in bits of the memory device data bus rd 3 tag width natural Width in bits of the tag in and out tag and qtag respectively timing ddrsdram timing t This value specifies the timing of the memory port For convenience an application may map it to one of the predefined constants Notes 1 The memory device address bus ra is composed of two fields in this memory port with the widths of each field specified by the num addr bits and num bank bi
529. val is left padded to a multiple of 4 elements before being converted to a hexadecimal string Element 1 of the result string corresponds to the rightmost 4 bits of val For example 100101 becomes 25 383 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data PLXSIM VHDL reference plxsim read Declaration Synopsis Description Declaration procedure plxsim read order E gl natural multiburst in boolean address gt in std logic vector be in byte enable t data out byte vector t nxfered out natural signal bus in dun locbus in t signal bus out out locbus out t Synopsis Performs a basic local bus read transfer with incrementing local bus address Description This procedure uses the bus in and bus out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim read FPGA design under tes t aut Stimulus rocess achbus in 1 Local bus LOCAL agent BUS ike J The order parameter specifies the width of the local data bus Valid values are e 2 for a 32 bit local data bus 384 ADM XRC SDK 4 9 3 User Guide Win32 plxsim read e for a 64 bit local data bus The multiburst parameter specifies the action taken if the target of the transfer terminates the burst before the desired number of bytes has been transferre
530. valid2 and valid3 outputs are always asserted together by arbiter 4 If one of the validi signals is asserted then all must be asserted This is because it is the responsibility of each client to recognize its own tags The arbiter 4 module does not attempt to decode the qtag signal see below in order to determine which client issued the corresponding read command The following figure illustrates a read command issued by client 1 All validi signals are always asserted together With reference to the above figure client 1 issues the read and recognizes its own data by decoding qtag1 However clients 0 2 and 3 must also respectively decode qtag0 qtag2 and qtag3 and determine that the data does not belong to them Depending on how many clients there are decoding a tag may be as simple as checking the top bit or top couple of bits of a qtagi value The interface presented to the shared memory port by the arbiter 4 module is as follows Signal Type Function Note a out Memory port logical address The arbiter 4 module drives this signal with a valid address when asserts ce in order to access the memory port on behalf of a client be out Memory port byte enables The arbiter 4 module drives this signal with a valid set of byte enables when it asserts ce and w together in order to perform a write to the memory port on behalf of a client A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory while
531. values of reg in and reg wr For example if the CPU writes a 16 bit value to the address 0x13e the 16 bit value is reflected in reg in 63 48 while bits 62 and 63 only of reg wr pulse asserted for exactly one memory user clock cycle When such an event occurs the user app module can at its discretion elect to store the value on reg in somewhere The user app module can drive the reg out vector which is 256 bytes in size with arbitrary status information This status information is visible in the USER registers when the CPU reads local bus addresses 0x100 to Ox1FF Note that synchronizing logic in the reg sync module results in a round trip delay of approximately 12 local bus clock cycles whenever some information must be communicated between the local bus interface and the user app module Hence if the CPU writes something to a USER register reading the same or another USER register is not guaranteed to return a value that reflects what was just written until approximately 12 local bus clock cycles have elapsed Source files For a list of the VHDL source files refer to the appropriate XST project file as referenced in the following table Model ADM XRC 4FX with 4VFX100 ADM XRC 4FX with 4VFX140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with VSFXT ADM XRC 5T1 with V5LXT ADM XRC 5T1 with V5SXT 147 XST script file memory64 xrc4fx v4fx scr memory64 xrc4fx v4fx scr
532. vhd fpga vhdl common memif ddrsdram v2 ddrsdram training v2 vhd If synthesizing the file fpga vhdl common memif memif def synth vhd must be included If simulating the file fpga vhdl common memif memif def sim vhd must be included instead 334 ADM XRC SDK 4 9 3 User Guide Win32 ddrsdram training v2 Parameters Name Type Function Note num port natural This is the width in bits of the tstdone and tstok ports 1 Notes 1 A single instance of ddrsdram training v2 can be used to train more than one instance of ddrsdram port v2 provided that the banks of memory are reasonably well matched When instantiating ddrsdram training v2 the value of the num port parameter is the number of instances of ddrsdram port v2 whose training will be controlled by that instance of ddrsdram training v2 Signals The signals of this interface to and from the user application are as follows Signal Type Function Note cedge in Capture edge This should be connected directly to the cedge ports of one or more instances of ddrsdram port v2 and carries information about how to retime data captured using the clkcO and clkc180 clocks into the memory ports user interface clock domain clk in Clock 2 3 All ports except rst clkc clkcO and clkc180 are synchronous to clk clkc in Capture clock in 4 This clock is used to generate the two capture clock phases clkcO and clkc180 clkcO out Capture clock phase 0 4 This clock should be connected dir
533. via the ce signal Accordingly the d width parameter which is the width of d and q is typically specified by the user application as being four times rd width However other values can be passed for d width o lf d width gt 4 rd width then the memory port simply truncates d internally so that its width is 4 rd width Data read from the memory devices is zero extended so that its width is d width before being returned on q o d width 4 rd width is the optimal usage case o If d width lt 4 rd width then the memory port zero extends d internally so that its width is 4 rd width 4 Thea width parameter is the width of the logical address bus a Generally it must be sufficiently wide to be able to address all of the memory in a DDR II SDRAM bank Hence the required value of a width depends on what memory devices are actually in use As an example consider two physical banks of DDR II SDRAM devices that use 13 row bits 10 column bits and 3 internal bank address bits The number of address bits is 13 row address bits 10 column address bits 3 internal bank address bits 4 1 2 physical banks CS pins 27 We must now subtract 2 because logical memory locations are 4 times as wide as the physical memory locations due to transferring 4 words on the DQ pins for every command entered on ce Hence a width for this configuration should be at least 25 When a width is larger than actually required th
534. was invalid timeout period Card could not be opened because it was already open An invalid parameter was supplied to the call The card was closed before th was completed operation A hardware error occurred on the card An operation was requested which is not supported or implemented The requested devic was in use or resourc The DMA descriptor passed was invalid No free DMA descriptors left The operation failed The operation is still in progress he bitstream file appears to be corrupt he bitstream file does not match the FPGA he operation was not completed within the The operation failed for reasons unknown ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 STATUS ADMXRC2 NULL POINTER null pointer was supplied in the call ADMXRC2 CANCELLED The operation was cancelled becaus requesting thread terminated ADMXRC2 BAD DRIVER The driver revision level is too low ADMXRC2 STATUS Description A variable of the enumerated type ADMXRC2 STATUS holds a code indicating the success or failure of a call to an ADM API function 502 ADM XRC SDK 4 9 3 User Guide Win32 ADMXRC2 SYNCMODE ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ADMXRC2 SYNCMODE Declaration typedef enum ADMXRC2 SYNCMODE ADMXRC2 SYNC CPUTOFPGA ADMXRC2 SYNC FPG
535. with 4vfx140 ADPE XRC 4FX with 4VFX100 ADPE XRC 4FX with 4VFX140 ADM XRC 5LX ADM XRC 5T1 with FXT ADM XRC 5T1 with LXT ADM XRC 5T1 with SXT ADM XRC 5T2 or ADM XRC 5T2 ADV with FXT ADM XRC 5T2 or ADM XRC 5T2 ADV with LXT ADM XRC 5T2 or ADM XRC 5T2 ADV with SXT ddma64 xrce4fx v4fx scr ddma64 xrce4fx v4fx scr ddma64 xrcblx v5lx scr ddma64 xrcbt1 vbfxt scr ddma64 xrcbt1 v5lxt scr ddma64 xrc5t1 v5sxt scr ddma64 xrcbt2 vbfxt scr ddma64 xrcbt2 v5lxt scr ddma64 xrc5t2 v5sxt scr Project Navigator files XST project file ddma64 xpl v2p prj ddma64 xp v2p prj ddma64 xpi v2p prj ddma64 xrc4fx v4fx prj ddma64 xrc4fx v4fx prj ddma64 xrce4fx v4fx prj ddma64 xrce4fx v4fx prj ddma64 xrcblx v5lx prj ddma64 xrcbt1 v5fxt prj ddma64 xrc5t1 v5Ixt prj ddma64 xrcbt1 v5sxt prj ddma64 xrcb5t2 v5fxt prj ddma64 xrc5t2 v5Ixt prj ddma64 xrc5t2 v5sxt prj UCF file ddma64 xpl ucf ddma64 xp ucf ddma64 xpi ucf ddma64 xrc4fx A4vfx100 ucf ddma64 xrc4fx A4vfx140 ucf ddma64 xrce4fx A4vfx100 ucf ddma64 xrce4fx A4vfx140 ucf ddma64 xrcblx ucf ddma64 xrcbt1 5vfxt ucf ddma64 xrcbt1 ucf ddma64 xrcbt1 ucf ddma64 xrcbt2 5vfxt ucf ddma64 xrcbt2 ucf ddma64 xrcbt2 ucf Project Navigator projects can be found in the projnav directory as follows Model ADM XPL ADM XP ADP XPI ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 Project Navigator project file projnav
536. word From the host s point of view the registers in the FPGA are the same as in the Simple FPGA design They can be accessed via the ADMXRC2 Read and ADMXRC2 Write API calls or via a memory mapped region The latter method is demonstrated by the Simple sample application FPGA Space Usage Nibble reversed data register REVDATA local bus address 0 0 Bits Mnemonic Type Function 31 0 VAL RAN When read this register returns the nibble reversed version of the last value written to it Nibble reversed data register DATA local bus address 0x4 Bits Mnemonic Type Function 31 0 VAL R W When read this register returns the last value written to it Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XPL simple xpl v2p scr simple xpl v2p prj simple xpl ucf ADM XP simple xp v2p scr simple xp v2p prj simple xp ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XPL projnav xpl lt device gt ADM XP projnav xp lt device gt 191 ADM XRC SDK 4 9 3 User Guide Win32 ZBT ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data ZBT sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Support
537. working on an FPGA design a user can copy and paste the relevant sections of the appropriate master constraints file into his or her own constraints file and then modify as necessary 203 ADM XRC SDK 4 9 3 User Guide Win32 Building designs for Virtex II ES ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Building designs for Virtex Il engineering samples At the time of writing Alpha Data suggests the following guidelines for users wishing to implement a design for a Virtex Il ES device The environment variable XIL BITGEN VIRTEX2ES must be set to 1 when running bitgen exe for a Virtex Il ES device Note that a bitstream generated for a Virtex Il ES device is compatible with a Virtex Il production device Use of Xilinx Foundation 4 1i SP3 or later is strongly recommended when building bitstreams for Virtex Il ES devices If Xilinx Foundation 4 1i SP2 or earlier is used to generate a bitstream using DCMs for a Virtex Il ES device Alpha Data cannot guarantee that a correctly working bitstream will be generated Xilinx Foundation 3 1i SP8 4 11 4 1i SP1 or 4 11 5 2 may safely be used to implement Virtex Il ES designs that do not use DCMs A patch available from the Xilinx website must be applied to Xilinx Foundation 3 1i SP8 in order for bitgen exe to recognise the BITGEN VIRTEX2ES environment variable Customers who require help implementing a design for a Virtex Il ES device should contact Alpha
538. xrc2l lt device gt projnav xrc2 lt device gt projnav xpl lt device gt projnav xp lt device gt projnav wrc2 lt device gt projnav drc2 lt device gt ADM XRC SDK 4 9 3 User Guide Win32 FrontlO ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data FrontlO sample Verilog FPGA design Model support Location Synopsis FPGA space usage Source files Project Navigator files Model support Model Supported ADM XRC ADM XRC P ADM XRC II Lite ADM XRC II ADM XPL ADM XP ADP WRC II ADP DRC II ADP XPI ADM XRC 4LX ADM XRC 4SX ADM XRC 4FX ADPE XRC 4FX ADM XRC 5LX ADM XRC 5T1 ADM XRC 5T2 ADM XRC 5T2 ADV ADM XRC 5TZ ADM XRC 5T DA1 Location SADMXRC_SDK4 fpga verilog frontio Synopsis The FrontlO FPGA design simply outputs a walking 1 bit on the front panel I O pins FPGA Space Usage 177 ADM XRC SDK 4 9 3 User Guide Win32 FrontIO The FrontlO design does not have a local bus interface thus there are no registers defined the FPGA space Source files For a list of the Verilog source files refer to the appropriate XST project file as referenced in the following table Model XST script file XST project file UCF file ADM XRC with frontio xrc v scr frontio xrc v prj frontio xrc ucf Virtex ADM XRC with frontio xrc ve scr frontio xrc ve prj frontio xrc ucf Virtex E ADM XRC II Lite frontio xrc2l v2 scr frontio xrc2l v2 prj frontio xrc2l ucf ADM XRC II frontio xrc
539. xrcbtz v5sxt scr ddma xrcbtda1 vb5fxt scr ddma xrcbtda1 vb5lxt scr XST project file ddma xrc v prj ddma xrc ve prj ddma xrcp v prj ddma xrcp ve prj ddma xrc2l v2 prj ddma xrc2 v2 prj ddma xpl v2p prj ddma xp v2p prj ddma wrc2 v2 prj ddma drc2 v2 prj ddma xpi v2p prj ddma xrc4lx v4lx prj ddma xrc4sx v4sx prj ddma xrc4fx v4fx prj ddma xrc4fx v4fx prj ddma xrce4fx v4fx prj ddma xrce4fx v4fx prj ddma xrc5Ix v5Ix prj ddma xrcbt1 vbfxt prj ddma xrcbt1 v5lxt prj ddma xrcbt1 v5sxt prj ddma xrcbt2 vbfxt prj ddma xrc5t2 v5lxt prj ddma xrc5t2 v5sxt prj ddma xrcbtz v5fxt prj ddma xrcbtz vb5lxt prj ddma xrcbtz v5sxt prj ddma xrc5tda1 v5fxt prj ddma xrc5tda1 v5lxt prj UCF file ddma xrc ucf ddma xrc ucf ddma xrcp ucf ddma xrcp ucf ddma xrc2l ucf ddma xrc2 ucf ddma xpl ucf ddma xp ucf ddma wrc2 ucf ddma drc2 ucf ddma xpi ucf ddma xrc4lx ucf ddma xrc4sx ucf ddma xrc4fx Avfx100 ucf ddma xrc4fx Avfx140 ucf ddma xrce4fx A4vfx100 ucf ddma xrce4fx A4vfx140 ucf ddma xrcblx ucf ddma xrcbt1 5vfxt ucf ddma xrcbt1 ucf ddma xrcbt1 ucf ddma xrc5t2 5vfxt ucf ddma xrc5t2 ucf ddma xrc5t2 ucf ddma xrcbtz 5vfxt ucf ddma xrcbtz ucf ddma xrcbtz ucf ddma xrcbtda1 5vfxt ucf ddma xrcbtda1 ucf ADM XRC SDK 4 9 3 User Guide Win32 DDMA ADM XRC 5T DA1 with SXT Project Navigator files ddma xrcbtda1 v5sxt scr ddma xrc5tda1 v5sxt prj ddma xrcbtda1 ucf Project Navigator projects
540. xrcp v scr dll xrcp ve scr dll xrc2l v2 scr dll xrc2 v2 scr dll xpl v2p scr dll xp v2p scr dll wrc2 v2 scr dil drc2 v2 scr dll xpi v2p scr dll xrc41x v4lx scr dli xrc4sx v4sx scr dil xrc4fx v4fx ser dll xrc4fx v4fx ser dil xrce4fx v4fx ser dil xrce4fx v4fx ser dll xrc5lx v5lx scr dll xrc5t1 v5fxt scr dll xrc5t1 v5lxt scr dll xrc5t1 v5sxt scr XST project file dll xrc v prj dll xrc ve prj dll xrcp v prj dll xrcp ve prj dll xrc2l v2 prj dll xrc2 v2 prj dll xpl v2p prj dll xp v2p prj dll wrc2 v2 prj dll drc2 v2 prj dll xpi v2p prj dll xrc4lx v4lx prj dll xrc4sx v4sx prj dll xrc4fx v4fx prj dll xrc4fx v4fx prj dll xrce4fx v4fx prj dll xrce4fx v4fx prj dll xrc5lx v5lx prj dll xrc5t1 v5fxt prj dll xrc5t1 v5lxt prj dll xrc5t1 v5sxt prj UCF file dll xrc ucf dll xrc ucf dll xrcp ucf dll xrcp ucf dll xrc2l ucf dll xrc2 ucf dll xpl ucf dll xp ucf dll wrc2 ucf dll drc2 ucf dll xpi ucf dll xrc4lx ucf dll xrc4sx ucf dll xrc4fx 4vfx100 ucf dll xrc4fx 4vfx140 ucf dll xrce4fx 4vfx100 ucf dll xrce4fx 4vfx140 ucf dll xrc5lx ucf dll xrc5t1 5vfxt ucf dll xrc5t1 ucf dll xrc5t1 ucf ADM XRC SDK 4 9 3 User Guide Win32 DLL ADM XRC 5T2 or dll xrc5t2 vbfxt scr dll xrcbt2 vbfxt prj dll xrcbt2 5vfxt ucf ADM XRC 5T2 ADV with FXT ADM XRC 5T2 dll xrc5t2 vblxt scr dli xrc5t2 v5lxt prj dll xrc5t2 ucf ADM XRC 5T2 ADV with LXT ADM XRC 5T2 or dll xrc5t2 v5sxt scr dll xrc5t2 v5sxt pr d
541. xsim write demand Declaration Synopsis Description Declaration procedure plxsim write demand order s ox natural address on std_logic_vector be 2p byte enable t data in byte vector t nxfered out natural signal bus in gt in locbus in t signal bus out out locbus out t signal dd in C Zn locbus ddma in t signal dd out out locbus ddma out t Synopsis Performs a demand mode DMA local bus write transfer with incrementing local bus address Description This procedure uses the bus in bus out dd in and dd out signals to drive a local bus agent as shown in this figure where the stimulus process makes calls to plxsim write demand lachus out t Idack 1 lt 02 gt lacbuz dama in t Idreg 1 0 gt Stimulus process n Local bus FPGA design unit under test agent LOCAL BUS 0 401 ADM XRC SDK 4 9 3 User Guide Win32 plxsim write demand Before calling this procedure a stimulus process should ensure that the FPGA ie the unit under test has asserted LDREOX This can be accomplished by calling plxsim wait demand before calling plxsim write demand When called plxsim read demand will continue to perform transfers until one of two conditions is met 1 The FPGA unit under test deasserts LDREQ in order to pause the DMA transfer or 2 All of the data has been transferred the length of the data vector specifies how many bytes must be transferred During the t
542. xt 6banks prj memory64 xrcbt2 v5sxt 6banks prj xrcbt2 memory64 xrcbt2 5vlx110t ucf xrcbt2 memory64 xrcbt2 5vIx330t ucf xrc5t2 memory64 xrc5t2 5vfx100t ucf xrcbt2 memory64 xrcbt2 5vfx130t ucf xrcbt2 memory64 xrcbt2 5vfx200t ucf xrc5t2 memory64 xrc5t2 5vsx240t ucf Project Navigator files Project Navigator projects can be found in the projnav directory as follows Model Project Navigator project file ADM XRC 4FX projnav xrc4fx lt device gt ADPE XRC 4FX projnav xrce4fx lt device gt ADM XRC 5LX projnav xrc5 x lt device gt ADM XRC 5T1 projnav xrc5t1 lt device gt ADM XRC 5T2 projnav xrc5t2 lt device gt ADM XRC 5T2 ADV Modelsim scripts Example Modelsim compatible script files for simulating this design are provided First change directory to where this design is located and then refer to the following table for the appropriate shell commands for a particular model These simulations make use of behavioural memory models supplied by Micron and Hynix These models are available from the websites of the respective vendors but for legal reasons Alpha Data does not supply these models with this SDK The models in question are e MT55L256L36F Micron flowthrough ZBT SSRAM e MT55L512L18P Micron pipelined ZBT SSRAM e MT55L256L36P Micron pipelined ZBT SSRAM 148 ADM XRC SDK 4 9 3 User Guide Win32 Memory64 e MT46V16M16 Micron DDR SDRAM e HY5PS121621F Hynix DDR II SDRAM Note that simulat
543. y the following figure clko clk45 dk2x0 dk2x90 T e ULL LLL Also shown is the DDR II SSRAM clock Its frequency is the same as clkO but its phase is indeterminate 6 For correction operation all sideband inputs must be static while the memory port is not idle 7 The delay from deassertion of reset to completion of training trained asserted is approximately 150 microseconds at a frequency of 133MHz The signals of this interface to and from the memory device s are as follows Signal Type Function ra in Memory device address bus This bus carries address information to from the memory port to the memory device s rc inout Memory device control bus This bus carries control signals between the memory port and the memory device s and is composed of various fields These signals are bundled together into the rc bus so that for the most part the user application need not care what they are Refer to note 2 for the mapping of the rc bus to device pins rd inout Memory device data bus This bus carries data between the memory port and the memory device s For each command entered via ce four words are transferred on rd which determines the relationship between the rd width and d with parameters Refer to note 3 for details Performance 353 ADM XRC SDK 4 9 3 User Guide Win32 ddr2sram port v4 This memory port features an internal command buffer capable of buffering about 1
544. ype FPGA Express names an instance strictly according to its label and hierarchy level 206 ADM XRC SDK 4 9 3 User Guide Win32 Other documentation ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Other documentation The ADM XRC series of cards utilise the PCI9080 and PCI9656 high performance IOPs from PLX Technology Inc e PCI9080 ADM XRC ADM XRC P and ADM XRC I Lite e 9656 ADM XRC II ADP WRC II ADP DRC II ADM XRC 4LX and ADM XRC 4SX Data books for these devices are included in PDF form in the doc directory of the ADM XRC SDK Please visit www plxtech com to obtain the latest and most up to date data books on the PCI9080 and PCI9656 We also recommend reading the errata and design notes for these devices also available at www plxtech com At the time of writing a preliminary version 0 90b of the PCI9656 data book is included PLX Technology Inc are committed to a policy of continual improvement of their documentation 207 ADM XRC SDK 4 9 3 User Guide Win32 Introduction to the local bus ADM XRC SDK 4 9 3 User Guide Win32 Copyright 2001 2009 Alpha Data Introduction to the local bus This section provides a brief primer to the protocol used on the local bus common to the Alpha Data Xilinx Reconfigurable Coprocessor range The key features of the local bus are e Supports multiple masters an arbitration protocol permits more than one master on the local bus e Burstable
545. ype ddr2sdram timing t is record t refresh natural Average periodic refresh interval t mrd natural Minimum time between mode register set commands t dllr natural Minimum time between DLL leaving reset and first read command gt natural Minimum time between row precharge and row activate commands t rfc natural Minimum time between refresh command and any other command t act natural Minimum time between row activate command and any read write command t wtr natural Minimum time between write command and read command t rtw natural Minimum time between read command and write command t rtp natural Minimum time between read command and precharge command t wtp natural Minimum time between write command and precharge command t ras natural Minimum number of cycles that a row must be open end record datatype can normally treated as an abstract datatype since the user application need typically only use one of the predefined constants of type ddr2sdram timing t However should it be necessary to create a new value the members are defined as follows Member Type Function t refresh natural Average periodic refresh interval in clkO cycles t mrd natural Mode register set command period in clkO cycles t natural Minimum number of cIkO cycles between DLL reset deasserted to first memory access t rp natural Minimum number of cIkO cycles between PRE prec

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