EVBUM2126 - NCP1030GEVB Isolated 2 W Bias Supply for
Contents
1. A Flyback topology operating in discontinuous mode is selected because of its simplicity and low part count Semiconductor Compon jy 1 blication Order Number June 2012 Rev 1 WA WAT WW com EVBUM2126 0 NCP1030GEVB Flyback Converter A dual output Flyback converter is shown in Figure 1 OUTPUT 1 is regulated by means of OUTPUT 2 providing an isolated OUTPUT 1 without the need for an optocoupler D1 TX gt o Cout Vout OUTPUT1 gt e o ay Vin Snubber hd F R Coc Vec OUTPUT2 1 R1 PWM o EA Mi Controller a R2 VREF 3 Figure 1 Isolated Flyback Converter Current flows in the primary side when the Power Switch M1 is ON The transformer primary side dot end becomes positive with respect to the non dot end While the Power Switch is ON energy is stored in the transformer and D1 and D2 are reverse biased When M1 turns OFF the transformer winding polarities are reversed forward biasing D1 and D2 Energy is transferred to the secondary outputs during this period If the secondary current decays to zero before the switch turns ON again the converter operates in discontinuous mode Otherwise it operates in continuous mode The converter regulates the output by sampling the output voltage and comparing it to a reference voltage A signal proportional to their difference is generated and used to adjust the ON2. Magnitude ay Phase alll 19 30 y 20 Ud a 20 l3 30 F Z o 10 40 2 S P Sok I 50 c amp 10 i 60 5 S 4 4 s 20 SL 70 lt pa PMT it 1 te r 40 90 50 100 101 102 103 104 105 108 Frequency Hz Figure 4 Open Loop Frequency Response for Gmop2 The frequency compensation can be achieved using a type II error amplifier EA as the one shown in Figure 5 Input F C6 Zf Ibias l R6 A Z1 om gt R4 C2 R7 a Output Rbias S R5 L t VREF Figure 5 Type Il Error Amplifier A type II error amplifier has 2 poles and 1 zero The transfer function is given by Equation 13 _ sR7Co 1 sR4 C2 Ce 1 sR7 C7C6 eq 13 C7 C6 One of the poles fp2 is at the origin The frequency of the remaining pole and zero are given by Equations 14 and 15 respectively _ _ 1 fz2 2nR7C2 eq 14 _ C2 C6 15 fp 2nR7C2Cg eq 15 The EA poles and zero locations are selected to achieve the desired crossover frequency fco A system crossover frequency of 10 kHz is selected for GMop As the modulator gain depends on the input voltage a higher fco is obtained for the maximum input voltage condition with equivalent output load The selection of the compensation components begins by noting that the voltage on the Vpg pin should be equal to 2 5 V VreF when the output is in regulation 12 V If the feedback sensing resistor network bias current
3. tan 5 eq 19 fz fco Op tan 9 eq 20 p fp The phase margin OM is evaluated taking into account the phase contribution of all the poles and zeros as shown below in Equation 21 M 180 p1 p2 8p3 621 822 eq 21 o o M 180 89 5 90 22 7 7 33 87 24 72 4 The calculated phase margin is 72 4 The 180 term arises because the EA is in an inverting configuration The simulated system frequency responses for GMop and Gmopz2 are shown in Figure 7 BO a i 80 70 j Phas 90 60 Le 100 m 50 7 110 A Z 40 AUU 120 3 3 S 30 130 amp 20 720Q 140 g 10 Magnitude l _450 z a Vin 36V Jj 0 ys Rout 72Q 4 160 NLU Magnitude l 10 Vin 76V H IHH 170 20 Rout iui III 180 10 102 108 104 105 106 Frequency Hz Figure 7 System Frequency Response Under Overvoltage Detectors The NCP1030 eliminates the need for additional supervisory circuitry by incorporating individual under and overvoltage detectors with hysteresis The controller is enabled if the voltage on the UV pin is above 2 5 V and the voltage on the OV pin is below 2 5 V The UV OV detectors can be biased using an external
4. Impedance Layout Considerations Switching regulators can be noisy However with careful layout noise is reduced A few things to remember are 1 Keep switching elements and high current traces away from the controller and sensitive nodes 2 Keep trace lengths to a minimum especially important for high current paths and timing components Use wide traces for high current paths Place bypass capacitors close to the components 5 Use a ground plane if possible or a single point ground system The bias supply is built using a single layer FR4 board The board size is 2 0 in x 3 5 in The complete circuit schematic is shown in Figure 12 and an actual size picture of the board is shown in Figure 13 The Bill of Material is listed in Table 4 BW 2 2 4 2 7g MBRA160T3 OS VY VY e p o Poy 499 35 76V 22 5 z tig 0 022 V EE NCP1030 GND VDRAIN CT VCC VFB UV a OV 680p COMP Ea 0 01 1k30 680p 0 01 S 34k L vv pay 0 033 10k Figure 12 Complete Circuit Schematic www BD TFt tom ON Table 4 BILL OF MATERIALS NCP1030GEVB Semiconductor NCP1030 Vout r j ere im ie Rt rial ME E Figure 13 Evaluation Board Actual Size Substi RoHS Desig Toler Manufacturer Part tution Com nator
5. Ipjas1 is known R4 and Rs are calculated using Equations 16 and 17 respectively VREF eq 16 Ibias1 Vcc R eq 17 Ibias1 Using a bias current of 2 0 mA R4 and Rs are calculated at 4 99 KQ and 1 30 KQ respectively Resistor Rg provides a test point to measure the open loop frequency response It is set at 10 Q to avoid disrupting the DC bias point The error amplifier DC gain Gga is calculated using Equation 18 It is set at 6 03 dB to achieve a gain of 0 dB at 10 kHz for Gmop1 R7 GEA 20 log 52 eq 18 The error amplifier zero f 9 is placed before the system response crosses 0 dB Pole fp3 is placed after fco to attenuate high frequency components Table 3 summarizes the system gain poles and zeros Figure 6 shows the EA frequency response Table 3 SYSTEM GAIN POLES AND ZEROS Frequency 0A www BD Fif tom ON NCP1030GEVB 60 T T rmm T TTT 0 Magnitude _ oe Phase 19 40 ACTEM 20 i 30 Ir h 30 Magnitude dB 3 a e Angle degrees 0 L 60 Ul 4 10 Pi 70 20 80 30 90 40 100 101 102 103 104 105 106 Frequency Hz Figure 6 Error Amplifier Frequency Response The phase contributions of a zero and a pole at the crossover frequency are given by Equations 19 and 20 respectively z
6. or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE F
7. resistor divider as shown in Figure 8 Vin R1 Ibias2 R2 C7 Vuy Voy C8 R3 az Figure 8 UV OV Resistor Bias Network If the resistor network bias current Ibias2 is known and the Voy and Vyy thresholds are equal Ry R3 and R232 are calculated using Equations 22 23 and 24 respectively 7 Vin max eq 22 lbias2 Bees Vov x R1 x Vin min eq 23 s Vin min Vin max VOV AVin Vin min z R3 x AVin eq 24 Vin min Using a bias current of 78 uA a turn ON voltage of 35 V a turn OFF voltage of 80 V and a Voy threshold of 2 55 V R R2 and R3 are calculated at approximately 1 0 MQ 45 3 KQ and 34 KQ respectively Capacitors C7 and Cg help reduce noise and provide a stable voltage during turn ON and turn OFF transitions They are set at 10 nF Oscillator Frequency An oscillator frequency of 275 kHz is obtained with a timing capacitor Cr of 680 pF The tolerance of Cr is set at 5 Snubber An RCD snubber as shown in Figure 9 is added to help reduce noise The snubber is returned to the positive supply rail to reduce the voltage stress on Co to Vin If returned to the negative supply rail the voltage stress is 2Vin www BD Tt tom ON NCP1030GEVB TX DIA R9 O O Vin e id C9 e e O Figure 9 RCD Snubber The power dissipation of Rg is determined by Co and is given by equation 25 P t Cg Vin f eq 25 The snubbe
8. Description Value ance Footprint Manufacturer Number Allowed pliant C1 C6 Ceramic Chip 680 pF 25 V Vishay VJ0805A681JXA Yes Capacitor C2 Ceramic Chip 0 033 uF 50 V AVX 08055C333KAT2A Yes Capacitor Corporation c3 Ceramic Chip 22 uF 25 V TDK C4532X5R1E226M Yes Capacitor C4 Ceramic Chip 2 2 uF 25 V TDK C4532X7R1H225M Yes Capacitor C5 Ceramic Chip 2 2 uF 100 V TDK C4532X7R2A225M Yes Capacitor C7 C8 Ceramic Chip 0 01 uF 50 V AVX 08055C103KAT2A Yes Capacitor Corporation c9 Ceramic Chip 100 pF 100 V TDK C1608C0G2A101J Yes Capacitor Optional C10 Ceramic Chip 0 022 uF 250 V TDK C2012X7R2E223K Yes Capacitor D1 D2 Shottky Power 1A 60V ON MBRA160T3G Yes Rectifier Semiconductor D3 Ultrafast Power 1A 100 V ON MURA110T3G Yes Rectifier Optional Semiconductor J1 J4 Printed Circuit Pin NA Mill Max 0912 0 00 80 00 00 Yes 03 0 L1 Surface Mount 2 2 uH 0 32 A Vishay IMC1210ER2R2K Yes Inductor R1 Thick Film Chip 1 00 MQ 1 8 W Yageo RC0805FR 071ML Yes Resistor R2 Thick Film Chip 45 3 KQ 1 8 W Yageo RC0805FR 0745K3L Yes Resistor R3 Thick Film Chip 34 KQ 1 8 W Yageo RC0805FR 0734KL Yes Resistor R4 Thick Film Chip 4 99 KQ 1 8 W Yageo RC0805FR 074K99L Yes Resistor R5 Thick Film Chip 1 30 KQ 1 8 W Yageo RC0805FR 071K3L Yes Resistor R6 Thick Film Chip 10 0 Q 1 8 W Yageo RC0805FR 0710RL Yes Resistor R7 Thick Film Chip 10 0 KQ 1 8 W Yageo RC0805FR 0710KL Yes Resistor R8 Thick Film Chip 0 Q 1 8 W Vishay CRCW08050000Z0EA Yes Resistor www BD
9. NCP1030GEVB Isolated 2 W Bias Supply for Telecom Systems Using the NCP1030 Evaluation Board User s Manual Introduction Power converters using secondary side controllers provide better transient response higher efficiency and usually require less components than their primary side referenced counterparts However secondary side controllers require a primary side referenced bias supply to start operation After start up the controller power can be provided from the secondary side The NCP1030 incorporates in a single IC all the active power control logic and protection circuitry required for implementing with a minimum of external components a highly integrated isolated bias supply The features included in the NCP1030 can result in a footprint area reduction by up to 91 compared to a solution implemented using discrete components The NCP1030 Power Switch Circuit is rated at 200 V making it ideal for 48 V Telecom and 42 V automotive applications In addition this IC can operate from an existing 12 V supply The NCP 1030 includes an extensive set of features including On Board Power Switch Eliminates the need for an external switch As the Power Switch characteristics are well known the gate drive is tailored to control switching transitions and help reduce electromagnetic interference EMI e An Internal Start up Regulator Provides power to the NCP1030 during start up After start up the regulator is disabled th
10. Tt E tom ON NCP1030GEVB Table 4 BILL OF MATERIALS Desig Toler nator QTY Description Value ance R9 Thick Film Chip Resistor Optional 499 Q 1 3 W Footprint 1210 Vishay Substi RoHS Manufacturer Part tution Com Manufacturer Number Allowed pliant CRCW1210499RFKEA Yes TX1 Flyback Transformer 120 uH 12 V 10 16 x Coilcraft 12 07 mm B0226 EL Yes U1 PWM Controller NA Design Verification The final step in our design includes validation and test of the bias supply Before powering the supply it should be inspected for potential problems A few suggestions include 1 Verify all connections Check for shorts and opens especially on the input and output terminals 2 Verify component values 3 Slowly increase the input voltage while monitoring the input current If the input current exceeds 10 mA repeat steps 1 to 3 4 Once the input voltage reaches 25 V measure the voltage on critical nodes The NCP1030 start up regulator should be ON If the voltages are not correct remove power and repeat steps 1 to 3 5 Increase the input voltage to 36 V Measure the output voltage If it is not approximately 12 V repeat steps 1 to 3 6 Increase the input voltage above 80 V The output should turn OFF Please be careful when probing and testing the converter High voltage may be present Exercise CAUTION Once the converter functionality is verified the board performance is evalu
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12. ated and compared to our original goals The evaluation criteria includes 1 Open loop frequency response 2 Efficiency 3 Line and load regulation 4 Step load response 5 Start up response The open loop response is measured injecting an AC signal across Rg using a network analyzer as shown in Figure 14 Micro8 ON NCP1030DMR2G Yes Semiconductor D2 o gt o To Converter V Ccc cc 0 g O e gq S R6 To Error id Amplifier lt Zi REF d A Network Analyzer Rbias B Figure 14 Open Loop Frequency Response Measurement Set up The measured frequency response is shown in Figure 15 The crossover frequency is measured at 9 kHz 50 40 i i Min 36V Hy IE NA Rout 72 2 30 MeL Rout Hl 20 t Mi g a 40 Nt S Daa 2 0 ull 2 i amp 10 NJ T 102 108 104 105 106 Frequency Hz Figure 15 Open Loop Frequency Response www BD Tt tom ON NCP1030GEVB Peak efficiency is measured at 83 Figure 16 shows the efficiency vs output current under several input voltage conditions n Efficiency 0 25 50 75 100 125 150 175 200 lout OUTPUT CURRENT mA Figure 16 Efficiency vs Output Current Line and load regulation are calculated using Equations 27 and 28 respectively AV RegLINE nA eq 27 Vo
13. cilloscope J2 a a 3 Check the switching waveform at scope CH1 to ooo ieas a see whether the start up circuit is enabled 4 Apply an input voltage Vin 36 V across J1 and J2 Measure the output voltage across J4 and J3 It pee should be approximately 12 V 5 Apply 175 mA loading from the electronic load 76 V 1 A Power Supply after powering up the evaluation board 6 Measure VIN lin lout Vout NCP1030 Evaluation Board 1 pRa NCP1030 Evaluation Board 1 7 Increase Vin to 80 V The output should tin OFF Table 6 DESIRED RESULTS Vin 36 V lin 70 mA to 80 mA Vout 11 1 V to 11 5 V Vin 48 V lin 50 mA to 60 mA Vout 11 1 V to 11 5 V Vin 76 V lin 30 mA to 40 mA Vout 11 0 V to 11 5 V ON Semiconductor and Q are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential
14. es Cec and Cout reflected to the auxiliary winding by the transformer turns ratio As the same turns ratio is used for both the auxiliary and output windings Cout adds directly to Ccc The output network has one zero and one pole and they are given by Equations 11 and 12 respectively 1 fat 55 Cout RESR eq 10 eq 11 1 Sr eq 12 fot on Rout Cout The modulator gain response depends on Vin Two extreme conditions both minimum Roy and input voltage Gmop1 as well as both maximum Rout and input voltage Gmopz2 are considered for frequency compensation In order to facilitate frequency compensation Cout is increased to 22 uF The simulated open loop frequency responses for Gmop1 and Gyop2 are shown in Figures 3 and 4 respectively www BD Tt 2tom ON NCP1030GEVB 50 THT T Maat E id T 0 Magnitude pr 40 f Phase j 10 30 F 20 ar 20 30 T 2 3 g 10 f 40 2 0 50 S gt 10t 60 amp lt 20 70 30f Pttit 780 40 90 50 100 10 102 108 104 10 106 Frequency Hz Figure 3 Open Loop Frequency Response for Gyop1 50 0 u
15. n Feedback Loop If the feedback loop is not stable the converter will oscillate To insure the loop is stable the open loop frequency response needs to cross 0 dB at a slope of 20 dB dec with a phase margin above 45 under all line and load conditions This is accomplished by shaping the loop response using the internal error amplifier EA The block diagram shown in Figure 2 is used to evaluate the converter open loop response D1 TX P o gt id z Cout ZZ Rout Vout A e be VvV Resr Rout eq e Cout eq Z PRISON Se ee age TE ty pee A L a a a PWM lt _ Controller lt lt NCP1030 j Io So 1 Figure 2 Flyback Converters The open loop frequency response of the system from A to B is approximated by the modulator gain and the output network frequency response Additional high frequency components are present but are not considered for our analysis as they are far beyond the crossover frequency The modulator gain Gyop is approximated by Equation 9 Rout eq x n eq 9 _3y GMOD 5 Vin x 2xfxLp The output network block is comprised of Cout Resp and Rout The frequency response of the output network is given by Equation 10 f SRESRCout eq 1 SCout eq RESR Rout eq 1 The total open loop frequency response is the product of Equations 9 and 10 Please note that Cout eq includ
16. ocking voltage rating A Schottky diode is selected to reduce the forward voltage drop thus reducing power dissipation On Semiconductor s MBRA160 is selected as it meets all the requirements Auxiliary Supply Regulator The auxiliary supply OUTPUT 2 provides a means to regulate the main output OUTPUT 1 In addition the auxiliary winding disables the internal start up circuit and provides power to the NCP1030 after initial power up The same turns ratio and rectification diode used for the main output are used for the auxiliary winding to improve voltage tracking between the outputs The auxiliary winding capacitor Ccc is selected such that a voltage greater than 7 5 V is maintained on the Vcc pin while the output reaches regulation The time the output reaches regulation is measured at 0 8 ms Once the start up time is known Ccc is calculated using Equation 8 _ Icc xt eq 8 CCC 55V where Icc includes the NCP1030 bias current Icc3 and any additional current supplied by Ccc Assuming an Icc3 of 3 0 mA and a 2 0 mA bias current for the feedback sensing resistors Ccc is calculated at 1 6 uF The Vcc capacitor is set at 2 2 uF Please note that if Ccc is increased to match Cout the transient response of the converter will suffer This is because the capacitance to current ratio of the auxiliary winding is significantly greater then the output winding taking it longer for Ccc to follow Cout during a transient conditio
17. pple Finally the converter turn ON response at full load is evaluated Figure 21 shows the output turn ON transient response at full load o lt DSS Operation 2 l OUTPUT2 T Vout Output Voltage 2 0 V DIV lour 170mA OUTPUTI Isolated 1 0 ms DIV Figure 21 Output Voltage During Turn ON at Full Load Output 2 operates in DSS while the converter is disabled Once the converter is enabled Output 1 tracks Output 2 Summary An isolated 12 V bias supply for a 48 V telecom system is implemented using the NCP1030 The converter achieves a peak efficiency of 83 while providing good transient response References 1 Ridley Ray The Evolution of Power Electronics Switching Power Magazine Fall 2001 16 30 2 Pressman Abraham I Switching Power Supply Design 2nd ed New York NY MacGraw Hill www BD Tt tom ON NCP1030GEVB TEST PROCEDURE FOR THE NCP1030GEVB Scope Electronic Load ome a lout C Power Supply CHI cH2O Multimeter 1 Multimeter 3 MM1 MM1 f B Sei SN 2 LNCP1030 Demo Board ile Multimeter 4 cc L J MM3 Figure 22 Test Setup Table 5 REQUIRED EQUIPMENT Test Procedure 1 Connect the test setup as shown above Quantity 2 Apply an input voltage Vin 25 V across J1 and Dual Channel Os
18. r components are not assembled in the converter However electrical connections are provided if the user wants to add the snubber components Input Filter An L C filter at the converter input is used to reduce EMI The input L C filter reduces noise and provides a solid input voltage to the converter The filter is shown in Figure 10 Capacitor C10 is used for common mode noise reduction YYY _ o 2 2 uH Vin C5 2 2 s O C10 Z 0 022 Figure 10 Input L C Filter Schematic Oscillation may occur if the converter input impedance Zin is lower than the LC filter output impedancel The converter input impedance can be approximated as a negative resistor using Equation 26 Zin dB Ohm 20 log T eq 26 lout The converter closed loop input impedance is ultimately determined by the converter feedback loop as well as the open loop input impedance However a resistor is a good approximation and will be used for our analysis Figure 11 shows the theoretical input filter output impedance and the approximated converter input impedance 40 p n a a a a E a E E a a E a E 30 Converter Input Impedance 20 10 MAGNITUDE dB LC Filter Output Impedance 40 102 108 104 105 106 FREQUENCY Hz Figure 11 LC Filter Output Impedance and Approximated Converter Input
19. time of M1 such that the voltage difference is reduced The Snubber limits the voltage across the Power Switch and helps reduce noise Design Procedure The converter is designed to operate at a maximum duty cycle DC of 40 and a primary peak current Ippx of 400 mA The required primary inductance Lp is calculated using Equation 1 Vin min x DC Lo In min eq 1 P fx IPPK Solving Equation 1 a primary inductance of 127 uH is required The transformer turns ratio E is calculated using Equation 2 Np _ Vin IPPK x RDS on x DC gt eq 2 Ns Vout V D1 x 0 8 DC where Vfp1 is the forward voltage drop across D1 and RDs on is the Power Switch on resistance Equation 2 relates the on time volt second product to the reset volt second product and adds a 20 dead time to insure the converter operates in discontinuous mode Solving Equation 2 assuming a 0 5 V drop across D1 Np _ 85V 0 4A x 7Q x 0 4 gt eq 3 Ns 12V 0 5 V x 08 0 4 a turns ratio greater than 2 58 is required A turns ratio of 2 78 is selected A maximum stress voltage of 110 V across the primary switch during the turn OFF period is calculated using Equation 4 N Vstress Vin max N x Vout VD1 eq 4 The voltage is significantly below the 200 V maximum rating of the NCP1030 internal Power Switch The transformer winding arrangement includes a split primary with bifilar secondaries The
20. transformer can be ordered from Coilcraft under part number B0226 E Table 2 summarizes the specifications of the transformer Table 2 TRANSFORMER SPECIFICATIONS Resonant Frequency O o 3 8 MHZ typ Main Output Two main factors voltage ripple and frequency compensation are considered for the selection of the output capacitor Cout This section will focus on voltage ripple while frequency compensation is covered in a latter section The output capacitor provides the load current during the switch ON time If the target voltage droop is known Cout is calculated using Equation 5 ee lout x 1 DC Gas f x Vdroop Solving Equation 5 a maximum voltage droop of 50 mV requires a 7 4 uF capacitor However Cout may be increased to facilitate frequency compensation The secondary peak current Ispx and the diode blocking voltage Vblock determine the selection of rectification diodes D1 and D2 The primary peak current and transformer turns ratio determine the secondary peak current as given by Equation 6 N ISPK IPPK x lt gt eq 6 Ns www BD Fif tom ON NCP1030GEVB The voltage across the rectification diode is given by Equation 7 N Vblock Vout Vin max X x eq 7 Solving Equations 6 and 7 the rectification diode needs to handle 1 11 A and 39 34 V In addition to the voltage calculated using equation 7 voltage spikes during switching transitions need to be considered when selecting the bl
21. us reducing power consumption The regulator can be powered directly from the input line e Internal Error Amplifier Allows the implementation of an isolated supply using primary side regulation without the need for an optocoupler e Internal Cycle by Cycle Current Limit Eliminates the need for external sensing components The programmed current limit is 500 mA ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL e Proprietary Active Leading Edge Blanking LEB Circuit Provides better current limit control compared to a fixed blanking period The active LEB circuit masks the current signal during the Power Switch turn ON transition Individual Line Undervoltage and Overvoltage UV OV Detectors with Hysteresis Eliminate the need for external supervisory function The UV OV detectors can be disabled if not needed e Single Capacitor Oscillator Eliminates traditional timing resistor Oscillator is optimized for operation up to 1 0 MHz e Internal 2 Voltage Reference Eliminates the need for an external bypass capacitor e Thermal Shutdown Circuit Protects the device in the event the maximum junction temperature is exceeded Design Specifications An isolated bias supply for a telecom system is designed and implemented using the NCP1030 The supply delivers 2 0 W at 12 V The converter specifications are listed in Table 1 Table 1 BIAS SUPPLY SPECIFICATIONS acetic om ouput Power ea 2ow
22. ut No Load Vout Full Load Vout No Load Line regulation is measured below 0 5 and load regulation is measured below 8 Figure 17 shows the output voltage variation to output current under several input voltage conditions RegLOAD eq 28 175 200 0 25 50 75 100 125 150 lout OUTPUT CURRENT mA Figure 17 Output Voltage vs Output Current The dynamic response of the converter is evaluated stepping the load current from 50 to 75 and from 75 to 50 of Tout max The step load transient responses are shown in Figures 18 and 19 lout Output Current 20 mA DIV 87 mA so Vout 11 6 V Vout Output Voltage 50 mV DIV 50 ms DIV Figure 18 Output Voltage Response to a Step Load from 87 mA to 127 mA r a poeren S i Vin 48V gt Qo ft T 2 lout 127mMA gt T 4 o Vout Output Voltage 50 mV DIV Vout 11 45 V 50 ms DIV Figure 19 Output Voltage Response to a Step Load from 127 mA to 87 mA Output voltage ripple is measured at 25 mV for an output current of 170 mA It is significantly below the 50 mV target The output voltage ripple waveform is shown in Figure 20 www BD Tt tom ON Vout Output Voltage 20 mV DIV NCP1030GEVB lt Vin 48 V lout 170 MA 2 0 us DIV Figure 20 Output Voltage Ri
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