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HT80C51 User Manual

1. 62 Format and States the Slave Receiver 63 Format and States of the Slave Transmitter 64 Simultaneous Repeated START Conditions from 2 71 Forced Access to a Busy I2C Bus sss ener enne 72 Recovering from a Bus Obstruction Caused by a Low Level on SDA 73 SPI block diagram Gah ade tdem ine hee ait Data Clock Timing Diagram 78 SPI Single Master Single Slave Configuration 79 Functional Diagram of the Watchdog Timer sss 81 O Philips Electronics N V 2005 Page 131 of 132 Handshake Solutions HT80C51 User Manual Document History A3 Document History Date Author 17 3 2005 UK 22 3 2005 UK 12 4 2005 UK 25 4 2005 UK 25 4 2005 UK 30 05 2005 CV UK 27 6 2005 CV Page 132 of 132 Version No 1 1 1 1 1 1 3 14 1 5 1 6 1 7 Change Report First Draft HT80C51 block diagram added Initialization chapters for interrupt controller timers 0 1 and UART added Pins ExtlntO n and Extlnt1 n used as external interupt inputs for the timers 0 1 Clock input for timers and serial interfaces is the core clock pin CCIK
2. instruction control stack pointer HT80C51 register peripheral special function registers peripheral logic code address external data address buffer register incrementer v O external logic Figure 1 Philips Electronics N V 2005 HT80C51 Architecture CPU centered Page 7 of 132 HT80C51 User Manual Handshake Solutions Introduction to HT80C51 Modules external HT80C51 int req i interrupt controller J int ack o up to 64Kbytes intO 3 program memory timer O 1 t1 overflow up to 64Kbytes UART external data memory up to 256bytes internal data memory Watchdog handshake peripherals optional synchronous synchronous 22I ipheral SFR bus brid GPIO peripherals us bridge HT SFR bus Figure 2 HT80C51 Achitecture Page 8 of 132 Philips Electronics N V 2005 HT80C51 User Manual Memory Organization Memory Map Handshake Solutions 2 Memory Organization The 80C51 architecture comprises several different and separated address areas The following chap ter describes the map of these memory areas which are described in more detail thereafter 2 1 Memory 80C51 has separate address spaces for program memory external and internal data memory Figure 3 shows a map of th
3. Long Call LCALL calls a subroutine located at the indicated address The instruction adds three to the pro gram counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the Stack Pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64k byte program memory address space No flags are af fected Initially the Stack Pointer equals 07H The label SUBRTN is assigned to program memory loca tion 1234H After executing the instruction LCALL SUBRTN at location 0123H the Stack Pointer will contain 09H internal RAM locations 08H and 09H will contain 26H and 01H and the PC will contain 1235H 3 2 0 0 0 1 0 0 1 0 addr15 addr8 addr7 addrO LCALL lt 3 SP lt SP 1 SP lt PC7 0 SP lt SP 1 SP lt PC15 8 PC lt addr15 0 Page 110 of 132 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions LJMP addr16 Function Long Jump Description LJMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively wi
4. the result reversed order DCO EY R6 RS R4 ROP E RIL RO N 43 DTXT DTXT DTXT DTXT DTXT DISA reverse byte order for read out will result with value 06h in RO 65h in R1 etc Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set 80C51 Instruction Set Summary Handshake Solutions 6 80C51 Family Instruction Set 6 1 80 51 Instruction Set Summary Instructions that affect flag settings Instruction Flag Instruction Flag C OV AC C OV AC ADD X X X CLR C 0 ADDC X X X C X SUBB X X X C bit x MUL 0 X ANL C bit x DIV 0 X ORL C bit x DA x ORL C bit X RRC X MOV C bit x RLC x CJNE x SETBC 1 1 Note that operations on SFR byte address 208 or bit addresses 209 215 i e the PSW or bits in the PSW will also affect flag settings Notes on instruction set and addressing modes Rn Register R7 RO of the currently selected Register Bank direct 8 bit internal data location s address This could be an Internal Data RAM location 0 127 or a SFR i e I O port control register status register etc 128 255 Ri 8 bit internal data RAM location 0 255 addressed indirectly through register R1 or RO data 8 bit constant included in the instruction data 16 16 bit constant included in the instruction addr 16 16 bit destination address Used by LCALL and LJMP A branch can be anywhere within the 64k byte Program Memory address
5. 10 Lower 128 bytes of RAM direct and indirect addressing 11 gue AUR 13 Interrupt Response Timing Diagram ssseseeee emm emm ene enn 24 Interrupt Sources From the Timers 0 1 28 Timer Counter mode 0 13bit counter 29 Timer counter Mode 2 8bit auto reload sssssssssssssseeeeees 30 Timer counter 0 mode 3 Two 8bit 30 Block Diagram of Serial Interface in Mode 0 ene 37 Block Diagram of Serial Interface in Mode 1 2 and 3 39 Typical lC Bus GONTIQUIATION eea a ata eate tee 48 Data Transfer the 1 BUS ovi scito tuts 48 2 Bus Serial Interface Block iHe etta 50 Arbitration 51 Serial Clock 2 ennemis 52 Serial Input Output Configuration ssssssssssessseeeeen enne 54 Shift in and Shift out Timing sete ee 55 Format and States in the Master Transmitter 61 Format and States in the Master Receiver
6. 3 101 clk i 1 8432 MHz Table 7 Timer 1 Generated Commonly Used Baud Rates 5 3 4 4 More About Mode 0 Serial data enters at input pin sio rxd and exits through output pin sio txd o Pin sio clk o outputs the shift clock during transmission 8 bits are transmitted received LSB first The baud rate is fixed at the clock input sio cik i Figure 12 shows a simplified functional diagram of the serial port in Mode 0 This mode should be used in half duplex operation only Transmission is initiated by any instruction that uses SBUF as a destination register SEND enables the output of the shift register to be routed to output pin sio txd o and also enables shift clock to the output pin sio clk o The output data is always stable on the rising edge of the shift clock Every clock cycle in which SEND is active the contents of the transmit shift are shifted to the right one posi tion Reception is initiated by the condition REN 1 and RI 0 RECEIVE enables the shift clock to the out put pin sio clk o The input data on pin sio rxd i is sampled on the falling edge of the shift clock Every clock cycle in which RECEIVE is active the contents of the receive shift register are shifted to the left one position At the 8th shift clock cycle RI is set and RECEIVE is cleared Clearing bit REN during reception immediately stops the receiver Page 36 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules
7. Table 2 Interrupt Signals Vectors and Priorities 5 1 3 2 How Interrupts Are Handled The interrupt flags are sampled at every start of an instruction The samples are polled at the start of the following instruction If one of the flags was in a set condition at the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 interrupt of equal or higher priority level is already in progress 2 The instruction in progress is RETI or any write to the IENx or IPx registers Any of these two conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that if the instruction in progress is RETI or any access to IENx or IPx then at least one more instruction will be executed before any interrupt is vectored to The polling cycle is repeated with each new instruction and the values polled are the values that were present at the start of the previous instruction Note that if an interrupt flag is active but not being re sponded to for one of the above conditions if the flag is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle is new O Philips Electronics N V 20
8. lt A DPTR MOVC A A PC Bytes Cycles Encoding Operation 1 2 1 0 0 OJO O 4 1 MOVC PC lt PC 1 lt PC MOVX lt dest byte gt lt src byte gt Function Description Example MOVX A Ri Bytes Cycles Encoding Operation Page 116 of 132 Move External The MOVX instructions transfer data between the Accumulator and a byte of external data mem ory hence the X appended to MOV There are two types of instructions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of RO or R1 in the current register bank provide an eight bit address Eight bits are sufficient for external I O expansion decoding or for a relatively small RAM array For somewhat larger arrays the SFR XRAMP be used to define higher order address bits These pins would be set by a move instruction to XRAMP preceding the MOVX In the second type of MOVX instruction The Data Pointer generates a sixteen bit address This form is faster and more efficient when accessing very large data arrays up to 64k bytes since no additional instructions are needed to set up the output ports It is possible in some situations to mix the two MOVX types A large RAM array with its high order address lines can be addressed via the Data Pointer or with code to output high order address bits to XRAMP followed by a MOVX in
9. of Internal Data 2 2 Accessing Program Memory The program memory is readable only and can be accessed by two access methods Instruction fetches using the 16bit program counter PC as the address or move code instructions using the 16bit data pointer MOvC DPTR or again the PC MOVC as reference 2 3 Accessing External Data Memory In contrast to the program memory the external data memory is read and writeable Accesses to ex ternal data memory can be done thru the MOVX instruction only which comes in two flavors MOVX QDPTR uses the data pointer to form the 16bit address MOVX Ri uses one of the index registers to form the lower 8bits of the address with the upper part of the address being defined by the SFR XRAMP The first variant is usually faster and a more general access method The second variant MOVX Ri can be used as a paging access to a rather small area of data Page 10 of 132 Philips Electronics N V 2005 HT80C51 User Manual Memory Organization Internal Data Memory Direct and Indirect Address Area Handshake Solutions 2 4 Internal Data Memory Direct and Indirect Address Area The lower 128 bytes of RAM can be accessed by both direct and indirect addressing and they can be divided into three segments as listed below and shown in Figure 5 7FH 30H 2FH 20H 1FH 18H 17H 10H 08H 07H 00H scratch pad area bit addressable segment bit
10. 1 If timer 1 is used to generate the baudrate and the serial interface is used in modes 1 2 or 3 then the baudrate is doubled 0 baudrate is not influenced PCON 6 0 See description of PCON register in CPU section 5 3 3 Interrupts The serial interface has two flags to indicate interrupt conditions TI for transmit interrupts and RI for receive interrupts However there is only one interrupt output that has to be shared by these interrupt sources So if any of the flags TI and RI is set an interrupt request will be generated The software has to check then which source was the cause interrupt Description interrupt Source signal UART TI Transmit interrupt flag int4 RI Receive interrupt flag The logical OR of TI and RI generates the interrupt request signal Note To comply with the standard specification the serial interface does not support transmit buffering So the transmit interrupt is issued when the transmission has been completed instead of as soon as the contents of SBUF are copied to the transmit shift register Interrupt flags are set by hardware and have to be reset by software 5 3 4 Operation The UART function is full duplex meaning it can transmit and receive simultaneously It is also re ceive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the register However if the first byte still hasn t been read by the time re cepti
11. Standard Serial Interface SIOO Handshake Solutions HT SFR bus SBUF read only SBUF write only sio rxd i gt sio txd o Sio dk i int 4 Sio clk o SEND RECEIVE Sio active o RECEIVE Sio modeO o 1 Figure 12 Block Diagram of Serial Interface in Mode 0 5 3 4 5 More About Mode 1 10 bits are transmitted through sio txd received through sio rxd i a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is derived from the overflow rate of timer 1 Figure 13 shows a simplified func tional diagram of the serial port in mode 1 Transmission is initiated by any instruction that uses SBUF as a destination register Transmission actually commences immediately after the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal After sending the start bit and 8 data bits the bit is set and the stop bit is sent Reception is initiated by the detection of a 1 to O0 transition at sio rxd i For this purpose sio rxd sampled at a rate of 16 times whatever baud rate has been established When a transi tion is detected the divide by 16 counter is immediately reset thus it aligns its rollovers with the boundaries of the incoming bit times At the 7th 8th and 9th counter states of each bit
12. Handshake Solutions SOLUTI o NS Handshake Solutions HT80C51 User Manual Document Information Document Information Document Title Date of Creation Date of last change File name Status Version Number Client Target Audience Summary Contact HT80C51 User Manual 27 06 2005 27 06 2005 HT80C51 UserManual doc Release 1 7 System architects and software developers using the HT80C51 This document describes and illustrates the general architecture the standard peripherals and the instruction set for the HT80C51 Handshake Solutions High Tech Campus Prof Holstlaan 4 phone 31 40 27 46114 Mailbox WAMO1 fax 31 40 27 46526 5656 AA Eindhoven info handshakesolutions com The Netherlands www handshakesolutions com 2005 Koninklijke Philips Electronics N V All rights reserved Reproduction in whole or in part in any way shape or form is prohibited without the written consent of the copyright owner All information in this document is subject to change with out notice Page 2 of 132 Philips Electronics N V 2005 HT80C51 User Manual Table of Contents Handshake Solutions Table of Contents 1 Introduction to HT80C51 5 eterne A E E DARIE AAN AIS TAL AARONA E VARIERES EN TIRTA 5 1 1 Compatibility i a OA A E RE EE A T 5 1 2 MOG UNOS R E EE A T E E T 6 2 Memory Organization seisein E ERANA PE A EANNAN DE Yo a RE E
13. i8H 1FH PSW 3 RSO Register Bank selector bit 0 see note PSW 2 OV Overflow Flag PSW 1 Usable as a general purpose flag PSW 0 P Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of 1 bits in the accumulator that means even parity 2 5 4 Stack Pointer SP The Stack Pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07H after a reset This causes the stack to begin at locations 08H Page 14 of 132 Philips Electronics N V 2005 HT80C51 User Manual Memory Organization Special Function Registers Handshake Solutions SP Stack Pointer addr 81H reset value 07H bits 7 6 5 4 3 2 1 0 2 5 5 Data Pointer DPTR DPH DPL The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function is to hold a 16 bit address for MOVX and MOVC instructions It may be manipulated as a 16 bit register or as two independent 8 bit registers DPH Data Pointer High byte addr 83H reset value 00H bits 7 6 5 4 3 2 1 0 DPH DPL Data Pointer Low byte addr 82H reset value 00H bits 7 6 5 4 3 2 1 0 DPL 2 5 5 1 Dual data pointer option HT80C51_CPU_DUALDPTR Optional two data pointer registers can be implemented DPTR0 and DPTR1 Only one data pointer can be used at a time This can be selected by bit DPS in SFR PCON
14. in internal RAM locations OAH and OBH respectively 2 2 1 1 0 0 0 0 0 0 direct address PUSH SP lt SP 1 SP lt direct Page 121 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions RET Function Return from subroutine Description RET pops the high and low order bytes of the PC successively from the stack decrementing the Stack Pointer by two Program execution continues at the resulting address generally the instruc tion immediately following an ACALL or LCALL No flags are affected Example The Stack Pointer originally contains the value OBH Internal RAM locations OAH and OBH contain the values 23H and 01H respectively The instruction RET will leave the Stack Pointer equal to the value 09H Program execution will continue at location 0123H Bytes 1 Cycles 2 Encoding 0 0 1 0 0 0 1 0 Operation RET PC15 8 lt SP SP lt SP 1 PC7 0 lt SP SP lt SP 1 RETI Function Return from interrupt Description RETI pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed The Stack Pointer is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution contin
15. interrupt disabled 1 interrupt enabled IPO Interrupt priority register O addr B8H reset value 00H IP bits 7 6 5 4 3 2 1 0 mos es eso Pr exi Pro bit symbol Function IPO 7 reserved IPO 6 Priority level for interrupt input int req i 6 5 51 Priority level for I2C interrupt if available or interrupt input int req i 5 4 ESO Priority level for UART interrupt if available or interrupt input int req i 4 IPO 3 ET1 Priority level for timer 1 overflow interrupt if available or interrupt input int req i 3 2 EX1 Priority level for external interrupt from timer 1 IE1 if available or interrupt input int req i 2 IPO 1 ETO Priority level for timer 0 overflow interrupt if available or interrupt input int req i 1 IPO 0 EXO Priority level for external interrupt from timer 0 IE0 if available or interrupt input int req i 0 Bit values 0 low priority 1 high priority O Philips Electronics N V 2005 Page 21 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Interrupt Controller IP1 Interrupt priority register 1 addr reset value 00H bits 7 6 5 4 3 2 1 0 bit symbol Function IP1 7 Priority level for interrupt input int req i 14 IP1 6 Priority level for interrupt input int req i 13 IP1 5 Priority level for interrupt input int req i 12 IP1 4 Priority level for interrupt input int req i 11 IP1 3 Priority lev
16. lt rel addr gt Function Description Example DJNZ Rn rel Bytes Cycles Encoding Operation Decrement and Jump if Not Zero DJNZ decrements the location indicated by 1 and branches to the address indicated by the sec ond operand if the resulting value is not zero An original value of OOH will underflow to OFFH No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Internal RAM locations 40H 50H and 60H contain the values 01H 70H and 15H respectively The instruction sequence DJNZ 40H LABEL 1 DJNZ 50H LABEL 2 DJNZ 60H LABEL 3 will cause a jump to the instruction at LABEL 2 with the values 00h 6FH and 15H in the three RAM locations The first jump was not taken because the result was zero This instruction provides a simple was of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles ith a single instruction The in struction sequence MOV R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE will toggle P1 7 eight times
17. 2005 HT80C51 User Manual Peripheral Modules Timers 0 and 1 Handshake Solutions 5 2 4 Operation The timer or counter function is selected by control bits C Tx in the special function register TMOD These two timer counters have four operating modes which are selected by bit pairs M1 M0 in TMOD Modes 0 1 and 2 are the same for both timers counters Mode 3 is different The four operating modes are described in the following text 5 2 4 1 Mode 0 Putting either timer into mode 0 makes it look like an 8048 timer which is an 8 bit counter with a di vide by 32 prescaler Figure 9 shows the mode 0 operation as it applies to timer 1 In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the timer interrupt flag TF1 The counted input is enabled to the timer when TR1 1 and either GATE1 0 or pin 201 inti n i 1 Setting GATE1 1 allows the timer to be controlled by external input t01 inti n facilitate pulse width measurements TR1 is a control bit in the spe cial function register TCON GATE1 is in TMOD The 13 bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are indeterminate and should be ignored Setting the run flag TR1 does not clear the registers Mode 0 operation is the same for the timer 0 as for timer 1 Substitute TRO TF0 GATEO C TO tO count i 01 intO n for the correspondi
18. Arbitration lost in SLA R W or Data bytes Table 10 O Philips Electronics N V 2005 no S1DAT action or no S1DAT action or no S1DAT action Load data byte or no S1DAT action or no S1DAT action or no S1DAT action Load data byte or no S1DAT action or no S1DAT action or no S1DAT action Load data byte or no S1DAT action or no S1DAT action or no S1DAT action No S1DAT action or no S1DAT action Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset I2C bus will be released not addressed slave will be entered START condition will be tr
19. Cycles 2 Encoding 4 14 0 1 dir addr src dir addr dest Operation MOV direct direct MOV direct Ri Bytes 2 Cycles 2 Encoding 4 1 1 i direct address Operation MOV direct Ri MOV direct data Bytes 3 Cycles 2 Encoding O 1 1 1 0 1 0 1 direct address immediate data Operation MOV direct data MOV Ri A Bytes 1 Cycles 1 Encoding 1 1 1 1 10 1 1 i Operation MOV Ri lt Philips Electronics N V 2005 Page 113 of 132 Handshake Solu HT80C51 User Manual tions 80C51 Family Instruction Set Instruction definitions MOV Ri direct Bytes Cycles Encoding Operation 2 2 1 0 1 0 0 1 1 i direct address MOV Ri lt direct MOV Ri data Bytes Cycles Encoding Operation 2 1 0 1 1 1 0 1 1 i immediate data MOV Ri data MOV lt dest bit gt lt src bit gt Function Description Example MOV C bit Bytes Cycles Encoding Operation MOV bit C Bytes Cycles Encoding Operation Page 114 of 132 Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly address
20. DKEY B4h MOV DKEY B3h MOV DKEY B2h MOV DKEY Blh MOV DCON 00h Write plain text into DTXT MONI DTE 37h MOVE DIEL D3h 8Ah IWON FCh MOV DTXT A9h MOV DTXT 3Fh MOMED TA 9Dh MOV DTXT 3Dh Invoke a single DES encrytion MOV DCON 4 the generated cipher text is F64E59B5B5A36506 Reading the result MOM DIAT MOVER TEDE MOVER MON 9 MOV R4 DTXT MOVERS MOVER MON 2077 IDE will result with value 06h in RO 65h in R1 etc Philips Electronics N V 2005 Page 85 of 132 Handshake Solutions HT80C51 User Manual Peripheral Modules Triple DES Converter Sometimes the text is in a different reversed byte order Then following sequence can be used Store key in KEYO Page 86 of 132 DK DK DK DK DK DK DK Ei Ed Ed bd EH Db ee 5 15 bs O Write plain DTX DTX DTX DTX DTX DTX DTX DTX DCO the byte order of the keys cannot be changed Y B8h Y B7h Y Boh Y BSh Y B4h Y B3h Y B2h Blh N 00h text into DTXT reversed order T 3Dh T 9Dh T 3Fh T A9h T FCh T 8Ah T D3h T 37h N 3 reverse byte order Invoke a single D MOV DCON 4 ES encrytion the generated cipher text is F64E59B5B5A36506 Reading
21. lt A C Ri 2 1 0 0 10 1 0 0 immediate data SUBB lt A C data O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions SWAP A Function Description Example Bytes Cycles Encoding Operation XCH A lt byte gt Function Description Example A Rn Bytes Cycles Encoding Operation A direct Bytes Cycles Encoding Operation XCH A Ri Bytes Cycles Encoding Operation Philips Electronics N V 2005 Swap nibbles within the Accumulator SWAP A interchanges the low and high order nibbles four bit fields of the Accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are af fected The Accumulator holds the value OC5H 11000101B The instruction SWAP A leaves the Accumulator holding the value 5CH 01011100B 1 1 1 1 0 0 0 1 0 0 SWAP A3 0 lt gt A7 4 Exchange Accumulator with byte variable XCH loads the Accumulator with the contents of the indicated variable at the same time writing the original Accumulator contents to the indicated variable The source destination operand can use register direct or register indirect addressing RO contains the address 20H The Accumulator holds the value 3FH 00111111B Internal RAM location
22. now SFR XRAMP added Description of C interface added Names of pins adapted Description of SPI and DES added Block diagrams of HT80C51 changed Chapter about clocks added SFR map updated Reset values updated Option names added Description of SIO condensed Minor changes in description of SIO Description of DKEY for the DES changed Some typos removed Update of illustrations Ch 1 5 4 and 5 8 end and formats Description of DES updated and extended Update of illustrations Ch 5 5 5 6 Update of figure 6 and table 7 O Philips Electronics N V 2005 This datasheet has been downloaded from www EEworld com cn Free Download Daily Updated Database 100 Free Datasheet Search Site 100 Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www EEworld com cn Datasheets Cannot Be Modified Without Permission Copyright O Each Manufacturing Company
23. see below All instructions using the DPTR DPL or DPH use either DPTRO or DPTR1 as selected by SFR bit DPS The DPS bit should be saved by software when switching between DPTRO and DPTR1 within procedures or interrupt routines 2 5 6 Power Saving Modes PCON The HT80C51 has two power reducing modes Idle and Power Down The input through which backup power is supplied during these operations is VDD In the Idle mode IDL 1 the oscillator continues to run and the Interrupt Serial Port and Timer blocks continue to be clocked but the clock signal is gated off to the CPU In Power Down PD 1 the oscillator is frozen Since switching on or off the oscillator is done outside the microcontroller dedicated output pins indi cate idle mode cpu idle and power down cpu powerdown o External circuits needs to ob serve these signals to switch off the clocks in power down or to change the supply voltage Setting bits in Special Function Register PCON activate the Idle and Power Down Modes O Philips Electronics N V 2005 Page 15 of 132 HT80C51 User Manual Handshake Solutions Memory Organization Special Function Registers PCON Power Control Register addr 87H reset value 0XX00000 Bits 7 6 5 4 3 2 1 0 svo oes cr cro w Bit symbol Function PCON 7 SMOD Double baud rate see chapter 5 3 Standard Serial Interface 1 If timer 1 is used to generate the baudrate and the serial interface is us
24. tially holds 30H representing the digits of 30 decimal the the instruction sequence ADD 99 DA A will leave the carry set and 29H in the Accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 1 1 1 1 0 1 0 1 0 0 DA contents of Accumulator are BCD IF A3 0 gt 9 v 1 THEN A30 lt A350 6 AND IF A7 4 gt 9 v C 1 THEN A7 4 lt A74 6 O Philips Electronics N V 2005 Page 101 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions DEC byte Function Decrement Description The variable indicated is decremented by 1 An original value of 00H will underflow to OFFH No Example DECA Bytes Cycles Encoding Operation DEC Rn Bytes Cycles Encoding Operation DEC direct Bytes Cycles Encoding Operation DEC Ri Bytes Cycles Encoding Operation flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original data will be read from the output data latch not the input pin Register O contains 7FH 01111111B Internal RAM locations 7EH and 7FH contain 00H and 40H respectively The instruction sequence DEC RO DEC RO DEC RO will leave register 0 set to 7EH and inte
25. will be returned during the acknowledge clock pulse on SCL when A data has been received while SIO1 is in the Master Receiver mode A data byte has been received while SIO1 is in the addressed Slave Receiver mode When SIO1 is in the addressed Slave Transmitter mode state C8H will be entered after the last serial is transmitted see Figure 11 When SI is cleared SIO1 leaves state C8H enters the not addressed Slave Receiver mode and the SDA line remains at a high level In state C8H the AA flag can be set again for future address recogni tion When SIO1 is in the not addressed Slave mode its own slave address and the general call address are ignored Consequently no acknowledge is returned and a serial interrupt is not requested Thus SIO1 can be temporarily released from the I2C bus while the bus status is monitored While SIO1 is released from the bus START and STOP conditions are detected and serial data is shifted in Ad dress recognition can be resumed at any time by setting the AA flag If the AA flag is set when the part s own Slave address or the general call address has been partly received the address will be recognized at the end of the byte transmission Page 56 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions The Clock Rate Bits CRO CR1 and CR2 These three bits determine the serial clock frequency when SIO1 is in a Master mode
26. 1 256 reload value timer 1 0 255 0 254 0 253 0 251 0 250 reload value timer 1 mode 2 0 0 0 0 1 1 1 1 A002 gt 00 2 0 Table 9 Serial Clock Rates needs update NOTES 1 These frequencies exceed the upper limit of 100 kHz of the I2C bus specification and cannot be used in an I2C bus application 2 AtfOSC 24 MHz 30 MHz the maximum 12C bus rate of 100 kHz cannot be realized due to the fixed divider rates 5 5 4 4 More Information on SIO1 Operating Modes The four operating modes are e Master Transmitter e Master Receiver e Slave Receiver e Slave Transmitter Data transfers in each mode of operation are shown in Figure 21 to Figure 24 O Philips Electronics N V 2005 Page 57 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 These figures contain the following abbreviations Abbreviation Explanation S Start condition SLA T bit slave address R Read bit high level at SDA W Write bit low level at SDA A Acknowledge bit low level at SDA A Not acknowledge bit high level at SDA Data 8 bit data byte P Stop condition In Figure 21 to Figure 24 circles are used to indicate when the serial interrupt flag is set The num bers in the circles show the status code held in the S1STA register At these points a service routine must be executed to continue or complete the serial transfer These service routines are not critical s
27. 3 5 1 Generating Baud Rates Serial Port in Mode 0 Mode 0 has a fixed baud rate which is the frequency at clock input sio_clk_i run the serial port in this mode none of the Timer Counters need to be set up Only the SCON register needs to be de fined Baud Rate dodici Serial Port in Mode 1 Mode 1 has a variable baud rate Timer 1 generates the baud rate For this purpose Timer 1 is used in mode 2 Auto Reload Refer to the initialization section of the timer description Chapter 5 2 5 Kx ck i 32 x 256 TH1 If SMOD 0 then K 1 If SMOD 1 then K 2 SMOD is in the PCON register Baud Rate Most of the time the user knows the baud rate and needs to know the reload value for TH1 Kx foo ck i 32x baud rate TH1 must be an integer value Rounding off TH1 to the nearest integer may not produce the desired baud rate In this case the user may have to choose another crystal frequency THl 256 Since the PCON register is not bit addressable one way to set the bit is logical ORing the PCON register 1 6 ORL 80H The address of PCON is 87H Serial Port in Mode 2 The baud rate is fixed in this mode and is 1 32 or 1 64 of the frequency at clock input sio clk i depending on the value of the SMOD bit in the PCON register Page 40 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Standard Serial Interface SIOO Handshake Solutions In this mo
28. 5 4 1 OPNS inier e e fos cede di oe nd 42 5 4 2 Special function registers POUTx PINX 42 5 4 3 a Evie aah ie dale bee eerie 43 5 4 4 Op ration tin wae Ai tis ie tino te eade 43 5 5 RG Interface SIOT ian euin oe on Seu a b MUS molten ctt dde ees 44 5 5 1 ODtlOnS ten e pt 44 5 5 2 Special function registers S1CON S1ADR S1DAT S1STA 44 5 5 3 derisum uu I LE 46 5 5 4 8 o ep T 46 5 5 5 Slave only Version e oe t tdt att dete aine 73 5 5 6 Application notes nere 73 5 6 Serial Peripheral Interface nennen 74 5 6 1 OPUONS n LEE 74 5 6 2 Special function registers SPCR SPSR 74 5 6 3 a Roel eevee toed weeded andl eee eee ee 76 5 6 4 nats ttt eet det ne te St cee de 76 5 7 Watchdog Timer under development nnns 80 5 7 1 P D 80 5 7 2 Special function registers T3 sse enm 80 5 7 3 dtd i e a edes 80 5 7 4 Operation EM 80 5 8 Triple DES Converter 2 82 5 8 1 ODtOnS 82 5 8 2 Special function registers D
29. DEC A Decrement Accumulator 1 1 DEC Rn Decrement Register 1 1 DEC direct Decrement direct byte 2 1 DEC Ri Decrement indirect RAM 1 1 INC DPTR Increment Data Pointer 1 2 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 4 DA A Decimal Adjust Accumulator 1 1 LOGICAL OPERATIONS ANL A Rn AND Register to Accumulator 1 1 ANL A direct AND direct byte to Accumulator 2 1 ANL A Ri AND indirect RAM to Accumulator 1 1 ANL A data AND immediate data to Accumulator 2 1 ANL direct A AND Accumulator to direct byte 2 1 ANL direct data AND immediate data to direct byte 3 2 ORL A Rn OR register to Accumulator 1 1 ORL A direct OR direct byte to Accumulator 2 1 ORL A Ri OR indirect RAM to Accumulator 1 1 ORL A data OR immediate data to Accumulator 2 1 ORL direct A OR Accumulator to direct byte 2 1 ORL direct Zdata OR immediate data to direct byte 3 2 XRL A Rn Exclusive OR register to Accumulator 1 1 XRL A direct Exclusive OR direct byte to Accumulator 2 1 Page 88 of 132 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set 80C51 Instruction Set Summary Handshake Solutions MNEMONIC DESCRIPTION BYTE MACHINE CYCLES LOGICAL OPERATIONS continued XRL A Ri Exclusive OR indirect RAM to Accumulator 1 1 XRL A data Exclusive OR immediate data to Accumulator 2 1 XRL direct A Exclusive OR Accumulator to direct byte 2 1 XRL direct data Exclusive OR immediate data to direct byte 3 2 CLR A Clear Accu
30. Figure 21 and Figure 22 If the STA flag in S1CON is set by the routines which service these states then if the bus is free again a START condition state 08H is transmitted without intervention by the CPU and a retry of the total serial transfer can commence Forced Access to the I2C Bus In some applications it may be possible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a tempo rary short circuit between SDA and SCL If an uncontrolled source generates a superfluous START or masks a STOP condition then the I2C bus stays busy indefinitely If the STA flag is set and bus access is not obtained within a reasonable amount of time then a forced access to the I2C bus is possible This is achieved by setting the STO flag while the STA flag is still set No STOP condition is transmitted The SIO1 hardware behaves as if a STOP condition was received and is able to transmit a START condition The STO flag is cleared by hardware see Figure 26 1 I RECEPTION OF THE OWN SLAVE BOTH MASTERS CONTINUE I I ADDRESS AND ONE OR MORE 5 BEI ye WITH SLA TRANSMISSION ACKNOWLEDGED 08H 28H OTHER MASTER SENDS REPEATED START CONDITION EARLIER Figure 25 Simultaneous Repeated START Conditions from 2 Masters O Philips Electronics N V 2005
31. Manual Peripheral Modules 12C Interface 5101 Handshake Solutions Arbitration and Synchronization Logic In the Master Transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and SIO1 immediately changes from master transmitter to slave receiver SIO1 will continue to output clock pulses on SCL until transmission of the current serial byte is com plete Arbitration may also be lost in the Master Receiver mode Loss of arbitration in this mode can only occur while SIO1 is returning a not acknowledge logic 1 to the bus Arbitration is lost when another device on the bus pulls this signal LOW Since this can occur only at the end of a serial byte SIO1 generates no further clock pulses The arbitration procedure is illustrated in Figure 17 The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device If two or more master devices generate clock pulses the mark duration is determined by the device that generates the shortest marks and the space duration is determined by the device that generates the longest spaces Figure 18 shows the synchronization procedure A slave may stretch the space duration to slow down the bus master The space duration may also be stretched for handshaking pur
32. OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immedi ate The Accumulator holds 11000011B and register 0 holds OAAH 10101010B with the carry flag set The instruction ADDC A RO will leave 6EH 01101110B in the Accumulator with AC cleared and both the Carry flag and OV set to 1 ADDC lt A Rn direct address ADDC lt A C direct ADDC lt A Ri 2 1 0 0 1 1 0 1 0 0 immediate data ADDC lt A C data Page 93 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions AJMP addr11 Function Description Example Bytes Cycles Encoding Operation Absolute Jump AJMP transfers program execution to the indicated address which is formed at run time by con catenating the high order five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2k block of program memory as the fir
33. Peripheral Modules 12C Interface 5101 5 5 Interface SIO1 The Handshake Technology I2C referred to as HT I2C is a low power version of the standard 80C51 12 as used in the 8XC552 80C51 The HT I2C implementation offers several unique features which are detailed below e The HT I2C consumes almost zero stand by power while in sleep mode yet is immediately available for full speed full functional operation e The HT I2C has very low electromagnetic emission EME e The HT I2C has low supply current peaks thus facilitating integration with analog and RF cir cuitry e The HT I2C use a dedicated special function register HT SFR bus for interconnects with the HT80C51 micro controller 5 5 1 Options A master slave combination of the I2C interface can be ordered by option HT80C51 I2C A slave only I2C interface can be ordered by using option HT80C51 I2C SLAVEONLY 5 5 2 Special function registers STCON S1ADR S1DAT S1STA S1CON SIO1 control register addr D8H reset value 00H bits 7 6 5 4 3 2 1 0 ENS1 bit symbol Function S1CON 7 CR2 Clock rate bit 2 not implemented in slave only version S1CON 6 ENS1 SIO1 enable bit 1 S101 enabled 0 8101 disabled S1CON 5 STA STArt flag starts transmission not implemented in slave only version S1CON 4 STO STOp flag stops transmission S1CON 3 Sl Serial Interrupt set by hardware when an interrupt request is gener ated must be reset be software S1CON 2 AA Assert Ac
34. SPCR 0000 0100 SPSR 00H SPDR 00H DCON XX DKEY XX DTXT XX Note XX means no initialization on reset Table 1 80C51 SFR Reset Values O Philips Electronics N V 2005 HT80C51 User Manual Clocks CPU Cock Handshake Solutions 4 Clocks 4 1 CPU Cock 4 1 1 Clockless Aynchronous Cnfiguration A handshake circuit does not require a clock to work it simply adapts its speed to the environment other blocks supply voltage temperature etc This is a complete asynchronous mode of operation and our standard configuration of the core 4 1 2 Clock synchronization Option HT80C51 CPU SYNC Some applications or programs require a precisely defined timing behavior of the instruction execu tion for instance when timing or waiting loops are used For this case an optional synchronization feature is offered With this feature come two additional input pins 1 and cpu sync i cpu clk i delivers the machine clock and thus the speed of the CPU input cpu sync i decides whether the CPU should be synchronized to cpu 1 i or not e In synchronous mode cpu sync i 1 the CPU synchronizes with 1 i on a machine cycle basis after each instruction in such a way that the number of clock cycles for that instruc tion is the same as the number of machine cycles for a synchronous implementation Since there are no clock dividers attached cik i cycle equals to one machine cycle e n asynchron
35. The various serial rates are shown in Table 9 A 12 5 kHz bit rate may be used by devices that interface to the I2C bus via standard l O port lines which are software driven and slow 100 kHz is usually the maximum bit rate and can be derived from a 16 MHz 12 MHz or a 6 MHz oscillator A variable bit rate 0 5 kHz to 62 5 kHz may also be used if Timer 1 is not required for any other purpose while SIO1 is in a Master mode The frequencies shown in Table 9 are unimportant when SIO1 is in a Slave mode In the Slave modes SIO1 will automatically synchronize with any clock frequency up to 100 kHz The Status Register S1STA S1STA is an 8 bit read only special function register The three least significant bits are always zero The five most significant bits contain the status code There are 26 possible status codes When S1STA contains F8H no relevant state information is available and no serial interrupt is requested All other S1STA values correspond to defined SIO1 states When each of these states is entered a serial inter rupt is requested SI 1 A valid status code is present in S18TA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software bit rate kbit s at fici 23 62 5 256 27 54 71 107 224 31 63 83 3 125 192 37 75 100 150 160 6 25 17 25 31 960 50 100 133 200 250 120 100 200 267 400 500 60 0 24 62 5 0 49 62 5 0 65 55 6 0 98 50 0 1 22 52
36. able bit No other register or flag is affected The carry flag is originally set The data present at input Port 3 is 11000101B The data previously written to output Port 1 is 35H 00110101B The instruction sequence MOV P1 3 C MOV C P3 3 MOV P1 2 C will leave the carry cleared and change Port 1 to 39H 00111001B 1 0 1 0 0 0 1 0 bit address MOV C lt bit 1 0 0 1 0 0 1 0 bit address MOV bit C O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions MOV DPTR data16 Function Description Example Bytes Cycles Encoding Operation Load Data Pointer with a 16 bit constant The Data Pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte DPH is the high order byte while the third byte DPL holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once The instruction MOV DPTR 1234H will load the value 1234H into the Data Pointer DPH will hold 12H and DPL will hold 34H 3 2 1 0 0 1 0 0 0 0 imm data 15 8 imm data 7 0 MOV DPTR lt data15 0 DPH DPL lt data15 8 data7 0 MOVC A A lt base reg gt Function Description Example Move Code byte Th
37. byte of data the SPIF status bit is set in both the master and the slave devices When the controller reads SPDR a buffer is actually read The corresponding SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist In cases of overrun the byte that causes the overrun is lost O Philips Electronics N V 2005 Page 75 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Serial Peripheral Interface SPI A write to SPDR is not buffered the data is directly stored into the shift register for trans mission 5 6 3 Interrupts When a data transfer is completed bit SPIF SPSR 7 is set If SPIF 21 and SFR bit SPIE SPCR 7 is set an SPI interrupt on interrupt line int is generated SPIF has to be cleared by software by reading SPSR first and accessing SPDR afterwards 5 6 4 Operation Figure 28 shows a block diagram of the serial peripheral interface circuitry When a master device transmits data to a slave device via the MOSI line the slave device responds by sending data to the master device via the master s MISO line This implies full duplex transmission with both data out and data in synchronized with the same clock signal Thus the byte transmitted is replaced by the byte received and eliminates the need for separate transmit empty and receiver full status bits A single status bit SPIF is used to signify that the
38. call address will be recognized if S1ADR O logic 1 no S1DAT action or Switched to not addressed SLV mode no recog nition of own SLA or General call address A START condition will be transmitted when the bus becomes free no S1DAT action Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if STADR O logic 1 A START condition will be transmitted when the bus be comes free Last data byte in STDAT No S1DAT action or Switched to not addressed SLV mode no recog has been transmitted nition of own SLA or General call address AA 7 0 ACK has been no S1DAT action or Switched to not addressed SLV mode Own SLA returned will be recognized General call address will be recognized if S1ADR O logic 1 no S1DAT action or Switched to not addressed SLV mode no recog nition of own SLA or General call address A START condition will be transmitted when the bus becomes free no S1DAT action Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if STADR O logic 1 A START condition will be transmitted when the bus be comes free Table 13 Slave Transmitter mode O Philips Electronics N V 2005 Page 69 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 application software response status of the I2C bus to STCON next action taken by SIO1 hardware and SIO1 hardware to from S1DAT sra s
39. electromagnetic emission EME e The HT80C51 has low supply current peaks at least a factor five lower than traditional clocked implementations thus facilitating integration with analog and RF circuitry e The HT80C51 CPU consumes zero stand by power while in sleep mode yet is immediately available for full speed full functional operation e The HT80C51 has an asynchronous and optionally a synchronous mode of operation When both are present the actual mode can be dynamically selected on an instruction per instruction base This is controlled via a dedicated input e n asynchronous mode of operation the CPU runs at its natural speed and a slow core clock does not slow it down e In synchronous mode the CPU synchronizes with a clock on a machine cycle basis after each instruction in such a way that the number of clock cycles for that instruction is the same as the number of machine cycles for a synchronous implementation e The HT80C51 core is configurable and has a range of configuration options offering selective instantiations of 80C51 peripherals and customization of memory interfaces e The HT80C51 peripherals consume zero power when not actively used e Optional dual datapointer for more compact code e Optional MOVC protection only grants program code from lower program memory permission to read lower program memory 1 1 Compatibility The HT80C51 implementation is functionally compatible to the instruction set and
40. in Special Function Register SCON while the stop bit is ignored The baud rate is pro grammable to either 1 32 or 1 64 of the clock input s3o 1 i 3 11 bits are transmitted through sio txd received through sio rxd start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is de rived from the overflow rate of timer 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 5 3 4 2 Baud Rates The baud rate in mode 0 has a fixed relation to the clock input sio clk i Mode 0 Baud Rate fjocki The baud rate in Mode 2 depends on the value of bit SMOD in special function register PCON If SMOD 0 which is the value on reset the baud rate is 1 64 of the frequency on clock input sio clk i l f SMOD 1 the baud rate is 1 32 of the frequency at sio clk i A SMOD Mode 2 Baud Rate eas x The baud rates Modes 1 and 3 are determined by the Timer 1 overflow rate 5 3 4 3 Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows SMOD Mode
41. is turned ON OFF by setting clearing bit TR1 in the software 2 The Timer is turned ON if both 01 intO n i 1 TRO 1 hardware control Page 32 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Standard Serial Interface SIOO Handshake Solutions 5 3 Standard Serial Interface SIO0 This module implements a buffered full duplex asynchronous serial interface with multimaster sup port 5 3 1 Options This module can be enabled ordered by using option 80 51 SIO 5 3 2 Special function registers SCON SBUF SMOD SCON Serial Port Control Register addr 98H reset value 00H bits 7 6 5 4 3 2 1 0 sw swe tes T eo T bit symbol Function SCON 7 SMO serial mode selection SM0 SM1 SCON 6 5 1 00 0 shift register fso ck i 01 mode 8sbit UART depending on fio overtow 10 mode2 9bit UART fsio a 1 64 OF fio a i 32 11 3 9bit UART depending on fio SCON 5 SM2 multiprocessor communication in modes 2 and 3 If 5 2 1 in modes 2 and 3 then RI will not be activated if the received 9 data bit RB8 is 0 If SM2 1 in mode 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 SCON 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception SCON 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by softwar
42. latch not the input pin The Accumulator holds 56H 01010110B The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified by the LABEL2 with the Ac cumulator modified to 52H 01010010B 3 2 bit address rel address JBC lt 3 IF bit 1 THEN bit lt 0 PC lt PC re Jump if Carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruc tion The branch destination is computed by adding the signed relative displacement in the sec ond instruction byte to the PC after incrementing the PC twice No flags are affected The carry flag is cleared The instruction sequence JC LABEL1 CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 0 1 0 0 0 0 0 0 JC PC PC 2 IF 1 rel address rel Page 107 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions JMP Function Description Example Bytes Cycles Encoding Operation JNB bit rel Function Description Example Bytes Cycles Encoding Operation Page 108 of 132 Jump indirect Add the eight bit unsigned c
43. modify an output pin the value used as the original data will be read from the output data latch not the input pin Port 1 has previously been written with 5DH 01011101B The instruction sequence CPL Pl CPL P1 2 will leave the port set to 5BH 01011011B bit address CPL bit lt bit O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions DAA Function Decimal adjust Accumulator for Addition Description Example Bytes Cycles Encoding Operation DA A adjusts the eight bit value in the Accumulator resulting from the earlier addition of two vari able each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If Accumulator bits 3 0 are greater than nine xxx1010 xxx1111 or if the AC flag is one six is added to the Accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagated through all high order bits but it would not clear the carry flag otherwise If the carry flag is now set or if the four high order bits now exceed nine 1010xxx 111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry flag if there was a carry out of the high order bits b
44. or event counters In the Timer function the register is incremented every timer clock cycle clock input 01 1 i Thus if the operation of the CPU is synchronized to the same clock one can think of it as counting machine cycles of the CPU In the Counter function the register is incremented in response to a 1 to 0 transition at its corre sponding external input 0 count i 1 count i By design there are no restrictions on the duty cycle or the frequency of the external input signals However depending on the standard cell library that is used and the actual layout some maximum limits will apply 5 2 1 Options This module can be enabled ordered by using option HT80C51_T01 5 2 2 Special function registers TMOD TCON TLO TL1 THO TH1 TMOD Timer Counter Mode Control addr 89H X reset value 00H bits 7 6 5 4 3 2 1 0 GATE1 C T1 T1M1 T1MO GATEO C TO TOM1 TOMO bit symbol Function TMOD 7 GATE1 Timer 1 gating control 1 Timer Counter 1 is enabled only while input 01 inti n iis high and TR1 TCON is 1 0 Timer Counter 1 is enabled if TR1 is set TMOD 6 C T1 Timer 1 operation selection 1 counter operation clock source is input pin 1 count i 0 timer operation clock source is the clock input t01 clik i TMOD 5 T1M1 Timer 1 mode selection TMOD 4 T1MO 00 8048 timer mode TL1 serves as a 5bit prescaler 01 16bit timer counter TH1 and TL1 are cascaded no prescaler 10 8bit auto reload tim
45. processes a particular bus status There are 26 possible bus states if all four modes of SIO1 are used The 5 bit status code is latched Page 52 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions into the five most significant bits of the status register when the serial interrupt flag is set by hard ware and remains stable until the interrupt flag is cleared by software The three least significant bits of the status register are always zero If the status code is used as a vector to service routines then the routines are displaced by eight address locations Eight bytes of code are sufficient for most of the service routines 5 5 4 3 The Four SIO1 Special Function Registers The microcontroller interfaces to SIO1 via four special function registers These four SFRs S1ADR S1DAT S1CON and S1STA are described individually in the following sections The Address Register STADR The CPU can read from and write to this 8 bit directly addressable SFR S1ADR is not affected by the SIO1 hardware The contents of this register are irrelevant when SIO1 is in a Master mode In the Slave modes the seven most significant bits must be loaded with the microcontroller s own slave ad dress and if the least significant bit is set the general call address 00H is recognized otherwise it is ignored 7 6 5 4 3 2 1 0 S1ADR DBH The most significant bit corresponds to
46. space addr 11 11 bit destination address Used by ACALL and AJMP The branch will be within the same 2k byte page of program memory as the first byte of the following instruction Rel Signed two s complement 8 bit offset byte Used by SJMP and all conditional jumps Range is 128 to 127 bytes relative to first byte of the following instruction Bit Direct Addressed bit in Internal Data RAM or Special Function Register Philips Electronics N V 2005 Page 87 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set 80C51 Instruction Set Summary MNEMONIC DESCRIPTION BYTE MACHINE CYCLES ARITHMETIC OPERATIONS ADD A Rn Add register to Accumulator 1 1 ADD A direct Add direct byte to Accumulator 2 1 ADD A Ri Add indirect RAM to Accumulator 1 1 ADD A data Add immediate data to Accumulator 2 1 ADDC A Rn Add register to Accumulator with carry 1 1 ADDC A direct Add direct byte to Accumulator with carry 2 1 ADDC A Ri Add indirect RAM to Accumulator with carry 1 1 ADDC A data Add immediate data to Accumulator with carry 2 1 SUBB A Rn Add register to Accumulator with borrow 1 1 SUBB A direct Add direct byte to Accumulator with borrow 2 1 SUBB A Ri Add indirect RAM to Accumulator with borrow 1 1 SUBB A data Add immediate data to Accumulator with borrow 2 1 INC A Increment Accumulator 1 1 INC Rn Rn Increment register 1 1 INC Direct Increment direct byte 2 1 INC Ri Increment indirect RAM 1 1
47. the 16 bytes in this segment can also be addressed as a byte 3 Scratch Pad Area 30H through 7 are available to the user as data RAM However if the stack pointer has been initial ized to this area enough bytes should be left aside to prevent overwriting of stack data Page 12 of 132 Philips Electronics N V 2005 HT80C51 User Manual Memory Organization Special Function Registers Handshake Solutions 2 5 Special Function Registers The upper address range of the direct addressable data memory is occupied by the special function registers SFRs These registers not only serve as data storage they also have special function for the CPU or peripherals they are attached to A map of this area is shown in Figure 6 S1CON S1STA S1DAT STADR TCON TMOD T SFRsin this column are bit addressable Figure 6 SFR memory map Note that in the SFR map not all of the addresses are occupied Unoccupied addresses are not im plemented on the chip Read accesses to these unimplemented SFR locations will in general return random data and write accesses will have no effect User software should not write 1s to these unim plemented locations since they may be used in other 80C51 Family derivative products to invoke new features There are two types of special functions registers registers which are part of the CPU and often di rectly used by certain instructions and SFRs which are implemented in peripheral blocks T
48. the peripherals of the original 80C51 The HT80C51 and its peripherals have been designed in Haste which is the high level programming language of the Handshake Technology design flow This design flow is to a large extent technology independent Mapping onto various VLSI technologies from different vendors is supported For production testing both functional and scan test version are supported The scan test version is compatible with standard ATPG tools O Philips Electronics N V 2005 Page 5 of 132 HT80C51 User Manual Handshake Solutions Introduction to HT80C51 Modules 1 2 Modules Following modules are currently available for a HT80C51 microcontroller system HT80C51 CPU with optional Prefetch unit to increase performance Dual datapointer MOVC protection Synchronization to external clock Interrupt controller With configurable number of interrupt lines 1 to 15 Timer 0 and timer1 UART SPI I2C Master slave or Slave only Watchdog Timer DES Bridge to synchronous SFR bus Supports legacy synchronous peripheral units Other peripherals are being developed or can be implemented on demand Page 6 of 132 Philips Electronics N V 2005 HT80C51 User Manual Introduction to HT80C51 Modules Handshake Solutions external data memory code memory internal data address
49. writing 00H to DCON or it can be copied to KEY1 by writing 01H to DCON 5 8 5 2 Writing a text into the triple DES module The text 3D9D3FA9FC8AD337 can be transferred to the DES module by writing the sequence 37 D3 8A FC A9 3F 9D 3D to SFR DTXT Alternatively the reverse sequence 3D 9D 3F A9 FC 8A D3 37 can be written to DTXT followed by the command 03H to DCON which reverses the order of the bytes 5 8 5 3 DES encryption or decryption All encryptions or decryptions be it single DES or triple DES can be simply performed by writing the apporopiate command into the SFR DCON The single DES encryption or decryption uses KEY0 only The triple DES encryption and decryption use first KEY0 then KEY1 and finally KEYO 5 8 5 4 Reading the text result from register the triple DES module If the generated text result is 3D9D3FA9FC8AD337 reading from DTXT will deliver the sequence 37 D3 8A FC A9 3F 9D 3D after which the internal register will again contain the original text result The text can also be read in the reverse order by first giving the reverse text command Page 84 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Triple DES Converter Handshake Solutions 5 8 5 5 Examples A single DES encryption with key B1B2B3B4B5B6B7B8 and plain text 3D9D3FA9FC8AD337 can be done using following code Store key in KEYO MOV DKEY B8h MOV DKEY B7h MOV DKEY B6h MOV DKEY B5h MOV
50. 05 Page 23 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Interrupt Controller Machine C1 ri lt C2 ri lt C3 C4 ri lt C5 s Cycle d A f Y ig E Interrupts Long Call to Interrupt Routine Are Poled Interrupt Interrupt Interrupt Vector Address Goes Latched Active This is the fastest possible response when Cis the final cycle of an instruction other than RETI or an access to IE or LP Figure 7 Interrupt Response Timing Diagram The polling cycle LCALL sequence is illustrated in Figure 7 Note that if an interrupt of higher priority level goes active prior to the instruction labeled C3 in Figure 7 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction of the lower priority routine having been executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt and in other cases it doesn t It never clears the Serial Port flag This has to be done in the user s software It clears an external interrupt flag IE0 or IE1 only if it was transition activated The hardware generated LCALL pushes the contents of the Program Counter on to the stack but it does not save the PSW and reloads the PC with an address that depends on the source of the interrupt being
51. 1 3 Baud Rate 32 x Timer 1 overflow rate The Timer 1 interrupt should be disabled in this application The Timer itself can be configured for either timer or counter operation and in any of its 3 running modes In the most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 00108 In that case the baud rate is given by the formula 2 for 4 x 32 256 1 One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled and con figuring the Timer to run as a 16 bit timer high nibble of TMOD 00018 and using the Timer 1 inter rupt to do a 16 bit software reload Table 7 lists various commonly used baud rates and how they can be obtained from Timer 1 Mode 1 3 Baud Rate Philips Electronics 2005 Page 35 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Standard Serial Interface SIOO sio mode baud rate clock input clock frequency SMOD Sio clk i 2 MHz t01 clk i 20 MHz t01 clk i 11 059 MHz t01 clk i 11 059 MHz 101 clk i 11 059 MHz t01 clk i 11 059 MHz t01 clk i 1 8432 MHz t01 clk i 0 9216 MHz t01 clk i 1 8432 MHz t01 clk i 1 8432 MHz 101 clk i 1 8432 MHz t01 clk i 1 8432 MHz 101 clk i 1 8432 MHz t01 clk i 1 MHz t01_clk_i 0 5 MHz O O O O O O O O O O O X N N N NY NBO M M NON YP M M XK o 3 3 3 3 3 3
52. 20H holds the value 75H 01110101B The instruction XCH A RO will leave the RAM location 20H holding the values 3FH 00111111B and 75H 01110101B in the Accumulator 1 1 0 0 1 r r r XCH A Rn 2 1 1 1 0 0 0 1 0 1 direct address XCH A e direct 1 1 1 1 0 0 0 1 1 i XCH A Ri Page 127 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions XCHD A QRi Function Description Example Bytes Cycles Encoding Operation Exchange Digit XCHD exchanges the low order nibble of the Accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the speci fied register The high order nibbles bits 7 4 of each register are not affected No flags are af fected RO contains the address 20H The Accumulator holds the value 36H 00110110B Internal RAM location 20H holds the value 75H 01110101B The instruction XCHD A RO will leave RAM location 20H holding the value 76H 01110110B and 35H 00110101B in the Ac cumulator 1 1 1 1 0 1 0 1 1 i XCHD A3 0 lt gt Ri3 0 XRL lt dest byte gt lt src byte gt Function Description Example Logical Exclusive OR for byte variables XRL performs the bitwise logical Exclusive OR operation between the indicated variables
53. 5 4 3 2 1 0 transmit receive data bit symbol Function S1DAT 7 Data byte to be transmitted or been received S1DAT remains un S1DAT 6 changed by hardware as long as SI in S1CON is set S1DAT 5 S1DAT 4 S1DAT 3 S1DAT 2 S1DAT 1 S1DAT O Philips Electronics N V 2005 Page 45 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 S1STA SIO1 status register addr D9H reset value F8H bits 7 6 5 4 3 2 1 0 Lo stats o o 0 bit symbol Function S1STA 7 Status code The status is valid as long as SI is set When no relevant S1STA 6 status is available S1STA contains the value F8H S1STA 5 S1STA 4 S1STA 3 S1STA 2 Always 0 S1STA 1 S1STA O 5 5 3 Interrupts The HT I2C can generate only one interrupt If the bit SI in the SFR S1CON is set an interrupt is re quested on line int req i 5 Slis set by hardware but has to be cleared by software for instance in the interrupt service routine 5 5 4 Operation The I2C bus uses two wires SDA and SCL to transfer information between devices connected to the bus The main features of the bus are e Bidirectional data transfer between masters and slaves e Multimaster bus no central master e Arbitration between simultaneously transmitting masters without corruption of serial data on the bus e Serial clock synchronization allows devices with different bit rates to communicate via one serial bus e Serial clock synchronization can be us
54. 7 and after a byte has been received the first bit of received data is located at the MSB of S1DAT While data is being shifted out data on the bus is simultaneously being shifted in S1DAT al ways contains the last byte present on the bus Thus in the event of lost arbitration the transition from master transmitter to slave receiver is made with the correct data in S1DAT O Philips Electronics N V 2005 Page 49 of 132 Handshake Solutions HT80C51 User Manual Peripheral Modules 12C Interface 5101 external pad drivers HT80C51 P 8 S1ADR ADDRESS REGISTER COMPARATOR i2c sda i INPUT gt _50 FILTER SDA 4 4 4 OUTPUT i2c sda o S1DAT SHIFT REGISTER M1 4 STAGE 4 A A 8 2 m ARBITRATION amp re d INPUT i2c sd i SYNCLOGIC gt 2 FILTER TIMING ui amp i2c dk i SCL 4 y CONTROL xd LOGIC Pe i2c scl o SERIAL CLOCK INTERRUPT OUTPUT GENERATOR STAGE t1 overflow 4 S1CON CONTROL REGISTER 8 2 STATUS STATUS BITS DECODER S1STA STATUS REGISTER LJ Figure 16 Bus Serial Interface Block Diagram Page 50 of 132 O Philips Electronics N V 2005 HT80C51 User
55. BEL2 will cause program execution to continue at the instruction at label LABEL2 3 2 0 0 1 1 0 0 0 0 bit address rel address JNB lt 3 IF bit 0 THEN PC lt PC rel Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions JNC rel Function Description Example Bytes Cycles Encoding Operation JNZ rel Function Description Example Bytes Cycles Encoding Operation Jump if Carry Not set If the carry flag is a zero branch to the address indicated otherwise proceed with the next instruc tion The branch destination is computed by adding the signed relative displacement in the sec ond instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC LABEL1 CPL JNC LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the la bel LABEL2 2 2 rel address JNC lt 2 IF C 0 THEN PC lt PC rel Jump if Accumulator Not Zero If any bit of the Accumulator is a one branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the se
56. E TO MASTER DATA n THIS NUMBER CONTAINED IN S1STA CORRESPONDS A DEFINED STATE OF THE TC BUS SEE TABLE 5 A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS Figure 22 Format and States in the Master Receiver Mode Page 62 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions RECEPTION OF THE OWN SLAVE ADDRESS AND ONE OR MORE DATA BYTES ALL ARE ACKNOWLEDGED 1 DATA A PorS LAST DATA BYTE RECEIVED IS NOT ACKNOWLEDGED ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE RECEPTION OF THE GENERAL CALL ADDRESS AND ONE OR MORE DATA BYTES 80H A0H LAST DATA BYTE IS NOT ACKNOWLEDGED ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE BY GENERAL CALL FROM MASTER TO SLAVE FROM SLAVE TO MASTER GENERAL CALL 1 DATA Pors ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER CONTAINED IN S1STA CORRESPONDS TO A DEFINED STATE OF THE C BUS SEE TABLE 6 Figure 23 Format and States in the Slave Receiver mode O Philips Electronics N V 2005 Page 63 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 RECEPTION OF THE OWN SLAVE i ADDRESS AND ONE OR MO
57. ES bit symbol Function IENO 7 EA General enable disable control If EA 0 Any individually enabled interrupt will be accepted 0 interrupt is enabled IENO 6 Enable interrupt input int req i 6 IENO 5 ES1 Enable I2C interrupt if available or interrupt input int req i 5 IENO 4 ESO Enable UART interrupt if available or interrupt input int req i 4 IENO 3 ET1 Enable timer 1 overflow interrupt if available or interrupt input int req i 3 IENO 2 EX1 Enable external interrupt from timer 1 IE1 if available or interrupt input int_req i 2 IENO 1 ETO Enable timer 0 overflow interrupt if available or interrupt input int req i 1 IENO O EXO Enable external interrupt from timer 0 IE0 if available or interrupt input int_req i 0 Bit values 0 interrupt disabled 1 interrupt enabled Page 20 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Interrupt Controller Handshake Solutions IEN1 Interrupt enable register 1 addr E8H reset value 00H bits 7 6 5 4 3 2 1 0 bit symbol Function IEN1 7 Enable interrupt input int req i 14 IEN1 6 Enable interrupt input int req i 13 IEN1 5 Enable interrupt input int req i 12 IEN1 4 Enable interrupt input int req i 11 IEN1 3 Enable interrupt input int req i 10 IEN1 2 Enable interrupt input int req i 9 IEN1 1 Enable interrupt input int req i 8 IEN1 0 Enable interrupt input int req i 7 Bit values 0
58. Function Description Example Bytes Cycles Encoding Operation PUSH direct Function Description Example Bytes Cycles Encoding Operation O Philips Electronics N V 2005 Pop from stack The contents of the internal RAM location addressed by the Stack Pointer is read and the Stack Pointer is decremented by one The value read is then transferred to the directly addressed byte indicated No flags are affected The Stack Pointer originally contains the value 32H and internal RAM locations 30H through 32H contain the values 20H 23H and 01H respectively The instruction sequence POP DPH POP DPL will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H At this point the instruction POP SP will leave the Stack Pointer set to 20H Note that in this special case the Stack Pointer was dec remented to 2FH before being loaded with the value popped 20H 2 2 direct address POP direct lt SP SP SP 1 Push onto stack The Stack Pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer Otherwise no flags are affected On entering an interrupt routine the Stack Pointer contains 09H The Data Pointer holds the value 0123H The instruction sequence PUSH DPL PUSH DPH will leave the Stack Pointer set to OBH and store 23H and 01
59. HT80C51 CPU MOVCP Handshake Solutions In the Power Down mode of operation VDD can be reduced to a level that is still sufficient for logic and RAM to keep their contents Care must be taken however to ensure that VDD is not reduced before the Power Down mode is invoked and that VDD is restored to its normal operating level be fore the Power Down mode is terminated The reset that terminates Power Down also should switch on the core clock again The reset should not be activated before VDD is restored to its normal operat ing level and must be held active long enough to allow an oscillator to restart and stabilize 2 5 7 External RAM Page XRAMP option HT80C51 CPU XRAMP The MOVX instruction comes in two flavors MOVX DPTR and MOVX Ri For the second version MOVX Ri the contents of one index register Ri specify the lower half of the 16bit address for the access to the external data memory The upper half is not specified by the instruction but the SFR XRAMP supplies it In other words the external data memory is divided into pages of 256bytes with XRAMP selecting the page and Ri addressing within this page XRAMP External RAM Page addr C9H reset value 00H bits 7 6 5 4 3 2 1 0 2 6 MOWVC protection option HT80C51 CPU MOVCP This optional feature protects a memory region in program memory from being read out by a program outside this region Thus any MOVC instruction that is executed outside the protected region and tries
60. I O operation has been completed The SPI is double buffered on read but not on write If a write is performed during data transfer the transfer occurs uninterrupted and the write will be unsuccessful This condition will cause the write collision WCOL status bit in the SPSR to be set After a data byte is shifted the SPIF flag of the SPSR is set Page 76 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Serial Peripheral Interface SPI Handshake Solutions spi miso o MISO Spi miso i De rR oe era M LU S TTE l 7 l spi mosi o Spi ck i MOSI 8 BIT SHIFT REGISTER spi mosi i 1 1 READ DATA BUFFER DIVIDER l BY 1 2 8 16 1 1 A clock SELECT SPI clock master gt e spi_sck_i S CLOCK LOGIC SCK Y T Y gt spi sck o Q Q 2 ot spi ssni SS MSTR spi mstr o SPI CONTROL SPE 4 Spi spe o lt zi Z x ax zio uL v Qv 2 77 o6 S 60225259609 SPI STATUS REGISTER 4 SPI CONTROL REGISTER SPI Y interrupt Y internal data request bus Figure 28 SPI block diagram In the master mode the SCK clock is driven to the output pin spi sck o It idles high or low depending on the CPOL bit in the SPCR until data
61. KEY 82 5 8 3 Interrupts ee eer 83 5 8 4 Operation A E iA E D EE ud 83 5 8 5 Software VIEW ce ple te Le e tei E rede dene aot eee dove ta a 84 6 lt 80C51 Family Instruction Selaia aana e AAAA AAA hne 87 6 1 80C51 Instruction Set Summary eese eene nnne nnn 87 6 2 Instruction definitions 1 eurer redde e secrete ener 91 nep qem E 130 A1 Eist of Tables o eee ete 130 A2 List of FIQUIFOS e 131 A3 Document HISTORY ee 132 Page 4 of 132 Philips Electronics N V 2005 HT80C51 User Manual Introduction to HT80C51 Compatibility Handshake Solutions 1 Introduction to HT80C51 The Handshake Technology 80C51 referred to as HT80C51 is an improved version of the ultra low power 80C51 known as ulp80C51 This ulp80C51 has been used in several products such as pagers game controllers telephony controllers and Mifare ProX and SmartMX smart card controllers Millions of these ICs have been shipped The HT80C51 implementation offers several unique features which are detailed below e The HT80C51 is extremely low power the CPU consumes only 0 1 nano joules per instruction e The HT80C51 has very low
62. MPLE INPUT Y Y Y Y Y Y Y Y NEN 1 DATA OUT MSB 6 5 4 3 2 1 LSB gt SS TO SLAVE Figure 29 Data Clock Timing Diagram When CPHA 0 the shift clock is the OR of spi ss n i with SCK In this clock phase mode spi ss n i must go high between successive characters in an SPI message When CPHA 1 spi ss n i may be left low for several SPI characters In cases where there is only one SPI slave its spi ss n iline could be tied to 0 as long as CPHA 1 clock modes are used 5 6 4 2 Standard Interconnections Due to data direction register control of SPI outputs and the port D wire OR mode DWOM option the SPI system can be configured in a variety of ways Systems with a single bidirectional data path rather than separate MISO and MOSI paths can be accommodated Page 78 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Serial Peripheral Interface SPI Handshake Solutions If the SPI slaves can selectively disable their MISO output a broadcast message protocol is also pos sible Master 8 SHIFT REGISTER rot 4 SPI CLOCK GENERATOR 4 Slave 4 IMISO MISO lt 8 BIT SHIFT IMosI MOSII REGISTER I l i ISPICLK seil I _ ssl gt I I I I I Figure 30 SPI Single Master Single Slave Confi
63. OUNTER then the value that must be loaded into TMOD is 69H 09H from Table 3 ORed with 60H from Table 6 Moreover it is assumed that the user at this point is not ready to turn the timers on and will do that at a different point in the program by setting bit TRx in TCON to 1 5 2 5 1 TIMER COUNTER 0 o TMO mode timer 0 function control external control note 1 note 2 0 13bit timer 1 16bit timer 01H 2 8bit auto reload 3 two 8bit timers Table3 Timer 0 as a Timer o TMO mode timer 0 function control external control note 1 note 2 0 13bit timer 1 16bit timer 2 8bit auto reload 3 two 8bit timers Table 4 Timer 0 as a Counter NOTES 1 The Timer is turned ON OFF by setting clearing bit TRO in the software 2 The Timer is turned ON if both 01 intO n 1 1 hardware control Philips Electronics 2005 Page 31 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Timers 0 and 1 5 2 5 2 TIMER COUNTER 1 IMO es mode timer 1 function yee control external control note 1 note 2 0 13bit timer 1 16bit timer 2 8bit auto reload 3 two 8bit timers Table 5 Timer 1 as a Timer TMOD mode timer 1 function control external control note 1 note 2 0 13bit timer 1 16bit timer 2 8bit auto reload 3 two 8bit timers Table 6 Timer 1 as a Counter NOTES 1 The timer
64. PI control register addr F5H reset value 0000 0100 bits 7 6 5 4 3 2 1 0 bit Symbol Function SPCR 7 SPIE SPI interrupt enable SPI interrupt enabled SFR bit SPIF causes an SPI interrupt int req i 6 SPI interrupt disabled no SPI interrupt generated SPCR 6 SPE SPI interface enable SPI interface enabled output pin spi spe 1 SPI interface disabled output pin spi spe ois 0 SPCR 5 DWOM Port D Wire OR Mode connected to output pin spi dwom o The environment can use the signal of this output pin to select the output mode oA oa 1 spi dwom 1 use open drain outputs 0 spi dwom o 0 use standard CMOS outputs DWOM is not used by the SPI interface internally SPCR 4 MSTR Master mode select 1 master mode 0 slave mode SPCR 3 CPOL Clock Polarity selects the polarity of the shift clock spi sck o master mode spi sck i in slave mode see Figure 29 1 shift clock is active low 0 shift clock is active high SPCR 2 CPHA Clock phase 1 As soon as input spi ss n i goes low the transaction begins and the first edge of spi sck i invokes the first data sample 0 f input pin spi ss n iis 0 the outputs are enabled SPCR 1 SPR1 Baudrate select bits SPCR 0 SPRO In master mode these bits select the clock divisor for generating the clock output spi sck o see table below In slave mode these bits have no effect Page 74 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Module
65. Page 71 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12 Interface 5101 TIME OUT STA FLAG SDA LINE SCL LINE START CONDITION Figure 26 Forced Access to a Busy I2C Bus I2C Bus Obstructed by a Low Level on SCL or SDA An 12 bus hang up occurs if SDA or SCL is pulled LOW by an uncontrolled source If the SCL line is obstructed pulled LOW by a device on the bus no further serial transfer is possible and the SIO1 hardware cannot resolve this type of problem When this occurs the problem must be resolved by the device that is pulling the SCL bus line LOW If the SDA line is obstructed by another device on the bus e g a slave device out of bit synchroniza tion the problem can be solved by transmitting additional clock pulses on the SCL line see Figure 27 The SIO1 hardware transmits additional clock pulses when the STA flag is set but no START condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free The SIO1 hardware attempts to generate a START condition after every two additional clock pulses on the SCL line When the SDA line is eventually released a normal START condition is transmitted state 08H is entered and the serial transfer continues If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed pulled LOW the SIO1 hardware performs the same action as described above In
66. RE 5 SA DATAS pA ROTS DATA BYTES ALL ARE i i I ACKNOWLEDGED FA ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE PROM MEST ER SAVE LAST DATA BYTE TRANSMITTED KS TT TT TTT SWITCHED NOT ADDRESSED A All 4 s Pors SLAVE AABITINSICON 0 RO FROM SLAVE TO MASTER 2s cen DATA ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER CONTAINED IN SISTA CORRESPONDS TO A DEFINED STATE OF THE fC BUS SEE TABLE 7 Figure 24 Format and States of the Slave Transmitter mode Page 64 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12 Interface S101 Handshake Solutions application software response code status of the I2C bus GSIN and SIO1 hardware to from S1DAT s A START condition has been Load SLA W transmitted A repeated START condition Load SLA W or As above SLA W will be transmitted SIO1 will be switched to MST REC mode next action taken by SIO1 hard ware SLA W will be transmitted bit will be received has been transmitted Load SLA R SLA W has been transmit Load data byte or Data byte will be transmitted ted ACK has been received bit will be received SLA W has been transmit ted NOT ACK has been received Data byte in S1DAT has been transmitted ACK has been received Data byte in STDAT has been transmitted NOT ACK has been received
67. STOP condition which is not transmitted SIO1 then transmits a START condition STO 0 When the STO bit is reset no STOP condition will be generated The Serial Interrupt Flag SI SI 1 When the SI flag is set then if the EA and ES1 interrupt enable register bits are also set a serial interrupt is requested SI is set by hardware when one of 25 of the 26 possible SIO1 states is entered The only state that does not cause 5 to be set is state F8H which indicates that no relevant state information is available While SI is set the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended A high level on the SCL line is unaffected by the serial in terrupt flag SI must be reset by software SI 0 When the SI flag is reset no serial interrupt is requested and there is no stretching of the serial clock on the SCL line The Assert Acknowledge Flag AA 1 If the flag is set an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line when The own slave address has been received The general call address has been received while the general call bit GC in S1ADR is set A data byte has been received while SIO1 is in the Master Receiver mode A data byte has been received while SIO1 is in the addressed Slave Receiver mode AA 0 if the AA flag is reset a not acknowledge high level to SDA
68. T action No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action Read data byte or read data byte Read data byte or read data byte or Read data byte or read data byte Read data byte or read data byte or application software response to STCON sra sro s aa X 0 Next action taken by SIO1 hardware Data byte wi NOT ACK bit will be returned Data byte wi bit will be returned be received be received Data byte wi NOT ACK bit will be returned Data byte wi bit will be returned be received be received Data byte wi NOT ACK bit will be returned Data byte wi bit will be returned be received be received Data byte wi NOT ACK bit will be returned Data byte wi bit will be returned be received be received Data byte will be received NOT ACK bit will be returned Data byte will be received bit will be returned Switched to not addressed SLV mode no recog nition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR O logic 1 Switched to not addressed SLV mode no recog nition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will b
69. TAR EANAN EAN Yo AE PARLARS SEA 9 2 1 Memory ET PM 9 2 2 Accessing Program Memory 10 2 3 Accessing External Data Memory eese 10 24 Internal Data Memory Direct and Indirect Address 11 2 5 Special Function nennen nennen nien nnne inire 13 2 9 1 Accumulator AGG act ect x dao tx o ER ed 14 2 5 2 celica LE 14 2 5 3 Program Status Word PSW enne 14 2 5 4 Stack Polnter SP Le ed e de ei Rites 14 2 5 5 Data Pointer DPTR DPL sse 15 2 5 6 Power Saving Modes PCON 15 2 5 7 External RAM Page XRAMP option HT80C51_CPU_XRAMP 17 2 6 MOVC protection option HT80C51 CPU 17 EM CCIDM e M 18 Ai lt COCKS e 19 4 1 GPU e I 19 4 1 1 Clockless Aynchronous Cnfiguration essem 19 4 1 2 Clock synchronization Option HT80C51 CPU 19 4 2 Peripheral ClOCKS ecrit eee crece ente eter ence 19 5 Periphlieral Modules onte rette tnu teret Ei Eran alin EEA iR RR RAS M RE E NERA 20 5 1 Interrupt C
70. YTE 30H Y gt ARBITRATION LOST IN SLAVE OTHERMST OTHER MST ADDRESS OR DATA BYTE CONTINUES CONTINUES 38H 38H gt ARBITRATION LOST AND a OTHER MST ADDRESSED AS SLAVE CONTINUES a TO CORRESPONDING STATES ESH wu ub gt MODE FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA A NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS _ n THIS NUMBER CONTAINED IN S1STA CORRESPONDS TO A DEFINED STATE OF BUS SEE TABLE 4 Figure 21 Format and States in the Master Transmitter mode Philips Electronics N V 2005 Page 61 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 MR e SUCCESSFUL RECEPTION T J L i t 1 I FROM A SLAVE TRANSMITTER oe R 1 5 E i A DATA A 08H 40H 50H 58H i NEXT TRANSFER STARTED WITH DRA A REPEATED START CONDITION ARS cc NRI t 10H NOT ACKNOWLEDGE RECEIVED box WS AFTER THE SLAVE ADDRESS NN 48H TO MST TRX MODE ENTRY MT gt oo gt ARBITRATION LOST IN SLAVE laora OTHER MST to OTHER MST ADDRESS OR ACKNOWLEDGE BIT 9 CONTINUES CONTINUES 88H 38H gt ARBITRATION LOST AND OTHER MST ADDRESSED AS SLAVE i CONTINUES 68H 78H Y 80H TO CORRESPONDING STATES IN 68H gt SLAVE MODE FROM MASTER TO SLAVE FROM SLAV
71. addresses 00 7F register banks register bank 0 Figure 5 Lower 128 bytes of RAM direct and indirect addressing 1 Register Banks 0 3 Locations 00H through 1FH 32 bytes The device after reset defaults to register bank 0 To use the other register banks the user must select them in software Each register bank contains eight 1 byte registers 0 through 7 Reset initializes the stack pointer to location 07H and it is incremented once to start from location 08H which is the first register R0 of the second register bank Thus in order to use more than one register bank the SP should be initialized to a different location of the RAM where it is not used for data storage i e the higher part of the RAM The register bank is selected by bits RS0 and RS1 in the program status word 2 Bit Addressable Area 16 bytes have been assigned for this segment 20H 2FH Each one of the 128 bits of this segment can be directly addressed 0 7 FH The bits can be referred to in two ways both of which are accept O Philips Electronics N V 2005 Page 11 of 132 HT80C51 User Manual Handshake Solutions Memory Organization Internal Data Memory Direct and Indirect Address Area able by most assemblers One way is to refer to their address i e 0 7 FH The other way is with ref erence to bytes 20H to 2FH Thus bits 0 7 can also be referred to as bits 20 0 20 7 and bits 8 FH are the same as 21 0 21 7 and so on Each of
72. ansmitted when the bus becomes free Master Transmitter mode not available for slave only version Page 65 of 132 Handshake Solutions HT80C51 User Manual Peripheral Modules 12 Interface 5101 status status of the I2C bus and SIO1 hardware code S1STA A START condition has been transmitted A repeated START condition has been transmitted Arbitration NOT ACK bit SLA R has been transmitted ACK has been received SLA R has been transmitted NOT ACK has been received Data byte has been received has been returned Data byte has been received NOT ACK has been returned application software response to SiCON to from S1DAT CACAR Load SLA R Load SLA R or Load SLA W No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action or no S1DAT action Read data byte or read data byte Read data byte or read data byte or read data byte next action taken by SIO1 hard ware SLA W will be transmitted ACK bit will be received As above SLA W will be transmitted SIO1 will be switched to MST TRX mode I2C bus will be released 101 will enter slave mode START condition will be transmitted when the bus becomes free Data byte will be received NOT ACK bit will be returned Data byte will be received bit will be returned Repeated START will be transmitted STOP condition will be transmitted STO flag
73. causing four output pulses to appear at bit 7 of output Port 1 Each pulse will last three machine cycles two for DJNZ and one to alter the pin 2 2 1 1 0 1 1 r r r rel address DJNZ PC PC 2 Rn lt Rn 1 IF Rn gt O or Rn O DJNZ direct rel Bytes Cycles Encoding Operation THEN PC lt PC rel 3 2 1 1 0 1 0 1 0 1 direct data rel address DJNZ lt 2 direct direct 1 IF direct gt 0 or direct 0 THEN PC lt PC rel Page 104 of 132 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions INC byte Function Increment Description INC increments the indicated variable by 1 An original value of OFFH will overflow to 00H No flags are affected Three addressing modes are allowed register direct or register indirect Example A Bytes Cycles Encoding Operation INC Rn Bytes Cycles Encoding Operation INC direct Bytes Cycles Encoding Operation INC Ri Bytes Cycles Encoding Operation Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Register O contains 7EH 01111110B Internal RAM locations 7EH and 7FH contain OFFH and 40H respectively The instr
74. cond instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally holds OOH The instruction sequence JNZ LABEL1 INC A JNZ LABEL2 will set the Accumulator to 01H and continue at label LABEL2 rel address JNZ lt PC 2 0 THEN PC lt PC rel Philips Electronics N V 2005 Page 109 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions JZ rel Function Description Example Bytes Cycles Encoding Operation LCALL addr16 Function Description Example Bytes Cycles Encoding Operation Jump if Accumulator Zero If all bits of the Accumulator are zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally holds 01H The instruction sequence JZ LABEL1 DEC A JZ LABEL2 will change the Accumulator to OOH and cause program execution to continue at the instruction identified by the label LABEL2 2 2 0 1 1 0 0 rel address JZ lt PC 2 IFA 0 THEN PC lt PC rel
75. contained in the instruction or a value computed in the Accu mulator at run time The instruction ANL P1 01110011B will clear bits 7 3 and 2 of output port 1 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions ANL A Rn Bytes 1 Cycles 1 Encoding Operation ANL lt A Rn ANL A direct Bytes 2 Cycles 1 Encoding 0 1 0 1 0 1 0 1 direct address Operation ANL lt A direct ANL A Ri Bytes 1 Cycles 1 Encoding 0 1 0 1 0 1 1 i Operation ANL lt A Ri ANL A data Bytes 2 Cycles 1 Encoding 9 1 0 1 0 1 0 0 immediate data Operation ANL lt A data ANL direct A Bytes 2 Cycles 1 Encoding O 1 0 1 0 0 1 O0 direct address Operation ANL A lt direct A ANL direct Zdata Bytes 3 Cycles 2 Encoding O 1 0 1 0 0 1 1 direct address immediate data Operation ANL direct direct data O Philips Electronics N V 2005 Page 95 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions ANL C lt src bit gt Function Description Example ANL C bit Bytes Cycles Encoding Operation ANL C bit Bytes Cyc
76. contains 5CH 01011100B The instruction CLR A will leave the Accumulator set to 00H 00000000B Clear bit The indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Port 1 has previously been written with 5DH 01011101B The instruction CLR P1 2 will leave the port set to 59H 01011001B bit address Page 99 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions CPLA Function Description Example Bytes Cycles Encoding Operation CPL bit Function Description Example CPLC Bytes Cycles Encoding Operation CPL bit Bytes Cycles Encoding Operation Page 100 of 132 Complement Accumulator Each bit of the Accumulator is logically complemented one s complement Bits which previously contained a one are changed to a zero and vice versa No flags are affected The Accumulator contains 5CH 01011100B The instruction CPL A will leave the Accumulator set to 10100011B 1 1 CPL A A Complement bit The bit variable specified is complemented A bit which had been a one is changed to zero and vice versa No other flags are affected CPL can operate on the carry or any directly addressable bit Note When this instruction is used to
77. ct byte from stack 2 2 XCH A Rn Exchange register with Accumulator 1 1 XCH A direct Exchange direct byte with Accumulator 2 1 XCH A Ri Exchange indirect RAM with Accumulator 1 1 XCHD A Ri Exchange low order digit indirect RAM with Acc 1 1 Philips Electronics N V 2005 Page 89 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set 80C51 Instruction Set Summary MNEMONIC DESCRIPTION BYTE MACHINE CYCLES BOOLEAN VARIABLE MANIPULATION CLR C Clear carry 1 1 CLR bit Clear direct bit 2 1 SETB C Set carry 1 1 SETB bit Set direct bit 2 1 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 1 ANL C bit AND direct bit to carry 2 2 ANL C bit AND complement of direct bit to carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to carry 2 2 MOV C bit Move direct bit to carry 2 1 MOV bit C Move carry to direct bit 2 2 JC rel Jump if carry is set 2 2 JNC rel Jump if carry not set 2 2 JB rel Jump if direct bit is set 3 2 JNB rel Jump if direct bit is not set 3 2 JBC bit rel Jump if direct bit is set and clear bit 3 2 PROGRAM BRANCHING ACALL addr11 Absolute subroutine call 2 2 LCALL addr16 Long subroutine call 3 2 RET Return from subroutine 1 2 RETI Return from interrupt 1 2 AJMP addr11 Absolute jump 2 2 LJMP addr16 Long jump 3 2 SJMP rel Short jump relative addr 2 2 JMP A DPTR Jump indirect relative to the DPTR 1 2 JZ rel Jump if Accumulator is ze
78. d integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two operands allow four addressing mode combinations the Accumulator may be com pared with any directly addressed byte or immediate data and any indirect RAM location or work ing register can be compared with an immediate constant The Accumulator contains 34H Register 7 contains 56H The first instruction in the sequence CJNE R7 60H NOT EQ stad ae ets R7 60H NOT EQ JC LOW IF R7 lt 60H E Pe daa ste R7 gt 60H sets the carry flag and branches to the instruction at label NOT By testing the carry flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then the instruction WAIT CJNE A P1 WAIT clears the carry flag and continues with the next instruction in sequence since the Accumulator does equal the data read from P1 If some other value was being input on P1 the program will loop at this point until the P1 data changes to 34H CJNE A direct rel Bytes Cycles Encoding Operation 3 2 1 0 1 1 0 1 0 1 direct address rel address lt 3 IF lt gt direct THEN PC lt PC relative offset IF A direct THEN C 1 ELSE lt 0 O Philips Electronics N V 2005 Page 97 o
79. d peripherals like timers and serial interfaces exist They are compatible to the standard peripherals in synchronous implementations The peripherals can be or dered along with the CPU and are then part of a combined delivery The following chapters describe these peripherals in detail with further options if available and their SFRs 5 1 Interrupt Controller This module handles the enabling and priority decoding of interrupt requests as well as entering and leaving the interrupt routines The number of interrupt inputs can be configured from 0 up to 15 5 1 1 Options The interrupt controller can be ordered by option HT80C51 INT The number of interrupt inputs int req i can be selected ordered by using option HT80C51 INT COUNT 5 1 2 Special function registers IENO IEN1 IPO IP1 The number of implemented SFRs for the interrupt controller and even the number of bits within these SFRs depends on the selected number of interrupt inputs For each interrupt input int req i x one interrupt enable bit and one interrupt priority bit exists All interrupt enable bits are collected in two SFRs and All interrupt priority bits are collected in further two SFRs and IP1 If the number of interrupt inputs is greater than 0 SFRs IENO and 1 0 exist If the number of interrupt inputs is greater than 7 SFRs IEN1 and IP1 exist too IENO Interrupt enable register O addr A8H reset value 00H IE bits 7 6 5 4 3 2 1 0
80. d the carry flag are together rotated one bit to the right Bit O moves into the carry flag the original state of the carry flag moves into the bit 7 position No other flags are affected The Accumulator holds the value OC5H 11000101B and the carry is zero The instruction RRC A leaves the Accumulator holding the value 62 01100010B with the carry set 1 1 RRC lt 1 n 20 6 lt C lt A0 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions SETB bit Function Set Bit Description SETB sets the indicated bit to one SETB can operate on the carry flag or any directly address able bit No other flags are affected Example The carry flag is cleared Output Port 1 has been written with the value 34H 00110100B The instructions SETB C SETB P1 0 will leave the carry flag set to 1 and change the data output on Port 1 to 35H 00110101B SETBC Bytes 1 Cycles 1 Encoding 4 4 110 0 1 4 Operation SETB C lt 1 SETB bit Bytes 2 Cycles 1 Encoding 4 4 o 1 0 o 14 0 bit address Operation SETB bit lt 1 SJMP rel Function Short Jump Description Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byt
81. de can be read from S1STA This status code is used to vector to an interrupt service routine and the appro priate action to be taken for each of these status codes is detailed in Table 12 The Slave Transmitter mode may also be entered if arbitration is lost while SIO1 is in the Master mode see state If the AA bit is reset during a transfer SIO1 will transmit the last byte of the transfer and enter state or C8H SIO1 is switched to the not addressed Slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While is reset SIO1 does not respond to its own slave address or a general call address However the I2C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus Page 60 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions MT e SUCCESSFUL TRANSMISSION NNI i OWN TO A SLAVE RECEIVER SASIA G 08H 18H 28H NEXT TRANSFER STARTED WITH IXY UN A REPEATED START CONDITION I 10H NOT ACKNOWLEDGE RECEIVED NN DS AFTER THE SLAVE ADDRESS ESI 20H TO MST REC MODE NOT ACKNOWLEDGE RECEIVED ia NS Se AFTER A DATA B
82. de none of the Timers are used and the clock comes from the serial clock input sio clk i SMOD 1 Baud Rate 1 32 of the frequency at sio clk i SMOD 0 Baud Rate 1 64 of the frequency at sio clk i To set the SMOD bit ORL PCON 80H The address of PCON is 87H Serial Port in Mode 3 The baud rate in mode 3 is variable and sets up exactly the same as in mode 1 Philips Electronics N V 2005 Page 41 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules General Purpose 1 5 4 General Purpose IOs This module comprises unidirectional parallel input and or output ports to read in signals from the environment or set signals for the system 5 4 1 Options The number and addresses of output ports can be selected ordered by using options HT80C51 GPIO POUT COUNT and HT80C51 GPIO POUT ADDRESSES The number and addresses of input ports can be selected ordered by using options HT80C51 GPIO PIN COUNT and HT80C51 GPIO PIN ADDRESSES Note If an output port is placed at an address ending with or 8H the bits of the port are directly addressable 5 4 2 Special function registers POUTx PINx POUTO Output Port 0 addr 80H reset value configurable bits 7 6 5 4 3 2 1 0 POUTO bit symbol Function POUTO 7 set the output values of output pins gpio poutO o 7 0 POUTO 0 POUT1 Output Port 1 addr 90H reset value FFH configurable bits 7 6 5 4 3 2 1 0 POUT1 bit symbol Function POUT1 7 set t
83. ded in time by the application software If the proc essor suffers a hardware software malfunction the software will fail to reload the timer This failure will produce a reset upon overflow thus preventing the processor running out of control The Watchdog Timer can only be reloaded if the condition flag WLE PCON 4 has been previously set by software At the moment the counter is loaded the condition flag is automatically cleared watchdog time interval The time interval between the timer reloading and the occurrence of a reset is dependent upon the reloaded value For example this time period may range from 2 ms to 500 ms when using a clock frequency fwat ck i2 1 MHz Page 80 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Watchdog Timer under development Handshake Solutions INTERNAL BUS fosc 12 PRESCALER TIMER T3 8 BIT overflow P LOAD LOADEN m RST internal 16 LOADEN PCON 1 EWN mm INTERNAL BUS Fig 12 Functional diagram of the T3 Watchdog Timer Figure 31 Functional Diagram of the T3 Watchdog Timer Philips Electronics N V 2005 Page 81 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Triple DES Converter 5 8 Triple DES Converter DES stands for Data Encryption Standard and is a widely used standard for enciphering and deci phering blocks of data This co
84. e recognized if STADR O logic 1 START condition will be transmitted when the bus be comes free Data byte will be received NOT ACK bit will be returned Data byte will be received bit will be returned Switched to not addressed SLV mode no recog nition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recoanized if S1ADR 0 loaic 1 Page 67 of 132 Handshake Solutions HT80C51 User Manual Peripheral Modules I2C Interface S101 STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX Page 68 of 132 read data byte or No S1DAT action or no S1DAT action or no S1DAT action or no S1DAT action Table 12 Switched to not addressed SLV mode no recog nition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR O logic 1 START condition will be transmitted when the bus be comes free Switched to not addressed SLV mode no recog nition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 Switched to not addressed SLV mode no recog nition of own SLA or General call address A START condi
85. e 18 Serial Clock Synchronization Serial Clock Generator This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the Master Transmitter or Master Receiver mode It is switched off when SIO1 is in a Slave mode The program mable output clock frequencies fi a 1 60 to fizc 256 and the Timer 1 overflow rate divided by eight The output clock pulses have a 5096 duty cycle unless the clock generator is synchronized with other SCL clock sources as described above Timing and Control The timing and control logic generates the timing and control signals for serial byte handling This logic block provides the shift pulses for S1DAT enables the comparator generates and detects start and stop conditions receives and transmits acknowledge bits controls the master and Slave modes con tains interrupt request logic and monitors the I2C bus status Control Register S1CON This 7 bit special function register is used by the microcontroller to control the following SIO1 func tions start and restart of a serial transfer termination of a serial transfer bit rate address recognition and acknowledgment Status Decoder and Status Register The status decoder takes all of the internal status bits and compresses them into a 5 bit code This code is unique for each I2C bus status The 5 bit code may be used to generate vector addresses for fast processing of the various service routines Each service routine
86. e 80C51 memory areas program memory external data internal data CODE memory memory XDATA IDATA DATA FFFH up to up to 64 Kbytes 64 Kbytes FFH up to 256 bytes 000H 00H Figure 3 HT80C51 Memory Map The Program memory CODE can be up to 64Kbytes It can be accessed by instruction fetches and by the MOVC instruction The 80C51 can address up to 64k bytes of external data memory XDATA Historically this area was located outside the chip hence the name external which is usually not the case for embedded sys tems The MOVX instruction is used to access the external data memory The 80C51 can address up to 256 bytes of on chip RAM plus a number of Special Function Registers SFRs The lower 128 bytes of RAM can be accessed either by direct addressing MOV data addr or by indi rect addressing MOV Ri The upper 128 bytes of RAM can be accessed by indirect addressing only Using addresses 80H to with direct addressing accesses the special function registers Figure 4 shows the internal data memory organization O Philips Electronics N V 2005 Page 9 of 132 HT80C51 User Manual Handshake Solutions Memory Organization Accessing Program Memory internal data memory FFH upper area of special functions 128 bytes registers SFRs 80H 7FH lower area of RAM 128 bytes 00H indirect addressing direct addressing IDATA DATA Figure 4 Memory
87. e MOVC instructions load the Accumulator with a code byte or constant from program mem ory The address of the byte fetched is the sum of the original unsigned eight bit Accumulator con tents and the contents of a sixteen bit base register which may be either the Data Pointer or the PC In the latter case the PC is incremented to the address of the following instruction before be ing added with the Accumulator otherwise the base register is not altered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected A value between 0 and 3 is in the Accumulator The following instructions will translate the value in the Accumulator to one of four values defined by the DB define byte lt irective REL PC INC A OVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H it will return with 77H in the Accumu lator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the Accumulator instead Philips Electronics N V 2005 Page 115 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions MOVC A At DPTR Bytes Cycles Encoding Operation 1 2 1 0 0 1 0 0 1 1 MOVC
88. e SDA and SCL outputs are in a high impedance state SDA and SCL input signals are ignored SIO1 is in the not addressed slave state and the STO bit in S1CON is forced to 0 No other bits are affected ENS1 1 When ENS1 is 1 SIO1 is enabled ENS1 should not be used to temporarily release SIO1 from the I2C bus since when ENS1 is reset the I2C bus status is lost The AA flag should be used instead see description of the AA flag in the follow ing text gt INTERNAL BUS SDA e A BSD7 S1DAT ACK y A SCL SHIFT PULSES Figure 19 Serial Input Output Configuration Page 54 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions 7 SHIFT IN SHIFT OUT SHIFT BSD7 4 LOADED BY THE CPU Valid data in STDAT Shifting data in STDAT and ACK 3 High level on SDA Figure 20 Shift in and Shift out Timing In the following text itis assumed that ENS1 1 The START Flag STA STA 1 When the STA bit is set to enter a Master mode the SIO1 hardware checks the status
89. e as desired SCON 2 RB8 In Modes 2 and 3 is the 9th data bit that was received In Mode 1 it SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used SCON 1 TI Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software SCON O RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software The serial port control and status register is the Special Function Register SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits and RI SBUF Serial Port Buffer addr 99H reset value XX bits 7 6 5 4 3 2 1 0 SBUF The serial port receive and transmit registers are both accessed thru special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register Philips Electronics N V 2005 Page 33 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Standard Serial Interface SIOO PCON Power Control Register addr 87H reset value 0xxx0000 bits 7 6 5 4 3 2 1 0 svo gro m bit symbol Function PCON 7 SMOD Double baud rate
90. e been received the serial interrupt flag 1 is set and a valid status code can be read from S1STA This status code is used to vector to an inter rupt service routine and the appropriate action to be taken for each of these status codes is detailed in Table 12 The Slave Receiver mode may also be entered if arbitration is lost while SIO1 is in the Master mode see status 68H and 78H If the AA bit is reset during a transfer SIO1 will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset SIO1 does not respond to its own slave address or a gen eral call address However the I2C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus O Philips Electronics N V 2005 Page 59 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12 Interface 5101 Slave Transmitter mode In the Slave Transmitter mode a number of data bytes are transmitted to a master receiver see Figure 24 Data transfer is initialized as in the Slave Receiver mode When S1ADR and S1CON have been initialized SIO1 waits until itis addressed by its own slave address followed by the data direction bit which must be 1 R for SIO1 to operate in the Slave Transmitter mode After its own slave ad dress and the R bit have been received the serial interrupt flag SI is set and a valid status co
91. e data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins If the Accumulator holds 11000011B and RO holds 55H 01010101B then the instruction ORL A RO0 will leave the Accumulator holding the value 0D7H 11010111B When the destination is a di rectly addressed byte the instruction can set combinations of bits in any RAM location or hard ware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the Accumulator at run time The instruction ORL P1 00110010B will set bits 5 4 and 1 of output Port 1 ORL A lt A v Rn Page 118 of 132 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions ORL A direct Bytes 2 Cycles 1 Encoding 0 1 0 0 0 1 0 1 direct address Operation ORL lt A v direct ORL A Ri Bytes 1 Cycles 1 Encoding 0 1 0 0 0 1 1 i Operation ORL lt A v Ri ORL A data Bytes 2 Cycles 1 Encoding 0 1 0 0 0 1 0 0 immediate data Operation ORL lt A v data ORL direct A Bytes 2 Cycles 1 Encoding 9 1 0 0 0 0 1 0 direct address O
92. e to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles 5 1 4 Setting up the Interrupt Controller To use any of the interrupts in the 80C51 Family the following three steps must be taken 1 Setthe EA enable all bit in the IE register to 1 2 Setthe corresponding individual interrupt enable bit in the IE register to 1 3 Begin the interrupt service routine at the corresponding Vector Address of that interrupt see Table 2 In addition for external interrupts input pins t01 intO n i and 01 inti n i depending on whether the interrupt is to be level or transition activated bits 170 or IT1 in the TCON register may need to be set to 1 ITx 0 level activated ITx 1 transition activated 5 1 4 1 Assigning a Higher Priority to One or More Interrupts In order to assign higher priority to an interrupt the corresponding bit in the IPx register must be set to Remember that while an interrupt service is in progress it cannot be interrupted by a lower or same level interrupt O Philips Electronics N V 2005 Page 25 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Timers 0 and 1 5 2 Timers 0 and 1 This module comprises two 16bit timers counters timerO and timer1 Both can be configured to oper ate either as timers
93. e to the PC after in crementing the PC twice Therefore the range of destinations allowed is from 128 bytes preced ing this instruction to 127 bytes following it Example The label RELADR is assigned to an instruction at program memory location 0123H The in struction SJMP RELADR will assemble into location 0100H After the instruction is executed the PC will contain the value 0123H Note Under the above conditions the instruction following SJMP will be at 102H There fore the displacement byte of the instruction will be the relative offset 0123H 0102H 21H Put another way an SJMP with a displacement of OFEH would be a one instruction infinite loop Bytes 2 Cycles 2 Encoding ncoding 4 0 o o o o rel address Operation SJMP PC PC 2 PC PC rel O Philips Electronics N V 2005 Page 125 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions SUBB A lt src byte gt Function Description Example SUBB A Rn Bytes Cycles Encoding Operation SUBB A direct Bytes Cycles Encoding Operation SUBB A Ri Bytes Cycles Encoding Operation SUBB A data Bytes Cycles Encoding Operation Page 126 of 132 Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the Accumulator leaving the result in the Accumulator SUBB sets the carry borrow flag if a borrow i
94. each case state 08H is entered after a successful START condition is transmitted and normal serial transfer continues Note that the CPU is not involved in solving these bus hang up problems Bus Error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame Examples of illegal positions are during the serial transfer of an address byte a data or an acknowledge bit The SIO1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave When a bus error is detected SIO1 immediately switches to the not ad dressed Slave mode releases the SDA and SCL lines sets the interrupt flag and loads the status register with 00H This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 14 Page 72 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface SIO1 Handshake Solutions STA FLAG Q 3 1 1 SDA LINE 1 1 v SCL LINE lt lt START CONDITION 1 Unsuccessful attempt to send a Start condition 2 SDA line released 3 Successful attempt to send a Start condition state 08H is entered Figure 27 Recovering from a Bus Obstruction Caused by a Low Level on SDA 5 5 5 Slave
95. ed as 0 if the input voltage is greater than 3 0 V the input logic level is interpreted as 1 For low speed implementations it is advisable to use input filter circuits for the pins SDA and SCL to suppress noise on these signals Page 48 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions The output stages should consist of open drain transistors that can sink 3mA at VOUT 0 4 V These open drain outputs should not have clamping diodes to VDD Thus if the device is connected to the I2C bus and VDD is switched off the I2C bus is not affected Address Register STADR This 8 bit special function register may be loaded with the 7 bit slave address 7 most significant bits to which SIO1 will respond when programmed as a slave transmitter or receiver The LSB GC is used to enable general call address 00H recognition Comparator The comparator compares the received 7 bit slave address with its own slave address 7 most signifi cant bits in STADR It also compares the first received 8 bit byte with the general call address 00H If equality is found the appropriate status bits are set and an interrupt is requested Shift Register S1DAT This 8 bit special function register contains a byte of serial data to be transmitted or a byte which has just been received Data in S1DAT is always shifted from right to left the first bit to be transmitted is the MSB bit
96. ed as a handshake mechanism to suspend and resume serial transfer e I2C bus may be used for test and diagnostic purposes The HT I2C logic here also named SIO1 provides a serial interface that meets the I2C bus specifica tion and supports all transfer modes other than the low speed mode from and to the I2C bus The HT I2C logic handles bytes transfer autonomously It also keeps track of serial transfers and a status register S1STA reflects the status of HT I2C and the I2C bus The CPU interfaces to the I2C logic via the following four special function registers S1CON SIO1 con trol register SISTA 5101 status register S1DAT 5101 data register and S1ADR SIO1 slave address register The SIO1 logic interfaces to the external I2C bus via two port 1 pins SCL serial clock line and SDA serial data line A typical I2C bus configuration is shown in Figure 14 Figure 15 shows how a data transfer is ac complished on the bus Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus 1 Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an ac knowledge bit after each received byte Page 46 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions 2 Data transfer from a slave t
97. ed in modes 1 2 or 3 then the baudrate is doubled 0 The baudrate is not influenced PCON 6 Reserved write 0 reads 0 PCON 5 PCON 4 DPS Data pointer select implemented with dual data pointer option only otherwise reserved bit write 0 reads 0 1 Select DPTR1 for all DPTR accesses and for DPL and DPH Select for all DPTR accesses and for DPL and DPH PCON 3 GF1 General purpose flag bit PCON 2 GFO General purpose flag bit PCON 1 PD Power Down bit Setting this bit activates power down operation which is also indicated at output pin cpu powerdown o 0 IDL Idle mode bit Setting this bit activates idle mode operation which is also indicated at output pin idle Note If 1s are written to PD and IDL at the same time PD takes precedence User software should never write 1s to unimplemented bits since they may be used in other 80C51 Family products 2 5 6 1 Idle Mode An instruction that sets PCON 0 immediately switches into the idle mode so no further instruction is executed The clock signal is gated off from the CPU but not to the Timer and Serial Port functions The CPU status is preserved in its entirety the Stack Pointer Program Counter Program Status Word Accumulator and all other registers maintain their data during ldle The port pins hold the logical states they had at the time Idle was activated There are two ways to terminate the Idle Activation of any enabled in
98. el for interrupt input int req i 10 IP1 2 Priority level for interrupt input int req i 9 IP1 1 Priority level for interrupt input int req i 8 IP1 0 Priority level for interrupt input int req i 7 Bit values 0 low priority 1 high priority 5 1 3 Operation The HT80C51 provides up to 15 interrupt inputs Depending on the configuration of standard periph erals some of these inputs are already internally connected to interrupt sources in these peripherals For a description of these interrupt sources please see the description of the peripheral blocks Table 2 shows these default connections All of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending inter rupts can be canceled in software Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Registers IEN0 and IEN1 IENO also contains a global disable bit EA which disables all interrupts at once 5 1 3 1 Interrupt Priority Level Structure Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Registers IP0 and IP1 A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt can t be interrupted by any
99. er counter TH1 holds the value which is loaded into TL1 each time it overflows 11 stopped TMOD 3 GATEO Timer 0 gating control 1 Timer Counter 0 is enabled only while input pin 01 intO n iishigh and TRO TCON is 1 0 1 is enabled if TRO is set TMOD 2 C TO Timer 0 operation selection 1 counter operation clock source is input pin t0 count i 0 timer operation clock source is the clock input 01 1 i TMOD 1 TOM1 Timer 0 mode selection TMOD O TOMO 00 8048 timer mode TL0 serves as a 5bit prescaler 01 16bit timer counter THO TL0 are cascaded no prescaler 10 8bit auto reload timer counter THO holds the value which is loaded into TLO each time it overflows 11 TLO is an 8bit timer counter controlled by standard timer 0 control bits THO is a further 8bit timer controlled by timer 1 control bits Page 26 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Timers 0 and 1 Handshake Solutions TCON Timer Counter Control addr 88H reset value 00H bits 7 6 5 4 3 2 1 0 bit symbol Function TCON 7 TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine or clearing the bit in software TCON 6 TR1 Timer 1 Run control bit Set cleared by software to turn Timer 1 on off 1 Timer 1 on 0 Timer 1 off TCON 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow C
100. eration XRL A lt A direct XRL A Ri Bytes 1 Cycles 1 Encoding 0 1 1 0 0 1 1 i Operation XRL A lt A Ri XRL A data Bytes 2 Cycles 1 Encoding 9 1 1 0 0 1 0 0 immediate data Operation XRL A A data XRL direct A Bytes 2 Cycles 1 Encoding O 1 1 0 0 1 O0 direct address Operation XRL direct direct A XRL direct Zdata Bytes 3 Cycles 2 Encoding 0 1 1 0 0 0 1 1 direct address immediate data Operation XRL direct direct data O Philips Electronics N V 2005 Page 129 of 132 HT80C51 User Manual Handshake Solutions List of Tables Appendix A1 List of Tables Table 1 80C5T SER Reset Values datei dre edere toa tee ss feo ee ga ERE RR xia 18 Table 2 Interrupt Signals Vectors and Priorities ssssssssssssssseeeeee 23 Table 3 Timer Q as a TUNG a ees saat a en at et cin in ie 31 Table 4 Timer Q as a Counter eerte te ato et eek Ret a o 31 Table 5 Timer as a Ter io oett bti iem niti audiet abe oda 32 Table 6 Timer 1cas a Counter tinet ate ete ane ti ie Rees 32 Table 7 Timer 1 Generated Commonly Used Baud Rates 36 Table 8 oetlal Port Set p 5 c ihe Ten n oa nile utei
101. est lines of the interrupt controller The following table and Figure 8 describe these sources and connections For interrupt priorities and interrupt vectors see the description of the interrupt con troller interrupt Description Interrupt source signal timer 0 IEO Set by hardware when external interrupt t01_int0_n_i is detected If SFR intO bit ITO is set the flag is set on a falling edge of the external interrupt if ITO is cleared a low level on the external interrupt line cause an interrupt Cleared when interrupt is processed TFO Timer 0 overflow flag int1 Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine or clearing the bit in software timer 1 IE1 Set by hardware when external interrupt 601 inti n iisdetected I SFR int2 bit IT1 is set the flag is set on a falling edge of the external interrupt if IT1 is cleared a low level on the external interrupt line cause an interrupt Cleared when interrupt is processed TF1 Timer 1 overflow flag int3 Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine or clearing the bit in software gt ITO gu TFO intl db m IT1 X TF1 gt int3 101 intO n i IEO gt into 01 intl n i gt 1 1 n Figure 8 Interrupt Sources From the Timers 0 and 1 Page 28 of 132 Philips Electronics N V
102. f 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions CJNE A data rel Bytes 3 Cycles 2 Encoding 1 0 1 1 0 immediate data rel address Operation PC lt 3 IF A data THEN IF A data THEN ELSE CJNE Rn data rel Bytes 3 Cycles 2 lt PC relative offset Cy C lt 0 Encoding 1 0 1 Operation lt 3 IF Rn lt gt data THEN IF Rn lt data THEN ELSE CJNE Ri data rel Bytes 3 Cycles 2 Encoding 1 0 1 1 immediate data rel address lt PC relative offset 0 immediate data rel address Operation PC lt PC 3 IF Ri lt gt data THEN IF Ri lt data THEN ELSE Page 98 of 132 lt PC relative offset lt 1 0 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions CLRA Function Description Example Bytes Cycles Encoding Operation CLR bit Function Description Example CLRC Bytes Cycles Encoding Operation CLR bit Bytes Cycles Encoding Operation O Philips Electronics N V 2005 Clear Accumulator The Accumulator is cleared all bits reset to zero No flags are affected The Accumulator
103. fer data from the master to a slave with the most significant bit sent first Serial Clock SCK The serial clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles Since the master device generates SCK this line becomes an input on a slave device spi sck i and an output at the master device spi sck o As shown in Figure 29 four possible timing relationships may be chosen by using control bits CPOL and CPHA in the serial peripheral control register SPCR Both master and slave devices must operate with the same timing The master device always places data on the MOSI line a half cycle before the clock edge SCK in order for the slave device to latch the data Two bits SPRO and SPR in the SPCR of the master device select the clock rate In a slave device SPRO and SPR have no effect on the operation of the SPI Slave Select SS The slave select input line spi ss n i is used to select a slave device It has to be low prior to data transactions and must stay low for the duration of the transaction The spi ss iline on the master must be tied high SCK CYCLE 1 2 3 4 5 6 7 8 FOR REFERENCE SCK CPOL 0 SCK CPOL 1 E SAMPLE INPUT v v v v v v v v 0 DATA OUT K MSB 6 5 4 3 2 1 LSB SA
104. fts in or shifts out an 8 bit byte followed by an acknowledge bit The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU Serial data is shifted through the ACK flag into S1DAT on the rising edges of serial clock pulses O Philips Electronics N V 2005 Page 53 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 on the SCL line When a byte has been shifted into S1DAT the serial data is available in STDAT and the acknowledge bit is returned by the control logic during the ninth clock pulse Serial data is shifted out from S1DAT via a buffer BSD7 on the falling edges of clock pulses on the SCL line When the CPU writes to S1DAT BSD7 is loaded with the content of S1DAT 7 which is the first bit to be transmitted to the SDA line see Figure 20 After nine serial clock pulses the eight bits in S1DAT will have been transmitted to the SDA line and the acknowledge bit will be present in ACK Note that the eight transmitted bits are shifted back into S1DAT The Control Register S1TCON The CPU can read from and write to this 8 bit directly addressable SFR Two bits are affected by the SIO1 hardware the SI bit is set when a serial interrupt is requested and the STO bit is cleared when a STOP condition is present on the I2C bus The STO bit is also cleared when ENS1 0 7 6 5 4 3 2 1 0 S1CON D8H ENS1 the SIO1 Enable Bit ENS1 0 When ENS1 is 0 th
105. guration O Philips Electronics N V 2005 Page 79 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Watchdog Timer under development 5 7 Watchdog Timer under development This module comprises an 8bit watchdog timer with prescaler 5 7 1 Options The watchdog timer can be selected ordered by using option t b d 5 7 2 Special function registers T3 T3 watchdog timer register addr reset value bits 7 6 5 4 3 2 1 0 bit Symbol Function T3 7 Watchdog timer count register Specifies the interval until the next timer T3 0 overflow Writeable when input ena 1 5 7 3 Interrupts No interrupts are generated If the watchdog timer expires a pulse on the reset output rst o is generated 5 7 4 Operation The Watchdog Timer consists of an 11 bit prescaler and an 8 bit timer It is controlled by the Watchdog Enable pin wat ena i When ena i 1 the timer is enabled and the Power down mode is disabled When wdt i 0 the timer is disabled and the Power down mode is enabled In the Idle mode the Watchdog Timer and reset circuitry remain active The Watchdog Timer is shown in O The timer interval is derived from the frequency of clock input wat cik i using the following formula _ 2048x 256 T3 p When a timer overflow occurs a reset output pulse is generated at the pin wdt rst o for 3 clock cycles To prevent a system reset the timer must be reloa
106. he SFRs of the CPU are available in all derivatives of this microcontroller and are described in the text below Peripheral blocks are optional and so are the SFRs which are implemented inside these peripherals Therefore the peripheral SFRs are described with the peripheral blocks in Chapter 5 O Philips Electronics N V 2005 Page 13 of 132 HT80C51 User Manual Handshake Solutions Memory Organization Special Function Registers 2 5 1 Accumulator ACC ACC is the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as A ACC A Accumulator addr EOH reset value 00H bits 7 6 5 4 3 2 1 0 2 5 2 Register B The B register is used during multiply and divide operations For other instructions it can be treated as another scratch pad register B Register B addr FOH reset value 00H bits 7 6 5 4 3 2 1 0 2 5 3 Program Status Word PSW The program status word PSW register contains program status information as detailed below PSW Program Status Word addr DOH reset value 00H bits 7 6 5 4 3 2 1 0 ac ro rst ov P bit symbol function PSW 7 CY Carry Flag PSW 6 AC Auxiliary Carry Flag PSW 5 FO Flag 0 available to the user for general purpose PSW 4 RS1 Register Bank selector bit 1 PSW 3 RSO Register Bank selector bit 0 RS1 RSO select the register bank as follows 00 BankO 00 07H 01 Bank1 08H 10 Bank2 10H 17H 11 Bank3
107. he output values of output pins gpio pouti o 7 0 POUT1 0 POUT2 Output Port 2 addr AOH reset value FFH configurable bits 7 6 5 4 3 2 1 0 POUT2 bit symbol Function POUT2 7 set the output values of output pins gpio pout2 o 7 0 POUT2 0 Page 42 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules General Purpose lOs Handshake Solutions POUT3 Output Port 3 addr BO reset value FFH configurable bits 7 6 5 4 3 2 1 0 POUT3 bit symbol Function POUT3 7 set the output values of output pins gpio pout3 o 7 0 POUT3 0 POUTx Output Port x x23 addr reset value configurable bits 7 6 5 4 3 2 1 0 POUTx bit symbol Function POUTx 7 set the output values of output pins gpio poutx o 7 0 POUTx 0 PINx Input Port x addr reset value configurable not applicable bits 7 6 5 4 3 2 1 0 bit symbol Function PINx 7 Read the values of input pins gpio pinx o 7 0 PINx 0 Write accesses have no effect 5 4 3 Interrupts No interrupts are generated 5 4 4 Operation Write accesses to output ports directly set the related output pins There is no synchronization to any external clocks done Read accesses to output ports return the contents of the output latches Read accesses to input port return the values that are applied to their related input pins Write ac cesses to an input port have no effect Philips Electronics N V 2005 Page 43 of 132 HT80C51 User Manual Handshake Solutions
108. he receive circuits are reset and the unit goes back to looking for another 1 to O transition This is to provide rejection of false start bits After the 9 data bits and the stop bit have been received the result is loaded into SBUF and RB8 and RI is set to 1 but that is only done if the following conditions are met 1 RI 0 2 Either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the first 8 data bits go into SBUF the 9 data bit goes into RB8 and RI is activated Then the unit goes back to looking for a 1 to O transition in sio rxd i Page 38 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Standard Serial Interface SIOO Handshake Solutions HT SFR bus int 4 Sio clk i t1 overflow Sio clk o Sio active o RECEIVE sio mode0 o Figure 13 Block Diagram of Serial Interface in Mode 1 2 and 3 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wan
109. he third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010B The Accumulator holds 56 01010110B The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 3 2 0 0 1 0 0 0 0 0 bit address rel address JB lt 3 IF bit 1 THEN PC lt rel Page 106 of 132 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions JBC bit rel Function Description Example Bytes Cycles Encoding Operation JC rel Function Description Example Bytes Cycles Encoding Operation O Philips Electronics N V 2005 Jump if Bit is set and Clear bit If the indicated bit is a one branch to the address indicated otherwise proceed with the next in struction The bit will not be cleared if it is already a zero The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will read from the output data
110. ien Malte meets 40 Table 9 Serial Clock Rates needs Update 57 Table 10 Master Transmitter mode not available for slave only 65 Table 11 Master Receiver Mode not available for slave only 66 Table 12 Slave Receiver modes ces sr een ai tete et eet ettet o ed 68 Table 13 Slave Transmitter 69 Table 14 Miscellaneous emere nnn nn 70 Page 130 of 132 O Philips Electronics N V 2005 HT80C51 User Manual List of Figures Handshake Solutions A2 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 HT80C51 Architecture CPU centered sssssssssee em emen 7 ELEO0 C5 T AChIteCtUre neue ere et PR E d eruta e EE AD MM RE 8 HT80C51 Memory Mapa tranor aeaaeai NEN 9 Memory map of Internal Data arser ee er ARE EEEE RE O
111. ince the serial transfer is suspended until the serial interrupt flag is cleared by software When a serial interrupt routine is entered the status code in S1STA is used to branch to the appropri ate service routine For each status code the required software action and details of the following serial transfer are given in Table 10 to Table 14 Master Transmitter mode not available for slave only version In the Master Transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 21 Before the Master Transmitter mode can be entered S1CON must be initialized as follows 1 0 bit rate 7 bit rate S1CON D8H 6 5 4 3 2 1 0 0 0 X CRO CR1 and CR2 define the serial bit rate ENS1 must be set to logic 1 to enable SIO1 If the AA bit is reset SIO1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus In other words if AA is reset SIOO cannot enter a Slave mode STA STO and SI must be reset The Master Transmitter mode may now be entered by setting the STA bit using the SETB instruction The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes free When a START condition is transmitted the serial interrupt flag SI is set and the status code in the status register 515 will be 08H This status code must be used to vector to an interrupt service routine that loads S1DAT
112. is causes 5101 to enter the not addressed Slave mode a defined state and to clear the STO flag no other bits in S1CON are affected The SDA and SCL lines are released a STOP condition is nottransmitted 5 5 4 6 Some Special Cases The SIO1 hardware has facilities to handle the following special cases that may occur during a serial transfer Simultaneous Repeated START Conditions from Two Masters A repeated START condition may be generated in the Master Transmitter or Master Receiver modes A special case occurs if another master simultaneously generates a repeated START condition see Figure 25 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the SIO1 hardware detects a repeated START condition on the I2C bus before generating a re peated START condition itself it will release the bus and no interrupt request is generated If another master frees the bus by generating a STOP condition SIO1 will transmit a normal START condition state 08H and a retry of the total serial data transfer can commence Page 70 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions Data Transfer After Loss of Arbitration Arbitration may be lost in the Master Transmitter and Master Receiver modes see Figure 17 Loss of arbitration is indicated by the following states in 515 38H 68H 78H and BOH see
113. is written to the shift register at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again Data is shifted out thru output pin spi mosi o and shifted in from input pin spi miso i In a slave mode the slave start logic receives a logic low at pin spi ss n i and the clock at input pin spi sck i Thus the slave is synchronized with the master Data from the master is received serially at the slave MOSI line spi mosi i and loads the 8 bit shift register After the 8 bit shift register is loaded its data is parallel transferred to the read buffer During a write cycle data is written into the shift register then the slave waits for a clock train from the master to shift the data out on the slave s MISO line spi miso o 5 6 4 1 Bitlevel protocol Master In Slave Out MISO The MISO line is configured as an input in a master device spi miso i and as an output in a slave device spi miso o ltis used to transfer data from the slave to the master with the most significant bit sent first The MISO line of a slave device should be placed in the high impedance state if the slave is not selected O Philips Electronics N V 2005 Page 77 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Serial Peripheral Interface SPI Master Out Slave In MOSI The MOSI line is configured as an output in a master device spi mosi o and as an input in a slave device spi mosi i ltis used to trans
114. knowledge flag type of acknowledge to be returned return NOT ACK 0 return ACK S1CON 1 CR1 Clock rate bit 1 not implemented in slave only version S1CON 0O CRO Clock rate bit 0 not implemented in slave only version Note For not implemented bits always write Os read accesses always return 0 The master and slave operate on a common clock signal which depends on the actual values of the signals CR1 and CR2 Changing one or more of the following bits CRO CR1 or CR2 during a data transfer may lead to unpredictable results The baud rates are derived from a dedicated clock input pin i2c clk i Note Baud rate generation and clock input 32c cik i are not available for the slave only ver sion Page 44 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions CR2 CR1 CRO Baud rate 0 0 0 foc i256 0 0 1 foc 224 0 1 0 foc a 192 0 1 1 foc a 1 160 1 0 0 foc ax 960 1 0 1 foc a 120 1 1 0 foc ax 1 60 1 1 1 Timer 1 overflow rate 8 S1ADR SIO1 slave address register addr DBH reset value 00H bits 7 6 5 4 3 2 1 0 bit symbol Function S1ADR 7 Own slave address in slave mode S1ADR 6 S1ADR 5 S1ADR 4 S1ADR 3 S1ADR 2 S1ADR 1 S1ADR 0 GC General Call enable 1 General call address is recognized 0 General call address is not recognized S1DAT SIO1 data register addr DAH reset value 00H bits 7 6
115. leared by hardware when processor vectors to interrupt routine or clearing the bit in software TCON 4 TRO Timer 0 Run control bit Set cleared by software to turn Timer 1 on off 1 Timer 0 on 0 Timer 0 off TCON 3 IE1 Interrupt 1 edge flag Set by hardware when external interrupt is de tected Cleared when interrupt is processed TCON 2 IT1 Interrupt 1 type control bit 1 External interrupt 601 inti n iis edge sensitive falling edge 0 External interrupt t01 inti n i is level sensitive low level TCON 1 IEO Interrupt 0 edge flag Set by hardware when external interrupt is de tected Cleared when interrupt is processed TCON O ITO Interrupt O type control bit External interrupt 01 0 is edge sensitive falling edge 0 External interrupt t01_int0_n_i is level sensitive low level TLO Timer 0 Counter Register Low Byte addr 82H reset value 00H bits 7 6 5 4 3 2 1 0 TLO THO Timer 0 Counter Register High Byte addr 84H reset value 00H bits 7 6 5 4 3 2 1 0 THO TL1 Timer 1 Counter Register Low Byte addr 83H reset value 00H bits 7 6 5 4 3 2 1 0 TL1 TH1 Timer 1 Counter Register High Byte addr 85H reset value 00H bits 7 6 5 4 3 2 1 0 1 O Philips Electronics N V 2005 Page 27 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Timers 0 and 1 5 2 3 Interrupts Each of the timers can generate two separate interrupt signals which are directly connected to inter rupt requ
116. les Encoding Operation Page 96 of 132 Logical AND for bit variables If the Boolean value of the source bit is a logical 0 then clear the carry flag otherwise leave the carry flag in its current state A slash preceding the operand in the assembly language indi cates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct addressing is allowed for the source operand Set the carry flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV C P1 0 LOAD CARRY WITH INPUT PIN STATE ANL C ACC 7 AND CARRY WITH ACCUM BIT 7 ANL C OV AND WITH INVERSE OF OVERFLOW FLAG 2 1 0 0 0 0 0 1 0 bit address ANL C lt C bit 2 2 1 0 1 1 0 0 0 0 bit address ANL C lt C A bit O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions CJNE lt dest byte gt lt src byte gt rel Function Description Example Compare and Jump if Not Equal CJNE compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigne
117. master the hardware waits until the bus is free before the Master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the Master mode SIO1 switches to the Slave mode im mediately and can detect its own slave address in the same serial transfer Philips Electronics N V 2005 Page 47 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 e Voo Rp Rp e e e e SDA PC bus SCL P1 7 SDA P1 6 SCL OTHER DEVICE WITH OTHER DEVICE WITH P89C66x 2 INTERFACE 2 INTERFACE Figure 14 Typical C Bus Configuration 1 4 STOP SDA CONDITION REPEATED START CONDITION SLAVE ADDRESS gt ACKNOWLEDGMENT RW SIGNAL FROM RECEIVER DIRECTION BIT J ACKNOWLEDGMENT SIGNAL FROM RECEIVER CLOCK LINE HELD LOW WHILE INTERRUPTS ARE SERVICED SCL 1 2 7 8 9 1 2 3 8 9 ACK ACK S REPEATED IF MORE BYTES 1 1 ARE TRANSFERRED I o START CONDITION Figure 15 Data Transfer on the Bus 5 5 4 2 SIO1 Implementation and Operation Figure 16 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks Input Filters and Output Stages The input filters should have I2C compatible input levels If the input voltage is less than 1 5 V the input logic level is interpret
118. mer function counting timer clocks 601 cik i and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode is provided for applications requiring an extra 8 bit timer on the counter With timer 0 in mode 3 an 80C51 can look like it has three timer counters When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial port as a baud rate generator or in fact in any application not requiring an interrupt t01 clk i v C TO 0 TLO J QI inti 8 Bits 1 t0 count i Control TRO ep GATEO 0 101 n i THO 101 i 8 Bits TF1 L int3 Figure 11 Timer counter 0 mode 3 Two 8bit counters Page 30 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Timers 0 and 1 Handshake Solutions 5 2 5 Setting up the Timers Table 3 and Table 4 give some values for TMOD which can be used to set up Timer 0 in different modes For these tables it is assumed that only one timer is being used at a time If it is desired to run Timers 0 and 1 simultaneously in any mode the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 Table 5 and Table 6 For example if it is desired to run Timer O in mode 1 GATE external control and Timer 1 in mode 2 C
119. mulator 1 1 CPL A Complement Accumulator 1 1 RL A Rotate Accumulator left 1 1 RLC A Rotate Accumulator left through the carry 1 1 RR A Rotate Accumulator right 1 1 RRC A Rotate Accumulator right through the carry 1 1 SWAP A Swap nibbles within the Accumulator 1 1 DATA TRANSFER MOV A Rn Move register to Accumulator 1 1 MOV A direct Move direct byte to Accumulator 2 1 MOV A Ri Move indirect RAM to Accumulator 1 1 MOV A data Move immediate data to Accumulator 2 1 MOV Rn A Move Accumulator to register 1 1 MOV Rn direct Move direct byte to register 2 2 MOV RN data Move immediate data to register 2 1 MOV direct A Move Accumulator to direct byte 2 1 MOV direct Rn Move register to direct byte 2 2 MOV direct direct Move direct byte to direct 3 2 MOV direct Ri Move indirect RAM to direct byte 2 2 MOV direct data Move immediate data to direct byte 3 2 MOV Ri A Move Accumulator to indirect RAM 1 1 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate data to indirect RAM 2 1 MOV DPTR data16 Load Data Pointer with a 16 bit constant 3 2 MOVC A A DPTR Move Code byte relative to DPTR to Acc 1 2 MOVC A A PC Move Code byte relative to PC to Acc 1 2 MOVX A Ri Move external RAM 8 bit addr to ACC 1 2 MOVX A DPTR Move external RAM 16 bit addr to Acc 1 2 MOVX A Ri A Move Acc to external RAM 8 bit addr 1 2 MOVX DPTR A Move Acc to external RAM 16 bit addr 1 2 PUSH direct Push direct byte onto stack 2 2 POP direct Pop dire
120. naffected 1 1 o 1 0 0 0 4 1 RL An 1 lt An n 0 6 lt A7 Rotate Accumulator Left through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit position No other flags are affected The Accumulator holds the value OC5H 11000101B and the carry is zero The instruction RLC A leaves the Accumulator holding the value 8AH 10001010B with the carry set 1 1 RLC 1 lt An n 2 0 6 A0 C lt A7 Page 123 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions RRA Function Description Example Bytes Cycles Encoding Operation RRCA Function Description Example Bytes Cycles Encoding Operation Page 124 of 132 Rotate Accumulator Right The eight bits in the Accumulator are rotated one bit to the right Bit O is rotated into the bit 7 posi tion No flags are affected The Accumulator holds the value OC5H 11000101B The instruction RR A leaves the Accumulator holding the value OE2H 11100010B with the carry unaffected 1 1 o olo 4 1 RR lt An 1 n 2 0 6 A7 lt A0 Rotate Accumulator Right through the Carry flag The eight bits in the Accumulator an
121. ng timer 1 signals in Figure 9 t01 ck i v C T1 0 i TH1 TH1 A tog 5 Bits 8 Bits I TF1 interrupt C T1 1 t1 count i i Control 1 GATE1 a gt D t01_int1_n_i Figure 9 Timer Counter mode 0 13bit counter 5 2 4 2 Mode 1 Mode 1 is the same as mode 0 except that the timer register is being run with all 16 bits 5 2 4 3 Mode 2 Mode 2 configures the timer register as an 8bit counter TL1 with automatic reload as shown in Figure 10 Overflow from TL1 not only sets TF1 but also reloads TL1 with the contents of TH1 which is preset by software The reload leaves TH1 unchanged Mode 2 operation is the same for timer counter 0 Philips Electronics 2005 Page 29 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Timers 0 and 1 101 i Y C T1 0 TL1 TS of 4 8 Bits TF1 interrupt C T1 1 t1 count i Control TRI Reload GATE1 m CNN zm EE 8 Bits t01 int1n i Figure 10 Timer counter Mode 2 8bit auto reload 5 2 4 4 Mode 3 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode establishes TL0 and THO as two separate counters The logic for mode on timer 0 is shown in Figure 11 TLO uses the timer 0 control bits GATEO 01 intO n i and THO is locked into a ti
122. of the I2C bus and generates a START condition if the bus is free If the bus is not free then SIO1 waits for a STOP condition which will free the bus and generates a START condition after a delay of half a clock period of the internal serial clock genera tor If STA is set while SIO1 is already in a Master mode and one or more bytes are trans mitted or received SIO1 transmits a repeated START condition STA may be set at any time STA may also be set when SIO1 is an addressed slave STA 0 When the STA bit is reset no START condition or repeated START condition will be generated The STOP Flag STO STO 1 When the STO bit is set while SIO1 is in a Master mode a STOP condition is transmit ted to the I2C bus When the STOP condition is detected on the bus the SIO1 hard ware clears the STO flag In a Slave mode the STO flag may be set to recover from an error condition In this case no STOP condition is transmitted to the I2C bus How ever the SIO1 hardware behaves as if a STOP condition has been received and O Philips Electronics N V 2005 Page 55 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12 Interface 5101 switches to the defined not addressed Slave Receiver mode The STO flag is auto matically cleared by hardware If the STA and STO bits are both set the a STOP condition is transmitted to the 12C bus if SIO1 is in a Master mode in a Slave mode SIO1 generates an internal
123. on of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed thru special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register 5 3 4 1 Overview operating modes The serial port can operate in 4 modes Mode 0 Serial data enters at input pin sio rxd i and exits through output pin sio txd o Pin sio clk o outputs the shift clock during transmission 8 bits are transmitted received LSB first The baud rate is fixed at the clock input sio clik i This mode is restricted to half duplex operation only Page 34 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Standard Serial Interface SIOO Handshake Solutions 1 10 bits are transmitted through sio txd received through sio rxd start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Spe cial Function Register SCON The baud rate is derived from the overflow rate of timer 1 2 11 bits are transmitted through sio txd or received through sio rxd start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8
124. only version The description above covers the full featured version of the HT I2C module with master and slave modes The slave only version of the HT I2C implements a subset of these features This means the slave only version covers the behaviour and features as described for the complete version but some features and pins are not implemented It comprises e master transmit mode e master receiver mode e no baud rate generator e bits CR1 CR2 and STA in the SFR S1CON are reserved 0 e no clock input pin i2c clk i 5 5 6 Application notes An 12 byte oriented system driver is described in application note AN435 Please visit http www semiconductors philips com products all appnotes html Philips Electronics N V 2005 Page 73 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Serial Peripheral Interface SPI 5 6 Serial Peripheral Interface SPI This serial peripheral interface is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode The main features are 5 6 1 Full Duplex Three Wire Synchronous Transfers Master or Slave Operation Four Programmable Master Bit Rates Programmable Clock Polarity and Phase End of Transmission Interrupt Flag Write Collision Flag Protection Options The SPI interface can be selected ordered by using option HT80C51 SPI 5 6 2 Special function registers SPCR SPSR SPDR SPCR S
125. ontents of the Accumulator with the sixteen bit data pointer and load the resulting sum to the program counter This will be the address for subsequent instruction fetches Sixteen bit addition is performed modulo 216 a carry out from the low order eight bits propa gates through the higher order bits Neither the Accumulator nor the Data Pointer is altered No flags are affected An even number from 0 to 6 is in the Accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP TBL MOV DPTR JMP_TBL JMP JMP TBL AJMP LABELO AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the Accumulator equals 04H when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other ad dress 1 2 0 1 1 110 0 1 1 JMP PC lt A DPTR Jump if Bit Not set If the indicated bit is a zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010B The Accumulator holds 56H 01010110B The instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LA
126. ontroller n erre Tere tuer 20 5 1 1 ODPUONS rete Eee en tre te it eee eder eem 20 5 1 2 Special function registers IENO IEN1 IPO 1 20 5 1 3 Operations zaor ba et ne Pes ni Mu Re Dr 22 5 1 4 Setting up the Interrupt Controller 25 5 2 Timers O and 1 2 2 eterne 26 5 2 1 PUOINS 13 Bie AEE tam 26 5 2 2 Special function registers TMOD TCON TLO TL1 1 26 5 2 3 lntetr pte ai 28 5 2 4 OPC ations otii pisi cani tun iet dein toe aaa 29 5 2 5 Setting up the Timers iion eri t t eri e e ert ae b get e gin 31 5 3 Standard Serial Interface 5100 nnn 33 5 3 1 2 2 hime Mis utis Durs cese Lites ela 33 5 3 2 Special function registers SCON SBUF 5 33 O Philips Electronics N V 2005 Page 3 of 132 HT80C51 User Manual Handshake Solutions Table of Contents 5 3 3 Interr pte i ette eder dee de eie pina Ue de ae ado cde 34 5 3 4 Operation ene ed e e e eR LU tere f etes 34 5 3 5 Setting up the serial port eee 40 5 4 General Purpose lOs 5 iere cotto eoe rhe rn Ret rece Rea E REED RE De rk Eee 42
127. other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second prior ity structure determined by the polling sequence as summarized in Table 2 Page 22 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Interrupt Controller Handshake Solutions standard internal t t t t interrup vector priority within interrupt connection input address select if peripheral is selected level int req 0 IEO timer 0 0003H IENO O IP0 0 highest int req 1 timer 0 000BH IENO 1 iP0 1 int req 2 IE1 timer 1 0013H IENO2 IP0 2 int_req_i 3 TF1 timer 1 001BH IENO 3 IP0 3 int req i4 Rl or TI SIO UART 0023H IENO4 IP0 4 int req 5 SI 12C 002BH IEN0 5 IP0 5 int req i 6 SPI 0033H IEN0 6 IP0 6 int req i 7 003BH IEN1 0 IP1 0 int req i 8 0043H IEN1 1 IP1 1 int req i 9 004BH IEN1 2 1P1 2 int req i 10 0053H IEN1 3 IP1 3 int req i 11 005BH IEN1 4 IP1 4 int req i 12 0063H IEN1 5 IP1 5 int req i 13 006BH IEN1 6 IP1 6 int req i 14 0073H IENT7 1 17 Note The priority within level structure is only used to resolve simultaneous requests of the same priority level
128. ous mode of operation cpu sync i 0 the CPU runs at its natural speed and Slow cpu clk i does not slow it down 4 2 Peripheral clocks In a traditional synchronous 80C51 system all clocks for peripherals are derived from the clock for the CPU or from the CPU s machine cycle which is usually 1 12 or 1 6 of the CPU clock frequency depending on the implementation of the CPU Hence all timing specifications like timer overflow times or baud rates were specified in relation to the CPU clock In a handshake design no single global clock source is needed the clock for the CPU can even be omitted which is the standard configuration for the HT80C51 Thus for each peripheral that needs a clock e g timers serial interfaces or the synchronous SFR bus a dedicated clock input is provided So the optimum clock frequency can be supplied to each peripheral completely independent from all other clock frequencies Also note that there is no internal clock divider implemented divide by 12 or 6 Thus compared to a synchronous design the same timings e g baud rates can be achieved with a lower input clock frequency resulting in lower power consumption The timing specifications of the peripherals are related to their specific input clock frequencies O Philips Electronics N V 2005 Page 19 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Interrupt Controller 5 Peripheral Modules For the HT80C51 a number of standar
129. peration ORL direct direct v A ORL direct Zdata Bytes 3 Cycles 2 Encoding O 1 0 0 0 1 1 direct address immediate data Operation ORL direct direct v data O Philips Electronics N V 2005 Page 119 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions ORL C lt src bit gt Function Logical OR for bit variables Description Set the carry flag if the Boolean value is a logical 1 leave the carry in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical comple ment of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Example Set the carry flag if and only if P1 0 1 ACC 7 1 or OV 0 ORL C P1 0 LOAD CARRY WITH INPUT PIN P10 ORL C ACC 7 OR CARRY WITH THE ACC BIT 7 ORL C OV OR CARRY WITH THE INVERSE OF OV ORL C bit Bytes 2 Cycles 2 Encoding 4 4 O 01 0 bit address Operation ORL C lt C v bit ORL C bit Bytes 2 Cycles 2 Encoding 4 o 1 o 0 o0 bit address Operation ORL C C v bit Page 120 of 132 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions POP direct
130. poses This can be done after each bit or after a complete byte transfer SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the ac knowledge bit has been transferred The serial interrupt flag SI is set and the stretching continues until the serial interrupt flag is cleared SDA 1 Another device transmits identical serial data 2 Another device overrules a logic1 dotted line transmitted by SIO1 master by pulling the SDA line low Arbitration is lost and SIO1 enters the slave receiver mode 3 SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmittedSlIO 1 will not generate clock pulses for the next byte Data on SDA originates from the new master once ithas won arbitration Figure 17 Arbitration Procedure O Philips Electronics N V 2005 Page 51 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules 12C Interface 5101 SPACE DURATION MARK DURATION 1 Another service pulls the SCL line low before the SIA mark duration is complete The serial clock generator is immediately reset and commences with the space duration by pulling SCL low 2 Another device still pulls the SCL line low after SIA releases SCL The serial clock generator is forced into the wait state until the SCL line is released 3 The SCL line is released and the serial clock generator commences with the mark duration Figur
131. processor can autonomously do a complete single or triple DES en cryption or decryption Features e two 56bit key registers e 64bit text register for encryption and decryption e Single DES encryption e single DES decryption e triple DES encryption e triple DES decryption 5 8 1 Options The triple DES converter can be selected ordered by using option HT80C51 DES 5 8 2 Special function registers DCON DKEY DTXT DCON DES control register write only addr COH reset value XX bits 7 6 5 4 3 2 1 0 DCMD bit symbol Function DCON 7 reserved bits DCON 6 write always 0 read 0 DCON 5 DCON 4 DCON 3 DCON 2 Command for triple DES converter For a list of commands see table DCON 1 below DCON 0O The DCON register is write only The value which is written into DCON determines the command for the triple DES converter This command is started immediately after DCON has been written DCMD command description Store key in KEYO Store key in KEY1 Swap KEYO and KEY1 Reverse the order of bytes in text register Single DES encryption Single DES decryption Triple DES encryption Triple DES decryption ON O Page 82 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Triple DES Converter Handshake Solutions DKEY DES key register write only addr C1H reset value XX bits 7 6 5 4 3 2 1 bit symbol Function DKEY 7 Tbit slice of the key regis
132. ransmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all re ceived bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the I2C bus will not be released 5 5 4 1 Modes of Operation The on chip SIO1 logic may operate in the following four modes 1 Master Transmitter mode not available for slave only version Serial data output through SDA while SCL outputs the serial clock The first transmitted byte contains the slave address of the receiving device 7 bits and the data direction bit In this mode the data direc tion bit R W will be logic 0 and we say that a W is transmitted Thus the first byte transmitted is SLA W Serial data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is re ceived START and STOP conditions are output to indicate the beginning and the end of a serial transfer 2 Master Receiver Mode not available for slave only version The first transmitted byte contains the slave addres
133. ration MOV lt Rn O Philips Electronics N V 2005 Page 111 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions MOV A direct Bytes 2 Cycles 1 Encoding direct address Operation MOV A lt direct MOV A Ri Bytes 1 Cycles 1 Encoding 1 1 1 o lo 4 1 Operation MOV lt Ri MOV A data Bytes 2 Cycles 1 Encoding 0 1 1 1 0 1 0 0 immediate data Operation MOV A lt data MOV Rn A Bytes 1 Cycles 1 Encoding 4 1 1 4 1 r r r Operation MOV MOV Rnirect Bytes 2 Cycles 2 Encoding 1 0 1 1 r r r direct address Operation MOV Rn lt direct MOV Rn Zdata Bytes 2 Cycles 1 Encoding 0 1 1 1 1 r r r immediate data Operation MOV Rn lt data MOV A ACC is not a valid instruction Page 112 of 132 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions MOV direct A Bytes 2 Cycles 1 Encoding 4 4 1 0 4 0 1 direct address Operation MOV direct A MOV direct Rn Bytes 2 Cycles 2 Encoding 1 0 0 1 r r r direct address Operation MOV direct lt Rn MOV direct direct Bytes 3
134. rnal RAM locations 7EH and 7FH set to OFFH and DEC lt 1 DEC Rn lt Rn 1 0 0 0 1 0 1 0 1 direct address DEC direct lt direct 1 DEC Ri lt Ri 1 Page 102 of 132 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions DIV AB Function Divide Description DIV AB divides the unsigned eight bit integer in the Accumulator by the unsigned eight bit integer Example Bytes Cycles Encoding Operation in register B The Accumulator receives the integer part of the quotient register B receives the integer remain der The carry and OV flags will be cleared Exception if B had originally contained 00H the values returned in the Accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case The Accumulator contains 251 OFBH or 11111011B and B contains 18 12H or 00010010B The instruction DIV AB will leave 13 in the Accumulator ODH or 00001101B and the value 17 11H or 00010001B in B since 251 13 x 18 17 Carry and OV will both be cleared 1 4 DIV A 15 8 lt A B B 7 0 Philips Electronics N V 2005 Page 103 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions DJNZ lt byte gt
135. ro s aa F8H No relevant state informa No S1DAT action No S1CON action Wait or proceed current transfer tion available SI 0 Bus error during MST or No S1DAT action Only the internal hardware is affected in the MST selected Slave modes due or addressed SLV modes In all cases the bus is to an illegal START or released and SIO1 is switched to the not ad STOP condition State 00H dressed SLV mode STO is reset can also occur when interference causes SIO1 to enter an undefined state Table 14 Miscellaneous States 5 5 4 5 Miscellaneous States There are two S1STA codes that do not correspond to a defined SIO1 hardware state see Table 14 These are discussed below S1STA F8H This status code indicates that no relevant information is available because the serial interrupt flag SI is not yet set This occurs between other states and when 5101 is not involved in a serial transfer S1STA 00H This status code indicates that a bus error has occurred during an SIO1 serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowl edge bit A bus error may also be caused when external interference disturbs the internal SIO1 sig nals When a bus error occurs SI is set To recover from a bus error the STO flag must be set and SI must be cleared Th
136. ro 2 2 JNZ rel Jump if Accumulator is not zero 2 2 CJNE A direct rel Compare direct byte to and jump if not equal 3 2 CJNE A data rel Compare immediate to Acc and jump if not equal 3 2 CJNE RN data rel Compare immediate to register and jump if not equal 3 2 CJNE Ri data rel Compare immediate to indirect and jump if not equal 3 2 DJNZ Rn rel Decrement register and jump if not zero 2 2 DJNZ direct rel Decrement direct byte and jump if not zero 3 2 NOP No operation 1 1 Page 90 of 132 All mnemonics copyrighted Intel Corporation 1980 Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions 6 2 Instruction definitions ACALL addr11 Function Absolute Call Description ACALL unconditionally calls a subroutine located at the indicated address The instruction incre ments the PC twice to obtain the address of the following instruction then pushes the 16 bit result onto the stack low order byte first and increments the Stack Pointer twice The destination ad dress is obtained by successively concatenating the five high order bits of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2k block of the program memory as the first byte of the instruction following ACALL No flags are affected Example Initially SP equals 07H The label SUBRTN is at program memor
137. s Serial Peripheral Interface SPI Handshake Solutions SPSR SPDR SPR1 SPRO Baudrate 0 0 foi a i 1 0 1 foi a i 2 1 0 a 1 8 1 1 fspi_ck i 16 SPI status register addr F6H reset value OOH bits 7 6 5 4 3 2 1 0 ser woo o o o o o o bit Symbol Function SPSR 7 SPIF SPI data complete flag 1 SPIF is set upon completion of a data transfer If SPIF 21 and SFR bit SPIE SPCR 7 is set an SPI interrupt is generated While SPIF is 1 any write attempts to SPDR are inhibitted until SPDR is read 0 SPIF has to be cleared by software by reading SPSR first and accessing SPDR afterwards SPSR 6 WCOL Write collision flag 1 set by hardware when SPDR is written while a data transfer is in pro gress 0 cleared by hardware when first SPSR is read and then SPDR is ac cessed SPSR 5 reserved bits SPSR 4 write always 0 read 0 SPSR 3 SPSR 2 SPSR 1 SPSR 0 SPI data register addr F7H reset value 00H bits 7 6 5 4 3 2 1 0 SPDR bit Symbol Function SPDR 7 Data to transmit or received by the SPI interface SPDR O The data register SPDR is used to communicate transmit and receive data between the controller and the SPI Transmit data is provided by writing to this register and receive data can be read from this register Only a write to this register will initiate transmis sion reception of another byte and this will only occur in the master device At the com pletion of transmitting a
138. s needed for bit 7 and clears C otherwise If C was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is sub tracted from the Accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or immediate The Accumulator holds OC9H 11001001B register 2 holds 54H 01010100B and the carry flag is set The instruction SUBB A R2 will leave the value 74H 01110100B in the Accumulator with the carry flag and AC cleared but OV set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the carry borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction SUBB lt A C Rn 2 1 1 0 0 1 0 1 0 1 direct address SUBB lt A C direct SUBB
139. s of the transmitting device 7 bits and the data direction bit In this mode the data direction bit R W will be logic 1 and we say that an is transmit ted Thus the first byte transmitted is SLA R Serial data is received via SDA while SCL outputs the serial clock Serial data is received 8 bits ata time After each byte is received an acknowledge bit is transmitted START and STOP conditions are output to indicate the beginning and end of a serial transfer 3 Slave Receiver mode Serial data and the serial clock are received through SDA and SCL After each byte is received an acknowledge bit is transmitted START and STOP conditions are recognized as the beginning and end of a serial transfer Address recognition is performed by hardware after reception of the slave address and direction bit 4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver mode However in this mode the di rection bit will indicate that the transfer direction is reversed Serial data is transmitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application SIO1 may operate as a master and as a slave In the Slave mode the SIO1 hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontroller wishes to become the bus
140. set carry is cleared Bytes 1 Cycles 4 Encoding 1 1 1 0 Operation MUL A 7 0 lt A x B B 15 8 O Philips Electronics N V 2005 Page 117 of 132 HT80C51 User Manual Handshake Solutions 80C51 Family Instruction Set Instruction definitions NOP Function Description Example Bytes Cycles Encoding Operation No Operation Execution continues at the following instruction Other than the PC no registers or flags are af fected It is desired to produce a low going output pulse on bit 7 of Port 2 lasting exactly 5 cycles A sim ple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be in serted This may be done assuming are enabled with the instruction sequence CLR P2 7 NOP NOP NOP NOP n ETB P2 7 r 0 0 0 0 0 0 NOP PC lt PC 1 ORL lt dest byte gt lt src byte gt Function Description Example ORL A Rn Bytes Cycles Encoding Operation Logical OR for byte variables ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected The two operands allow six addressing mode combinations When the destination is the Accumu lator the source can use register direct register indirect or immediate addressing when the des tination is a direct address the source can be the Accumulator or immediat
141. sitive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immedi ate The Accumulator holds 11000011B and register 0 holds OAAH 10101010B The instruc tion ADD A RO will leave 6DH 01101101B in the Accumulator with the AC flag cleared and both the Carry flag and OV set to 1 ADD A lt A Rn direct address ADD A lt A direct ADD lt A Ri immediate data ADD lt data Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions ADDC A lt src byte gt Function Description Example ADDC A Rn Bytes Cycles Encoding Operation ADDC A direct Bytes Cycles Encoding Operation ADDC A Ri Bytes Cycles Encoding Operation ADDC A data Bytes Cycles Encoding Operation Philips Electronics N V 2005 Add with Carry ADDC simultaneously adds the byte variable indicated the carry flag and the Accumulator con tents leaving the result in the Accumulator The carry and auxiliary carry flags are set respec tively if there is a carry out from bit 7 or bit 3 and cleared otherwise When adding unsigned inte gers the carry flag indicates an overflow occurred
142. st byte of the instruction following AJMP The label JMPADR is at program memory location 0123H The instruction AJMP JMPADR is at location 0345H and will load the PC with 0123H 2 2 ai0 a9 a8 0 O 1 ad a2 al lt 2 PC10 0 lt page address ANL lt dest byte gt lt src byte gt Function Description Example Page 94 of 132 Logical AND for byte variables ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected The two operands allow six addressing mode combinations When the destination is the Accumu lator the source can use register direct register indirect or immediate addressing when the des tination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins If the Accumulator holds 11000011B and register 0 holds 55H 01010101B then the in struction ANL A RO will leave 41H 01000001B in the Accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be a constant
143. storing the results in the destination No flags are affected The two operands allow six addressing mode combinations When the destination is the Accumu lator the source can use register direct register indirect or immediate addressing when the des tination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins If the Accumulator holds 11000011B and register 0 holds OAAH 10101010B then the instruction XRL A RO will leave the Accumulator holding the value 69H 01101001B When the destination is a directly addressed byte this instruction can complement combinations of bits in any RAM location or hardware register The pattern of bits to be complemented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the Accumulator at run time The instruction P1 400110001B will complement bits 5 4 and 0 of output Port 1 Page 128 of 132 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions XRL A Rn Bytes 1 Cycles 1 Encoding Operation XRL A lt A Rn XRL A direct Bytes 2 Cycles 1 Encoding 0 1 1 0 0 1 0 1 direct address Op
144. struction using RO or R1 An external 256 byte RAM using multiplexed address data lines is connected to the 8051 Regis ters 0 and 1 contain 12H and 34H Location 34H of the external RAM holds the value 56H The instruction sequence MOVX A QR1 MOVX RO A copies the value 56H into both the Accumulator and external RAM location 12H MOVX lt Ri Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions MOVX A QDPTR Bytes Cycles Encoding Operation 1 2 1 1 1 0 0 0 0 0 MOVX lt DPTR MOVX QRi A Bytes 1 Cycles 2 Encoding 4 4 4 1 0 0 14 i Operation MOVX Ri lt A MOVX DPTR A Bytes 1 Cycles 2 Encoding 4 4 4 4 8 0 o o Operation MOVX DPTR A MUL AB Function Multiply Description MUL AB multiplies the unsigned eight bit integers in the Accumulator and register B The low order byte of the sixteen bit product is left in the Accumulator and the high order byte in B If the product is greater than 255 OFFH the overflow flag is set otherwise it is cleared The carry flag is always cleared Example Originally the Accumulator holds the value 80 50H Register B holds the value 160 0AOH The instruction MUL AB will give the product 12 800 3200H so B is changed to 32H 00110010B and the Accumulator is cleared The overflow flag is
145. ta bit goes into RB8 in Special Func tion Register SCON while the stop bit is ignored In mode 2 the baud rate is programmable to either 1 32 or 1 64 of the clock input sio cik mode the baud rate is derived from the overflow rate of timer 1 Figure 13 shows a simplified functional diagram of the serial port in modes 2 and 3 The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SBUF as a destination register Transmission actually commences immediately after the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal After sending the start bit and 9 data bits the bit is set and the stop bit is sent Reception is initiated by the detection of a 1 0 0 transition at sio rxd i For this purpose sio rxd i is sampled at a rate of 16 times whatever baud rate has been established When a transi tion is detected the divide by 16 counter is immediately reset thus it aligns its rollovers with the boundaries of the incoming bit times At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of sio rxd i The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 t
146. tatus codes in S1STA are possible These are 40H 48H or 38H for the Master mode and also 68H 78H or BOH if the Slave mode was enabled logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 11 ENS1 CR1 and CRO are not affected by the serial transfer and are not referred to in Table 5 After a repeated start condition state 10H SIO1 may switch to the Master Transmitter mode by loading S1DAT with SLA W Slave Receiver mode In the Slave Receiver mode a number of data bytes are received from a master transmitter see Figure 23 To initiate the Slave Receiver mode S1ADR and S1CON must be loaded as follows 7 6 5 4 3 2 1 0 S1ADR DBH The upper 7 bits are the address to which SIO1 will respond when addressed by a master If the LSB GC is set SIO1 will respond to the general call address 00H otherwise it ignores the general call address 7 6 5 4 3 2 1 0 S1CON X 1 0 0 0 1 X X CRO CR1 and CR2 do not affect SIO1 in the Slave mode ENS must be set to logic 1 to enable 5101 The AA bit must be set to enable SIO1 to acknowledge its own slave address or the general call ad dress STA STO and SI must be reset When S1ADR and SiCON have been initialized 5101 waits until it is addressed by its own slave ad dress followed by the data direction bit which must be 0 W for SIO1 to operate in the Slave Re ceiver mode After its own slave address and the W bit hav
147. ted Only the three least significant bits in register DCON have a meaning The conversions take so little time that no additional synchronization mechanism interrupt or ready bit in status information is needed Instead the handshaking mechanism is used to obtain the required synchronization between the micro controller and the DES converter As long as the unit is busy in conversion it does not accept any accesses to one of its SFRs Therefore after having given a conver sion command the micro controller can immediately start reading the resulting text If in the case of a triple DES conversion the result is not yet available the first read access is held up in a handshake until the conversion is completed no busy waiting Philips Electronics N V 2005 Page 83 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Triple DES Converter 5 8 5 Software view For an encryption or decryption using the Triple DES module the following steps are neccesary e Store the key in the key register or both keys for triple DES e write the text into the DES module e start the encryption or decryption e the encrypted or decrypted text These steps are described in further detail below 5 8 5 1 Storing a key into auxiliary register KEY The key B1B2B3B4B5B6B7B8 can be stored in key register KEY0 or KEY1 by writing the sequence B8 B7 B6 B5 B4 B3 B2 B1 to SFR DKEY Then the contents of DKEY can be copied into KEY0 by
148. ter Used to shift in a 56bit key which can be DKEY 6 stored in either key register KEY0 or KEY1 DKEY 5 DKEY 4 DKEY 3 DKEY 2 DKEY 1 DKEY O Ignored DTXT DES data register addr C2H reset value XX bits 7 6 5 4 3 2 1 0 DTXT bit symbol Function DTXT 7 8bit slice of a complete 64bit data block for encryption or decryption A s write access shifts in 8bits a read access shifts out 8bits DTXT O 5 8 3 Interrupts No interrupts generated 5 8 4 Operation Write accesses to all three registers are supported However only read accesses from DTXT are sup ported read accesses from the other registers have no effect Each supported access on the 8 bit slice of either the key or the text register is followed by a permutation of the corresponding register Writing the 64 bit text register takes 8 write accesses to DTXT Reading the text register takes 8 read accesses from DTXT after which the contents of the text register are back in the original state Writing the 56 bit key register takes also 8 write accesses to DKEY In these accesses the least significant bit of each byte is discarded To support triple DES the converter has two internal key registers KEY0 and KEY1 After a key has been shifted in its value has to be stored in KEY0 or KEY1 before it can be used A single DES conver sion uses KEY0 and a triple DES conversion uses first KEY0 then KEY1 and finally KEY0 again After a command has been written into DCON it will be execu
149. terrupt will cause PCON 0 to be cleared by hardware terminating the idle mode The interrupt will be serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal op eration or during an Idle For example an instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The other way of terminating the idle mode is with a hardware reset which starts the processor in the same manner as a power on reset 2 5 6 2 Power Down Mode An instruction that sets PCON 1 immediately switches into the Power Down mode In the Power Down mode the CPU clock and all peripheral clocks can be stopped completely to lower the power con sumption This has to be done be external circuits which observe the output pin cpu powerdown o that indicates the power down mode With the clocks frozen all functions are stopped the contents of the on chip RAM and Special Function Registers are maintained The port pins output the values held by their respective SFRs The only exit from Power Down is a hardware reset Reset redefines all the SFRs but does not change the on chip RAM Page 16 of 132 Philips Electronics N V 2005 HT80C51 User Manual Memory Organization MOVC protection option
150. th the second and third instruction bytes The destina tion may therefore be anywhere in the full 64k program memory address space No flags are af fected Example The label JMPADR is assigned to the instruction at program memory location 1234H The in struction LJMP JMPADR at location 0123H will load the program counter with 1234H Bytes 3 Cycles 2 Encoding 0 0 0 0 0 1 0 addr15 addr8 addr7 addrO Operation LJMP lt addr15 0 MOV lt dest byte gt lt src byte gt Function Move byte variable Description The byte variable indicated by the second operand is copied into the location specified by the first operand The source byte is not affected No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination address ing modes are allowed Example Internal RAM location 30H holds 40H The value of RAM location 40H is 10H The data present at input port 1 is 11001010B OCAH The instruction sequence OV RO 30H RO lt 30H OV A RO A lt 40H OV R1 A RL lt 40H OV R1 B lt 10H OV R1 P1 RAM 40H lt OCAH OV P2 P1 P2 0CAH leaves the value 30H in register 0 40H in both the Accumulator and register 1 10H in register B and OCAH 11001010B both in RAM location 40H and output on port 2 MOV A Rn Bytes 1 Cycles 1 Encoding 1 1 1 1 r r r Ope
151. the first bit received from the I2C bus after a start condition A logic 1 in STADR corresponds to a high level on the I2C bus and a logic 0 corresponds to a low level on the bus The Data Register STDAT S1DAT contains a byte of serial data to be transmitted or a byte which has just been received The CPU can read from and write to this 8 bit directly addressable SFR while it is not in the process of shifting a byte This occurs when SIO1 is in a defined state and the serial interrupt flag is set Data in S1DAT remains stable as long as SI is set Data in S1DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of S1DAT While data is being shifted out data on the bus is simultaneously being shifted in SiDAT always contains the last data byte present on the bus Thus in the event of lost arbi tration the transition from master transmitter to slave receiver is made with the correct data in S1DAT 7 6 5 4 3 2 1 0 S1DAT DAH lt shift direction SD7 SDO Eight bits to be transmitted or just received A logic 1 in S1DAT corresponds to a high level on the I2C bus and a logic 0 corresponds to a low level on the bus Serial data shifts through S1DAT from right to left Figure 19 shows how data in S1DAT is serially transferred to and from the SDA line S1DAT and the ACK flag form a 9 bit shift register which shi
152. time the bit detector samples the value of s3o i The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 Philips Electronics N V 2005 Page 37 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Standard Serial Interface SIOO the receive circuits are reset and the unit goes back to looking for another 1 to O transition This is to provide rejection of false start bits After the 8 data bits and the stop bit have been received the result is loaded into SBUF and RB8 and RI is set to 1 but that is only done if the following conditions are met 1 RI 0 and 2 Either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated Then the unit goes back to looking for a 1 to 0 transition in s3o rxd i 5 3 4 6 More About Modes 2 and 3 These modes are very similar to mode 1 with the main difference that here 9 data bits are used in stead of 8 data bits in mode 0 11 bits are transmitted through sio txd o or received through sio rxd i start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 On receive the 9th da
153. tion will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if STADR O logic 1 START condition will be transmitted when the bus be comes free Slave Receiver mode O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12 Interface S101 Handshake Solutions application software response status of the I2C bus code to S1CON next action taken by SIO1 hardware and SIO1 hardware to from S1DAT sralsrol s nn Own SLA R has been Last data byte will be transmitted received ACK has been ACK bit will be received returned Data byte will transmitted ACK bit will be received Arbitration lost in SLA R W Load data byte or Last data byte will be transmitted as master Own SLA R ACK bit will be received has has been received load data byte Data byte will transmitted has been returned bit will be received Data byte in STDAT has Load data byte or Last data byte will be transmitted been transmitted ACK has bit will be received been returned load data byte Data byte will transmitted bit will be received Data byte in STDAT has No S1DAT action or Switched to not addressed SLV mode no recog been transmitted NOT nition of own SLA or General call address has been returned no S1DAT action or Switched to not addressed SLV mode Own SLA will be recognized General
154. to access the protected region will return the value 00H instead of the real memory content The pro tection is only one way so a protected program can read the complete program memory area The protected region is defined to start at address 0000H The upper limit of the protected region is defined by static inputs ht80c51 movcp uaddr i so the protected code memory region is from 0000H addr ht80c51 movcp uaddr i The value of this upper limit is under control of the customer but must not change during execution Usually it is hard wired to a constant value O Philips Electronics N V 2005 Page 17 of 132 Handshake Solutions HT80C51 User Manual Reset 3 Reset The reset input is the Z_R pin An asynchronous reset is accomplished by holding the Z_R pin low The minimum low time is not depending on the clock frequency but it depends on the standard cell library placement and routing However usually a reset pulse of about 100ns is sufficient A reset initializes most of the SFRs The following table lists the SFR reset values The internal RAM is not affected by reset On power up the RAM content is not defined Page 18 of 132 register reset value PC 0000H ACC 00H B 00H PSW 00H SP 07H DPTR 0000H PCON 0xx0 000 IENO 00H IEN1 00H IPO 00H IP1 00H TMOD 00H TCON 00H THO 00H TLO 00H TH1 00H TL1 00H SCON 00H SBUF XX POUTO FFH POUT1 FFH POUT2 FFH POUT3 FFH S1CON 00H S1STA F8H S1DAT 00H S1ADR 00H
155. to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated 5 1 3 4 Response Time 01 intO n i and t01 inti n i levels are inverted and latched into IE0 and IE1 The values are not actually polled by the circuitry until the next start of an instruction If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine Page 24 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules Interrupt Controller Handshake Solutions A longer response time would result if the request were blocked by one of the 2 previously listed con ditions If an interrupt of equal or higher priority level is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more the 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or an access to IE or IP the additional wait time cannot be more than 5 cycles a maximum of one more cycl
156. ts to transmit a block of data to one of several slaves it first sends out an address byte that identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the coming data bytes SM2 has no effect in Mode 0 and in Mode 1 it can be used to check the validity of the stop bit In a Mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is re ceived Philips Electronics 2005 Page 39 of 132 HT80C51 User Manual Handshake Solutions Peripheral Modules Standard Serial Interface SIOO 5 3 5 Setting up the serial port Table 8 summarizes the initialization values for SCON to select different modes of the UART SIO mode SM2 0 SM2 1 SMOD 0 SMOD 1 single processor multi processor environment environment shift register ck i fsio ck i 8bit UART fto1_overtiow 32 fto 16 9bit UART fso 64 ax 1 32 9bit UART ftot overtiow 32 fto1 overttow 16 Table 8 Serial Port Setup 5
157. uction sequence INC RO INC RO INC RO will leave register O set to 7FH and internal RAM locations 7EH and 7FH holding respectively 00H and 41H INC lt A 1 Rn lt Rn 1 direct address INC direct lt direct 1 INC Ri lt Ri 1 Philips Electronics N V 2005 Page 105 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions INC DPTR Function Description Example Bytes Cycles Encoding Operation JB bit rel Function Description Example Bytes Cycles Encoding Operation Increment Data Pointer Increment the 16 bit data pointer by 1 A 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFFH to 00H will increment the high order byte DPH No flags are affected This is the only 16 bit register which can be incremented Registers DPH and DPL contain 12H and OFEH respectively The instruction sequence INC DPTR INC DPTR INC DPTR will change DPH and DPL to 13H and 01H 1 2 1 0 1 INC DPTR lt DPTR 1 Jump if Bit set If the indicated bit is a one jump to the address indicated otherwise proceed with the next instruc tion The branch destination is computed by adding the signed relative displacement in t
158. ues at the resulting ad dress which is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt has been pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed Example The Stack Pointer originally contains the value OBH An interrupt was detected during the instruc tion ending at location 0122H Internal RAM locations OAH and OBH contain the values 23H and 01H respectively The instruction RETI will leave the Stack Pointer equal to 09H and return program execution to location 0123H Bytes 1 Cycles 2 Encoding O 0 1 1 0 0 1 0 Operation RETI PC15 8 lt SP SP lt SP 1 PC7 0 lt SP SP SP 1 Page 122 of 132 O Philips Electronics N V 2005 HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions Handshake Solutions RLA Function Description Example Bytes Cycles Encoding Operation RLCA Function Description Example Bytes Cycles Encoding Operation O Philips Electronics N V 2005 Rotate Accumulator Left The eight bits in the Accumulator are rotated one bit to the left Bit 7 is rotated into the bit O posi tion No flags are affected The Accumulator holds the value OC5H 11000101B The instruction RL A leaves the Accumulator holding the value 8BH 10001011B with the carry u
159. ut wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected All of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60H or 66H to the Accumulator depending on initial Accumula tor and PSW conditions Note DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation nor does DA A apply to decimal subtraction The Accumulator holds the value 56H 01010110B representing the packed BCD digits of the decimal number 56 Register 3 contains the value 67H 01100111B representing the packed BCD digits of the decimal number 67 The carry flag is set The instruction sequence ADDC A R3 DA A will first perform a standard two s complement binary addition resulting in the value OBEH 10111110B in the Accumulator The carry and auxiliary carry flags will be cleared The Decimal Adjust instruction will then alter the Accumulator to the value 24H 00100100B indi cating the packed BCD digits of the decimal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 BCD variables can be incremented or decremented by adding 01H or 99H If the Accumulator ini
160. vec tored to as shown in column vector address in Table 2 Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note that a simple RET instruction would also have returned execution to the inter rupted program but it would have left the interrupt control system thinking an interrupt was still in pro gress making future interrupts impossible 5 1 3 3 External Interrupts The external sources can be programmed to be level activated or transition activated by setting or clearing bit IT1 or ITO in Register TCON If ITx 0 external interrupt x is triggered by a detected low at the t01 intx n i If ITx 1 external interrupt x is edge triggered In this mode if the interrupt input t01 intO n iforliTO0 tO1 inti n for IT1 shows a high to low transition interrupt request flag IEx in TCON is set Flag bit IEx then requests the interrupt Since the external interrupt pins are not sampled there is no minimum low duration specified IEx will be automatically cleared by the CPU when the service routine is called If the external interrupt is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has
161. will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be received NOT ACK bit will be returned Data byte will be received bit will be returned Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Table 11 Master Receiver Mode not available for slave only version Page 66 of 132 O Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12 Interface S101 Handshake Solutions status of the I2C bus and SIO1 hardware Own SLA W has been received ACK has been returned Arbitration lost in SLA R W as master Own SLA W has has been received ACK has been returned General call address 00H has been received ACK has been returned Arbitration lost in SLA R W as master General call address 00H has been received ACK has been returned Previously addressed with own SLV address DATA has been received ACK has been returned Previously addressed with own SLA DATA has been received NOT ACK has been returned Previously addressed with General Call DATA has been received ACK has been returned Previously addressed with General Call DATA has been received NOT ACK has been returned O Philips Electronics N V 2005 to from S1DAT No S1DAT action or no S1DA
162. with the slave address and the data direction bit SLA W The SI bit in STCON must then be reset before the serial transfer can continue When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in S1STA are possible There are 18H 20H or 38H for the Master mode and also 68H 78H or BOH if the Slave mode was enabled logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 10 After a repeated start condition state 10H SIO1 may switch to the Master Re ceiver mode by loading S1DAT with SLA R Page 58 of 132 Philips Electronics N V 2005 HT80C51 User Manual Peripheral Modules 12C Interface 5101 Handshake Solutions Master Receiver mode not available for slave only version In the Master Receiver mode a number of data bytes are received from a slave transmitter see Figure 22 The transfer is initialized as in the Master Transmitter mode When the start condition has been transmitted the interrupt service routine must load S1DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in S1CON must then be cleared before the serial transfer can con tinue When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of s
163. y location 0345 H After execut ing the instruction ACALL SUBRTN at location 0123H SP will contain O9H internal RAM locations 08H and 09H will contain 25H and 01H respectively and the PC will contain 0345H Bytes 2 Cycles 2 Encoding a10 a9 a8 1 0 1 a5 a2 al Operation ACALL lt PC 2 SP lt SP 1 SP lt PC7 0 SP lt SP 1 SP lt PC15 8 PC10 0 lt page address Philips Electronics N V 2005 Page 91 of 132 Handshake Solutions HT80C51 User Manual 80C51 Family Instruction Set Instruction definitions ADD A lt src byte gt Function Description Example ADD A Rn Bytes Cycles Encoding Operation ADD A direct Bytes Cycles Encoding Operation ADD A Ri Bytes Cycles Encoding Operation ADD A data Bytes Cycles Encoding Operation Page 92 of 132 Add ADD adds the byte variable indicated to the Accumulator leaving the result in the Accumulator The carry and auxiliary carry flags are set respectively if there is a carry out from bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow oc curred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 oth erwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two po

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