Serial Communications
Contents
1. exceed table Wireless e Order Increasing complexity power and bandwidth SimpliciTl lt 200 kbS Zigbee IEEE 802 15 4 250 kbS Bluetooth IEEE 802 15 1 1 MbS 24 MbS WiFi IEEE 802 11 b 11 MbS g 54 MbS n 150 MbS e Data rates needed Voice 4 kbS Music 700 kbS Video 3 5 MbS Standard 40 MbS Blu ray References MSP430x4xx Family User s Guide http focus ti com lit ug slau056j slau056j pdf MSP430FG4618 F2013 Experimenter s Board User s Guide http focus ti com lit ug slau213a slau213a pdf Serial Comm image http www ee nmt edu rison ee308 spr99 supp 990406 sync serial gif RS 232 byte image http www eeherald com images rs232 3 jpg RS 232 Connector Image http www bisque com tom bluetooth Images db9 jpg SPI http en wikipedia org wiki Serial Peripheral Interface Bus I2C http en wikipedia org wiki I C2 B2C I2C http www best microcontroller projects com i2c tutorial html I2C http www eetimes com design analog design 4010395 SIGNAL CHAIN BASICS Part 32 Digital interfaces con t The l2C Bus2. s manual has formulas for these UCAOMCTL 0x06 Modulation UCAOCTL1 amp UCSWRST Initialize USCI state machine IE2 UCAORXIE Enable USCI_AO RX interrupt _BIS SR LPMO bits GIE Enter LPMO interrupts enabled Echo back RXed character confirm TX buffer is ready first pragma vector USCIABORX_ VECTOR _interrupt void USCIAORX_ISR void while IFG2 amp UCAOTXIFG Make sure last character went out UCAOTXBUF UCAORXBUF TX gt RXed character SPI Serial Peripheral Interface Motorola SPI MOSI hmat Master MISO cc e Two types of devices masters and slaves e We ll consider only one master but multiple slaves e Signals SCLK Serial CLocK set by Master MOSI Master Out Slave In MISO Master In Slave Out SS Slave Select e Each slave gets its own slave select other lines are shared e Pulling line low selects slave SPI and the clock intro Pull slave select line low to select device e First bit of data gets put on MISO and MOSI so a byte goes both ways e Data gets shifted out typically 8 bits but not necessarily The data gets put on bus on falling edge of clock The data gets read on the rising edge of clock Cycle TEO MISO 2 ODIETIIDEDODERE Z MOSI 2 COD DEE Z SPI and the clock the hard truth Unfortunately clock can be set many ways as determined by clock polarity and phase e CPOL 0 Base value of
3. up from LPMx modes UCSSELY e Slave operation in LPM4 Bit Clock Generator UCxBRx UCICLK ACLK i SMCLK SMCLK MSP430xG461x Demo USCI_BO I2C Master Interface to DAC8571 Write Description Using UCBOTXIE a continuous sine wave is output to external DAC using a 16 point look up table Only one start is executed Data is handled by the ISR and the CPU is in LPMO MCLK SMCLK TACLK BRCLK 1MHz DAC8571 I2C address Ox4C AO GND MSP 430xG461x I2C Code DAC8571 P3 1 UCBOSDA lt P3 2 UCBOSCL XOUT I2C MASTER 32kHz GND AO void main void WDTCTL WDTPW WDTHOLD Stop Watchdog Timer P3SEL 0x06 Assign I2C pins to USCI_BO UCBOCTL1 UCSWRST Enable SW reset UCBOCTLO UCMST UCMODE 3 UCSYNC I2C Master synchronous mode UCBOCTL1 UCSSEL_2 UCSWRST Use SMCLK keep SW reset UCBOBRO 11 SCL SMCLK 11 95 3kHz UCBOBR1 0 UCBOI2CSA 0x4c Set slave address UCBOCTL1 amp UCSWRST Clear SW reset resume operation IE2 UCBOTXIE Enable TX ready interrupt UCBOCTL1 UCTR UCTXSTT I2C TX start condition UCBOTXBUF 0x010 Write DAC control byte __bis_ SR_register CPUOFF GIE Enter LPMO w interrupts USCI_BO Data ISR pragma vector USCIABOTX_VECTOR _ interrupt void USCIABOTX_ISR void static unsigned char ByteCtr UCBOTXBUF Sine_Tab ByteCtr ByteCtr amp 0Ox1f Transmit data byte Do not
4. CXTAIFG Contral _ Transmit State Machine SPI Code XIN 32kHz XOUT CS lt P3 0 DATAOUT gt P3 2 UCBOSOMI include msp430xG46x h I O CLK lt P3 3 UCBO0OCLK P5 1 gt LED void main void volatile unsigned int i char data P5DIR 0x02 P5 1 output P3SEL 0x0C P3 3 2 option select P3DIR 0x01 P3 0 output direction UCBOCTLO UCMST UCSYNC UCMSB 8 bit SPI mstr MSb 1st CPOL 0 CPHS 0 UCBOCTL1 UCSSEL 2 SMCLK UCBOBRO 0x02 Set Frequency UCBOBR1 0 UCBOCTL1 amp UCSWRST Initialize USCI state machine while 1 P30UT amp 0x01 Enable TLC549 A D CS SS reset UCBOTXBUF 0x00 Dummy write to start SPI while IFG2 amp UCBORXIFG USCI_BO RX buffer ready data UCBORXBUF data OO DATA P30UT 0x01 Disable TLC549 CS SS set if data gt Ox7F P5OUT 0x02 data AIN gt 0 5 REF REF LED On else P50UT amp 0x02 LED off I2C or I C Inter Integrated Circuit Philips As with SPI a master Slave system Also called a 2 wire bus It Has only clock and data with Suluo resistors Rp in diagram Lines can be pulled low by any device and are high when all devices release them There are no slave select lines instead the devices have addresses that are sent as part of the transmission protocol Four max speeds 100 kbS standard 400 kbS fast 1 Mbs fast
5. Serial Communications Chapter 10 Communications e The simplest is parallel Multiple 8 One Way typically data e There may be mechanism for peripheral to get attention of uC Peripheral uC i e interrupt or poll Two way i lines uC atch Peripheral Zi UD n E e This is resource expensive pins real estate in terms of hardware but easy to implement Serial Communications e Many fewer lines are required to transmit data This is requires fewer pins but adds complexity OxD6 11010110 Peripheral CS e Synchronous communications requires clock Whoever controls the clock controls communication speed e Asynchronous has no clock but speed must be agreed upon beforehand baud rate Asynchronous Serial RS 232 Commonly used for one to one communication e There are many variants the simplest uses just two lines TX transmit and RX receive e Transmission process 9600 baud 1 bit 1 9600 0 104 mS Transmit idles high when no communication It goes low for 1 bit 0 104 mS It sends out data LSB first 7 or 8 bits There may be a parity bit even or odd error detection There may be a stop bit or two Data packet for ASCII A 3 LSB i SE Paa aa a Oo 1 0 0O 0 O0 0O 0 1 QO 1 a Start bit oT Two stop bits e From processor side OV logic O e Ina serial cable 12 5 3V logic O RS232 Voltage levels Data
6. a odd even or non parity e Independent transmit and receive eLSB first or MSB first data Receiver start edge detection for auto wake up from LPMx modes eIndependent interrupt capability for receive and transmit e Status flags for error detection and Suppression eBuilt in idle line and address bit communication protocols for multiprocessor systems e Status flags for address detection ACLK USCI_Ax Block Diagram VART Mode UCSYNC 0 Set UCORZIFG Set UCADDRAUCIDLE UCIRAXPL UCIRAXFLx UCIRAXFE UCIREN E UCLISTEN al IDA Decoder a i 0 A UCORX o lt gt 0 g UCPEN UCPAR UCMSB UCTBIT UCABEN Recenve Baudrate Generator UCOBRx Tranamit Glock A 3 UCBRFx UCBRSx UCOS 6 UCPEN UCPAR UCMSB UC7BIT UCIREN gol 1 UCOTX Transmit Butter UC OTXBUF ii UCIRTXPLx T a Set UCOTXIFG UCTXBRK UCTXADDOR UCMODEx UCSPB Echo a received character RX ISR used Normal mode is LPM3 USCI_AO RX interrupt triggers TX Echo UA RT c ACLK BRCLK LFXT1 32768 MCLK SMCLK DCO 1048k CO e Baud divider 32768hz XTAL 9600 32768 9600 3 41 0003h 03h MSP430xG461x XIN 32kHz RST XOUT P4 7 UCAORXD include msp430xG46x h 9600 8N1 P4 6 UCAOTXD lt void main void volatile unsigned int 1 PASEL 0x0CO P4 7 6 USCI_AO RXD TXD UCAOCTL1 UCSSEL 1 CLK ACLK UCAOBRO 0x03 32k 9600 3 41 UCAOBR1 0x00 User
7. packet for ASCI A LSB Start bit e On Experimenter s board MSB ata 0 1 0 1 1 oT Two stop bits e Physical connector Data Sat Ready amp Request to Senc f Clear to Send 8 Ring Indicator 3 mn E Ww fh Ee Data Carrer Detect Raceive Data Hx Latal Transmit Data Tx Date Data Terminal Ready Signal Ground 3 3V logic 1 3 5 12V logic 1 Data packet for ASCI A LSB MEB f data bits f Start bit Parity bit Isolated RS232 Communication 1k VCC o R5 100 8 Yr AN y i J J o MMBT5088_3 5 R9 r PS8802 PC_GND 2k2 RS232 Handshaking e Some RS232 connections using handshaking lines between DCE Data Communications Equipment and DTE Data Terminal Equipment RTS Ready To Send e Sent by the DTE to signal the DCE it is Ready To Send CTS Clear To Send e Sent by the DCE to signal the DTE that it is Ready to Receive DTR Data Terminal Ready e Sent to DTE to signal the DCE that it is ready to connect DSR Data Set Read e Sent to DC to signal the DTE that it is ready to connect e In practice if these handshaking lines are used it can be difficult to set up the serial communications but it is quite robust once working e There is also software handshaking XON XOFF DTE and DCE have different connector pinouts MSP430 USCI in UART mode also USART peripheral UART mode features include Figure 19 1 e 7 or 8 bit dat
8. plus and 3 4 Mbs high speed a E E a All allow SDA SCL start high Master SDA low to signal start Master Send out SCL and 7 bit address followed by 0 W on SDA Slave Pull SDA low to signify ACKnowledge Master Send out 8 data bits on SDA Slave Ack All allow SDA to go high when SCL is high stop For Read 3 Master Address following by 1 R on SDA 5 Slave Send out 8 data bits on SDA 6 Master Ack Other Features e You can transfer multiple bytes in a row S Slave Address WA DATA A DATA AP A Acknowledge I From Master to Slave Master Transmitter writing to Slave Receiver A Not Acknowledge S Start From Slave to Master P Stop S Slave Address RA DATA A DATA A R Read W Write Master Receiver Reading from Slave Transmitter e At end of transfer slave can hold SCL low to slow transfer down called clock stretching H i x iE SDA A A AM AX AB RK A Rw T X os X pe Rds X de T Ko X AKA e Any device that malfunctions can disable bus I2C and SCI _ The 12C features include gt Receo St Regi e Compliance to Philips 12C specificatior Receive Buffer UC 1RXBUF e Slave receiver transmitter mode e Standard mode up to 100 kbps and fast mode up to 400 kbps support e Programmable UCXCLK frequency in iiaa master mode gt Transmit shift Register gt Designed for low power a ST e Slave receiver START detection for UCSLAI0 SON auto wake
9. the clock is O CPHA 0 Data read on rising edge put on bus on falling edge of SCLK i e clock is low Case from previous slide CPHA 1 Data read on falling edge put on bus on rising edge i e clock is high e CPOL 1 Base value of the clock is 1 CPHA 0 Data read on falling edge put on bus on rising edge i e clock is high CPHA 1 Data read on rising edge put on bus on falling edge i e clock is low CPOL 0 LOLOL Ln SCK CPOL 1 MLA AAA Cycle CPHA 0 MISO MOSI Cycle GEIS CPHA 1 Mso MOSI 2X2 SYST YE SPI and SCI SPI mode features include e 7 or 8 bit data length e LSB first or MSB first data e Master or slave modes e Selectable clock polarity and phase control e Programmable clock frequency in master mode e Independent transmit and receive e Continuous transmit and receive e Independent interrupt capability for receive and transmit e Slave operation in LPM4 Figure 20 1 USCI Block Diagram SPI Mode WA ACLK SMCLK SMCLK Set UCOE Set UCXxAXIFG _ Receive State Machine UCLISTEN UCMST Receive Buffer UC xAXBUF UCxSOMI gt Receive Shift Register UCMSB UC BIT UCSSELx Bit Clock Generator UCxBRx 16 UCCKPH UCCKPL ee Clock Direction Prescaler Divider Phase and Polarity C 3 UCMSB UC7BIT UcxSIMO gt Transmit Shift Register ___ UCMODE x 2 UCxSTE Transmit Bufer UC xTXBUF gt Transmit Enable L gt Set UCFE Set U
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