BERTScope Clock Recovery Instruments
Contents
1. lock status bit rate peaking and roll off The system is designed to make sure that you are always aware of the test conditions always aware of the factors in play that will affect your measure ment results Graphing capability allows the user to plot the loop response and the inverse response curves with 20 dB and 40 dB plot lines and 3 dB point Cursors are available for marking X Y axis on each graph Future firmware upgrade For engineers wanting to utilize test equip ment already available on their lab bench the BERTScope CR and CR HS are controllable via the front panel for stand alone operation In keeping with the BERTScope family s philoso phy of being the easiest to use signal integrity tools available the clock recovery instruments provide the information you most need imme diately available Duty Cycle Distortion BERTScopeCR and BERTScopeCR HS are the only clock recovery instruments that can measure the rising edge timing deviations versus the falling edge timing deviations to determine the duty cycle distortion of a signal under test This output parameter is available via front paneland BERTScope user interface Clock Out and Sub rate Clock Out Both clock recovery instruments offer full rate clock out to 12 5 Gb s and sub rate clock out at all the popular divide ratios see listing on page 6 BERTScope Clock Recovery Instruments For easy verification of compliance the cor rect characteri2. ERTScope CR and CR HS are the first clock recovery instruments to recover clocks from spread spectrum clocked signals used in Serial ATA SAS PCI Express and FB DIMM applications BERTScope Clock Recovery Instruments An instrument front panel display gives critical information on the measurement being made and settings can also be managed through the knob and 4 buttons located below the display along with a lock button and LED indicator This combination ensures that you are never lost always certain whether the measurement you are making includes the effects of clock recovery User Interface The instruments can be used with the BERT Scope S Stress Analyzer AND in stand alone operation Inexperienced users and experts alike will respond to the same ease and accu racy already available in the BERTScope S Signal Integrity Analyzer Perfect companions to the BERTScope the clock recovery instru ments smoothly integrate with the analyzer seamlessly sharing a common user interface A single USB connection and supplied high quality microwave coax cables connect the two units together that s all that is required to start measurements The BERTScope automati cally senses the presence of the Clock Recovery instrument and control is achieved through the Clock Recovery setup screen It s that sim ple Additional information is also immediately available on the front panel display showing parameters such as the PLL bandwidth
3. Oupsu BERTScope Clock Recovery Instruments Key Features Instrumentation quality clock recovery 150 Mb s 12 5 Gb s continuous data rate coverage Accurate variable loop bandwidth from 100 kHz to 12 MHz Auto lock capability with LED display Two hardware configurations standard data inputs and high sensitivity data inputs Programmable peaking adjustment with first and second order roll off capability Self measured and displayed PLL frequency response USB control connection to BERTScope or stand alone operation via front panel Single ended or differential 50 Q data inputs outputs DC coupled data through path Full and divided clock outputs with selectable divide ratios Measurement of clock phase error as a function of frequency and time Data measurement capability Edge Density Measurement determine the mark density of the signal under test Duty cycle distortion measure the rising edge timing deviations versus the falling edge timing deviations of the signal under test Ideal for spread spectrum clock SSC applications with large jitter excursions The vision of a scope the confidence of a BERT with clock recovery you can count on SYNTHE A RC SYS IN i BERTScope BERTScope Clock Recovery Instruments Compliant Clock Recovery Many communication standards now specify that jitter testing must be carried out using a reference clock that has b
4. een derived from the data signal Typical phase lock loop PLL char acteristics are specified in terms of the 3 dB bandwidth of the recovery loop the rate of roll off of the frequency response and the degree of response peaking allowable The BERTScope CR and BERTScope CR HS advanced architectures measure and display the PLL frequency response from 100 kHz to 12MHz the widest loop bandwidth available for jitter testing on the market today The first clock recovery instruments to allow full control of parameters including loop bandwidth peak ing damping and roll off Design and test engineers can now find and lock onto signals of undefined or unknown data rate The engineer can recover full rate clocks including spread spectrum clocks for signals at data rates from 150Mbps to 12 5 Gb s The engineer has full control of key parameters for variable loop bandwidth peaking damping and 1st and 2nd order roll offs optimizing jitter tracking GOLDENPLL Many test standards require the use of a Golden PLL phase lock loop Control of the BERT Scope CR and CR HS variable loop bandwidth allows for control of the jitter transferred to the recovered clock When the loop bandwidth setting is narrow much of the high frequency jitter is removed from the clock signal The narrowest LBW setting is desirable when an un jittered clock is required When the loop bandwidth setting is wide jitter is transferred to the recovered clock emulat
5. eference 1 1st order Loops bandwidths spec d with SAS single transition density of 1 100 or Gen2 ffrau 1667 pole 1010101 pattern Only standard we re aware of to specify this Assumption is that loop bandwidth will change proportionally as transi tion density reduces Instrument specifications Data input Data interfaces Data rate coverage Data insertion loss Data input voltage High sensitivity data input voltage Input sensitivity High sensitivity configuration Data output Phase error out Edge density Clock Clock interfaces Clock output range Loop bandwidth Frequency response roll off Intrinsic jitter Output frequency deviation tracking 30 to 33 kHz sawtooth modulated SSC Clock and sub rate clock output amplitude Divided clock output Divided Clock Interface Device info Communication Ordering Information BERTScope Clock Recovery Instruments 50 O differential or single ended DC coupled APC 3 5 user replace able Planar Crown adapters 150 Mb s to 12 5 Gb s D 1 2 dB typical 5 Vmin 5 Vmax 5 Vmin 5 Vmax 3 Vpeak peak 100 mV single ended typical 50 mV differential typical 40 mV single ended typical 20 mV differential typical 10 minimum 90 maximum 10 minimum 100 maximum 50 Q single ended AC Coupled APC 3 5 user replaceable Planar Crown adapter 150 MHz to 12 5 GHz full rate clock output 100 kHz 12 MHz variable 20 dB decade a
6. ing a clock signal similar to the CDR of the receiver under test Each standard provides an optimum LBW set ting for clock recovery often called the Golden PLL Recover Clocks for Optical Storage Enterprise and TelecomTesting The BERTScope CR and BERTScope CR HS have been designed from the ground up to provide users with flexibility and accuracy in compliance measurements The HS model uti lizes high sensitivity data inputs 40 mV single ended 20 mV differential with regenerated data outputs It is ideal for optical test appli cations like 4X 8X Fibre Channel and 10G Ethernet standards where the signal under test must be split off and converted from electrical to optical before fed into the clock recovery data input The BERTScope CRand CR HS recover a full rate clock up to 12 5 Gb s an important requirement for testing XFP and other 10 Gb s MSA modules The BERTScope CR HS config uration is also the model of choice in electrical applications where the additional data input sensitivity is critical to the test set up Recover Spread Spectrum Clocks for Testing to Electrical Serial Bus Standards Spread Spectrum Clocking SSC is an increas ingly required feature of serial bus standards When employed it can prove difficult to track but its effect must be included in test These instruments able to track SSC correctly with large jitter excursions up to 5000 ppm making it unique amongst clock recovery test solutions The B
7. nd 40 dB decade 250fsec RMS 500 5500 ppm 0 05 0 55 250 mV minimum 1 5 V maximum Full rate divided by 1 2 4 5 6 7 8 9 10 12 14 16 18 20 24 25 28 30 32 35 36 40 42 45 48 49 50 54 56 60 63 64 70 72 80 81 90 100 108 112 120 126 128 140 144 160 162 168 180 192 196 200 216 224 240 252 256 280 288 320 324 336 360 384 392 432 448 504 512 576 648 SMA Serial number revision codes available via front panel display USB cable supplied Unit also provides hub capability giving 3 additional USB ports Ordering number and prices on request The BERTScope CR and CR HS come standard with USB cable US power cord clock and data cables for use with BERTScope S SMA terminations for data outputs software on CD ROM and User s Manual for stand alone use O J DS U BERTScope Clock Recovery Instruments About BERTScopeTM pitw Elta LAP i re Th a BERTScopeTM is a registered trademark of SyntheSys Research Inc a privately held California corporation founded in 1989 with the mission to develop advanced test instruments for identifying and locating the source of errors in high speed digital bit streams BERTScope CR pairs with BERTScope to offer the vision of a scope the confidence of a BERT and clock recovery you can count on 2008 FINALIST More information is available at www bertscope com PT g SAS pe WL Sree e All statements technical i
8. nformation and recommendations related to the products herein are based upon infor mation believed to be reliable or accurate However the accuracy or completeness thereof is not guaranteed and no responsibility is assumed for any inaccuracies The user assumes all risks and liability whatsoever in connec tion with the use of a product or its applications JDSU reserves the right to change at any time without notice the design specifications function fit or form of its products described herein including withdrawal at any time of a product offered for sale herein JOSU makes no representations that the products herein are free from any intellectual property claims of others Please contact JDSU for more information JDSU and the JDSU logo are trademarks of JDS Uniphase Corporation Other trademarks are the property of their respective holders 2006 JDS Uniphase Corporation All rights reserved 30137432 500 0206 BERTSCOPE DS CPO TM AE Test amp Measurement Regional Sales NORTH AMERICA LATIN AMERICA ASIA PACIFIC EMEA WEBSITE www jdsu com TEL 1 866 228 3762 TEL 55 11 5503 3800 TEL 852 2892 0990 TEL 49 7121 86 2222 FAX 1 301 353 9216 FAX 55 11 5505 1598 FAX 852 2892 0770 FAX 49 7121 86 1222
9. proportional to the frequency deviation The phase error deviation is displayed in peak peak and RMS with 10 min 90 max available range e Standards 24 industry standards have been pre programmed into the clock recovery firmware available via the front panel interface Custom settings can also be pro grammed and saved for future use BERTScope Clock Recovery Instruments Standards Coverage H ww Loop Response dB f ETE xH MHz w MH 12MH Loop Bardwidih Hz MAL 10 Gigabit Ethernet Bit Rate 3 125 Gbs Bit Rate 10 3125 Giss Loap Bandwidth 1 875 MHz Peaking 0 dB Loop Bancherictth 4 MHz Peaking 0 dB 4x Fibre Channel Bit Rate 4 25 Ghis Loop Bandwidth 2 55 MHz Peaking 0 3 dB max 2x Fibre Channel Bit Rate 2 12 Ghi s Loop Bandwidth 1 275 MHz Peaking 0 3 dB max The small graphics and accompanying table show common standards the data rates they employ and the loop bandwidths required for compliance measurements The clock recovery instruments encompass a class leading majority of the common standards including those listed in the table and displayed in the graphs This ensures that your current and future needs will be covered for compliance and beyond OIF CEL G Bit Rate 6 25 bb s Loop Bandwidth 3 6 MHz Peaking 0 1 dB max 8x Fibre Channel Bit Rate 8 5 Ghi s Loop Bandwidth 5 1 MHz Peaking 0 3 dB max OIF CEI 116 Bit Rate 11 0 Ghi
10. s Loop Bandwidth 4 MHz Peaking 0 1 dB max OIF CEI 116 Bit Rate 11 0 Gbs Loop Bandwidth amp MHz Peaking 0 1 dB max OIF CEI 116 Bit Rate 11 0 Gis Loop Bandwidth amp MHz Peaking 0 1 dB max Serial ATA Gen 2 frauwS00 Bit Rate 3 0 Ghi Loop Bandwidth 3 MHz Peaking 2 1 dB Serial ATA Gen 2 thaudlo67 Bit Rate 3 0 Ghis Loop Bandwidth 0 9 MHz Peaking 0 dB SONET 0 48 SDH STM 16 Bit Rate 2 488 Ghi Loop Bandwidth 1 MHz Peaking 0 dB Fully Buffered DIMM I Bit Rate 4 8 Ghis Loop Bandwidth 11 MHz Peaking 0 2 dB Fully Buffered DIMM I Bit Rate 6 4 Ghis Loop Bandwidth 11 MHz Peaking 0 5 dB SONET 0C 192 SDH STM 64 Bit Rate 9 95 Gibs Loop Bandwidth 4 MHz Peaking 0 dB XF PVF Bit Rate 10 5 bs Loop Bandwidth 8 MHz Peaking 0 1 dB max Notes 1 Ripple at high loop bandwidths in these graphs are a feature of the measurement system rather than the loop 2 The reference dotted lines are placed in identical positions in each graph to aid comparison P I Express II Bit Rate 5 0 Gibs Loop Bandwidth 5 MHz Peaking 1 dB BERTScope Clock Recovery Instruments Specifications Common Standard Data rate clock divide Peaking Slope Spread spectrum Gb s dB clocking ratios 10 Gb s Ethernet 10 312 20 dB Ethernet transmitter test eade XAUI 3 125 1X 1 063 Fibre 2X 2 12 20 dB Channel 4X 4 25 decade 8X 8 65 4 976 to RCDE 6 375 20 dB 8 MHz foremost test
11. s for ITU appli OIF CEI Ee T cations BW1667 other Minimum of 11 Gb s 9 95 to 11 1 4 MHz for stress testing in one case 250Ul1 Gen 1 amp 2 categories i internal hard drives etc and Gen1 f _ 1667 l l lantema pave m medium reach use f _ 500 5UI 150 000 and 10 for Gen 2 and 250UI f 500 6 000 and 65UI for Genb 1 i x extended reach uses f 1667 f 1667 1 800 Type 2 This is same as SAS Implied spec d as damping factor SATA see Yes for SATA Optional of 0 707 min to 1 00 max conver note for SAS sion taken from Gardner reference 1 Gen 2 Loops bandwidths spec d with i f __ 10 300 000 transition density of 1 100 or 1010101 pattern Only standard we re aware of to specify this Assumption is that loop bandwidth will change proportionally as transi tion density reduces O0C12 STM 4 0 250 oby OC48 STM 16 1 000 3 OC192 STM 64 4 000 E Receiver 8 000 test XFP XFI XFP XFI Trans 9 95 11 2 20 dB mitter 4 000 decade test 3 2 4 0 24 11 to 33 Eua Ae M 4 8 24 11 to 22 eraio test Full buffered 2nd order SSC swing 4 8 6 4 8 0 F i DIMM FB DIMM2 a a E Receiver test 0 06 UI 9 6 clock swing 1st order PCI 2 5 25 with 20 Yes optional veyed dB decade Receiver test 65 ps p ii 50 Up to 1 dB 1st or 2nd pk pk swing order Gen 1 f aua 1667 f 15 Implied spec d as damping factor of 0 707 min to 1 00 max conver sion taken from Gardner r
12. stics are automatically set when a given standard is selected from a pull down menu However for users wanting to explore the limits of their designs full control of param eters is also easily available A good example of this is for systems where restricting the build up of jitter is critical Clock recovery plays a crucial role in this and the ability to emulate a clock recovery source with excessive peaking is a great way of understanding the system sensi tivity to jitter gain e Edge Density The user has the ability to adjust the desired LBW to the edge density of the signal under test The edge density in monitored and then optimized through loop gain settings The clock recovery locks on data patterns with 10 to 100 edge densities Each instrument has variable jitter peaking that goes way beyond simple compliance and allows jitter gain in excess of 10 dB if desired Remote control of the instrument is easily accessible via USB through BERTScope or via laptop PC TCP IP and GP IB protocol inter faces are supported e Primary Input Parameters nominal frequen cy of the data input signal loop bandwidth and peaking up to 6 dB are configurable on the front panel display e Lock modes Manual and auto modes are supported Locking status is displayed as locked LED green locking LED amber unable to lock LED red Lock range min 10MHz max 500MHz e Phase Error The clock extraction circuit produces a phase error
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