Altera - RocketBoards.org
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1. 31 2015 Altera Corporation Public JAN DTE RYA e Physical Address Mapping FPGA to SDRAM FPGA Masters have access to full 4GB of SDRAM address space Subject to MPFE MPU restrictions No coherency No virtual addressing 32 2015 Altera Corporation Public ANU S n YAN 33 Physical Address Mapping MPU MPU has access to the lower 3 GBytes of SDRAM Kernel manages and can allocate memory in this ID 3GByte space Allocate for both user and kernel Space Allocatable on 4K Byte Boundaries page size 2 GB 1 GB 0 GB 2015 Altera Corporation Public AN S RYAN Physical Address Mapping MPU to FPGA FPGA Portion MPU can access 960 MBytes of FPGA address space via HPS to FPGA Bridge MPU can access 2 MB of FPGA address space via HPS to FPGA Lightweight bridge lt Not allocatable in user space Space FPGA peripherals on Linux page size 4KB boundaries Access methods discussed In Developing Linux Drivers for Custom Peripherals Workshop 34 2015 Altera Corporation Public Physical Address Mapping FPGA to HPS FPGA to HPS F2H masters see 4 GByte address space E T c i H2F FPGA Slaves lt F2H bandwidth to SDRAM limited vs FPGA to SDRAM bridge 6d Bit AX Bus um Bit A2. Linux Strategy Kernel Same kernel source tree for all SoC s and NIOS I Same kernel binary for all 32bit SoCFPGA Same kernel binary for all 64bit SOCFPGA Device tree support SoCs and NIOS II Upstream and maintain to kernel org U Boot 2013 01 01 supported for Cyclone V amp Arria V SoC 2014 10 supported for Arria 10 SoC 2015 xx support in progress Same U Boot source tree for all SoC s and NIOS II Toolchain Standard un patched Linaro Toolchain gcc linaro arm linux gnueabiht 4 9 2014 09 59 2015 Altera Corporation Public Nios II 4 Altera SoC ARM ARM Cortex A9 Cortex A9 FPGA S Peripherals Crypto Engine DSP Accelerator Soft Core AN S RYAN Linux Strategy Build Systems O lt Offer support for Angstrom for SoC Angstr om Embedded Linux distribution Yocto Project configuration package manager OPKG Uses meta altera Yocto layer Currently 2014 12 Linaro GCC 4 9 for 32 bit SoCs lt Yocto Project Support for SoC yocto PROJECT SOCFPGA layer meta altera upstreamed to Angstrom Yocto Project v1 7 ready Buildroot for both SoC and Nios II Holl your own from relevant source 60 2015 Altera Corporation Public JAN DTE RYA Build System Resources Angstrom flow for SoC http rocketboards org foswiki view Documentation AngstromOnSoCFPGA 1 Yocto flow for So
3. How do you build Linux for an FPGA fabric that changes You use the Device Tree Generator User Information Device tree information can be added to custom Qsys peripherals and custom drivers Device Tree Source can be edited by hand 113 9 2015 Altera Corporation Public NOTE R A z How to use Altera SoC Device Tree Generator sopcinfo file describes HPS and FPGA system lt Board info file describes external devices on board Device Tree Generator creates a plain text representation of the device tree called the Device Tree Source DTS Device Tree Generator SOCEDS sopc2dts tool sopc2adts distributed as part or SOCEDS or on RBO GIT repo Compile the text into a binary representation called the Device Tree Blob DTB Optionally directly generate DTB from sopc2dts Device Tree Source to Device Tree Blob DIES Compiler Board User Info Device SOpcinfo Tree Handoff file CEN Directly generate Device Tree Blob 114 2015 Altera Corporation Public NOTE R A E Board Info File XML file required as an input to sop2ats lt Specifies information of which QSys isn t aware SPI or 12C timing or external peripherals and their properties External flash QSPI SPI or NAND properties organization specs etc lt Board specific Ethernet amp PHY information Allows the developer to disable peripherals which may be enabled in pr
4. Secure tt 2015 Altera Corporation Public JAN DTE RYA 28nm SoC System Architecture Hard Processor System HPS Processor Dual core ARM Cortex A9 MPCore processor ARM Cortex A9 Y ARM Cortex A9 NEON FPU NEON FPU Up to 5 250 MIPS 1050 MHz per core maximum L1 Cache L1 Cache NEON coprocessor with double precision FPU 32 KB 32 KB L1 caches per core 512 KB shared L2 cache sn Multiport SDRAM controller DDR3 DDR3L DDR2 LPDDR2 umct Integrated ECC support High bandwidth on chip interfaces HMM alallala SO SdH gt 125 Gbps HPS to FPGA interface 7 gt 125 Gbps FPGA to SDRAM interface rr Cost and power optimized FPGA fabric M10Kmemoryand Lowest power transceivers me Up to 1 600 GMACS 300 GFLOPS Up to 25Mb on chip RAM IHHHHHI hn Hard Multiport DDR Hard 3 9 6 More hard intellectual property IP PCle9 and SDRAM Controller PCle and 10 Gbps Transceivers memory controllers son asod ng 19435 YO dy Notes 1 Integrated direct memory access DMA 93 O 2015 Altera Corporation Public 2 Integrated ECC 24 ARM CORTEX A9 MP ARM CoreSight Multicore Debug Trace ARM Cortex A9 ARM Cortex A9 MP Core MP Core NEON SIMD FPU NEON SIMD FPU 32 KB I D w Parity 32 KB I D w Parity 512 KB L2 CACHE SHARED w ECC Accelerator Coherency Port 64 bit AXI Coherent Bus
5. Altera SoC Linux Intro Workshop 2015 Altera Corporation Public Altera SW SoC Workshop Series SW Workshop 1 Altera SoC SW Development Overview SW Workshop 2 Introduction to Linux on Altera SoC SW Workshop 3 Developing Drivers for Altera SoC Linux D 2015 Altera Corporation Public NB S RYAN Co Agenda Essential Information Resources SoC Device Overview SoC Physical Address Map SoCFPGA Development Flow amp Tools Altera SoC Linux Overview Components of the SoC FPGA Linux BSP SoC Linux Upstreaming amp Driver Support Altera SoC Linux Boot Flow Das U Boot Bootloader Linux Device Tree for Soc FPGA Take Home Lab 2015 Altera Corporation Public ADER Welcome Here s What You Can Expect Today Experienced Linux Developers New Linux Developers Find a familiar embedded Linux An exposure to the components of development flow embedded Linux Overview of upstreaming and driver Essential Linux learning and support for mach SoCFPGA documentation resources architecture Guide to SoCFPGA resources Hardware Developers Everyone HW handoff to Linux build flow SoC FPGA architecture specific Boot and FPGA configuration for information Linux SoC FPGA recommendations and SW implications of HW architecture best practices Focused on SoC Nios Linux Specific Topics 2015 Altera Corporation
6. HARDWARE TRIGGER 000 31 A 001h 1 00 h A 0Gbh X X X GBR AN S RYAN Cross Domain Debug 2 lt Trigger from FPGA world to software world SignalTap II Logic Analyzer HARDWARE TRIGGER of 2 ignal Configuration x ose EA ger tna strane ane ene Trier rane M Trigger aut oles a Pin Jauto_stp_trigger_in_2 RAM type Auto M C Instance El wave trigger_in segments f Hard Processor System HPS trigger in trigger 2012 08 17 14 39 10 1 Lock mode Wtckc5 hip astidl Itssm hip astid Itssm 4 _hip_astidl_Itssm 3 _hip_astidi_itssm 2 _hip_astidi_tssm 1 Sis S ST s s S S S a aaa Level Don t Care Latency delay s cycles rst n Pi Mew Trace View err din a Ddh X 000h X O01h X 00h jostat Doublero ES 6 98 Setup Set Maximum Instruction Depth con done Index From Stark status n EXECUTION STOP valid data a OR Index Fram End Find Trigger Packet data b 64h X 65h X HW TRACE TRIGGER Refresh Freeze Data 39 0x8000000 E350000 CHP r 38 0x80000010 0200000 BEQ LoopO Oxs000003C NEUE E Wa trigg gaa nS SSS sc 37 0x8000003C E2511001 E ADD ri ri 1 3 6 0OX60000040 EBOOOOOS DoubleRO 5A 2015 Altera Corporation Public JAN D
7. M MontaVista embedded Lin x a Li amp A o roca AIS n 2 f j xardname amp archgroupz All amp processor amp editionz CGE amp v All amp a0 1 G E Googie 8 Most Visited _ Getting Started gt PRODUCTS SOLUTIONS COMPANY CONTACT US Ha Ny dle linux Boardisupport The table below lists all Linux board support packages supported by the MontaVista Linux family of products Under Platform is listed the specific MontaVista product that supports each board The number following the Edition refers to the generation of that product e g Version 5 0 While the list is comprehensive it may not necessarily be complete since we are always working with our semiconductor partners on support for new boards If you do not find the board you need support for please contact us Also for more information about our partners visit our Partnering Program section Vendor Board Name Architecture Processor Platform Search Vendor Board Name Architecture Processo latform Availability CGE7 MSD a for Altera ARM wore GEO Available Corporation MPCore AN S A Latest Stable Kernel Access to latest kernel features New features and drivers often released only to the latest kernel version Significant investment in kernel maintenance Back porting features bug fixes device support amp new drivers Or Constant upgrades to lat
8. Public Essential Information Resources Where to learn more a non exhaustive list 2015 Altera Corporation Public Linux Foundation Training Linux Developer classes are desig ned to help partici pants e FD331 Developing Linux Device Drivers a Learn how to develop An e FD405 Building Embedded Linux with the Yocto Project i e LFD411 Embedded Linux Developmen embedded Linux product j oM e FD414 Introduction to Embedded Android Development m Become fam liar with and e LFD205 How to Participate with the Linux Community learn tO write device d rive S e FD211 Introduction to Linux for Developers s e LFD262 Developing with Git Get practical experience with e FD312 Developing Applications for Linux the Li n UX kernel e LFD320 Linux Kernel Internals amp Debugging Learn how tO work with the e LFD415 Inside Android An Intro to Android Internals Li n Ux developer CO m m u n ity e FD432 Optimizing Linux Device Drivers for Power Efficiency http training linuxfoundation org linux courses development training L1 LINUX FOUNDATION 6 IRAI N NG N NN NN N VAA OS V NUN amp X NC M NC e t NC Linux Documentation Resources GIT Distributed revision control system to enable distributed collaboration On line documentation amp training http git scm com doc https training github com Denx U Boot Manual Complete
9. C O O SoCFPGA Linux Boot Flow Cyclone V amp Arria V SoC 2015 Altera Corporation Public e Starts Running code at reset exception address Normal operation BootROM is mapped to reset address e Hardcoded by Altera into device e Read Boot source from BSEL pins e Setup minimal configuration to read flash Load Preloader from Flash or execute from FPGA e Jumps to Preloader LI rR 29 am TF P fl En ieee N Boot ROM e U Boot SPL e Setup HPS lOs and pinmuxing e Setup PLLs and clocking e Initialize SDRAM e Load subsequent stage from Flash into SDRAM e Jump to subsequent stage typically U Boot Preloader Overview Cyclone V amp Arria V SoC Loaded by Boot ROM From flash and executed from on chip RAM or run directly from FPGA Uses U boot Secondary Program Loader SPL Open source GPL Licensed Loads U boot into RAM and jumps to U boot Always regenerate and recompile Preloader when QSys system or HPS configuration changes Quartus QSys version changes Not regenerating and recompiling the Preloader is the single most common source of SoC SW problems Covered in detail in SoCEDS User Guide and Designing Software for ARM Base SoC training class 96 2015 Altera Corporation Public JAN DTE RYA SoCFPGA Linux Boot Flow Arria 10 e Starts Running code at reset exception address Normal operation BootRO
10. Edition GSRD User Manual GHRD Golden Hardware Reference Design Overview Booting Linux Using Prebuilt SD Card Image 2 Connecting to Board Web Server 2 Connecting to Board Using SSH Running Sample Linux Applications Using Yocto Source Package GSRD v14 1 SD Card Arrow SoCKit Edition Compiling the Hardware Design FPGA Programming Generating and Compiling the Preloader Generating the Device Tree Using System Console Using Git Trees Example Designs Device Wide AMP a Arria V PCle Root Port with MSI Cyclone V PCle Root Port with MSI CycloneV SGMII Example Design Altera SoC Triple Speed Ethernet Design Example 9 Cyclone V RGMII Example Design AN S RYAN RocketBoards org Useful Links GSRD User Manual Getting Started Guides he best starting point for Linux development Beotna Linux Using Prebuili SO Card mage Connecting to Board Web Server _htip www rocketboards org foswiki Documentation GSRD Connecting to Board Using SSH Running Sample Linux Applications Compiling the Hardware Design Generating and Compiling the Preloader Generating the Device Tree Compiling Angstrom Linux Distribution Creating and Updating SD Card GSRD FPGA Programming FPGA Programming with Quartus Il Programmer Using System Console Angstrom Getting Started Device Tree Generator User Guide http www rocketboards org foswiki Documentation G
11. 0000 a Ox 0002 OOO IRQ 880003 QOO 0x00605 0000 multiple Gxt ttt_t OxOO01 D 0x0001_0 0x0001_0 0x0001_0 Ox0000_ f OxOO02 D IRG 31 OxOO03 D OxOOOf f1 Cyclone V SoC GSRD Memory Map Example L System Contents E E System sac system Use Connections E vl 41 I El El El El El El El El El sul LR LL F E p Mame O hps 0 hzf axi master f2h axi slave h2f lw axi maste EE hps only ma master O sysid qsys control slave E button pio sl El dipsw pio sl H led pio E onchip memory ell E jtag_uart avalon jtag slave O fpga only ma master H intr capturer 0 avalon slave 0 O sub 0 Si to ddr 2015 Altera Corporation Public ltis connected to 3 Masters Description Arria V Cyclona Y Hard Proce Export Aw Slave TAG to Avalon Master Bridge Avalon Memory Mapped Master System ID Peripheral Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Mapped Slave PIO Parallel 110 Avalon Memory Mapped Slave PIO Parallel 110 Avalon Memory Mapped Slave On Chip Memory RAM or ROM Avalon Memory Mapped Slave TAG UART Avalon Memory Mapped Slave TAG to Avalon Master Bridge apped Master nterrupt Capture Module Avalon Memory Mapped Slave FFT sub Avalon Memory Mapped Slave Avalon Memory Mapped Master Clock clk_ 0 clk_ clk clk_O clk clk 0 clk clk_
12. 2015 Altera Corporation Public The Two Best Sources for Linux Development Information lt An open source OS breeds open source information o bo boot time reduction x 3 C B https www google com search q embedded linux boot time reduction amp oq emb Google boot time reduction linux 0 Nom Web Images Maps Shopping More v Search tools About 131 000 results 0 37 seconds Embedded Linux boot time reduction Free Electrons free electrons com services boot time Making your embedded Linux systems boot faster Investigating boot time issues and applying optimization techniques that dont require a redesign Free Electrons Embedded Linux Experts free electrons com v Embedded Linux kernel and Android development training and consulting services Buildroot commercial support Embedded Linux boot time reduction Offering our broad embedded Linux development experience through our 42 295 views How to boot an uncompressed Linux kernel on ARM 38 199 views Youve visited this page 4 times Last visit 11 1 14 2 Update on boot time reduction techniques with figures T events linuxfoundation org opdenacker boot time p Linux Foundation gt http free electrons com doc training boot time gt That s where you will find extensive 9 2015 Altera Corporation Public JAN DTE RYA m RocketBoards org Altera SoC Linux Community Portal The source
13. Memory Mapped Slave cIK 0 Qx0000 3040 0xO0000 3047 la 10 Hard Processo interrupt receiver Interrupw Receiver clock IRQ O IRQ 31 9 Arria V Cyclone Y Hard Pro El hps_only_master J TAG to Avalon Master Bridge Inter Process Communication master Avalon Memory Mapped Master clk_0 o Peripherals o Osys Interconnect es as rm Type Path 6 Info Messages soc_system hps_0 i S i Fr LET anil i D 4 Eee 47 2015 Altera Corporation Public JAN DTE RYA Hard Processor System Configuration Hard Processor System hps_ sys Hard Processor System altera_hps 5 x baud sys File Edit System View Tools Internal Documentation Block Diagram a FPGA Interfaces Peripheral Pin Multiplexing HPS Clocks SORA bel Component Library Show signals hard x Enable MPU standby and event signals Eu Project lm Enable MPU general purpose signals 049 New component Enable FPGA ta HPS Interrupts Library Enable Debug APE interface Embedded Processors a Floating Point Hardwan C Hard Processor System Interface Protocols PCI Enable System Trace Macrocell hardware events L Enable FPGA Cross Trigger Interface ne Enable FPGA Trace Port Interface Unit Boot and Clock Selection Enable boot from FPGA ready a Arria V Hard IP far a Avalon MM Arria a A
14. Register Share You are here Documentation Welcome to the Documentation Web SoC Boards Terasic DE1 SoC Development and Education Board Altera Cyclone V SoC Board Altera Arria V SoC Board Arrow SoCKit Evaluation Board EBV SoCrates Evaluation Board Macnica Helio SoC Evaluation Kit DENX MCV SoM NOVPEK CVLite Devboards DBM SoC1 module Enclustra SA series e e e SoC Devices amp Board References Cyclone V SoC Links Arria V SoC Links Preloader amp U Boot HPS Boot Flow Preloader and U Boot Source Code Files amp Folders Adding a New Board to Preloader amp U Boot QSPI Serial NOR Flash Layout SDMMC Flash Layout 12 2015 Altera Corporation Public GSRD Golden System Reference Design Documentation GSRD User Manual GHRD Golden Hardware Reference Design Overview Booting Linux Using Prebuilt SD Card Image Connecting to Board Web Server Connecting to Board Using SSH Running Sample Linux Applications Angstrom On SoCFPGA Using Yocto Source Package GSRD v13 1 SD Card Compiling the Hardware Design FPGA Programming Generating and Compiling the Preloader Generating the Device Tree Using System Console Using Git Trees e o e FPGA Programming FPGA Programming from HPS Software FPGA Programming with Quartus Il Programmer Booting Maa Pla GSRD Documentation Arrow SoCKit
15. documentation from the folks who wrote Das U Boot hito www denx de wiki U Boot Documentation Free Electrons Complete training materials posted free lt hitp free electrons com docs Device Tree for Dummies http events linuxfoundation org sites events files slides petazzoni device tree dummies pdf 7 2015 Altera Corporation Public JAN DTE RYA e The Two Best Sources for Linux Development Information Linux Kernel Documentation The most complete and most essential Linux kernel documentation Included with the Linux kernel source code lt local GIT repo gt Documentation Documentation bash Konsole File Edit View Bookmarks Settings Help NO_HZ txt KWrite File Edit View Bookmarks Tools Settings Help NO_HZ Reducing Scheduling Clock Ticks This document describes Kconfig options and boot parameters that can reduce the number of scheduling clock interrupts thereby improving energy efficiency and reducing OS jitter Reducing OS jitter 1s important for some types of computationally intensive high performance computing HPC applications and for real time applications There are three main ways of managing scheduling clock interrupts also known as scheduling clock ticks or simply ticks l Never omit scheduling clock ticks CONFIG HZ PERIODIC y or CONFIG_NO_HZ n for older kernels You normally will not want to choose this option 8 O
16. for SoC FPGA Linux info Golden System Reference Design GSRD Updates on latest releases Step by step getting started guides SoC FPGA Mailing List RFI Active community participation in answering SoC FPGA and Linux questions Example Projects Applications and Designs From Altera and the SoC community Enables the SoC community to support Linux RocketBoards org 10 2015 Altera Corporation Public JAN DTE RYA e 11 y FA RocketBoards org x Y C 5 rocketboards org RocketBoards org tBoards org L Let s Get Started Learn how to set up yoi r Linux host PC and connect to a De relopment code and have your boa d up and running in no time DOCUMENTATION Find information on boards flows and open hardware and software MAIL LISTS Stay updated with latest news features questions and feedback 2015 Altera Corporation Public CODE Access the latest SoC Linux code from our git repositories FORUM Jump into the forum to get help and offer help Login Register Share PROJECTS Check out prpjects submitted by the community fb get inspired BOARDS Explore the latest hardware RocketBoards org Documentation yn Documentation Roc x V Bill gt CQ jrocketboards org foswiki view Documentation WebHome WE RocketBoards org Community search Projects Boards a Login
17. lab was completed Submit results amp feedback 120 2015 Altera Corporation Public NOTE R A E Thank You MEASURABLE ADVANTAGE 2014 Altera Corporation Confidential ALTERA ARRIA CYCLONE ENPIRION MAX Trademark Office and in other countries All oth
18. A recommended for Linux U boot supports file systems for FPGA configuration data All peripherals available at OS boot e Linux can configure the FPGA but tricky Not all peripherals are available at boot e 28nm F2S Bridge Errata can lock the device Linux 102 2015 Altera Corporation Public JAN DTE RYA FPGA Configuration Arria 10 SoC m e When FPGA is configured first the HPS is held in reset until the FPGA releases the HPS reset Boot ROM U boot can configure the FPGA U boot supports file systems for FPGA configuration data All peripherals available at OS boot Partial reconfiguration from Linux Quartus 16 0 103 2015 Altera Corporation Public JAN DTE RYA Das U Boot Bootloader 102 2015 Altera Corporation Public What is u boot Common embedded bootloader Command line interface w decent help and lots of hardware support Capable board bring up tool Driver support for a wide variety of essential peripherals Loads the Device Tree and modities Device Tree configuration at run time Loads the kernel and passes boot arguments From local file system over network or over a serial link Open source GPL licensed http www denx de wiki U Boot 105 2015 Altera Corporation Public NOTE R A E U Boot for SoCFPGA Sourced from GitHub Altera Opensource or SOCEDS httos github c
19. Altera Corporation Public AU S RA Te A Cross Domain Debug 1 0 SOPA TRIGGER EA N ga seg Re ade Breakpoint Enable Breakpoint 43 44 ne 45 46 Breakpoint Properties Breakpoint Types ELE a Toggle Breakpoint D5 5 Breakpoints 47 i Default Breakpoint Type a Toggle Hardware Breakpoint Go to Annotation Ctri 1 Resolve Breakpoint 3 Enable Breakpoint Add Bookmark Breaknoint F ti i c n j Bu Add Task 9a re apu T iE PFO IPEF JES 11 Toggle Trace Start Point W Show Quick Diff CErl Shift Q 7 Toggle Trace Stop Point Show Annotation ES Tri Point aggle Trace Trigger Point wv Shaw Line Numbers nel UE 53 Preferences O BOx18 j Standarc Name rst n err din a QU M Trigger in Pin auto_stp_trigger_in_2 Node lauto_stp_trigger_in_2 El C Instance A waveltrigger_in Hard Processor System HPS trigger out Pattern Don t Care d SignalTap 7 2015 Altera Corporation Public 42main int argc Trigger from software world to FPGA world char argv gboolean retval GError error NOLL if games runtime init gnometris return 1 ARDWARE TRIGGER
20. Altera s primary embedded engineering center Austin provides access to one of the richest embedded processing talent bases in the world 20 2015 Altera Corporation Public Altera SoC Product Portfolio LOW END SoCs MID RANGE SoCs HIGH END SoCs Lowest Power Form Factor 8 Cost High Performance with Low Power Form Factor amp Cost Highest Performance amp System Bandwidth Lu O E _ Stratix 10 Soc O z e 14nm Intel Tri Gate 64 bit Quad ARM A53 MP Arria 10 Core T e Optimized for Max Performance per Watt 7 e 20nm TSMC 4 T Arria V 4 5 GHz Dual ARM a Soc Cortex A9 MPCore 17G Transceivers e 28nm TSMC 1333 MHz DDR4 Cvclone V 1 05 GHz Dual ARM Up to 660 KLE y SoC Cortex A9 MPCore Up to 3356 Multipliers 10G Transceivers 18x19 533 MHz DDR3 e 28nm TSMC 925 MHz Dual ARM Upto462KLE Cortex A9 MPCore Up to 2136 Multipliers 5G Transceivers 18x19 400 MHz DDR3 25 to 110 KLE Up to 224 Multipliers 18x19 SS DEVICE AVAILABILITY LOW POWER SoC devices available across entire product portfolio 24 2015 Altera Corporation Public JAN DTE RYA e ARM Public Processor Offering Stratix 10 Application Processor Cyclone V Arria V Arria 10 uy Cortex R7 CORTEX R ee Cortex R4 CORTEX M E Real time control Cortex M1 Cortex MO Cortex MO Microcontroller SECURCORE e SC100 C300
21. Board Support Package U Boot User Space Device Tree debug compiler shell etc lt SoC Machine Specific Layer mach socfpga c Drivers for SoC and board A y components Drivers Kernel Machine Specific Layer sinus SoC Linux BSP release provides all of the components in fully non proprietary source code form 75 2015 Altera Corporation Public SoC Linux Board Support Package User Space debug compiler shell etc Example configuration to enable evaluation and initial develooment Root File System Kernel configuration to enable s evaluation and initial development Up streamed and community J Drivers supported drivers Up streamed mach socfpga Machine Specific Layer architecture Board specific layer which 5 enables common kernel binary Open source community gt supported boot loader BSP Development kit or custom board 76 2015 Altera Corporation Public jm n Cd C mi d adi TRG T 2 1 de M zz iil um Yers 418 Everything you need to begin Linux development SoC Development Kit Golden System Reference Design A Linux distribution for the dev kit Features 1 user license for ARM DS 5 Altera Edition Toolkit Ethernet USB CAN UART DDR3 HPS and FPGA SDCard QSPI PCle rootport amp endpoint Expansion hea
22. C http www rocketboards org foswiki Documentation YoctoDoraBuildWithMetaAltera Source Poky from the Yocto Project website git git yoctoproject org poky git Buildroot flow for Nios II http rocketboards org foswiki view Documentation NiosliLinuxUserManual Buildroot flow for SoC http www rocketboards org foswiki Documentation BuildrootForSoCFPGA 61 O 2015 Altera Corporation Public JAN DTE RYA e Angstrom Yocto Information Resources lt Yocto Project https www yoctoproject org documentation lt Angstrom Distribution http www angstrom distribution org Open Embedded htto www openembedded org wiki Main Page lt Bullding Linux w Yocto Linux Foundation class LFD405 Building Embedded Linux with the Yocto Project 62 2015 Altera Corporation Public JAN DTE RYA e Altera SOC Linux Provides Customers Kernel Choices 2014 2015 2016 Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Altera SoC Linux supports the latest stable kernel 3 mos 3 mos 3 mos 3 mos 3 mos 3 mos NEW Altera SoC Linux also supports LTSI kernel 24 months LTSI kernel available with or without Preempt Heal Time Patches 63 2015 Altera Corporation Public JAN DTE RYA Status of the Linux kernel for SoC FPGA Current versions Latest stable refer to linux socfpga git repo tags rel socfpga x x We keep up w
23. C Arria V SoC Arria 10 SoC m Cyclone V SoC Arria V SoC Arria 10 SoC 20nm 1 5 GHz 60 40 Lower Gen 3 x8 DDR4 3 LPDDR2 3 QDRIV RLDRAM III Hybrid Memory Cube 72 bit 64 bit ECC EMAC x 3 8 bit and 16 bit SD SDIO MMC 4 5 with eMMC 160 660K 900 MHz Posse eT SoC Physical Address Map Essential HW information for SW Developers 2015 Altera Corporation Public Cyclone V amp Arria V SoC HPS Physical Memory Map L3 MPU FPGA Default to SDRAM 4 GB OxFF20 0000 H2F FPGA Slaves H2F FPGA Slaves 0xC000 0000 3 GB 0x8000 0000 2 GB 1 GB 0x0000 0000 0 GB Default remap to 0x0 Hemaps as RAM amp ROM or SDRAM og 2015 Altera Corporation Public As Fo Arria 10 SoC HPS Physical Memory Map L3 MPU FPGA Default to SDRAM 4GB OxFF20 0000 H2F FPGA Slaves H2F FPGA Slaves 0xC000 0000 3 GB 0x8000 0000 2 GB 1 GB 0x0000 0000 0 GB Remaps as RAM amp ROM or SDRAM 29 2015 Altera Corporation Public JAN DTE RYA e Arria 10 SoC HPS Physical Memory Map FPGA to MPU FPGA HPS Bridge to SDRAM 4 GB OxFF20 0000 H2F FPGA Slaves H2F FPGA Slaves 0xC000 0000 3 GB 0x8000 0000 2 GB 1 GB 0x0000 0000 0 GB ACP SDRAM selected by AXCACHE 30 2015 Altera Corporation Public ANU amp A A m Physical Address Mapping L3 Main Switch mm mm men meg 7T Joss 3e Bit AX Bus Peripheral 35 py Switch AXI Bus
24. D PIO in FPGA Cyclone V SoC GSRD Memory Map Example L System Contents E Use Connections E vl 40 E System sac system Mame O hps 0 hzf axi master f2h axi slave haf lw axi master EIE hps only ma master E sysid qsys control slave BB A button pio gl sul El dipsw pio r ell TTT Kla ted pio S dl El onchip memory sl TT El jtag uart avalan jtag slave E O fpga only ma master E intr capturer 0 avalon slave 0 8 O sub 0 sO to ddr 2015 Altera Corporation Public Description Arria ViCyclone Y Hard Proce AX Master AX Slave AXI Master TAG to Avalon Master Bridge Avalon Memory Mapped Master System ID Peripheral Avalon Memory Mapped Slave PIO Parallel 1101 Avalon Memory Mapped Slave PIO Parallel 110 Avalon Memory Mapped Slave PIO Parallel 110 Avalon Memory Mapped Slave On Chip Memory RAM or ROM Avalon Memory Mapped Slave TAG UART Avalon Memory Mapped Slave TAG to Avalon Master Bridge Avalon Memory Mapped Master Interrupt Capture Module Avalon Memory Mapped Slave FFT sub Avalon Memory Mapped Slave Avalon Memory Mapped Master Export Look at led_pio at Address 0x0001 0040 Clock clk_ o clk clk clk_O clk clk 0 clk clk_ 0 clk clk clk clk_O clk1 clk 0 clk clik clk clack clk_O clk clk Base multiple OxG000 06000 88000 OO 0 0001_00c0 GxGOG OOo Ca oxo01_ 0099 gt 0x0000
25. G to Avalon Master appe Interrupt Capture Mac Avalon Memory Mappeusrawe FFT sub Avalon Memory Mapped Slave Avalon Memory Mapped Master hridae ARM sees LED through the LW bridge H2F bridge LED _ PIO base 0x0001_0040 Oxff21 0040 Oxff20 0000 ldk o l 6x0001 0080 clk dk o ia oxo001 0040 elk1 JTAG Master sees LED H2F LED PIO base 0x0001 0040 0x0001 0040 VIT x E A PPP clk clk 0x00605 0000 OxOOGl D 0x0001_0 f E weno E OxOOOf ft SOCFPGA Development Flow amp Tools Why Does This Matter for Linux Development Altera SoCs offer unique advantages User specified peripheral set Tightly coupled MPU amp FPGA fabric One of a kind HW SW debug capabilities Altera SoCs have unique requirements Understanding of paths to exchange data between MPU and FPGA Building custom BSP for user specified peripheral set Correct handling and configuration of HPS FPGA bridges Altera SoCs have tools to enable the power of a integrated MPU and FPGA 44 2015 Altera Corporation Public JAN DTE RYA FPGA Design Flow lt Sa Hardware Se saQsys Development _ QUARTUS e Quartus II design software Qsys system integration tool e Standard RTL flow Altera and partner IP HW SW Handoff e ModelSim VCS NCSim etc AMBA AXI and Avalon bus functional models BFMs e Signallap II lo
26. Interface Snoop Control Unit 2 32 64 128 Port 2 1 32 64 bit Port AXI 32 64 128 AXI 32 64 128 250MHz FPGA LOGIC 300 MHz 300 MHz PCle Gen 3 X 8 Controller Hard IP PCS amp FEC Interlaaken PCS 10G KR FEC PHY Notes 1 Integrated direct memory access DMA 2 Integrated ECC 2015 Altera Corporation Publi 3 DDR3 4 amp LP DDR3 SDRAM Support fo HPS Memory Ol 4251 High Level Block Diagram FPGA HPS to FPGA Configuration FPGA to HPS Control FPGA to SDRAM ARM Cortex A9MPCore HPS CPUO CPU1 ARM Cortex A9 ARM Cortex A9 NEON FPU NEON FPU 32 KB I 32 KB I 32 KB D 32 KB D ALL Multi port DDR L2 Cache 512 KB SDRAM Controller TMC Trace Debug Port Low Speed Peripherals Timers GPIO UART SPI I2C CAN 25 2015 Altera Corporation Public 26 Technology Processor Performance Total Power Dissipation Max PCI Express Hard IP Memory Devices Supported Max HPS DDR Data Width EMAC Cores NAND Device Supported SD MMC devices Supported FPGA Logic Density Range LEs FPGA Core Performance 2015 Altera Corporation Public 28nm 925 MHz 100 Gen 2 x4 DDR2 DDR3 DDR3L LPDDR2 40 bit 32 bit ECC EMAC x 2 8 bit SD SDIO MMC 25 110K 260 MHZ 28nm 1 05 GHZ 100 Gen 2 x8 DDR2 DDR3 DDR3L LPDDR2 40 bit 32 bit ECC EMAC x 2 8 bit SD SDIO MMC 3 0 450K 307 MHz A Comparison Cyclone V So
27. M is mapped to reset address e Hardcoded by Altera into device e Setup minimal configuration to read flash Load Preloader from Flash in On Chip memory skipped if booting from FPGA e Jumps to Preloader Boot ROM e Setup IOCSRs and pinmuxing e Setup PLLs and clocking Initialize SDRAM e Load Linux Linux 97 O 2015 Altera Corporation Public JAN DTE RYA e Booting from SD eMMC GSRD Flow Simplified e Reads MBR from SD eMMC e Locates custom Altera raw partition 1 type OxA2 e Checksums amp loads Preloader image 0 from partition start address On fail loads next preloader image S Checksums amp loads U Boot from raw A2 partition 1 e Loads kernel from FAT32 partition 2 Boot script e Configures FPGA from image on FAT32 partition 2 Enables HPS FPGA Bridges Loads dtb amp boots kernel Boots and mounts root file system from EXT partition 3 Provides ONE example of an SD eMMC Linux boot flow 2015 Altera Corporation Public JAN DTE RYA m address 99 GSRD SD Card Image for Cyclone V amp Arria V Location FileName Desciption socfpga dtb Device Tree Blob soc_system rof FPGA configuration file u boot scr U Boot script Partition 1 configures FPGA and FAT32 loads kernel zimage Compressed Linux Partiti kernel image file LI i Partition 2 Various Linux root file system U boot Environment Settings EXT 3 Part
28. O IRQ 31 Basic Functions E a 16550 uart 0 Altera 16550 Compatible UART clock e DSP RET avalon_slave Avalon Memory Mapped Slave clk_0 0x0000_2200 0x0000_23fT y Interface Protocols irq_sender Interrupt Sender clock gt al HER E a 16550 uart 1 Altera 16550 Compatible UART clock En avalon_slawe Avalon Memory Mapped Slave clk_0 x 000 2000 jOoxOOOO 21ff Interlaken EE gt JESD irq sender Interrupt Sender clock gt amp PCI Express HER E spi 0 SPI 3 Wire Serial clk Rapidlo 3 E spi control port Avalon Memory Mapped Slave cIk 0 x0000 2400 0x0000_241F 9 Serial ira Interrupt Sender clk gt Altera 16550 Compatible aa E button_pio PIO Parallel 1 0 clk FER s1 Avalon Memory Mapped Slave clk_0 0x0000_0020 Ox0000_002f JTAG UART irc Interrupt Sender clk gt SPI 3 Wire Serial FTT E dipsw pio PIO Parallel 1 0 clk UART RS 232 Serial Port Pat sl Avalon Memory Mapped Slave cIk 0 0x0000 0030 0x0000_003F Transceiver PHY ES ira Interrupt Sender clk Y O O o Memory Interfaces and Controllers m E led pio PIO Parallel 1 0 clk o PLL sl Avalon Memory Mapped Slave clk_0 0x0000_0000 0x0000_001T 9 Processors and Peripherals L 14 E onchip memory2 0 On Chip Memory RAM or ROM clk1 Co Processors sl Avalon Memory Mapped Slave cIK 0 0x0000_0000 0x0000_FFFT Embedded Processors ale El intr_capturer_0 Interrupt Capture Module clock Hard Processor Systems E avalon slave O Avalon
29. SRD141 Device I reeGenerator lt Programming FPGA from HPS http www rocketboards org foswiki Documentation GSRD131ProgrammingFPGA GSRD Releases http releases rocketboards org 13 2015 Altera Corporation Public JAN DTE RYA e Several Ways to Learn lt Instructor led training Face to face with an Altera expert Training Engineer 20 courses to choose from 8 hour classes lt Virtual classes taught via WebEX Can ask questions to Altera expert Training Engineer Course content same as instructor led classes 1 2 day sessions 200 topics available 30 minutes in length lt Videos free and always available YouTube videos 4 minutes each 2015 Altera Corporation Public SoC Classes Available Instructor led or virtual classes Designing with an ARM based SoC Developing Software for an ARM based SoC Online classes Hardware Design Flow for an ARM based SoC Software Design Flow for an ARM based SoC SoC Hardware Overview the Microprocessor Unit SoC Hardware Overview Interconnect and Memory SoC Hardware Overview System Management Debug and General Purpose Peripherals SoC Hardware Overview Flash Controllers and Interface Protocols SoC Bare metal Programming and Hardware Libraries Getting Started with Linux for Altera SoCs 15 2015 Altera Corporation Public JAN DTE RYA e Essential SoC Software Too
30. TE RYA e Oxso00006 Correlate HW and SW Events Debug event trigger point set from either ARMS DS 5 Toolkit Tor Memory Screen oE Outline f Disassembly 7 Si g n a IT a p TM L O g l C Index Address Opcode Disassembly OxD0DB2CC2C e BCS get dc size chroi BitstreamGetBits Analyzer 0x00820C30 MOV ri 2 0x00820C34 MOV ra r Or 000820038 BL BitstreamshowBit BitstreamShowBbits DS 5 debu er 0x008 20864 PUSH r4 Og 3 971 524 0x0082D26 590300C LOR r3 r6 40xc 0x0D82D25C LDR r12 r8 4 amp 0 Timestamp Correlated Captured trace can then be analyzed using SignalTap Il Logic Analyzer timestamp correlated H d 3 AE AE 14 12 10 B E E g d E I I 1 I 1 even tS os TE ma SOSA ne SEMEL po ime enon anion anion fg foot ing XR tigi Loon m Soon ten oon Ing n Tn m Xn y xmi toy Jon Trigger Position BE 2015 Altera Corporation Public JAN DTE RYA 56 SoC EDS Editions Summary 30 Day Edition Edition Evaluation TURBO open Image Generator X X A Flash Image Creator X Device Tree Generator Linux X Component Key Feature xls Q gt Q O h O 2 o gt D O Q O1 gt D D gt A Eclipse IDE X Debugging over Ethernet Linux X Debugging over USB Blaster ll JTAG a O 5 Automatic FPGA Register Views X xX 2X xX xX Pe Hardware Cross triggeri
31. XI Eus 3e Bit AX Bus L4 32 Bit APB Bus UART Timer EC y CAN GAO Clock Reset Scan 2 2 14 m ig 3 Manager Manager Manager 35 2015 Altera Corporation Public JAN DTE RYA 36 Cyclone V SoC Memory Map Example SDRAM 1 GByte FPGA JTAG Chain SDRAM x19 Blaster Accelerator Bus REFCLK x1 Tj Flash 2015 Altera Corporation Public 1 GByte HPS SDRAM ANOTE RYAN Cyclone V SoC GSRD Memory Map Example SDRAM FPGA F2H MPU FPGA Master to SDRAM 960MB available Y 4GB for all FPGA slaves MPU cannot directly access full Saves ES RRE SES 1GByte of FPGA 3 GB SDRAM Not allocatable by kernel UT 2 GB cee ll 1GB 1 GByte HPS SDRAM OO 0 GB Default remap to 0x0 37 2015 Altera Corporation Public Cyclone V SoC Memory Map Example PIO LED aie JTAG Chain x19 Blaster Accelerator Bus DIPSW x4 b gt 38 2015 Altera Corporation Public JAN DTE RYA m 39 Cyclone V SoC Memory Map Example PIO 2015 Altera Corporation Public ARM A9 ARM A9 NEON FPU NEON FPU monaco Cussore Luseore pe RTE ethernet sone noes RAM 64KB FPGA mngr OMA DDR SDRAM QSPI GPIO NS D O UART UART cn U v CA CA TIMERS Z zZ HPS HPS FPGA itn iem ui FPGAPHPS ow latency FPGA Memory E B Er n JT AG Master LE
32. anches Provide feedback to developers Infrastructure Linaro s LAVA is used Linaro Automated Validation Architecture Runs our unit tests and log results Tests start automatically after each build is complete 70 2015 Altera Corporation Public JAN DTE RYA e Altera SoC Linux Support Model Rocketboards org SoC Nios II Linux documentation o RocketBoards org SoC amp Nios II SoC Linux reference amp example designs Rocketboards org RFI amp Linux Community Kernel RFS u boot questions SoC Nios ll subsystem and driver questions Altera com and Rocketboards org SOCEDS amp Quartus QSys documentation and questions SoC Preloader questions SoC HPS implementation specific questions Use myAltera for service requests Support from Altera is focused on SOCFPGA and Nliosll Linux Board Support Package Altera enables Linux community development on SOCFPGA amp Nios II 71 2015 Altera Corporation Public JAN DTE RYA Break 2015 Altera Corporation Public Components of the SoC FPGA Linux BSP 2015 Altera Corporation Public Building a Custom Embedded Linux Distribution How do get from here to here Altera provides a Linux BSP not a Linux distribution The BSP enables the creation of a custom distribution 74 2015 Altera Corporation Public JAN DTE RYA m SoC Linux
33. clk clk clk clk_O clk1 clk 0 clk cIk o clk clack cIk clk clk Base multiple OxG000 06000 88000 OO 0 0001_00c0 GxGOG OOo Ce oxo001 040 D 0x0000 0000 a Ox 0002 OOO IRQ 880003 QOO 0x00605 0000 multiple Gxt ttt_t OxOO01 D QxOBDOl ad 0x0001_0 0x0001_0 Ox0000_ f OxOO02 D IRG 31 OxOO03 D Cyclone V SoC GSRD Memory Map Example L System Contents E Il System soc system Use Connections Name Ftd hps 0 h2f_axi_master f2h_axi slave h2f lw axi maste EIE hps only ma master El sysid qsys control slave BB E button pio gl sul E dipsw pio zl a Cerca pie D dl E oncnip memory TT El TEE uart avalon jtag slave E Aa fnga only ma master J H intr capturer 0 awalon_slawe_0 8 E sub 0 Si to der 49 2015 Altera Corporation Public Each master sees the slave at a different address These address are offsets from the HPS bridge address ARM sees LED through the H2F Description Arria ViCyelone Y Hard Ay Slave TAG to Avalon Master E Avalon Memory Mappec System ID Peripheral Avalon Memory Mappec PIO Parallel 1 0 Avalon Memory Mappec PIO Parallel 110 Avalon Memory Mapped Slave PIO Parallel 1400 Avalon Memory Mapped Slave Gn Chip Memory RAM or ROM Avalon Memory Mappe TAG UART Avalon Memory Mappe TA
34. ddress optional size md w 0xC0000000 0x2 Control u boot auto boot Boot without delay setenv bootdelay 0 Disable auto boot stop at u boot command line setenv bootdelay l Save environment variables to flash SaveceerNnv 109 2015 Altera Corporation Public ANU S RYA z Linux Device Tree for SoC FPGA m 2015 Altera Corporation Public What s a Linux Device Tree A tree like data structure for describing hardware in embedded systems Enables device drivers to be linked to Linux kernel at run time No Linux kernel recompile required Drivers loaded dynamically after loading Device Tree Driver specific Device Tree bindings are documented in the kernel documentation Documentation devicetree bindings See Device Tree Generator User Guide See link in GSRD User Guide 111 2015 Altera Corporation Public JA Of RYA E SoC FPGA Device Tree Bindings Example 12cR0x c04000 Specify base address and size cid lt pe reg 4 Specify driver Specify interrupts Specify clock sources Enable peripheral Driver specific bindings Load and configure drivers for sub nodes 112 2015 Altera Corporation Public JA D amp RYA E o p PY IY C Cf rf EEE TTT 1 1 E ETT TE IER E ZIIIILLEL LLI NIAIXXEAB Device Trees for a Configurable Peripheral Set lt Typically developers build Linux for fixed form chips
35. der Much more y AND af SR n YA Linux GSRD for Development Kits Boot Linux from an SD card Updated images on http releases rocketboards org Choose a release date folder the gsrd folder then the bin folder Ex http releases rocketboards org release 2014 12 gsrd bin 3 10 LTSI kernel Angstrom Linux distribution for SoC Package manager to load packages from Angstrom s on line package feed Add whatever tools are needed for evaluation gstreamer usb utils etc GSRD contents Complete HW reference design w FPGA programming file Bootable SD card image amp component binaries Tagged for rebuilding in angstrom socfpga git repository ACDSX X REL GSRD PR A complete SD card ships with the board Take it out and stick it in a drawer Based on out of date 3 9 kernel 78 2015 Altera Corporation Public JAN DTE RYA Multiple Dev Kit Options w Linux BSP Kit A Family a Arria 10 SoC Dev Kit Altera Arria 10 SoC Arria V SoC Dev Kit Altera Arria V SoC Cyclone V SoC Dev Kit Altera Cyclone V SoC Atlas Board Altera Cyclone V SoC SoCKit Arrow Cyclone V SoC Helio SoC Eval Platform Macnica Cyclone V SoC ooCrates EBV Elektronik Cyclone V SoC 79 2015 Altera Corporation Public SoC Linux Up streaming amp Driver Support Maintaining and Up streaming Altera awarded maintainership Open Source Communit
36. eloader or FPGA HW 115 2015 Altera Corporation Public NOTE R A E Take Home Lab wi 2015 Altera Corporation Public Workshop 2 Lab Overview Goal Familiarize you with SoC FPGA Linux components and where to obtain them lt Overview You will build the SoC specific pieces of a Cyclone V or Arria V SoC Linux distribution and run it on your dev kit This flow builds each component discretely without a build system It does not use the optional Yocto or Angstrom based build systems It configures the distribution in a way which works for this lab which may differ trom your actual system requirements 117 2015 Altera Corporation Public NOTE R A E What You ll Need PROS Dev Kit ii cr Altera Atlas Board ao rtp ded Altera Cyclone V SoC Board Altera Arria V SoC Board Arrow SoCKIT Macnica Helio Board microSD Card Linux machine native or VM 4GByte RAM minimum Serial Terminal Application 118 2015 Altera Corporation Public NOTE YA E Obtaining Lab Files and Instructions Posted on RocketBoards Link will be emailed out after class F RocketBoards org x FA ws2 Linux Kernel intr x WN Bill gt amp 5rocketboards org foswiki view Documentation WS2LinuxKernellntroductionForAlteraSoCDevices w a nz RocketBoards org earch Q Login Register Share C
37. est stable kernel 67 2015 Altera Corporation Public Latest Stable Kernel vs LTSI Kernel L TSI Kernel LISI kernel versions supported for 2 years Critical bug fixes priority features amp new device or driver support back ported to LTSI kernel by the community Reduces investment in kernel maintenance Features bug fixes device support amp new drivers ported by the community LTSI Economic value Economic Value of LTSI Cost of Back porting CIHNYX security and bug fixes are 3MS per year per The Economic Value of mE the Long lerm Support version Initiative LTS n rabies iiia pe ma zat Sal Support Cost of maintaining in Development io ae Ocipber 2013 house patch is 288K moe in case of LTSI 3 4 Mona Fukbuyaso The Linux Foundation D 68 2015 Altera Corporation Public c nt Linux Code Quality Altera s internal development process is similar to the community s Code Peer reviews Code style checked Copyright licenses etc checked All checks enforced lt Daily Builds Automated builds run daily Complete system boot loader kernel Angstrom SD card image produced Daily Tests Linaro s LAVA is used All kernel branches tested 69 2015 Altera Corporation Public JAN DTE RYA Linux Code Tests lt Objectives Daily test of the supported Linux kernel br
38. gic analyzer System Console Debug e Quartus Il Programmer In system Update Release 45 2015 Altera Corporation Public FPGA Adaptive Debugging Software Design Flow Software Development l Design Software Development Simulate Debug Release So what exactly is Qsys GUI based system integration tool for HW system design using IP blocks lt Simplifies complex system development Raises the level of design abstraction IP verification Provides a standard platform IP integration Custom IP authoring Enables design re use Scales easily to meet the needs of end product Reduces time to market 2015 Altera Corporation Public JAN DTE RYA Qsys System Integration Platform fe QG Qsys soc system qsys data wmoyer work test soc cv soc devkit ghrd soc system qsys ww Q9 File Edit System Generate View Tools Help m IP Catalog 33 System Contents 2 Address Map Interconnect Requirements Device Family 23 Parameters 2 rmm I Use Connections Name Description Clock Base End IRQ Ta LS x E hps 0 Arria Y Cyclone Y Hard Proce Project h2f axi master AX Master ck 0 M New Component f2h axi slave AXI Slave dk 0 0x0000 0000 Oxffff ffff o Other h2f lw axi master AXI Master dk o System f2h irqo Interrupt Receiver IRQ O IRQ 31 Library a mn f2h_irql Interrupt Receiver IRQ
39. git Repository for Yocto recipes for SoCFPGA e Starting point for custom Yocto recipes angstrom soctpga git setup scripts for SOCFPGA Angstrom distribution uboot socfpga git SOCFPGA u boot development repository sopc2dts git Device Tree Generator sopc2dts repository linux refdesigns git SW source code for Linux reference designs Sourced from github com altera opensource 2015 Altera Corporation Public Kernel Release Cycle Merge amp Bug Fix 2 Weeks 12 Weeks Long Term Stable Tree gt kernel org linux stable repo Mainline Kernel Development Tree _ gt kernel org mainline repository Merge Merge Stabilizati ilizati abilization Window Stabilization Window e o New Features e o New Features Community Peature Bug Fixes Onl eal re Bug Fixes Onl Accepted Code various development repositories 84 O 2015 Altera Corporation Public JAN DTE RYA e Kernel Release Cycle Merge amp Bug Fix 2 Weeks 12 Weeks Long Term Stable Tree gt kernel org linux stable repo Mainline Kernel Development Tree kernel org mainline repository Merge A a Stabilization e o New Features e o New Features Altera up streams hare Bug Fixes Onl eat re Bug Fixes Onl with the community github com altera opensource linux socfpga development repository Altera moves with the community to the latest stable kernel 85 2015 Al
40. ith Linus Torvalds releases LTSI v3 10 Maintained for its lifetime Next LTSI version for SoCFPGA will be 4 1 available end of 2015 Real Time 3 10 ltsi rt LTSI kernel with PREEMP_RT patches lt All branches are kept in sync Bug fixes New features No changes of API in the LTSI branches 64 2015 Altera Corporation Public JAN DTE RYA e Wind River Linux Wind River Linux version 7 Linux SMP Kernel version 3 14 LTSI Real Time patches amp Carrier Grade Linux available lt Yocto project user space lt Bitbake build system WR Workbench Tools Available now from Wind River Technical Support WWw windriver com support windriver com yocto COMPATIBLE rel om the leader in er ease frc nbedde n bene WIND RIVER aT er Linun S d gt M the le d open source it your k 65 2015 Altera Corporation Public JAN DTE RYA Monta Vista Linux Monta Vista Linux CGE7 Carrier Grade Edition Linux SMP Kernel version 3 10 LTSI lt Yocto project user space Available from Monta Vista Technical Support Wwww mvista com yocto PROJECT COMPATIBLE 66 2015 Altera Corporation Public e MontaVista embedded Linux software and development tools for intelligent devices and embedded systems Mozilla Firefox Bce E E me A O es co Am o A PP
41. ition 3 Preloader image s 2015 Altera Corporation Public GSRD SD Card Image for Arria 10 Location FileName Desciption socfpga dtb Device Tree Blob soc_system rof FPGA configuration file loads kernel u boot scr U Boot script Partition 1 configures FPGA and FAT32 zimage Compressed Linux kernel image file Partition 2 Various Linux root file system EXT3 Partition 3 n a U Boot image A2 raw U boot Environment Settings address AN S RYAN 100 2015 Altera Corporation Public Creating SD Card Images Create using Altera provided script See tools folder under GSRD release folders http releases rocketboards org Builds complete SD card image which can be directly copied Use pre built images In bin folder under GSRD release folders http releases rocketboards org lt SOCEDS install directory gt examples software Can be directly copied to SD card lt Described in Creating and Updating SD Card section of GSRD User Manual http www rocketboards org foswiki Documentation GSRD 101 2015 Altera Corporation Public NOTE R A E FPGA Configuration Cyclone V amp Arria V SoC a e When FPGA is configured first the HPS is held in reset Reset until the FPGA releases the HPS reset Boot ROM PreLoader Preloader can configure the FPGA Loue Currently requires boot from QSPI U boot can configure the FPG
42. ity GPIO drivers gpio gpio dwapb c Community Timer drivers clocksource dw_apb_timer_of c Community UART drivers tty serial 8250 8250 dw c Community QSPI spi spi cadence qspi c Altera Clock Manager drivers clk socfpga clk c Altera FPGA Manager drivers fpga fpga mgors altera c Altera FPGA Bridges drivers misc fpga bridge Altera EDAC ECC drivers edac altera Altera 91 2015 Altera Corporation Public 92 Linux Driver Support for soft Peripherals Driver Kernel Source Tree Location Maintainer TSE Ethernet PCle Root Port Frame Buffer Avalon SPI Avalon UART JTAG UART QSYS Sys ID Mailbox Altera 16550 UART Avalon PIO 2015 Altera Corporation Public drivers net ethernet altera www rocketboards org www rocketboards org w o MSI video altvipfb c Spi spi altera c tty serial altera_uart c tty serial altera_jtaguart c misc altera_sysid c drivers mailbox mailbox altera c drivers tty serial 8250 8250_core c drivers gpio gpio altera c Altera Altera Community Community Community Community Altera Altera Community Altera Altera SoC Linux Boot Flow 2015 Altera Corporation Public Altera SoC FPGA Configuration Options SOC Device a HPS 2 O U E Boot code RAM ROM qu Passive Serial O O j Boot Source 94 2015 Altera Corporation Public QSPI SPI MMC SD QD P nD a O Le C O O Qs 3 EE O o M
43. ls Online Videos ARM DS 5 Altera Edition Toolchain https youtu be HV6NHr6gLx0 DS 5 Altera Edition Bare metal Debug and Trace https youtu be u_xKybPhcHl DS 5 Altera Edition FPGA adaptive Linux Kernel Debug and Trace https youtu be IrR SfVZd18 Debugging Linux applications on the Altera SoC with ARM DS 5 https youtu be ZcGQEjKYWOc FPGA adaptive debug on the Altera SoC using ARM DS 5 https youtu be 2NBcUv2 I xbl Streamline Profiling on Altera SoC FPGA Part 1 Setup httos youtu be X k9ImMXQTio Streamline Profiling on Altera SoC FPGA Part 2 Running Streamline https youtu be Tzbd7qldKqY 2015 Altera Corporation Public JAN DTE RYA Essential SoC Hardware Documentation Resources Hard Processor System Technical Reference Manuals Available in Device Handbooks https www altera com products soc portfolio cyclone v soc support html https www altera com products soc portfolio arria v soc support html https www altera com products soc portfolio arria 10 soc support htm Contain Functional Descriptions Peripheral Contain Control Register Address Map and Definitions These are also available online at the links above in HTML and PDF formats HPS SoC Boot Guide Cyclone V SoC Arria V SoC AN709 HPS SoC Boot Guide Arria 10 SoC included in HPS TRM in Arria 10 Device Handbook ARM Documentation Site Documen
44. m HPS Altera SoC HPS built mainly ER FF with off the shelf Hard IP components JL ARM E Synopsys DesignWare M m Cadence Wide spread usage and Shared Multiport DDR SDRAM Controller 2 Configu community support result in AAA RE h Ig h q u al ty a rive rS amp As DSP Altera is actively contributing OK memory and features updates and fixes ms to the community Bl and 10 Gbps Transceivers Notes 1 Integrated direct memory access DMA 89 2015 Altera Corporation Public 2 Integrated ECC SO l SdH son asod ng 194935 YO dy Linux Driver Support for HPS Peripherals Driver Kernel Source Tree Location Maintainer SPI drivers spi spidev c Community drivers spi spi dw c drivers spi spi dw mmio c CAN drivers net can c can c can platform c Community Ethernet drivers net ethernet stmicro stmmac stmm Community ac platform c NAND mtd nand denali dt c Community l2C drivers i2c busses i2c designware platdrv c Community USB drivers usb dwc2 Community USB PHY usb phy phy generic c Community SDMMC drivers mmc host dw_mmc pltfm c Community Timer drivers clocksource dw_apb_timer_of c Community 90 2015 Altera Corporation Public Linux Driver Support for HPS Peripherals Driver Kernel Source Tree Location Maintainer Watchdog drivers watchdog dw_wadt c Community PL330 DMA dma pl330 c Community GIC drivers irqchip irq gic c Commun
45. ng CPU FPGA Event Correlation X A Compiler Tool Chains Linaro Tool Chain Linux X X X ee CodeBench Lite EABI Bare metal X X X Hardware Libraries Bare metal programming Support X X X E Programming Golden System Reference Design X X X xamples Everything needed for Linux development is free amp open source 2015 Altera Corporation Public Altera SoC Linux Overview Linux for Altera SoCs 4 RocketBoards org amp Chris Martin New Share High Quality Linux Support Documentation Community Projects Boards Stay up to date on all the exciting news on RocketBoards org noteworthy events announcements latest software updates new Modern release strategy oj Let s Get Started Learn how to set up your Linux host PC and connect to a Development Kit Download code and have your board up and running in no time lt Multiple Kernel Versions TI DOCUMENTATION CODE PROJECTS Find information on boards flows Access the latest SoC Linux code Check out projects submitted by the and open hardware and software from our git repositories community to get inspired ha MAIL LISTS FORUM BOARDS O t a e e t Stay updated with latest news Jump into the forum to get help and Explore the latest hardware features questions and feedback offer help A CNE Angstrom 4 git Linaro YOCtO ue PROJECT 2015 Altera Corporation Public JAN DTE RYA m 58
46. om altera opensource u boot socfpga git lt SoC EDS install dir gt examples hardware lt _ghrd gt uboot socfoga lt Supported u boot versions Cyclone V SoC amp Arria V SoC 2013 01 01 Preliminary support for 2015 xx up streamed to Denx GIT repo Arria 10 SoC 2014 10 2014 10 4 later up streamed to Denx Git repo u boot socfpga branch amp tag convention similar to linux socfpga 106 2015 Altera Corporation Public NOTE R A E U Boot for SoCFPGA SoCFPGA specific u boot documentation lt u boot socfpga repo gt doc README SOCFPGA u boot controls SDRAM size passed to kernel u boot SDRAM sizing algorithm overwrites device tree SDRAM memory node entry Device tree entry overrides boot arguments SOCFPGA u boot environment variables Pass HPS FPGA bridge status and configuration info from preloader Enable FPGA programming from preloader 107 2015 Altera Corporation Public NOTE R A E SOCFPGA HPS Peripherals Supported in U boot Peripheral support in u boot socfoga 2013 01 01 _MPU Subsystem FPGAManager Ethernet MAC Serial Cache MMU Clock Manager __ Flash Memory e Timers 108 2015 Altera Corporation Public NOTE R A E Useful U boot Commands and Variables lt Write memory location mw lt address gt lt size gt lt optional count gt mw OxCOO00000 0x10 0x6 Read memory location md optional b w 1 gt a
47. ommunity Projects Boards You are here Documentation Training Altera SoC Workshop Series WS2 Linux Kernel Introduction for Altera SoC Devices WS2 Linux Kernel Introduction for Altera SoC Devices This is the first of a series of workshops to help users become familiar with software development for the Altera SoC family of parts 15 Jul 2015 02 10 Version 43 amp Chris Martin Introduction Link to Workshop Slides Links to Lab Sections Set Up for Labs install Required Tools Obtain Development Board Obtain SD card Image Verify that the SD card is properly programmed and that your board and host PC are properly configured Copy the Lab Materials from SD Card Introduction This workshop will take you though the manual steps of building the SoCFPGA specific pieces of a custom embedded Linux distribution It is intended to familiarize you with the resources necessary to build an embedded Linux distribution for your own custom SoCFPGA based board This workshop is not an introduction to or training on Embedded Linux it is only intended to be an overview of the SoC FPGA specific components of a custom Linux 2015 Altera Corporation Public JAN DTE RYA m 119 What You Will Accomplish Generate and build the preloader Generate and compile the device tree Obtain and build u boot lt Obtain configure and build the kernel lt Program to an SD card lt Run a Simple Linux App Verifies the
48. rate only when user options boot source etc change Provided by Altera Open Source Input File JE Intermediate File U Boot Output File Binary 2015 Altera Corporation Public JAN DTE RYA m Altera SoC Embedded Design Suite Comprehensive Suite SW Dev Tools Hardware to Software Hardware software handoff tools cae Preloader amp Device Tree Generators Bare metal application development Firmware Development Linux Application SoC Hardware Libraries Development Bare metal compiler tools FPGA adaptive debugging i FPGA ARM DS 5 Altera Edition Toolkit Adaptive Debugging Linux application development A Yocto Linux build environment v Free Web Edition Work in conjunction with the Community Portal Y Subscription Edition Design examples v Free 30 day Eval Pre built binaries for Linux U Boot 51 2015 Altera Corporation Public JAN DTE RYA Eclipse Compiler Debugger Perf Analyzer Altera USB Blaster Il MBA ETS Connection Ci ARM Development Studio 5 DS 5 Altera Edition Toolkit Removes debugging barrier between CPUs and FPGA Exclusive OEM agreement between Altera and ARM Result of innovation in silicon software and business model Supports FPGA Adaptive Linux kernel driver amp application debug DSPAccaerator Soft Core 52 O 2015
49. tation available for all ARM IP Cortex A9 amp A53 MP Cores FPU NEON GIC ARM Peripherals etc Requires free registration Refer to HPS TRM for IP core names and revision information http infocenter arm com help index sp 17 2015 Altera Corporation Public JAN DTE RYA Essential SoC Software Documentation Resources Altera SoC Embedded Design Software SoC EDS Tools User Guide Linux Baremetal Software Development Tools Overview HPS Preloader User Guide HPS Flash Programmer User Guide SD Card Boot Utility Getting Started Guides Preloader Linux Bare Metal Debug HW Library htto www alterawiki com wiki SoCEDSGeitingStarted SoC HPS Release Notes SoC Abstraction Layer SoCAL API Reference lt SoC EDS install dir gt ip altera hps altera_hps doc socal html index html Hardware Manager API Reference lt SoC EDS install dir gt ip altera hps altera_hps doc hwmgr html index html GCC Documentation lt SoC EDS install dir gt ds 5 documents gcc getting_started html Bare Metal Compiler lt SoC EDS installation directory gt host_tools mentor gnu arm baremetal share doc sourceryg arm altera eabi 18 2015 Altera Corporation Public JAN DTE RYA SoC Device Overview 2015 Altera Corporation Public Altera Investment in Embedded Technologies Altera established Austin Technology Center ATC in 2011
50. tera Corporation Public JAN DTE RYA Altera BSP Kernel Development 2 Weeks 12 Weeks Long Term O 2 gt 3 17 8 Stable Tree kernel org linux stable repo Mainline Kernel Development Tree Altera BSP Kernel Dev Major Release amp Frequent Updates New Features and New Features and all Bug Fixes 8 all Bug Fixes amp updates updates github com altera opensource linux socfpga repository 86 2015 Altera Corporation Public Altera LTSI Kernel Development Long Term __MS Sd 222222222222 M gt Stable Tree kernel org linux stable repo LTS Industry Tree kernel org ltsi kernel repository LTSI patches Altera BSP Kernel Dev New Features Major Release 8 amp Bug Fixes Frequent Updates Latest tested release github com altera opensource linux socfpga repository 87 2015 Altera Corporation Public JAN DTE RYA e Altera LTSI Kernel Development Long Term __MS Sd 222222222222 M gt Stable Tree kernel org linux stable repo LTS Industry S gt Tree kernel org ltsi kernel repository LTSI patches Altera BSP Kernel Dev New Features Major Release 8 amp Bug Fixes Frequent Updates Kernel tags for GSRD releases on Rocketboards github com altera opensource linux socfpga repository 88 O 2015 Altera Corporation Public NOTES RAYA s SoC Hard IP Driver Support Hard Processor Syste
51. valon MM Cyclon a Cyclone Y Hard IP Example design fo amp Stratix V Hard IP fa Enable boot from FPGA on failure AXI Bridges FPGA to HPS interface width 32 bit HPS to FPGA interface width 64 bit v Lightweight HPS to FPGA interface width Unused FPGA to HPS SDRAM Interface Click the and buttons to add and remowe FPQGA to HPS5S SDRAM ports i h ee bee E Warning hps sys ODT is disabled Enabling ODT Mode Register 1 may improve signal integrity e Info hps sys Peripheral MAND pin mapping ALEMIXEDLIGO CEMEXSEDIIOT CLEMESEDIIOZ REMESEDIIOS RE MIZED1IO4 DOO MESEDIIOS DOT MEXEDTIIOS6 DOZ MEDLO e Info hps sys Peripheral EMACO pin mapping TS CLK EMA CIOD TXDO EMACIOT TEXDI EMACIO2 TSD EMA CIOS LXD3 EMACIOS3 RXDO EMACIOS MDIO EMACIOS MDC EMA 48 2015 Altera Corporation Public JAN DTE RYA e Linux HW SW Handoff Cyclone V SoC and Arria V SoC Qsys system info SDRAM calibration files D timestamp HPS IOCSR data Hardware Q Sa QUARTUS II system iswinfo system sopcinfo board info Preloader Device Tree Generator Generator ED Linux Software source files Device Tree u boot spl 49 2015 Altera Corporation Public Linux HW SW Handoff Arria 10 SoC Different DTBs Regenerate when HW project is recompiled Handoff Folder Bootloader DTBlob Bootloader P DT Source J Regene
52. y Kernel org U Boot other for the SoC FPGA architecture Kernel arch arm mach socfpga upstream U Boot altera socfoga_cycloned Being a maintainer means We upstream the SoC related code We control the changes against the SoC code requested by the community See kernel org and git denx de Repo git Other community contributions Device Tree Generator sopc2dts Customers amp Partners Yocto meta altera layer Contributors 81 O 2015 Altera Corporation Public SOCFPGA Linux Code Repositories on GitHub lt Public git repos for SOCFPGA httos github com altera opensource M le rated fro M Rocket Boards we C GitHub Inc US https github com altera opensource Rocketboards org git repos are GitHub Explore Fates En no longer updated Altera Opensource http rocketboards org Filters linux socfpga C 4 1 Linux development repository for socfpga Updated 6 hours ago meta altera BitBake 0 10 Yocto Layer for SoCFPGA Angstrom specific branches Updated 3 days ago angstrom socfpga Shell 0 po Angstrom repository with updated layers file 82 O 2015 Altera Corporation Public JAN DTE RYA e 83 SOCFPGA Linux Code Repositories on GitHub linux socfpga git SOCFPGA Linux development repository Mirrors kernel org linux repo releases Downstream branches for socfoga specific patches and updates meta altera
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