DE2 Development and Education Board User Manual
Contents
1. itiati ze t CPLD Initiation b DLY2 end Detector TD VS TD VS punc aso BE z aa Seguence mE IET TV YUV 4 2 2 rana Decoder a Pi ITU R 656 TD DATA Mana 7180 YUV 4 4 4 Data Valid Decoder 8 DC SCLK DC SCLK tp eech DC SDAT I2C SDAT Config sa el to an din RGB Le LC Len RGB Controller LCD HD r m LCD HD TDM LCD HD Touch gt To ontroller ll l LCD_VD LCD_VD EE LCD VD Ee pm Figure 5 7 Block diagram of LCD TV design Demonstration Setup File Locations and Instructions e Project directory MTDB LCD TV e Bit stream used MTDB LCD TV sof e Connect a DVD player s composite video output yellow plug to the Video IN RCA jack J11 of the MTDB board The DVD player has to be configured to provide o NTSC output o 60 Hz refresh rate o 4 3 aspect ratio o Non progressive video e Connect the audio output of the DVD player to the line in port of the MTDB board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert it to the mini stereo plug supported on the MTDB board this 1s the same type of plug supported on most computers e Load the bit stream into FPGA on the Cyclone III Starter board e Press BUTTONI on the MTDB board to reset the circuit 47 MTDB User Manual Dt Ik Line Out Lin2. AUD ADCDAT AUD ADCLRCK 11 Clock Audio CODEC ADC LR HC AUD ADCLRCK HC l2C SDAT Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level HC DC SCLK translator chip U10 4 6 RS 232 Serial Port The MTDB board uses the ADM3202 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver please refer to the datasheet which 1s available in the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site Figure 4 8 shows the related schematics and Table 4 8 lists the HSMC pin assignments U5 UART RXD lt UART TXD 2 C27 pF RXD M1 YA LEDR R75 330 UART RXD Mee eg LEDG Se 330 UART TXD R1OUT R2OUT T1IN T2IN T2OUT 1U ADM3202 VCC GND C1 C2 V V C29 C30 i Figure 4 8 ADM3202 RS 232 schematic 30 MTDB User Manual Table 4 8 RS 232 pin assignments ERE HC UART RXD ns es UART RXD U5 12 UART Receiver HC UART TXD Me me UART TXD U5 11 2 UART Transmitter Notes 1 U5 12 connects to pin 3 on the RS 232 connector J6 via U5 13 2 U5 11 connects to pin 2 on the RS 232 connector J6 via U5 14 4 7 PS 2 Serial Port The MTDB includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 9 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard ca
3. www terasic com Terasic Multimedia Touch Panel Daughter Board MTDB V2 0 User Manual Preliminary Version 2 00 Copyright 2009 Terasic Technologies Inc Terasic Multimedia Touch Panel Daughter Board Chapter 1 The e EET TID E TM 1 1 1 CAS COINS E l 1 2 KEE EE eege 2 Chapter 2 MTDB Hardware Specification eege ana ee ENEE 3 21 eu EE 3 22 Block Dao cai Or he MIDE aa aa mn nasa 6 Chapter MIDB Bus Controller hee bea 10 3 1 MIDB B s Controller Introd cHON ko one i 10 32 Block Design of the MIDE Bus COntrOl let konon na nb ER ue Reto san 10 3 3 Timing Protocol of the LCD TDM Controller on 11 3 4 Level Translators and MAX II Mode Control Register ccccceseeessecceceeeeeaeseseeeeeees 12 Chapter 4 0 ine the MEDE ee 20 4 1 Configuring the Cyclone III Starter Board nana 20 4 2 Connecting MTDB Board with the Altera DE3 Board 21 4 3 Using the 45 LCD Touch Panel Module o ooo omoocc coommmemmkmemuamuka smua 21 E ZEE TS NG ee 26 GC Using Tie o SIE 8 1DIS S 20 4 6 I2 02 Setia PORE oat HE CONDES LOCI mmm naas besi 30 4 7 P2 Sena Polls dm UM MENU DIUINUM Nb 3l 4 8 Ethernet Physical Layer TEAOSCE DIVER o ooooooo oo foro women Eed teca eoi eua 32 4 9 RSA WT BI eos E A O E E 33 TAO PEE Serial EEPROM E 35 E SI Gara Int ORE 35 4 12 General Purpose I O Connector Mode 1 and 2 only oo oo XX 37 Chapter 5 Examples of Advanced Demonstration oooooooooooooooooooo
4. Interface 143 D18 U6 15 Chip Select Input AD7843 Serial Interface 122 A oo U6 12 Data Out HC ADC PENIRQ n U6 11 AD7843 pen Interrupt HC ADC BUSY U6 13 AD7843 Serial Interface Busy Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip U11 M3 ADC PENIRQ n M2 e e e e gt JI ag zip g 3 g Ce Cc Z lt 3 I SS I E I SP I Se Se g g K gt gt gt gt We We Q UO UO UO UO UO O JJ O O O O gt m m Z CD UO O UO UO A CH We 5 O C r m A LN es o IS 25 MTDB User Manual 44 Using VGA The MTDB includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone III FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC is used to produce the analog data signals red green and blue The associated schematic 1s given in Figure 4 5 VGA AVCC VGA RIO 9 C Merr R68 47K VGA B D CSS eee rz ba hapa Rape belied LI L L LL let let leet let RSET R69 560 9SSISISESISISISSg BC43 BC44 0 1U 0 1U VGA GO VGA G1 VGA G2 VGA R VGA G3 4 88 5 VGA_G VGA_G4 32 VGAB VGA G5 e p VGA G6 ADV7123 e VGA G7 e o T R70 R71 R72 Tel VGA G8 9 23 VGA G9 0 75 75 75 ol VGA BLANK a3 s VGA SYNC K bw VGA AGND VGA AGND VGA AGND VGA HS R73 47 SNGAVS R74 47 aa b VGA A
5. Ri Pe R2 LE Ke C31 H3 EE VCC33 R4 LI 202 CGH R5 IE cu R5 10K HVDE R6 34 C33 R7 E R59 A10K SDA WAN poor ee TP AGND 37 R6 10K ADC PENIRQ n di svo VDDN 3 vecs3o _ HVDE 5 R6 10K ADC CS n GREST C35 STBY EE R6 10K SCEN VDDP m T 22 goe ADC DCLK 43 DA L PPN EE C42 10N B FB G X RIGHT 37 BA VCC330 VMP C43 10N VMN Y TOP C38 CH Sa VMP C12 C44 10N CGL X LEFT C39 Y TOP VMN X LEFT C45 10N Y BOTTOM X RIGHT Y BOTTOM BON er c D5 PMEG2010ABE LED B O LED Bo FPC 60B_CONNECTOI Figure 4 4 Schematic diagram of the LCD Touch Panel Module Table 4 3 Pin assignments for the LCD Touch Panel Module MTDB User Manual G 1 20 LCD green data bus bit 1 T 12 LCD blue data bus bit 2 2 T s s s T 7 T LCD 3 Wire Serial Interface 3 2 DIS HC LCD DATA 2 151 C16 esch 2 1 R 3 HC LCD DATA S 126 D13 2 3 B 3 3 HC LCD DATA 4 128 D15 2 G 4 esch B 4 3 R 5 HC LCD DATA B 146 B15 1 G 5 2 B 5 HC LCD DATA 6 1150 B14 3 G 6 2 R 7 HC LCD DATA 7 152 A15 3 G 7 1 BI7 2 GREST SCEN D no Enable wesch A AK UJ O h ch oo C2 50 U11 5 1 J10 44 LCD 3 Wire Seriallnterface Data AN C sch lt I AD7843 LCD 3 Wire Serial 157 B18 C3 ADC DCLK U6 16 Interface Clock AD7843 Serial Interface 155 B16 NO U6 14 Data In AD7843 Serial
6. Supports Auto MDIX for 10 100M Serial ports e One RS 232 port e One PS 2 port e DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the MTDB board MTDB User Manual I2C serial EEPROM e Use one 128 bit EEPROM e Supports 2 wire serial interface I2C compatible General Purpose I O e 8 general purpose I O pins as well as 3 3 volt power and ground line MTDB User Manual Chapter 3 MTDB Bus Controller The MTDB comes with a bus controller that allows user to access all components on the board through the HSMC connector without being limited by the number of user I Os of the HSMC connector This chapter describes its structure in block diagram form and finally describes its capabilities 3 1 MTDB Bus Controller Introduction The two major functions of the MTDB Bus Controller are listed 1 Provide time division multiplexing functions to the LCD and VGA color data bus 2 Provide level shifting feature for the 2 5 V Cyclone III FPGA and 3 3V the MTDB side domains 3 2 Block Design of the MTDB Bus Controller Figure 3 1 shows the block diagram of MTDB Bus Controller Both the LCD and VGA TDM blocks are simple 8 bit to 24 bit and 10 bit to 30 bit data de multiplexing functions respectively which are final logic driving the LCD panel and VGA DAC In the LCD TDM block the 8 bit input data successive BGR color data comes in at 3 times the rate of the 24 bit output data b
7. U12 3 U12 18 SD DAT2 SD 4 bit Data MAXII Mode Control Register 1 SD 4 bit Data2 MAXII Mode Control Register 1 36 MTDB User Manual 4 12 General Purpose I O Connector Mode 1 and 2 only The MTDB v2 0 includes a standard GPIO header J13 When the Mode Control Register in the MAX II device 1s set to 1 there are 8 pins available When it 1s set to 2 there are two pins available see Level Translators and MAX II Mode Control Register or Appendix When the Mode Control Register is set to 0 the GPIO Header pins are disabled Table 4 14 shows the pinout of General Purpose I O Connector Mode 1 and 2 Only with HSMC connector Table 4 14 General Purpose I O Connector Mode 1 and 2 only Pinouts HC TD D2 e uma U12 17 DBG D2 J13 5 GPIO data pin 2 Mode Control Register 1 HC TD D3 e U12 5 U12 16 DBG D31J13 6 GPIO data pin 3 Mode Control Register 1 HC TD D4 U12 6 DBG D4 GPIO data pin 4 Mode Control Register 1 HC TD D5 12 7 U12 14 DBG D5 J13 8 GPIO data pin 5 Mode Control Register 1 J13 DBG DO DBG D1 IER DBG D2 o l e DBG p3 Si DBG D4 e a DBG D3 DBG D6 g 5o l 10 DBG D7 ag Debug Connector Figure 4 14 General Purpose I O Connector Schematic MTDB User Manual Chapter 5 Examples of Advanced Demonstration This chapter provides a few examples of advanced circuits implemented using MTDB and a Cyclone III Starter board These circuits provide demonstra
8. folder of the MTDB System CD ROM or from the manufacturers web site 24LCOO Figure 4 12 I2C Serial EEPROM schematic Table 4 12 I2C Serial EEPROM pin assignments noi osc jm o je pn e EEPROM 20 Cio einer a be Ps Decor s eeprom 12C Dat 4 11 SD Card Interface The MTDB includes a SD card socket and provides both SPI and SD 4 bit mode for SD Card access Instructions for using SD card can be found by performing an appropriate search on various educational web sites The SD Card can also be accessed in 4 bit mode when the Mode Control Register in the MAX II Device is set to 1 see Level Translators and MAX II Mode Control 35 MTDB User Manual Register and Appendix Figure 4 13 shows the schematic of the SD card interface and the associated pin assignments are listed in Table 4 13 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 Q Q Q Q R38 R39 R42 R79 R80 4 7K 4 7K 4 7K 4 7K 4 7K lt 8D DAT2 2 SD DAT3 dL Lear oS SD CMD pc 2 CND ERE SD Card Socket Figure 4 13 SD card interface schematic Table 4 13 SD card interface pin assignments HC_SD_DAT3 153 me pe jaan DAT3 al aa i SD 1 bit Mode Card Detect SD 4 bit Mode Data3 SPI Mode Chip Select Active Low SD 1 bit Mode Command Line SD 4 bit Mode Command Line SPI Mode Data In SD 1 bit Mode Data Line SD 4 bit Mode DataO SPI Mode Data Out HC SD DAT U10 8 RE SD DAT HC TD DO U12 1 U12 20 SD DAT 1 HC TD D1
9. pin package 4 3 800x480 LCD Touch panel Module and Touch Screen Digitizer e Equipped with Toppoly TDO43MTEA1 active matrix color TFT LCD module e Uses the Analog Devices AD7843 touch screen digitizer e Support 24 bit parallel RGB interface e 3 wire register control for display and function selection e Built in contrast brightness and gamma modulation MTDB User Manual SD card socket e Accessible as memory in both SPI and 4 bit SD modes Clock inputs e 100 MHz oscillator Audio CODEC e Wolfson WM8731 24 bit sigma delta audio CODEC e Line level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 140 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector NTSC PAL Video decoder circuit e Uses the ADV7180 Multi format SDTV Video Decoder e Supports worldwide NTSC PAL SECAM color demodulation e One 10 bit ADC 4X over sampling for CVBS e Supports Composite Video CVBS RCA jack input e Supports digital output formats 8 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD e Applications DVD recorders LCD TV Set top boxes Digital TV and Portable video devices Ethernet Physical Layer Transceiver e Uses the DP83848C Single Port 10 100M Ethernet Physical Layer Transceiver e Supports both 100Base T and 10Base T Ethernet protocols e
10. the HSMC connector are limited users need to multiplex the VGA synchronization signals and RGB data to fit the input timing specification of the VGA TDM block as mentioned in Section 3 3 26 MTDB User Manual Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder of the MTDB System CD ROM The pin assignments are listed in Table 4 6 An example of code that drives a VGA display 1s described in Sections 5 2 and 5 3 Back porch b Front porch d HA Display interval c lt DATA HSYNC Ce i Figure 4 6 VGA horizontal timing specification Table 4 4 VGA horizontal timing specification wes sea Pas io faa oe eo ewm emo v6 22 ve 16 vmm seem mem o2 22 a ama Dmm men perpe KSR owe mem e es se ne onem Deme omm a pe per er e ree 2e0rto2a eora 1280x102 CARE 108 2806 Table 4 5 VGA vertical timing specification oe wem 1 am wem a e 1 ae wem s ww 1 xw eme s m mm 5 men meme s m mm fs 27 MTDB User Manual Table 4 6 ADV7123 pin assignments 1 N16 ex C1 lt HC VGA DATA 0 4 JJ 7 lt 7 HC_VGA_DATA 1 Oo zl M16 4 1 N HC VGA DATA 2 M18 3 6 HC VGA DATA 3 M17 2 lt lt LI lt LI I SI IISI SISI lt OIOI OI OIOI QO QO OI O
11. GA HS DAC ontroller VP VGA_VS VGA_VS Controller VGA VS ae Figure 5 9 Block diagram of LCD TV design Demonstration Setup File Locations and Instructions e Project directory MTDB VGA TV e Bit stream used MTDB VGA TV sof e Connect a DVD player s composite video output yellow plug to the Video IN RCA jack J11 of the MTDB board The DVD player has to be configured to provide o NTSC output o 60 Hz refresh rate 49 MTDB User Manual o 4 3 aspect ratio o Non progressive video Connect the audio output of the DVD player to the line in port of the MTDB board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the MTDB board this 1s the same type of plug supported on most computers Load the bit stream into FPGA on the Cyclone III Starter board Press BUTTONI on the MTDB board to reset the circuit yee w Line Out Line In Audio Output CVBS S Video YPbPr Output Video In VGA Out Figure 5 10 The setup for the VGA TV demonstration 50 MTDB User Manual Chapter 6 Appendix 6 1 EEPROM and Mode Switch Utility Starting the EEPROM and Mode Switch Utility HMB2 CONFIG exe A common utility application is provided that allows you to change the EEPROM data or the Mode Control Re
12. GND VGA CLOCK VGA BO VGA B1 VGA B2 VGA B3 VGA B4 VGA B5 VGA B6 VGA B7 VGA B8 VGA B9 O VGA_AVCC Figure 4 5 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 6 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next Async pulse coming up The timing of the vertical synchronization vsync is same as shown in Figure 4 6 except that a vsync pulse signifies the end of one frame and the start of the next The data refers to a set of rows in the frame horizontal timing Table 4 4 and Table 4 5 show the durations of time periods a b c and d for both horizontal and vertical timing at different resolution Since the number of user IOs of
13. HC HD 0 gt 1 or 1 gt 0 coincide with the presentation of BLUE color on the HC_LCD_DATA input The GREEN and RED values for that same pixel are presented on the next two clock cycles Figure 3 3 shows the timing information from the output side The LCD TDM block will generate a NCLK clock and 24 bit RGB data to the LCD panel The NCLK signal runs at 1 3 frequency of the incoming clock HC_NCLK In addition the timing protocol of the VGA TDM controller is very similar to the LCD TDM controller The input color data bus HC_VGA_DATA changes from 8 bit to 10 bit and the VGA TDM controller uses the HC_VGA_HS to determine the position of the BLUE color sample MTDB User Manual HC HD N Figure 3 2 The timing diagram shows the input side of the VGA TDM Controller HC NCLK LCDR G B Color data HD VD DEN Syne Sienn HD VD DEN HD VD DEN NCLK fo Figure 3 3 The timing diagram shows the output side of the LCD TDM Controller 3 4 Level Translators and MAX II Mode Control Register Bidirectional level shift interface U10 U11 U12 There are 3 bidirectional level shifters on the board U10 U11 and U12 These chips are all Texas Instruments TXBO108 or TXBO104 devices U10 is used completely as bi directional level shifters from 2 5V input Cyclone III FPGA to 3 3V required by many of the interface chips U11 and U12 however are also used to multiplex signals based on the setting of the mode select logic regist
14. JI OJO gt gt gt gt gt gt gt a gt gt gt D Di Wy OI DIVJI OIDI wl OO JI o w INININISlaA1l IOlOol oOo 13 HC VGA DATA 4 77 L17 HC VGA DATA B 79 L18 HC VGA DATA 6 83 L16 HC VGA DATA 7 85 K16 P10 HC VGA DATA 8 K18 R10 Hc vea DATAS Jar lie sn fo or bk T YT M NJ CO B9 Was red data bus bit 0 1 14 40 VGA red data bus bit 1 2 VGA green data bus bit 1 15 VGA blue data bus bit 1 41 VGA red data bus bit 2 3 VGA green data bus bit 2 16 VGA blue data bus bit 2 42 VGA red data bus bit 3 18 VGA blue data bus bit 4 lt lt Q MD gt gt S c o CO D o Q o 2 ET D c CT o c oO o gt CT eo eo 44 VGA red data bus bit 5 VGA green data bus bit 5 19 VGA blue data bus bit 5 45 VGA red data bus bit 6 7 VGA green data bus bit 6 20 VGA blue data bus bit 6 46 VGA red data bus bit 7 VGA green data bus bit 7 2 1 VGA blue data bus bit 7 AA NJ VGA red data bus bit 8 VGA green data bus bit 8 2 2 VGA blue data bus bit 8 4 VGA red data bus bit 9 1 O VGA green data bus bit 9 2 oo VGA blue data bus bit 9 11 VGA BLANK 13 VGA Horizontal Sync Input 14 VGA Vertical Sync Input MTDB User Manual HC VGA CLOCK s ke e en CLOCK 24 Was TDM Clock 4 5 Using the 24 bit Audio CODEC The MTDB provides high quality 24 bit audio via the Wolfson WMS731 audio CODEC ENCoder DECoder This chip supports microphone in
15. K 13 Figure 3 5 Level Shift Interface Schematic MTDB User Manual Table 3 1 Device U11 Level Shift Interface Pinouts with HSMC Connector I2C data to audio codec and video HC DC SDAT DC SDAT U1 27 U8 33 decoder HC PS2 ox PS2 CLK PS2 CLK x6 res Clock OO umo HG res DAT rer pur a psi2 Data HC MDIO MDIO U2 30 Ethernet PHY Management Data I O SD 1 bit Mode Card Detect HC SD DAT3 SD DAT3 SD 4 bit Mode Data3 SPI Mode Chip Select Active Low SD 1 bit Mode Command Line 44 HC SD CMD E SD 4 bit Mode Command Line SPI Mode Data In SD 1 bit Mode Data Line 48 HC SD DAT Si l SD 4 bit Mode Data0 SPI Mode Data Out ET J044 LOD 3 Wire Seral trace Dat Bidirectional level shift interfaces and the Mode Control Registers In order to provide additional peripheral flexibility the MTDB provides the user with 3 separate pinout modes These modes as described in Table 3 2 affect the usage of the Video Decoder U8 the SD Card Connector J4 and the 10 pin GPIO connector J13 This section describes the mode configuration details and signals that are affected for each mode Chapter Appendix describes the EEPROM and Mode Settings tool used to change the mode register value Table 3 2 Device U11 Level Shift Interface Pinouts with HSMC Connector Video decoder in standard x8 operating mode SD Card in 1 bit Enabled 1 bit mode No GPIO 1 Video decoder disabled 8 GPIO available SD Card in 4 bit mode Disable
16. MAX II chip They pass through the MAX3378 level translator chip U10 4 9 Digital Video Decoder The MTDB is equipped with an Analog Devices ADV7180 VIDEO decoder chip The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal NTSC PAL and SECAM into 4 2 2 component video data which is compatible with 8 bit CCIR601 CCIR656 The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in the VIDEO decoder can be programmed by a serial I2C bus which is connected to the HSMC connector as indicated in Figure 4 11 The pin assignments are listed in Table 4 11 Detailed information of the ADV7180 is available in the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site 33 MTDB User Manual VCC33 O VCC18 AV VCC18 PV VCC18 O O O 48 0 1U C47 R63 1 74K J11 10N ID D 0 7 36 CVBS1 IN C49 0 1U s RN2 47 o o TDD RCA JACK 0 bs rey 9 LE Ss TD RESET So VM 5 TD D2 em Le SE EE C50 0 1U G 3 Bs aMMa 10 D4 C51 Paro 14 pu TD D5 pola qn yA EE 52 0 1U 0 1U P6 A e ID D7 ADV7180 jadi ab 28MHz R66 120 TD VS VS FIELD R67 120 TD HS LL IPC ADDRESS IS 0x40 VCC33 O GC SCLK L 2 196 SDAT E 28 63636MHz Figure 4 11 Digital VIDEO Decoder schematic Table 4 11 VIDEO Decoder pin assignme
17. abled and the multiplexing in the MAXII device is disabled This mode disables the signals from the video decoder U8 and provides the signals to all the SD Card J4 to run in 4 bit mode Also there are now 8 GPIO pins available on J13 Figure 3 7 shows the block diagram for this mode which is a subset of the block diagram shown in Figure 3 4 Table 3 4 shows the signals enabled to the HSMC connector 16 MTDB User Manual HC PS2 CLK HC PS2 DAT PS2 CLK PS2 DAT HC MDIO HC SDA HC DC HC DC SDAT MDIO SDA DC DC SDAT Bi Dir Level Shifter U10 SD DAT DAT3 CMD SD Card SD D 1 2 SD DAT 1 2 J4 WT 4 bit B BLS GPIO 2 7 U12 GPIO 2 7 GPIO GPIO 0 1 BLS GPIO 0 1 J13 U11 8 Pins HSMC J6 Enable Enable Mode Register Logic SD D 1 2 GPIO2 7 Video Decode U8 GPIO 0 1 TD VS HS iino MAX II U4 Figure 3 7 Block Diagram of Bidirectional Level Shift Interface for Mode 1 Table 3 4 Device U11 and U12 Level Shift Interface Pinouts with HSMC Connector in Mode 1 SD Card data bus signal 1 for 4 bit HC TD DO SD DAT 1 U12 20 mode SD Card data bus signal 2 for 4 bit HC TD D1 SD DAT2 U12 18 mode emt oap Uii GP datapin2 ow eme was wee see ow seme oeo wes eme ow emus was me seen 1 MTDB User Manual Bidirectional level shift interfaces for Mode 2 In mode 2 the bidirectional volta
18. ard e Switches and Pushbuttons Table 5 1 Usage of the switches and pushbuttons BUTTONs BUTTON 1 Reset Circuit Press BUTTON 2 Demo Music Mode BUTTON 2 Release BUTTON 2 PS2 Keyboard Mode BUTTON 4 Reset Keyboard e PS 2 Keyboard 43 MTDB User Manual 44 MTDB User Manual VGA Out Keyboard Input ARE TE rr TITI Li LED NEN Figure 5 6 The Setup of the Music Synthesizer Demonstration 45 MTDB User Manual 5 3 LCD TV Demonstration This demonstration plays video and audio input from a DVD player using LCD Touch panel module audio CODEC and one Video decoder on the MTDB board Figure 5 7 shows the block diagram of the design There are two major blocks in the circuit called 2C AV Config and TV to VGA The TV to VGA block consists of ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCrCb to RGB and VGA Controller As soon as the bit stream is downloaded into the FPGA on the Cyclone III starter board the register values of the Video decoder chip will be configured via the 2C AV Config block which uses the I2C protocol to communicate with the Video decoder chip on the MTDB board Upon the power on sequence the Video decoder chip will be unstable for a time period the Lock Detector 1s responsible for detecting this instability The TU R 656 Decoder block extracts YCrCb 4 2 2 YUV 4 2 2 video signals out of the TU R 656 data stream which is sent by the Vi
19. d 8 an Video decoder enabled but Vertical Sync VS and Horizontal Sync Enabled but no VS HS pins disabled 2 GPIO pins available others are disabled 2 1 bit or HS signals SD Card in 1 bit mode 14 MTDB User Manual e Bidirectional level shift interfaces for Mode 0 Mode 0 is the compatibility mode for the original version of the MTDB In this mode The bidirectional voltage level shifters U11 and U12 are disabled and the SD Card J4 has a 1 bit interface there no GPIO pins available on J13 and the video decoder U8 is enabled Figure 3 6 shows the block diagram for this mode which is a subset of the block diagram shown in Figure 3 4 Table 3 3 shows the signals enabled to the HSMC connector HC PS2 CLK HC PS2 DAT PS2 CLK PS2 DAT HC MDIO HC SDA HC 12C HC DC SDAT MDIO SDA DC l2C SDAT Bi Dir 5 Level Shifter U10 sp DAT DAT3 CMD BLS U12 BLS U11 6 Disable BER Mode Register Logic TD DO 7 TD VS HS Figure 3 6 Block Diagram of Bidirectional Level Shift Interface for Mode 0 TD D0 7 TD VS HS n ID I2C MTDB User Manual Table 3 3 MAXII Pinouts with HSMC Connector in Mode 0 LS Juss mos sp wegen LS EE E Dee ee Lx p e HC TD D4 Video decoder data4 ow reon Tue em nes toca rest e Bidirectional level shift interfaces for Mode 1 In mode 1 the bidirectional voltage level shifters Ull and U12 are en
20. deo decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the Video decoder is interlaced we need to perform de interlacing on the data source We used Frame Buffer and a field selection multiplexer MUX which is controlled by the LCD controller to perform the de interlacing operation Internally the LCD Controller generates data request and odd even selected signals to the Frame Buffer and filed selection multiplexer MU X The YUV422 to YUV444 block converts the selected YCrCb 4 2 2 YUV 4 2 2 video data to the YCrCb 4 4 4 YUV 4 4 4 video data format The YCrCb to RGB block converts the YCrCb data into RGB output The LCD Timing Controller block generates standard LCD sync signals LCD HD and LCD VD to the LCD TDM block The LCD TDM Controller block will take these sync signals and RGB data as input and multiplex these signals to the MAXII CPLD device on the MTDB board via the HSMC connector Finally the LCD TDM Controller block in the MAXII CPLD device will de multiplex the LCD RGB data and the sync signals before sending them to the LCD Touch panel module for display Figure 5 8 illustrates the setup for this demonstration 46 MTDB User Manual Cyclone III Starter Board MTDB Board DLYO To Control the Zorten Initiation e TD HS MAXII TD HS E
21. e In CVBS S Video Audio Output YPbPr Output Video In Figure 5 8 The setup for the LCD TV demonstration 5 4 VGA TV Demonstration This demonstration plays video and audio input from a DVD player using VGA output audio CODEC and one Video decoder on the MTDB board Figure 5 9 shows the block diagram of the design There are two major blocks in the circuit called 2C AV Config and TV to VGA The TV to VGA block consists of ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCrCb to RGB and VGA Controller As soon as the bit stream is downloaded into the FPGA on the Cyclone III starter board the register values of the Video decoder chip will be configured via the 2C AV Config block which uses the I2C protocol to communicate with the Video decoder chip on the MTDB board Upon the power on sequence the Video decoder chip will be unstable for a time period the Lock Detector 1s responsible for detecting this instability 48 MTDB User Manual The TU R 656 Decoder block extracts YCrCb 4 2 2 YUV 4 2 2 video signals out of the ITU R 656 data stream which is sent by the Video decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the Video decoder is interlaced we need to perform de interlacing on the data source We used Frame Buffer and a field selection multiplexer MU X which is controlled by the VGA controller to perform the de interlacing o
22. er Figure 3 4 shows the block diagram and signals for the combination of the HSMC connector the MAX II device and the level shifters Figure 3 5 shows the Level Shift Interface schematic Table 3 shows the pinouts of level shift interface with HSMC connector for U11 straight level shifting 12 HC PS2 CLK HC PS2 DAT ID GC Mode Register Logic TD DO 7 or 3 SD D 1 2 4 GPIO 2 7 E TD DO 7 TD VS HS or GPIO 0 1 IN d TD_VS HS MTDB User Manual PS2 CLK PS2 DAT HC MDIO HC SDA HC 12C HC DC SDAT MDIO SDA I2C DC SDAT Bi Dir Level Shifter U10 SD DAT DAT3 CMD SD D 1 2 SD DAT 1 2 PIO 2 7 BLS bs U12 GPIO 2 7 GPIO 0 1 BLS GPIO 0 1 U11 6 Enable Enable Figure 3 4 Block Diagram of Bidirectional Level Shift Interface and MAX II Control VCC25 VCC33 H U10 i HC_12C_SDAT lios Kn GC SDAT lt gt HC PS2 CLK HC PS2 DAT HC MDIO m m R HC SD DAT3 e lt _ gt HC SD CMD CG VCC25 VCC33 SR ee n u11 O SS VCCA VCCB OE onoi HC TD VS DBG D1 TXB010 3 1 HC_TD_Dj0 7 N DBG D 0 7 lt D BG ERE X B e 10 gt E ND VCC25 VCC33 id U12 TXBO194GYR R82 HC TD DO SD DAT 2 2K HC TD D1 SD DAT2 HC TD D2 DBG D2 HC TD D3 DBG D3 m HC TD D4 6 z 15 DBG D4 HC TD D5 DBG D5 HC TD D6 DBG D6 HC TD D7 9 gt 12 DBG D7 DBG ENT S eno 14 TXB0108 R78 N 2 2
23. f the EEPROM b WRITE Write the values shown in the EEPROM RAW section c Default Reset the valued in the EEPROM RAW section to a default set of values MTDB User Manual d Save to File Save the data read from the EEPROM to a file e Load from File Load values into the EEPROM RAW section Changing the Mode Control Register Setting in the MAX II device 5 By clicking on Get Mode button the value currently stored in the mode control register will be displayed 6 To change the mode select a different Mode Control Register value and then click the Set Mode button 6 2 Revision History Version Date Change Log 2007 11 28 Initial Version Preliminary V1 01 2007 12 15 Modify Figure 2 4 Figure 2 6 Modify Ch 5 1 V1 02 2008 5 15 Modify Table 4 3 Table 4 6 e Modify clock frequency of the VGA DAC V 2 0 0 2009 4 24 e Modify for HMB Hardware V2 0 53
24. ge level shifter U11 1s enabled allowing GPIO signals 0 and 1 to propagate to the GPIO Header J13 The complementary multiplexer in the MAX II device disables the vertical sync and horizontal sync signals from the video decoder chip U8 from propagating Also in this mode U12 is disabled thus GPIO signals 2 7 are not available on the GPIO header J13 but the complementary multiplexer in the MAX II device enables the propagation of the data bus signals 0 7 from the video decoder U8 to the HSMC connector J6 Figure 3 8 shows the block diagram for this mode which is a subset of the block diagram shown in Figure 3 4 Table 3 5 shows the signals enabled to the HSMC connector HC PS2 CLK HC PS2 DAT PS2 CLK PS2 DAT HC MDIO HC SDA HC I2C HC DC SDAT MDIO SDA I2C I2C SDAT BiDir O PC Level Shifter U10 SD DAT DAT3 CMD BLS U12 GPIO 0 1 BLS GPIO 0 1 U11 6 Disable Enable Mode Register Logic TD D0 7 K TD_DO 7 Figure 3 8 Block Diagram of Bidirectional Level Shift Interface for Mode 2 18 MTDB User Manual Table 3 5 MAX II and U11 Device Pinouts with HSMC Connector in Mode 2 LS Juss mos sp wegen LS EE E Dee ee Lx p e HC TD D4 Video decoder data4 ow rere wem wm foros 19 MTDB User Manual Chapter 4 Using the MTDB This chapter gives instructions for using MTDB and describes each of its IO devices The MTDB is designed for an Alte
25. gister value stored 1n the MAX II Device s user flash memory This appendix describes how to use this utility l Before using this tool make sure the USB cable is connected to between the development kit board and the host PC The EEPROM and Mode Switch Utility is located in the directory Tool HMB2 Configuration Utility in the MTDB System CD which can be download from http www terasic com downloads cd rom mtdb MTDB SYSTEM CD V2 0 zip To execute the program simply copy the whole folder to your host computer and launch the control panel by double clicking the HMB2 CONFIG exe Figure A 1 shows the switch tool as it 1s launched 51 EEPROM FEPROM SIZE EEPROM RAW Ir BYTES H WRITE E Detault cave to File Load from File SWITCH Set Mode C Mode U e Mode 1 Get Mode C Mode MTDB User Manual l Tasic Disconnect Exit Dead success Figure A 1 EEPROM SWITCH Utility 3 There should be a sof file in this directory HMB2 CONFIG sof that will automatically download into the FPGA and the application will display Connected when communications is established with the downloaded design If any error message is shown please check the power and USB cable then press Connect button to reconfigure FPGA Changing the contents of the EEPROM device 4 Using the buttons to the left of the EEPROM section of this utility you can a READ Read the current contents o
26. gt GND OUT 25MHZ VCC33 O C6 BC6 TXD O 3 L 10U 0 1U a RXD O 3 PFBOUT dl d gl od ld BC7 RX CLK R15 33 0 1U RX pv R16 33 EE weem E AGND Rx cns R17 33 P 4 PFBIN2 8 Rx CLK RX_ERR R18 33 1 4 RX DV MII MODE e p 0 1 CRS CRS DV LED CFG Rx coL R19 33 lt DP83848C Rei 33 E RXD1 2 RXD 3 PHYAD4 Vcc33 48 IOGND O R22 33 EE IOVDD33 L PWR DOWN INT RXD3 R23 33 gt TXD 3 SNI MODE TX CLK R31 33 TXDO R33 33 TXD1 R34 33 TXD2 R35 33 TXD3 R36 33 TX EN R82 33 R37 ETH RESET N Lei ACT R12 120 ACTIVITY ACTIVITY SPE R13 120 SPEED 100Mbps LEDR DUPLEX DUPLEX R14 1K ei ovcc33 DUPLEX PFBOUT zT C7 BC8 ud Zu 10U 0 1U ds 99 R24 4 7K E RBIAS 2 PFBOUT GN T CUN na 5 D SEH BC10 0 1U Q 2 E AGND 17 DE AG 16 K E AGND R27 R28 R29 R30 49 9 49 9 49 9 49 9 BC12 BC13 0 1U 0 1U E AGND E AGND TD K 4 z 14 T s2 el PSA NY E AGND OE_AVCC33 gun es E AVCC33 O D3 ACTIVITY YELLOW D4 D2 m SPEED z Di GREEN 72 D RJ45INTLED E AVCC33 Geng 0 1U 0 1U E AGND Figure 4 10 Fast Ethernet schematic Table 4 10 Fast Ethernet pin assignments P2 TXD3 e MII Transmit Data bit 3 T3 Eth RESET N DP83848C Reset MTDB User Manual HC MDIO U10 5 1 U10 16 1 MDIO Management Data IO ier a br ue 2 7577571539 xax pe pm je Ja ses EECHER E Notes 1 These signals do not go through the
27. he HSMC connector are limited the LCD RGB data and synchronization signals outputted to the MTDB board need to be multiplex to fit the input timing specification of the LCD TDM Controller on the MTDB board as mention in the Section 3 3 Finally the associated schematic of the LCD touch panel module is given in Figure 4 4 and the pin assignments are listed in Table 4 3 Detailed information for using the LCD panel and AD7843 are available in their datasheets which can be found in the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site 2l MTDB User Manual Dos si ra IT NCLK RO R7 3 G0 G7 Valid Data B0 B7 3 Display Area Chop 3 tha tur 1 Horizontal Line t ep te 3 DEN Figure 4 2 LCD horizontal timing specification Table 4 1 LCD horizontal timing parameters HSYNC Pulse Width NCLK DEN Enable Time EE EE NCLK 22 MTDB User Manual RO R7 3 G0 G7 Display Area 3 1 Vertical Line tv 3 toe 3 Figure 4 3 LCD vertical timing specification Table 4 2 LCD vertical timing parameters 23 MTDB User Manual H O 7 VCC33 U6 G 0 7 ADC_DCLK CGH Fi et gU SPO rn Hl ADC CS n g CPL2 X RIGHT SM X LEFT ADC DIN 6 s id lt LO Y_TOP ADC BUSY DEN a ADC_DOUT BO 25 B1 ESCH ADC PENIRQ n B2 B3 gt U7 B6 AD7843 V B7 TRI GO G1 G2 G3 G4 G5 G6 G7 6
28. line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial DC bus interface which is connected to the HSMC connector A schematic diagram of the audio circuitry is shown in Figure 4 7 and the pin assignments are listed in Table 4 4 Detailed information for using the WMS731 codec is available in its datasheet which can be found in the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site Since the direction of the signals HC AUD ADCLRCK HC AUD DACLRCK and HC AUD BLCK in the MAX II CPLD are from HSMC connector to the WM8731 codec the WMS731 codec only works in Slave mode If users need the WM8731 codec working in Master mode they can modify the direction of the HC AUD BCLK in the MAX II CPLD RTL code which can be found in the MTDB Bus Controller default folder on the MTDB System CD ROM VCC33 VCC33 O O w Sg AGND AGND GC SDAT PSK I2C SCLK R6 330 al tc e O o z od o 4 C3 2m PHONE JACK P R7 680 C4 10U K AA a AGND C5 R8 AGND OA VCC33 IN 47K EFA AGND AGND O A VCC33 W e AGND AGND Figure 4 7 Audio CODEC schematic 29 MTDB User Manual Table 4 7 Audio CODEC pin assignments Audio CODEC HC AUD BCLK Bit Stream Clock Audio CODEC Chip HC AUD XCK Clock HC AUD DACDAT AUD DACDAT 109 HC AUD i 8 Audio CODEC DAC Data Audio CODEC DAC LR Clock Audio CODEC ADC Data
29. ling the BYPASS and SITETONE functions in the audio chip Finally users can obtain the status of the SD music player from the 2x16 LCD module the 7 segment displays and the LEDs The top and bottom row of the LCD module will display the file name of the music that is playing on the DE2 70 board and the value of music volume respectively The segment displays will show how long the music file has been played The LED will indicate the audio signal strength Demonstration Setup File Locations and Instructions e Project directory MTDB SD Card Audio e Bit stream used MTDB SD Card Audio sof e Nios II Workspace MTDB SD Card Audio Software e Format your SD card into FAT 6 format e Put the played wave files to the root directory of the SD card The provided wave files must have a sample rate of 96 48 44 1 32 or 8 KHz In addition the wave files must be stereo and 16 bits per channel Furthermore the file name must be short filename 40 MTDB User Manual Execute the demo batch file sdcard audio bat The batch file is located in the folder MTDB SD Card AudiofDemo Batch Insert the SD card LED2 will be flashing when the SD card is not inserted in SD card socket LED will be flashing while the demonstration is playing music Connect a headset or speaker to the DE2 70 board and you should be able to hear the music played from the SD Card Press BUTTON on the Cyclone III Starter board will play the next music file
30. n be found by performing an appropriate search on various educational web sites The pin assignments for the associated interface are shown in Table 4 9 VCC5 VCC5 Q Q R53 R54 2K 2K PS2_DAT R56 120 PS2DAT SS PS2 CLK ena lt gt VCC5 O D3 D4 BAT54S BAT54S BC34 0 1U F Q VCC33 VCC33 Figure 4 9 PS 2 schematic Table 4 9 PS 2 pin assignments Tebe U10 3 U10 18 PS2 CLK U10 4 U10 17 PS2 DAT Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip U10 HC PS2 CLK HC PS2 DAT 31 4 8 Ethernet Physical Layer Transceiver MTDB User Manual The MTDB board provides Ethernet support via the National Semiconductor DP83848C Ethernet Physical Layer Transceiver chip The DP83848C is a one port Fast Ethernet PHY Transceiver supporting IEEE 802 3 physical layer applications at 10Mbps and 100Mbps The DP83848C provides Media Independent Interface MII to connect DP83848C to a MAC in 10 100M systems Figure 4 10 shows the schematic for the Ethernet Physical Layer Transceiver interface and the associated pin assignments are listed in Table 4 10 For detailed information on how to use the DP83848C please refer to its datasheet and application note which are available in the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site VCC33 O R11 VCC33 O 1 5K MDIO 4 MDC 0 1U EN VCC
31. nts Video Decoder Data Register 0 or 2 Video Decoder Register 0 or 2 Video Decoder Register 0 or 2 Video Decoder Register 0 or 2 Video Decoder i i i m d i i lt 4 4 POTE Register 0 or 2 Video Decoder Register 0 or 2 HC_TD_D 2 HC TD DI Video Decoder Data Register 0 or 2 Video Decoder Data7 Mode Control HC TD DIO c lt Register 0 or 2 U8 TD_27MHZ I2C Clock 34 HC TD 27MHZ zh AA MTDB User Manual HC TD RESET 80 J14 TD RESET 131 Video Decoder Reset HC l2C SDAT Mud 2 U10 20 1 l2C DATA de Data DEER l2C SCLK Ut feoso SCLK ou Video Decoder Clock Input Video Decoder V SYNC Mode Control HC TD VS TD VS Register 0 Video Decoder H SYNC Mode Control HC TD HS TD HS Register 0 Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip U10 4 10 I2C Serial EEPROM The MTDB uses a Microchip 128 bit I2C serial EEPROM to store the MAC address and the boundary parameters of the touch panel for the Ethernet operation and touch panel respectively The EEPROM is programmed by I2C serial Interface which is connected through the CPLD to the HSMC connector Figure 4 12 shows the schematic of the I2C Serial EEPROM and the associated pin assignments are listed in Table 4 12 Detailed information for using the UC EEPROM is available in its datasheet which can be found in the Datasheet
32. oller SSRAM LED Button Flash Figure 5 3 Hardware Block diagram of the SD card Music Player Demonstration Figure 5 4 shows the software stack of this demonstration SD 1 Bit Mod block implements the SD I bit mode protocol for reading raw data from the SD card The FAT16 block implements FAT16 file system for reading wave files that stored in the SD card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for receiving audio signal from wave files The I2C block implements I2C protocol for configuring audio chip The Audio block implements audio FIFO checking function and audio signal sending receiving function 39 MTDB User Manual Software Architecture WAVE RC FAT16 SDCARD IOWR IORD Figure 5 4 Software Block diagram of the SD Music Player Demonstration The audio chip should be configured before sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio interface as I2S with 16 bits per channel and sampling rate according to the wave file content In audio playing loop the main program reads 512 byte audio data from the SD card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program have to make sure the FIFO is not full The design also mixes the audio signal from the microphone in and line in for the Karaoke style effects by enab
33. ooo 0 0000 00 000 00 0 000oooooo 38 5 1 SD Card MUSIC BIA Y EE 38 0 2 Music Synthesizer Demonstra Om EE 42 5 3 LED IV D IODSLEOL rn E ONUS HET SUE 46 5 4 VOA PY Denon SICHERE nb 48 KREE 51 6 1 EEPROM and Mode Switch ENER 51 EE ISTO BY Rc 53 MTDB User Manual Chapter 1 The Package The Multimedia Touch Panel Daughter board MTDB package contains all components needed for MTDB in conjunction with an Altera FPGA board with HSMC connector 1 1 Package Contents The MTDB package includes e The Terasic Multimedia Touch Panel daughter board e Optional Components to assemble the MTDB with a Cyclone III Starter Board into a BRICK format as shown in Figure 1 1 The detailed instructions on how to assemble MTDB with a Cyclone III Starter board into a BRICK format can be found in the Cyclonelll Starter Board BRICK folder of the MTDB System CD ROM Figure 1 1 The BRICK form of combining the MTDB to an Altera Cyclone III Starter Board 1 2 Here are the addresses where you can get help if you encounter problems Getting Help Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web www terasic com MTDB User Manual MTDB User Manual Chapter 2 MTDB Hardware Specification This chapter presents the features and design characteristics of the MTDB hardware 2 1 Layout and Components A photograph of the MTDB is shown in Figure 2 1 Figu
34. peration Internally the VGA Controller generates data request and odd even selected signals to the Frame Buffer and filed selection multiplexerr MU X The YUV422 to YUV444 block converts the selected YCrCb 4 2 2 YUV 4 2 2 video data to the YCrCb 4 4 4 YUV 4 4 4 video data format The YCrCb to RGB block converts the YCrCb data into RGB output The VGA Timing Controller block generates standard VGA sync signals VGA HS and VGA VS to the VGA TDM Controller block will take these sync signals and RGB data as input and multiplex these signals to the MA XII CPLD device on the MTDB board via the HSMC connector Finally the VGA TDM Controller block in the MAXII CPLD device will de multiplex the VGA RGB data and the sync signals to enable the display on a VGA monitor Figure 5 9 illustrates the setup for this demonstration Cyclone III Starter Board MTDB Board DLYO To Control the a py Initiation ees TD HS MAXII TD HS 4 amp TT lies Ee amp CPLD Initiation DLY2 gd Detector TD VS TD VS Sequence X TV YUV 4 2 2 rana Decoder C dius ITU R 656 TD DATA TD DATA 7180 YUV 4 4 4 en Data Valid Decoder a RC SCLK DC SCLK w awe ea I2C SDAT I2C SDAT Config E YCbCr VGA To 10 bit RGB Timing VGA VGA VGA RGB TDM i Controller VGA_HS am VGA HS TDM V
35. ra FPGA board with a HSMC connector The demonstration projects illustrated here are using MTDB with the latest Cyclone III Starter Board 4 1 Configuring the Cyclone III Starter Board The procedure for downloading a circuit from a host computer to the Cyclone III Starter board is described in the Cyclone III Starter Kit User Manual This tutorial is found in the Cyclonelll Starter Kit folder on the MTDB System CD ROM and it is also available on the Altera Cyclone III Starter Kit web pages User 1s encouraged to read the tutorial first and to treat the information below as a short reference Figure 4 1 illustrates how to connect your MTDB to a Cyclone III Starter board To download a configuration bit stream into the Cyclone III FPGA perform the following steps e Ensure that power is applied to the Cyclone III Starter board e Connect the supplied USB cable to the USB Blaster port on the Cyclone III Starter board e The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension Figure 4 1 Connection of a MTDB Board and a Cyclone III Starter Board 20 MTDB User Manual Users can find the default demonstration project under the Demonstrations default folder in the MTDB System CD ROM Users are also encouraged to examine the top level RTL code when reading the following sections 4 3 Connecting MTDB Board with the Altera DE3 Board To connec
36. re 2 2 Figure 2 3 Figure 2 4 and Figure 2 5 These pictures depict the layout of the board and indicate the location of the connectors and key components Figure 2 1 The MTDB Top View MTDB User Manual Figure 2 2 The MTDB Connector view 1 en amp 6 Figure 2 3 The MTDB Connector view 2 MTDB User Manual Mic in Linein Line Out Videoin VGA Video Port RS 232 Port PLE T 3 O VGA 10 bit DAC z iv gt UA J emm D A J Qing aint A fz 32 wis 3 nn DEE x w i J E qune Gemeng E ce 1003 om amp 4 GPIO Header 24 bit Audio Codec ue my c iila u S S oe xix LUE Setan an i Video Decoder 64 is NA E NTSC PAL a Ethernet 10 100M Port Altera MAX II 2210 CPLD device d SD Card Slot M 4 PS 2 Keyboard Mouse Port ler PAT Kee wiw terasic com ag eman 221 200048 PO 08080145 Ethernet 10 100M PHY 100 MHz Oscillator LCD Touch Panel Connector EEPROM Figure 2 4 The MTDB PCB and Component diagram 00000 Kul 2 gt Jof d Ka 53 iz PERANAN pum OO SSES ER H e an L d e ELI SS Le Leet Ss HSMC Connector Hi Kr KI Cp E eee pn or on en on ee i n le iS es PAL 853 KE 29 3M Y4V U verse C359 4017 Figure 2 5 The MTDB Back side HSMC connector view MTDB User Manual The MTDB board has many features that allow users to implement a wide range of designed circuits from
37. sic files are stored in an SD card and the board can play the music files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music Figure 5 3 shows the hardware block diagram of this demonstration The system requires a 50MHz clock provided from the board The PLL generates a 100MHz clock for NIOS II processor and the other controllers except for the audio controller The audio chip is controlled by the Audio Controller which is a user defined SOPC component This audio controller needs an input clock running at 18 432 MHz In this design the clock is provided by the PLL block The audio controller requires the audio chip working in master mode so the serial bit BCK and the left right channel 38 MTDB User Manual clock LRCK are provided by the audio chip Two PIO pins are connected to the I2C bus The I2C protocol is implemented by software Four PIO pins are connected to the SD CARD socket SD 1 Bit Mode is used to access the SD card and is implemented by software All of the other SOPC components in the block diagram are SOPC Builder built in components JTAG UART is added for debug and shows prompt messages for this demonstration Cyclone III Starter Board MTDB Board SD CARD NIOSH Lu PIO gt Socket Processor Controller ml PIO DC 4 i MAC In Controller I Controller 214q8J YDJIMS UOJBAY Memory Contr
38. simple circuits to various multimedia projects with touch panel applications The following hardware is provided on the MTDB board Altera MAX II 2210 CPLD device SD Card socket 100 MHz oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in jacks VGA DAC 10 bit high speed triple DACs with VGA out connector Video decoder NTSC PAL SECAM and TV in connector 10 100M Ethernet Physical Layer Transceiver RS 232 transceiver and 9 pin connector PS 2 mouse keyboard connector 800x480 Active matrix color TFT LCD Touch Panel module I2C Serial EEPROM General Purpose I O To use the MTDB the user has to be familiar with the Quartus II software 2 2 Block Diagram of the MTDB Figure 2 6 gives the block diagram of the MTDB To provide maximum flexibility for the user all connections are made through the HSMC connector device Thus the user can configure the FPGA on the mother board to implement any system design MTDB User Manual MAXII CPLD amp Level Shift 24 bit AUDIO CODEC VGA 10 bit Video Video decoder PS2 amp RS232 Ports HSMC gt BUS Connector d Controller LCD Touch Panel module 10 100 Ethernet PHY SD Card RC EEPROM GPIO Header gt e 100M Hz OSC Figure 2 6 Block diagram of the MTDB board Following is more detailed information about the blocks in Figure 2 6 MAX II 2210 CPLD e 2210 LEs e 272 user IO pins e FineLine BGA 324
39. stored in the SD card Press BUTTON3 and BUTTON4 will increase and decrease the output music volume respectively Akun Cyeinga Suri Board cc lb EAE T AE NN T c css SE W I aa eO el E is 1 aii TLLA m B E B ar e eg gi WW Sih a Hm 7 eae wa E with music files wav Figure 5 1 Setup of the SD Card Music Player Demonstration 41 MTDB User Manual sche E Ju salt v 08 ISS unt fua Wunn OO NT Mi a T m i Diet pem HUH TD ai Pi p Wana y S 8 ei ER H E D I 1 re Gi be SE vi WI st T T X d m ju am R e HE SN i H5 i E 4 v n Be e Knei S t Insert SDCARD t i Mh mumm E z Indicator i mW 2 i Play Indicator TUK mammen DN ER Hina ALL DR Ue HE RELON IGRE MEE BETTON OI d r e Volume Down Volume Up Next Song Figure 5 2 Man Machine Interface of the SD Music Player Demonstration 5 2 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using Cyclone III Starter board and MTDB board with a PS 2 Keyboard and a speaker PS 2 Keyboard is used as a piano keyboard for input The FPGA on the Cyclone III Starter board serves as a Music Synthesizer to generate music and tones The VGA connected to the MTDB board is used to display which key is pressed during the playing of the music Figure 5 5 shows the block diagram of
40. t the MTDB board with the Altera DE3 board please refer to the How to connect MTDB to DE3 pdf which can be availabe from the directory Using MTDB on DE3 in the MTDB SYSTEM CD 4 3 Using the 4 3 LCD Touch Panel Module The MTDB provides a 4 3 Toppoly TDO43MTEAI active matrix color TFT LCD panel The LCD Touch Panel module has the highest resolution 800x480 to provide users the best display quality for developing applications The LCD panel supports 24 bit parallel RGB data interface and provides 3 wire serial port interface to control the display function registers The MTDB Board is also equipped with an Analog Devices AD7843 touch screen digitizer chip The AD7843 1s a 12 bit analog to digital converter ADC for digitizing x and y coordinates of touch points applied to the touch screen Also the coordinates of the touch point can be read through the serial port interface on the AD7843 However because of limited IOs of the HSMC connector the clock signal of the serial port interface for the LCD panel and AD7843 share the same HSMC connector IO called HC ADC DCLK users must not control both LCD panel and AD7843 at the same time To display images on the LCD panel correctly the first thing users need to do is that the RGB color data and synchronization signals need to follow the timing specification of the LCD Touch panel as shown in Figure 4 2 Figure 4 3 Table 4 1 and Table 4 2 Further more because the number of user IOs of t
41. the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAFF and TONE GENERATOR The DEMO SOUND block stores a demo sound for user to play PS2 KEYBOARD handles the user input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s on the PS 2 Keyboard are pressed The TONE GENERATOR is the core of music synthesizer User can switch the music source either from PS52 KEYBOAD or the DEMO SOUND block using BUTTON2 Figure 5 6 illustrates the setup for this demonstration 42 MTDB User Manual Cyclone III Starter Board amp FPGA MTDB Board VGA HS DEMOI1 CODE VGA VS VGA CLOCK VGA R DEMO1 CODE VGA CG SEAL VGA B KEY1 CODE SOUNDI KEY1 CODE BUTTON2 Figure 5 5 Block diagram of the Music Synthesizer design Demonstration Setup File Locations and Instructions e Project directory MTDB Synthesizer e Bit stream used MTDB_Synthesizer sof e Connect a PS 2 Keyboard to the MTDB board e Connect the VGA output of the MTDB board to a VGA monitor e Connect the Line out of the MTDB board to a speaker e Load the bit stream into FPGA on the Cyclone III Starter board e Press BUTTON 1 on the Cyclone III Starter board to reset the circuit e Press BUTTON 2 on the Cyclone III Starter board to start the music demo Table 5 1 and 5 2 illustrate the usage of the switches pushbuttons BUTTONS and PS 2 Keybo
42. tions of the major features on the board such as its audio and video capabilities and SD card connectivity For each demonstration the Cyclone III FPGA configuration file is provided as well as the full source code in Verilog HDL code All of the associated files can be found in the MTDB demonstrations folder from the MTDB System CD ROM For each demonstration described in the following sections we give the name of the project directory for its files which are subdirectories of the MTDB demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory MTDB demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 5 1 SD Card Music Player Introduction Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality can be produced The Cyclone III Starter board and MTDB board provide the hardware and software needed for SD card access and professional audio performance so that it is possible to design advanced multimedia products using the Cyclone III Starter board and MTDB board In this demonstration we show how to implement an SD Card Music Player on the MTDB system in which the mu
43. us 8 bit B 8bit G 8bit R we drive to the LCD panel This function can reduce the pin count of the HSMC connector The I2C Bir bus block provides bidirectional control for I2C Serial EEPROM data bus 10 MTDB User Manual MAXII CPLD LCD Touch Panel amp AD converter LCD R data LCD Color Data Bus RGB LCD G data LCD TDM m Controller Bana LCD Timing Control Bus LCD Timing Control Bus LCD Touch Panel Module VGA R data VGA Color Data Bus RGB VGA G data virens zt pes m ontroller VGA Timing Control Bus VGA Timing Control Bus RC EEPROM Interface DC bir bus Controller EN Other uni directional I Os ode Register Logic Bi directional Level Translator U10 U11 VGA DAC HSMC Connector I2C EEPROM AUDIO DAC Ethernet PHY Bi directional I Os SD Card Soket RS232 PS 2 Ports Video Decoder GPIO Figure 3 1 The Block Diagram of MTDB Bus Controller 3 3 Timing Protocol of the LCD TDM Controller Figure 3 2 describes the input timing waveform information of the LCD TDM Controller The 8 bit wide HC_LCD_DATA signal is presumed to contain a stream of color pixel data with each pixel represented by three successive clock cycles of the stream The data is presented as BGR The LCD TDM Controller uses the HC_HD pulse to determine the position of the BLUE color sample and thus the start of each three clock pixel period State transitions on
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