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Z90230 Family of Digital Television Controllers User`s Manual

1. Figure 4 27 Smoothing Figure 4 27 shows a character a 1X 2X without smoothing and 2X with smoothing 4 6 3 Fringing Effect Fringing is surrounding a character with color different from the foreground and background colors as shown in Figure 4 26 Fringing adds Table 4 2 RGB Colors visual appeal to the character presentation The fringing effect is enabled or disabled in DISP_ATTR 03h Bank A 5 The fringing color 0 0 0 Black is INT ST 07h Bank C 7 to either 0 the 0 0 1 Blue character background color or to 1 a RGB color that is specified in INT_ST 07h Bank 6 5 4 0 L 0 Green The eight RGB colors available for fringing and 0 1 1 Cyan background are defined in Table 4 2 1 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White 4 22 UM97TELO700 Zilog Z90230 Family of DTCs On Screen Display 4 7 DISPLAY ATTRIBUTE CONTROL Display attribute control determines characteris tics of the screen display for the entire screen not just the OSD area The background that covers the entire screen is
2. Figure 4 23 Fade Position Register 2 Figure 4 24 Row Space Register Figure 4 25 Character Pixel Map in Example Figure 4 26 Icon Display 22 221 2222222 02 1 Figure 4 27 Smoothing pu diese cu Doe o Ob Deus Figure 4 28 Display Attribute Register Figure 4 29 VRAM Address Figure 4 30 Color Palette Selection Bits Update Figure 4 31 Color Index Register 1 4 UM97TELO0700 290230 Family of DTCs List of Figures PAGE Z90230 Family of DTCs List of Figures Zilog NUMBER AND TITLE PAGE Chapter 4 On Screen Display Continued Figure d 32 Color Palette D ds edad aen te ELE Eds qeu dus 4 25 Figure 4 92 Color Palette T ete o eratac laid ahd Soc 4 26 Fig re 4 34 Golor Palette 9 51 oodd eO oeque eed 4 26 Figure 4 35 Color Palette 3 2 ette te iioi tse eet v eov ge essa cece 4 26 Figure 4 36 Color Palette oo Mini n i umama ED d p un
3. Figure 0 26 Timer Control Register 0 Figure 0 27 Timer Control Register 1 Figure 0 28 IR Capture Register Figure D 29 IR Capture Register 1 Figure 0 30 Port 4 Data Register Figure 0 31 Port 4 Direction Control Register Figure 0 32 HV Interrupt Status Register UM97TELO0700 290230 Family of DTCs List of Figures PAGE Z90230 Family of DTCs List of Figures Zilog NUMBER AND TITLE PAGE Appendix D Registers Continued Figure 0 33 Port 4 Pin Out Selection Register ener D 16 Figure 0 34 Color Index Register 2 cccc ssesseeeseeeseeesceceeceeeceneeeeneeeeeeeneeeerenedeedseesdeensetesseeeees D 17 Figure D 35 Master 2 Data pice ame ne n n Sa na oer heed D 17 Figure D 36 Master IC Command Register D 17 Figure D 37 Master 2 Control aei ER D 18 Figure D 38 Port Configuration ROgISIer ti etx reete Redi ken D 19 Figure D 39 4 Bit ADC Data Register D 19 Figure 0 40 Port 6 Direction Control R
4. 2 26 Table 2 6 DO Characteristics zoe dicio cua 2 27 Table 2 7 AG Characteristics Ufo 2 28 Chapter 3 Internal Microprocessor Overview Table 3 1 Working Register Groups E re Do i 3 2 Table 3 2 Expanded Register File Bank 3 8 Table 3 3 Expanded Register File Bank B r 3 9 Table 3 4 Expanded Register File Bank C 88 3 9 Table 3 5 Expanded Register File Bank F 3 9 Table 3 6 Sample Control and Peripheral Register Reset Values 3 17 Table 3 7 Expanded Register File Bank 0 Reset Values at Reset 3 19 Table 3 8 Time Out Period of the WDT a 3 20 Table 3 9 Interrupt Types Sources and Vectors rr 3 31 TOs um n 3 34 Table 3 11 Interrupt Group Priority soc e 3 34 Table 3 t2 IRQ F ncti r SUMMARY E 3 36 Table 3 13 IRQ Register Configuration
5. 7 3 Timer Mode 3 25 Timer Mode Reset 3 29 Vertical Position 4 4 Reset aae ccrte federe eco eoe 3 18 Interrupt Conditions 3 41 IRQ Functional Logic Diagram 3 37 IRQ Register 3 35 Pin Internal 3 17 Power On Timer 3 21 Presealet 3 29 1 toad ee ro Se 3 28 Timer Mode Register 3 29 TAUNTING TEC 3 18 Values ERF Bank 3 19 Resonators 3 15 RETURN SS tas 3 11 Index 4 Zilog S Second Color usu el eles 4 5 Smoothing and Character Size 4 20 Stack Effects of Interrupt 3 38 Operations 3 11 Stop Mode Operation 3 41 Recovery Circuit 3 42 Recovery Prescaler 3 26 Recovery Register 3 42 Recovery Register and POR 3 21 Recovery Source 3 43 Symbols iiic ue 3 58 Synchronization Specification
6. D ee 3 4 3 3 Expanded e ep oor OR oix 3 5 3 4 Control and Peripheral Baglslers n ta e rq otro dh Da RE 3 8 3 4 1 Standard Registers te tp tee eee 3 8 3 4 2 Expanded M A A E 3 8 3 5 Program Memory TOT 3 10 S LACKS usus LI E M ML 3 11 STe PEE 3 12 3 8 3 12 3 9 1 tona Um ritate d stub AM 3 13 3 8 2 Indications of an Unreliable Design 3 13 3 8 3 Circuit Board Design Rules cree a bee ee Re 3 14 3 9 4 Grystals and HesoOllalOls pe rH I a AM CU MU Up tan E EOS 3 15 SEMESTER 3 16 9 TO HESET Waltch Dog Timer io eiae iet rb a ena eee t 3 16 3 11 Reset Pin Internal POR Operation 2 3 17 3 12 3 20 E 3 21 3 14 DITIGES e Deme qo pcne er 3 21 9 15 Prescalers and Cournter TIIierS 2 uu tub 3 22 3 16 Counter Timers Operation 3 24 3 16 1 Load and Enable Count Bits
7. 3 55 7 aa p Guau 3 54 PIGGISIEN sua 3 54 Settings Definitions 3 56 MEO FTN RM RPC FIT IRE 3 55 Zero 3 55 Frame Data Read Flowchart 5 9 Data Write Flowchart 5 8 PRICING eer 4 21 G General Purpose Registers 3 3 Global Interrupt Enable 3 35 H 5 Res 4 7 Halt Mode Operation 3 41 2 5 1 Data Transfer 5 1 Master Interface 5 3 Software Control 5 6 GE GRID 2 asya 2 4 Index 2 Zilog Infrared Decoding 7 5 Interface ERR xiva oss adus 7 1 Remote Control Interface 7 1 Initialization Code for IRQ Register 3 36 Instructions eas osa eure terae ts 3 53 Bit Manipulation 3 53 Block Transfer 3 53 CPU Control 3 54 Functional Summary of Instruction Set 3 52 Interrupt Return 3 34 3 53 3 5
8. de 3 37 Table 3 14 Stop Mode Recovery Source 3 43 Table 3 15 Load Instructions tete eb d e bti eats 3 53 Table 3 16 Arithmetic Instructions r 3 53 Tables TZ Logical oat e o ea uwa usted cua 3 53 Table 3 18 Program Control Instructions r 3 53 Table 3 19 Bit Manipulation Instructions 7 3 53 Table 3 20 Block Transfer Instructions oc aa A ee 3 53 UM97TELO700 xvii Z90230 Family of DTCs List of Tables Zilog NUMBER AND TITLE PAGE Chapter 3 Internal Microprocessor Overview Continued Table 3 21 Rotate and Shift Instructions 3 53 Table 3 22 CPU Control Instructions exi rcu beca ext era a 3 54 Table 3 23 Flag DefinitjonS to 3 56 Table 3 24 Flag Settings Definitions e De itia ed ore RE 3 56 Table 3 25 Condition GOOGS itin 3 56 Table 3 26 Notational Shorthand naa nnn namo ran magnas 3 57 Table 3 27 Additional NOtati ry s Ceca etc
9. 3 38 3 24 1 Vectored Interrupt Cycle TAM NG s eee arcad tek Ee uet aere ee 3 39 3 24 2 Nesting of Vectored Interrupts 3 40 2 25 P lled Processing z uu Lea indi S A E 3 40 3 26 Interrupt Reset Conditions ae te ih oec ratu 3 41 3 27 Power Down Halt Mode Operation 3 41 3 28 Stop Mod Operation EB PL n Pte Uu 3 41 3 29 STOP Mode Recovery Register a 3 42 3 30 Addressing Modes LL An Mi ed E 3 45 3 31 Register Addressing EE 3 45 3 32 Indirect Register Addressing re trenes anda bat 3 46 3 99 Indexed Adare SS hupu 3 49 Addr6SSinmgu a Papa E tapis 3 50 3 95 Relative AddrGSSIng uuu e e ea MM Ep 3 51 3 36 Immediate Data Addressilhig irpo eo ean Aisa ai 3 52 3 37 Instruction Set Functional Summary e 3 52 3 38 Processor xou freien 3 54 cs ee 3 55 BD ee ZNO FLAG mu ct 3 55 uama TO
10. D 25 Stack Pointer High Register D 25 0 25 Flag Register D 25 Interrupt Mask Register D 26 Interrupt Request 1 D 26 Interrupt Priority Register D 27 Port 2 Control Register D 27 Port 2 Mode Register D 28 Prescaler 0 Register D 28 Counter Timer 0 Register D 29 Prescaler 1 Register D 29 Counter Timer 1 Register D 29 Timer Mode Register D 30 Port 2 Data Register D 30 D 1 Z90230 Family of DTCs Registers Zilog Second Color SNDCLR Color Palette 0 CLR_PO Color Palette 1 CLR_P1 PWM 8 Data Register PWM8 09h PWM 9 Data Register PWM9 3 Bit ADC Data Register 00h PAMO TD Timer Control Register 0 TCRO 01h Port 5 Data Register 5 DTA 0 Timer Control Register 1 TCR1 02h PWM MODE Register P MODE IR Capture Register 0 IR 03h Port 5 Direction Register PRT5_DRT OEh IR Capture Register 1 IR_CP1 04h Port 4 Data Register PRT4 DTA Port4 Direction Register PRT4 DRT 06h HVInterrupt S
11. D 27 Figure D 56 Port 2 Mode Register 1 a D 28 Figure D 57 Prescaler 0 Register D 28 Figure D 58 Counter Timer 0 Register 222222 2 1 1 0 D 29 Figure D 59 Prescaler mei qq su atum rou ice e a icto bte D 29 Figure D 60 Counter Timer 1 Register enn rn d eio ete D 29 Figure D 61 Timer Mode Register Perl Q sui Odin D 30 Fig re 52 Data Register S co babe ei ret du DA D 30 Appendix E EMI Noise Reduction Figure Applieation CIF CHIE Be eb in ocu bt a eh e bm e eee a eiet E 1 xiv UM97TELO700 w M P Z90230 FAMILY OF DTCs USER S MANUAL LIST OF TABLES NUMBER AND TITLE PAGE Chapter 1 Introduction Table 1 1 Z90200 Family Product Summary R DU 1 3 Chapter 2 Architectural Overview Table 2 1 Z90230 Family OTP and Production Pin Assignment 2 3 Table 2 2 Z90239 Pin Assignments ma pr ERE 2 4 Table 2 3 IRQ Function Summary r 2 22 Table 2 4 IRQ Register ii uu tex t esp LH Rm 2 23 Table 2 5 Operational Limits
12. 4 29 Syntax of Assembly Language 3 58 V Vectored Processing 3 38 VRAM Address Map 4 23 Mode ona UPON DE ELTE 4 23 W Watch Dog Timer Description 3 20 HALT Las uode 3 20 Instruction and Flags 3 55 Mode Register 3 20 Time Out Period 3 20 Working Register Groups 3 3 UM97TELO700 1998 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products
13. ofo Horizontal Position Control Reserved Figure 4 7 Horizontal Position Example 4 2 4 Second Color Feature Second Color feature is the logical division of each column into two parts along each row for changing foreground color The number of each half column is called the Second Color Position The Second Color feature can be used for the smooth change of color in a row The change step for color is half of the character size UM97TEL0700 4 5 Z90230 Family of DTCs On Screen Display 4 2 5 Second Color Control Register The Second Color Position is the place where the foreground color changes to the color defined in the Second Color Control Register Register 07h Bank SNDCLR_CNTRL Second Color Control Register Read Write D7 be p5 p4 ps p2 p1 po Zilog Row Address for Second Color Control Second Color R G B Second Color Enable 0 Disables the second color feature 1 Enables the second color feature Figure 4 8 Second Color Control Register 4 2 6 Second Color Register Register 08h Bank A SNDCLR Second Color Register Read Write D7 pe b5 p4 ps v2 p1 o HVsync Interrupt Option 0 Interrupt Pending Disabled 1 Interrupt Pending Enabled Second Color Position Reserved Figure 4 9 Second Color Register Bit 7 is reserved When the register is read bit 7 returns a value 1 Bit 6 HVsync Interrupt Option
14. JA 2 ALS gt 22129 a E Ti S Reserved Expanded Register Register Reset Condition 0 03 Reserved 0 02 P2 0 01 Reserved 0 00 Reserved Figure D 2 Register and Expanded Register File Map UM97TELO0700 D 3 Z90230 Family of DTCs Registers D 4 OSD Control Register Read Write D7 pe ps p4 ps p2 pi po Zilog Vertical Retrace Blanking Character Size 1 1 2 Sync Polarity 0 Positive 1 Negative VRAM Mode 00 Select 10 row buffer mode 01 Select 4 row buffer mode 10 Select 2 row buffer mode 11 Reserved OSD Blank 0 Enable OSD POR default 1 Disable OSD Figure D 3 OSD Control Register Register 01h Bank A VERT_POS Vertical Position Register Read Write D7 D6 D5 D2 1 Do Vertical Position Control Reserved Figure D 4 Vertical Position Register Register 02h Bank A HOR_POS Horizontal Position Register Read Write D7 D6 D5 D4 D2 51 00 Horizontal Position Control Reserved Figure D 5 Horizontal Position Register UM97TELO700 Zilog Register 03h Bank A DISP_ATTR Display Attribute Register Read Write D7 D6 D5 D4 D3 D2 200 290230 Family of DTCs Registers Blue Master Background Green Master Background R
15. 4 10 4 3 3 Mesh Row Enable Register 4 10 97 0700 Z90230 Family of DTCs Table of Contents Zilog CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 4 On Screen Display Continued 4 3 Mesh and Halftone Effect Continued 4 3 4 Mesh Control Register eens iude dx 4 11 4 3 5 Mesh Window Display Example 4 12 4 4 OSD P AT 4 15 Z52Inter RoW 4 17 4 6 Character Generdtiot oou ei Eb Hte GM ue DUO d 4 18 4 6 1 Character Cell Resolution 4 18 4 6 2 Character Size and Smoothing Effect ht ri n 4 20 4 6 3 Eririgirig fois ol EE E LE 4 21 4 7 Display Attribute Control olere lait rr rerit eter 4 22 1 Display Attrib te Registe Tm 4 22 4 7 2 Video Refresh RAM Access nerve eee 4 23 4 7 3 Color Table and Color Index Register 4 25 4 7 4 Row Attribute Register deste o 4 27 4 8 HV Interrupt Processing 4 27 4 8 1 HV Interrupt Status Register 4 28 4 8 2 HsyNc and Vsync
16. and the register file The register file is composed of 236 bytes of general purpose registers 16 control and status registers 1 I O port register and 2 reserved registers The on screen display control circuits support 10 rows by 24 columns 10x24 of characters The character color is specified per character There are eight foreground colors and eight back ground colors When foreground and back ground colors are the same the background is transparent An analog bar line can be displayed when settings are defined for Row Second Color and Character Set The bar is used to display volume control signal levels and tuning The OSD is capable of displaying 2 character sizes 1X 14x18 pixels or 2X 28x36 pixels Inter row spacing is programmable from 0 to 15 horizontal scan lines This allows user to create pseudo icons using multiple characters with 0 row spacing A 14 bit Pulse Width Modulator PWM port provides enough voltage resolution for a voltage synthesizer tuning system Ten 6 bit PWM ports are used for controlling audio base treble balance and volume and video contrast brightness color tint and sharpness signal levels There are 27 pins dedicated to input and output functions They are grouped into four ports and are configurable under software control to provide timing status signals serial and parallel I O UM97TELO700 Z90230 Family of DTCs Zilog Introduction To handle re
17. 3 55 3 38 4 Overflow Flag ua ua usun ua ua naa aa op 3 55 9 39 5 Decirmal AdjustEFlag u sas oo oe oia v 3 55 9 38 6 Teall uio qp onto n npe e ap mE E DIR Drs d np pre PRU erus 3 55 3 39 Condition Dr bates Lei 3 56 3 40 Notation and Binary Encoding cocco oe Inpede 3 57 3 40 1 Assembly Language Syntax o iei ie ob s eee a barcode aad 3 58 Chapter 4 On Screen Display IntFodHelloi ter ua ted eet EE 4 1 A 2H OSD POSINOM uuu manpas qo Ete t n met LAE DE 4 2 4 2 1 OSD Control Register on ip bem m a cd ete te esed 4 3 4 2 2 Vertical Position Register D ot eo ERE Ud 4 4 4 2 3 Horizontal Position Register p E ere ERE av do een EROR epe 4 4 42 4 Second Color op n up d bp E eu 4 5 4 2 5 Second Color Control Register L 4 5 4 2 6 Second Color oed il tape un trus 4 6 4 2 7 Second Color Example I iege Rd Rene 4 6 4 3 Mesh and Halftone Effect 2 4 7 4 3 1 Mesh Column Start Register 4 9 4 3 2 Mesh Column End Register
18. 4 29 4 9 Dot Clock OSolllalOE uama t red E x 4 30 Z9 ato Eu aite 4 30 Chapter 5 2 Interface C BUS Concepts beaches dcbet nay d DATEN on UD erc 5 1 5 2 Data e asas 5 1 5 3 START d STOP Conditions 5 1 Data BRAS Sl 5 1 5 97 Byte Formatiu ie eps dette ba 5 2 PACINO WS Dm 5 3 5 7 Z90230 Family Master Interface 5 3 5 7 1 Master 2C Control Register cascos 5 5 5 8 Software Control of the C Interface 5 6 Chapter 6 Input Output Ports PT cp 6 1 6 1 1 Port Configuration Register ucc pt narro een qae host Ge degere iude 6 1 6 1 2 Port 2 Mode Register edet tbe ttt dam utut ah S ME A 6 2 6 13 Port Register x oae Dna alu rd pM MAU 6 3 6 1 4 Port 4 Pin Out Selection 6 3 6 1 5 Port 4 Data Heglslot 2 2 bv date pid ue oi eee re a Rb u d 6 5 6 1 6 Port 4 Direction Control Register 6 6 6 1 7 Port 5 PWM Mode
19. Load 0 Function 1 Load TO Count 0 Disable Count 1 Enable TO Count Load 1 0 No Function 1 T1 T1 Count 0 Disable T1 Count 1 Enable T1 Count Reserved Must be 00 Reserved Must be 00 Figure D 61 Timer Mode Register Register 02h P2 Port 2 Data Register Read Write D7 D6 D5 D4 D3 D2 D1 bo P20 Read Data Input on P20 Write Data Output on P20 P21 Read Data Input on P21 Write Data Output on P21 P22 Read Data Input on P22 Write Data Output on P22 P23 Read Data Input on P23 Write Data Output on P23 P24 Read Data Input on P24 Write Data Output on P24 P25 Read Data Input on P25 Write Data Output on P25 P26 Read Data Input on P26 Write Data Output on P26 P27 Read Data Input on P27 Write Data Output on P27 Figure D 62 Port 2 Data Register D 30 97 10700 USER S MANUAL APPENDIX E EMI NOISE REDUCTION E 1 EMI NOISE REDUCTION THROUGH PCB DESIGN Z90230 family is a complicated mixed signal device The performance of analog circuitries can be very susceptible to external noise Digital circuits can generate high frequency noises and EMI from other components in the PCB can dete riorate performance For the best EMI performance PCB design needs to be done for sufficient decoupling of noise from the microcontroller That noise can be Ferrite Bead picked up by external circuitry if it does not have good decoupling High EMI im
20. hah hunu acs ok uu Mi n 2 2 ly Pin Taentitig StOFI u uu nu n Eo 2 2 2 Z90239 124 Pin PGA Ceramic Package Pin Out Diagram 2 2 3 Z90239 Pin Assignment Be Ah EA A A Ln ADU Bie hie ADM 2 2 4 Pin Descriptions 2 65 22 5 GOREAGUSTOMIZALION osos e Coe eei e Corb 2 2 b BIOGK DISSERT E DUC tp ata c 2 3 1 3 Bit ADC Data Register 2 3 2 4 Bit ADC Data Register as Se 2 3 3 Port 4 Pin Out Selection Register tete deat a pc dept i ap i etel dus Expanded Regist r File uo PH RH inet n cba rs 2 3 5 Stop Mode Recovery Register n 2 3 6 Watch Dog Timer Mode Register 2 3 7 Timer Mode Register x eee pet s o ab er i 2 3 8 Gounter Timer 1 Register rere netto cad ae ho se eot gei 2 9 9 Prescaler rotae aaa eds 2 3 10 Counter Timer 0 a rue E EET RA RS 2 3 11 Presealor u uuu DAE RERUM atrii ederet 2 3 12 Port 2 Mode Register uan op erectio t Pre
21. 2 3 13 Port 2 Control Register Bale t A dA UE 2 3 14 Interrupt Priority Register 8 840 2 3 15 Interrupt Request Register e pute Al slate 2 3 16 Interrupt Mask Registe 2 3 T7 Flags PROC ISU c o hai Ep DE 2 9 19 Register PONCE uu L L aea 2 93 Oe Stack ett 2 97 10700 Z90230 Family of DTCs Table of Contents Zilog CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 2 Architectural Overview Continued 2 3 Control Registers Continued 2 39 20 IAG KF ollitet LOW 222 ___ 2 25 2 3 21 Port Data Register 2 25 2 4 Operating Characteristics i oie ied cac edis 2 26 2 41 BI Ga GharacierstieS co hte ot dde d ah ESE ooa M t bett d 2 27 2 28 Chapter 3 Internal Microprocessor Overview SI Address Spaces RU Hm ite pups M p MM E 3 1 9 2 Standard Register aout bcr coo Meo tpi cen E caius 3 1 3 2 1 General Purpose Fleglsiel s en nio en b x ee he eR e meu 3 3 32 2 RAM NE T DU ES 3 3 3 2 3 Working Register Groups 3 3
22. nd oet ir aS eR 2 29 UM97TELO700 ix Z90230 Family of DTCs List of Figures Zilog NUMBER AND TITLE PAGE Chapter 3 Internal Microprocessor Overview Figure 3 1 16 Bit Register Addressing 3 2 Figure 3 2 Accessing Individual Bits Example 2 3 2 Figure 3 3 Working Register Addressing Examples 2 3 3 Figure 3 4 Register Pointer 3 4 Figure 3 5 Register and Expanded Register File 3 6 Figure 3 6 Register Pointer FDh Example J rite te ten rcu Dee ore eL Eo en 3 7 Figure 3 7 Program Memory tee 3 10 Figure 3 8 Stack Pointer ee Rm 3 11 Fig re 3 9 Stack Operation ua usus teal ite iod Ua 3 11 Figure 3 10 Port Configuration Register devi oie under aped 3 12 Figure 3 11 Pierce Oscillator with Internal Feedback Circuit 3 13 Figure 3 12 Circuit Board Design Rules eee 3 14 Figure 3 13 Crystal Ceramic Resonator Oscillator 3 15 Figure 3 14 UC huuu Sauna 3 15 Figure 3 15 External Slack wv C
23. p Zilog pns RGB Color Programming R6f G6f B6f R6b G6b B6b Reserved Figure 4 38 Color Palette 6 4 7 4 Row Attribute Register ROW ATTR Row Attribute Register Read Write D7 be p5 p4 ps p2 p1 po Defines the Row Background Color R G B Respectively Row Background Enable 0 Row Background Color is Disabled 1 Row Background Color is Displayed Defines the Row Foreground Color R G B Respectively Row Foreground Enable 0 Row Foreground Color is Displayed 1 Row Foreground Color is Disabled Figure 4 39 Row Attribute Register The Row Attribute Register is mapped to VRAM as shown in Figure 4 39 This register controls row background and foreground display If the Color Index is set to 000 the display color is read from the Row Attribute Register Bit 7 Row Foreground Enable enables or disables row foreground color 4 8 HV INTERRUPT PROCESSING An interrupt is issued at the beginning of a row and at the leading edge of the Vsync signal The leading edge of the first HsyNc of a row consti tutes the beginning of a row The Z90230 soft ware tracks this cycle as two recurring events 4 28 Bits 6 5 and 4 Row Foreground Color desig nate the color of the characters displayed in the row Bit 3 Row Background Enable disables or enables row background color Bits 2 1 and 0 Row Background Color desig nate the color of the row backgro
24. 2 17 Figure 2 11 Timer Mode Register 2 2 17 Figure 2 12 CounterTimer1 Register i Ree creep Ee Eo Eb Ce ire it eae 2 18 Figure 2 13 Prescaler 1 REGIS itt Bate teat aed a eileen eee Be 2 18 Figure 2 14 Counter Timer 0 Register 2 ssseceseceeeeteeetencneceneeeteeteteneeetedenedeneseeseneneseceneeenes 2 18 Figure 2 15 Prescaler 0 Register 1 deter oeedoeaceeucndeceadeemeede 2 19 Figure 2 16 Port 2 Mode Register oc aid ia e e pee ee 2 20 Figure 2 17 Port 2 Control Register a a 2 20 Figure 2 18 Interrupt Priority Register oboe re eee 2 21 Figure 2 19 Interrupt Request Register 2 22 Figure 2 20 Interrupt Mask Register a eu cese nardo eru nn 2 23 Figure 2 22 Register deni T 2 24 Figure 2 23 Stack Pointer High Register euenit 2 24 Figure 2 21 Flags Regisler uuu 2 24 Figure 2 24 Stack Pointer Low Register 255 222512 2 25 Figure 2 25 Port 2 Data Register edet br bruni detecte px uia 2 25 Figure 2 26 AC Characteristics
25. Figure D 7 Row Space Register Figure D 8 Fade Position Register 1 Figure D 9 Fade Position Register 2 Figure D 10 Second Color Control Register Figure 0 11 Second Color Register Figure D 12 Color Palette oed Figure 0 13 Color Palette 1 Figure D 14 Color Palette 2 I oe Figure D 15 Color Palette 9 ieget ete ete Figure 0 16 Color Palette 4 2222 2222222 Figure D 17 Color Palette 5 ose tete reden fener estes Figure 0 18 Color Palette 6 Figure 0 19 PWM11 Register Figure 0 20 PWM1 through PWM10 Registers Figure 0 21 Row Attribute Register Figure 0 22 Port 5 Data Register Figure 0 23 PWM Mode Register Figure 0 24 Port 5 Direction Control Register Figure D 25 3 Bit ADC Data Register
26. 000000 E 1 Appendix F Sales Offices 2222 2222 242 2 4 1 1 F 1 Appendix Literature sss G 1 97 0700 vii W NM 3 290230 FAMILY DTCs eM USER S MANUAL LisT OF FIGURES NUMBER AND TITLE PAGE Chapter 1 Introduction Figure 1 1 290230 DTC System Application eee eeeeeeeeeeeesneeeeeedeneeeneeeeee 1 2 Chapter 2 Architectural Overview Figure 2 1 290231 and Z90233 Pin Identification 2 2 Figure 2 2 290239 124 Pin PGA Ceramic Package Pin Out Diagram 2 4 Figure 2 3 Block Diagram 2 ocv eu ui 2 10 Figure 2 4 3 Bit ADC Data Register 2 11 Figure 2 5 4 Bit ADC Data Register 222222 4 4 4140 2 12 Figure 2 6 Port 4 Pin Out Selection Register 2 13 Figure 2 7 Register and Expanded Register File 2 14 Figure 2 8 Expanded Register File 22111 ce drin 2 15 Figure 2 9 Stop Mode Recovery Register 22222222221 4 4 1 1 2111 1200 1711 4 1 4111 2 16 Figure 2 10 Watch Dog Timer Mode Register
27. 54 Pulse Width Modulator 5 or Port 5 Pin 4 The PWM signal generator channel has 6 bit resolution Port 5 pin 4 is a programmable input or output port PWM4 P53 Pulse Width Modulator 4 or Port 5 Pin 3 The PWM signal generator channel has 6 bit resolution Port 5 pin 3 is a programmable input or output port 2 2 5 Core Customization Several features have been added to and removed from the internal microprocessor used in the Z86C43 to form the Z90230 family However the description of core still applies to the Z90210 and Z90230 DTC family of applica tions Information about the registers is included in Chapter 3 The following Z86C43 features are not available in the Z90230 family m P3voltage comparators are not supported m Port handshaking is not supported m PortO and Port not available and yield 05 when read UM97TELO0700 290230 Family of DTCs Architectural Overview PWM3 P52 Pulse Width Modulator 3 or Port 5 Pin 2 The PWM signal generator channel has 6 bit resolution Port 5 pin 2 is a programmable input or output port PWM2 P51 Pulse Width Modulator 2 or Port 5 Pin 1 The PWM signal generator channel has 6 bit resolution Port 5 pin 1 is a programmable input or output port PWM1 P50 Pulse Width Modulator 1 or Port 5 Pin 0 The PWM signal generator channel has 6 bit resolution Port 5 pin 0 is a programmable input or output port 2 9 Z90230 Family of DTCs Architectural Overview Zilog
28. The following codes appear within tables through 7 A letter may appear in the bit place to indi cate the type of information stored in the bit The fol Al Analog Input lowing letters designate the bit type or value Input NC Not Connected D Data Bit ae T Timer Bit E 2 U Unknown Value w jos X Place Holder D 0 Binary Value 0 eS 1 Binary Value 1 0 4 2 tional BV The terms of the license agreement require h in an I ided that th display of the following notice these components an I C system provided that the system conforms to the 2 standard specification as Purchase of I C components of Zilog Inc or one of its defined by Philips sublicensed Associated Companies conveys a 0 5 ABOUT THIS USER S MANUAL The following individuals have contributed to the prepara Laura Bayer Dongsoo Kim Bruno Kranzen Steven Lau tion of this User s Manual Alexander Marquez Alex Muratov Donghyun Song and Anatoliy Tsyrganovich ii UM97TELO700 w IM Z90230 FAMILY OF DTCs USER S MANUAL TABLE OF CONTENTS CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 1 Introduction 1 2 EI CIN eei a a ve eh a ret eed eae Chapter 2 Architectural Overview Po Te
29. 0700 D 13 Z90230 Family of DTCs Registers Zilog Register 03h Bank C IR_CP0 IR Capture Register 0 Read 07 06 05 4 0 2 01 Capture Register 0 Reading Low Byte of IR Capture Data Figure D 28 IR Capture Register 0 Register 04h Bank C IR_CP1 IR Capture Register 1 Read D7 be p5 p4 ps p2 p1 po IR Capture Register 1 Reading High Byte of IR Capture Data Figure D 29 IR Capture Register 1 Register 05h Bank C PRT4 DTA Port 4 Data Register Read Write D7 be p5 p4 ps p2 p1 po 40 Read Data Input 40 Write Data Output on P40 P41 Read Data Input on P41 Write Data Output on P41 P42 Read Data Input on P42 Write Data Output on P42 P43 Read Data Input on P43 Write Data Output on P43 P44 Read Data Input on P44 Write Data Output on P44 P45 Read Data Input on P45 Write Data Output on P45 P46 Read Data Input on P46 Write Data Output on P46 P47 Read Data Input on P47 Write Data Output on P47 Figure D 30 Port 4 Data Register D 14 UM97TEL0700 Zilog UM97TEL0700 Register 06h Bank C PRT4_DRT Z90230 Family of DTCs Port 4 Direction Control Register Read Write D7 D6 D5 D4 D2 1 00 P40 I O Definition 0 Defines P40 as Output 1 Defines P40 as Input POR P41 I O Definition 0 Defines P41 as Output 1 Defines P41 as Inpu
30. 3 22 Zilog level to ensure correct operation of the device Reset is globally driven if Vcc is below the spec ified voltage The POR time is specified as On the Stop Mode Recovery register SMR bit 5 selects whether the POR timer is used after Stop Mode Recovery or by passed If bit D5 1 then the POR timer is used If bit 5 0 then the POR timer is by passed In this case the Stop Mode Recovery source must be held in the recovery state for 5 TpC or 5 crystal clocks to pass the reset signal internally This option is used when the clock is provided with an LC clock or an external clock since these clock resources do not require a long stabilization time POR always resets the control and port registers to their default condition In the SMR register the warm start bit resets to 0 to indicate POR Each counter timer operates in either Single Pass or Continuous Mode At the end of count counting either stops or the initial value is reloaded and counting continues Under soft ware control new values are loaded immediately or when the end of count is reached Software also controls the counting mode how a counter timer is started or stopped and its use of I O lines Both the counter and prescaler regis ters can be altered while the counter timer is running UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview OSC Internal Data Bus Write it D1 SMR PREO TO TO I
31. Z90230 Family of Digital Television Controllers User s Manual UM97TELO0700 0 1 PURPOSE This user manual provides a comprehensive document that serves as a one stop reference m Z90230 Family of Digital Television Controllers DTCs Chapters 1 2 4 6 and 7 contain information that directly relates to the Z90230 family components General Description Architectural Overview Memory Registers On Screen Display Input Output Ports and the Infrared Interface W Internal Microprocessor Overview Chapter contains information about the microcontroller base functions used within the Z90230 family of products m 2 Standard Chapter 5 contains information about the implementation of the 2 bus with the Z90230 products Appendix A contains a copy of the 2 Standard 0 2 290230 FAMILY OF PRODUCTS 290230 represents a number of individual products Please be aware that not all information within the manual applies to all products Specific product applicability and 0 3 NOTATION The following conventions have been adopted for use throughout this manual m The notation addr n is used to refer to bit n of a given location For example bit 7 of the dst operand is referenced as dst 7 Bits 4 3 2 1 and 0 of the FADE POS register are referenced as FADE POS 4 3 2 1 0 UM97TELO0700 USER S MANUAL PREFACE m Additional Reference Appendices B and C contain reference information abou
32. m Proceed with interrupt processing m After processing is complete execute DI instruction m Restore the IMR to its original value by returning the previous mask from the stack m Execute IRET Depending on the application some simplifica tion of the above procedure may be possible To enable any interrupt first the interrupt mech anism must be engaged with an El instruction If only polled interrupts are to be serviced execute UM97TELO700 Zilog El Enable interrupt mechanism DI Disable vectored interrupts To initiate polled processing check the bits of interest in the IRQ using the Test Under Mask TM instruction If the bit is set call or branch to the service routine The service routine services the request resets its Request Bit in the IRQ and branches or returns back to the main program An example of a polling routine is as follows TM IRQ Test for request JR 4 NEXT no request go to NEXT 3 26 INTERRUPT RESET CONDITIONS At Reset all bits in IPR are undefined 290230 Family of DTCs Internal Microprocessor Overview CALL SERVICE request is there service it NEXT SERVICE Process Request AND IRQ MASKB RET Clear Request Bit Return to NEXT In this example if IRQ2 is being polled MASKA In IMR bit 7 is 0 and bits 0 6 are undefined The IRQ register is reset and held in that state until an enable interrupt El instruction is executed 3 27
33. 3 16 Prescaler And Counter Timers 3 22 Operations u Cd Rs 3 25 Register and Timer Input 3 27 Product Summary 1 3 Program Memory Interrupt Vectors 3 10 cgi 3 10 Pulse Width Modulators 8 1 PUSH q a a 3 11 PWMs Mode Register 8 1 PWM1 through PWM 11 8 3 Settings in the PIN SLT Register D 16 Timing Diagram 14 8 5 Timing Diagram 6 8 4 R RAM Protect aig 3 3 Interrupt Mask Register 3 35 Register ADC Data 2 11 2 12 B 2 Addressing 3 45 Bank A ecc 3 8 Bank B 3 9 8 1 3 9 Bar Gontrol uyasapa 4 5 Bar Position 4 6 Color Index oio e e bep 4 25 Counting Mode 3 25 Display Attribute 4 22 Expanded File 2 15 Expanded File Map 2 14 3 6 Expanded Z8 3 8 Fade Position 1 4 17 Fade u uuu un uu Susu 4 17 Flag PERDERE 3 54 Horizontal Position 4 4 In
34. Disables Interrupt 1 Enables Interrupt Figure 2 20 Interrupt Mask Register Note 1 This option must be selected when ROM code is sub mitted for ROM masking Otherwise this control bit is disabled permanently UM97TELO0700 2 23 Z90230 Family of DTCs Architectural Overview Zilog 2 3 17 Flags Register Register FCh Flags Flags Register Read Write D7 D6 D5 D4 D3 D2 D1 D0 L User Flag F1 User Flag F2 Half Carry Flag H Decimal Adjust Flag D Overflow Flag V Sign Flag S Zero Flag Z Carry Flag C Figure 2 21 Flags Register 2 3 18 Register Pointer Register FDh RP Register Pointer Read Write D7 pe ps p4 p3 p2 pilpo Defines Expanded Register File Defines Working Register Pointer Figure 2 22 Register Pointer 2 3 19 Stack Pointer High Register FEh SPH Stack Pointer High Read Write D7 pe ps p4 ps p2 pilpo T Stack Pointer Upper Byte SP8 SP15 Figure 2 23 Stack Pointer High Register There are 236 FFh general purpose registers in the Z90230 family of products The SPH register is reserved for future expansion 2 24 UM97TEL0700 Zilog 2 3 20 Stack Pointer Low Register FFh SPL Stack Pointer Low Read Write 07 06 05 04 03 2 01 Stack Pointer Lower Byte SP0 SP7 Z90230 Family of DTCs Architectural Overview Figure 2 24 Stack Pointer Low Register 2 3 21 Por
35. IRQ5 gt IRQ3 1 IRQ3 gt IRQ5 Reserved Must be 0 Figure 3 42 Interrupt Priority Register Table 3 10 Interrupt Priority Priority Group Bit Value Highest Lowest C 1 0 IRQ1 IRQ4 1 IRQ4 IRQ1 B 2 0 IRQ2 IRQ0 1 IRQ0 IRQ2 A 5 0 IRQ5 IRQ3 1 IRQ3 IRQ5 3 34 UM97TEL0700 Zilog Table 3 11 Interrupt Group Priority Bit Pattern Group Priority Bit4 Bit0 High Medium Low 0 0 0 Not Used 0 0 1 C A B 0 1 0 A B C 0 1 1 A C B 1 0 0 B C A 1 0 1 C B A 1 1 0 B A C 1 1 1 Not Used 3 22 2 Interrupt Mask Register Initialization An Interrupt Mask Register IMR initialization individually or globally enables or disables the six interrupt requests When bits 5 4 3 2 1 0 are set to 1 the corresponding interrupt requests are enabled Bit 7 is the master enable and must be set before any of the individual interrupt requests can be recognized Resetting bit 7 globally disables all the interrupt requests Bit 7 is set and reset by the El and DI instructions It is automat ically reset during an interrupt service routine and set following the execution of an Interrupt Return IRET instruction 97 0700 290230 Family of 5 Internal Microprocessor Overview 3 35 Z90230 Family of DTCs Internal Microprocessor Overview Note Bit 7 must be reset by the DI instruction before the contents of the Interrupt Mask Register or the Interrupt Priority Register are
36. Mnemonic Operands Instruction Table 3 20 Block Transfer Instructions ADC dst src Add with Carry ADD dst src Add CP dst src Compare DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word SBC dst src Subtract with Carry SUB dst src Subtract Operand Mnemonic 6 Instruction LDCI dst src Load Constant Auto Increment LDEI dst src Load External Auto Increment Table 3 21 Rotate and Shift Instructions Table 3 17 Logical Instructions Mnemonic Operands Instruction AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical Exclusive OR Table 3 18 Program Control Instructions Mnemonic Operands Instruction CALL dst Call Procedure DJNZ dst src Decrement and Jump Non Zero IRET Interrupt Return JP cc dst Jump JR cc dst Jump Relative RET Return UM97TELO700 Operand Mnemonic s Instruction RL dst Rotate Left RLC dst Rotate Left Through Carry RR dst Rotate Right RRC dst Rotate Right Through Carry SRA dst Shift Right Arithmetic SWAP dst Swap Nibbles 3 55 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Table 3 22 CPU Control Instructions Mnemonic Operands Instruction CCF Complement Carry Flag DI Disable Interrupts El Enable Interrupts HALT Halt NOP No Ope
37. P45 PWM8 0 Selects PWM8 1 Selects P45 POR P46 PWM9 0 Selects PWM9 1 Selects P46 POR P47 PWM10 0 Selects PWM10 1 Selects P47 POR Reserved Figure 8 2 Port 4 Pin Out Selection Register 8 1 3 PWM1 through PWM11 Two data registers PWM11 and PWM11 1 hold the 14 bit PWM11 ratio The upper 7 bits controls the width of the distributed pulse The lower 7 bits distribute the minimum resolution pulse in the various time slots By using this tech nique the pseudo repetition of frequency is raised up to 128 times faster than ordinary pulse width modulation There are 128 time slots which start from time slot 7Fh to 0 because a 14 bit binary down counter is used When the glitch exceeds 127 pulses the upper 7 bits take precedence and fill 128 pulses of the same width in different loca tions Generating the pulse train output requires UM97TELO0700 the following equation Time slot Fts and one cycle of frequency F14 Fdp Distribution pulse frequency XTAL 128 Hz Fts Time slot frequency XTAL 128 Hz F14 a cycle frequency XTAL 16384 Hz When the 6 bit data is the PWM output is Low The maximum value is 3Fh and emits High DC level output A Selected PWM cycle frequency is shown in the following equa tion F6 a cycle frequency XTAL 16 64 Hz Figures show various timing pulses and resultant frequencies for the 6 and 14 bit PWMs 8 3 Z90230 Family of DTC
38. Register OEh Bank A CLR_P5 Color Palette 5 Read Write b ps spaps pa RGB Color Programming R5f G5f B5f R5b G5b B5b Reserved Figure D 17 Color Palette 5 Register OFh Bank A CLR P6 Color Palette 6 Read Write bpspsp pspe ro RGB Color Programming R6f G6f B6f R6b G6b B6b Reserved Figure D 18 Color Palette 6 Register 00h Bank PWM11H PWM11 High Data Register Read Write 5 NEM PWM11 High Byte Reserved Register 01h Bank B PWM11L 11 Low Data Register Read Write p7 pe ps p4 ps p2 p po Litt Low Byte Figure D 19 PWM11 Register D 8 UM97TELO700 Zilog UM97TELO700 Register 02h Bank PWM1 PWM1 Data Register Read Write brppspsp spe p oo w Register 03h Bank B PWM2 PWM2 Data Register Read Write bpspspapspzpps 2 Value Register 04h Bank B PWM3 PWMS3 Data Register Read Write p7 pe ps p4 ps pz p po pl C PWMS Value Register 05h Bank B PWM4 PWMA Data Register Read Write 75824329 LL Value Register 06h Bank B PWM5 PWM5 Data Register Read Write 7 5 1 MES CES PWMb5 Value Register 07h Bank B PWM6 PWM6 Data Register Read Write p7 pe ps p4 pa p2 pi po 0 LLL PWM6 Value Register 08h Bank B PWM7 PWM7 Data Register Read Write 2756555435250 pre PWM7 Value Register 09h
39. m P32 and P33 port interrupts are not available clock to Timer1 P62 is still an interrupt input and yield 0s when read port WDT is not clocked when in Stop Mode m P62 edge selection in interrupt request register has been modified m Timer 1 is used for horizontal synchronization P62 input is no longer valid as the external 2 2 6 Block Diagram 2 10 Oscillator WDT RESET ounter Counter Timer 4 Bit ADC Port 6 PWM 11 14 bit 8 12 16 24 32 KB Program ROM or 16 KB Program OTP Internal Microprocessor Core Register File 236 Byte 2 lt gt SCLKO Character RAM lt gt SDATAO 240 x 11 Bit Interface 8 10 x 8 Bit lt gt SDATA1 On Screen Character Display ROM or OTP 9 KB by 7 Bit Figure 2 3 Block Diagram UM97TELO700 Zilog 2 3 CONTROL REGISTERS Most of the control registers are mapped into expanded register file groups in the internal microprocessor core Refer to the Z8 2 3 1 3 Bit ADC Data Register Four multiplexed analog inputs are available to either a 3 bit or 4 bit analog to digital converter ADC depending on the configuration Register 00h Bank C 3ADC_DTA 3 Bit ADC Data Register Read Write Z90230 Family of DTCs Architectural Overview Microcontrollers User s Manual for a detailed functional description Figure 2 4 Figure 2 5 and Figure 2 6 describe the 3ADC DTA 4ADC_DTA
40. m Vcc is at the low end of the device s operating range m WDT is Off in the Stop Mode m Output current sourcing is minimized m All inputs digital and analog are at the low or high rail voltages 3 29 STOP MODE RECOVERY REGISTER This register selects the clock divide value and determines the mode of Stop Mode Recovery 3 44 All bits are Write Only except bit 7 that is Read Only Bit 7 is a flag bit that is hardware set on the UM97TELO700 Zilog condition of Stop Mode Recovery and reset by a power on cycle Bit 6 controls whether a Low level a High level is required from the recovery source Bit 5 controls the reset delay after recovery Bits 2 3 and 4 of the SMR register Register 0Bh Bank F SMR Z90230 Family of DTCs Internal Microprocessor Overview specify the source of the Stop Mode Recovery signal Bits 0 and 1 control internal clock divider circuitry The SMR is located in bank F of the expanded register file at address 0Bh Stop Mode Recovery Register Write Only Except Bit D7 Which Is Read Only 2585942362550 1 001 010 P62 101 27 Stop Dela O Off T 1 High 0 POR 1 2 On POR SCLK TCLK Divide by 16 0 Off POR External Clock Divide by 2 0 SCLK TCLK XTAL 2 POR 1 SCLK TCLK XTAL Stop Mode Recovery Source 000 Bea and or External Reset 011 Must not be used 100 Must not be used 110 P2 NOR 0 3 111
41. quent Decimal Adjust DA operation can func tion properly Normally the Decimal Adjust Flag 3 38 6 Half Carry Flag The Half Carry Flag H is set to 1 whenever an addition generates a carry out of bit 3 overflow or a subtraction generates a borrow into bit 3 The Half Carry Flag is used by the Decimal Adjust DA instruction to convert the binary 97 0700 290230 Family of 5 Internal Microprocessor Overview Following Rotate and Shift instructions the carry flag contains the last value shifted out of the specified register IRET may change the value of the carry flag when the Flag register saved in the stack is restored zero flag is set to 1 Otherwise the Zero Flag is cleared to 0 IRET changes the value of the Zero Flag when the flag register saved in the stack is restored The WDT instruction sets the Zero Flag to 1 significant bit position bit 7 therefore the Sign Flag is also 0 A negative number is identified by a 1 in the most significant bit position bit 7 therefore the Sign Flag is also 1 IRET changes the value of the Sign Flag when the flag register saved in the stack is restored Overflow Flag is set to 0 if no overflow occurs Following logical operations the Overflow Flag is set to 0 IRET changes the value of the overflow flag when the flag register saved in the stack is restored cannot be used as a test condition After a subtraction the Decimal Adjust Flag is set to 1 Fol
42. 1 2 Frequency Figure 4 43 Oscillation Frequency where L is the total inductance including para sitics and Cy is the total series capacitance 4 9 1 Layout Traces connecting capacitors inductor and dot clock oscillator should be as short and wide as possible This reduces parasitic inductance and resistance The components capacitors and inductor should be placed close as possible to the dot oscillator pins of the Z90230 UM97TELO0700 including the parasitics Simple series capaci tance is calculated using the following equation d ei Figure 4 44 Simple Series Capacitance Care must be exercised in choosing LC values Recommended values are L 27uH and C 22pF This value of C does not include routing capac itance The traces from the oscillator pins of the IC and the ground side of the lead caps should be guarded from all other traces clock Voc address data lines and system ground to reduce cross talk and noise injection Z90230 Family of DTCs On Screen Display Zilog 4 32 UM97TELO700 5 1 05 CONCEPTS Inter Integrated Circuit I C is a serial interface Two wires serial data SDATA and serial clock SCLK carry information between the devices connected to the bus Each device is recognized by a unique address and can operate as a trans mitter and receiver except as limited by the func tion of the device A Master is a device which initiates a data transfer on
43. 3 17 MODE The Timer Mode Register TMR F1h is used to configure Hsync as TMR 3 the enable count bit must be set to 1 and initial values must be loaded into the down counters by setting the load bit TMR 2 to a 1 before counting begins In the descriptions of that follow it is assumed the programmer has performed these 97 0700 290230 Family of 5 Internal Microprocessor Overview occurs on the timer clock following an end of count New initial values should be written before the desired load operation since the prescalers always effectively operate in Continuous Mode The time interval i until end of count is given by the equation i tXpXv in which t four times the internal clock period The internal clock frequency defaults to the external clock source XTAL ceramic resonator and others divided by 2 Some microcontrollers allow this divisor to be changed via the Stop Mode Recovery register See the product data sheet for available clock divisor options Note that t is equal to eight divided by XTAL frequency of the external clock source for T external clock mode only p the prescaler value 1 63 for TO and T1 The minimum prescaler count of 1 is achieved by loading 000001XX The maximum count of 63 is achieved by loading 111111XX v the Counter Timer value 1 255 Minimum duration is achieved by loading 01h 1 prescaler output count
44. Bank B PWM8 PWMSB Data Register Read Write p7 be o5 p4 ps pe p bo ie PWMB8 Value Register 0Ah Bank B PWM9 PWM9 Data Register Read Write p7 ps ps p4 ps p2 pi po _ PWM9 Value Register 0Bh Bank B PWM10 PWM10 Data Register Read Write 5 Es PWM10 Value PWM1 Value Z90230 Family of DTCs Registers Figure D 20 PWM1 through PWM10 Registers D 9 Z90230 Family of DTCs Registers Zilog ROW_ATTR Row Attribute Register Read Write D7 D6 D5 D3 D2 1 00 Defines the Row Background Color R G B Respectively Row Background Enable 0 Row Background Color is Disabled 1 Row Background Color is Displayed Defines the Row Foreground Color R G B Respectively Row Foreground Enable 0 Row Foreground Color is Displayed 1 Row Foreground Color is Disabled Figure D 21 Row Attribute Register Register Bank B PRT5 DTA Port 5 Data Register Read Write D7 D6 D5 D4 D3 D2 pi 00 po P50 Read Data Input on P50 Write Data Output on P50 P51 Read Data Input on P51 Write Data Output on P51 P52 Read Data Input on P52 Write Data Output on P52 P53 Read Data Input on P53 Write Data Output on P53 P54 Read Data Input on P54 Write Data Output on P54 P55 Read Data Input on P55 Write Data Output on P55 P56 Read Data Input on P56 Write Data Output on P56
45. C or F only changes register addresses 00h to OFh the working register pointer can be used to access either the selected ERF bank bank C or F working register group 0 or the Standard Register File ERF bank 0 working register groups 1 through F Note When an ERF bank other than bank 0 is enabled the first 16 bytes of the standard register file I O ports 0 to 3 Groups 4 to F are no longer accessible The selected ERF bank registers 00h to 0Fh are accessed instead It is important to re initialize the register pointer to enable ERF bank 0 when these registers are required for use 3 7 Z90230 Family of DTCs Internal Microprocessor Overview Zilog 3 4 CONTROL AND PERIPHERAL REGISTERS 3 4 1 Standard Registers The standard control registers govern the opera tion of the CPU Any instruction which references the register file can access these control regis ters Available control registers are m Interrupt Priority Register IPR m Interrupt Mask Register IMR m Interrupt Request Register IRQ Program Control Flags FLAGS m Register Pointer RP Stack Pointer Upper Byte SPH m Stack Pointer Lower Byte SPL A 16 bit Program Counter PC determines the sequence of current program instructions The PC is not an addressable register 3 4 2 Expanded Registers The expanded control registers govern the oper ation of additional features or peripherals Any instruction which references the register file
46. Defines P52 as Output 1 Defines P52 as Input POR P53 I O Definition 0 Defines P53 as Output 1 Defines P53 as Input POR P54 I O Definition 0 Defines P54 as Output 1 Defines P54 as Input POR P55 I O Definition 0 Defines P55 as Output 1 Defines P55 as Input POR P56 I O Definition 0 Defines P56 as Output 1 Defines P56 as Input POR Reserved Figure 6 9 Port 5 Direction Control Register The Port 5 Direction Control Register identifies each bit as output 0 or input 1 data UM97TELO0700 6 9 Z90230 Family of DTCs Input Output Ports 6 1 10 Port 6 Data Register Register 03h Bank F PRT6_DTA Port 6 Data Register Read Write 2755552453522 L P60 Read Write P61 Read Write P62 Read Write P63 Read Write Data Input on P60 Data Output on P60 Data Input on P61 Data Output on P61 Data Input on P62 Data Output on P62 Data Input on P63 Data Output on P63 Reserved Figure 6 10 Port 6 Data Register 6 10 Zilog UM97TEL0700 Z90230 Family of DTCs Zilog Input Output Ports 6 1 11 Port 6 Direction Control Register Register 02h Bank F PRT6_DRT Port 6 Direction Control Register Read Write 2755552453522 60 0 Data Output 1 Data Input POR P61 0 Data Output 1 Data Input POR P62 0 Data Output 1 Data Input POR P63 0 Data Output 1 Data Input POR P60 0 Open Drain Output 1 Push Pull O
47. I C_CMD OBh Register 0Bh Bank C I C_CMD Master 2 Command Register Read Write D7 be p5 p4 ps p2 p1 po Busy Read 0 Idle 1 Busy Write No effect Reset Read Return 1 Write 0 No effect 1 I C interface Reserved 2 Command See Table 5 1 Reserved Figure 5 4 Master IC Command Register The commands in Table 5 1 are the values that into 06 D5 and D4 of the Master 2 Command Register Software puts data for transmission into 2 Data Register I7C_DATA OAh OCh and reads received data from it Bit 7 of this register is used as an acknowledgment bit during receiving data from a Slave Bit 0 of DATA register contains an acknowledgment bit generated by Slave Register 0Ah Bank C 2 DATA Master 2 Data Register Read Write D7 pe ps p4 Dps p2 pilpo Data Read Received data Write Data to be sent Figure 5 5 Master 2 Data Register 5 6 In order to have appropriate sequence of command executed by the module software has to check Busy Bit bit 0 in the 2 CMD The busy bit is set to 1 at the beginning of each command executed by the module and stays 1 for the entire command cycle Then it changes to 0 Flowcharts of writing and reading a data frame for 2 devices with 7 bit addresses are shown in Figure 5 6 and Figure 5 7 The same algorithms can be used for devices with 10 b
48. Internal Microprocessor Overview Zilog 3 20 INTERRUPT SOURCES Table 3 9 presents the interrupt types sources and vectors that are available Table 3 9 Interrupt Types Sources and Vectors Vector Name Sources Location Comments IRQ0 IR Input 0 1 Edge Triggered Internal IRQ1 Hsync and Vsync Input 2 3 Edge Triggered Internal Generated at the start of every row and at the leading edge of the Vsync signal IRQ2 P62 4 5 External P62 Programmable Edge Triggered IRQ3 P63 6 7 External P63 Edge Triggered IRQ 4 TO 8 9 Internal IRQ5 T1 10 11 Internal 3 20 1 External Interrupt Source External interrupt source involves IRQ3 and IRQ2 and can be generated by a transition on Port 63 and Port 62 Multiple Signa Conditioning Circuitry System Clock Internal Figure 3 39 Interrupt Sources IRQ0 IRQ2 Block Diagram When the port 6 pin P63 and P62 transitions Note Although interrupts are edge triggered the first flip flop is set The next two flip flops minimum interrupt request low and high times synchronize the request to the internal clock and must be observed for proper operation See AC delay it by two internal clock periods The output Characteristics for exact timing requirements on of the last flip flop goes to D2 of the IRQ register external interrupt requests for P62 and D3 for P63 3 32 UM97TELO700 Zilog Z90230 Family of DTCs Internal Microprocessor Overview
49. Operation 3 2 Programmable ROM 3 10 Test Under Instruction 3 40 Mesh Effect 4 7 N Nesting Vectored Interrupts 3 40 Notation 3 57 O One Time Programmable ROM 3 10 On Screen Display Format 4 2 Oscillator Control uuu nasa aasan apas 3 12 Crystal Ceramic Resonator 3 15 3 13 Low anun TA 3 16 Operation 3 12 p Pierce Oscillator with Internal Feedback p 3 13 Pin 124 Pin Pin Out Diagram 2 4 Assignment 2 4 Descriptions 2 7 Z90231 and Z90233 Identification 2 2 Pointer Full Register File 3 4 ES pe oe usu aaa 3 11 Working Register Group 3 3 Polled Processing 3 40 Port 4 Pin Out Selection Register 2 13 8 2 Configuration Register 3 12 VOPOMS nte etate 6 1 Pin Out Selection Register 6 3 UM97TELO0700 290320 Family of DTCs Index Power On Reset 3 21 Reset Pin WDT and Recovery
50. Port 2 Control Register Write Only L Port 2 Output 0 Select Open Drain 1 Select Push Pull Reserved Must 0 Figure 2 17 Port 2 Control Register 2 20 UM97TEL0700 Zilog If P27 P26 are selected as 12 channel 1 or P25 P24 are selected as 12 channel 0 then selected pins in the 2 channel are automati cally set into open drain mode regardless of the 2 3 14 Interrupt Priority Register Register F9h IPR 290230 Family of DTCs Architectural Overview setting in this control register If P20 is used asa halftone pin then this pin becomes push pull regardless of the setting in this control register Interrupt Priority Register Write Only 2755254535559 Interrupt Group Bits Priority 000 Reserved 001 C gt A gt B 010 gt gt 011 gt gt 100 B gt CsA 101 gt gt 110 B gt A gt C 111 Reserved Group C and IRQ4 Priority 0 IRQ1 gt IRQ4 1 IRQ4 gt IRQ1 Group IRQO and IRQ2 Priority 0 IRQ2 gt IRQO 1 IRQO gt IRQ2 Group A IRQ3 and IRQ5 Priority 0 IRQ5 gt IRQ3 1 IRQ3 gt IRQ5 Reserved Must be 0 Figure 2 18 Interrupt Priority Register Whenever Power On Reset POR is executed the IRQ register is reset to 00h and the interrupt state machine is disabled Before the IRQ UM97TEL0700 Register can accept requests the IRQ register must be ena
51. TO internal timer 1 P62 and P63 must be configured as input if used as an interrupt source Data bits 6 and 7 set the P62 edge Some coding is required to clear P62 for input for example m To select Rising Edge for P62 interrupt DI disable all interrupts OR IRQ 49680 enable rising edge for P62 interrupt AND IRQ FB IRQ2 P62 interrupt keep other IRQ s bits untouched El enable interrupts m To select Rising and Falling Edge for P62 interrupt DI disable all interrupts OR IRQ C0 enable rising and falling edge for P62 interrupt clear IRQ2 bit P62 interrupt keep other IRQ s bits untouched AND IRQ FB 3 38 Zilog El enable interrupts The IMR is cleared before the IRQ enabling sequence to insure no unexpected interrupts occur when El is executed This code sequence should be executed prior to pro gramming the application required values for IPR and IMR Note IRQ bits 6 and 7 are device dependent When reserved the bits are not used and will return a 0 when read When used as the Interrupt Edge select bits the configuration options are as shown in the following table Table 3 13 IRQ Register Configuration IRQ Interrupt Edge D7 D6 P62 0 0 Falling 0 1 Falling 1 0 Rising 1 1 Rising Falling The proper sequence for programming the inter rupt select bits is assumes IPR and IMR have been previously initialized D
52. Z90230 Family of DTCs Zilog On Screen Display 4 3 2 Mesh Column End Register Register 05h Bank F MC_End Mesh Column End Register Read Write D7 pe bs p4 p3 p2 Dpi po T Mesh Window End Value Reserved Figure 4 15 Mesh Column End Register MC St and MC End define the width and hori zontal position of the mesh window 4 3 3 Mesh Row Enable Register Register 06h Bank F MR En Mesh Row Enable Register Read Write p7 pe p5 D4 D3 D2 D1 Do NEN Mesh Window Row 0 No mesh OSD for Next Row 1 Mesh OSD for Next Row Reserved Must be 0 Reserved Must be 0 Foreground Character for Halftone Effect 0 Not Included 1 Included Vai Delay 0000 No delay 0001 Delay by 0 5 Dot Clock Period 0010 Delay by 1 0 Dot Clock Period 0011 Delay by 1 5 Dot Clock Period 0100 Delay by 2 0 Dot Clock Period 0101 Delay by 2 5 Dot Clock Period 0110 Delay by 3 0 Dot Clock Period 0111 Delay by 3 5 Dot Clock Period 1000 Delay by 4 0 Dot Clock Period 1001 Delay by 4 5 Dot Clock Period 1010 Delay by 5 0 Dot Clock Period 1011 Delay by 5 5 Dot Clock Period 1100 Delay by 6 0 Dot Clock Period 1101 Delay by 6 5 Dot Clock Period 1110 Delay by 7 0 Dot Clock Period y 7 5 D 1111 Delay b ot Clock Period Figure 4 16 Mesh Row Enable Register Bits 7 6 5 and 4 VBLANK Delay is the amount Bit 3 Character Foreground for Halftone Effect of time that the VBLANK signal is
53. and Vsync must have the same polarity This feature is designed to provide flexibility for TV chassis designers TL M Positive SYNC LT LJ Negative SYNC Figure 4 3 Positive and Negative Sync Signals UM97TELO0700 Bit 3 Character Size sets the size of the charac ters that are displayed Two sizes are supported 1 X and 2X The default value is 1X To change the size of the characters in a row alter the value of the bit during the previous hori zontal interrupt The character size of the first row is programmed during vertical interrupt Vsync processing Character size is a row interrupt driven attribute Bits 2 1 and 0 Vertical Retrace Blanking sets a time period when the OSD is disabled while the electron gun returns from the bottom to the top of the screen and all VBLANK and RGB output are disabled The blanking period is determined by counting horizontal pulses as follows Blanking Period 4 x Vertical Retrace Blanking 2 x THL The retrace blanking bits OSD CNTL 2 1 0 must be set to deactivate the electron guns during the retrace period During vertical retrace no video information is available in the TV signal for display OSD should not be displayed at every retrace so it must be blanked out 4 3 Z90230 Family of DTCs On Screen Display 4 2 2 Vertical Position Register The Vertical Position Register sets the vertical placement of the OSD on the screen The unit of measure for placemen
54. capacitance Load 10pF lt CL lt 220 pF capacitance 15 typical Resistance 100 ohms max Depending on the operation frequency the oscil lator may require the addition of capacitors C1 and C2 shown in Figure 3 13 The capacitance values are dependent on the manufacturer s crystal specifications GND Z90230 XTAL1 XTAL2 Figure 3 13 Crystal Ceramic Resonator Oscillator UM97TELO0700 290230 Family of DTCs Internal Microprocessor Overview XTAL1 Z90230 GND XTAL2 Figure 3 14 LC Clock In most cases the RD is 0 Ohms and HF is infi nite It is determined and specified by the crystal ceramic resonator manufacturer The RD can be increased to decrease the amount of drive from the oscillator output to the crystal It can also be used as an adjustment to avoid clip ping of the oscillator signal to reduce noise The HF can be used to improve the start up of the crystal ceramic resonator The oscillator already has an internal shunt resistor in parallel to the crystal ceramic resonator XTAL1 290230 GND XTAL2 Figure 3 15 External Clock Itis recommended that the load capacitor ground trace be directly connected to the GND pin This ensures that no system noise is injected into the MCU clock This trace should not be shared with any other components except at the GND pin In some cases the XTAL1 pin also functions as one of the EPROM high voltage mode program ming pins or as a special fa
55. 04h Bank B PWM3 PWMS3 Data Register Read Write p7 pe ps p4 ps pz p po pl C PWMS Value Register 05h Bank B PWM4 PWMA Data Register Read Write 75824329 LL Value Register 06h Bank B PWM5 PWM5 Data Register Read Write 7 5 1 MES CES PWMb5 Value Register 07h Bank B PWM6 PWM6 Data Register Read Write p7 pe ps p4 pa p2 pi po 0 LLL PWM6 Value Register 08h Bank B PWM7 PWM7 Data Register Read Write 2756555435250 pre PWM7 Value Register 09h Bank B PWM8 PWMSB Data Register Read Write p7 be o5 p4 ps pe p bo ie PWMB8 Value Register 0Ah Bank B PWM9 PWM9 Data Register Read Write p7 ps ps p4 ps p2 pi po _ PWM9 Value Register 0Bh Bank B PWM10 PWM10 Data Register Read Write p7 pe ps p ps p2 p bo iesu PWM10 Value PWM1 Value Figure 8 5 PWM1 through PWM10 Registers Zilog UM97TELO700 Z90230 Family of DTCs Zilog Pulse Width Modulators Register 00h Bank B PWM11H PWM11 High Data Register Read Write 7 2 1 NN unum PWM 1 High Byte Reserved Register 01h Bank B PWM11L PWM11 Low Data Register Read Write 7 LL Low Byte Figure 8 6 PWM11 Register 8 1 4 Digital Analog Conversion via PWM The DTC can generate square waves which the pulse width of the square wave Cases A and have fixed periods but
56. 1 Port Configuration Register 2 1 1 6 1 Figure 6 2 Port 2 Mode Register DE nci rre ear ae ab die dead 6 2 Figure 6 3 Port 2 Data Register U een 6 3 Figure 6 4 Port 4 Pin Out Selection Register 6 4 Figure 5 Data 58 nu SS e C De i u Sa aee Pts 6 5 Figure 6 6 Port 4 Direction Control Register 6 6 Figure b PWM Mode Register ces Lebe ted 6 7 Figure 6 8 Port 5 Data Register dae aedes 6 8 Figure 6 9 Port 5 Direction Control Register des ope col be iege oe 6 9 Figure 6 10 Port 6 Data Register 2222244 4 1 122422 2 11 717 7221 12474 0 6 10 Figure 6 11 Port 6 Direction Control Register 6 11 Chapter 7 Infrared Interface Figure 7 1 Timer Control Register aoe es 7 2 Figure 7 2 Timer Gontrol Register ul Eco b t 7 3 Figure 7 3 IR Capture alee oe reed RE tu os 7 4 Figure 7 4 IR Capture Register 1 Depart eroe eques odo nc ep niger nr ee Dee Ee d 7
57. 10 3 10 RESET WATCH DOG TIMER This section describes the microcontroller reset conditions reset timing and register initialization procedures Reset is generated by Power On Reset POR Reset Pin Watch Dog Timer WDT and Stop Mode Recovery A system reset overrides all other operating conditions and puts the microcontroller into a known state To initialize the chip s internal logic the Reset input must be held Low for at least 5 XTAL clock cycles The control register and ports are reset to their default conditions after a POR 3 16 a reset from the Reset pin or WDT timeout while in RUN Mode and Halt Mode The control regis ters and ports are not reset to their default condi tions after Stop Mode Recovery and WDT timeout while in Stop Mode The program counter is loaded with 000Ch I O ports and control registers are configured to their default reset state Resetting the microcontroller does not effect the contents of the general purpose registers UM97TELO700 Zilog Z90230 Family of DTCs Internal Microprocessor Overview 3 11 RESET PIN INTERNAL POR OPERATION In some cases the microcontroller hardware 0 while bits whose states are unknown are indi Reset pin initializes the control and peripheral cated by the letter U registers Specific reset values are shown by 1 or Table 3 6 Sample Control and Peripheral Register Reset Values Register Re
58. 20 0101 5 MI Minus S21 0100 4 OV Overflow 1 1100 No Overflow V 0 3 58 UM97TEL0700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Table 3 25 Condition Codes Continued Binary HEX Mnemonic Definition Flag Settings 0110 6 EQ Equal Z 1 1110 E NE Not Equal Z 0 1001 9 GE Greater Than or Equal S XOR V 0 0001 1 LT Less Than S XOR V 1 1010 A GT Greater Than Z OR S XOR V 0 0010 2 LE Less Than or Equal Z OR S XOR V 1 1111 UGE Unsigned Greater Than or C 0 Equal 0111 7 ULT Unsigned Less Than C 1 1011 B UGT Unsigned Greater Than 0 AND Z 0 1 0011 ULE Unsigned Less Than or Equal C OR Z 1 3 40 NOTATION AND BINARY ENCODING In the detailed instruction descriptions that make Operands condition codes address modes and their notations are as follows up the rest of this chapter operands and status flags are represented by a notational shorthand Table 3 26 Notational Shorthand Notation Address Mode Operand Range Condition Code See condition codes r Working Register Rn 0 15 R Register Reg Reg represents a number in the range of 00h to FFh or Working Register Rn 0 15 RR Register Pair Reg Reg represents an even number in the range of 00h to FEh or Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 Ir Indirect Working Rn n 0 15 Register IR Indirect Register Reg Reg represents a n
59. 3 15 Figure 3 16 Capacitance Calculation 3 16 Figure 3 17 Reset TIMING usus suu 3 18 Figure 3 18 External Power On Reset Circuit Example 3 18 Figure 3 19 Microprocessor Reset with Reset Pin SMR and POR Example 3 19 Figure 3 20 Watch Dog Timer Mode Register Write Only Example 3 20 Figure 3 21 Counter Timers Block Diagram sse 3 22 Figure 3 22 Counter Timers Register 3 23 Figure 3 23 Prescalen T Register ese Dette at adress eed 3 23 Figure 3 24 Prescaler 0 Register 1 1 3 24 Figure 3 25 Counter Timer 0 and 1 Registers 3 24 Figure 3 26 Timer Mode Register 3 25 Figure 3 27 Starting The Count e oe o boite fi bio Dato nitur 3 25 Figure J 28 Counting MOGBS tene mh cu ten oret 3 25 Figure 3 29 Timer Mode Register Operation r 3 27 Figure 3 30 Prescaler 1 Register Operation 44 44 4414 4 1 44 6 3 27 Figure 3 31 Heysc Clock Input Mode tei prater ede tetti ere ee pre
60. 3 19 INTERRUPTS The microcontroller allows six different interrupts from a variety of sources up to four external inputs the on chip counter timer s software and serial peripherals These interrupts can be masked and their priorities set by using the Interrupt Mask and the Interrupt Priority Regis ters All six interrupts can be globally disabled by resetting the master interrupt enable bit 7 in the interrupt mask register with a Disable Interrupt DI instruction Interrupts are globally enabled by setting bit 7 with an Enable Interrupt El instruction Register Hex Identifier Interrupt Mask FBh IMR Interrupt Request FAh IRQ Interrupt Priority F9h IPR Figure 3 37 Interrupt Control Registers There are three interrupt control registers the Interrupt Request Register IRQ the Interrupt Mask register IMR and the Interrupt Priority Register IPR Figure 3 37 shows addresses and identifiers for the interrupt control registers Figure 3 38 is a block diagram showing the Inter rupt Mask and Interrupt Priority logic UM97TELO0700 290230 Family of DTCs Internal Microprocessor Overview The Z8 MCU family supports both vectored and polled interrupt handling Details on vectored and polled interrupts can be found later in this chapter IRQO IRQ5 Global Interrupt Enable Interrupt Priority Logic Vector Select Figure 3 38 Interrupt Block Diagram 3 31 Z90230 Family of DTCs
61. 3 40 1 Assembly Language Syntax For proper instruction execution assembly produced by the assembler This binary format language syntax requires dst src be specified in that order The following instruction descrip tions show the format of the object code 3 60 should be followed by users who prefer manual program coding or who intend to implement their own assembler UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Example The contents of registers 43h and 08h are added and the result is stored in 43h The assembly syntax and resulting object code are ASM ADD 43h 08h ADD dst src OBJ 04 08 43 OPC src dst 97 0700 3 61 Z90230 Family of DTCs Internal Microprocessor Overview Zilog 3 62 UM97TELO700 4 1 INTRODUCTION The On Screen Display OSD generates and displays a 10 row by 24 columns of 256 charac ters at 14 x 18 dots resolution The color of each character is specified on a row basis The DTC detects Hsync and Vsync signals to synchronize its internal circuitry to the video signal then outputs RGB and Video Blank VBLANK signals The VBLANK signal is used to multiplex the OSD signal and video signal onto the screen The result is that the On Screen Display is superimposed over the TV picture UM97TELO0700 USER S MANUAL CHAPTER 4 ON SCREEN DISPLAY The display results from the successful timing of several components m OSD Positioning m Seco
62. 8 Crystal Oscillator Input 31 Crystal Oscillator Output 32 Dot Clock Oscillator Input 28 Dot Clock Oscillator Output 29 Horizontal Synchronization 26 Vertical Synchronization 27 Video Blanking 25 Video Red Green Blue 24 23 22 4 Bit Analog to Digital Converter 9 10 11 12 Input Device Reset 33 Note 1 When Pins 39 42 are configured for 2 pins 39 and 40 comprise one channel and pins 41 and 42 comprise another channel UM97TELO0700 2 3 Z90230 Family of DTCs Architectural Overview Zilog 2 2 2 Z90239 124 Pin PGA Ceramic Package Pin Out Diagram Z90239 ICE chip contains more pins than Figure 2 2 illustrates the pin assignment of the the production devices The additional pins Z90239 ICE chip Following the figure Table 2 2 provide internal values that are valuable during describes the assignment for each pin design activities 123456 7 8 9 10111213 OOOOOOOOOOOOO OOOOOOOOOO 290239 Top View gt OOOOOOOOOO OOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOO Figure 2 2 Z90239 124 PGA Ceramic Package Pin Out Diagram 2 2 3 Z90239 Pin Assignment The function of each pin of the Z90239 ICE chip is described in the table below Table 2 2 Z90239 Pin Assignments 2 1 OSD Dot Clock D3 Oscillator Input OSD Dot Clock C2 Osc
63. B D Bar Display u suasana ioco bx dte rrt 45 p If Not Z 3 51 Binary encoding 3 57 2 EIOS Diagram Circuit Board Rules 3 14 Device eee ere 2 0 Indications of Unreliability 3 13 Interrupt Peer rere ere errr rere eee reer eee ee ee eee 3 30 Digital Analog Conversion via PWM P 8 7 Direct Register Map 3 50 C Disable au al o etri eene 3 34 CALL Interrupts and Polled Processing 3 40 Direct Addressing Mode 3 50 3 11 CGROM Notes 419 EMI Noise Reduction E 1 UM97TEL0700 Index 1 Z90320 Family of DTCs Index Enable COUNT Ss asc d teen 3 26 dU 3 34 Interrupt and Polled Processing 3 40 Interrupts Instruction and IRQ Register 3 35 Error Conditions 3 4 Expanded Register File 2 14 3 5 F etri 4 15 Features 1 1 Flags ers decet 3 55 Condition Codes 3 56 Decimal Adjust 3 55 Definitions 3 56 3 55 OverfloW
64. CHAPTER 2 ARCHITECTURAL OVERVIEW stores settings for the On Screen Display that is output through the hardware device and debugging OTP and production devices utilizes a 42 pin SDIP format Pin identification and assignments are provided below for both formats 2 1 Z90230 Family of DTCs Architectural Overview Zilog PWM11 P56 PWM6 P55 PWM5 P54 PWM4 P53 PWM3 P52 PWM2 P51 PWM1 P50 P40 P60 ADC3 Pet ADC2 r 10 490231 P41 ADC1 p 11 290233 P62 ADCO AGND P42 P43 P63 P44 PWM7 P45 PWM8 P46 PWM9 P47 PWM10 P20 HLFTN Top View Figure 2 1 290231 and 290233 Pin Identification Note The pins on the Z90230 are assigned to Note In this and the following sections all perform the functions identified in Table 2 1 Signals with an overbar are active Low 2 2 UM97TELO700 Z90230 Family of DTCs Zilog Architectural Overview Table 2 1 Z90230 Family OTP and Production Pin Assignment 5 Volts 0 Volts Infrared Remote Capture Input 14 bit Pulse Width Modulator Output 6 Bit Pulse Width Modulator 20 19 18 17 2 3 4 Output 5 6 7 Bit Programmable I O Ports 1 2 3 4 5 6 7 Bit Programmable Ports 42 41 40 39 38 37 35 21 Halftone Output 21 I2C Data Bidirectional 40 421 Send Receive Serial Data Lines 2 Clock 39 411 Bit Programmable I O Ports 16 12 10 9 Bit Programmable I O Ports 20 19 18 17 15 14 11
65. Carry Flag C is set to 1 whenever the result of an arithmetic operation generates a carry out of or a borrow into the high order bit 7 Other wise the carry flag is cleared to 0 An instruction can set reset or complement the carry flag 3 38 2 Zero Flag For arithmetic and logical operations the Zero Flag Z is set to 1 if the result is 0 Otherwise the Zero Flag is cleared to If the result of testing bits in a register is the Zero Flag is set to 1 Otherwise the Zero Flag is cleared to O If the result of a Rotate or Shift operation is 00h the 3 38 3 Sign Flag The Sign Flag S stores the value of the most significant bit of a result following an arithmetic logical ROTATE or SHIFT operation When performing arithmetic operations on signed numbers binary two s complement notation is used to represent and process information A positive number is identified by a 0 in the most 3 38 4 Overflow Flag For signed arithmetic ROTATE and SHIFT operations the Overflow Flag V is set to 1 when the result is greater than the maximum possible number 2127 or less than the minimum possible number 128 that can be represented in two s complement form The 3 38 5 Decimal Adjust Flag The Decimal Adjust Flag D is used for BCD arithmetic Since the algorithm for correcting BCD operations is different for addition and subtraction this flag specifies what type of instruction was last executed so that the subse
66. Control Register D 12 3 Bit ADC Data Register D 12 Timer Control Register 0 D 13 Timer Control Register 1 D 13 IR Capture Register 0 D 13 IR Capture Register 1 D 14 97 0700 USER S MANUAL APPENDIX D REGISTERS Description Page Port 4 Data Register D 14 Port 4 Direction Control Register D 15 HV Interrupt Status Register D 16 Port 4 Pin Out Selection Register D 16 Color Index Register D 17 Master I C Data Register D 17 Master 2C Command Register D 17 Master I C Control Register D 18 Port Configuration Register D 19 4 Bit ADC Data Register D 19 Port 6 Direction Control Register D 20 Port 6 Data Register D 21 Mesh Column Start Register D 21 Mesh Column End Register D 22 Mesh Row Enable Register D 22 Mesh Control Register D 23 Stop Mode Recovery Register D 24 Watch Dog Timer Mode Register D 24 Stack Pointer Low Register
67. Data Output on P42 Data Input on P43 Data Output on P43 Data Input on P44 Data Output on P44 Data Input on P45 Data Output on P45 Data Input on P46 Data Output on P46 Data Input on P47 Data Output on P47 Figure 6 5 Port 4 Data Register UM97TEL0700 6 5 Z90230 Family of DTCs Input Output Ports 6 1 6 Port 4 Direction Control Register 6 6 Register 06h Bank C PRT4_DRT Port 4 Direction Control Register Read Write 2755432225 i P40 I O Definition 0 Defines P40 as Output 1 Defines P40 as Input POR P41 I O Definition 0 Defines P41 as Output 1 Defines P41 as Input POR P42 I O Definition 0 Defines P42 as Output 1 Defines P42 as Input POR P43 I O Definition 0 Defines P43 as Output 1 Defines P43 as Input POR P44 I O Definition 0 Defines P44 as Output 1 Defines P44 as Input POR P45 I O Definition 0 Defines P45 as Output 1 Defines P45 as Input POR P46 I O Definition 0 Defines P46 as Output 1 Defines P46 as Input POR P47 Definition 0 Defines P47 as Output 1 Defines P47 as Input POR Figure 6 6 Port 4 Direction Control Register Zilog UM97TELO700 Zilog 6 1 7 Port 5 UM97TEL0700 PWM Mode Register Register 0Dh Bank B P_MODE PWM Mode Register Read Write 07 06 05 04 03 02 D1 Do _____ PWM 1 0 Select PWM 1 1 Select P50 POR PWM2 0 Select PWM 2
68. P25 Data Output on P25 Data Input on P26 Data Output on P26 Data Input on P27 Data Output on P27 6 1 4 Port 4 Pin Out Selection Register Bits 5 4 3 and 2 control the configuration of This value is the default following a Power multiplexed pins 20 19 18 17 If a bitis Reset If a bit is set to 1 the pin functions as reset to 0 the pin functions as a PWM output a programmable regular input output port UM97TELO0700 6 3 Z90230 Family of DTCs Input Output Ports Zilog Register 08h Bank C PIN SLT Port 4 Pin Out Selection Register Read Write D7 pe Dbs p4 p3 p2 Dpi Do MENT Reserved Reserved P44 PWM7 0 Selects PWM7 1 Selects P44 POR P45 PWM8 0 Selects PWM8 1 Selects P45 POR P46 PWM9 0 Selects PWM9 1 Selects P46 POR P47 PWM10 0 Selects PWM10 1 Selects P47 POR Reserved Figure 6 4 Port 4 Pin Out Selection Register 6 4 UM97TELO700 Zilog 6 1 5 Port 4 Data Register Register 05h Bank C PRT4_DTA Port 4 Data Register Read Write D7 D6 25 D4 0322 01 00 P40 Read Write P41 Read Write P42 Read Write P43 Read Write P44 Read Write P45 Read Write P46 Read Write P47 Read Write Z90230 Family of DTCs Input Output Ports Data Input on P40 Data Output on P40 Data Input on P41 Data Output on P41 Data Input on P42
69. POWER DOWN HALT MODE OPERATION The Halt Mode suspends instruction execution and turns off the internal CPU clock The on chip oscillator circuit remains active so the internal clock continues to run and is applied to the counter timer s and interrupt logic To enter the Halt Mode it is necessary to first flush the instruction pipeline to avoid suspending execution in mid instruction To do this the appli cation program must execute a NOP instruction opcode FFh immediately before the Halt instruction opcode 7Fh that is FF NOP clear the instruction pipeline enter Halt Mode The Halt Mode is exited by interrupts either externally or internally generated Upon comple tion of the interrupt service routine the user program continues from the instruction after Halt The Halt Mode may also be exited via a POR Reset activation or a Watch Dog Timer WDT timeout See the product data sheet for 97 0700 WDT availability In this case program tion restarts at the reset restart address 000Ch To further reduce power consumption in the Halt Mode some Z8 family devices allow dynamic internal clock scaling Clock scaling may be accomplished on the fly by reprogramming bit 0 and or biti of the Stop Mode Recovery register SMR Note Internal clock scaling directly effects Counter Timer operation adjustment of the prescaler and downcounter values may be required To determine the
70. SCLK 16 The IR capture counter is driven by the clock generated by dividing the system clock of the 290230 7 3 Z90230 Family of DTCs Infrared Interface Zilog 7 1 3 IR Capture Register 0 Register 03h Bank C IR_CP0 IR Capture Register 0 Read D7 pe ps p4 ps p2 pi po IR Capture Register 0 Reading Low Byte of IR Capture Counter Figure 7 3 IR Capture Register 7 1 4 IR Capture Register 1 Register 04h Bank C IR_CP1 IR Capture Register 1 Read D7 pe ps p4 ps p2 pi po IR Capture Register 1 Reading High Byte of IR Capture Counter Figure 7 4 IR Capture Register 1 7 4 UM97TEL0700 Z90230 Family of DTCs Zilog Infrared Interface 7 1 5 IR Decoding Start IR Routine No Timer Out Counter Overflow Yes Is It Expected Signal MN Falling Rising Yes Check Capture Timing lt Yes Increment Bit Full Byte Transaction Yes Process Byte Is Transmission Complete Initialize IR Capture Parameter Exit IR Routine Figure 7 5 IR Decoding Flowchart Example Note This flow chart does not include processing a start bit which some protocols require UM97TEL0700 7 5 Z90230 Family of DTCs Infrared Interface Zilog The Full Byte Transaction conditional statement user s responsibility to determine the number of does not necessarily require a full byte It is the bits required to decode the IR signal 7 6 UM97TELO700 8 1 PULSE WIDTH MODULATORS The Z9023
71. UM97TELO700 Zilog NUMBER AND TITLE Chapter 3 Internal Microprocessor Overview Continued Figure 3 47 Interrupt Vectors in Memory Figure 3 48 Interrupt Acknowledge Timing Figure 3 49 Stop Mode Recovery Register Figure 3 50 Stop Mode Recovery Source Level Select Figure 3 51 8 Bit Register Addressing Figure 3 52 4 Bit Register Addressing Figure 3 53 8 Bit Indirect Register Addressing Figure 3 54 4 Bit Indirect Register Addressing Figure 3 55 Indexed Register Addressing Figure 3 56 Direct Addressing m oni edere Figure 3 57 Relative Addressing 1 1 1 Figure 3 58 Immediate Data Addressing Figure Flag REgIStET to d pend Ee de Chapter 4 On Screen Display Figure d 1 OSD FORMAL etes Figure 4 2 OSD Control Register Figure 4 3 Positive and Negative Sync Signals Figure 4 4 Vertical Position Re
72. actual Halt mode current ICC1 value for the various optional modes available see the selected microcontroller device s product specification 3 43 Z90230 Family of DTCs Internal Microprocessor Overview 3 28 STOP MODE OPERATION The Stop Mode provides the lowest possible device standby current This instruction turns off the on chip oscillator and internal system clock To enter the Stop Mode it is necessary to first flush the instruction pipeline to avoid suspending execution in mid instruction To do this the appli cation program must execute a NOP instruction opcode FFh immediately before the Stop instruction opcode 6Fh that is FF NOP 6F Stop clear the instruction pipeline Stop Mode The Stop Mode is exited by any one of the following resets Power On Reset activation WDT timeout if available or a Stop Mode Recovery source Upon reset generation the processor always restarts the application program at address 000 POR Reset activation is present on all Z8 base devices and is implemented as a reset pin and or an on chip power on reset circuit Some microcontrollers allow for the on chip WDT to run in the Stop Mode If so activated the WDT timeout generates a Reset some fixed time period after entering the Stop Mode Note Stop Mode Recovery SMR by the WDT increases the Stop Mode standby current ICC2 This is due to the WDT clock and divider circuitry that is now enabled and runnin
73. and PIN SLT registers for ADC control and I O mode selec tions Input Selection 00 Select ADC0 POR 01 Select ADC1 10 Select ADC2 11 Select ADC3 ADC Speed 00 No ADC POR 01 SCLK 2 10 SCLK 3 11 SCLK 4 Reserved Figure 2 4 3 Bit ADC Data Register UM97TELO0700 Z90230 Family of DTCs Architectural Overview Zilog 2 3 2 4 Bit ADC Data Register Register 01h Bank F 4ADC_DTA 4 Bit ADC Data Register Read Write 1 ADC Input Selection 00 Select ADC0 POR 01 Select ADC1 10 Select ADC2 11 Select ADC3 ADC Speed 00 No ADC POR 01 SCLK 2 10 SCLK 3 11 SCLK 4 Figure 2 5 4 Bit ADC Data Register P41 must be set to input mode for ADC 1 selection 2 12 UM97TEL0700 Z90230 Family of DTCs Zilog Architectural Overview 2 3 3 Port 4 Pin Out Selection Register Register 08h Bank C PIN SLT Port 4 Pin Out Selection Register Read Write 07 5 4 02 1 00 BEEN Reserved Reserved P44 PWM7 0 Selects PWM7 1 Selects P44 POR P45 PWM8 0 Selects PWM8 1 Selects P45 POR P46 PWM9 0 Selects PWM9 1 Selects P46 POR P47 PWM10 0 Selects PWM10 1 Selects P47 POR Reserved Figure 2 6 Port 4 Pin Out Selection Register UM97TELO700 2 13 Z90230 Family of DTCs Architectural Overview 2 3 4 Expanded Register File Register
74. as Input P25 I O Definition 0 Defines P25 as Output 1 Defines P25 as Input P26 I O Definition 0 Defines P26 as Output 1 Defines P26 as Input P27 I O Definition 0 Defines P27 as Output 1 Defines P27 as Input Figure D 56 Port 2 Mode Register Register F5h PREO R245 ms ro rite Only ae Count Mode 0 Single Pass 1 TO Modulo N Clock Source Must be 1 Prescaler Modulo Range 1 63 Decimal 01 3Fh Figure D 57 Prescaler 0 Register D 28 UM97TELO700 Z90230 Family of DTCs Zilog Registers Register F4h T0 R244 Counter Timer 0 Register Write Read 27285423229 Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure D 58 Counter Timer 0 Register Register F3h PRE1 R243 Prescaler 1 Register Write Only 2765453229 Count Mode 0 Single Pass 1 71 Modulo N Clock Source 0 T1 External Timing Input Hsync 1 Internal Prescaler Modulo Range 1 63 decimal 01 3Fh Figure D 59 Prescaler 1 Register Register F2h T1 R242 Counter Timer 1 Register Write Read b7pspspapspep po Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure D 60 Counter Timer 1 Register D 29 UM97TELO0700 Z90230 Family of DTCs Registers Zilog Register F1h TMR R241 Timer Mode
75. be configured in standard drive mode PCON 00h Bank F when the 2 interface is active P2CNTL 0 P2M 1 Input q a 0 Output PAD DATA Output T P2 Output 77 2 Selection e P2 Input DATA Input e Enable b For 2 e Figure 5 2 Bidirectional Port Pin Pad Multiplexed with IC Port 5 4 UM97TELO700 Zilog 5 7 1 Master Control Register Register 0Ch Bank C I C_CNTL Master 2 Control Register Read Write D7 D6 D5 D4 D3 D2 1 00 290230 Family of DTCs Interface 12 Speed For 6 MHz XTAL 00 10 KHz 01 50 KHz 10 100 KHz 11 330 KHz 2 Enable 0 Disable 2 interface 1 Enable 2 interface Reserved Must be 0 2 Selection 0 0 P24 selection POR default P25 selection POR default 1 SCLKO selection on P24 SDATAO selection on P25 2 Selection 1 0 P26 selection POR default P27 selection POR default 1 SCLK1 selection on P26 SDATAt selection on P27 Reserved Figure 5 3 Master 2 Control Register If bits D4 and D5 both equal 1 then the Selection 0 prevails 97 0700 5 5 Z90230 Family of DTCs Interface Zilog 5 8 SOFTWARE CONTROL OF THE 2 INTERFACE Software controls the 2 module by writing appropriate commands into the 2 Command Register
76. bits 6 and 7 are device dependent When reserved the bits are not used and will P62 Input return a 0 when read When used as the Interrupt P63 Input Edge select bits the configuration options are as shown in the following table TO Internal Timer T1 Internal Timer Note P62 and P63 must be configured as input if used as an interrupt source Data bits 6 and 7 set the P62 edge Some coding is required to clear P62 for input 2 22 UM97TELO700 Z90230 Family of DTCs Zilog Architectural Overview Table 2 4 IRQ Register Assembly code assumes IPR and IMR have Configuration been previously initialized IRQ Interrupt Edge DI Inhibit all D7 D6 P62 sinterrupts 0 0 Falling input edges 0 1 Falling configured 1 0 Rising OR 000000B Configure interrupt 1 1 Rising Falling not disturb sedges as needed The proper sequence for programming the inter IRQ 0 5 rupt edge select bits is shown in the following El Re enable interrupts 2 3 16 Interrupt Mask Register Register FBh IMR Interrupt Mask Register Read Write 2722524532559 IRQ0 0 Disables IRQ0 1 Enables IRQ0 IRQ1 0 Disables IRQ1 1 Enables IRQ1 L IRQ2 0 Disables IRQ2 1 Enables IRQ2 IRQ3 0 Disables IRQ3 1 Enables IRQ3 IRQ4 0 Disables IRQ4 1 Enables IRQ4 IRQ5 0 Disables IRQ5 1 Enables IRQ5 RAM Protect 0 Disables RAM Protect 1 Enables RAM Protect Interrupt Enable 0
77. changed except Register FBh IMR Zilog m Immediately after a hardware reset Immediately after executing interrupt service routine and before IMR 7 has been set by any instruction Interrupt Mask Register Read Write 2722554532559 IRQ0 0 Disables IRQ0 1 Enables IRQ0 IRQ1 0 Disables IRQ1 1 Enables IRQ1 IRQ2 0 Disables IRQ2 1 Enables IRQ2 IRQ3 0 Disables IRQ3 1 Enables IRQ3 IRQ4 0 Disables IRQ4 1 Enables IRQ4 IRQ5 0 Disables IRQ5 1 Enables IRQ5 RAM Protect 0 Disables RAM Protect 1 Enables RAM Protect Interrupt Enable 0 Disables Interrupt 1 Enables Interrupt Figure 3 43 Interrupt Mask Register Notes 1 The RAM Protect option is selected at ROM mask submission time or at EPROM program time If not se lected or not an available option this bit is reserved and must be 0 3 22 3 Interrupt Request Register Initialization An Interrupt Request Register IRQ Figure 3 44 is a read write register that stores the inter rupt requests for both vectored and polled inter rupts When an interrupt is made on any of the six the corresponding bit position in the register is set to 1 Bit 0 to bit 5 are assigned to interrupt requests IRQ0 to IRQ5 respectively 3 36 Whenever Power On Reset POR is executed the IRQ register is reset to 00h and disabled Before the IRQ register will accept requests it must be enabled by
78. configured identi Note Port 2 must be configured to output for cally with the exception of bit D3 on expanded halftone effect Register Bank F MC REG For halftone effect set bit D3 to 1 For mesh set bit D3 to O MC St 04h Bank F Reg 07h Bank F HEIDE E Mesh Starts Column 2 Mesh Enabled Reserved MC_End 05h Bank F Display the Even Field xx xX 1 of 7 of Normal Mesh X X X 1 1 1 Blue Mesh Color x Mesh Window is 21 Blue Green Red Reserved Halftone Output Delay on P20 MR_En 06h Bank F fof of ofo No Mesh OSD for Next Row Reserved Reserved Foreground Character for Halftone VBLANK Delay Figure 4 20 Mesh Window Display Registers for Row 7 Example The values of these registers would remain unchanged for the remaining rows of the field 4 4 OSD FADE Fading is the gradual disappearance of the OSD Fade control registers must be updated only Fading occurs vertically up or down Figure 4 21 during Vsync not during row interrupt Other demonstrates the fade down effect wise unexpected results might occur Figure 4 21 Video Fade Example 4 16 UM97TELO700 Zilog CONTRAST CONTRAST CONTRAST CONTRAST 60 290230 Family of DTCs On Screen Display UM97TEL0700 4 17 Z90230 Family of DTCs On Screen Display This feature is controled through the FADE_POS1 FADE_POS2 and ROW_SPACE registers Register 05h
79. egister in One Operand Register File Instruction Example Points to Register of Operand Figure 3 53 8 Bit Indirect Register Addressing Value Used in Instruction Execution UM97TELO0700 3 49 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Register File Register Pair LB Points to Origin of Workin Register Group Program Memory 4 Bit Workin Register Working Register Instruction Example Pair Even References Either Address Program Memory or Data Memory 16 Bit Address Points to Program or Data Memory Program or Data Memory Figure 3 54 4 Bit Indirect Register Addressing Value Used in Instruction 3 50 UM97TELO700 Zilog 3 33 INDEXED ADDRESSING The Indexed Addressing Mode is used only by the Load LD instruction An indexed address consists of a register address offset by the contents of a designated working Program Memory Address dst X src OpCode Two Operand Instruction Points to Working Register Offset 290230 Family of DTCs Internal Microprocessor Overview register the Index This offset is added to the register address to obtain the address of the operand Figure 3 55 illustrates this addressing convention Register File Points to Origin of Workin Register roup Offset Value Used in Instruction Figure 3 55 Indexed Register Addressing UM97TELO0700 3 51 Z90230 F
80. executing an ENABLE INTERRUPTS El instruction Note Setting the Global Interrupt Enable bit in the Interrupt Mask Register IMR bit 7 does not UM97TEL0700 Zilog enable the IRQ Execution of the El instruction is required Figure 3 44 UM97TEL0700 Z90230 Family of DTCs Internal Microprocessor Overview For polled processing IRQ must still be initial ized by an El instruction To properly initialize the IRQ register the following code is provided CLR IMR sure disabled vectored interrupts El enable IRQ register otherwise read only not needed if interrupts were previously enabled DI disable interrupt heading Note An IRQ is always cleared to 00h and is read only until the first El instruction which enables the IRQ to be read write Register FAh IRQ Interrupt Request Register Read Write bpe sp pspap po L IRQ0 0 IRQ0 Reset 1 IRQ0 Set IRQ1 0 IRQ1 Reset 1 IRQ1 Set IRQ2 0 IRQ2 Reset 1 IRG2 Set IRQ3 0 IRQ3 Reset 1 IRQ3 Set IRQ4 0 IRQ4 Reset 1 IRQ4 Set IRQ5 0 IRQ5 Reset 1 IRQ5 Set P62 Edge Falling Edge 10 Rising Edge 11 Rising Falling Edge Figure 3 44 Interrupt Request Register 3 37 Z90230 Family of DTCs Internal Microprocessor Overview The functions of the IRQs are as follows Table 3 12 IRQ Function Summary IR input HVsync input P62 input P63 input
81. group 0 No other standard registers are effected since only working register group 0 is implemented in ERF bank C Access to the ERF is accomplished through the register pointer FDh The lower nibble of the register pointer determines the ERF bank while the upper nibble determines the working register group within the register file 0111 1100 Working Expanded Register Register Group Bank Select ERF Bank C h Working Register Group 7 h Figure 3 6 Register Pointer FDh Example The value of the lower nibble in the register pointer FDh corresponds to the ERF bank iden tification Table 3 2 shows the lower nibble value and the register file assigned to it The upper nibble of the register pointer selects the group of 16 bytes in the register file out of the full 256 to be accessed as working registers 97 0700 Z90230 Family of DTCs Internal Microprocessor Overview R253 RP 00h ERF Bank 0 Working Reg Group 0 R0 Reserved 00h R1 Reserved 01h R2 Port 2 02h R3 Reserved 03h R11 GPR 0Bh R15 GPR 0Fh If R253 RP OFh ERF Bank F Working Reg Group 0 RO PCON 00h R1 4 _ 01h R2 PRT6_DRT 02h R11 SMR 0Bh R15 0Fh If R253 RP ERF Bank F Working Reg Group F RO Reserved 00h PCON R1 TMR 01 4ADC_DTA R2 T1 02h PRT6_DRT R11 IMR SMR R15 SPL OFh WDTMR Note Enabling an ERF bank
82. properly defines whether display of a foreground color for aligned with the OSD RGB output with delay character display is included If bit 3 is set to 0 from external circuitries halftone is disabled for pixels with foreground UM97TELO0700 4 11 Z90230 Family of DTCs On Screen Display color If bit 3 is set to 1 halftone is active for pixels with both foreground and background colors Bit 2 Character Background Color with Halftone Effect on P20 is Reserved and must be 0 4 3 4 Mesh Control Register Register 07h Bank F MC_Reg Mesh Control Register Read Write D7 D6 D5 D3 D2 D1 00 L Mesh Enable 0 Mesh is Disabled 1 Mesh is Enabled Software Mesh 0 Hardware Defines Field Number 1 Software Defines Field Number Software Field Number Polarity of Halftone Effect Output 0 Even Field Positive Halftone Effect Output 1 Odd field Negative Halftone Effect Output P20 for Halftoning 0 Normal Mesh 1 Use P20 Output for Halftoning Mesh Color Zilog Bit 1 Character Background Display Enable is Reserved and must be 0 Bit 0 Mesh Window Row sets the mesh window to On or Off for the next row of the OSD Halftone Effect Output Delay on P20 Bits 5 4 in ROW_SPACE 7 00 0 No Delay 00 1 Delay by 0 5 Dot Clock Period 01 0 Delay by 1 0 Dot Clock Period 01 1 Delay by 1 5 Dot Clock Period 10 0 Delay by 2 0 Dot Clock Period 10 1 Delay by 2 5
83. steer b ai tbe a edn hls 3 24 3 16 2 Prescaler Operations 3 25 3 17 TIN PAGS NRI RR m ER UT DUDEN ROC 3 26 3A Fale lock Input us u u u seres dee a nitentes d draco 3 27 3 18 Counter Timer Reset CORCITIOFIS 3 27 ire e HUE IRR MU HU MEME 3 30 9 20 IMTS PENSE OU CSS a aca pes Cobre eee bac tent cee ay 3 31 3 20 1 External Interrupt Source acit eee ese eth A Anc LA LA dA 3 31 3 21 Interrupt Request Register Logic and Timing 3 32 iv UM97TELO0700 Z90230 Family of DTCs Zilog Table of Contents CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 3 Internal Microprocessor Overview Continued 3 22 Initialization 2 2 3 32 3 22 1 Interrupt Priority Register Initialization 3 33 3 22 2 Interrupt Mask Register Initialization 2 0 3 34 3 22 3 Interrupt Request Register Initialization 3 35 3 23 IRQ Software Interrupt GenerallOlt s der e in citur rudi iE RES 3 37 3 24 Vectored is iere toti P pee dede gom cbe
84. system software must configure the control register for the preferred ADC The converted 3 bit data is available as bits 0 1 and 2 of the data register 3ADC_DTA 00h Bank The converted 4 bit data is available as bits 0 1 2 and 3 of the 4ADC data register 4ADC_DTA 01h Bank 97 0700 USER S MANUAL APPENDIX B ANALOG PERIPHERALS Four input pins P60 ADC3 P61 ADC2 P41 ADC1 and P62 ADCO function as analog input channels and as digital ports To sup port the analog function the digital ports must be configured as analog through software Ana log digital selection is controlled by bits D4 and D3 of the 3ADC Data Register for 3 bit and D5 and D4 of 4 ADC Data Register for 4 bit If ADC Input Selection equals 00 ADCO is selected this value is the default following POR If ADC Input Selection equals 01 ADC1 is selected If ADC Input Selection equals 10 ADC2 is selected If ADC Input Selection equals 11 ADC3 is select ed Sampling occurs at one eighth of an ADC clock tick On ADC clock tick equals one half third or quarter of a system clock SCLK tick as set by 3ADC_DTA 6 5 for 3 bit or 4 0 7 6 for 4 bit If ADC speed bits are set to 00 the ADC is not operative this is the default value following POR If these bits equal 01 ADC speed is based on one half of a system clock tick SCLK 2 If these bits equal 10 ADC speed is based on one third of a system clock
85. the bus and generates the clock signals to enable the transfer The non initiating device is designated as the Slave The 12 bus is multi Master bus That is more than one device capable of controlling the bus can be connected at any given time Generation 5 2 DATA VALIDITY Data on the SDATA line must be stable during the High clock period Figure 5 1 The High and 5 3 START AND STOP CONDITIONS Within the procedure of the I C bus unique situ ations arise which are defined as Start and Stop conditions One such unique case is when a High to Low transition of the SDATA line while the SCLK line is High This situation indicates a Start condition A Low to High transition of the 5 4 DATA TRANSFER Data transfer follows the procedure illustrated in Figure 5 1 At the Start condition the address of a Slave device is sent This address is 7 bits long UM97TELO0700 USER S MANUAL CHAPTER 5 2 INTERFACE of clock signals on the I C bus is always the responsibility of Master devices Each Master generates its own clock signals when transfer ring data Bus clock signals from a Master can only be altered when they are stretched by a slow Slave device retaining the clock line at Low Both SDATA and SCLK are bidirectional lines connected to a positive supply voltage via pull up resistors When the bus is free both lines are High The output stages of devices connected to the bus must have an open drain or open collect
86. 0 Disables the Second Color Feature 1 Enables the Second Color Feature Figure D 10 Second Color Control Register Register 08h Bank A SNDCLR Second Color Register Read Write D7 D6 D5 D4 Ds 22 01 00 Second Color Position HV sync Interrupt Option 0 Interrupt Pending Disabled 1 Interrupt Pending Enabled Reserved Figure D 11 Second Color Register D 6 UM97TELO700 Zilog UM97TELO700 290230 Family of DTCs Registers Register 09h Bank A CLR Color Palette 0 Read Write 27592354352 Color Programming ROf ROb G0b BOb Reserved Figure D 12 Color Palette 0 Register 0Ah Bank CLR_P1 Color Palette 1 Read Write Ppp a E Programming R1f G1f B1f R1b G1b B1b Reserved Figure D 13 Color Palette 1 Register 0Bh Bank CLR_P2 Color Palette 2 Read Write 2725254232129 EN RGB Color Programming R2f G2f B2f R2b G2b B2b Reserved Figure D 14 Color Palette 2 Register Bank A CLR P3 Color Palette 3 Read Write b7pspsp p pep os vet sss Programming R3f G3f B3f R3b B3b Reserved Figure D 15 Color Palette 3 D 7 Z90230 Family of DTCs Registers Zilog Register 0Dh Bank A CLR_P4 Color Palette 4 Read Write 2728255432519 Color Programming R4f G4f B4f R4b G4b B4b Reserved Figure D 16 Color Palette 4
87. 0 Family of DTCs Internal Microprocessor Overview WDT can be permanently enabled through a ROM option Permanently enabled WDTs are always enabled and the WDT instruction is used to refresh it The WDT circuit is driven by an on board RC oscillator Note Execution of the WDT instruction affects the Z zero S sign and V overflow flags Watch Dog Timer Mode Register Write Only WDT TAP 00 6 ms 01 12 ms POR 10 24 ms 11 96 ms WDT During Halt 0 Off 1 POR Reserved Must be 0 Figure 3 20 Watch Dog Timer Mode Register Write Only Example Note The WDTMR register is accessible only during the first 60 processor cycles from the execution of the first instruction after Power On Reset Watch Dog Reset or a Stop Mode Recovery After this point the register cannot be modified by any means intentional or otherwise The WDTMR is a Write Only register The WDTMR is located in Expanded Register File Bank F register 0Fh The control bits are described as follows WDT Time Select T1 T0 Bits 0 and 1 control a tap circuit that determines the time out period Table 3 8 shows the different values that can be obtained The default value of D1 and D0 are 0 and 1 respectively UM97TEL0700 Table 3 8 Time Out Period of the WDT Minimum Time Out of Time Out of D1 D0 Internal RC OSC 0 0 6 ms min 0 1 12 ms min 1 0 24 ms min 1 1 96 ms min Notes The default
88. 0 family has 11 Pulse Width Modu lator channels PWMs 1 through 10 have 6 bit resolution and are typically used for audio and video level control PWM 11 has 14 bit resolution and is typically used for voltage synthesis tuning The PWM control registers are mapped into ERF Bank B Table 8 1 Expanded Register File Bank B Register Working Register Function Register E PRT5 DRT R14 D P MODE R13 PRT5_DTA R12 B PWM10 R11 A PWM9 R10 8 1 1 PWM Mode Register PWM Mode Register controls the setting of the multiplexed pins 1 7 These pins can be config ured to function as PWM output ports or regular UM97TEL0700 USER S MANUAL CHAPTER 8 PULSE WIDTH MODULATORS Table 8 1 Expanded Register File Bank B Register Working Register Function Register 9 PWM8 R9 8 PWM7 R8 7 PWM6 R7 6 PWM5 R6 5 PWM4 R5 4 PWM3 R4 3 PWM2 R3 2 PWM1 R2 1 11 Low Byte H1 0 PWM 1 High Byte HO PWM 11 uses two registers to accommodate its 14 bit resolution There are 6 bit and 14 bit binary counters for the 6 bit and 14 bit PWMs The counter value is compared with the respective PWM register value and an output flip flop is set to 1 when the values match The flip flop is reset to 0 when the counter section reaches zero All PWM registers and their respective output flip flops are cleared to zero after reset therefore all PWM ports are set to Low as an initial state Table 8 2 Pulse Width Mod
89. 00 Selects background foreground color in row attribute 001 Selects color palette 0 in color look up table 010 Selects color palette 1 in color look up table 011 Selects color palette 2 in color look up table 100 Selects color palette 3 in color look up table 101 Selects color palette 4 in color look up table 110 Selects color palette 5 in color look up table 111 Selects color 6 in color look up table There are eight different foreground background palettes including the 000 case that reads the color s from the ROW_ATTR register mapped into video RAM UM97TEL0700 4 25 Z90230 Family of DTCs On Screen Display Zilog 4 7 3 Color Table and Color Index Register Register 09h Bank C CLR_IDX Color Index Register Read Write D7 D6 D5 D4 D3 D2 D1 00 Index Defines the Color Palette Selection Bits Reserved Figure 4 31 Color Index Register When software reads the Color Index Register palette that contains the RGB foreground and for the Color Index the 5 unused bits bits 7 3 background colors to be displayed In the Color return 1s Palette register descriptions below the following notation is used When the Color Index has a value other than 000 the value indicates the number of the color Rnf Red n Palette Number f Foreground Rnb Red n Palette Number b Background Gnf G Green n Palette Number f Foreground Gnb G Green n Palette Number b Bac
90. 1 Select P51 POR PWM 3 0 Select PWM 3 1 Select P52 POR PWM 4 0 Select PWM 4 1 Select P53 POR PWM 5 0 Select PWM 5 1 Select P54 POR PWM 6 0 Select PWM 6 1 Select P55 POR PWM 11 0 Select PWM 11 1 Select P56 POR Reserved Figure 6 7 PWM Mode Register 290230 Family of DTCs Input Output Ports 6 7 Z90230 Family of DTCs Input Output Ports Zilog 6 1 8 Port 5 Data Register Register 0Ch Bank B PRT5_DTA Port 5 Data Register Read Write D7 06 D5 D2 D1 00 P50 Read Data Input on P50 Write Data Output on P50 P51 Read Data Input on P51 Write Data Output on P51 P52 Read Data Input on P52 Write Data Output on P52 P53 Read Data Input on P53 Write Data Output on P53 P54 Read Data Input on P54 Write Data Output on P54 P55 Read Data Input on P55 Write Data Output on P55 P56 Read Data Input on P56 Write Data Output on P56 Reserved Figure 6 8 Port 5 Data Register 6 8 UM97TELO700 Zilog 6 1 9 Port 5 Direction Control Register Register 0Eh Bank C PRT5_DRT Z90230 Family of DTCs Input Output Ports Port 5 Direction Control Register Read Write D7 D6 Ds D4 D3 D2 D P50 I O Definition 0 Defines P50 as Output 1 Defines P50 as Input POR P51 I O Definition 0 Defines P51 as Output 1 Defines P51 as Input POR P52 I O Definition 0
91. 2 5 Dot Clock Period 11 0 Delay by 3 0 Dot Clock Period 11 1 Delay by 3 5 Dot Clock Period Figure D 45 Mesh Control Register Zilog Register 07h Bank F MC_Reg Mesh Control Register Read Write 07 D6 D5 D4 D3 D2 D1 Do UM97TELO700 D 23 Z90230 Family of DTCs Registers Zilog Hegister Bank F SMR Stop Mode Recovery Register Write Only Except Bit D7 Which Is Read Only Pppp SCLK TCLK Divide by 16 0 Off POR 1 On External Clock Divide by 2 0 SCLK TCLK XTAL 2 POR 1 SCLK TCLK XTAL n Stop Mode Recovery Source 000 POR and or External Reset 001 P63 010 P62 011 Must not be used 100 Must not be used 101 P27 110 P2 NOR 0 3 111 P2 NOR 0 7 Stop Dela 0 rt 1 Stop Recovery Level 0 Low POR 1 High Stop Flag Read Only 0 POR 1 Stop Recovery Figure D 46 Stop Mode Recovery Register Register OFh Bank F WDTMR Watch Dog Timer Mode Register Write Only BI _ WDT TAP 00 6 ms 012 12 ms POR 10 24 ms 11 96 ms 1 On POR Reserved Must 0 WDT During Halt ff Figure D 47 Watch Dog Timer Mode Register D 24 UM97TELO700 Z90230 Family of DTCs Zilog Registers Register FFh SPL Stack Pointer Low Read Write 07 06 05 04 03 2 01 0 Figure 0 48 Stack Pointer Low Register Stack Pointer Lower Byte SP0 SP7 Register FEh SPH Stack Pointer
92. 3 Program Control 3 53 Rotate and Shift 3 53 Test Under Mask 3 40 Interrupts Acknowledge Timing 3 40 Control registers 3 30 Description 3 30 Effects on Stack 3 38 Initialization 3 32 IRQ0 IRQ2 Block Diagram 3 31 Mask Register Initialization 3 34 Polled Processing 3 40 Priority Register Initialization 3 33 Processing 4 27 Request Register Configuration 2 23 3 37 Request Register Initialization 3 35 Request Register Logic and Timing 3 32 Request Register Map 2 22 3 36 Request Register Reset Functional Logic Diagram 3 37 Return Instruction 3 34 Service Routine 7 3 Software Generation 3 37 SOURCES MT a 3 30 Vectored Cycle Timing 3 39 Vectored Nesting 3 40 J Jump Conditional and Direct Addressing 3 50 Conditional and Flag Register 3 54 Relative TEN 3 51 UM97TELO700 Zilog L LC Network Oscillator 3 16 M Mask
93. 3 21 INTERRUPT REQUEST REGISTER LOGIC AND TIMING Figure 3 40 shows the logic diagram for the Interrupt Request IRQ Register The leading edge of the request sets the first flip flop which remains set until interrupt requests are sampled Requests are sampled internally during the last clock cycle before an op code fetch Figure 3 41 External requests are sampled two internal clocks earlier due to the synchronizing flip flops shown in Figure 3 40 and Figure 3 41 IRQO IRQ5 At sample time the request is transferred to the second flip flop in Figure 3 40 that drives the interrupt mask and priority logic When an inter rupt cycle occurs this flip flop will be reset only for the highest priority level that is enabled The user has direct access to the second flip flop by reading and writing the IRQ Register IRQ is read by specifying it as the source register of an instruction and written by specifying it as the destination register To Mask and Priority Logic Figure 3 40 IRQ Register Logic Mn M1 M2 Interrupt Request Sampled Internally External Interrupt Request Sampled Figure 3 41 Interrupt Request Timing 3 22 INTERRUPT INITIALIZATION After reset all interrupts are disabled and must be initialized before vectored or polled interrupt 97 0700 processing can begin The Interrupt Priority Register IPR Interrupt Mask Register IMR 3 33 Z90230 Family of DTCs Internal Microproc
94. 4 Figure 7 5 IR Decoding Flowchart Example sese 7 5 xii UM97TELO700 Zilog NUMBER AND TITLE Chapter 8 Pulse Width Modulators Figure 8 1 PWM Mode Register 222 222 2 2 Figure 8 2 Port 4 Pin Out Selection Register Figure 8 3 Pulse Width Modulator Timing Diagram 6 Bit Figure 8 4 Pulse Width Modulator Timing Diagram 14 Bit Figure 8 5 PWM1 through PWM10 Registers Figure 8 6 PWM11 Register Figure 8 7 Analog Signals Generated from PWM Signals Appendix B Analog Peripherals Figure B 1 3 Bit ADC Data Register Figure B 2 4 Bit ADC Data Register Figure 3 ADC Block Diagram Appendix D Registers Figure D 1 Expanded Register File Figure D 2 Register and Expanded Register File Figure D 3 OSD Control Register Figure D 4 Vertical Position Register Figure D 5 Horizontal Position Register Figure D 6 Display Attribute Register
95. 5 Reset 1 IRQ5 Set P62 Edge Falling Edge 10 Rising Edge 11 Rising Falling Edge Figure D 53 Interrupt Request Register D 26 UM97TELO700 Zilog UM97TELO700 290230 Family of DTCs Registers Register F9h IPR 1 Write Only Interrupt Group Bits Priority 000 Reserved 001 C gt A gt B 010 gt gt 011 gt gt 100 B gt CsA 101 gt gt 110 B gt A gt C 111 Reserved oup C IRQ1 and IRQ4 Priority RQ1 gt IRQ4 RQ4 gt IRQ1 IRQO and IRQ2 Priority gt IRQ0 IRQ0 gt IRQ2 and IRQ5 Priority IRQ5 gt IRQ3 IRQ3 gt IRQ5 __ Gro 0 1 Gro 0 1 Reserved Must be 0 Figure D 54 Interrupt Priority Register Register F7h P2CNTL Port 2 Control Register Write Only 7582345352 Too L Port 2 Output 0 Select Open Drain 1 Select Push Pull Reserved Must be 0 Figure D 55 Port 2 Control Register D 27 Z90230 Family of DTCs Registers Zilog Register F6h 2 Port 2 Mode Register Write Only P20 I O Definition 0 Defines P20 as Output 1 Defines P20 as Input P21 Definition 0 Defines P21 as Output 1 Defines P21 as Input P22 I O Definition 0 Defines P22 as Output 1 Defines P22 as Input P23 I O Definition 0 Defines P23 as Output 1 Defines P23 as Input P24 I O Definition 0 Defines P24 as Output 12 Defines P24
96. 90230 family of DTCs C 1 1 ICEBOX Family In Circuit Emula tors The Zilog ICEBOX product family of in circuit emulators are interactive Window oriented development tools featuring a real time environ ment for emulation and debugging 1 2 Z90219 Emulator 290219012 Packages Emulation Programming 42 Pin SDIP 290233 290234 Z90231 124 Pin PGA 290219 790239 C 1 3 Z90219 Emulation Module Z9020900TSC The Z90219 Emulation Module can be used like a One Time Programmable OTP for plug in emulation of the Z90230 family of devices in user target applications It provides external EPROMS to simulate an OTP and can be used repeatedly Its electrical characteristics are nearly identical with the OTP Packages Emulation 42 Pin SDIP 290233 290234 97 0700 1 4 Z89332 Evaluation Board Z8933200ZCO The Z89332 Evaluation Board enables users to become familiar with the functions of the Z89300 and Z90230 family of devices in TV VCR and Cable Box environments The board includes Z89 OTP pre programmed with sample code to demonstrate the Applications Programming Interface API Packages Supported Devices 42 Pin SDIP Z89331 289332 42 Pin SDIP 290233 290234 C 1 5 ICEBOX HP Logic Analyzer Adapter Board Z89C0000ZHP The ICEBOXHP Logic Analyzer Adapter Board provides users of the HP Logic Analyzer 165XX Series with real time trace capabilities for Zilog ICEBOX Emulators Captured code can be
97. Bank A FADE POS1 Fade Position Register 1 Read Write EH CA LA A eA eA E eA OSD Row Number for Fading Reserved Figure 4 22 Fade Position Register 1 Bits 3 2 1 and 0 defines the boundary row for the fade area The portion of the OSD above or 4 5 INTER ROW SPACING Register 04h Bank A ROW_SPACE Row Space Register Read Write 27 06 6524 03 2200 Zilog below the row number fades up or down as set in Fade Direction ROW_SPACE 6 The fade starts at the scan line set in FADE_POS2 4 3 2 1 0 within the row number set in FADE_POS1 3 2 1 0 Register 06h Bank A FADE_POS2 Fade Position Register 2 Read Write 276 D5 ps D2 pi po Scan Line of Each Character for Fading Reserved Figure 4 23 Fade Position Register 2 Inter Row Space Halftone Effect Output Delay On P20 Fade Direction 0 Fade Area Below the Defined Fade Position 1 Fade Area Above the Defined Fade Position Fade On Off 0 Fade Feature Disabled 1 Fade Feature Enabled Figure 4 24 Row Space Register Bit 7 Fade On Off disables or enables the fade effect When Fade On Off is reset to 0 the entire OSD is displayed When Fade On Off is set to 1 a portion of the OSD is transparent Bit 6 Fade Direction controls the direction the fade appears to move on the screen When Fade Direction is set to 0 fading moves toward the bottom of the TV screen Fading occurs beg
98. CMD Send DEAS Send ACK Receive data byte Read 2C_CMD 0 Busy 1 No Write 111 0 Send Stop bit Figure 5 7 Data Frame Read Flowchart UM97TELO700 5 9 USER S MANUAL CHAPTER 6 INPUT OUTPUT PORTS 6 1 INPUT OUTPUT PORTS There are 20 input output I O ports In addition I O ports available is 27 Please refer to the port seven pulse width modulators PWM PWM 1 bank and number carefully for exact addressing through PWM 6 and PWM 11 can be configured and access as regular output ports The maximum number of 6 1 1 Port Configuration Register Register 00h Bank F PCON Port Configuration Register Read Write 07 6 5 4 03 02 51 00 Reserved Low EMI OSD Oscillator 0 Low Noise 1 Standard POR Low EMI Port 4 and PWMs 0 Low Noise 1 Standard POR Reserved Low EMI Port 2 0 Low Noise 1 Standard POR Low EMI Port 6 0 Low Noise 1 Standard POR Low EMI Oscillator 0 Low Noise 1 Standard POR Figure 6 1 Port Configuration Register UM97TEL0700 6 1 Z90230 Family of DTCs Input Output Ports Zilog Ports 2 4 and 6 may be set for Standard or Low lator Standard 1 is the High setting Following EMI The Low EMI option can also be selected Power On Reset Bits 2 5 6 7 each has a value for the microcontroller oscillator or OSD oscil of 1 6 1 2 Port 2 Mode Register Register F6h
99. DTA 3 Bit ADC Data Register Read Write 2 1 Data ADC Input Selection 00 Select ADC0 POR 01 Select ADC1 10 Select ADC2 11 Select ADC3 ADC Speed 00 No ADC POR 01 SCLK 2 10 SCLK 3 11 SCLK 4 Reserved Figure D 25 3 Bit ADC Data Register D 12 UM97TEL0700 Z90230 Family of DTCs Zilog Registers Register 01h Bank C TCR0 Timer Control Register 0 Read Write D7 be p5 p4 ps p2 p1 po U Tout_CAP Read 0 No Timeout of the Capture Timer 1 Timeout of the Capture Timer Write 0 No Effect 1 Reset Flag CAPint_f Read 0 No Falling Edge is Captured 1 Falling Edge is Captured Write 0 No Effect 1 Reset Flag CAPint r Read 0 No Rising Edge is Captured 1 Rising Edge is Captured Write 0 No Effect 1 Reset Flag Reserved Figure D 26 Timer Control Register 0 Register 02h Bank C TCR1 Timer Control Register 1 Read Write D7 D6 D5 D4 D3 2 D1 Do CAP Speed 00 SCLK 32 01 SCLK 4 10 SCLK 8 11 SCLK 16 CAP Glitch 00 Glitch Filter Disabled 01 lt 2SCLK Filtered Out 10 lt 8SCLK Filtered Out 11 lt 16SCLK Filtered Out CAP Edge 00 No capture 01 Capture on Rising Edge Only 10 Capture on Falling Edge Only 11 Capture on Both Edges CAP Halt 0 Capture Timer Running 1 Capture Timer Halted Reserved Figure D 27 Timer Control Register 1 97
100. Display Row 7 Row 8 Row 9 3 4 5 6 7 8 9 03h Offset Column 0 Column 1 Column 2 Second Color Position Figure 4 10 Second Color Example In this figure a second color is displayed at Second Color Position 6 The second color position for the first column has a value of 3 because the OSD is offset from the left of the TV screen a distance equal to 03h Each column is the size of one display character Each Second Color column is a half column which is the same as a half character The screen position offset is added to the Second Color Position UM97TELO0700 In the example the offset is 03h Therefore Second Color Positions begin with 3 340 4 3 1 5 3 2 and so forth The change in color occurs at Second Color Position 6 Before displaying row 8 the value of SNDCLR CNTRL must be programmed as 11001000B and the value of SNDCLR is XX000110B The register values are illustrated in Figure 4 11 4 7 Z90230 Family of DTCs On Screen Display SNDCLR_CNTRL 07h Bank A Row 8 Second Color Red Enable Second Color SNDCLR 08h Bank A Second Color Position 6 HVsync Interrupt Option 0 Reserved Figure 4 11 Second Color Example Registers 4 3 MESH AND HALFTONE EFFECT Mesh is a grid like area that contains alternating pixel display of OSD and transparent zones The transparent zones allow the TV signal display to appear in part while the mesh display is active Halftone effe
101. Dot Clock Period 11 0 Delay by 3 0 Dot Clock Period 11 1 Delay by 3 5 Dot Clock Period Figure 4 17 Mesh Control Register Note The order of the colors differs from the order Red Green Blue of the Second Color field of the SNDCLR_CNTRL register Bit 7 Halftone Output Delay on P20 is the amount of time that output of the halftone signal 4 12 is delayed to compensate for the amount of delay of OSD RGB from external circuitries UM97TEL0700 Zilog Bits 6 5 and 4 Mesh Color defines the color of the mesh window The colors are specified in Blue Green Red order as shown in Table 4 1 Table 4 1 BGR Mesh Colors Black Red Green Blue Magenta Cyan White 0 1 0 1 Yellow 0 1 0 1 Bit 3 P20 for Halftone selects mesh or halftone effect If bit 3 is set to 1 P20 outputs halftone If reset to 0 P20 is a normal I O pin 290230 Family of DTCs On Screen Display Bit 2 Software Field Number Polarity of Halftone Output has several possible values The value of this bit remains the same for the entire mesh window it does not change from row to row If bit 3 is set to 1 halftone bit 2 defines the polarity of halftone output If bit 3 is reset to 0 and bit 1 is set to 1 then bit 2 defines the field number even or odd Bit 1 Software Mesh sets whether hardware or software defines the current field number When the value equals 0 hardware d
102. FCEO FCF8 2000 2018 2020 2038 41 D8 D9 D10 for Row 2 FE58 Row 2 Video RAM Buffer FE61 D8 D9 D10 for Row 3 FE78 Row 3 Video RAM Buffer FE81 D8 D9 D10 for Row 4 FE98 Row 4 Video RAM Buffer FEA1 D8 D9 D10 for Row 5 8 Row 5 Video RAM Buffer FEC1 D8 09 010 for Row 6 FED8 Row 6 Video RAM Buffer FEE1 D8 09 010 for Row 7 FEF8 Row 7 Video RAM Buffer FF01 D8 D9 D10 for Row 8 FF18 Row 8 Video RAM Buffer FF21 D8 09 D10 for Row 9 FF38 Row 9 Video RAM Buffer Figure 4 29 VRAM Address Map 4 24 UM97TELO700 Zilog Hardware processes the entire 11 bits of data at the same time it processes the OSD The Color Palette Selection Bits serve as a 3 bit Color Index to the color palette look up table Whenever software writes any Character Byte 1 Byte Data Color Index Register Jt Writing A Character Byte into Z90230 Family of DTCs On Screen Display data D0 D7 into VRAM it also takes the data in the color index register and writes the corre sponding Color Palette Selection Bits D8 D10 These three bits can be updated separately Figure 4 30 3 bits Data 01111 Writing Color Index Bits into VRAM Figure 4 30 Color Palette Selection Bits Update The Color Palette Selection Bits D8 D10 are decoded as follows Table 4 3 Color Palette Selection Bits Color Index Function 0
103. High Read Write D7 D6 D5 D4 D3 D1 00 Figure D 49 Stack Pointer High Register Stack Pointer Upper Byte SP8 SP15 Register FDh RP Register Pointer Read Write D7 D5 D4 D3 b2 D1 Defines Expanded Register File Defines Working Register Pointer Figure D 50 Register Pointer Register FCh Flags Flag Register Read Write 2 User Flag 1 User Flag F2 Half Carry Flag H Decimal Adjust Flag D Overflow Flag V Sign Flag S Zero Flag Z Carry Flag C Figure D 51 Flag Register UM97TELO700 D 25 Z90230 Family of DTCs Registers Zilog Register FBh IMR Interrupt Mask Register Read Write PPP L IRQ0 0 Disables IRQ0 1 Enables IRQ0 IRQ1 0 Disables IRQ1 1 Enables IRQ1 IRQ2 0 Disables IRQ2 1 Enables IRQ2 IRQ3 0 Disables IRQ3 1 Enables IRQ3 IRQ4 0 Disables IRQ4 1 Enables IRQ4 IRQ5 0 Disables IRQ5 1 Enables IRQ5 RAM Protect 0 Disables RAM Protect 1 Enables RAM Protect Interrupt Enable 0 Disables Interrupt 1 Enables Interrupt Figure D 52 Interrupt Mask Register Register FAh IRQ Interrupt Request Register Read Write bzpe pspaps apro IRQ0 IRQ0 Reset 1 IRQ0 Set IRQ1 IRQ1 Reset 1 IRQ1 Set IRQ2 IRQ2 Reset 1 IRQ2 Set IRQ3 IRQ3 Reset 1 IRQ3 Set RQ4 0 IRQ4 Reset 1 IRQ4 Set RQ5 0 IRQ
104. I Inhibit all interrupts until input edges are configured Configure interrupt not disturb edges as needed 0 5 EI Re enable interrupts OR IRQ XX 000000B UM97TELO700 Zilog El as Power On Reset POR 290230 Family of DTCs Internal Microprocessor Overview Interrupt Request Register IRQ FAh Figure 3 45 IRQ Reset Functional Logic Diagram 3 23 IRQ SOFTWARE INTERRUPT GENERATION An IRQ can be used to generate software inter rupts by specifying an IRQ as the destination of any instruction referencing the Standard Register File These Software Interrupts SWI are controlled in the same manner as hardware generated requests in other words the IPR and the IMR control the priority and enabling of each SWI level To generate a SWI the desired request bit in the IRQ is set as follows OR IRQ 3 24 VECTORED PROCESSING Each interrupt level has its own vector When an interrupt occurs control passes to the service routine pointed to by the interrupt s vector loca tion in program memory The sequence of events for vectored interrupts is as follows m PUSH the Program Counter PC lower byte on to the stack m PUSH the PC upper byte on to the stack m PUSH FLAGS on to the stack m Fetch the upper byte of the vector m Fetch the lower byte of the vector UM97TELO0700 where the immediate data NUMBER has a 1 in the bit position corresponding to th
105. Input POR P62 0 Data Output 1 Data Input POR P63 0 Data Output 1 Data Input POR P60 0 Open Drain Output 1 Push Pull Output POR P61 0 Open Drain Output 1 Push Pull Output POR P62 0 Open Drain Output 1 Push Pull Output POR P63 0 Open Drain Output 1 Push Pull Output POR Figure D 40 Port 6 Direction Control Register D 20 UM97TEL0700 Z90230 Family of DTCs Zilog Registers Register 03h Bank F PRT6 Port 6 Data Register Read Write 2755552455 P60 Read Data Input on P60 Write Data Output on P60 P61 Read Data Input on P61 Write Data Output on P61 P62 Read Data Input on P62 Write Data Output on P62 P63 Read Data Input on P63 Write Data Output on P63 Reserved Figure D 41 Port 6 Data Register Register 04h Bank F _51 Mesh Column Start Register Read Write 07 5 4 03 2 51 00 Mesh Window Start Value Reserved Figure D 42 Mesh Column Start Register Register 05h Bank F MC_End Mesh Column End Register Read Write D7 D6 D5 D4 D3 D2 D1 Do s Mesh Window End Value Reserved Figure D 43 Mesh Column End Register UM97TELO700 D 21 Z90230 Family of DTCs Registers D 22 Register 06h Bank F MR_En Mesh Row Enable Register Read Write D7 D6 D5 D4 D2 D1 00 NEN Mesh Window Row 0 No mesh OSD for Next Row 1 Mesh OSD for
106. M97TELO700 Zilog 7 1 2 Timer Control Register 1 Register 02h Bank C TCR1 Timer Control Register 1 Read Write D7 pe ps p4 ps p2 pi po Z90230 Family of DTCs Infrared Interface CAP Speed 00 SCLK 32 01 SCLK 4 10 SCLK 8 11 SCLK 16 CAP Glitch 00 Glitch Filter Disabled 01 lt 2SCLK Filtered Out 10 lt 8SCLK Filtered Out 11 lt 16SCLK Filtered Out CAP Edge 00 No capture 01 Capture on Rising Edge Only 10 Capture on Falling Edge Only 11 Capture on Both Edges CAP Halt 0 Capture Timer Running 1 Capture Timer Halted Reserved Figure 7 2 Timer Control Register 1 Bit 7 is Reserved Bit 6 resets the IR Capture Timer To stop the timer set this bit to 1 To start the timer set the bit to 0 Bits 5 and 4 set the IR Capture Edge The rising edge the falling edge or both edges of an input signal can be used as the source of IR interrupts If both edges are set as interrupt sources Timer Control Register 0 TCRO 01h bank C must be read and checked by the Interrupt Service Routine ISR in order to identify which edge has been captured Bits 3 and 2 contain a time constant used in a digital filter to process the IR Capture module in order to prevent errors UM97TELO0700 Bits 1 and 0 set the IR Capture Counter to one of four different speeds Table 7 2 IR Capture Timer Speed Setting TCR 1 0 Timer Speed 00 SCLK 32 01 SCLK 4 10 SCLK 8 11
107. Next Row Reserved Must be 0 Reserved Must be 0 Foreground Character for Halftone 0 Not Included 1 Included Delay 0000 No delay 0001 Delay by 0 5 Dot Clock Period 0010 Delay by 1 0 Dot Clock Period 0011 Delay by 1 5 Dot Clock Period 0100 Delay by 2 0 Dot Clock Period 0101 Delay by 2 5 Dot Clock Period 0110 Delay by 3 0 Dot Clock Period 0111 Delay by 3 5 Dot Clock Period 1000 Delay by 4 0 Dot Clock Period 1001 Delay by 4 5 Dot Clock Period 1010 Delay by 5 0 Dot Clock Period 1011 Delay by 5 5 Dot Clock Period 1100 Delay by 6 0 Dot Clock Period 1101 Delay by 6 5 Dot Clock Period 1110 Delay by 7 0 Dot Clock Period y 7 5 D 1111 Delay b ot Clock Period Figure D 44 Mesh Row Enable Register Zilog UM97TEL0700 Z90230 Family of DTCs Registers Mesh Enable 0 Mesh is Disabled 1 Mesh is Enabled Software Mesh 0 Hardware Defines Field Number 1 Software Defines Field Number Software Field Number Polarity of Halftone Output 0 Even Field Positive Halftone Output 1 Odd field Negative Halftone Output P20 for Halftoning 0 Normal Mesh Effect 1 Use P20 Output for Halftoning Mesh Color Halftone Output Delay on P20 xx x Bits 5 4 in ROW_SPACE 7 00 0 No Delay 00 1 Delay by 0 5 Dot Clock Period 01 0 Delay by 1 0 Dot Clock Period 01 1 Delay by 1 5 Dot Clock Period 10 0 Delay by 2 0 Dot Clock Period 10 1 Delay by
108. O E13 0 16 KB System ROM 1 32 KB System ROM E11 Analog Ground D12 Port 4 Pin 2 3 C13 A12 B13 D11 C12 A13 D10 C11 B12 M10 Port 6 Pin 3 C10 P44 PA7 PWMT PWM10 Port 4 Pin 4 5 6 7 PWM 7 8 9 10 B11 A11 C9 B9 ICE External ROM Selection B10 DTIMER Disable WDT TimerO Timer1 A10 GND Ground A9 P20 HLFTN Port 2 Pin 0 Halftone Output C8 MDATAO MDATA7 MCU Data B8 8 B7 C7 A7 B6 C6 B5 Blue Video A6 Green Video A5 Red Video A4 C5 2 6 Video Blank B4 UM97TELO700 Z90230 Family of DTCs Architectural Overview Table 2 2 Z90239 Pin Assignments Continued Horizontal Synchronization Vertical Synchronization Interrupt Acknowledge 2 2 4 Pin Descriptions 2 2 4 1 Single Purpose Pin Descriptions AGND Analog Ground B Blue CMOS output of the blue video signal B Y Video blue is programmable for either polarity CGADRO CGADR13 CGROM Addresses 0 through 13 CGDATA6 CGDATAO CGROM Data Input Pins 6 through 0 G Green CMOS output of the green video signal G Y Video green is programmable for either polarity GND Ground Horizontal Sync Pin input for external horizontal synchronization signal nterrupt Acknowledge ICE External ROM Selection IRIN nfrared Capture Input MAS MCU Address Strobe Ou
109. P2 NOR 0 7 Stop Recovery Level 0 Low PO Stop Flag Read Only 1 Stop Recovery Figure 3 49 Stop Mode Recovery Register m SCLK TCLK Divide by 16 Select DO This bit of the SMR controls a divide by 16 prescaler of SCLK TCLK The purpose of this control is to selectively reduce device power consumption during normal processor execution SCLK control and or Halt Mode where TCLK sources counter timers and interrupt logic External Clock Divide by Two D1 This bit can eliminate the oscillator divide by two circuitry When this bit is 0 the System Clock SCLK and Timer Clock TCLK are equal to 97 0700 the external clock frequency divided The SCLK TCLK is equal to the external clock frequency when this bit is set D1 1 Using this bit together with D7 of PCON helps further lower EMI D7 PCON 0 D1 SMR 1 The default setting is zero Stop Mode Recovery Source D2 D3 and D4 These three bits of the SMR specify the wake up source of the Stop Mode recovery Table 3 14 and Figure 3 50 3 45 Z90230 Family of DTCs Internal Microprocessor Overview Table 3 14 Stop Mode Recovery Source SMR 432 Operation D4 D3 D2 Description of Action 0 0 POR and or external reset recovery 0 0 1 P63 transition 0 1 0 P62 transition not in Analog Mode 1 0 1 P27 transition 1 1 0 Logical NOR of P20 through P23 1 1 1 Logical NOR of P20 through 27 Z
110. P2M Port 2 Mode Register Write Only b7pspspapspz pp3 P20 I O Definition 0 Defines P20 as Output 1 Defines P20 as Input P21 I O Definition 0 Defines P21 as Output 1 Defines P21 as Input P22 I O Definition 0 Defines P22 as Output 1 Defines P22 as Input P23 I O Definition 0 Defines P23 as Output 1 Defines P23 as Input P24 I O Definition 0 Defines P24 as Output 12 Defines P24 as Input P25 I O Definition 0 Defines P25 as Output 1 Defines P25 as Input P26 I O Definition 0 Defines P26 as Output 1 Defines P26 as Input P27 I O Definition 0 Defines P27 as Output 1 Defines P27 as Input Figure 6 2 Port 2 Mode Register When 27 26 or P25 P24 are used as C pins then these pins are automatically set to open drain mode 6 2 UM97TELO700 Zilog 6 1 3 Port 2 Data Register Register 02h P2 Port 2 Data Register Read Write D7 D6 D5 D4 D3 22 D1 Do P20 Read Write P21 Read Write P22 Read Write P23 Read Write P24 Read Write P25 Read Write P26 Read Write P27 Read Write Figure 6 3 Port 2 Data Register 290230 Family of DTCs Input Output Ports Data Input on P20 Data Output on P20 Data Input on P21 Data Output on P21 Data Input on P22 Data Output on P22 Data Input on P23 Data Output on P23 Data Input on P24 Data Output on P24 Data Input on
111. Pointer 92330633853 Working Register Group Pointer Expanded Register Bank Pointer Register File Reserved Expanded Register Reset Condition Register pz ps ps p4 ps pz po 5 wFE SPH RP FLAGS IMR IRQ 9 IPR F5 PRE0 1 Reserved Expanded Register Bank F Register Reset Condition F OE Reserved F OD Reserved OC Reserved B SMR OA Reserved 09 Reserved 08 Reserve 07 MC_Reg 06 MR_En 05 MC End ujujulo ol o ol o 04 MCSU B F 02 PRTe 01 4ADC DTA 0 0 o o Hilli fo 5 o S 25 5 5 aS LIL 8 mmm BIS mm o o 9 8 PN 2 70 2 gt L L m Register Reset Condition 0 03 Reserved 0 02 P2 0 01 Reserved 0 00 Reserved Figure 2 7 Register and Expanded Register File Map 2 14 UM97TELO700 Z90230 Family of DTCs Zilog Architectural Overview PWM 8 Data Register PWM8 09h PWM 9 Data Register PWM9 3 Bit ADC Data Register 00h PAMO TD Timer Control Register 0 TCRO 01h Port 5 Data Register 5 DTA 0 Timer Control Register 1 TCR1 02h PWM MODE Register P MODE IR Capture Register 0 IR 03h Port 5 Direction Register PRT5_DRT OEh IR Capture Register 1 IR_CP1 04h Port 4 Data Registe
112. Port 6 Pin 1 or Analog to Digital Converter Channel 2 Port 6 pin 1 is a program mable input or output line P41 ADC1 Port 4 Pin Analog to Digital Converter Channel 1 P63 Port 6 Pin 3 P63 input may be read directly at 03h A negative edge event is latched to IRQ 3 An IRQ3 vectored interrupt occurs if appropri ately enabled A typical application would place the device in Stop mode when P63 goes Low IRQ 3 interrupt routine When P63 subse quently goes High a Stop Mode Recovery is initiated P44 PWM7 Port 4 Pin 4 or Pulse Width Modu lator 7 Port 4 pin 4 is a programmable input or output port The PWM channel has 6 bit resolu tion P45 PWMB8 Port 4 Pin 5 or Pulse Width Modu lator 8 Port 4 pin 5 is a programmable input or output port The PWM channel has 6 bit resolu tion P46 PWMB8 Port 4 Pin 6 or Pulse Width Modu lator 9 Port 4 pin 6 is a programmable input or output port The PWM channel has 6 bit resolu tion P47 PWM10 Port 4 Pin 7 or Pulse Width Modu lator 10 Port 4 pin 7 is a programmable input or output port The PWM channel has 6 bit resolu tion PWM11 P56 Pulse Width Modulator 11 or Port 5 Pin 6 The PWM signal generator channel has 14 bit resolution Port 5 pin 6 is a programmable input or output port UM97TELO700 Zilog PWM6 P55 Pulse Width Modulator 6 or Port 5 Pin 5 The PWM signal generator channel has 6 bit resolution Port 5 pin 5 is a programmable input or output port
113. Register 6 7 6 1 8 Port Register 6 8 6 1 9 Port 5 Direction Control Register 6 9 0 110 Port 6 Data Registe o e ususikuna ete iet 6 10 6 1 11 Port 6 Direction Control Register 6 11 vi UM97TELO0700 Z90230 Family of DTCs Zilog Table of Contents CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 7 Infrared Interface Z la 7 1 TAs Tirer Gorntrol Register RR 7 2 Toles Timer Control Register i Suyu titan hH ukana 7 3 7 1 3 IR Capture Register 7 4 71 4 IY Capture Register ERRORI x Feet 7 4 7S IR DecodiNg mM cce cS 7 5 Chapter 8 Pulse Width Modulators 8 1 Pulse Width Modulators yale Rene date e petes 8 1 PWM Made Register count ore eoi a e aus 8 1 8 1 2 Port 4 Piri Out Selection Register 8 2 8 1 3 PWM1 through te qu 8 3 8 1 4 Digital Analog Conversion PWM 8 7 Appendix A Philips
114. Reserved Figure D 22 Port 5 Data Register D 10 UM97TELO700 Zilog UM97TEL0700 Register 0Dh Bank P_MODE PWM Mode Register Read Write D7 D6 D5 D4 D3 D2 D1 Do 290230 Family of DTCs p PWM 1 0 Select PWM 1 1 Select P50 POR PWM 2 0 Select PWM 2 1 Select P51 POR PWM 3 0 Select PWM 3 1 Select P52 POR PWM 4 0 Select PWM 4 1 Select P53 POR PWM 5 0 Select PWM 5 1 Select P54 POR PWM 6 0 Select PWM 6 1 Select P55 POR PWM 11 0 Select PWM 11 1 Select P56 POR Reserved Figure D 23 PWM Mode Register Registers Z90230 Family of DTCs Registers Zilog Register 0Eh Bank C PRT5_DRT Port 5 Direction Control Register Read Write 07 06 5 04 03 02 01 00 P50 I O Definition 0 Defines P50 as Output 1 Defines P50 as Input POR P51 I O Definition 0 Defines P51 as Output 1 Defines P51 as Input POR P52 I O Definition 0 Defines P52 as Output 1 Defines P52 as Input POR P53 I O Definition 0 Defines P53 as Output 1 Defines P53 as Input POR P54 I O Definition 0 Defines P54 as Output 1 Defines P54 as Input POR P55 I O Definition 0 Defines P55 as Output 1 Defines P55 as Input POR P56 I O Definition 0 Defines P56 as Output 1 Defines P56 as Input POR Reserved Figure D 24 Port 5 Direction Control Register Register 00h Bank C 3ADC_
115. SDATAO Selection on P25 2 Selection 1 0 26 Selection POR 27 Selection POR 1 SCLK1 Selection on P26 SDATA1 Selection on P27 Reserved Figure 0 37 Master Control Register Registers Register 0Ch Bank C I C_CNTL Master 2 Control Register Read Write D7 D6 D5 D4 D3 D2 51 00 D 18 UM97TELO700 Z90230 Family of DTCs Zilog Registers Register 00h Bank F PCON Port Configuration Register Read Write D7 pe bs p4 p3 p2 pi po Reserved Low EMI OSD Oscillator 0 Low Noise 1 Standard POR Low EMI Port 4 and PWMs 0 Low EMI Noise 1 Standard POR Reserved Low EMI Port 2 0 Low Noise 1 Standard POR Low EMI Port 6 0 Low Noise 1 Standard POR Low EMI Z8 Oscillator 0 Low Noise 1 Standard POR Figure D 38 Port Configuration Register Register 01h Bank F 4ADC_DTA 4 Bit ADC Data Register Read Write ADC Input Selection 00 Select ADC0 POR 01 Select ADC1 10 Select ADC2 11 Select ADC3 ADC Speed 00 No ADC POR 01 SCLK 2 10 SCLK 3 11 SCLK 4 Figure D 39 4 Bit ADC Data Register UM97TELO700 D 19 Z90230 Family of DTCs Registers Zilog Register 02h Bank F PRT6_DRT Port 6 Direction Control Register Read Write 72555545352 P60 0 Data Output 1 Data Input POR P61 0 Data Output 1 Data
116. Specification A 1 Philips 6 Specification ase fige D A 1 Appendix B Analog Peripherals B 1 Analog to Digital Converter xiii ai qe al gai gena B 1 B 1 1 3 Bit ADC Data Register B 2 B 2 4 BIt ADC Data Register t B 2 B 1 3 ADC Blok B 3 Appendix C Support Products 1 Z90230 Family Support Products gen teh a me cee ea n etes dos C 1 C 1 1 ICEBOX Family In Circuit Emulators C 1 1 2 Z90219 Emulator Z902 190 1Z tert pre eterne GE necs eee C 1 C 1 3 290219 Emulation Module 29020900 50 C 1 C 1 4 Z89332 Evaluation Board Z8933200ZCO C 1 1 5 ICEBOX HP Logic Analyzer Adapter Board Z89C0000ZHP C 1 C 1 6 Zilog Macro Cross Assembler ZMASMOWOZAS C 2 QT 7 ZMASM Supported Cores Devices C 2 Appendix D Registers BAN SI IIR il Ate a MAE aN D 1 Appendix E EMI Noise Reduction E 1 EMI Noise Reduction Through PCB Design 2
117. TpHsOH 2 28 Hsync Start To OSDX2 Start UM97TELO700 Z90230 Family of DTCs Zilog Architectural Overview XTAL1 IRQn Internal Reset External Reset HsyNc OSDX2 Figure 2 26 AC Characteristics UM97TEL0700 2 29 USER S MANUAL CHAPTER 3 INTERNAL MICROPROCESSOR OVERVIEW 3 1 ADDRESS SPACE Four address spaces are available for the Z90200 Family of Digital Television Controllers DTCs m The Standard Register File contains addresses for peripheral control all general purpose and all I O port registers This is the default register file specification 3 2 STANDARD REGISTER FILE The Standard Register File consists of up to 256 consecutive bytes registers The register file consists of 1 I O port 02h 236 General Purpose Registers 04h EFh and 16 Control 97 0700 The Expanded Register File contains addresses for control and data registers for additional peripherals features m ExternalProgram Memory contains addresses for all memory locations having executable code and or data m External Data Memory contains addresses for all memory locations that hold data only Registers FOh FFh Registers 00h 01h and 03h are reserved Table 3 1 shows the layout of the register file including register names loca tions and identifiers 3 1 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Table 3 1
118. When instructions are executed registers are read when defined as sources and written when defined as destinations All general purpose registers function as accumulators address pointers index registers stack areas or scratch pad memory UM97TELO700 Zilog 3 2 1 General Purpose Registers General Purpose Registers GPR are unde fined after the device is powered up The regis ters keep their last value after any reset as long as the reset occurs in the Vcc voltage specified operating range It does not keep its last state from a V y reset if Vcc drops below 1 8V 3 2 2 RAM Protect The upper portion of the register file address space 80h to EFh excluding the control regis ters may be protected from reading and writing The RAM Protect bit option is mask program mable and is selected by the customer when the ROM code is submitted After the mask option is 3 2 3 Working Register Groups Instructions can access 8 bit registers and register pairs 16 bit words using either 4 bit or 8 bit address fields 8 bit address fields refer to the actual address of the register For example register 58h is accessed by calling upon its 8 bit binary equivalent 01011000 58h With 4 bit addressing the register file is logically divided into 16 Working Register Groups of 16 registers each as shown in Table 3 4 These 16 registers are known as Working Registers A Register Pointer one of the control registers FDh contains the b
119. Working Register Groups Register Pointer FDh High Working Register Group Actual Registers Nibble Hex Hex 1111 b F FO FF 1110 b E EO EF 1101 b D DO DF 1100 b C CO CF 1011 5 BO BF 1010 b A 0 1001 b 9 90 9 1000 b 8 80 8F 0111 b 7 70 7 0110 b 6 60 6 0101 b 5 50 5 0100 b 4 40 4 0011 b 3 30 001 0 b 2 20 2F 0001 b 1 10 1 0000 b 0 00 0F Registers can be accessed as either 8 bit or 16 bit registers using Direct Indirect or Indexed Addressing All 236 general purpose registers can be referenced or modified by any instruction that accesses an 8 bit register without the need for special instructions Registers accessed as 16 bits are treated as even odd register pairs there are 118 valid pairs In this case the data s Upper Byte UB is stored in the even numbered register while the Lower Byte LB goes into the next higher odd numbered register Hn Rn 1 n Even Address Figure 3 1 16 Bit Register Addressing By using a logical instruction and a mask indi vidual bits within registers can be accessed for bit set bit clear bit complement or bit test oper 3 2 ations For example the instruction AND R15 MASK performs a bit clear operation op 1 AND R15 DFh Clear Bit 5 of Working Register 15 R 5 Figure 3 2 Accessing Individual Bits Example
120. Write Read Counter Time 0 Register Write Read 7 5 4 1 Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure 3 25 Counter Timer 0 and 1 Registers 3 16 COUNTER TIMERS OPERATION Under software control counter timers are started and stopped via the Timer Mode Register TMR Fih bits D3 D2 D1 D0 Each 3 16 1 Load and Enable Count Bits Setting the Load bit D0 for T0 and D2 for T1 transfers the initial value in the prescaler and the counter timer registers into their respective down counters The next internal clock resets bits D0 and D2 to 0 readying the load bit for UM97TEL0700 counter timer is associated with a Load bit and an Enable Count bit the next load operation New values may be loaded into the down counters at any time If the counter timer is running it continues to do so and starts the count over with the new value Therefore the load bit actually functions as a software re trigger 3 25 Z90230 Family of DTCs Internal Microprocessor Overview Register F1h TMR R241 Timer Mode Register Read Write 11 1 5 Load 0 No Function 1 2 Load TO TO Count 0 Disable TO Count 1 Enable TO Count Load T1 0 No Function 1 Load T1 Count 0 Disable T1 Count 1 Enable T1 Count Figure 3 26 Timer Mode Register The counter timers remain at rest as long as the Enable Coun
121. al time events such as counting The device is housed in a 42 pin SDIP and timing and data communication two on chip provides an ideal reliable solution for high counter timers with a large number of user volume consumer television applications selectable modes are implemented Table 1 1 Z90200 Family Product Summary 1 10 124 Channels 42 SDIP 3 bit 4 Channels 10 42 SDIP 3 bit 4 Channels 10 124 PGA 3 bit 4 Channels 10 42 SDIP 3 bit 4 Channels 10 124 4 bit 4 Channels 10 42 SDIP 4 bit 4 Channels 10 42 SDIP 4 bit 4 Channels 10 124 4 bit 4 Channels 10 42 SDIP 4 bit 4 Channels 10 42 SDIP 4 bit 4 Channels 10 42 SDIP 4 bit 4 Channels 10 UM97TELO0700 42 SDIP 4 bit 4 Channels 10 1 3 2 1 INTRODUCTION The Z90239 Digital Television Controller func tions as the result of the interaction between hardware and software series of registers 2 2 HARDWARE Two formats are used for this family of devices The Z90239 in a 124 Pin PGA ceramic package is used with the ICEBOX Emulator during design 2 2 1 Pin Identification Figure 2 1 shows the pin numbers for the OTP and production device format Following the figure Table 2 1 describes the function that each pin is assigned to UM97TEL0700 USER S MANUAL
122. alere dti ed nee at ei debe eda eb eaa 3 58 Chapter 4 On Screen Display Table 4 1 BGR Mesh Colors u ua n unu uu ma a Aa V 4 12 Table 4 2 RGB Colors 2 000000 0 00 0 000 4 21 Table 4 3 Color Palette Selection 4 24 Chapter 5 12 Interface Table 5 1 Master 12 Bus Interface Commands 5 7 Chapter 7 Infrared Interface Table 7 1 IR Interrupt Captured Values r nnn 7 2 Table 7 2 IR Capture Timer Speed 7 3 Chapter 8 Pulse Width Modulators Table 8 1 Expanded Register File Bank ba pn Se eel iei e pal 8 1 Table 8 2 Pulse Width Modulator Pin Functional Description Example 8 1 xviii UM97TELO700 1 1 FEATURES The Z90230 Family of Digital Television Control lers DTCs features a variety of RAM and ROM options together with a host of advanced On Screen Display OSD features to support high end graphics The display resolution is particu larly suitable for Asian languages Advanced features include m New Color Palette System m Flexible Inter Row Spacing m Higher Character Cell Resolution 1 2 GENERAL DESCRIPTION The Z90200 DTC family consists of three basic device types Z90200 Z90220 and Z90230 The Z90200 family supports the IC communication standard via software The Z90220 family supports closed caption de
123. amily of DTCs Internal Microprocessor Overview Zilog 3 34 DIRECT ADDRESSING The Direct Addressing mode as shown in Jump JP and Call CALL instructions use this Figure 3 56 specifies the address of the next addressing mode instruction to be executed Only the Conditional Program Memory Program Memory Address Used Lower Address Byte Upper Address Byte OpCode Figure 3 56 Direct Addressing 3 52 UM97TELO700 Zilog 3 35 RELATIVE ADDRESSING In the Relative Addressing RA Mode illustrated in Figure 3 57 the instruction specifies a two s complement signed displacement in the range of 128 to 127 This is added to the contents of the program counter PC to obtain the address of the next instruction to be executed Program Memory Next OpCode Displacement JR DJNZ OpCode Current PC Value 290230 Family of DTCs Internal Microprocessor Overview The PC prior to the add consists of the address of the instruction following the Jump Relative JR or Decrement and Jump if Not Zero DJNZ instruction JR and DJNZ are the only instruc tions which use this addressing mode Program Memory Address Used Figure 3 57 Relative Addressing UM97TELO0700 3 53 Z90230 Family of DTCs Internal Microprocessor Overview 3 36 IMMEDIATE DATA ADDRESSING Immediate IM Data is considered an addressing mode for the purposes of this discus sion It is the only addressing mode tha
124. are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Z8 MCU is a registered trademark of Zilog Inc ICEBOX is a trademark of Zilog Inc The I C specification is reprinted with the permission of the copyright owner Philips Interna tional BV copyright 1992 Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 FAX 408 370 8056 Internet http www zilog com
125. ase address of the active working register group The high nibble of the register pointer determines the current Working Register Group 290230 Family of DTCs Internal Microprocessor Overview Note Registers in banks EO EF may only be accessed through the working register and indirect addressing modes Direct access cannot be used because the 4 bit working register address mode already uses the format E dst where dst represents the working register number from Oh to Fh selected the user activates this feature from the internal ROM code to turn off on the RAM protect by loading either a 0 or 1 into IMR D6 A 1 in D6 enables RAM protect Only devices that use registers 80h to EFh offer this feature When accessing one of the working registers the 4 bit address of the working register is combined within the upper four bits high nibble of the register pointer forming the actual 8 bit address Figure 3 3 illustrates this operation Since working registers are typically specified by short format instructions fewer bytes of code are needed which reduces execution time In addition when processing interrupts or changing tasks the register pointer speeds context switching A special Set Register Pointer SRP instruction assigns a new value to the register pointer 1 Register Pointer FDh Standard Register File INC Instruction Short Format o io 1 0 Actual Regis
126. bled by executing an Enable Inter rupts El instruction 2 21 Z90230 Family of DTCs Architectural Overview Zilog 2 3 15 Interrupt Request Register m Toselect Rising Edge for P62 interrupt Register FAh IRQ Interrupt Request Register Read Write 27553546352 DI disable all interrupts IRQ0 ORIRQ 80 enable rising edge for P62 0 IRQO Reset interrupt 1 IRQ0 Set gt p IRQ1 AND IRQ FB clear IRQ2 P62 interrupt 0 IRQ1 Reset bi 1 IRO Set keep other IRQs bits IRQ2 untouched 0 IRQ2 Reset El enable interrupts 1 IRQ2 Set 0 IRQ3 Reset tr 1 IRQ3 Set m To select Rising amp Falling Edge for P62 IRQ4 i 0 IRQ4 Reset Interrupt 1 IRQ4 Set IRQ5 0 IRQ5 Reset ssl DI disable all interrupts 0X Falling Edge ORIRQ C0 enable rising amp falling edge 10 Rising Edge for P62 interrupt 11 Rising Falling Edge AND IRQ FB clear IRQ2 bit P62 interrupt keep other IRQ s bits untouched Figure 2 19 Interrupt Request Register EI enable The functions of the IRQs are as follows Table 2 3 IRQ Function Summary The IMR is cleared before the IRQ enabling sequence to insure no unexpected interrupts occur when El is executed This code sequence should be executed prior to programming the application required values for IPR and IMR IR Input HVsync Input Note IRQ
127. called the Master 4 7 1 Display Attribute Register Register 03h Bank A DISP_ATTR Display Attribute Register Read Write D7 D6 D5 D4 D2 D1 00 Background Its color setting can be used to generate a blue screen when the TV signal is not present Blue Master Background Green Master Background Red Master Background RGB Polarity 0 Positive 1 Negative Smoothing Effect Enable 0 2X character smoothing enabled 1 2X character smoothing disabled Fringe Effect Enable 0 Disabled 1 Enabled Master Background Enable 0 No master background 1 Incoming video is swapped with the background color Character Display 0 Disable 1 Enable Figure 4 28 Display Attribute Register Bit 7 Display Enable disables or enables the use of foreground and background color and therefore character display When this bit is set to 0 effective space characters are sourced from the video RAM Background On Off and row background color are programmed indepen dently When bit 7 is set to 1 the actual video RAM characters are displayed Bit 6 Master Background Enable disables or enables the use of a background color for the entire screen instead of the broadcast signal If this bit is set to 1 the incoming video signal is blanked and the screen background is displayed in color according to the setting of the back ground color bits The color is specified in bits 2 1 0 If bi
128. can access these registers Working register group 0 in ERF bank A consists of the registers for the On Screen Display OSD Table 3 2 shows the registers within this group Table 3 2 Expanded Register File Bank A Register Working Register Function Register F CLR_P6 R15 E CLR_P5 R14 D CLR_P4 R13 C CLR_P3 R12 B CLR_P2 R11 A CLR P1 R10 9 CLR_PO H9 3 8 Peripheral registers are used to transfer data configure the operating mode and control the operation of the on chip peripherals Any instruc tion that references the register file can access the peripheral registers The peripheral registers are m Timer Mode TMR m Timer Counter 0 TO m PREO m Timer Counter 1 T1 m Prescaler PRE 1 m Port 2 Mode 2 m Port 2 Output Control P2CNTL In addition the port register P2 is considered to be a peripheral register Table 3 2 Expanded Register File Bank A Register Working Register Function Register 8 SNDCLR R8 7 SNDCLR_CNTRL R7 6 FADE POS R6 5 FADE_POS R5 4 ROW_SPACE R4 3 DISP_ATTR R3 2 HOR_POS R2 1 VERT_POS R1 0 OSD_CNTL RO Working register group 0 in ERF bank B consists of the registers for the pulse width modulators Table 3 3 shows the registers within this group UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Table 3 3 Expanded Register File Bank B port control Figure 3 5
129. coding CCD and is currently under develop ment The Z90230 family supplies a standard UM97TELO0700 USER S MANUAL CHAPTER 1 INTRODUCTION m Halftone Effect m Window Based Background Mesh Effect m Dedicated Infrared Interface m On Chip Analog to Digital Conversion VRAM and Increased System ROM m Hardware Master Mode C Interface The memory efficient core in combination with these advanced features makes the Z90230 DTC family an ideal choice in the PAL SECAM and NTSC markets 2 communication port half tone OSD circuitry and programmable two pin I O assignment Figure 1 1 illustrates how the Z90230 DTC can be used as an application specific controller designed to provide complete audio and video control of television receivers and video recorders and advanced on screen display facil ities 1 1 Z90230 Family of DTCs Introduction FM Audio Color Decoder Composite Video Television Tuner Tuning Control Keypad I R Detector Deflection Unit R G B 290230 Digital T elevision Controller DTC Zilog RGB Output Stages VBLANK 2 Bus Figure 1 1 Z90230 DTC System Application The Z90200 family takes full advantage of the Z8 s expanded register file space to offer greater flexibility in creating a user friendly on screen display Three basic addressing spaces are available program memory Video RAM
130. ct is a transparent area that appears slightly darker than the regular picture that is carried by the TV signal Mesh and halftone effects both serve as back grounds for menus action bars and other On Screen Displays The mesh feature is only for interlaced mode video systems Mesh can be controlled in two ways through hardware or through software for alternating pixel display in different fields 4 8 UM97TELO700 Zilog Software must define a character based window in OSD to support mesh halftone effects The following control registers must be programmed properly to support the character based mesh halftone window Field 1 Z90230 Family of DTCs On Screen Display MC_St MC End MR En MC Reg Field 2 Figure 4 12 Mesh Example A close up example shows more precisely how the OSD overlays the TV signal when the mesh is active 97 0700 4 9 Z90230 Family of DTCs On Screen Display Zilog Picture Screen Mesh On Mesh Color Figure 4 13 Mesh On General descriptions of the registers used to below An example appears after the tables to control the mesh are contained in the tables further describe this feature 4 3 1 Mesh Column Start Register Register 04h Bank F MC St Mesh Column Start Register Read Write D7 D6 D5 D4 D3 D2 D1 Do Mesh Window Start Value Reserved Figure 4 14 Mesh Column Start Register 4 10 UM97TEL0700
131. ctor Table 8 41 Z90230 Family of DTCs Internal Microprocessor Overview maximum time required from interrupt genera tion to fetch of the first instruction of the interrupt service routine sum these components Zilog Worst Case Interrupt Latency 24 INT CLK interrupt acknowledge time TpC of longest instruction present in the user s application program 2 TpC internal synchronization time Fetch Fetch Stack Stack V V I MI Pushi Push 1 Posh Boh ow 1 MI M2 Internal Clock AS DS L T LT TT y LT LT l For Stack External Only Odd Vector Address 5 1 SP2 SP 3 n A0 A7 OUT PCH FLAGS VECT 1 Even Vector Address A0 A7 IN 1 OpCode Discarded VECTH First Instruction Of Interrupt Service Routine SM L For Stack External Only Figure 3 48 Interrupt Acknowledge Timing 3 24 2 Nesting of Vectored Interrupts Nesting of vectored interrupts allows higher priority requests to interrupt a lower priority request To initiate vectored interrupt nesting do the following during the interrupt service routine m Push old IMR on to the stack m Load IMR with a new mask to disable lower priority interrupts m Execute El instruction 3 25 POLLED PROCESSING Polled interrupt processing is supported by masking off the IRQ to be polled This is accom plished by clearing the corresponding bits in the IMR 3 42
132. ctory test pin In this 3 15 Z90230 Family of DTCs Internal Microprocessor Overview case applying 2V above Vcc on the XTAL1 pin causes the device to enter one of these modes Since this pin accepts high voltages to enter these respective modes the standard input protection diode to is not on XTAL1 It is recommended that in applications where the microcontroller is exposed to high system noise 3 9 LC OSCILLATOR The oscillator can use a LC network to generate a XTAL clock The frequency stays stable over Vcc and temperature The oscillation frequency is deter mined by the equation 1 Frequency q y 2n where L is the total inductance including para sitics and C is the total series capacitance including the parasitics Simple series capacitance is calculated using the following equation Zilog a diode from XTAL1 to Vcc be used to prevent accidental enabling of these modes This diode does not affect the crystal ceramic resonator operation Parallel resonant crystal or resonator data sheets specify a load capacitor value that is the series combination of C4 and including all parasitics PCB and holder sss C4 Co Co E NES Ce Figure 3 16 Capacitance Calculation Sample calculation of capacitance C4 and for 5 83 MHz frequency and inductance value of 27 uH 1 2n 2 7x 10 C C1 27 6 pF Thus 55 2 pF and 55 2 pF 5 83 x
133. ctually reaches 0 For UM97TELO700 Zilog example if the prescaler is set to divide by three the count sequence is 3 2 1 3 2 1 3 2 1 3 Each time the prescaler reaches its end of count a carry is generated which allows the counter timer to decrement by one on the next timer clock input When the counter timer and the prescaler both reach the end of count an interrupt request is generated IRQ4 for TO IRQ5 for T1 Depending on the counting mode selected the counter timer either rests with its value at 00 Single Pass Mode or the initial value is automatically reloaded and counting continues Continuous Mode The counting modes are controlled by PREO 0 and PRE1 0 A 0 written to this bit configures the counter for Single Pass counting mode while a 1 written to this bit configures the counter for Continuous Mode The counter timer can be stopped at any time by setting the Enable Count bit to 0 and restarted by setting it back to 1 The counter timer continues its count value at the time it was stopped The current value in the counter timer can be read at any time without affecting the counting operation Note The prescaler registers are Write Only and cannot be read New initial values can be written to the prescaler or the counter timer registers at any time These values are transferred to their respective down counters on the next load operation If the counter timer mode is Continuous the next load
134. disassembled providing a complete listing of program flow in native assembly language on the analyzer screen Supported Devices Z89301 Z89331 Z89346 289239 Z89313 Z89332 Z89300 Z89319 Z89341 Z90231 Z90239 Z90230 Family of DTCs Support Products C 1 6 Zilog Macro Cross Assembler ZMASMOWOZAS Zilog s Macro Cross Assembler ZMASM is a powerful and full featured relocatable assembler that enhances programmer productivity It is designed as a perfect match for use with the Ziog ICEBOX line of in circuit emulators and also with Zilog s evaluation boards but is still compatible with other vendor s products as well ZMASM processes assembly language source code written for a supported device target processor and translates it into the binary code that the processor can execute ZMASM can also provide source level debug information in the object file ZMASM has a graphical user based project front end interface that efficiently manages large numbers of source files so only the minimum number of required files are reassembled when source code changes are made ZMASM also has a command line interface mode available C 2 Zilog C 1 7 ZMASM Supported Cores Devices Processor Cores Z8 based Z89C00 based DSP Target Processor Devices Z86C47 E47 Z89313 Z90102 Z90231 Z89300 Z89319 Z90103 Z90233 Z89301 Z89331 Z90104 Z90341 Z89302 Z89332 Z90211 Z90346 UM97TEL0700 D 1 REGISTERS This section serves as a quick reference
135. e level of the SWI desired For example if an SWI is desired on IRQ5 NUMBER would have 1 in bit 5 OR IRQ 00100000B With this instruction if the interrupt system is globally enabled IRQ5 is enabled and there are no higher priority pending requests control is transferred to the service routine pointed to by the IRQ vector m Branch to the service routine specified by the vector Figure 3 46 and Figure 3 47 illustrate the vectored interrupt operation 3 39 Z90230 Family of DTCs Internal Microprocessor Overview Zilog SP and Stack Before an Interrupt SP and Stack After an Interrupt mE ws Figure 3 46 Effects of an Interrupt on the Stack 3 40 UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Program Memory Interrupt Service Routine PC Upper Byte Flags Interrupt Figure 3 47 Interrupt Vectors in Memory 3 24 1 Vectored Interrupt Cycle Timing The interrupt acknowledge cycle time is 24 internal clock cycles In addition two internal clock cycles are required for the synchronizing flip flops The maximum interrupt recognition time is equal to the number of clock cycles required for the longest executing instruction present in the user program assumes worst case condition of interrupt sampling Figure 3 48 just prior to the interrupt occurrence To calculate the worst case interrupt latency UM97TELO0700 Vector Selected By Priority Logic Ve
136. e total phase shift around the loop is forced to zero 360 degrees Since must be in phase with itself the amplifier inverter provides 180 degree phase shift and the feedback element is forced to provide the other 180 degrees of phase shift UM97TELO700 Zilog R1 is a resistive component placed from output to input of the amplifier The purpose of this feed back is to bias the amplifier in its linear region and to provide the start up transition Capacitor C2 combined with the amplifier output resistance provides a small phase shift It also provides some attenuation of overtones Capacitor C1 combined with the crystal resis tance provides additional phase shift 290230 Family of DTCs Internal Microprocessor Overview C1 and C2 can affect the start up time if they increase dramatically in size As C1 and C2 increase the start up time increases until the oscillator reaches a point where it does not start up any more It is recommended for fast and reliable oscillator start up over the manufacturing process range that the load capacitors be sized as low as possible without resulting in overtone operation Figure 3 11 Pierce Oscillator with Internal Feedback Circuit 3 8 1 Layout Traces connecting crystal caps and the oscil lator pins should be as short and wide as possible This reduces parasitic inductance and resistance The components caps crystal resistors should be placed as close as possible t
137. ecremented prior to a PUSH operation and incremented after a POP operation The stack address always points to the data stored on the top of the stack The stack Top of Stack Stack Contents After a CALL Instruction Z90230 Family of DTCs Internal Microprocessor Overview is a return stack for CALL instructions and inter rupts as well as a data stack During a CALL instruction the contents of the PC are saved on the stack The PC is restored during a RETURN instruction Interrupts cause the contents of the PC and Flag registers to be saved on the stack The IRET instruction restores them Figure 3 9 When the microcontroller is configured for an internal stack using the Standard Register File register FFh serves as the Stack Pointer The value in FEh is ignored FEh can be used as a general purpose register in this case only An overflow or underflow can occur when the stack address is incremented or decremented during normal stack operations If not prevented an unpredictable operation occurs Stack Contents After an Interrupt Cycle Figure 3 9 Stack Operations UM97TEL0700 Z90230 Family of DTCs Internal Microprocessor Overview 3 7 OSCILLATOR CONTROL In some cases the microcontroller offers soft ware control of the oscillator to select low EMI drive or standard drive The selection is done by programming bit D7 of the Port Configuration PCON register The PCON register is located in Expanded registe
138. ed Master Background RGB Polarity 0 Positive 1 Negative Smoothing Effect Enable 0 2X Character Smoothing Enabled 1 2X Character Smoothing Disabled Fringe Effect Enable 0 Disabled 1 Enabled Master Background Enable 0 No Master Background 1 Incoming Video is Swapped with the Background Color Character Display 0 Disable 1 Enable Figure D 6 Display Attribute Register Register 04h Bank A ROW_SPACE Row Space Register Read Write D7 D6 D5 D4 D2 1 00 Inter Row Space Halftone Output Delay On P20 Fade Direction 0 Fade Area Below the Defined Fade Position 1 Fade Area Above the Defined Fade Position Fade On Off 0 Fade Feature Disabled 1 Fade Feature Enabled Figure D 7 Row Space Register UM97TELO0700 D 5 Z90230 Family of DTCs Registers Zilog Register 05h Bank A FADE POS1 Fade Position Register 1 Read Write 575555543 22250 OSD Row Number Fading Reserved Figure D 8 Fade Position Register 1 Register 06h Bank FADE_ POS2 Fade Position Register 2 Read Write 272655 p4 ps p2 pipo Scan Line of Each Character for Fading Reserved Figure D 9 Fade Position Register 2 Register 07h Bank A SNDCLR_CNTRL Second Color Control Register Read Write 7 5 01 00 Row Address for Second Color Control Second Color R G B Second Color Enable
139. effectively reduced to 3 8 3 Circuit Board Design Rules The following circuit board design rules are suggested To prevent induced noise the crystal and load capacitors should be physically located as close to the microcontroller as possible Signal lines should not run parallel to the clock oscillator inputs In particular the crystal input circuitry and the internal system clock output should be separated as much as possible Vcc power lines should be separated from the clock oscillator input circuitry Resistivity between XTAL1 or XTAL2 and the other pins should be greater than 10 Mohms 3 14 Board Design Example Zilog unity and constant oscillation is achieved A signal of less than 2 5 volts peak to peak is an indication that low gain may be a problem Either C1 or C2 should be made smaller or a low resistance crystal should be used XTAL1 Clock 290230 Generator Circuit XTAL2 GND Signals A B l Parallel Traces ust Be Avoided Signal li XTAL1 290230 XTAL2 to System Group Must Be Avoided Signal Line Layout Should Avoid Shaded Areas Z90230 Top View Figure 3 12 Circuit Board Design Rules UM97TEL0700 Zilog 3 8 4 Crystals and Resonators Crystals and ceramic resonators should have the following characteristics to ensure proper oscillator operation Crystal cut AT crystal only Mode Parallel Fundamental Mode Crystal lt 7
140. efines field number When the value equals 1 software defines the field number Bit 0 Mesh Enable disables or enables use of the mesh This field is used in conjunction with MR_EN 0 The value of Mesh Enable should be changed only when Mesh Window Row equals 0 the current OSD row is not part of a mesh window the value is changed when the current row is part of the mesh window partial or missing characters are likely to be displayed 4 3 5 Mesh Window Display Example A software controlled mesh window is to be displayed in columns 2 through 20 of rows 3 through 7 of the OSD 97 0700 At the start of the display of the OSD row 0 the values in the registers are as follows 4 13 Z90230 Family of DTCs On Screen Display MC_ St 04h Bank F Mesh Starts Column 2 Reserved MC End 05h Bank F Column Following the Mesh Window is 21 Reserved L MR En 06h Bank F Zilog MC Reg 07h Bank F 1 L Mesh Enabled Mesh is Software Controlled the Even Normal Mesh Blue Mesh Color Blue Green Red Halftone Effect Output Delay on P20 No Mesh OSD for Next Row Reserved Reserved Foreground Character for Halftone Effect VBLANK Delay Figure 4 18 Mesh Window Display Registers for Row 0 Example Note 1 The value shown for VBLANK Delay is not signifi cant For this examp
141. egister 22 2 4 442224 10 22 D 20 Figure D 41 Port 6 Data Register o eot ceret diete erro D 21 Figure 0 42 Mesh Column Start Register 2 eene e nnne neenA D 21 Figure 0 43 Mesh Column End Register r sssssssssssssssssssssssssss D 21 Figure 0 44 Mesh Row Enable Register D 22 Figure D 45 Mesh Control Register uico eir nde tete xi Rc DO HORT D 23 Figure 0 46 Stop Mode Recovery Register D 24 Figure 0 47 Watch Dog Timer Mode Register 0 D 24 Figure D 48 Stack Pointer Low Register D 25 Figure 0 49 Stack Pointer High Register 1 2 11 1 2 1 1 14 4 1 44424 D 25 Fig re D 50 egislenPolntel oce onm t dusk Cond con ase ese ese cent cost be e mie e lementre trois D 25 Fig re D 51 Flag ce eoa bete o egest ie f o e ettet n e eet D 25 Figure D 52 Interrupt Mask Register vic sand it etd D 26 Figure 0 53 Interrupt Request Register D 26 Figure D 54 Interrupt Priority Register 222222222 2 1 00 D 27 Figure D 55 Control Register ua cuu tte bis
142. egister The Horizontal Position Register sets the hori zontal start position of the OSD The unit of measure for placement is the number of pixels from the left of the display screen Bits 7 and 6 are reserved for future use If this register is read these bits return 1s Bits 5 4 3 2 1 and 0 Horizontal Position specify the horizontal position of the OSD window from the start of Hsywc 4 4 Register 02h Bank A HOR POS Horizontal Position Register Read Write D7 pe b5 p4 ps p2 p1 o Horizontal Position Control Reserved Figure 4 6 Horizontal Position Register UM97TELO700 Zilog The value required for this register may be computed using the following equation HOR_POS Hpos 1 4 HOR_POS represents the contents of bits 5 4 3 2 1 0 of the Horizontal Position Register HOR_POS The default value is 0 When the value is 0 the OSD is at the left most OSD posi tion on the screen Hpos is the number of pixels from the left of the screen to the OSD start position must be 290230 Family of DTCs On Screen Display a positive integer with a minimum value of 5 incrementing by 4 Some possible values include 9 13 17 21 25 29 For example Hpos 17 HOR_POS 17 1 4 HOR_POS 16 4 HOR_POS 4 The contents of the register HOR_POS 5 4 3 2 1 0 should be for this example set to Register 02h Bank A HOR_POS Horizontal Position Register Read Write LX
143. egister Bank F Register Reset Condition F OF WDTMR F OE Reserved F OD Reserved F OC Reserved F OB SMR F OA Reserved F7 F6 5 PREO 4 09 Reserved 08 Reserved 07 MC Reg F F 06 F F 05 MC End 904 MC St F 03 DTA UL UL UU 1 1 1 f 2402 DRT 1 1 1 1 1 111 F fofo pem Reserved Expanded Register Register Reset Condition 0 03 Reserved 0 02 P2 0 01 Reserved 0 00 Reserved Figure 3 5 Register and Expanded Register File Map 3 6 UM97TELO700 Zilog Currently 4 of the 16 possible ERF banks have been implemented ERF bank 0 also known as the Standard Register File has all 256 bytes defined Figure 3 5 Only working register group 0 register addresses 00h to 0Fh have been defined for bank C and bank F All other working register groups in ERF banks C and F as well as the remaining 13 ERF banks are unimplemented All are reserved for future use When an ERF Bank is selected register addresses 00h to 0Fh access those sixteen ERF bank registers in effect replacing the first sixteen locations of the standard register file For example if ERF bank C is selected the stan dard registers 00h through 0Fh are no longer accessible Registers 00h through 0Fh are now the 16 registers from ERF bank C working register
144. es Registers are accessed using 8 bit addresses in the range of 00h FFh The program memory or data memory is accessed using 16 bit addresses register pairs in the range of 0000h FFFFh 3 31 REGISTER ADDRESSING In 8 bit Register Addressing R mode the operand value is equivalent to the contents of the specified register or register pair Program Memory 8 Bit Register File Address One Operand Instruction Example OpCode 290230 Family of DTCs Internal Microprocessor Overview Working registers are accessed using 4 bit addresses in the range of 0 15 Oh Fh The address of the register being accessed is formed by the combination of the upper four bits in the register pointer R253 and the 4 bit working register address supplied by the instruction Registers can be used in pairs to designate 16 bit values or memory addresses A Register Pair must be specified as an even numbered address in the range of 0 2 14 for working registers or 4 6 238 for actual registers In the following definitions of addressing modes the use of register can also imply register pair working register or working register pair depending on the context Note See the product data sheet for exact program data and register memory types and address ranges available In the register addressing Figure 3 51 the destination and or source address specified corresponds to the actual register in the reg
145. eserved and must not be used 2 16 UM97TEL0700 Z90230 Family of DTCs Zilog Architectural Overview 2 3 6 Watch Dog Timer Mode Register The WDT always uses the internal RC oscillator Register 0Fh Bank F WDTMR Watch Dog Timer Mode Register Write Only 00 6ms 01 12 ms POR 10 24 ms 112 96 ms WDT During Halt Off 1 POR Reserved Must 0 Figure 2 10 Watch Dog Timer Mode Register 2 3 7 Timer Mode Register Register F1h TMR R241 Timer Mode Register Read Write 2728354536279 L_ Load To 0 No Function 1 Load TO TO Count 0 Disable TO Count 1 Enable TO Count Load T1 0 No Function 1 Load T1 T1 Count 0 Disable T1 Count 1 Enable T1 Count Reserved Must be 00 Reserved Must be 00 Figure 2 11 Timer Mode Register UM97TELO0700 2 17 Z90230 Family of DTCs Architectural Overview 2 3 8 Counter Timer 1 Register Zilog Register F2h T1 R242 Counter Timer 1 Register Write Read p7 pe ps pa ps pe p po Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure 2 12 CounterTimer1 Register 2 3 9 Prescaler 1 Register Register F3h PRE1 R243 Prescaler 1 Register Write Only Jonan Count Mode 0 T1 Single Pass 1 T1 Modulo N ____ Clock Source 0 T1 External Timing Input 1 T1 Internal Prescaler Modulo Range 1 63 decimal 01 3Fh Fig
146. espectively 2 26 UM97TELO700 Z90230 Family of DTCs Zilog Architectural Overview 2 4 1 DC Characteristics Table 2 6 DC Characteristics Power Supply Voltage Input Voltage High Input Voltage Low Input XTAL Oscillator Input High Input XTAL Oscillator Input Low Output Voltage High 0 V 2 00 Output Voltage Low V 22 00mA Schmitt Hysteresis Reset Input Current 20V Input Leakage OV Voc Tri State Leakage OV Supply Current All inputs at rail outputs floating Halt Mode Current All inputs at rail outputs floating Stop Mode Current All inputs at rail outputs floating UM97TELO700 2 27 Z90230 Family of DTCs Architectural Overview 2 4 2 AC Characteristics The numbers in Table 2 7 correspond to the numbered signal segments in Figure 2 26 Table 2 7 AC Characteristics Input Clock Period Clock Input Rise And Fall Time Input Clock Width TwHsynciNL Hsync Input Low Width TwHsyne yH Hsync Input High Width TpHsynciN Hsync Input Period TRHsyncisN Hsync Input Rise And Fall Time Interrupt Request Input Low TwIH Interrupt Request Input High TpPOR Power On Reset Delay TpLVIRES Low Voltage Detect To Internal Reset Condition TwRES Reset Minimum Width TpHgOl Hsync Start To OSDX2 Stop
147. essor Overview and Interrupt Request Register IRQ must be initialized in that order to start the interrupt Zilog process However IPR need not be initialized for polled processing 3 22 1 Interrupt Priority Register Initialization An Interrupt Priority Register IPR initialization is a Write Only register that sets priorities for the vectored interrupts in order to resolve simulta neous interrupt requests There are 48 sequence possibilities for interrupts The six interrupt levels IRQ0 IRQ5 are divided into three groups of two interrupt requests each One group contains IRQ3 and IRQ5 The second Register F9h IPR group contains IRQ0 and IRQ2 while the third group contains IRQ1 and IRQ4 Priorities can be set both within and between groups as shown in Table 3 10 and Table 3 11 Bits 1 2 and 5 define the priority of the individual members within the three groups Bits 0 3 and 4 are encoded to define six priority orders between the three groups Bits 6 and 7 are Interrupt Priority Register Write Only b7 pe ps p4 ps p2 p Jbo Interrupt Group Bits Priority 000 Reserved 001 C gt A gt B 010 gt gt 011 gt gt 100 B gt CsA 101 C gt BsA 110 B gt A gt C 111 Reserved Group C IRQ1 and IRQ4 Priority 0 IRQ1 gt IRQ4 1 IRQ4 gt IRQ1 POE B IRQO and IRQ2 Priority 0 IRQ2 gt IRQO 1 IRQ0 gt IRQ2 atone and IRQ5 Priority 0
148. f 0 has no effect a value of 1 resets the vertical interrupt flag Bit 0 Horizontal Interrupt has different mean ings depending on its status In Read State a value of 0 indicates that a horizontal interrupt has 4 8 2 Hsync and Vsync Requirements Hsync and Vsync must meet the all TV broad casting specifications Zilog not been issued a value of 1 indicates that a horizontal interrupt has been issued In Write State a value of 0 has no effect a value of 1 resets the horizontal interrupt flag When an interrupt is issued while another interrupt is being processed the last issued interrupt is pended The interrupt flag bit which is in service the interrupt issued first must be cleared or serviced before the pended interrupt can be processed see SNDCLR 6 The minimum width of Vsync must conform to the following design T I Id I Field 2 1 2 HCYCLE As it is shown has to be larger than 1 5 x HCYCLE The same timing specification must be applied in negative polarity Figure 4 41 Hsync and Vsync Specification 4 30 UM97TELO700 Z90230 Family of DTCs Zilog On Screen Display 4 9 DOT CLOCK OSCILLATOR Dot clock oscillator for Z90230 family is generated by the LC network as shown in Figure 4 42 GND Z90230 OSDX2 OSDX1 Figure 4 42 Dot Clock Oscillator The frequency stays stable over Vcc and temperature The oscillation frequency is deter mined by the equation
149. fset of 40h from the Multiple characters may be combined to form previous character large icon Figure 4 26 shows an example Each block marked by the darker grid lines is 14 x 18 pixels one character No Spacing Row 5 No spacing Row 6 LLLLLLLLLLL MEE 6HL Spacing Fringing Effect Figure 4 26 Icon Display 4 6 2 Character Size and Smoothing Effect Z90230 supports two sizes of characters 1X and Smoothing is the enhancing of a character to 2X as shown in Figure 4 26 The 2X size dupli improve its appearance This effect can be cates each pixel horizontally and vertically to applied only to 2X characters and is enabled reach the double size and disabled in DISP ATTR 03h Bank 4 Check the effect of smoothing on 2X characters before finalizing OSD programming UM97TELO0700 4 21 Z90230 Family of DTCs On Screen Display Zilog
150. g to support this recovery mode See the product data sheet for actual ICC2 values All Z8 microcontroller bases provide some form of dedicated Stop Mode Recovery SMR circuitry Two SMR methods are implemented a single fixed input pin or a flexible program mable set of inputs The selected Z8 base Zilog product specification should be reviewed to determine the SMR options available for use Note For devices that support SPI the Slave mode compare feature also serves as a SMR source In the simple case a Low level applied to input pin P27 triggers a SMR To use this mode pin P27 I O Port 2 bit 7 must be configured as an input before the Stop Mode is entered The Low level on P27 must meet a minimum pulse width TWSM See the product data sheet to trigger the device Reset Mode Some microcontrollers provide multiple SMR input sources The desired SMR source is selected via the SMR Register Note Use of specialized SMR modes P27 input or SMR register based or the WDT timeout only when in the Stop Mode provide a unique reset operation Some control registers are initialized differently for a SMR WDT triggered POR than a standard reset operation See the product specification register file map for exact details To determine the actual Stop Mode current ICC2 value for the optional SMR modes avail able see the selected Z8 device s product data sheet Note The Stop Mode current ICC2 is minimized when
151. gister Figure 4 5 Vertical Position Example Figure 4 6 Horizontal Position Register Figure 4 7 Horizontal Position Example Figure 4 8 Second Color Control Register Figure 4 9 Second Color Register Figure 4 10 Second Color Example Figure 4 11 Second Color Example Registers Figure 4 12 Mesh Example Figure Se MOST ON FI T Figure 4 14 Mesh Column Start Register Figure 4 15 Mesh Column End Register Figure 4 16 Mesh Row Enable Register Figure 4 17 Mesh Control Register 22 222 Figure 4 18 Mesh Window Display Registers for Row 0 Example Figure 4 19 Mesh Window Display Registers for Row 1 6 Example Figure 4 20 Mesh Window Display Registers for Row 7 Example Figure 4 21 Video Fade Example Figure 4 22 Fade Position Register 1
152. gister Bits HEX Name 7 6 5 4 3 2 1 0 Comments FO Serial I O U UU UU UUU F1 Timer Mode 0 0 0 0 0 0 0 0 Counter Timers Stopped F2 Counter Timer1 U U U U U U U U F3 T1 Prescaler U U U U U UO 0 Single Pass Count Mode External Clock Source F4 Counter TimerO U U U U U U U U F5 Prescaler U U U U U U U 0 Single Pass Count Mode F6 Port 2 Mode 1 1 1 1 1 1 1 1 AllInputs F7 P2CNTL 0000000 1 Port2Open Drain F8 Port 0 1 Mode 0 4 0 O 4 1 0 1 Internal Stack Normal Memory Timing F9 Interrupt U UU U U UUU Priority FA Interrupt 00000000 AIIInterrupts Cleared Request FB Interrupt Mask 0 U U U U U U U Interrupts Disabled FC Flags UUUUUUUU FD Register 00000000 Pointer FE Stack Pointer UUUUUUUU High FF Stack Pointer UUUUUUUU Low Program execution starts 5 to 10 clock cycles instruction fetch is from location 000 after Internal Reset has returned High The initial Figure 3 17 shows Reset timing UM97TELO0700 3 17 Z90230 Family of DTCs Internal Microprocessor Overview Clock Reset Internal Signals Zilog First Machine Cycle Hold Low For 4 SCLK Periods Minimum Lq First Instruction Fetch 1 Figure 3 17 Reset Timing After a reset the first routine executed should be one that initializes the control registers to the required system configuration The Reset pin is the input of a Schmitt triggered circuit Resetting the microcontroller initializes port and control registers to their defau
153. ics for actual values UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Z90230 IN4148 Figure 3 18 External Power On Reset Circuit Example Table 3 7 Expanded Register File Bank 0 Reset Values at Reset Register Register Bits HEX Name 7 6 5 4 3 2 1 0 Comments 00 N A 01 N A 02 Port 2 U UU UU Input mode 03 N A 04 General Purpose UUUUUUUU Undefined Registers 04 EF UM97TELO700 3 19 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Reset 4 Clock Clear 18 Clock Reset Reset Filter CLK Generator Internal Reset XTAL WDT SELECT POR 6ms 12ms 24ms 96 ms OSC CLK CLR WODT POR Counter Chain 2 6V Operating Vpp Detector 2 6V REF 2 From Stop Mode ___ gt Recovery Source l O I Stop Delay Select SMR Figure 3 19 Microprocessor Reset with Reset Pin WDT SMR and POR Example 3 20 UM97TELO700 Zilog 3 12 WATCH DOG TIMER The Watch Dog Timer WDT is a retriggerable one shot timer that resets the microcontroller if it reaches its terminal count When operating in the RUN or Halt Modes a WDT reset is functionally equivalent to a hardware POR reset The WDT is initially enabled by executing the WDT instruc tion and refreshed on subsequent executions of the WDT instruction The WDT cannot be disabled after it has been initially enabled The Register OFh Bank F WDTMR 29023
154. iew 3 5 PROGRAM MEMORY The first 12 bytes of Program Memory are reserved for the interrupt vectors These loca tions contain six 16 bit vectors that correspond to the six available interrupts Address 12 up to the maximum ROM address consists of on chip mask programmable ROM See the product data sheet for the exact program data register memory size and address range available The internal program memory is one time program FFFF VRAM FC00 7FFF 3FFF 2FFF 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 Zilog mable OTP or mask programmable dependent on the specific device Note A ROM protect feature prevents the dumping of ROM contents by inhibiting execution of the LDC LDCI LDE and LDEI instructions to program memory in all modes The ROM Protect option is mask programmable On Chip ROM lt 32 16 KB 12 Start of On Chip ROM Location of First Byte of Instruction Executed After Reset Interrupt Vector Lower Byte Interrupt Vector Upper Byte Figure 3 7 Program Memory Map 3 10 UM97TELO700 Zilog 3 6 STACKS The register pair FEh and FFh form the 16 bit Stack Pointer SP that is used for all stack oper ations The stack address is stored with the UB in FEh and LB in FFh Lower Byte Upper Byte Figure 3 8 Stack Pointer FFh Stack Pointer Low FEh Stack Pointer High The stack address is d
155. illator Output Ground 1 MADR14 MADRO MCU Address D2 D1 F3 F2 F1 G2 G3 G1 H1 H2 H3 J1 J2 J3 External Crystal E2 Oscillator 2 4 UM97TELO700 Zilog Z90230 Family of DTCs Architectural Overview Table 2 2 Z90239 Pin Assignments Continued External Crystal Oscillator System Reset Power Supply Last T Cycle L1 Port 2 Pin 1 M1 K3 L2 N1 K4 L3 M2 IRIN IR Serial Data Input N2 P22 P23 Port 2 Pin 2 3 L4 M3 N3 P24 SCLKO MAS Port 2 Pin 4 2 Clock MCU Address Strobe N3 P25 SDATAO Port 2 Pin 5 2 Data P26 SCLK1 P27 SDATA1 Port 2 Pin 6 7 2 Clock Data MCU Data Strobe CGROM Data 5 L6 M7 L7 7 N8 Pulse Width Modulator 11 Port 5 Pin 6 M8 Power Supply L8 N9 PWMO P55 PWM1 P50 Pulse Width Modulator Port 5 Pin 5 4 3 2 1 0 9 L9 N11 N12 L10 M11 SCLK System Clock N10 NC N13 K10 L11 M12 M13 K11 Port 4 Pin 0 L12 P60 ADC3 UM97TELO700 Port 6 Pin 0 ADC3 L13 2 5 Z90230 Family of DTCs Architectural Overview Table 2 2 Z90239 Pin Assignments Continued CGROM Address K12 K13 J12 J13 H11 H12 H13 G12 G13 F13 F12 F11 E12 D13 Zilog P61 ADC2 Port 6 Pin 1 2 J11 P41 ADC1 Port 4 Pin 1 ADC1 G11 P62 ADCO Port 6 Pin 2 ADC
156. ilog configuration of this bit is 1 If the fast wake up is selected the Stop Mode Recovery source is kept active for at least 5 TpC Stop Mode Recovery Level Select D6 1 in this bit position indicates that a High level on any one of the recovery sources wakes the microcontroller from Stop Mode A 0 indicates Low level recovery The default is 0 on POR Figure 3 50 Cold or Warm Start D7 This bit is set by the device upon entering Stop Mode A 0 in this bit cold indicates that the device reset by POR WDT Reset A 1 in this bit warm indicates that the device awakens by a SMR m Stop Mode Recovery Delay Select D5 This bit if High enables the Reset delay after Stop Mode Recovery The default source SMR D4 D3 D2 0 0 SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 0 1 1 O 1 1 1 0 1 1 1 P20 P20 27 23 P27 To POR ep Mode Recovery Edge e To Figure 3 50 Stop Mode Recovery Source Level Select Note If P62 is used as a SMR source the digital mode of operation must be selected prior to entering the Stop Mode 3 46 UM97TELO700 Zilog 3 30 ADDRESSING MODES Six addressing modes are available m Register R m Indirect Register IR m Indexed X m Direct D m Relative RA m Immediate IM With the exception of immediate data and condi tion codes all operands are expressed as register file program memory or data memory address
157. in ning with the row number set in FADE_POS1 3 2 1 0 and the scan line number set in FADE_POS2 4 3 2 1 0 For example fading 4 18 could begin in row 0 scanline 0 and move down the screen When the Fade Direction is set to 1 fading is toward the top of the screen Fading occurs beginning with the row number set in FADE POS 3 2 1 0 and the scan line number set in FADE POS2 4 3 2 1 0 For example fading could begin in row 9 scanline 17 and move up the screen Bits 5 and 4 Halftone Effect Delay on P20 works with REG 7 UM97TELO700 Zilog Bits 3 2 1 and 0 Inter Row Space specifies a number of Horizontal Scan Lines HL to add between displayed rows Inter Row Spacing can be from 0 to 15 HL A setting of 0 HL is called Continuous Row Display The spacing between any two rows can be controlled by programming it during the period of 4 6 CHARACTER GENERATION Character generation provides the content of the OSD The Z90230 family of products support a 4 6 1 Character Cell Resolution Z90230 Family of DTCs On Screen Display the previous horizontal interrupt service A hori zontal interrupt is generated at the start of each character row Software must program the spacing between the current row and the next row during the current horizontal interrupt The amount of time required to process a row should not exceed the display time of the row true 14 pixel horizontal by 18 pixel vertical cha
158. ister Send bit 7 of 2 DATA register as an acknowledgment bit ACK OXXXXXXX 1XXXXXXX Used in a Read frame One SCLK cycle is generated Null operation Must be used with a Reset bit Received one data byte Used in a Read frame in order to receive the first data byte after an address byte is transmitted Eight SCLK cycles are generated Send Stop bit One SCLK cycles are generated UM97TELO0700 5 7 Z90230 Family of DTCs Interface 5 8 Zilog START m Head 2 CMD 0 Busy Write 1 lt DATA Addr 7 1 0 2 000 Send Start bit followed by device addr ma Read 2 CMD 0 Busy 1 No Read 2 2 DAT 0 0 Yes ACK Write I C DATA 7 0 Data 2 x001xx0x Send data byte pes _ Read 2 MD 0 Busy 1 gad 2 DATE EG DAT O Yes Are there more bytes to send Write 111 0 Send Stop Bit Figure 5 6 Data Frame Write Flowchart UM97TELO700 Z90230 Family of DTCs Zilog Interface he Read I C_CMD 0 Busy 1 Write DATA Addr 7 1 1 x000xx0x Send Start bit followed by device address 2 Yes ACK Write IC CMD x110xx0x Receive data byte Read I C_CMD 0 Busy 1 Read 2 DATA 7 0 Read data byte More bytes to read 2 Write DATA 1xxxxxxx Write I C DATA 2 CMD x010xxOx FO
159. ister file Register File Points to ue Register Figure 3 51 8 Bit Register Addressing UM97TELO0700 3 47 Z90230 Family of DTCs Internal Microprocessor Overview In 4 bit Register Addressing Figure 3 52 the destination and or source addresses point to the working register within the current working register group Program Memory OpCode 4 Bit Working Registers Two Instruction Example Points to One Register Zilog This 4 bit address is combined with the upper 4 bits of the register pointer to form the actual 8 bit address of the affected register Register File Points to Origin of Working Register Group Figure 3 52 4 Bit Register Addressing 3 32 INDIRECT REGISTER ADDRESSING In the Indirect Register Addressing Mode the contents of the specified register are equivalent to the address of the operand Figure 3 53 and Figure 3 54 Depending upon the instruction selected the specified register contents points to a register 3 48 program memory or an external data memory location When accessing program memory or external data memory register pairs or working register pairs are used to hold the 16 bit addresses UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Program Memory Register File Address of Operand Used By Instruction 8 Bit Register File Address ons to one
160. it addresses The 10 bit addressing does not affect the existing 7 bit addressing A special combination 11110xx for the first 7 bits of the first byte following a START bit is reserved for 10 bit addressing only The special combination can not be used as an address of a device with 7 bit addressing The last two bits xx of this combination are the two most significant bits MSBs of the 10 bit address The eighth bit of the first byte is a data direction bit R W It has same meaning as in 7 UM97TELO700 Z90230 Family of DTCs Zilog Interface bit addressing a indicates a transmission 10 bit address Then Master sends or receives Write 1 indicates request for data Read data as in 7 bit addressing mode The second byte contains remaining 8 bits of the Table 5 1 Master 22 Bus Interface Commands Send a Start bit followed by the address byte specified in the data register then fetch the acknowledgment bit in DATA 0 Used to initialize communication Nine SCLK cycles are generated Send the byte of data specified in the data register then fetch an acknowledgment bit stored in bit 0 Used in a Write frame Nine SCLK cycles are generated Send bit 7 of 2 DATA register as an acknowledgment bit ACK OXXXXXXX 1XXXXXXX then receive a data byte Used in a Read frame when the next data byte is expected Nine SCLK cycles are generated Received data is read in the data reg
161. k source for T1 is internal or external These control bits are discussed in detail throughout this chapter The counter timer registers TO F4h and 1 F2h each consist of an 8 bit down counter a Write Only register that holds the initial count value and a Read Only register that holds the 3 23 Z90230 Family of DTCs Internal Microprocessor Overview current count value The initial value can range from 1 to 256 decimal 01h 02h 00h Dec 247 245 244 243 242 241 Figure 3 22 Counter Timers Register Map P2CNTL TO Prescaler Timer Counter 0 T1 Prescaler Time Counter 1 Timer Mode Register F3h PRE1 R243 Prescaler 1 Register Write Only bpeppsp pspzp El Count Mode 0 T1 Single Pass 1 T1 Modulo N Hex Identifiers F7 F5 F4 F3 F2 F1 Clock Source 0 T1 External Timing Input 12 T1 Internal Figure 3 23 Prescaler 1 Register 3 24 Prescaler Modulo Range 1 63 decimal 01 3Fh Zilog UM97TELO700 Zilog Z90230 Family of DTCs Internal Microprocessor Overview Register F5h PRE0 R245 Prescaler 0 Register Write Only 0 TO Single Pass 1 TO Modulo N Clock Source Must be 1 Prescaler Modulo Range 1 63 Decimal 01 3Fh Figure 3 24 Prescaler 0 Register Register F2h 1 R242 Counter Timer 1 Register F4h R244 egister
162. kground Bnf B Blue n Palette Number f Foreground Bnb B Blue n Palette Number b Background Register 09h Bank A CLR PO Color Palette 0 Read Write b spsppspzpTo L Color Programming ROf GOf BOf ROb GOb BOb Reserved Figure 4 32 Color Palette 0 4 26 UM97TELO700 Zilog Register 0Ah Bank CLR_P1 Color Palette 1 Read Write 2755453625 Color Programming R1f G1f B1f Rib Gib B1b Reserved Figure 4 33 Color Palette 1 Register OBh Bank A CLR_P2 Color Palette 2 Read Write 2755554232555 _________ RGB Color Programming R2f G2f B2f R2b G2b B2b Reserved Figure 4 34 Color Palette 2 Register Bank A Color Palette 3 Read Write bzpe spspspap po RGB Color Programming R3f G3f B3f R3b G3b B3b Reserved Figure 4 35 Color Palette 3 UM97TELO700 290230 Family of DTCs On Screen Display Register 0Dh Bank A CLR_P4 Color Palette 4 Read Write 75623543220 Color Programming R4f G4f B4f R4b G4b B4b Reserved Figure 4 36 Color Palette 4 Register OEh Bank A CLR P5 Color Palette 5 Read Write is I RGB Color Programming 5 G5f B5f R5b G5b B5b Reserved Figure 4 37 Color Palette 5 4 27 Z90230 Family of DTCs On Screen Display Register 0Fh Bank A CLR_P6 Color Palette 6 Read Write
163. le the value is unused bits 7 4 would equal some previously assigned value When the interrupt is issued to start the display of Row 2 register values are the same as for Row 0 with one exception MR En 0 would be 1 rather than 0 Mesh Window Row must indicate that the following row Row 3 is to be included in the mesh window When the Row 1 interrupt is issued the registers have the following values UM97TELO700 Z90230 Family of DTCs Zilog On Screen Display MC St 04h Bank F MC Reg 07h Bank F E EIER EI Mesh Starts Column 2 Mesh Enabled Display the Even MC End 05h Bank F Field xixixi Normal Mesh Blue Mesh Color Column Following the Blue Green Red Mesh Window is 21 Reserved Halftone Output Delay on P20 MR_En 06h Bank F Display Mesh OSD in Next Row Reserved Reserved Foreground Character for Halftone VBLANK Delay Figure 4 19 Mesh Window Display Registers for Row 1 6 Example When the interrupt is issued to start the display of Row 2 these registers have exactly the same values as shown in Figure 4 19 the values are unchanged from the start of Row 1 In fact the values remain the same until prior to the display of row 7 when the Mesh Window Row value reverts to 0 indicating that Row 8 is not included in the mesh window UM97TELO700 4 15 Z90230 Family of DTCs On Screen Display Zilog Mesh and halftone effects are
164. lowing an addition it is cleared to IRET changes the value of the Decimal Adjust Flag when the flag register saved in the stack is restored result of a previous addition or subtraction into the correct decimal BCD result As in the case of the Decimal Adjust Flag the user does not normally access this flag IRET changes the 3 57 Z90230 Family of DTCs Internal Microprocessor Overview value of the Half Carry Flag when the flag register saved in the stack is restored Zilog 3 39 CONDITION CODES The C Z S and V Flags control the operation of the Conditional Jump instructions Sixteen frequently useful functions ofthe flag settings are encoded in a 4 bit field called the Condition Code Table 3 23 Flag Definitions CC which forms bits 4 7 of the conditional instructions Condition codes and flag settings are summa rized in Table 3 23 Table 3 24 and Table 3 25 Table 3 24 Flag Settings Definitions Flag Description Symbol Definition Carry Flag 0 Cleared to 0 Z Zero Flag 1 Set to 1 S Sign Flag D Set or cleared according to V Overflow Flag operation D Decimal Adjust Flag Unaffected H Half Carry Flag X Undefined Table 3 25 Condition Codes Binary HEX Mnemonic Definition Flag Settings 0000 0 Always False 1000 8 blank Always True 0111 7 Carry C 1 1111 F NC No Carry C 0 0110 6 Z Zero Z 1 1110 E NZ Non Zero Z 0 1101 D PL Plus
165. lt states To form the internal reset line the output of the trigger is synchronized with the internal clock The clock must therefore be running for Reset to function It requires four internal system clocks after Reset is detected for the microcontroller to reset the internal circuitry An internal pull up combined with an external capacitor of 1ypf provides enough time to properly reset the microcontroller The internal POR timer circuit holds the microcontroller in Reset Mode for a duration Tpog before releasing the device out of reset The internally generated reset drives the reset pin low for the POR time Any devices driving the reset line must be open drained in order to avoid damage from possible conflict during reset conditions This Tpor time allows the on board clock oscillator to stabilize To avoid asynchronous and noisy reset prob lems the microcontroller is equipped with a reset 3 18 filter of four external clocks 4 TpC If the external reset signal is less than 4 TpC in dura tion no reset occurs On the fifth clock after the Reset is detected an internal Reset signal is latched and held for an internal register count of 18 external clock cycles or for the duration of the external Reset whichever is longer Program execution begins at location 000Ch 5 10 TpC cycles after Reset is released For the internal Power On Reset the reset output time is speci fied as Tpog Please refer to the AC characteris t
166. maximum duration is achieved by loading FFh 255 prescaler outputs counts The prescaler and counter timer are true divide by n counters operations Initial values are automatically loaded in Trigger and Retrigger Modes so soft ware loading is unnecessary 3 27 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Register F1h TMR Timer Mode Register Read Write L 16554 Ty Must be 00 Figure 3 29 Timer Mode Register Operation Register F3h PRE1 R243 Prescaler 1 Register Write Only o Clock Source Must be 1 Figure 3 30 Prescaler 1 Register Operation 3 17 1 Clock Input Mode External Clock Input Mode bit 5 Note See the product data sheet for the and bit 4 both set to 0 supports counting of minimum allowed Ty external clock input period external events where an event is considered to Tiy be a High to Low transition on TMR D5 D4 00 IRQ5 IRQ2 Figure 3 31 Hsync Clock Input Mode 3 18 COUNTER TIMER RESET CONDITIONS After a hardware reset the counter timers are and prescaler registers are undefined However disabled and the contents of the counter timer the counting modes are configured for single pass and the T clock source is set for external 3 28 UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Register F2h T1 R242 Counter Ti
167. mer 1 Register Write Read Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure 3 32 Counter Timer 1 Register After Reset Register F4h T0 R244 Counter Timer 0 Register Write Read iu u u uj u uj uu Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure 3 33 Counter Timer 0 Register After Reset Register F3h PRE1 R243 Prescaler 1 Register Write Only Pe Count Mode 0 1 Single Pass 1 T1 Modulo N ____ Clock Source 0 T1 External Timing Input Hsync 1 Internal Prescaler Modulo Range 1 63 decimal 01 3Fh Figure 3 34 Prescaler 1 Register After Reset UM97TELO700 3 29 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Register F5 PRE0 Weite Prescaler 0 Register Write Only L Count Mode 0 Single Pass 12 TO Modulo N Clock Source Must be Prescaler Modulo Range 1 63 Decimal 01 SFh Figure 3 35 Prescaler 0 Register After Reset Register F1h TMR R241 Timer Mode Register Read Write L Load To 0 No Function 1 Load TO Count 0 Disable TO Count 1 Enable TO Count Load T1 0 No Function 1 2 Load T1 T1 Count 0 Disable T1 Count 1 Enable T1 Count Reserved Must be 00 Reserved Must be 00 Figure 3 36 Timer Mode Register After Reset 3 30 UM97TELO700 Zilog
168. munity means good resistiveness that results from Decoupling m PCB Layout The following figure demonstrates an effective decoupling scheme 5V 2 e Ima 0O 01uF 1000pF Components 290230 GND Interfacing with L 100pF I O Ports Z90230 AGND Interface Signals Figure E 1 Application Circuit UM97TEL0700 E 1 Z90230 Family of DTCs EMI Noise Reduction Figure E 1 illustrates a sample PCB layout Only one power line is needed to minimize interfer ence from other circuits J1 is a virtual shunt on the ground line for PCB auto layout to group grounds With this design the device requires only one common ground which is connected to the chassis ground Port outputs can be very susceptible to high frequency noise and can radiate EMI to the long path and capacitive loading termination Wires close to the ports could induce E 2 Zilog interference The design should include surface mount capacitors Cp on the ports side of the board with a short path between the ground and the ports Power decoupling should be done with ferrite beads electrolyte capacitors and ceramic capacitors UM97TELO0700 lt ya Z90230 FAMILY DTCs USER S MANUAL INDEX A Character II Resolution 4 18 AC Characteristics 2 28 E Al pid 4 19 Add
169. nd Color Feature m Mesh and Halftone Effect m OSDFade Inter Row Spacing m Character Generation The OSD format is 10 rows containing 24 columns Row and column numbering begin with the number O A full row contains 24 characters which can be referred to as columns 0 through 23 The 10 rows of the OSD can be referred to as rows 0 through 9 4 1 Z90230 Family of DTCs On Screen Display Zilog Figure 4 1 OSD Format 4 2 OSD POSITION OSD Positioning is controlled by programming the following registers m OSD Control Register m Vertical Position Register m Horizontal Position Register 4 2 UM97TELO700 Zilog 4 2 1 OSD Control Register Register 00h Bank A OSD_CNTL OSD Control Register Read Write D7 De D5 D4 Ds D2 01 00 290230 Family of DTCs On Screen Display Vertical Retrace Blanking Character Size 0 1 1 2 Sync Polarity 0 Positive 1 Negative VRAM Mode 00 Select 10 row buffer mode 01 Select 4 row buffer mode 10 Select 2 row buffer mode 11 Reserved OSD Blank 0 Enable OSD POR default 1 Disable OSD Figure 4 2 OSD Control Register Bit 7 OSD Blank enables or disables the OSD When the value is set to 0 the OSD is available for use When the value is set to 1 the OSD is disabled Bits 6 and 5 VRAM Mode select 10 4 or 2 row buffer mode Bit 4 Sync Polarity provides the polarity of the and Vsync signals
170. nitial Value Initial Value Current Value Register Register Register 6 Bit 8 Bit 4 Down Down Counter Counter IRQ4 16 Internal Clock 6 Bit 8 Bit IRQ5 Down Down Counter Counter a PRE1 T1 Initial Value Initial Value Current Value Register Register Register wid Write V Internal Data Bus Figure 3 21 Counter Timers Block Diagram Counter Timers 0 and 1 are driven by a timer clock generated by dividing the internal clock by four The divide by four stage the 6 bit pres caler and the 8 bit counter timer form a synchro nous 16 bit divide chain The counter timer prescaler and associated mode registers are mapped into the register file as shown in Figure 3 22 This allows the soft ware to treat the counter timers as general purpose registers and eliminates the need for special instructions 3 15 PRESCALERS AND COUNTER TIMERS The prescalers PRE 0 F5h and PRE 1 each consist of an 8 bit register and a 6 bit down counter as shown in Figure 3 21 The prescaler registers are Write Only registers Reading the prescalers returns the value FFh Figure 3 23 and Figure 3 24 show the prescaler registers The Six most significant bits D7 D6 D5 D4 D3 D2 of PREO or PRE1 hold the prescalers count modulo a value from 1 to 64 97 0700 decimal The registers also contain control bits that specify and T1 counting modes These bits also indicate whether the cloc
171. o Effect 1 Reset Vertical Interrupt Flag Horizontal Interrupt Enable 0 No Horizontal Interrupt 1 Enable Horizontal Interrupt Palette Mode 0 Normal Mode 1 Color Palette Mode Fringe Color Defines Fringe Color RGB Fringe Color Selection 0 Select Character Background Color 1 Select Fringe Color RGB Figure 4 40 HV Interrupt Status Register Bit 7 Fringe Color Selection sets the fringe color to the background color or to a Red Green and Blue color that is specified in bits 6 5 4 Bits 6 5 and 4 Fringe Color sets the Red Green and Blue values of the fringe color Bit 3 Palette Mode sets color to Normal 8 bit or VRAM 11 bit Mode When the value is 0 Normal Mode the color attribute of a row is 97 0700 controlled by values in the ROW_ATTR register which is mapped in VRAM but the Color Palette Selection Bits are ignored When the Palette Mode value is 1 the Color Palette Selection Bits are used unless they are set to 0s In that case the values in ROW_ATTR register are used Bit 2 Horizontal Interrupt Enable disables or enables the horizontal Hsync interrupt 4 29 Z90230 Family of DTCs On Screen Display Bit 1 Vertical Interrupt has different meanings depending on its Read and Write status In Read State a value of 0 indicates that a vertical inter rupt has not been issued a value of 1 indicates that a vertical interrupt has been issued In Write State a value o
172. o the oscillator pins The traces from the oscillator pins of the IC and the ground side of the lead caps should be guarded from all other traces clock Voc address data lines system ground to reduce 3 8 2 Indications of an Unreliable Design There are two major indicators that are used in working designs to determine their reliability over full lot and temperature variations They are UM97TELO0700 cross talk and noise injection This is usually accomplished by keeping other traces and system ground trace planes away from the oscil lator circuit and by placing a device Vss ground ring around the traces components The ground side of the oscillator lead caps should be connected to a single trace to the GND pin It should not be shared with any other system ground trace or components except at the GND pin This is to prevent differential system ground noise injection into the oscillator Figure 3 1 1 m Start Up Time If start up time is excessive or varies widely from unit to unit there is probably a gain problem C1 C2 should be reduced the amplifier gain is not adequate at frequency or crystal Rs is too large 3 13 Z90230 Family of DTCs Internal Microprocessor Overview Output Level The signal at the amplifier output should swing from ground to Vcc This indicates there is adequate gain in the amplifier As the oscillator starts up the signal amplitude grows until clipping occurs at which point the loop gain is
173. on reset is D0 1 and D1 0 The values given are for Vcc 5 0V See the device product specification for exact WDTMR timeout select options available WDT During Halt Mode T2 Bit 2 determines if the WDT is active during Halt Mode A 1 value indicates active during Halt The default is 1 WDT timeout during Halt Mode resets control register ports to their default reset conditions 3 21 Z90230 Family of DTCs Internal Microprocessor Overview Bits 3 4 5 6 and 7 These bits are reserved Vcc Voltage Comparator An on board voltage comparator checks that Vcc is at the required 3 13 POWER ON RESET A timer circuit clocked by a dedicated on board RC oscillator is used for the Power On Reset POR timer function The POR time allows Vcc and the oscillator circuit to stabilize before instruction execution begins The POR timer circuit is a one shot timer trig gered by one of three conditions 1 Power fail to Power OK status cold start 2 Stop Mode Recovery if bit 5 of SMR 1 3 WDT timeout 3 14 COUNTER TIMERS The microcontroller provides up to two 8 bit counter timers TO and T1 each driven by its own 6 bit prescaler PRE 0 and PRE 1 Both counter timers are independent of the processor instruction sequence that relieves software from time critical operations such as interval timing or event counting Some MCUS offer clock scaling using the SMR register The following descrip tion is typical
174. on the CRT at the same time VBLANK output turns off the Y signal Vcc Power Supply Vpp Power Supply Vsync Vertical Sync Pin input for external vertical synchronization signal XTAL1 XTAL2 Time Based Input Output respectively These pins connect to the internal parallel resonant clock crystal oscillator circuit with two capacitors to GND XTAL1 can be used as an external clock input Low EMI noise oper ation deletes a divide by 2 in the instruction clock timing chain 2 2 4 2 Multiplexed Pin Descriptions DTIMER Disable Watch Dog Timer or Timers 0 and 1 P20 HLFTN Port 2 Pin 0 or Halftone Output Port 2 is 8 bit CMOS compatible and each bit is programmable for either input or output Input buffers are Schmitt triggered Bits programmable as outputs may be globally programmed as either push pull or open drain Port operation is accomplished by Port 2 Mode Register at F6h Port 2 is at 02h which is part of the Register File P24 SCLKO Port 2 Pin 4 or FC Clock P25 SDATAO Port 2 Pin 5 or FC Data P26 SCLK1 P27 SDATA1 Port 2 Pin 6 or FC Clock and Port 2 Pin 7 or Data 2 8 Zilog P62 ADCO Port 6 Pin 2 or Analog to Digital Converter Channel 0 P62 may be read directly A negative edge event is latched into IRQ 2 to initiate an IRQ 2 vectored interrupt if appropri ately enabled P60 ADC3 Port 6 Pin or Analog to Digital Converter Channel 3 Port 6 pin 0 is a program mable input or output line P61 ADC2
175. or in order to perform the wired AND func tion Low state of the data line can only change when the clock signal on the SCLK line is Low SDATA line while SCLK line is High defines a Stop condition Start and Stop conditions are always generated by the Master The bus is considered to be busy after the Start condition The bus is free again after the Stop condition followed by an eighth bit which is a data direction bit R W a 0 indicates a transmission Write a 1 indicates a request for data Read 5 1 Z90230 Family of DTCs Interface A data transfer is always terminated by a Stop condition generated by the Master However if a Master still wishes to communicate on the bus it can generate a repeated Sthart condition to another Slave address without generating a Stop condition This type of data transfer is called combined format Some examples of combined format include mg Master transmits data to a Slave and then reads data from the same Slave Zilog m A Master transmits data to one Slave and then transmits data to another Slave m 10 bit and 7 bit addressing can be combined in one serial transfer For some types of serial memory a combined format is the only way to read data from a precise location Condition SDATA line is High ACK SDATA line is pulled Low by receiver Condition Figure 5 1 Data Transfer 5 5 BYTE FORMAT The number of b
176. outputs registers and return 1s in each address bit location when read Writing bits that are defined as timer output serial output or handshake output have no effect The instruction DJNZ uses any general purpose working register as a counter Logical instructions such as OR and AND require that the current contents of the operand be read Therefore they do not function properly on Write Only registers UM97TELO700 Zilog m The WDTMR register must be written within the first 60 internal system clocks cycles of operation after a Reset 3 3 EXPANDED REGISTER FILE The standard register file has been expanded to form 16 Expanded Register File ERF Banks Figure 3 5 Each ERF bank consists of up to UM97TEL0700 Z90230 Family of DTCs Internal Microprocessor Overview 256 registers the same amount as in the stan dard register file that can then be divided into 16 working register groups This expansion allows for access to additional feature peripheral control and data registers 3 5 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Reset Condition Register 07 pe ps p4 s p2 D po FF SPL FE SPH s FD RP Register Pointer C LAGS b Working Register Expanded Register FA Group Pointer Bank Pointer F9 IPR 8 P01M P2CNTL 6 _ 1 TO Register File PRE1 F2 T 1 FO Reserved Expanded R
177. r PRT4 DTA Port4 Direction Register PRT4 DRT 06h HVInterrupt Status Register INT ST 07h Port 4 Pin Out Selection PIN SLT 08h Color Index Register CLR IDX 09h Master 12C Data Register 2 DATA Port Configuration Register PCON ooh Command Register 2 SBIEADG Data Register GADC_DTA Master 12C Control Register I2C_CNTL 02h Port 6 Data Register PRT6_DTA O3h Mesh Column End MC End Mesh Row Enable MR En Mesh Control Register MC Reg 07h N A 08h N A 09h N A OCh N A _ 90 N A OEh WDT Mode Register WDTMR OFh Figure 2 8 Expanded Register File UM97TELO700 Z90230 Family of DTCs Architectural Overview Zilog 2 3 5 Stop Mode Recovery Register Register 0Bh Bank F SMR Stop Mode Recovery Register Write Only Except Bit D7 Which Is Read Only 2758532423225 SCLK TCLK Divide by 16 0 Off POR 1 On External Clock Divide by 2 0 SCLK TCLK XTAL 2 POR 1 SCLK TCLK XTAL Stop Mode Recovery Source 000 POR and or External Reset 001 P63 010 P62 011 Must not be used 100 Must not be used 101 P27 110 P2 NOR 0 3 111 2 P2 NOR 0 7 Stop Dela 0 Off y 1 Stop Recovery Level 0 Low POR 1 High Stop Flag Read Only 0 POR 1 Stop Recovery Figure 2 9 51 Recovery Register Note The Stop Mode Recovery Source values 011 and 100 r
178. r file bank F register 00h Register 00h Bank F PCON Port Configuration Register Read Write D7 be p5 p4 ps p2 p1 po Zilog A 1 in bit D7 configures the oscillator with stan dard drive while a 0 configures the oscillator with Low EMI drive This only affects the drive capa bility of the oscillator and does not affect the rela tionship of the XTAL clock frequency to the internal system clock SCLK x Reserved LOW EMI OSD Oscillator 0 Low EMI noise 1 Standard POR Low EMI Port 4 and PWMs 0 Low EMI noise 1 Standard POR Reserved Low EMI Port 2 0 Low EMI noise 1 Standard POR Low EMI Port 3 0 Low EMI noise 1 Standard POR Low EMI Z8 Oscillator 0 Low EMI noise 1 Standard POR Figure 3 10 Port Configuration Register 3 8 OSCILLATOR OPERATION The microcontroller uses a Pierce oscillator with an internal feedback The advantages of this circuit are low cost large output signal low power level in the crystal stability with respect to Vcc and temperature and low impedances not disturbed by stray effects One draw back is the need for high gain in the amplifier to compensate for feedback path losses The oscillator amplifies its own noise at start up until it settles at the frequency that satis 3 12 fies the gain phase requirements A x B 1 where is the gain of the amplifier and B Vi VO is the gain of the feedback element Th
179. racter display with 256 character sets To achieve improved performance characters are mapped pixel by pixel in Character Generation Read Only Memory CGROM 97 0700 4 19 Z90230 Family of DTCs On Screen Display Zilog Left Half Right Half Even Odd Figure 4 25 Character Pixel Map in CGROM Example The character pixel map in Figure 4 25 repre sents one character It is 14 pixels horizontal and 18 pixels vertical Each row in the map is 7 bits long half the width of the character scan line Even numbered rows of the map correspond to pixels on the left half of the character scan line odd rows of the map correspond to pixels on the right half of the character scan line The Hex Add column is a hexadecimal number that serves as an address for the group of pixels 4 20 from the starting point of the scan line Addressing begins at 0000h and ends at 0023h Each bit in the map sets the foreground back ground designation of the corresponding pixel 0 background 1 foreground pixel The patterns formed by the bits comprise the charac ters that are displayed when the scan line is output to the screen Each of these character pixel maps is one char acter 256 characters may be mapped Each UM97TELO700 Z90230 Family of DTCs Zilog On Screen Display character starts with an of
180. ration RCF Reset Carry Flag SCF Set Carry Flag SRP src Set Register Pointer STOP Stop WDH WDT Enable During Halt WDT WDT Enable or Refresh 3 38 PROCESSOR FLAGS The Flag Register FCh informs the user of the current status of the microcontroller The flags and their bit positions in the Flag Register are shown in Figure 3 59 The Flag Register contains six bits of status information which are set or cleared by CPU operations Four of the bits C V Z and S can be tested for use with conditional Jump instruc tions Two flags H and D cannot be tested and are used for BCD arithmetic The two remaining Register FCh Flags Flag Register Read Write bits in the flag register F1 and F2 are available to the user but they must be set or cleared by instructions and are not usable with conditional Jumps As with bits in the other control registers the flag register bits can be set or reset by instructions however only those instructions that do not affect the flags as an outcome of the execution should be used Load Immediate prps ps 5255 eo User Flag 1 L User Flag F2 Half Carry Flag H Decimal Adjust Flag D Overflow Flag V Sign Flag S Zero Flag Z Figure 3 59 Note The Watch Dog Timer WDT instruction 3 56 Carry Flag C Flag Register effects the Flags accordingly Z 1 S 0 V 0 UM97TEL0700 Zilog 3 38 1 Carry Flag The
181. ress Space nipote Ae 3 1 Character Size and Smoothing 4 20 Addressing Modes Clock 16 Bit Register 3 2 External u sq NEC NORCO Re 3 15 4 Bit Indirect 3 48 HSYNC Input 3 97 8 Bit Indirect Register 227 3 15 8 Bit 2 ponis 3 45 Stop Mode Recovery 3 43 Direct ata D maunmuannnanannasannanannnannannannaanananan XTAL from LG Oscillator 3 1 6 immediale x Color Palette Selection Bits 4 24 RANA UR SC 244 Gohdl lonCodes 3 56 ndirect 3 46 Core Customization 2 9 Introduction 3 45 Counter Timers Relative E eee eee eee eee ee eee eee eee ee eee ee eee 3 51 Block Diagram 3 22 Working Registers 0779 Continuous Mode 3 26 Analog to Digital Converter Description 3 21 Block Diagram B 3 Operation CHR TU CT 4 24 20182 Register Map e 3 23 Reference 1 Single Pass 4 26 Assembly Language Syntax 3 58 Crystals and Resonators 3 15
182. s Pulse Width Modulators 8 4 A PWM2 00H B PWM2 01H C PWM2 03H D PWM2 20H E PWM2 3FH F6 XTAL 16 64 XTAL 2 Zilog LL jJ Hd e 4 Sa l j f J d P Figure 8 3 Pulse Width Modulator Timing Diagram 6 Bit UM97TELO700 Z90230 Family of DTCs Zilog Pulse Width Modulators XTAL 128 lt lt M Time Slot 40H A PWM11 0001H p Time Slot 60H Time Slot 20H B PWM11 0002H Lu Time Slot 60H Time Slot 40H Time Slot 20H C PWM11 0003H Slot 70 Time Slot 50 Time Slot 30H Time Slot 10H D PWM11 0004H 70H 50H 40H 30H 10H E PWM11 0005H F PWM11 007FH pe ui Time Slot 0 No Pulse G One of Distribution Pulse XTAL 128 XTAL PWM11 0080H 1 PWM11 0180H J PWM11 2000H K PWM11 3F80H Distribution Pulses Added These Places L PWM11 0081H lt Time Slot 44H lt Time Slot 40H lt Time Slot 8 Time Slot Figure 8 4 Pulse Width Modulator Timing Diagram 14 Bit UM97TELO700 8 5 Z90230 Family of DTCs Pulse Width Modulators 8 6 Register 02h Bank B PWM1 PWM1 Data Register Read Write brppspsp spe p oo w Register 03h Bank B PWM2 PWM2 Data Register Read Write bpspspapspzpps 2 Value Register
183. s 4 26 Figure d olor Palette S d coto teet cte ee du tM 4 26 Figure 4 39 Row Attribute Register 2 2 2 1 1 2 2 1 1 460 nni 4 27 Figure 4 38 Color Palette 6 t 4 27 Figure 4 40 HV Interrupt Status Register a 4 28 Figure 4 41 Hsync and Vsync Specification rper 4 29 Figure 4 42 Dot Clock Oscillator miese ee e Li e 4 30 Figure 4 43 Oscillation Frequency 4 30 Figure 4 44 Simple Series Capacitance 4 30 Chapter 5 Interface Figure sls Data Transfer e o rigat te edidi b 5 2 Figure 5 2 Bidirectional Port Pin Pad Multiplexed with 12 Port 5 4 Figure 5 3 Master 12 Control Register 5 5 Figure 5 4 Master IC Command 5 6 Figure 5 5 Master 12 Data Register 5 6 Figure 5 6 Data Frame Write Flowchart tene et tape EC coder Ce aera aed 5 8 Figure 5 7 Data Frame Read Flowchart een 5 9 Chapter 6 Input Output Ports Figure 6
184. s PWM7 1 Selects P44 POR P45 PWM8 0 Selects PWM8 1 Selects P45 POR P46 PWM9 0 Selects PWM9 1 Selects P46 POR P47 PWM10 0 Selects PWM10 1 Selects P47 POR Reserved Figure D 33 Port 4 Pin Out Selection Register UM97TELO700 Z90230 Family of DTCs Zilog Registers Register 09h Bank C CLR_IDX Color Index Register Read Write 07 D6 05 64 D3 02 2120 ere Index Defines the Color Palette Selection Bits Reserved Figure D 34 Color Index Register Register 0Ah Bank C 2 DATA Master 2 Data Register Read Write D7 D6 D5 D4 D3 D2 D1 Do Data Read Received Data Write Data to be Sent Figure D 35 Master Data Register Register 0 Bank C 2 CMD Master 2 Command Register Read Write D7 D6 25 D4 D3 D2 D1 Do Read 0 Idle 1 Write No effect Reset Read Return 1 Write 0 No effect 1 Reset I C interface Reserved 2 Command See Table 5 1 Reserved Figure D 36 Master Command Register UM97TELO700 D 17 Z90230 Family of DTCs Zilog 2 Speed For 6 MHz XTAL 00 10 KHz 01 50 KHz 10 100 KHz 11 330 KHz 2 Enable 0 Disable 2 Interface 1 Enable I C Interface Reserved Must be 0 2 Selection 0 0 24 Selection POR P25 Selection POR 1 SCLKO Selection on P24
185. se 3 27 Figure 3 32 Counter Timer 1 Register After Reset 3 28 Figure 3 33 Counter Timer 0 Register After Reset 3 28 Figure 3 34 Prescaler 1 Register After Reset 3 28 Figure 3 35 Prescaler 0 Register After Reset 122222112111 sssss8 3 29 Figure 3 36 Timer Mode Register After Reset 3 29 Figure 3 37 Interrupt Control Registers DH ttis aceite fees 3 30 Figure 3 38 Interrupt Block Diagram a r eese einsehen iini 3 30 Figure 3 39 Interrupt Sources IRQO IRQ2 Block Diagram 3 31 Figure 3 40 IRQ Register Logic co oc cto leto aou ced eroe 3 32 Figure 3 41 Interrupt Request Timing J 1 ple 3 32 Figure 3 42 Interrupt Priority Register 3 33 Figure 3 43 Interrupt Mask Register 1 2 1 1 1 3 35 Figure 3 44 Interrupt Request Register e 3 36 Figure 3 45 IRQ Reset Functional Logic Diagram 3 37 Figure 3 46 Effects of an Interrupt on the Stack 3 38 x
186. sets the proce dure for processing when a second interrupt is 4 2 7 Second Color Example Figure 4 10 illustrates a second color display in row 8 of the OSD Each of the small grid squares represents one pixel Each column is comprised of two parts 4 6 issued before the processing of the first interrupt has completed For example interrupt comes in before completion of the Vsync inter rupt processing If bit 6 is reset to 0 and interrupt request is disabled during vertical interrupt the horizontal interrupt will be missed If bit 6 is set to 1 and the interrupt request is reset to 0 during vertical interrupt service then the horizontal interrupt will be pended and serviced after completion of the vertical interrupt processing Bits 5 4 3 2 1 and 0 Second Color Position control second color display This field specifies the place at which to start the second color A specific color can be assigned as the second color UM97TELO700 Z90230 Family of DTCs Zilog On Screen
187. shows the registers within this group Register Working Register Function Register 5 DRT R14 Table 3 5 Expanded Register File Bank F D P_MODE R13 Register Working PRT5 DTA R12 Register Function Register B PWM10 R11 E T idis A PWM9 R10 E Reserved R14 9 PWM8 R9 D Reserved R13 8 PWM7 R8 C Reserved R12 7 R7 EE R11 6 PWM5 R6 A Reserved R10 5 R5 9 Reserved H9 4 PWM3 R4 8 Reserved R8 7 Mesh Control R7 gt is Register Reg 1 PWMTL R1 6 Enable R6 PWM RO 5 Mesh Column End R5 Register bank C in the ERF consists of the regis MG ters for the I C interface Table 3 4 shows the 4 Mesh Column Start R4 registers within ERF bank C working register MC_St 2 PRT6_DRT R2 Table 3 4 Expanded Register File Bank C 1 R1 Register Working 0 PCON R0 Register Function Register 2 CNTL R12 The functions and applications of the control and B 2 CMD R11 peripheral registers are described in other sections of this manual A 2 DATA R10 9 CLR IDX H9 8 PIN SLT R8 7 INT_ST R7 6 PRT4 DRT R6 5 PRT4_DTA R5 4 IR CP1 R4 3 IR_CPO R3 2 TCR1 R2 1 TCRO R1 0 3ADC DTA RO Working register group 0 in ERF bank F consists of the control registers for Stop mode WDT and UM97TELO0700 3 9 Z90230 Family of DTCs Internal Microprocessor Overv
188. t POR P42 I O Definition 0 Defines P42 as Output 1 Defines P42 as Input POR P43 I O Definition 0 Defines P43 as Output 1 Defines P43 as Input POR P44 I O Definition 0 Defines P44 as Output 1 Defines P44 as Input POR P45 I O Definition 0 Defines P45 as Output 1 Defines P45 as Input POR P46 I O Definition 0 Defines P46 as Output 1 Defines P46 as Input POR P47 I O Definition 0 Defines P47 as Output 1 Defines P47 as Input POR Figure D 31 Port 4 Direction Control Register Registers Z90230 Family of DTCs Registers Register 07h Bank C INT_ST HV Interrupt Status Register Read Write 07 De 05 p4 p3 p2 p1 po T Zilog Horizontal Interrupt Read 0 No Horizontal Interrupt 1 Horizontal Interrupt Write 0 No Effect 1 Reset Horizontal Interrupt Flag Vertical Interrupt Read 0 No Vertical Interrupt 1 Vertical Interrupt Write 0 No Effect 1 Reset Vertical Interrupt Flag Horizontal DP Enable 0 No Horizontal Interrupt 1 Enable Horizontal Interrupt Palette Mode 0 Normal Mode 1 Color Palette Mode Fringe Color Defines Fringe Color RGB Fringe Color Selection 0 Select Character Background Color 1 Select Fringe Color RGB Figure D 32 HV Interrupt Status Register Register 08h Bank C PIN SLT Port 4 Pin Out Selection Register Read Write D7 be p5 p4 ps p2 p1 po Reserved Reserved P44 PWM7 0 Select
189. t 2 Data Register Register 02h P2 Port 2 Data Register Read Write D7 pe p5 p4 ps p2 p1 po P20 P21 P22 P23 P24 25 26 27 Read Write Figure 2 25 Port 2 Data Register UM97TELO700 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Data Input on P20 Data Output on P20 Data Input on P21 Data Output on P21 Data Input on P22 Data Output on P22 Data Input on P23 Data Output on P23 Data Input on P24 Data Output on P24 Data Input on P25 Data Output on P25 Data Input on P26 Data Output on P26 Data Input on P27 Data Output on P27 2 25 Z90230 Family of DTCs Architectural Overview 2 4 OPERATING CHARACTERISTICS Zilog Stress outside the levels listed under Opera only not optimal operating levels Exposure to tional Limits may cause permanent damage to maximum rating conditions for extended periods the device These limits represent stress limits may affect device reliability Table 2 5 Operational Limits Power Supply Voltage Input Voltage Output Voltage Output Current High One pin Output Current High Total all pins Output Current Low One pin Output Current Low Total all pins Operating Temperature Storage Temperature A typical value is 25 C Minimum and maximum values are 0 C and 70 C r
190. t 6 is set to 0 the incoming video signal is displayed Bit 5 Fringe Enable sets the fringe effect On or Off Bit 4 Smoothing Effect Enable sets smoothing On or Off and is available only for 2X size char acters Bit 3 RGB Polarity sets color polarity of OSD color output signals to positive or negative 97 0700 4 23 Z90230 Family of DTCs On Screen Display Zilog Bits 2 1 and 0 form the color for the master background The eight possible colors are the same as are listed in Table 4 2 4 7 2 Video Refresh RAM Access The Z90230 family of products supports 11 bit Figure 4 29 contains the address map of VRAM character data Eight bits DO through 07 for displaying 10 rows and 24 columns contain character data Three additional bits D8 through D10 contain color palette information Character Byte D0 through D7 Color Palette Selection Bits Row 0 Attribute FCOO D8 09 010 for Row 0 Column FCO1 D8 D9 D10 for Row 0 Column 2 FC02 Through Row 0 Column 22 FE17 Row 0 Col 2 Through Col 22 09 010 for Row 0 Col 23 FE18 Character Data FC17 FC18 How 1 Attribute ROW1 FC20 D8 D9 D10 for Row 1 Column 0 FC21 D8 D9 D10 for Row 1 Column 1 FE22 FC22 Through Row 1 Column 22 Row 1 Column Through Column D8 D9 D10 for Row 1 Col 23 22 Character Data FC37 aracter Data FC38 FC40 FC58 FC60 FC78 FC80 FC98 FCAO FCB8 FCCO FCD8
191. t Analog Peripherals and Support Tools Quick Reference Appendix D contains a quick reference of Memory Registers for experienced technical personnel The Glossary provides an easy guide to acronyms and terminology In addition the detailed Index combines with the Table of Contents List of Figures and List of Tables to make infor mation easier to access Essential information is at your fingertips eliminating the need to cross reference sepa rate sources exceptions may exist Please check the Product Specifica tion for the latest technical information on all supported devices m When the binary contents of a register are included in a text paragraph the number appears as a series of 1s and Os followed by B For example 11001110B Z90230 Family of DTCs Preface Zilog A register is described a figure with the following format Hexadecimal Address Register 08h Bank A BAR_POS Register Bank As Bar Position Register Read Write 4 Mode Appropriate Descriptive D7 pe ps p4 ps p2 p1 po lt Register Name Name of the Data Bits 7 0 Register Bar Column Position 6 Field HV SYNC Interrupt Option lt 1 Bit Field 0 Interrupt pending disabled Description Possible Field Values 0 and 1 1 Interrupt pending enabled of Reais Reserved Reserved Field Figure 0 1 Example of Register Notation Register Bits are numbered from right to left 0
192. t bits are 0 To enable counting the Enable Count bit D1 for TO and for T1 must be set to 1 Counting actually starts when the enable count bit is written by an instruction The first decrement occurs four internal clock periods after the enable count bit has been set If T1 is configured to use an external clock the first Zilog decrement begins on the next clock period The load and enable count bits can be set at the same time For example using the instruction OR TMR 03h sets both DO and D1 of the TMR This loads the initial values of PRE 0 and TO into their respec tive counters and starts the count after the M2T2 see Figure 3 28 machine state after the operand is fetched Register F3h PRE1 R243 Prescaler 1 Register Write Only Register F5h isteri R245 Prescaler 0 Register Write Only E Count Mode 0 T1 Single Pass 1 T1 Modulo N Figure 3 27 Starting The Count First Decrement Occurs 4 Clock Periods Later TMR is Written Counter Timer is Loaded 03h is Fetched Figure 3 28 Counting Modes 3 16 2 Prescaler Operations During counting the programmed clock source drives the 6 bit Prescaler Counter The counter is counted down from the value specified by bits of the corresponding Prescaler Register PREO 7 6 5 4 3 2 or PRE1 7 6 5 4 3 2 When the 3 26 Prescaler Counter reaches its end of count the initial value is reloaded and counting continues The prescaler never a
193. t does not indicate a register or memory address as the source operand Zilog The operand value used by the instruction is the value supplied in the operand field itself Because an immediate operand is part of the instruction it is always located in the program memory address space Program Memory OpCode Immediate Data The Operand value is in the instruction Figure 3 58 Immediate Data Addressing 3 37 INSTRUCTION SET FUNCTIONAL SUMMARY Instructions can be divided functionally into the following eight groups Load m Bit Manipulation m Arithmetic m Block Transfer m Logical m Rotate and Shift Program Control 3 54 CPU Control The following tables show the instructions belonging to each instruction group and the number of operands required for each The codes used for the operands are src Source Operand m dst Destination Operand m cc Condition Code UM97TELO700 Z90230 Family of DTCs Zilog Internal Microprocessor Overview Table 3 15 Load Instructions Table 3 19 Bit Manipulation Instructions Mnemonic Operands Instruction Mnemonic Operands Instruction CLR dst Clear TCM dst src Test LD dst src Load Complement LDC dst src Load Constant Under Mask LDE dst src Load External TM dst src Test Under Mask POP dst Pop AND dst src Bit Clear PUSH src Push OR dst src Bit Set Table 3 16 Arithmetic Instructions XOR dst src Bit Complement
194. t is the number of scan lines from the top of the display screen Bits 7 and 6 are reserved for future use If this register is read these bits return 1s Bits 5 4 3 2 1 and 0 Vertical Position specify the vertical position of the OSD window from the start of Vsync Register 01h Bank A VERT_POS Vertical Position Register Read Write D7 D6 D5 D4 D3 2 D1 Do Vertical Position Control Reserved Figure 4 4 Vertical Position Register The value required for this register may be computed using the following equation VERT_POS Vpog 6 4 VERT_POS represents the contents of bits 5 4 3 2 1 0 of the Vertical Position Register VERT_POS The default value is 0 When the Zilog value is 0 the OSD is at the top most OSD posi tion on the screen with an offset of 06h scan lines above the OSD area Vpos is the number of scan lines from the Vsync to the OSD start position Vpos must be a posi tive integer with a minimum value of Ah incre menting by 4 Some possible values include 10 14 18 22 26 30 For example Vpos 22 VERT_POS 22 6 4 VERT_POS 16 4 VERT_POS 4 The contents of the register VERT POS 5 4 3 2 1 0 should be for this example set to Register 01h Bank A VERT_POS Vertical Position Register Read Write fo oj o o Vertical Position Control Reserved Figure 4 5 Vertical Position Example 4 2 3 Horizontal Position R
195. ta line to allow the Master to generate the Stop condition 5 7 Z90230 FAMILY 12 MASTER INTERFACE 290230 family has the hardware module which supports the I C Master interface Bus arbitra tion and Masters arbitration logic is not imple mented in other words the Z90230 family is designed for a single Master application The IC interface can be configured to run at 4 different transfer speeds defined by bits 1 0 in the 2 Control Register 2 CNTL OCh Bank C In order to suppress possible glitches on both DATA and SCLK lines digital filters with time constant equal to is implemented on all inputs of the bus interface The 290230 family has two separate 2 busses which share the same control and data registers The 2 module is enabled by setting bit 2 in the CNTL register to 1 This bit blocks out 2 logic if it is set to 0 Figure 5 2 To prevent switching the 12 bus during activation bits 7 6 UM97TELO0700 5 3 Z90230 Family of DTCs Interface of the Port 2 Data Register for selection 1 bits 5 4 of Port 2 Data Register for 12 selec tion 0 should be set to 1 before the 2 module is enabled Notes 2 1 When the module is enabled pins used as must be configured as output Zilog in the Port 2 Mode Register P2M F6h If P27 P26 or P25 P24 are used pins then these pins are automatically set to open drain mode Port 2 must
196. tatus Register INT ST 07h Port 4 Pin Out Selection PIN SLT 08h Color Index Register CLR IDX 09h Master 2 Data Register 2 _ DAh Port Configuration Register PCON ooh 2 Command Register 2 CMD oBh 4 Bit ADC Data Register 4ADC_DTA 02h Port 6 Data Register PRT6_DTA 03h Mesh Column Start MC_St Mesh Column End MC End Mesh Row Enable MR En Mesh Control Register MC Reg 07h N A 08h N A 09h N A Stop Mode Recovery Register SMR OBh N A 0Ch N A ODh N A WDT Mode Register WDTMR OFh Master Control Register I C_CNTL Figure D 1 Expanded Register File D 2 UM97TEL0700 Z90230 Family of DTCs Zilog Registers Reset Condition Register pz pe ps p ps pe P po SPH RP Register Pointer p7 ps ps pa ps p p 00 FB IMR Working Register Expanded Register Group Pointer Bank Pointer F8 7 P2CNTL F6 F5 PRE0 4 _ Register File Ey ae T 1 FO Reserved Expanded Register Bank F Register Reset Condition F OF WDTMR F OE Reserved F OD Reserved OC Reserved 0B SMR Reserved 09 Reserved 08 Reserve 07 MC_Reg 06 MR_En 05 MC End 04 MC St PUP UP Uf Uf t 1 1 02 PRT6_DRT 01 4ADC DTA ofo JoJo U U U U o ov o
197. ter Address 76h Figure 3 3 Working Register Addressing Examples UM97TELO0700 3 3 Z90230 Family of DTCs Internal Microprocessor Overview Cro Z EF 80 C ___________ Specified Working Register Group Working Register Group 1 Working Register Group 0 I O Ports Zilog IR7 Re R5 R4 R3 R2 R1 Ro R253 Register Pointer The upper nibble of the register file address pon ed by the register pointer specifies he active working register group Working Register Group F The lower nibble of the register file address provided by the instruction points to the specified register R15 to RO R15 to R4 JERS to RO Figure 3 4 Register Pointer Note 1 The full register file is shown Please refer to the selected device product specification for the actual file size 3 2 4 Error Conditions Registers in the Standard Register File must be correctly used because certain conditions produce inconsistent results and should be avoided 3 4 Registers F3h and F5h F9h are Write Only registers If an attempt is made to read these registers FFh is returned Reading any Write Only register returns FFh When register FDh register pointer is read the least significant four bits lower nibble indicate the current Expanded Register File Bank For example 0000 indicates the standard register file while 1010 indicates Expanded Register File Bank A When Ports 0 and 1 are defined as address
198. terrupt Control 3 30 Interrupt Mask Initialization 3 34 Interrupt Priority Initialization 3 33 Interrupt Request 3 35 Interrupt Request Configuration 2 23 3 37 Index 3 Z90320 Family of DTCs Index Register Continued Interrupt Request Logic and Timing 3 32 Interrupt Request Map 2 22 3 36 Interrupt Status 4 28 IR Capture 0 ous eere test 7 4 IR Capture 7 4 Master 2 5 5 Mesh Column End 4 10 Mesh Column Start 4 9 Mesh Control 4 11 Mesh Row Enable 4 10 Port 4 Data 6 5 Port 4 Direction Control 6 6 6 9 Port 4 Pin Out Selection 2 13 6 3 8 2 Port Configuration 6 1 Prescaler uineis aysay 3 27 PWM Mode 8 2 PWM1 through PWM10 8 6 Ea tr Ceca 8 7 Quick Reference D 1 Row Attribute 4 27 Standard Z8 3 8 Stop Mode Recovery 2 16 3 21 3 43 Timer Control O _ 7 2 Timer Control T
199. tick SCLK 3 If these bits equal 11 ADC speed is based on one quarter of a system clock tick SCLK A B 1 Z90230 Family of DTCs Analog Peripherals Zilog B 1 1 3 Bit ADC Data Register Register 00h Bank C SADC_DTA 3 Bit ADC Data Register Read Write 1 ADC Data ADC Input Selection 00 Select ADC0 POR 01 Select ADC1 10 Select ADC2 11 Select ADC3 ADC Speed 00 No ADC POR 01 SCLK 2 10 SCLK 3 11 SCLK 4 Reserved Figure B 1 3 Bit ADC Data Register B 1 2 4 Bit ADC Data Register Register 01h Bank F 4ADC_DTA 4 Bit ADC Data Register Read Write 1 ADC Input Selection 00 Select ADC0 POR 01 Select ADC1 10 Select ADC2 11 Select ADC3 ADC Speed 00 No ADC POR 01 SCLK 2 10 SCLK 3 11 SCLK 4 Figure B 2 4 Bit ADC Data Register P41 must be set to input mode for ADC 1 selection B 2 UM97TELO0700 Z90230 Family of DTCs Zilog Analog Peripherals B 1 3 ADC Block Diagram Comparators Ww 1 Analog Multiplexer lt ADC Data Decoder 3 Register zu ADC2 ADC3 Control G z D Figure B 3 ADC Block Diagram UM97TEL0700 B 3 USER S MANUAL APPENDIX SUPPORT PRODUCTS C 1 Z90230 FAMILY SUPPORT PRODUCTS The following development tools are available for use with the Z
200. to the Z90230 data registers The following registers are contained in this appendix Description Page Expanded Register File D 2 Register and Expanded Register File Map D 3 OSD Control Register D 4 Vertical Position Register D 4 Display Attribute Register D 4 Display Attribute Register D 5 Row Space Register D 5 Fade Position Register 1 D 6 Fade Position Register 2 D 6 Second Color Control Register D 6 Second Color D 6 Color Palette 0 D 7 Color Palette 1 xs hes D 7 Color Palette 2 D 7 Color Palette 3 D 7 Color Palette 4 D 8 Golor Palette ore ertet D 8 Color Palette 6 D 8 PWM11 Register D 8 PWM1 through PWM10 Registers D 9 Row Attribute Register D 10 Port 5 Data Register D 10 PWM Mode D 11 Port 5 Direction
201. tput MDS MCU Data Strobe MDATAO MDATA 7 MCU Data Input Bits 0 through 7 UM97TELO700 B3 A1 D4 MADR14 MADRO MCU Address Output Bits 14 through 0 NC No Connection OSDX1 OSDX2 On Screen Display Dot Clock Oscillators OSDX1 and OSDX2 These oscillator input and output pins for on screen display circuits are connected to an inductor and two capacitors to generate the character dot clock The dot clock frequency determines the char acter pixel width and phase synchronized to HsYNC P21 Port 2 Pin 1 P22 P23 Port 2 Pins 2 and 3 P40 Port 4 Pin 0 Bidirectional digital port config ured to read digital data or to send output to an attached device This pin is not multiplexed P42 43 Port 4 Pins 2 and 3 R Red CMOS output of the red video signal R Y Video red is programmable for either polarity RESET System Reset SCLK System Clock 2 7 Z90230 Family of DTCs Architectural Overview SIZE System ROM Size When the value is 0 available system ROM is 16 KB When the value is 1 available system ROM is 32 KB SYNC Last Timer Cycle VBLANK Video Blank CMOS output program mable polarity This pin is used as a super impose control port to display characters from video RAM The signal controls Y signal output of CRTs and turns off the incoming video display while the characters in video RAM are super imposed on the screen The output ports of color data directly drive three electron guns
202. tware 7 1 Z90230 Family of DTCs Infrared Interface 7 1 1 Timer Control Register 0 Register 01h Bank C TCR0 Timer Control Register 0 Read Write D7 pe bs p4 ps p2 p1 o Zilog Tout_CAP Read 0 No Timeout of the Capture Timer 1 Timeout of the Capture Timer Write 0 No Effect 1 Reset Flag CAPint_f Read 0 No Falling Edge is Captured 1 Falling Edge is Captured Write 0 No Effect 1 Reset Flag CAPint_r Read 0 No Rising Edge is Captured 1 Rising Edge is Captured Write 0 No Effect 1 Reset Flag Reserved Figure 7 1 Timer Control Register 0 Rising edge falling edge interrupt is preserved even when a falling edge rising edge interrupt occurs But it is overridden by a second rising edge falling edge if the second one occurs before the first rising edge falling edge is serviced Preservation of the interrupt means that it will generate the hardware interrupt after the first interrupt is serviced when two different rising edge falling edge interrupts are already ON During the interrupt service routine software must read the contents of this register Then it checks which bit is set to 1 indicating the type of edge which generated the interrupt see Table 7 1 7 2 Table 7 1 IR Interrupt Captured Values D2D1D0 Edge Timeout 100 Rising No 101 Rising Yes 010 Falling No 011 Falling Yes 110 Rising Falling No 111 Rising Falling Yes U
203. ulator Pin Functional Description Example output ports If a bit is reset to O the pin outputs the PWM signal This setting is the default 8 1 Z90230 Family of DTCs Pulse Width Modulators value following a Power On Reset If a bit is set to 1 the pin serves as a regular output port Register 0Dh Bank P_MODE PWM Mode Register Read Write 27 56 25 24 D3 D2 1 Do Bit 7 is reserved PWM 1 0 Select PWM 1 1 Select P50 POR PWM 2 0 Select PWM 2 1 Select P51 POR PWM 3 0 Select PWM 3 1 Select P52 POR PWM 4 0 Select PWM 4 1 Select P53 POR PWM 5 0 Select PWM 5 1 Select P54 POR PWM 6 0 Select PWM 6 1 Select P55 POR PWM 11 0 Select PWM 11 1 Select P56 POR Reserved Figure 8 1 PWM Mode Register 8 1 2 Port 4 Pin Out Selection Register Bits 5 4 3 and 2 control the configuration of multiplexed pins 20 19 18 and 17 If a bit is reset to 0 the pin functions as a PWM output 8 2 Zilog port This value is the default following a Power On Reset If a bit is set to 1 the pin functions as a programmable regular input output port UM97TELO700 Zilog Register 08h Bank C PIN SLT 290230 Family of DTCs Pulse Width Modulators Port 4 Pin Out Selection Register Read Write D7 be p5 p4 ps p2 p1 po NEN Reserved Reserved P44 PWM7 0 Selects PWM7 1 Selects P44 POR
204. umber in the range of 00h to FFh UM97TELO0700 3 59 Z90230 Family of DTCs Internal Microprocessor Overview Zilog Table 3 26 Notational Shorthand Continued Notation Address Mode Operand Range or Indirect Working Rn 0 15 Register Irr Indirect Working RRp p 0 2 4 6 8 10 12 or 14 Register Pair IRR Indirect Register Pair Reg Reg represents an even number in the range 00h to FFh or Working Register Pair RRp 0 2 4 6 8 10 12 or 14 X Indexed Rn Reg represents a number in the range of 00h to FFh and n 0 15 DA Direct Address Addrs Addrs represents a number in the range of 00h to FFh RA Relative Address Addrs Addrs represents a number in the range of 127 to 128 which is an offset relative to the address of the next instruction IM Immediate Data Data is a number between 00h to FFh Note Additional notation includes 1 See the device product specification to determine the exact register file range available The register file size varies by the device type Table 3 27 Additional Notation Symbol Definition dst Destination Operand src Source Operand Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS Flag Register FCh RP Register Pointer FDh IMR Interrupt Mask Register FBh Immediate Operand Prefix Hexadecimal Number Prefix h Hexadecimal Number Suffix b Binary Number Suffix OPC Opcode
205. und the Horizontal Hsync Interrupt and the Vertical Vsync Interrupt A Vsync interrupt marks the time a new field of a frame is to be displayed beginning with Row 0 UM97TELO700 Zilog The display of subsequent rows coincides with the issuance of the Hsync interrupt The inter rupts mark the time when the display of a row or start of a field is to occur Software must be ready to properly output the OSD when the inter rupts are issued Each text row is comprised of 18 scan lines Each scan line takes 63 5 us to be displayed So 1143 us is the amount of time available for changing the programming for the next row Double size characters span 36 scan lines allowing 2286 us for programming the next 4 8 1 HV Interrupt Status Register Register 07h Bank C INT ST HV Interrupt Status Register Read Write 07 De 05 D4 0302 0100 290230 Family of On Screen Display row Additional programming time is with inter row spacing During that time VRAM is updated If the program has too much to display black lines appear at the top of the screen The HV Interrupt Status Register keeps track of the type of interrupt that is issued horizontal or vertical Horizontal Interrupt Read 0 No Horizontal Interrupt 1 Horizontal Interrupt Write 0 No Effect 1 Reset Horizontal Interrupt Flag Vertical Interrupt Read 0 No Vertical Interrupt 1 Vertical Interrupt Write 0 N
206. ure 2 13 Prescaler 1 Register 2 3 10 Counter Timer 0 Register Register F4h TO R244 Counter Timer 0 Register Write Read s psppapsppappo Initial Value When Written Range 0 255 decimal 00 FFh Current Value When Read Figure 2 14 Counter Timer 0 Register 2 18 UM97TELO700 Z90230 Family of DTCs Zilog Architectural Overview 2 3 11 Prescaler 0 Register Register F5h PRE0 R245 rite Only a Count Mode 0 Single Pass 1 TO Modulo N Clock Source Must be 1 Prescaler Modulo Range 1 63 Decimal 01 SFh Figure 2 15 Prescaler 0 Register UM97TELO0700 2 19 Z90230 Family of DTCs Architectural Overview Zilog 2 3 12 Port 2 Mode Register Register F6h P2M Port 2 Mode Register Write Only aS PE 5 EI L P20 I O Definition 0 Defines P20 as Output 1 Defines P20 as Input P21 I O Definition 0 Defines P21 as Output 1 Defines P21 as Input P22 I O Definition 0 Defines P22 as Output 1 Defines P22 as Input P23 I O Definition 0 Defines P23 as Output 1 Defines P23 as Input P24 I O Definition 0 Defines P24 as Output 12 Defines P24 as Input P25 I O Definition 0 Defines P25 as Output 12 Defines P25 as Input P26 I O Definition 0 Defines P26 as Output 1 Defines P26 as Input P27 Definition 0 Defines P27 as Output 1 Defines P27 as Input Figure 2 16 Port 2 Mode Register 2 3 13 Port 2 Control Register Register F7h P2CNTL
207. utput POR P61 0 Open Drain Output 1 Push Pull Output POR P62 0 Open Drain Output 1 Push Pull Output POR P63 0 Open Drain Output 1 Push Pull Output POR Figure 6 11 Port 6 Direction Control Register UM97TELO700 6 11 7 1 INFRARED INTERFACE The Z90230 family easily supports the Infrared IR Remote Control interface with a minimum of software overhead The Digital Television Controller DTC has a hardware IR capture module which consists of m Timer Control Register0 TCR0 01h Bank C m Timer Control Register1 TCR1 02h Bank C m Capture Register0 IR_CP0 03h Bank m IR Capture Register1 IR_CP1 04h Bank C The IR capture registers are the Low and High bytes of the IR Capture Counter UM97TEL0700 USER S MANUAL CHAPTER 7 INFRARED INTERFACE After an IR interrupt occurs the software clears the corresponding interrupt flag bit Two bytes of data are received through the Infrared IR Interface The upper byte bits 15 8 is stored in IR Capture Register 1 The lower byte bits 7 0 is stored in IR Capture Register 0 When an IR interrupt occurs the IR capture registers contain the amount of time passed from the previous IR interrupt if bit 0 in the TCRO is set to 0 If bit 0 is set to 1 the IR capture registers contain the amount of time passed from the last overflow of the IR capture counter The IR inter rupt flags are reset by the IR interrupt service routine sof
208. variable duty cycles If show fixed voltage samples while case C such a signal is passed through an RC inte shows a varying voltage example grator the output is a DC voltage proportional to 97 0700 8 7 Z90230 Family of DTCs Pulse Width Modulators Zilog PWM Signal DC Signal Vcc Voltage Case A Time PWM Signal DC Signal Voltage Voc Case B PWM Signal DC Signal Ame Voltage Voc Case C PWM Signal DC signa lime Figure 8 7 Analog Signals Generated from PWM Signals 8 8 UM97TELO700 USER S MANUAL APPENDIX PHILIPS IC SPECIFICATION A 1 PHILIPS SPECIFICATION This section comprises reference documentation The specification contained in this section pro for the 2 bus The material includes detailed in vides the standard that the Z90230 family sup formation about application design as well as a ports and to which application products should technical description of the bus itself conform 97 0700 1 1 ANALOG TO DIGITAL CONVERTER The Z90230 family is equipped with a 3 bit or 4 bit depending on software configuration flash analog to digital converter ADC with four multi plexed analog input channels There are two register addresses one for 93 bit ADC SADC 00h Bank C and the other for 4 bit ADC 4ADC_DTA 01h Bank F Because no de fault is set
209. ytes transmitted or received by a Master during one communication session is unrestricted Each byte must be followed by an acknowledgment bit Data is transferred with the most significant bit MSB first If the Slave is not capable to receive or transmit another complete byte of data in one continuous stream it can hold 5 2 the SCLK line Low to force the Master into a wait state Data transfer is automatically resumed when the Slave releases the SCLK line The Slave may start to hold clock line Low only during the lower period of the clock pulse generated by the Master UM97TELO700 Zilog 5 6 ACKNOWLEDGE Acknowledgment of a data transfer is obligatory The acknowledge related clock pulse is gener ated by the Master The transmitter releases the SDATA line changing it to High prior to the acknowledge clock pulse The receiver changes the SDATA line during the acknowledge clock pulse ACK so it remains stable and Low during the upper period of the clock pulse Figure 5 1 When a Slave receiver does not acknowledge NAK a transmitted byte the data line is left 290230 Family of DTCs Interface High by the Slave during the acknowledge clock pulse and the Master can generate a Stop condition to abort the transfer The Master receiver must signal the end of data to the Slave transmitter by not generating an acknowledge on the last byte that was trans ferred from the Slave The Slave transmitter must release the da

Z90230 Family of Digital Television Controllers User`s Manual

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