XEM7350 User`s Manual
Contents
1. 13 Igio zin iie CDD 14 Reset Profile dcr pice tociens 14 System Flash 3 524 255 Errio tiA REEE ditus a 14 Layout 14 Loading a Power On FPGA Configuration 14 Clock Osolllatol rioris done bah erano eoru hie 15 S n acte ataca us inb eR Ed eb ud iuit aaa fud 15 Hop Wr c MEET E 16 JIAG eo rrr 16 DDRS SDRAM auus earn dra diye qaa Rene A dole De uqg Grace 16 Clock Configuration Source Synchronous 17 MIG Settings dine Ree eee es 17 Key Memory Storage kisis 18 Volatile Encryption Key Storage 19 Non Volatile Encryption Key Storage eFUSE 19 Device Sensors coeno rer ex Rer 19 DEVICE dao garcia dedo Sum 20 FMC Device Settings 20 Fan Control Device Settings 20 Expansion Connector 21 Fan Power SUDDlV akui aka baa 24 PMCsAPG ss uwa de eee oed P beware oe 22 Setting the FMC Vans I O Voltage LA and HA Groups 22 FMC Vio HB GIOUD gt Garand ead dt ated eared ae a 23 KADC Optional seis disita 85 53 90 5 60 94 2 208 23 Considerations for Differential Signals 23 Gigabit MAaNSCEIVCRSs u uu roses shaq ata dnd 24 Gigabit Transceiver IBERT Performance 24 dels cdc Gad eas rcu E Oed2. Viu Clock pairs HB Vio Clockpairs Setting the FMC Vans I O Voltage LA HA Groups FMC specifies a single adjustable voltage Vany for the two LA groups that are routed to FPGA banks 15 and 16 and the HA group routed to FPGA bank 12 A high efficiency switching regula tor on the XEM7350 controls this voltage and is configured according to Device Settings FMC1_ VADJ MODE FMC1 VADJ VOLTAGE FMC1 VADJ ENABLE When FMC1 VADJ MODE 2 default the contents of the IPMI EEPROM on the FMC periph eral are queried If the contents are valid VapJ is set to the voltage specified If the contents are not valid then Vans is set to the FMC1 VADJ VOLTAGE as fallback When FMC1_VADJ_MODE 1 the contents of the IPMI EEPROM are queried If the contents are valid Vans is set to the voltage specified If the contents are not valid then the voltage output is disabled When FMC1_VADJ_MODE 3 the contents of the IPMI EEPROM are ignored Vans is set to the value in FMC1 VADJ VOLTAGE When FMC1_VADJ_MODE 0 Vadj output is disabled Valid output voltages are 3 3v 2 5v 1 8v 1 5v 1 25v 1 2v and 0 8v www opalkelly com XEM7350 User s Manual FMC Vio HB Group The pins on the FMC HB group are routed to FPGA bank 32 Vcco for this bank is connected to FMC_VIO_B_M2C which is a voltage provided by the mezzanine peripheral to the carrier 7350 Please see the Xilinx Kintex 7 User s Manual for details on ac
3. SDK a powerful C class library available to Windows Mac OS X and Linux pro grammers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for C Java and Python making the API available under those languages as well Sample wrappers unsupported are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel www opalkelly com 9 XEM7350 User s Manual 10 www opalkelly com XEM7350 User s Manual Applying the XEM7350 Powering the XEM7350 The XEM7350 requires a clean filtered DC supply within the range of 4 5v to 5 5v This supply must be delivered through the DC power connector The XEM7350 power distribution system is rather complex with several supplies designed to provide suitable efficient power for several systems and modules A schematic diagram of the system follows with input VDC shown to the left and accessible supply rails shown to the right www opalkelly com 11 XEM7350 User s Manual Current Sensor Linear Supply O Voltage Sensor Switching Supply Jumper FMC 12 R48 VDC 3 3v 6A ie FMC 3P3V 4 5 to 5 5v EMC 3P3VAUX System Controller FPGA Vccio DDR3 Memory 2 0v 0 4A DDR3 Termination 1 8v 1 5A FO 1 Sv 1 O GTP Transceiver Aux 1 2v 0 4A 1 0v 9A KO FPGA Vccint 1 8v 1 5 GTP Transceiver Termination 1 5v 3A GTP Tran
4. between clock and data MIG Settings Kintex 7 devices support external high performance memory through the use of the Memory Interface Generator MIG provided by Xilinx MIG produces a custom memory interface core that may be included in your design These parameters have been used successfully within Opal Kelly but your design needs may require deviations www opalkelly com 17 XEM7350 User s Manual Reference Clock Type Debug Por Internal Vref IO Power Reduction DCI for DQ 005 DM internal Termination Memory Interface Design Clock Frequency 250ps 800 0 MHz Phy to Controller Ratio Input Clock Period 000ps CLKFBOUT MULT DIVCLK DIVIDE Memory Type Memory Part Data Width EC Data Mask gem Burst Length Read Burst Type CAS Latency Output Drive Strength Controller CS Option Rt NOM ODT Rtt WR Dynamic ODT Memory Address Mapping Bank 33 Bank 34 Byte Group TO Address Ctrl 0 Byte Group T1 Address Ctrl 1 Byte Group T2 Address Ctrl 2 Byte Group T3 DQ 0 7 Key Memory Storage The Kintex 7 FPGA supports design security using AES decryption logic and provides two methods for encryption key memory storage The first is a volatile memory storage supported by an external battery backup supply voltage VBATT The second is a one time programmable eFUSE register The XEM7350 design supports both types of key storage with user modification required for VBATT support 18 www opalkelly com XEM7350
5. fan control PWM 0 At THRESH 16C fan control PWM 50 At THRESH 32C fan control PWM 100 Expansion Connector Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins Fan Power Supply A small 2 pin connector Molex 53398 0271 at JP1 provides power to an optional fan for FPGA cooling This fan is under direct or temperature proportional control of a digital fan controller Please see the Device Settings section for details on controlling the fan www opalkelly com 21 XEM7350 User s Manual 22 FMC HPC A single FMC HPC high pin count connector provides direct access to I O pins and Gigabit transceiver on the FPGA The tables below illustrate the number of pins that are available on an FMC HPC connector and the number that are routed to available sites on the FPGA LA Van VO pairs Vani VO pais m AB Vio WO pairs 2 b h Clock Pins Clock pins are given special attribution within the FMC specification Available clock pins are il lustrated in the table below Bank Group voltage FMC HPC 70T 160T 410T LA Vai Clock pairs
6. through the VITA website http www vita com fmc html8 The XEM7350 specifically supports the HPC high pin count version of the specification Note the K70T does not have a fully populated HPC connector For details on supported FMC features please see the FMC Feature Support section FMC connectors are manufactured by Samtec The FMC connector on the XEM7350 is the Samtec ASP 134486 01 The mating con nector which would appear on an FMC peripheral is the Samtec ASP 134488 01 These are both surface mount pin field array style connectors The connectors ship with a solder plug on each connector which melts during reflow to the solder paste spread on the bare board for assembly Connector contact is solid and insertion and removal forces are relatively small High frequency performance is up to 9 5 GHz in single ended operation and to 10 5 GHz in differential operation FrontPanel Support The XEM7350 is fully supported by Opal Kelly s FrontPanel Application FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex dis plays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigurable I O board and adds tremendous value to the XEM7350 as an experimentation or prototyping system 8 www opalkelly com XEM7350 User s Manual Programmer s Interface In addition to complete support within FrontPanel the XEM7350 is also fully supported by the FrontPanel
7. utilization Pt ar ita Supply Heat Dissipation IMPORTANT Due to the limited area available on the small form factor of the XEM7350 and the density of logic provided heat dissipation may be a concern This depends entirely on the end application and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM7350 Of primary focus should be the FPGA U8 and SDRAM U12 Although the switching supplies are high efficiency they are very compact and consume a small amount of PCB area for the current they can provide If you plan to put the XEM7350 in an enclosure be sure to consider heat dissipation in your design Heat Sink The device has been fitted with two heat sink anchors proximate to the FPGA for mounting a passive or active heat sink The following heat sinks have been tested with the XEM7350 www opalkelly com 13 XEM7350 User s Manual Part Number Aavid Termalloy 374524B60023G Off the shelf passive Aavid Termalloy 3358230 PAL03010 PO Custom with fan mount The passive heat sink above is a low cost option available through Aavid Thermalloy distributors such as Arrow Electronics and Newark Electronics The active heat sink above was custom built based on design specifications provided by Opal Kelly to mate to the XEM7350 It includes a small fan which connects to the fan controller on board for manual or automatic fan speed control It is av
8. 0 25 362 0 P2B 67 pix reset x 533 L50P 0 21 102 0 P2B 68 AA ema VCMOS33 L51N 0 23 293 0 P2B 69 RESET pix reset IOSTANDARD LVCMOS33 L50N 0 19 964 0 P2B 70 PIX6 pix data 6 IOSTANDARD LVCMOS33 Specifying Net Names The Pin List view for a Peripheral includes three additional editable columns Design Net The name of the signal as it appears in your top level HDL Constraints Text that is inserted into the constraints file for that signal Comment Additional comment text that is added to the constraints file These additional data are merged with the default Pin List constraints file prior to export The re sult is a constraints file complete with net names that can be used with your FPGA development flow www opalkelly com XEM7350 User s Manual Export Features Constraint file template Default Enable the specific module features you would like to appear in the exported con UE NETS Rud straints file When a feature is enabled Pins will export the constraints appropri Export features lead In ate to that feature such as pin locations Z FrontPanel When a feature is disabled Pins will skip Z FrontPanel Timing that portion System Clock Reset The User Lead In and User Lead Out Wu c eee sections allow you to add custom pay loads your own constraints that will be Pes added to the exported constraints file Additional timing constraints or com ments can be added here _ User Lead
9. 350 User s Manual The DDR3 SDRAM is a Micron MT41K256M16HA 125 E or compatible FPGA Flash 16 MiB Serial Flash Memory A 128 Mib serial flash device Numonyx N25Q128A11B1240E or equivalent provides on board non volatile storage for the FPGA This device is attached directly to the FPGA for use in your design System Flash 16 MiB Serial Flash Memory A 128 Mib serial flash device Numonyx N25Q128A11B1240E or equivalent provides on board non volatile storage accessible to the USB microcontroller This device is used to store device firmware and configuration settings as well as other user assets such as FPGA configuration files or calibration data Erase read and write functions are available at all times with or without a configured FPGA through the use of FrontPanel API methods LEDs Four LEDs and are available for general use as indicators FPGA Fan Controller A small connector provides power to an optional 5v fan mounted on the FPGA heat sink This power is under the control of the microcontroller Device Sensors On board voltage and current sensors provide real time access to several power supply mea surements through the FrontPanel SDK sensors API FMC Expansion Connector FMC FPGA Mezzanine Connector is the common name for the VITA 57 specification which describes a common connector design to interface large pin counts to devices with configurable I O such as an FPGA The specification is available for purchase
10. 7 2 Opal Kelly XEM7350 User s Manual A compact 80mm x 70mm FMC carrier featuring the Xilinx Kintex 7 FPGA SuperSpeed USB 3 0 on board DDR3 memory and two 16 MiB Flash memories The XEM7350 is a compact USB 3 0 SuperSpeed FPGA integration module featuring the Xilinx Kin tex 7 FPGA 4 Gib 256 Mx16 bit DDR3 SDRAM two 128 Mib SPI Flash devices high efficiency switch ing power supplies and a single FMC HPC expansion connector with full gigabit transceiver capability The USB 3 0 SuperSpeed interface provides fast configuration downloads and PC FPGA communication as well as easy access with our popular FrontPanel application and SDK Two low jitter crystal oscilla tors 100 MHz and 200 MHz are attached to the FPGA Software documentation samples and related materials are Copyright 2014 2015 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark righ
11. D the FPGA pin should be at logic 0 To turn OFF an LED the FPGA pin should be at logic 1 The JTAG connections on the FPGA are wired directly to the 2mm header JP2 on the XEM7350 to facilitate FPGA configuration and ChipScope usage using a Xilinx JTAG cable The JTAG interface presented at JP2 is a 1 8v interface By design the FMC module is intended to complete the JTAG chain If a mezzanine module is not present or does not properly complete the chain the chain may be bypassed using SW1 or optionally installing a 0 O resistor at location R56 To accommodate the FMC requirement that the JTAG chain operate at 3 3v level shifters are present on board Installing 0 Q resistor at location R73 keeps the entire chain at 1 8v but U33 must also be removed to avoid drive contention from the 3 3v side to the 1 8v side Level JP2 Shift p 18v 33v Module Shuttle TX1 1 R56 is not installed at the factory DDR3 SDRAM 16 The Micron DDR3 SDRAM is connected exclusively to the 1 5 v I O on Banks 33 and 34 of the FPGA The tables below list these connections www opalkelly com XEM7350 User s Manual DDR3Pin FPGA Pin RESET AM m Clock Configuration Source Synchronous The DDR3 clocking is designed to be source synchronous from the FPGA This means that the FPGA sends the clock signal directly to the SDRAM along with control and data signals allowing very good synchronization
12. Out Add payload www opalkelly com 29 XEM7350 User s Manual PCB Version History 20131121 First production PCB 30 www opalkelly com XEM7350 User s Manual www opalkelly com 31 XEM7350 User s Manual XEM7350 Mechanical Drawing 80 001 78 62 74 00 72 00 i 69 36 65 38 62 66 57 25 50 00 13 06 8 56 2 03 All dimensions in mm 32 www opalkelly com
13. SK qe Seman Zr 26544644 ER 4 cei ua qua ua 27 PU ASUS uU L beh PCT 27 gil cbe 28 SEI c baa s dudo Saver tution 28 Export PDF CSV Constraints Files 28 3 2 222202 d tios e exo ga kaqa iei 28 PCB Version History draconem mm em es 30 OA epp TP PP 30 XEMT7350 Mechanical Drawing 32 XEM7350 User s Manual Introducing the XEM7350 The XEM7350 is a compact FPGA board featuring the Xilinx Kintex 7 FPGA and SuperSpeed USB 3 0 connectivity via a USB 3 0 Micro B receptacle Designed as a full featured integration and evaluation system the XEM7350 provides access to over 170 I O pins on its 676 pin Kin tex 7 device and has 512 MiByte DDR3 SDRAM available to the FPGA Two SPI Flash de vices provide a total of 32 MiB of non volatile memory one attached to the USB microcontroller and one attached to the FPGA Available with LX70T LX160T and LX410T FPGA densities the XEM7350 is designed for high performance system integrations with transceiver capable FMC modules including JESD204B data converters PCB Footprint A mechanical drawing of the XEM7350 is shown at the end of this manual The PCB is 80mm x 70mm with four mounting holes M2 metric screws spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM7350 The two connectors USB and DC power overhang the PCB by approximately 1 3mm in orde
14. User s Manual For quantity purchases of 50 or more units please contact Opal Kelly sales opalkelly com to discuss factory installation of these components Volatile Encryption Key Storage VBATT A small lithium rechargeable battery and three support components can be installed to provide Vaarr to the FPGA when the XEM is unpowered This will preserve the contents of the FPGA s volatile key storage so long as Vaarr remains over the threshold specified in the Kintex 7 docu mentation Please see the Xilinx 7 Series FPGA s Configuration UG470 for more details The applicable schematic section and components required to support this functionality are shown below Manufacturer P N Seiko Instruments TS518FE FL35E 1 5V 1 5mAh lithium battery D5 Micro Commercial BAS40 04 TP Eum Dese son Diode SOT23 R78 Generic 4 7 kQ 5 SM 0402 R139 Generic 0 SM 0402 VBarr to Required if not used D 5 540 04 NoLoad 4 7k 5 NoLoad CL US518FE FL35E NoLoad DGND Non Volatile Encryption Key Storage eFUSE Non volatile storage of the encryption key is also possible by programming the Kintex 7 eFUSE register via JTAG Please see the Xilinx 7 Series FPGAs Configuration UG470 for more details Device Sensors On board device sensors provide measurements of a number of device parameters These may be read via the FrontPanel Device Sensors API and ca
15. ailable for purchase directly from Opal Kelly The assigned part number should allow you to order direct from Aavid if desired Host Interface There are 41 signals that connect the on board USB microcontroller to the FPGA These signals comprise the host interface on the FPGA and are used for configuration downloads After con figuration these signals are used to allow FrontPanel communication with the FPGA If the FrontPanel okHost module is instantiated in your design you must map the interface pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file Please see the sample projects includ ed with your FrontPanel installation for examples Reset Profile RESET Pin AB8 of the FPGA is an active high RESET signal from the host interface This signal is as serted when configuration download begins and is deasserted during the execution of the Reset Profile For more information on the timing of this deassertion event see the FrontPanel User s Manual System Flash The Flash memory attached to the USB microcontroller stores device firmware and settings as well as user data that is accessible via the FrontPanel API The API includes three methods for accessing this memory FlashEraseSector FlashWrite and FlashRead Please refer to the FrontPanel User s Manual and the FrontPanel API Reference for information about applying these m
16. anon style 2 1mm 5 5mm jack The outer ring is connected to DGND The center pin is connected to VDC 6 www opalkelly com XEM7350 User s Manual Powering via USB Note Read this section carefully before applying this technique The XEM7350 power consump tion depends greatly on the FPGA and device configuration and could easily exceed available power from USB The XEM7350 has been designed to accept power 5VDC only via the USB connector with a small modification To power from USB you will need to install a 0 Q resistor 0402 dimension at location R30 located on the reverse side of the PCB under the power connector This will con nect the 5VUSB from the USB connector to the 5VDC on the XEM7350 With this resistor in place you should not apply 5VDC to the external power connector Powering via the FMC Connector Note Read this section carefully before applying this technique This technique is not part of the FMC standard so will not work with other FMC carriers The XEM7350 has been designed to accept power 5VDC only via the FMC connector with a small modification To power from the FMC peripheral you will need to install a 0 O resistor 0402 dimension at location R48 located on the top side of the PCB near the JTAG bypass Switch This will electrically connect the device 5VDC to 12PV0 pins C35 and C37 on the FMC connector With this resistor in place you may apply 5VDC NOT 12v as is indicated by the FMC nam
17. apacitors are installed between the FMC connector and the FPGA for all MGTREFCLK signals AC coupling capacitors are not installed for any of the GTP transmit or receive pairs If AC cou pling is desired or required for the serial application they should be installed on the peripheral side your board IBERT Configuration Xilinx provides the IBERT tool to test and experiment with gigabit transceivers The settings below are compatible with the XEM7350 using Vivado 2013 4 Protocol Definition Silicon Version General ES Production Protocol Custom 1 Line Rate 6 6 Gbps Data Width 32 RefCIk 100 000 MHz Quad Count 2 Quad PLL Checked Protocol Selection GTX Location QUAD 115 QUAD 116 Protocol Selected Custom 1 6 6 Gbps Custom 1 6 6 Gbps RefCIk Selection MGTREFCLK1 115 MGTREFCLK1 115 TXUSRCLK Source Channel 0 Channel 0 Clock Settings Add RXOUTCLK Probes Unchecked Clock Type System Clock Source External Standard LVDS P Package Pin ACA N Package Pin AC3 Frequency 200 MHz Enable DIFF Term Unchecked Gigabit Transceiver IBERT Performance Xilinx s IBERT tool enables an automated self measurement of a GTP channel s eye diagram when used in a loopback mode Eye diagrams for three different speeds were captured using this 24 www opalkelly com XEM7350 User s Manual tool on an FMC loopback peripheral While results may vary these were rather typical captures and actually represent the worst case capture ov
18. ceptable voltages XADC Optional The Xilinx Kintex 7 XADC feature is routed through two resistors to the FMC connector In the factory configuration these two resistors are not inserted In the FMC specification B24 and B25 locations are transceiver pin locations These pins are otherwise not used on the XEM7350 FPGA Function FPGA Pin Resistor RefDes ADO VNO ADO VP 0 Considerations for Differential Signals The XEM7350 PCB layout and routing has been designed with several applications in mind including applications requiring the use of differential LVDS pairs Please refer to the Xilinx Kintex 7 datasheet for details on using differential I O standards with the Kintex 7 FPGA FPGA I O Bank Voltages In order to use differential I O standards with the Kintex 7 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Kintex 7 datasheet Please see the section above entitled Setting the FMC Vans I O Voltage for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is approxi mately 500 Differential Pair Lengths In many cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also included the lengths of the board routes for these connections
19. er all channels for the respective rates Note that in loopback modes it is often helpful to disable the GBT DFE decision feedback equal izer to avoid over compensation In these test cases the DFE has been disabled 3 3 Gbps XEM7350 K70T Unit Interval 0 312 0 0 312 BER Voltage Codes 6 6 Gbps XEM7350 K70T Unit Interval 0 5 0 375 0 25 0 125 0 0 125 0 25 0 375 0 5 100 1 1 1 2 1E 3 0 5 4 1 4 50 5E 5 1 5 SE 6 100 1E 6 www opalkelly com 25 Voltage Codes XEM7350 User s Manual 8 0 Gbps XEM7350 K160T 0 5 0 375 0 25 0 125 0 Voltage Codes 26 www opalkelly com 0 375 BER XEM7350 User s Manual Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins Toolbar The toolbar at the top of a Pins product page has a number of features Explore a bit you won t break it Click for column selection and filters Y Export PDF CSV or constraints file PRODUCT XEM6310 choose J Click for symbol legend Drop down for search behaviors Im Pin Lists As the primary reference
20. ethods Layout The Numonyx N25Q128A11B1240E is a 16 MiB Flash memory arranged into 256 64 kiB sectors Each sector contains 256 256 byte pages Sectors 0 15 are reserved for device firmware and settings and are not accessible to user software The remaining 15 MiB may be erased written and read using the FrontPanel API at any time even without a valid FPGA configuration Full 64 kiB sectors must be erased at a time However contents may be read or written on any page address boundary Loading a Power On FPGA Configuration The user area in System Flash may be used to store a Xilinx bitfile to configure the FPGA at power on Power on configuration takes approximately 6 10 seconds from when power is ap plied A full Reset Profile may also be performed after configuration 14 www opalkelly com XEM7350 User s Manual The API is used to erase and program the power on bitfile and the Flashloader sample is pro vided to perform these steps from a simple command line utility Source code to the Flashloader sample is included with the FrontPanel SDK Called with a single argument the filename for a valid Xilinx bitfile the Flashloader sample will erase the first sectors in the System Flash user area then write the bitfile It will also setup the Boot Reset Profile to point to this area on power on No Power On Configuration Called with no arguments the Flashloader sample will clear the existing Boot Reset Profile This has the effec
21. for Opal Kelly integration module expansion connectors Pin Lists con tain a comprehensive table of the FPGA to Connector data including connector pin FPGA pin signal description routed length when applicable breakout board pin mapping FPGA I O bank and other properties By default not all data columns are visible Click on the Toggle Filters icon at the top left to se lect which columns to show Depending on the specific module several additional columns may be shown The data in these columns is always exported when you export the pin list to CSV PRODUCT E ge XEM6310 cHoose PRopucr 2 J DISPLAY OPTIONS Reset filters Connector all Power all Ground all Power all VO all VOBank all JTAG all Clock all FPGA Clockin all TABLE LAYOUT Drag to rearrange columns click to show and hide columns CONNECTOR PIN FPGA PIN DESCRIPTION LENGTH MM VO BANK BRK6110 EVB1005 PROPERTIES Connector Pin FPGA Pin Description Length mm BRK6110 2 1 em DGND JPIA 1 2 2 e 3 3VDD 2 2 Vbatt VBATT 2 4 e 3 3VDD 4 2 5 JTAG_TCK JP3 6 JP2 6 EEG 3 3 VDD 6 2 7 JTAG_TMS JP3 4 www opalkelly com 27 XEM7350 User s Manual 28 You can hide or show the additional information associated with each signal by clicking on the icon at the top left Toggle Filters Use these filters to limit the visible pin listing to
22. inary operating mode and enabling the fan at all times You may optionally configure a proportional control whereby the PWM output is proportional to the measured temperature of the FPGA die Name Type Description FMC1 VADJ VOLTAGE Vany output voltage specified 10 s of mV For example 330 would set Vans 3 3v DEFAULT 0 FMC1 VADJ ENABLE INT32 Vany output enable O disable 1 enable DEAFULT 0 20 www opalkelly com XEM7350 User s Manual Name Type Description FMC1 VADJ MODE INT32 Vans setting mode 0 Disabled 1 IPMI setting only If a valid IPMI EEPROM is not found is disabled 2 IPMI with fallback If a valid IPMI EEPROM is not found is set according to FMC1 VADJ VOLTAGE 3 IPMI ignore IPMI settings are ignored and Vans is set accord ing to FMC1 VADJ VOLTAGE DEFAULT 2 FMC1 CONTROL INT32 Write only register that controls FMC1 signals during runtime 0 TRST L DEFAULT 0x00000001 FMC1 STATUS INT32 Read only register that contains the FMC1 signal status during runtime 0 PRSNT 2 1 CLKDIR 2 PG M2C 3 POK 3P3 4 VADJ 6 5 GA 0 1 XEM7350 FAN MODE 0 Binary mode 1 Temperature slope mode DEFAULT 0 XEM7350 FAN ENABLE INT32 In binary mode O disable 1 enable DEFAULT 1 XEM7350 FAN TEMP THRESHOLD In temperature slope mode the number here represents the lower threshold in degrees Celsius for temperature dependent operation At THRESH
23. ing for these pins to power the Shuttle TX1 from the FMC peripheral SuperSpeed USB 3 0 Interface The XEM7350 uses a Cypress FX3 USB microcontroller to make the XEM a USB 3 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peripheral on millions of PCs More importantly FPGA downloads to the XEM happen quickly virtual instruments under FrontPanel update quickly and data transfers are blazingly fast On board Peripherals The XEM7350 is designed to compactly support a large number of applications with a small num ber of on board peripherals These peripherals are listed below Low Jitter Crystal Oscillators A fixed frequency 200 MHz low jitter oscillator is included on board and outputs LVDS to the FPGA The Kintex 7 FPGA can produce a wide range of clock frequencies using the on chip DCM and PLL capabilities A second 100 MHz oscillator is available to the transceiver portions of the FPGA as a reference 512 MByte Word Wide DDR3 Synchronous DRAM The XEM also includes a 512 MiByte DDR3 SDRAM with a full 16 bit word wide interface to the FPGA This SDRAM is attached exclusively to the FPGA and does not share any pins with the expansion connector The maximum clock rate of the SDRAM is 800 MHz With the 1 speed grade of the Kintex 7 the maximum clock rate is 800 MHz 400 MHz for the K70T for a sup ported peak memory bandwidth of 25 6 Gb s 12 8 Gb s for the K70T www opalkelly com 7 XEM7
24. n be displayed in the FrontPanel GUI in real time Name Win Step votas vorme o feor sow www opalkelly com 19 XEM7350 User s Manual Name Min Max Stp 3 3 Voltage VOLTAGE O 3 5 305 18 CURRENT o 2 0 Volage voras o ss 05 18 wv 1 8 Voltage 1 5 Voltage 1 2 Voltage 305 18 uV 305 18 uV 305 18 3 815 mA FMC Voltage 305 18 uV FMC 12v Voltage 1 642 mV FMC Vadj Current 3 815 mA Board Temp 1 0 0625 Board Temp 2 0 0625 FPGA Temp 0 0625 Device Settings The XEM7350 supports the FrontPanel Device Settings in the table below accessible from the FrontPanel Application as well as the Device Settings API O _ O 1 0 Current CURRENT 0 FMC Device Settings The XEM7350 has a single FMC port which is configured using the FMC1 settings These set tings are used to control FMC VapJ behavior as well as control and query FMC connector signals FMC1 CONTROL and FMC1 STATUS are volatile device settings that are never stored to nor retrieved from non volatile storage on the device Instead they control and query signals on the connector in real time Fan Control Device Settings You may optionally connect a fan to JP1 Molex 53398 0271 This connector drives 3 PWM signal to the fan according to the Device Settings For most applications we recommend b
25. particular subsets of signals you are interested in Search You can search the pin list using the search entry at the top right Click on the magnifying glass drop down to adjust the function of the search to one of Highlight Highlights search results only Hide Matching Hides rows where search matches are found Show Only Matching Shows only rows where a search match is found Export PDF CSV Constraints Files The export button near the search entry allows you to export the pin list in several formats PDFs can be viewed or printed CSV can be loaded into a spreadsheet application or manipulated with scripts Constraints files can be used as inputs to Xilinx and Altera synthesis and mapping tools The constraints files include additional mapping information for other peripherals on the module such as memory clock oscillators and LEDs Peripherals A Pins Peripheral is a project definition where you can enter your top level HDL design nets to have Pins generate a complete constraint file for you When you create a Peripheral you will select a target integration module The Peripheral is paired to this module so that the design parameters match the features and expansion capabili ties of the module L38P 0 25 099 0 P2B 63 SDATA pix sdata IOSTANDARD LVCMOS33 L37P GCLK13 0 20 996 0 P2B 64 VCMOS33 L38N_VREF_O 22 706 0 P2B 65 kanar ER 5933 L37N_GCLK12_0 20 055 0 P2B 66 533 L51P_
26. r to accommodate mounting within an enclosure The XEM7350 has a single high pin count HPC FMC connector providing access to over 170 I O 8 multi gigabit transceivers and electrically programmable adjustable voltage per the VITA 57 standard www opalkelly com 5 XEM7350 User s Manual Functional Block Diagram System Flash FPGA Flash DDR3 SDRAM 16 MiB 16 MiB 4 Gb 512 MB Kintex 7 FPGA lt gt 4 LEDs ost Interface Bus XC7K70T 1FBG676C or 200 MHz ___ y XC7K160T 1FFG676C ___ 100 MHz Clock LVDS LVDS MGT Reference 1701 0 8 Multi Gb Transceivers FMC VITA 57 Expansion Connector FPGA The XEM7350 is offered in three variants These variants are identical except for the FPGA pro vided The table below lists some of the differences between the two devices Please consult the Xilinx documentation for a more thorough comparison Feature XEW7350 LXTOT KEMT7360 Lx160T XEM7350 LX410T ClockManagementTies Power Supply The XEM7350 is designed to be operated from a single 5 volt power source supplied through the DC power jack on the device This provides power for the several high efficiency switching regu lators on board to provide multiple DC voltages for various components on the device as well as an adjustable supply for the FMC peripheral DC Power Connector The DC power connector on the XEM7350 is part number PJ 102AH from CUI Inc It is a stan dard c
27. sceiver Core ADJv FO FMC VADJ FMC Vadj Power Budget The table below can help you determine your power budget for each supply rail on the XEM7350 All values are highly dependent on the application speed usage and so on Entries we have made are based on typical values presented in component datasheets or approximations based on Xilinx power estimator results Shaded boxes represent unconnected rails to a particular component Empty boxes represent data that the user must provide based on power estimates The user may also need to adjust parameters we have already estimated such as FPGA Vcco values where appropriate All values are shown in milliwatts mW Note that this table does not include the two supplies dedicated to the GTX transceivers These are independent and can be computed separately for power budget based on their assigned function 12 www opalkelly com XEM7350 User s Manual componen tov zov 5v ow x de o o FPGA mf am FPGAVccux ds FPGAVecuno FPGA Vecos DR est zs T FPGA Veco USB Pea L T j TT j j J Example XEM7350 K160T FPGA Power Consumption XPower Estimator version 14 3 was used to compute the following power estimates for the VccINT supply These are simply estimates your design requirements may vary considerably The num bers below indicate approximately 80
28. t of preventing an FPGA configuration from being loaded at power on This func tionality may also be accomplished from the API by setting an empty okTFPGAResetProfile using the API SetFPGABootResetProfile See the FrontPanel API Reference for details Clock Oscillator A fixed frequency 200 MHz low jitter oscillator is included on board and outputs LVDS to the FPGA on bank 34 The Kintex 7 FPGA can produce a wide range of clock frequencies using the on chip DCM and PLL capabilities 200 MHz Pin FPGA Pin LVbS Lvbs A second 100 MHz oscillator is available to the transceiver portions of the FPGA as a reference 100 Pin FPGAPin 08 Lvos FPGA Flash The SPI Flash attached to the FPGA is a Numonyx N25Q128A11B1240E or equivalent It pro vides non volatile storage for use by the FPGA It may not be used for FPGA configuration stor age The System Fash is used to store FPGA boot configurations The Flash FPGA pin mappings are shown in the table below Flash Pin pg NZ Da2 IW Das HOLD www opalkelly com 15 XEM7350 User s Manual LEDs JTAG There are four LEDs on the XEM7350 in addition to the power LED Each is wired directly to the FPGA according to the pin mapping tables at the end of this document The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA on Bank 13 with a bank I O voltage of 3 3v To turn ON an LE
29. to help you equalize lengths in your final application Due to space constraints some pairs are better matched than others Reference Voltage Pins VREF The Xilinx Kintex 7 supports both internal and externally applied input voltage thresholds for some input signal standards The XEM7350 supports these Vrer applications for banks 12 15 16 and 32 Please see the Xilinx Kintex 7 documentation for more details In summary For banks 15 and 16 the four VREF pins are routed to the FMC connector pin VREF A 2 at location H1 Internal may also be used For bank 12 internal VREF may be used Vrer pins are also available on the FMC connector pins HA18_N J19 and 22 J22 if external is required Doing so prevents the use of HA18_N and HA22_N for I O www opalkelly com 23 XEM7350 User s Manual For bank 32 internal may be used pins are also available on the FMC connector pin VREF B M2C K1 For external Vrer you must install 0 Q resistors 0402 dimension at R105 and R106 Doing so prevents the use of HB01_N J25 for I O Gigabit Transceivers Access to eight high speed serial transceiver pairs 8 Rx and 8 Tx corresponding to GTX tiles 115 and 116 on the FPGA are available on the FMC expansion connector MGTREFCLKO of tile 115 and MGTREFCLKO of tile 116 are also routed to FMC MGTREFCLK1 of tile 115 is connected to a low jitter 100 MHz LVDS oscillator AC Coupling 0 1uF AC coupling c
30. ts to the same are claimed Revision History Date Descrptin 20140423 Initial release 20140924 Fixed location reference for R48 Contents Introducing the XEM7350 5 POBUOOQDPIDU upa ed dere etat 5 Functional Block 6 eee one 6 POWEr SUDO cisci qup RA ae 6 DC Power Connect rf casas s T 6 Powering USB uu Se ko ates 7 Powering via the FMC Connector T SuperSpeed USB 3 0 Interface 7 On board T Low Jitter Crystal Oscillators T 512 MByte Word Wide DDR3 Synchronous DRAM 7 FPGA Flash 16 MiB Serial Flash Memory 8 System Flash 16 MiB Serial Flash Memory 8 LEDS asa cranar A I maaa pumapa 8 FPGA Fan Controller 8 Device Senso 52953 dante ios Da ace s da 8 FMC Expansion 8 FrontPanel Support 8 Programmer s Interface 9 Applying the XEM7350 11 Powering the dni acid nre kiida 11 Power B dget 2 e gated cate om s Spoke teite ti 12 Example XEM7350 K160T FPGA Power Consumption 13 Supply Heat Dissipation IMPORTANT
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