HMC987lP5E - Analog Devices
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1. For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com L o z O E m as Q m lt O l O I o z O zm m am pes Q e NC SITE nmcos7z psE MICROWAVE CORPORATION vo3 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz EARTH FRIENDLY Serial Port Write Operation Table 7 SP Open Mode Write Timing Characteristics Parameter Conditions Min Typ Max Units ty SDI setup time 3 ns t2 SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 ns t5 SCLK 9 Rising Edge to SEN Rising Edge 10 ns Serial port Clock Speed DC 50 MHz tg SEN to SCLK Recovery Time 10 ns A typical WRITE cycle is shown in Figure 38 a The Master host places 9 bit data d8 d0 MSB first on SDI on the first 9 falling edges of SCLK b The slave shifts in data on SDI on the first 9 rising edges of SCLK c Master places 4 bit register address to be written to r3 r0 MSB first on the next 4 falling edges of SCLK 10 13 d Slave shifts the register address bits on the next 4 rising edges of SCLK 10 13 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 14 16 The chip address is fixed at 001 f Slave shifts the2. I o z O zm m as ES O m NC O c Hittite MICROWAVE CORPORATION 03 1112 RoHS v EARTH FRIENDLY Figure 19 Harmonic Performance Single Ended Input amp Output 191 POWER dBm 100 1000 10000 FREQUENCY MHz Figure 21 S Parameters S12 11 30 40 50 60 70 S12 dB 80 90 5 H Differential 100 110 0 2000 4000 6000 8000 10000 FREQUENCY MHz 10 Not corrected for board cable loss HMC987LP5E LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz Figure 20 S Parameters 11 11 0 2000 4000 6000 8000 10000 FREQUENCY MHz Figure 22 S Parameters S22 11 0 10 B 15 S22 d 20 25 30 f 0 2000 4000 6000 8000 10000 FREQUENCY MHz 11 Effects of the customer evaluation board are not corrected Improvements in S11 and S22 are possible under different evaluation board configurations For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com r Hittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v EARTH FRIENDLY LOW NOISE 1 9 FANOUT BUFFER DC 8GHz Table 2 Pin Descriptions Pin Number Function Description 1 VCCHF Powe
3. RoHS v EARTH FRIENDLY Table 3 Absolute Maximum Ratings Parameter Rating Max Vdc to paddle on supply pins 1 9 16 25 0 3 V to 4 V Max RF Power CLKP CLKN 15 dBm single ended CLKP CLKN 0 3 V to 3 6 V LVPECL Min Output Load Resistor 100 Ohms to GND LVPECL Output Load Current 40 mA leg Digital Load 1 kQ min Digital Input Voltage Range 0 3 to 3 6 V Thermal Resistance junction to ground paddle 25 C W Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 125 C Maximum Junction Temperature 125 C Reflow Soldering Peak Temperature 260 C Time at Peak Temperature 40 sec ESD Sensitivity HBM Class 1B HMC987LP5E LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC987LP5
4. 0 Toggle XOR with RFBUFEN pin the internal RF Buffer on off 8 5 4 0 Reserved 0 Table 13 Reg04h Gain Select Bit Name Width Default Description 0 Disabled 1 9 dBm single ended 2 6 dBm single ended 3 3 dBm single ended 4 0 dBm single ended gt 4 3 dBm single ended 2 0 RF Buffer Gain 3 7 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EXE nmcos7z psE MICROWAVE CORPORATION v03 1112 RoHS LOW NOISE 1 9 FANOUT BUFFER E DC 8 GHz Table 14 Reg05h Biases Bit Name Width Default Description 1 0 Reserved 2 2 Reserved 2 3 2 Reserved 2 2 Reserved 2 5 4 Reserved 2 3 Reserved 3 8 6 Reserved 3 0 Reserved 0 i o z O D m am m eA e NC O 1 O For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com
5. Figure 11 Fundamental Output Power vs Frequency amp Termination at 27 C 61 120 Ohms 200 Ohms 300 Ohms fi OUTPUT POWER dBm 100 1000 10000 OUTPUT FREQUENCY MHz HMC987LP5E LOW NOISE 1 9 FANOUT BUFFER DC 8GHz Figure 8 RF Output Power Control OUTPUT POWER dBm 100 1000 10000 FREQUENCY MHz Figure 10 Fundamental Output Power vs Frequency amp Supply Voltage at 27 C 61 OUTPUT POWER dBm 100 1000 10000 OUTPUT FREQUENCY MHz Figure 12 Signal Swing vs Frequency 7 1 6 Corrected For Evaluation Board Loss Observed and Not Corrected i For Evaluation Board Loss SIGNAL SWING Vppd 0 1000 2000 3000 4000 5000 6000 7000 8000 FREQUENCY MHz 6 Measured single ended Corrected for trace loss 200 Q DC termination 3 3 V 6 dBm single ended input HMC987LP5E AC coupled to 50 O instrument 7 Input signal power 6 dBm 120 O leg DC termination AC coupled via 50 pF to 26 GHz Oscilloscope 50 Ohm leg termination For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com eariittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY Figure 13 Phase Noise Performance at 2 GHz Differential Drive 9 Figure 14 Phase N
6. chip address bits on the 3 rising edges of SCLK 14 16 g Master asserts SEN after the 16th rising edge of SCLK h Slave registers the SDI data on the rising edge of SEN 1 2 7 8 9 10 SCK Tula t2 B CIO CI E CICICEE SEN t T L Figure 38 SPI Timing Diagram Write Operation Serial Port Read Operation In order ensure correct read operation a pull down resistor to ground 1 2kOhm is recommended on the Serial Data Out line from the part A typical READ cycle is shown in Figure 39 In general SDO line is always active during the WRITE cycle SDO will contain the data from the addresses pointed to by RegOOh If RegOOh is not changed the same data will always be present on the SDO If it is desired to READ from a specific address it is necessary in the first SPI cycle to write the desired address to RegOOh then in the next SPI cycle the desired data will be available on the SDO For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY An example of the two cycle procedure to read from any random address is as follows The Master host on the first 9 falling edges of SCLK places 9 bit data d
7. 00 300 Base current under external Input Bias Current DC bias Internal termination 165 UA open Logic Inputs Switching Threshold Vsw VIH VIL within 50 mV of Vsw 38 47 54 VDD LVPECL DC Output Characteristics Output Voltage High Level 3 3 V 2 25 VDD 1 2 VDD 1 0 VDD 0 8 V Ouput Voltage Common Mode 3 3 V 1 82 VDD 1 7 VDD 1 5 VDD 1 3 V Output Voltage Low Level 3 3 V 1 42 VDD 2 1 VDD 1 9 VDD 1 7 V Output Voltage Single Ended 800 mVpp AC Performance Input Output Frequency 1 gt 400 Vpp single ended DC 8000 MHz 3 dB Bandwidth 4000 MHz Output Rise Fall Time 20 to 80 65 ps Typical Channel Skew E s 0 1 5 3 1 ps Small Signal Gain S21 1000 MHz 26 qB 4000 MHz 15 qB Input P1dB 1000 MHz 20 dBm 4000 MHz 10 dBm Saturated Power in fundamental tone Single Ended 1000 MHz 2 5 dBm 4000 MHz 0 5 dBm Output Voltage Swing Vppd into 100 Q 700 MHz 1 5 1 6 1 7 2000 MHz 1 2 1 3 1 4 1 For frequencies lt 700 MHz square wave signals should be used to maintain high quality phase noise performance For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com Phone 978 250 3343 Fax 978 250 3373 E Hittite MICROWAVE CORPORATION v03 1112 RoHS v EARTH FRIENDLY Table 1 Electrical Specifications Continued HMC987LP5E LOW NOISE 1 9 F
8. 234 mA SPI Interface Vil 14 V Vih 2 0 V Vol 0 4 V Voh 2 8 V For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com r Hittite MICROWAVE CORPORATION v03 1112 RoHS v m EARTH FRIENDLY TYPICAL PERFORMANCE CHARACTERISTICS HMC987LP5E LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz Unless otherwise specified T 27 C Regulated VDD 3 3 V 2 GHz 6 dBm in AC coupled single ended input and output 120 O leg DC termination AC coupled into 50 Q measuring load Figure 1 LVPECL Output vs Frequency 1 04 4 GHz oure 4 GHz OUTN 2 GHz OUTP 03 EM OUTPUT VOLTAGE V o o N k o _ N 800 600 400 200 0 200 400 600 800 TIME picoseconds Figure 3 Current Consumption vs Num of Enabled Buffers amp Load Resistors 2 500 400 300 a 200 CURRENT mA 100 1 2 3 4 5 5 6 Eg 8 RF MinRF Max NUMBER OF OUTPUTS SUCCESSIVELY TURNED ON Figure 5 Fundamental Output Power vs Input Power 13 5 T T 400 MHz OUTPUT POWER dBm 30 24 18 12 6 0 6 INPUT POWER dBm Figure 2 LVPECL Output vs Frequency 11 0 6 o o M AMPLITUDE V differential E M 0 4 0 6 0 8 0 20 40 60 80 100 120 TIME ps Figure 4 Skew of LVPECL Outp
9. 8 d0 MSB first on SDI as shown in Figure 39 d8 dO should be set to zero d3 dO address of the register to be READ on the next cycle a The slave shifts in data on SDI on the first 9 rising edges of SCLK b Master places 4 bit register address r3 r0 the address the WRITE ADDRESS register MSB first on the next 4 falling edges of SCLK 10 13 r3 r0 0000 c Slave shifts the register bits on the next 4 rising edges of SCLK 10 13 d Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 14 16 The chip address is fixed at 001 e Slave shifts the chip address bits on the next 3 rising edges of SCLK 14 16 f Master asserts SEN after the 16th rising edge of SCLK g Slaveregisters the SDI data on the rising edge of SEN h Master clears SEN to complete the address transfer of the two part READ cycle i If we do not wish to write data to the chip at the same time as we do the second cycle then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle Master places the same SDI data as the previous cycle on the next 16 falling edges of SCLK k Slave shifts the SDI data on the next 16 rising edges of SCLK I Slave places the desired data i e data from address in RegOOh 3 0 on SDO on the next 16 rising edges of SCLK m Master asserts SEN after the 16th rising edge of SCLK to complete the cycle Note that if the chip a
10. ANALOG Mittite DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK i gt 0 z O zm m LUC Q m NC c Hittite MICROWAVE CORPORATION 03 1112 RoHSv EARTH FRIENDLY Typical Applications The is suitable for SONET Fibre Channel GigE Clock Distribution ADC DAC Clock Distribution Low Skew and Jitter Clock or Data Fanout Wireless Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single Ended to Differential Conversion Functional Diagram L cs an a 5 n z a z lt z m E o eo la L 2 a Oo E o x o o o gt g k G o L rn wo s mM be M N N N N N vecHF 1N N N 24 OUTN3 cLkP 2 gt 23 OUTP3 CLKN 3 gt 22 OUTN4 spi 4 21 OUTP4 spo 5 gt 20 OUTPS PMODE SEL 6 19 OUTNS 18 OUTP6 OUTN6 RFOUTP 7 RFOUTN 8 amp e veces 167 PACKAGE BASE GND vccRF 9N SCLK 10 SEN 11 OUTP8 12 OUTN8 13 OUTP7 14 OUTN7 15 HMC987LP5E LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz Featur
11. ANOUT BUFFER DC 8 GHz Parameter Conditions Min Typ Max Units 4000 MHz 14 1 2 1 8 V Harmonics Fo 2 dBm 2Fo 25 dBc 3Fo 8 dBc 4Fo 28 dBc 5Fo 12 dBc SSB Phase Noise at 100 Hz Offset 622 08 MHz Carrier Frequency 147 dBc Hz 1750 MHz Carrier Frequency 147 dBc Hz 4000 MHz Carrier Frequency 147 dBc Hz SSB Phase Noise Floor 2 100 MHz Carrier Frequency 167 dBc Hz 622 08 MHz Carrier Frequency 167 dBc Hz 1750 MHz Carrier Frequency 166 dBc Hz 2000 MHz Carrier Frequency 166 dBc Hz 4000 MHz Carrier Frequency 163 dBc Hz 4200 MHz Carrier Frequency 162 dBc Hz Floor Jitter Density 622 08 MHz Carrier Frequency 1 8 asec JHz 1750 MHz Carrier Frequency 0 7 asec Hz 4000 MHz Carrier Frequency 0 5 asec JHz Integrated RMS Jitter 100 Hz to 100 MHz 17 fs rms 12 kHz to 20 MHz 8 fs rms 622 08 MHz Carrier Frequency 20 kHz to 80 MHz 17 fs rms 50 kHz to 80 MHz 17 fs rms 4 MHz to 80 MHz 16 fs rms 100 Hz to 100 MHz 7 fs rms 12 kHz to 20 MHz 3 fs rms 1750 MHz Carrier Frequency 20 kHz to 80 MHz 6 fs rms 50 kHz to 80 MHz 6 fs rms 4 MHz to 80 MHz 6 fs rms 100 Hz to 100 MHz 4 fs rms 12 kHz to 20 MHz 2 fs rms 4000 MHz Carrier Frequency 20 kHz to 80 MHz 4 fs rms 50 kHz to 80 MHz 4 fs rms 4 MHz to 80 MHz 4 fs rms Output Return Loss 500 MHz to 4 GHz 16 12 8 dB 2 CML buffer has similar phase noise characteristics at m
12. Application Support Phone 978 250 3343 or apps hittite com earittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY RF Output Stage The RF output buffer is a CML output stage with 50 O impedance single ended and adjustable power In parallel mode the PMODE SEL pin 1 it is at max gain 3 dBm single ended whereas under SPI control the gain can be lowered in 3 dB steps down to 9 dBm single ended See Reg04 h for more information 3 3V 50Q RFOUTP RFOUTN QD RF Buffer Gain A Reg04h 2 0 Figure 37 Output Stage Serial Port Interface SPI Control The HMC987Lp5E can be controlled via SPI or parallel port control for more information on parallel control see Parallel Port Control SPI control offers more flexibility External pin PMODE SEL 1 configures the for parallel port operation while PMODE SEL 0 will enable the SPI control of The SPI control is required in order to re configure the input bias network from its default state RegO3h to adjust the output power control on the RF CML buffer and to individually enable arbitrary LVPECL outputs Operational Modes Serial Port Interface features a Compatibility with general serial port protocols that use a shift and strobe approach to communication b Compatible with HMC multi Chip solutions useful to address multiple chips of various types from a single serial port bus
13. E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY Outline Drawing IOP VIEW BOTTOM VIEW 012 938 201 5 10 007 EIL 016 0 40 REF 7495 490 7 77 008 0 20 MIN 32 25 S LT L LU U 70 1 24 mes F 4 mal PIN 1 uo 3 16 LOT NUMBER 150 3 80 38 s o square 039 1 00 031 585 LR 002 0 05 0 00 000 H HH HHHH SEATING PLANE LCS 003 0 08 C om NOTES 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY 3 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN 4 DIMENSIONS ARE IN INCHES MILLIMETERS 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD BURR LENGTH SHALL BE 0 15 mm MAX PAD BURR HEIGHT SHALL BE 0 05 mm MAX 7 PACKAGE WARP SHALL NOT EXCEED 0 05 mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Table 4 Package Information Part Number Package Body Material Lead Finish MSL Rating Package Marking DI RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 2 Har 1 4 Digit lot number XXXX 2 Max peak reflow temperature of 260 C For price delivery and to place orders Hittite Micr
14. N 5s TE HU lt Po AAE Tu i m 2n As Eu o n UT 8d BB l b l l il 88 z S g ek 48 z er sg a L j TOUT gees 8 88 e t s s 8 8 8 88 8 B amp o Tae I sigg sE s EZ El f j Eco EI l z Bok n RR Bese Bs jl Bok BSE B E 8 lL E 1 5 IO KE aS PG sa sQ KIO RIO je cg 3 P 8 Ez amp ege 5 o A E E For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com i gt 0 z O zm m am pes Q e NC SITE nmcos7z psE MICROWAVE CORPORATION vo3 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz EARTH FRIENDLY Theory of Operation Parallel Port Control The various outputs of the can be enabled disabled by using parallel pin control or via the SPI In parallel mode PMODE SEL 1 the SPI input pins SCLK SKI SEN are re interpreted as a 3 bit control bus and enable the LVPECL drivers according to the following truth table SCLK SDI SEN 000 OUT2 001 OUT2 OUT7 010 OUT2 OUT7 OUT4 011 OUT2 OUT7 OUT4 OUT6 100 OUT2 OUT7 OUT4 OUT6 OUT5 101 OUT2 OUT7 OUT4 OUT6 OUT5 OUT3 110 OUT2 OUT7 OUT4 OUT6 OUT5 OUT3 OUT8 111 OUT2 OUT7 OU
15. T4 OUT6 OUT5 OUT3 OUTS OUT1 Under SPI control PMODE SEL 0 see section Register Map for the register map and SPI protocol details there is slightly more flexibility in that any combination of buffers can be enabled or disabled via the individual buffer enable bits in RegO2h The part features switches on both the input and output signals so that when the part is disabled via either the CEN pin or the SPI control bit RegO1h 0 the power down current drops to lt 2 pA regardless of the IO termination scheme Input Stage The input stage Figure 26 is flexible It can be driven single ended or differential with LVPECL LVDS or CML signals If driven single ended a large AC coupling cap to ground should be used on the undriven input The input impedance is selectable via RegO3h 3 between 50 Q or 150 Q single ended 100 Q or 300 Q differential The DC bias level of 2 0 V can be generated internally by programming Reg03 1 1 default configuration supplied externally or generated via an LVPECL termination network inside the part Chip Enable The HMC987 has a chip enable feature CEN which can be used to power down or deactivate the LVPECL and RF outputs This can be done by either hardware pin 31 or a SPI command Reg01 For a hardware selection a logic O applied to CEN will power down the HMC987 however SPI commands can still be written which will be recognized upon when a logic 1 is applied to CEN Note
16. aximum output power level For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com Phone 978 250 3343 Fax 978 250 3373 o Z O D m LC A m lt O O l EXE nmcos7z psE MICROWAVE CORPORATION vo3 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY Table 1 Electrical Specifications Continued Parameter Conditions Min Typ Max Units H Isolation gt In to Out Chip Disabled 47 dB dp Off isolation Relative to Power of neighboring driven port 700 MHz 60 48 dB Z 4000 MHz 50 32 dB e Output to Output Isolation with 500 MHz Aggressor Signal Injected into Output Port To Locally paired output buffer 25 dB To other buffers 45 dB en RF Output Buffer 5 3 dB Bandwidth 5000 MHz is oo Power vs Temperature at Single Ended 3 32 dBm O Power Control Range 3 dB steps Single Ended 9 3 dBm Delay Relative to LVPECL Output 140 ps x Power Supply Rejection z FM Phase Pushing 0 8 ps V 1 AM Rejection 7 dB Q Current Consumption 3 3 V Unloaded Outputs Chip Disabled 1 UA 1 Output 60 mA 2 Outputs 71 mA 3 Outputs 97 mA 4 Outputs 108 mA 5 Outputs 134 mA 6 Outputs 144 mA 7 Outputs 170 mA 8 Outputs 180 mA 8 RF Buffer Min to Max Power 198
17. ddress bits are unrecognized a2 a0 the slave will tri state the SDO output to prevent a possible bus contention issue For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com o Z O E m as A ea lt O l O CUTIRI HwucsszLPsE MICROWAVE CORPORATION v03 4112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz EARTH FRIENDLY Table 8 SP Open Mode Read Timing Characteristics Parameter Conditions Min Typ Max Units ty SDI setup time 3 ns t2 SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 ns t5 SCLK Rising Edge to SDO time 8 2 0 2ns pF ns t6 SEN to SCLK Recovery Time 10 ns t7 SCLK 16 Rising Edge to SEN Rising Edge 10 ns Figure 39 SPI Diagram Read Operation 2 Cycles FIRST CYCLE 5 6 9 10 13 14 15 16 PAT ty t2 a te uP eles T fis o z O zm m as pes Q e NC O 1 O READ Address Register Address 00000 Chip Address 001 an SDO E EEE E TRI STATE SEN SECOND CYCLE 5 6 9 10 Wyuuvuut so u a To s je 5 ej jeljep GG G SEN For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On
18. es Ultra Low Noise Floor 166 dBc Hz 2 GHz Wideband DC 8 GHz Operating Frequency Flexible Input Interface LVPECL LVDS CML CMOS Compatible AC or DC Coupling On Chip Termination 50 or 150 100 300 Q Diff Multiple Output Drivers Up to 8 Differential or 16 Single Ended LVPECL Outputs 800 mVpp into 50 O Single Ended 3 dBm Fo One Adjustable Power CML RF Output 9 to 3 dBm Single Ended Serial or Parallel Control Hardware Chip Enable Power Down Current lt 1 uA 32 Lead 5x5 mm SMT Package 25 mm General Description The 1 to 9 fanout buffer is designed for low noise clock distribution It is intended to generate relatively square wave outputs with rise fall times lt 100 ps The low skew and jitter outputs of the HMC987LP5E combined with its fast rise fall times leads to controllable low noise switching of downstream circuits such as mixers ADCs DACs or SERDES devices The noise floor is particularly important in these applications when the clock network bandwidth is wide enough to allow square wave switching Driven at 2 GHz outputs of the HMC987LP5E have a noise floor of 166 dBc Hz corresponding to a jitter density of 0 6 asec rtHz or 50 fs over an 8 GHz bandwidth The input stage can be driven single ended or differentially in a variety of signal formats CML LVDS LVPECL or CMOS AC or DC coupled The input stage also features adjustable input impedance It has 8 LVPECL outputs and 1 CML output with adjus
19. ic Evaluation Software For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com tJ Hittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz Evaluation PCB Schematic EB T2 JE EL 5 i Z S HAN TIENE z d 25 ii O IM PE B elt E H T ag S ME gr S ae 1 Sa y E i am En m I l B OQ S O o 8 g BS 3
20. ions the user often has the luxury of using AC coupling unlike in many data path situations Figure 36 shows a simplified interface schematic between an LVPECL output and input stage where various options and trade offs for the termination components are provided in Table 6 The Hittite evaluation board has a great deal of flexibility in how the I Os are configured and allows the configuration in Figure 34 among many others js o z O zm m am pes Q e NC OUTP Rs HMC987LPSE Rs OUTN ac Figure 36 Recommended Interface Diagram Table 6 Interface Values Rs Used to increase Ro to match to 50 Q environment already has 10 Q internally 00 Hittite EVB Largest signal swing lowest common mode shift 100 Better S22 RI DC current termination for LVPECL output stage 1200 Hittite EVB default Standard LVPECL termination voltages 2000 Reduced current no performance degradation 3000 Further reduced current lower output power but flatter frequency response OPEN If using internal DC termination network at the Rx Cac AC coupling cap BIG CAP Hittite EVB default If using AC coupling SHORT If using internal DC termination network at the Rx For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com
21. line at www hittite com Application Support Phone 978 250 3343 or apps hittite com E Hittite HMC987LP5E MICROWAVE CORPORATION v03 1112 Honey LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz EARTH FRIENDLY Register Map Table 9 Reg00h ID and Read Register Bit Name Width Default Description 3 0 Read Control 4 Enter Register Address to be Read From 4 Soft Reset 1 0 1 Reset Registers are set to the Default Condition 8 0 Chip ID 9 197hex Register 00 contains the Chip ID 197hex Table 10 Reg01h Master Enable Bit Name Width Default Description 0 Master Chip Enable 1 1 12 Active O Power Down Table 11 Reg02h Individual Enables o lt O D m LC A m lt l Bit Name Width Default Description 0 eni 1 1 Enable Buffer 1 1 en2 1 1 Enable Buffer 2 2 en3 1 1 Enable Buffer 3 3 en4 1 1 Enable Buffer 4 4 en5 1 1 Enable Buffer 5 5 en6 1 1 Enable Buffer 6 6 en 1 1 Enable Buffer 7 7 en8 1 1 Enable Buffer 8 Table 12 Reg03h Rx Buffer Configuration Bit Name Width Default Description 0 1 0 Reserved 0 1 DC Internal 1 1 Use internal DC bias string 2 DC LVPECL 1 0 Use internal LVPECL Rx termination Input termination select 3 Zin 50 1 1 1 50 O single ended 100 Q differential 0 150 Q single ended 300 Q differential 4 RFBUF XOR 1
22. m Application Support Phone 978 250 3343 or apps hittite com SITE HwcsszLPsE MICROWAVE CORPORATION vo3 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz EARTH FRIENDLY CLKP 2 CLKP u 500 Te i 50Q or 1500 500 eem lt CLKN 306 CLKN 500 or 1500 O 3 3 2 HMC987LP5E m HMC987LP5E as Figure 29 DC Coupled LVPECL Interface Figure 30 AC Coupled Differential CML LVPECL LVDS CMOS Interface e e NC O CLKP O Q net 500 or 1500 O e CLKN 500 or 1500 3 HMC987LP5E Figure 31 AC Coupled Single Ended CML LVPECL LVDS CMOS Interface LVPECL Output Stage The LVPECL output driver produces up to 1 6 Vppd swing into 100 O differencial loads LVPECL drivers are terminated with off chip resistors that provide the DC current through the emitter follower output stage The output stage has a switch which disconnects the output driver from the load when not used The switch series resistor significantly improves the output match when driving into 50 O transmission lines The switch series resistor causes a small DC level shift and swing degradation depending on the termination current If unused disabled LVPECL outputs can be left floating terminated or grounded For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Supp
23. oise Floor vs Slew Rate 110 161 120 130 o PHASE NOISE dBc Hz a o 2 PHASE NOI SE dBc Hz ES o Au M t Pin 10 dBm ___ amp Pin 10 dBm 3 4 5 6 7 8 10 10 10 10 10 10 0 2 ri 6 8 m i SLEW RATE V nsec FREQUENCY OFFSET Hz L o z O E D m LC A ea lt O l O Figure 15 Phase Noise Floor Figure 16 Phase Noise Performance with at 1 6 GHz vs Input Power Low Frequency Sinusoidal Inputs 81 156 248 158 250 Z aeo LOO 8 us D 2 162 254 2 2 164 7 956 166 258 168 260 45 Ao 5 0 5 10 0 500 1000 1500 2000 INPUT POWER dBm SINUSOIDAL INPUT FREQUENCY MHz Figure 17 Phase Noise Floor Figure 18 Phase Noise Floor vs at 2 GHz vs VDD and DC Termination Temperature 160 200 Ohm Termination A 1 162 L Frequency 4 2 GHz E 8 164 l aiae I o 166 Frequency 2 GHz 168 Frequency 100 MHz 170 2 7 2 8 2 9 3 3 1 3 2 3 3 3 4 3 5 0 p 29 109 VDD TEMPERATURE Deg C 8 Input power 10 dBm single ended Phase Noise Floor dBc Hz FOM dBc Hz 10log Fout Hz 9 HMC830LP6GE used as signal source Driving 9 dBm differentially For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com
24. ort Phone 978 250 3343 or apps hittite com earittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER E DC 8 GHz 3 3V 3 3V O 100 OUTP enable 3 3V BN f s N OUTN AZ enable O d RegO1h X Figure 32 Output Stage Figures 34 35 36 illustrate common output interface configurations u 3 3V 3 5V 100 2 OUTP li K RL 3 3V 100 I OUTN ii IT E RL HMC987LP5E HMC987LP5E Figure 33 DC Coupled to LVPECL Interface Figure 34 AC coupled to LVDS CML LVPECL CMOS For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com L o z O E D m as A e lt O l O SITE HwcsszLPsE MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY o 3 3V 3 3V o 10 Rs zi OUTP Ne RL 3 3V Y 10 2 OUTN Open Circuit HMC987LPSE Figure 35 DC Coupled to CMOS Interface The user has a number of choices in how they connect LVPECL drivers and receivers and there are great number of resources that deal in detail with this issue As a quick introduction there are compromises between matching performance common mode levels and signal swing For clocking applicat
25. owave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com o Z O E m LC A ea lt l O EXEC nmcos7z psE MICROWAVE CORPORATION v03 1112 RoHS LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY Evaluation PCB J13 J15 J18 J20 J22 J23 324 325 J26 RFOUT N oe 2 Hittite sq 600 00076 00 1 us 329 The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request fis o z O zm m as pes Q e NC Table 5 Evaluation Order Information Item Contents Part Number Evaluation PCB Evaluation PCB EVAL01 HMC987LP5E Evaluation PCB USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable EKITO1 HMC987LP5E CD ROM Contains User Manual Evaluation PCB Schemat
26. r Supply 2 CLKP Differential clock inputs 3 CLKN 4 SDI Serial port data input 5 SDO Serial port data output Parallel mode select If 1 pins SCLK SDI SEN are interpreted as a control word which enables 6 PMODE SEL I Bre different buffers See section Parallel Port Control 7 RFOUTP Differential signal output 8 RFOUTN 9 VCCRF Power supply 10 SCLK Serial port clock 11 SEN Serial port latch enable 12 OUTP8 Differential signal output 13 OUTN8 14 OUTP7 Differential signal output 15 OUTN7 16 VCCB Power supply 17 OUTN6 Differential signal output 18 OUTP6 19 OUTN5 Differential signal output 20 OUTP5 21 OUTP4 Differential signal output 22 OUTN4 23 OUTP3 Differential signal output 24 OUTN3 25 VCCA Power supply 26 OUTN2 Differential signal output 27 OUTP2 28 OUTN1 Differential signal output 29 OUTP1 30 RFBUFEN Active high RF buffer enable The polarity of this control input can be swapped via SPI bit RegO3h 4 31 CEN Hardware chip enable Logic 0 Power Down Logic 1 Active 32 NC No Connect For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com o lt O E m LC A m lt O O l O I o z O zm m as pes Q e NC E Hittite MICROWAVE CORPORATION vo03 1112
27. table swing power level in 3 dB steps Individual output stages may be enabled or disabled for power savings when not required using either hardware control pins or under control of a serial port interface For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com i gt 0 z O zm m am pes Q e X O E Hittite MICROWAVE CORPORATION v03 4112 RoHS v s EARTH FRIENDLY Table 1 Electrical Specifications Unless otherwise specified T 27 C Regulated VDD of 3 3 V 2 GHz 6 dBm in AC coupled single ended input and output 120 O leg DC termination AC coupled into 50 O measuring load Effects of customer eval board Evaluation PCB Schematic are de embedded For convenience all voltages are referenced to GND OV but negative supply references are acceptable HMC987LP5E LOW NOISE 1 9 FANOUT BUFFER DC 8 GHz Parameter Conditions Min Typ Max Units DC Input Characteristics VDD VCCHF VCCA VCCB VCCRF 3 0 3 3 3 6 V Input Common Mode Voltage 1 35 2 VDD 0 2 V Input Swing Single Ended 0 2 2 Vpp Input Capacitance 0 5 pF Input Impedance Single Ended Selectable 50 150 Differential Selectable 1
28. there is no internal pull up or pull down and this pin must be terminated To control CEN by SPI command Reg 01h 0 is set to 1 which is the default mode and enables the outputs When Reg01 0 0 then the outputs are disabled Either a hardware pin 31 or a SPI command will disable the outputs For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC987LP5E MICROWAVE CORPORATION v03 1112 RoHS v LOW NOISE 1 9 FANOUT BUFFER DC 8GHz EARTH FRIENDLY 3 3V Figure 26 Input Stage CLKN Rego03h 1 1 Reg03h 3 1 Q Closed Closed gt Default State Default State Termination Select gt INTERNAL eo DC BIAS 2 0V an 20p 50 Reg03h 2 0 L 0 RegO3h 1 Lr Default State bod LVPECL Q TERMINATION v Figures 27 to Figure 31 illustrate common input interface configurations CLKP CLKP 500 or 1500 Z 1500 VDD_CMOS 500 or 1500 l CLKN l S Rn 3 HMC987LP5E HMC987LP5E Figure 27 DC Coupled CML Interface Figure 28 DC Coupled CMOS Interface For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite co
29. uts Relative to Output Channel 1 41 RELATIVE DELAY psec P1 P2 P3 P4 P5 P6 P7 P8 OUTPUT CHANNEL Figure 6 Evaluation Board LVPECL Output Trace Loss vs Frequency 51 OUTPUT TRACE LOSS dB 100 1000 10000 OUTPUT FREQUENCY MHz 1 2dBm input Uncorrected for board loss Measurement is band limited by the trace bandwidth of 7 GHz 2 Buffers 1 through 8 are successively turned on RF Min RF buffer turned on with minimum gain RF Max RF buffer turned on with maximum gain 3 200 Q Termination Corrected for board loss 4 Characterized at 2 GHz Effects of customer evaluation board skew and loss are embedded 5 The graph shows only output trace distortion For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com o lt O E m LC A m lt O l O I o z O zm m LUC ES O e NC c Hittite MICROWAVE CORPORATION v03 1112 RoHS v EARTH FRIENDLY Figure 7 RF Buffer Fo Output Power vs Frequency amp Temperature Max Gain OUTPUT POWER dBm 100 1000 10000 FREQUENCY MHz Figure 9 Fundamental Output Power vs Frequency amp Temperature 61 OUTPUT POWER dBm 100 1000 10000 OUTPUT FREQUENCY MHz
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