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1. 8 1 3 Referenced Documents nu SENS 10 Table 1 2 Referenced 10 Chapter2 Carrier Board Schematic Guidelines 11 2 1 Gigabit Ethernet 11 2 1 1 Signal Descriptions SUR FE eda Ea an 11 2 1 2 DC 5 11 2 1 3 Schematic Guidelines aae sedata uat tuis 12 usi oaa Rp tein atin 13 2 2 AC 97 Audio HD Audio esses 18 2 2 1 18 2 2 2 Specifications sssssssssseeemmmnnnnnne 18 2 2 3 97 Uoc 18 2 24 Schematic 4 19 2 2 5 22 Al A oce eee ut ep eee MEE 25 2 3 1 5 25 2 3 2 Layout cc mm 26 At 27 2 4 1 Signal Description 27 2 4 2 DC Specifications 4 27 243 MBE SPEC EE 28 2 4 4 Schematic 28 2 4 5 Layout Guidelines eiie tin ttai 30 2 5 POGlEXDISSS Bb 31 2 5 1 Signal Description 31 2 5 2 Schematic GUidellniBS
2. Carrier Board Design Guide Advantech COM Express Carrier Board Design Guide Addendum Notices The copyright on this user manual remains with Advantech Co Ltd No part of this user manual may be transmitted reproduced or changed Other companies product names that may be used herein remain the property of their respective owners The product specifications design and this user s manuals content are subject to change without notice If you have any questions please contact your merchant or our service center for clarification We are not responsible for any losses resulting from using this product no matter what the reason Revision History Version Revision date Date A Descipion July 2006 Initial release July 2007 po e e e April 2009 Change format to Addendum May 2010 O O August 2010 Do Part No 2006001801 Edition 2 1 Printed in Taiwan August 2010 2 Notices Advantech COM Express Carrier Board Design Guide Addendum Table of Contents Table of GOmte ints m 3 Chapter 1 7 1 CONI EXpress 7 8 Table 1 1 Conventions and
3. 26 Figure 2 20 SATA traces length 27 Figure 2 21 IDE Master Slave Handshake Signals Connection 28 Figure 2 22 IDE Master Slave DASP S Signals Connection 28 Figure 2 23 IDE Bus Trace Length on Carrier 29 Figure 2 24 Mbzmecu ei Mem EE 29 Figure 2 25 CF Connections xk Ree 30 Figure 2 26 PCI Express Interconnect Example 32 Figure 2 27 PCI Express Connector Schematic 32 Figure 2 28 Polarity Inversion on TX to RX 33 Figure 2 29 Lane Reversal and Polarity Inversion TX to RX Interconnect 34 Figure 2 30 Trace Length Matching in Each 35 Figure 2 31 Topology 1 COM Express to PCI Express Device Down 36 Figure 2 32 interleaved left and non interleaved pairs right 36 Figure 2 33 Topology 2 and 3 COM Express to Express Card or Docking aaa sta 21 Figure 2 34 38 Figure 2 35 Interrupt Routing
4. 32 2 5 3 Layout Guidelines Drak pm 35 Bh 38 Wal cg n 39 2 7 1 Signal mm 39 2 7 2 Specifications 000 00000000 000000 nenene 40 2 7 3 40 2 7 4 Schematic 40 2 7 5 Layout 44 2 8 Universal Serial Bus 47 2 8 1 Signal DeSCrIpliOTL RR RN ERE 47 2 8 2 Specifications 47 2 8 3 TES 47 2 8 4 Schematic Guidelines 47 2 9 9 Layout 49 29 gnus E 51 2 9 1 51 2 9 2 DC Specifications 1 11000000 000000000 51 2 9 3 Schematic Guidelines 51 2 9 4 Layout 52 Table of Contents Advantech COM Express Carrier Board Design Guide Addendum 2 10 VGA T 53 2 10 1 Signal Description TO n 53 2 10
5. 68 3 1 2 ATX power with Super l O 69 3 1 3 ATX power w o Super 69 3 1 4 AT Power Delivery Block 70 3 1 5 AT Power Working as 71 Chapter 4 PCB Layout Guidelines eese 72 4 1 Nominal Board 72 4 1 1 Four layer board ia uso eate asd tentis 73 Table 4 1 Recommended Four Layer Stack Up Dimensions 73 4 1 2 Six layer board 74 4 2 JAlemalte Stack 0 75 4 3 Differential Impedance Targets for Trace Routing 75 Chapter 5 Mechanical Schematic Guidelines 76 5 1 COM Express Mechanical 2 76 5 2 COM Express Module 77 5 3 COM Express Carrier Board 77 5 4 COM Express Connector PCB Pattern 78 4 Table of Contents Advantech COM Express Carrier Board Design Guide Addendum Figure 2 1 10 100M Ethernet 444222020 4 12 Figure 2 2 Gigabit Ethernet 12 Figu
6. 2 2 5 2 EMI Considerations The signals entering or leaving the analog area must cross the ground split through the beads between digital ground and analog ground No signal can cross the split gap between the ground planes which will cause a ground loop and greatly increase EMI emissions and degrade the analog and digital signal quality 2 2 5 3 HD Audio Layout Guidelines Figure 2 13 and Table 2 6 show the SDIN layout topology Carrier board COM Express T Audio Codec down R1 Figure 2 13 HD Audio SDIN Topology Table 2 6 HD Audio SDIN Routing Trace HD Audio Requirements Trace Series Signal Impedance length Termination Length Resistance Matching 550 5 on 7 stripline 1 33 15 5 on 7 microstrip 0 5 Figure 2 14 and Table 2 7 show the layout topology 1 of AC SDOUT AC SYNC AC BITCLK and AC_RST signals 22 Advantech COM Express Carrier Board Design Guide Addendum Carrier board L3 Audio Codec down R1 L2 2 COM Express 1 I2 L3 Codec R2 Lupe 12 5 Audi rJ L5 6 gt R3 42 Figure 2 14 HD Audio AC_SDOUT AC_SYNC AC_BITCLK AC_RST Topology 1 Table 2 7 HD Audio AC SDOUT AC SYNC AC BITCLK AC_RST Topology 1 Trace HD Audio Requirements Trace Se
7. e The LVDS transmitter timing domain signals have maximum trace length of 10 inches Be sure that the max trace length routed on the carrier board is 7 5 inches Please refer to Advantech layout checklist for detailed info e Clocks must be matched to the associated data signals to within 10 mils e Channel to Channel clock length must be matched to within 10 mils e Minimum spacing between neighboring trace pair is 20 mils e Traces must be ground referenced e When choosing cables it is important to remind that the differential impedance of cable should be 1000 The cable length should be less than 0 5 meter for better signal quality 52 Advantech COM Express Carrier Board Design Guide Addendum 2 10 VGA COM Express Module provides analog display signals There are three signals red green and blue which send color information to a VGA monitor Analog levels between 0 completely dark and 0 7 V maximum brightness on these control lines tell the monitor what intensities of these three primary colors to combine to make the color of a dot or pixel on the monitor s screen 2 10 1 Signal Description Table 2 35 shows COM Express VGA signals Table 2 34 VGA signals description B89 RED Red analog video output signal for CRT monitors designed to drive a 37 5 equivalent load B VGA GRN Green analog video output signals for CRT monitors designed to drive a 37 5 equivalent load 91 B92 VGA BLU Bl
8. 270 330 series damping resistors 54 Advantech COM Express Carrier Board Design Guide Addendum for HSY and VSY should be placed near the D SUB connector Please refer to Advantech layout checklist for detail recommended resistor value The impedance control of VGA is important for VGA signal quality The RGB traces with proper width for 500 impedance should be routed between the 1500 resistor and COM Express connector And the routing section between 1500 resistor and VGA connector should be kept as short as possible with proper trace width for 750 impedance 2 11TV Out The TV out display TV DAC interface consists of 3 outputs which can be used in different combinations to support component video S video or composite video 2 11 1 Signal Description Table 2 37 TV signals description Sora vo _ O TVDAC Channel A Output supports the following Composite video CVBS Component video Chrominance Pb analog signal S Video not used DAC TVDAC Channel C Output supports the following Composite video not used Component video Chrominance Pr analog signal S Video Chrominance analog signal TVDAC Channel B Output supports the following Composite video not used Component video Luminance Y analog signal S Video Luminance analog signal TV DAC C 2 11 2 Schematic Guidelines 2 11 2 1 Termination resistor output filter and ESD protection diodes There are three
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10. It should be assigned starting at the first pair as REQO GNTO Therefore external bus mastering devices should be placed in the lowest number and the non bus mastering devices should be placed in the highest number of REQx GNTx 2 7 4 4 Non necessary Signals for Individual PCI device A PCI device implemented directly on the carrier board uses a subset of the signals shown on the slot connector Some pins on the slot connector are used for slot and PCI card management functions and are not necessary for the operation of the PCI device An individual device will not have pins REQ64 ACK64 M66EN PRSNT1 PRSNT2 SDONE SBO or the reserved pins Most devices do not implement the test pins TDI TMS and TRST Most PCI devices use INTA only and do not have a connection for INTB INTC or INTD 43 Advantech COM Express Carrier Board Design Guide Addendum 2 7 4 5 Carrier Board PCI slot Power Requirements All PCI connectors require four power rails 5 V 3 3 V 12 V and 12 V Systems that provide PCI connectors are required to provide all four rails in every system with the current budget Systems may optionally supply 3 3 Vaux power Systems that do not support PCI bus power management must treat the 3 3 Vaux pin as reserved There are no specific system requirements for current per connector on the 3 3 V and 5 V rails this is system dependent Note that an add in card must limit its total power consu
11. LPC FRAME Reciver LPC_DRQO Heal 6 LPC DRQ1 7 LPC SERIRQ on LPC USE en e 8 rl 9 Figure 2 53 Serial Bus Connection 2 12 4 2 PS 2 Keyboard and Mouse For a general design consideration the keyboard and mouse should be far away from audio and signal traces to avoid crosstalk According to the general keyboard and mouse power specifications the traces of keyboard and mouse power trace should be routed to afford 1A The power can be Vcc main power or 5VSB if wake up from 3 is needed The reference schematic is shown in Figure 2 54 Keyboard Connector COM Super Mini dim 6P Express Bead vcc LPC AD 0 LPC_AD 1 LPC_AD 2 LPC AD 3 LPC_FRAME KB_DAT m KBDAT LPC_DRQ 0 KB_CLK KBCLK LPC DRQ I LPC SERIRQ E GND LPC CLK Digital Ground Chassis Ground ouse Connector vec Trace Wide Mini dim 6P Fuse Bead VCC deans MSDAT MS_CLK MSCLK GND Figure 2 54 Keyboard and Mouse connection To avoid EMI and ESD the ground plane of the keyboard mouse connector and other digital ground planes should be separated with an isolation moat which is recommended to be at least 40 mils in width Digital ground and chassis ground should be connected via screw holes to assure the integrity of the ground plane 59 Advantech COM Express Carrier Board Design Guide Addendum
12. c16 SIDESURR R SIDESURR R1 123 1181028 SIDESURR R2 FA LINE1 R 1 122 and1B1025__LINE1 R2 Aa E 119 du SIDESURR JD R12l F2 tu SIDESURR L SIDESURR L1 125 jw 1181028 _ SIDESURRL 1 N LINET L 124 41181025 22 c12 C120 c12 100p 100 100 100 44 4 mA Figure 2 12 Reference Audio Schematic 21 Advantech COM Express Carrier Board Design Guide Addendum 2 2 5 Layout Guidelines 2 2 5 1 General Board Routing Recommendations e The ground return paths for the analog signals should be considered e Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split Place the analog and digital signals as far as possible from each other e Partition the board with all analog components grouped together in one area and all digital components in another Keep digital signal traces especially the clock as far away as possible from the analog inputs and voltage reference pins e All resistors in the signal path or on the voltage reference should be metal film Carbon resistors can be used for DC voltages and the power supply path where the voltage coefficient temperature coefficient and noise are not factors e Locate the crystal or oscillation closed to the codec The AC 97 Audio HD Audio trace impedance from codec to COM Express Module should be 55 t 15
13. such that the pairs alternate between TX and RX on the carrier board or non interleaved where the TX and RX pairs are routed next to each other Only interleaved routing can be used for micro strip routing topologies For strip line routing it is recommended to route the TX and RX differential pairs as interleaved to reduce the crosstalk Figure 2 32 shows the example TX 0 TX 0 RX 0 TX 1 TX 1 RX 1 RX 0 RX 1 Figure 2 32 interleaved left and non interleaved pairs right 36 Advantech COM Express Carrier Board Design Guide Addendum 2 5 3 4 PCI Express Topology 2 and 3 Device Up Routing Both the ExpressCard and the docking topologies allow a maximum of 9 inches from COM Express connector to the device up docking connector as Figure 2 33 The maximum length takes into account all routing including the breakout region The Table 2 18 shows the traces length limitation and capacitors value The TX and RX pairs must be routed interleaved to reduce the crosstalk effect on the micro strip and strip line traces COM Express Express TX RX or Docking RX 12 TX connector Figure 2 33 Topology 2 and 3 COM Express to Express Card or Docking Connector Table 2 18 COM Express to Express Card L1 L2 Capacitor Value Max 9 inches Max 9 inches 75 nF to 200 nF Tolerance 20 37 Advantech COM Express
14. 2 12 4 3 LPT Floppy The pulled up resistors of LPT and Floppy are shown in Figure 2 55 and Figure 2 56 COM Express LPC LPC ADI LPC AD 2 LPC AD 3 LPC FRAME LPC_DRQO LPC SERIRQ COM Express LPC LPC LPC AD 2 LPC 03 LPC FRAMH LPC DRQ0 LPC DRQI LPC SERIRQ LPC CLK Super VO 4 7k ohm Route to Minimum Figure 2 55 LPT Connection Super Figure 2 56 Floppy Connection 33 ohm 1k ohm Route to Minimum 2 12 4 4 EMI Considerations Legacy I O such as LPT Floppy or COM ports should be physically isolated between digital circuitry analog circuitry power and ground planes This isolation prevents noise sources located elsewhere on the PCB from corrupting susceptible circuits An example is power plane noise from digital circuits entering the power pins of analog devices audio components I O filters and interconnects vcc Parallel Port D Sub 25 Strobeft Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 AutoFeed Error Initial Select Input Acknowledge Busy Out of Paper Select Floppy Index Track Write Protect Read Data Diskette Chang Motor 0 Drive Select A Drive Density Seleq Head Select DIR Step Drive Select Motor on 1 Write Data Write Enable 8 Each I O port must have a
15. 2 DC Specifications 1 90 000 0 53 2 10 3 VGA Specifications 54 2 10 4 Schematic Guidelines retreat tne ek ie 54 2 10 5 Layout Guideline E 54 gt pl A 55 2 11 1 LE aa 55 2 11 2 Schematic Guidelines 55 2 11 3 Layout Guidelines T 57 AUN mP 57 57 2 12 2 Schematic Guidelines 58 2 12 3 Layout 58 2 12 4 Application Notes for Super I O 58 2 13 Power Management Signals 1 1 1 62 2 13 1 Power Good Reset 4 62 2 13 2 63 PACA EOS 64 2 14 1 Miscellaneous Signal Descriptions 64 64 2 14 3 2C BUS 65 2 14 4 12C 66 2 14 5 SMBUS Q 66 2146 WDT 67 Chapter 3 Power Management and Power Delivery 68 3 1 Power Design Guidelines rt ueque sque duet us 68 3 1 1 ATX Power Delivery Block
16. 4 4 Critical Dimensions There are two critical dimensions that must be considered during the layout phase of an Ethernet controller These dimensions are identified in Figure 2 8 as distance A and B Distance A Transformer to RJ 45 LAN Connector Priority 1 The distance labeled A should be given the highest priority in the backplane layout The distance between the transformer module and the RJ 45 connector should be kept to less than 1 inch of separation The following trace characteristics are important and should be observed 1 Differential Impedance The differential impedance should be 100 The single ended trace impedance will be approximately 50 however the differential impedance can also be affected by the spacing between the traces 2 Trace Symmetry Differential pairs should be routed with consistent separation and with exactly the same lengths and physical dimensions for example width and spacing Distance B From COM Express Module to Transformer Priority 2 Distance B should also be designed to be as short as possible Be sure not to route Distance B 16 Advantech COM Express Carrier Board Design Guide Addendum over 2 5 inches for Intel s layout guide The high speed signals propagating through these traces require the shortest distances between these components COM Express GBE_MDI 0 GBE_MDI 0 GBE_MDI 3 GBE_MDI 3 Figure 2 8 Critical Dimensions LAN
17. Carrier Board Design Guide Addendum 2 6 SDVO The SDVO function shares the pins of the PEGX16 interface SDVO ports should be working with proper intel Video BIOS for setting SDVOB and SDVOC configurations For CH7308 SDVO to LVDS application the reference schematic of Advantech carrier board is as in Figure 2 34 VCC LVD 2 50 VCC LVD 2 50 10825 SDVO R429 gt 419 58K T 56K SDVO SDVO CLCLK SDVO CLDATA SDVO TXP2 SDVO 1 2 FB 0603 MLDST AVDD 99 L cose pee D tuF FB 1 2 FB 0603 051 0 00 lose i usus J 0 tuF 3 g Fes 1 2_ 0603 MLDSLAVDD C346 C350 Linorr R383 R384 8 2K 8 2K 0 192 1 052 5 AS 1 address 70H AS 0 address 72H LVDS ENBKL CH7308 VOS 7308 D tuF R381 1K R385 10K LVDSI LVDS DDCPDATA LVBST LVOS DDCPCLK voc 8 0 24 WP 2 R368 T 3 R365 55K R366 5 6K 1 LvDS SC TOS S0 FROM A SCL 5 Tour C352 si C334 S TO LVDS 14318MHZ C353 CL 22P 4903 n 6 5 51PF 529899329 CH7308 64 pin LQFP CONNECTOR MLDS1 LvDD1 i 2 FB T if Ey ee c34g
18. Connector Magnetic Module RJ 45 Transformer ES B 2 5 inches max A 1 inches max 17 Advantech COM Express Carrier Board Design Guide Addendum 2 2 AC 97 Audio HD Audio COM Express provides an AC 97 Audio HD Audio interface which is compliant to AC 97 AUDIO Rev 2 3 Specification and the HD Audio Specification Please establish the CODEC of AC 97 Audio HD Audio on the carrier board for your application 2 2 1 Signal Description Table 2 3 shows COM Express AC 97 Audio HD Audio interface signals including pin number signals 1 0 and descriptions Table 2 3 Audio signals description RST lo 97 Audio HD Audio Reset output to AC97 CODEC active AC 97 Audio HD Audio 48 kHz fixed rate sample synchronization signal to the CODEC s AC 97 Audio Bit Clock Input This signal is a 12 288 MHz serial data clock generated by the external codec s This signal has an SYNC integrated pull down resistor HD Audio Bit Clock Output This signal is a 24 MHz serial data clock generated by COM Express This signal has an integrated pull down resistor so that AC BITCLK does not float when an HD Audio codec or no codec is connected but the signals are temporarily configured as AC 97 AUDIO 2 2 2 DC Specifications Symbol Parameter Min Mex um Wi mputowvotag v vn mpuHgnvolag v 1 Dvdd 5V or 3 3V Table 2 5 97 AUDIO C
19. Guide Addendum COM ExPress Carrier board SATA port e Cac LB LA TX Cac e LB 1 RX SATA connector TX Cac LD TX RX Cac e LE e LD e LE e Figure 2 20 SATA traces length matching 2 4 Primary IDE 2 4 1 Signal Description Table 2 9 shows the COM Express IDE signals Table 2 9 IDE signals description Signal 1O Description D13 14 15 o D16 51 0 IDE Device Chip Select for 1 to fFFOhrange O Device Chip Select for 3FOh to 3FFOh IDE DMA Request for IDE Master This is the input pin from the IDE DMA request to do the IDE Master Transfer It will active high in DMA or Ultra 33 mode and always be inactive low in PIO mode IDE_ACK O IDE device DMA Acknowledge D17 IDE_CS3 IDE_REQ IDE device I O ready input Pun iow by me IDE Seuke civelow __ IDE_IOR VO ready line to IDE device write line to IDE device ows Data latched on trailing rising edge Interruptrequestfrom IDE device IDE RESET amp Low active hardware reset RSTISA inverted Input from off module hardware indicating the type of IDE cable being used High indicates a 40 pin cable used for IDE_CBLID legacy IDE modes Low indicates that an 80 pin cable with interleaved grounds is used Such a
20. USB 0 1 OC line shall be present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low USB over current sense USB channels 2 and 3 A pull up for this USB 2 3 OC line shall be present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low USB over current sense USB channels 4 and 5 A pull up for this USB 4 5 OC line shall be present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low USB over current sense USB channels 6 and 7 A pull up for this USB 6 7 OC line shall be present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low 2 8 2 DC Specifications Table 2 30 DC specification of USB signals Symbol Vbus High power port supply voltage 5 25 Vbus Low power port supply voltage 5 25 Vi v 20 27 35 Vo 0 Vs Notes For high power function the Max Supply current for each port is 500mA 2 8 3 USB Spec Refer to Universal Serial Bus Specification Revision 2 0 April 27 2000 2 8 4 Schematic Guidelines The Figure 2 41 shows the USB connections for COM Express USB signals The ESD are recommended and the capacitors are reserved for EMI compliance which are usually not loaded 47 Advantech COM Express Carrier Board Design Guide Addendum V5 USB 0 1 15 USB VCC2 P
21. cable is required for Ultra DMA 66 100 and 133 modes 2 4 2 DC Specifications Table 2 10 Ultra DMA modes 1 4 5V Symbol Parameter Min Vu imptHgnvoge _ Output Low Vow Output High Votes 2 oOo 1V 27 Advantech COM Express Carrier Board Design Guide Addendum 2 4 3 IDE Spec Please refer to Information Technology AT Attachment with Packet Interface 7 Volume 2 ATA ATAPI 7 V2 Annex B 5 for the details 2 4 4 Schematic Guidelines 2 4 4 1 Design Considerations The IDE port can support two hard drives or other ATAPI devices The two devices on the port are wired in parallel which is accomplished by plugging both drives into a single flat ribbon cable equipped with two socket connectors A jumper can be manually set on each IDE device for selecting master or slave mode If two devices are used in the master slave mode the IDE CBLID of both devices must be connected together as in Fig 2 21 These pairs of pins negotiate between the master and slave devices The devices may not function correctly unless these pins are interconnected If two devices are plugged into one standard IDE cable the cable will interconnect the pins properly by itself Host connector Device 0 Device 1 connector connector PDIAG CBLID conductor Figure 2 21 IDE Master Slave Handshake Signals Connection The DASP S pin 39 on IDE connector or pin 45 on CF connector should be al
22. components are semiconductor devices specifically designed for transient voltage suppression applications The features are the stable and fast time constant to avalanche and a stable clamping level after avalanche 3 LC filters is a combination of an inductor and a capacitor to ground This constitutes a low pass LC filter that prevents high frequency ESD energy from entering the system The inductor presents a high impedance source to the pulse thus attenuating the impulse energy that enters the system The capacitor located on the input side of the inductor will shunt high frequency ESD spectral level components to ground An additional benefit is the enhancement of radiated EMI noise suppression 61 Advantech COM Express Carrier Board Design Guide Addendum 2 13 Power Management Signals Power button to bring system out of S5 soft off active on button input Active low input System is held hardware SYS RESET reset while this input is low and comes out of reset upon Reset output from module to Carrier Board Active low Issued by module chipset and may result from a low SYS_RESET CB RESET input a low PWR OK input 12V power input that falls below the minimum specification a watch dog timeout or may be initiated by the module software Power OK from main power supply A high value indicates that SUS STAT maras system suspend operation used to notify LPC SUS_S3 Indicates syste
23. control the power management of ATX 5V standby 5VSB power is needed in ATX Mode The 5VSB is sourced from the DC input of AT power as 12V The chipsets COM Express Module needs the 5VSB to enable the control mechanism for the power on off and ACPI functions The standby power 5VSB should be generated by carrier board power circuits from 12V AT power source The ATX working model can be implemented by using a switch to turn on the AT power 12V input to the COM E Module in S0 S1 and Turn off the AT power input power in S3 S4 S5 The schematic for the design of the ATX working model is below in Figure 3 4 Use the signal SLP_S3 to control the PMOS switch and Q1 for controlling the AT power input to the COM Express Module For ATX power pressing the power button can turn on or turn off the system power controlled by SLP_S3 In S3 mode the 5VSB in COM E Module is still supplied by the carrier board but the AT power input 12V should be turned off on the carrier board without supplying the 12V to the COM Express Module 04425 V12_IN ot 12 DC IN L1 150 100MHz N c5 ce T 470uF 0 1uF Figure 3 4 ATX Working Model Based on AT Power Input Reference Schematics 71 Advantech COM Express Carrier Board Design Guide Addendum Chapter 4 PCB Layout Guidelines A brief description of the Printed Circuit Board PCB for COM Express based boards is provided in this section Fro
24. maximum allowable clock skew is 2 ns as the Tskew shown in the Table 2 24 and Figure 2 37 The specification applies not only at a single threshold point but at all points on the clock edge that fall in the switching range The maximum skew is measured between any two components rather than between connectors To correctly evaluate clock skew the system designer must take into account clock distribution on the add in card Symbol 3 3 V Signaling 5 V Signaling Units Tskew 2 max 42 Advantech COM Express Carrier Board Design Guide Addendum CLK Device CLK Device Figure 2 37 Clock Skew of PCI 2 7 4 3 Clock Buffer and PCI Arbiter REQ GNT signals are used by bus mastering PCI devices Most COM Express Modules do not have enough REQ GNT pairs and pins available to support the bus mastering device on each slot The PCI arbiter should be implemented while the extra REQ GNT pairs are required Figure 2 38 shows the design example for PCI arbiter OPZ FRAME AVCC PCIREQ 1 STOP PCIGNTZ SY SREQ VCC Y PREOZ SY SGNT MS1PCICLK MS1PGNT 1 PCIREQ1 PCICLKI PCIRSTZ VETPREOZ 8 PCIGNT1 RESET 33 MS1PGNT 2 PCIREQ2 PCICLKO 33 PCICLK PCIGNT2 PCICLK1 33 D K Ue DCN TH PCIREQ3 PCICLK2 33 PCIGNT3 PCICLK3 33 PCICLK4 VC3A VC3B AVSS VC5A VC5B MS 1 Figure 2 38 Design Example PCI Arbiter If there are less than four REQ GNT pairs available for external devices
25. maximum length difference between the data signals and the strobe signal IDE IOR and IDE IOW should be less than 100 mils Refer to Advantech layout checklist for the detail of each platform Use Daisy chain not Y type routing if two connectors as both IDE and CF are needed Table 2 11 IDE Routing Summary IDE Routing Trace Impedance Trace length IDE Signal length matching The two strobe signals must be 5 on 5 Based matched within 100 mils of each other 55 1596 on stack up in 1 7 inches The data lines must be within 450 chap 4 mils of the average length of the two strobe signals 30 Advantech COM Express Carrier Board Design Guide Addendum 2 5 PCI Express Bus COM Express provides a PCI Express Bus interface that is compliant with the PCI Express Base Specification Revision 1 0a It supports several general purpose PCI Express port x1 and external graphics using PCI Express architecture x16 as PEG interface 2 5 1 Signal Description Table 2 12 shows COM Express PCI Express bus signals for general purpose Table 2 13 shows PCI Express bus signal for external graphics Table 2 14 shows ExpressCard signals Description 69 65 62 59 56 53 PCIE TX 0 5 B69 65 62 59 56 53 PCIE RX 0 5 3 PCIE TX 16 31 A88 PCIE WAKEO PCI Express Differential Transmit Pairs 0 through 5 PCI Express Differential Receive Pairs 0 through 5 PCI Express Differential Trans
26. of PCI Slots Devices on carrier board 41 Figure 2 36 Interrupt Routing and IDSEL Schematic Reference 42 Figure 2 37 Clock Skew of PG Mecca TES 43 Figure 2 38 Design Example PCI 222 2 222 24 43 Figure 2 39 PCI Bus Layout Example with 2 2222 45 Figure 2 40 46 Figure 2 41 5 48 Figure 2 42 Common Mode Choke and ESD suppression design 48 Figure 2 43 Overcurrent GIPGUIL Ina 49 Figure 2 44 Power Switch with Overcurrent Protection Circuits 49 Figure 2 45 USB Layout G idelifigs ttr rina 50 Figure 2 46 Violation of Proper Routing Techniques 50 Figure 2 47 One LVDS Differential Pair with Choke 51 Figure 2 48 VGA reference 54 Figure 2 49 Connection Diagram 56 Figure 2 50 TV 56 Figure 2 51 TV DAC 57 Chapter 1 Introduction 5 Figure 2 52 Figure 2 53 Figure 2 54 Figure 2 55 Figure 2 56 Figure 2 57 Figure 2 58 Figure 2 59 Figure 2 60 Fig
27. pairs The USB data pairs ex USB 0 and USB 0 should be routed on the carrier board as differential pairs with a differential impedance of 90 The proper trace width and spacing to achieve the impedance is based on the impedance calculation of adopted PCB stack up design The two data traces of each USB pair should be matched in length and kept at the same spacing as Figure 2 45 Sharp corners should be avoided The loop routing areas should be minimized near the pins of COM Express Module connector and USB connector USB data pairs should be routed as far from other signals as possible for reducing crosstalk 49 Advantech COM Express Carrier Board Design Guide Addendum Recommended USB Connector 7 x COM Express N USB 0 uet I USB 0 zem Route to Minimum jg x z USB 3 uss 1 amp 7 Sor Not Recommended Figure 2 45 USB Layout Guidelines 2 8 5 2 Crossing a plane split Figure 2 46 shows the data lines crossing a plane split This will cause the return path currents poor and cause EMI problems If a plane split crossing cannot be avoided the capacitor bridge on the plane split is needed as shown in Figure 2 46 Ground or power plane Dont cross Avoid creating stubs plane splits Figure 2 46 Violation of Proper Routing Techniques 50 Advantech COM Express Carrier Board Design Guide Addendum 2 9 LVDS 2 9 1 Signal Description Table 2 31 shows the C
28. should be guaranteed by design It is the minimum voltage to which pulled up resistors are calculated to pull a floated network Applications sensitive to static power utilization must assure that the input buffer is conducting minimum current at this input voltage 2 7 3 AC Specifications Refer to PCI Local Bus Specification Revision 2 3 chapter 4 2 for details 2 7 4 Schematic Guidelines 2 7 4 1 Differences among PCI Slots Most PCI signals are connected in parallel to all the slots or devices The exceptions are the following pins from each slot or device as Table 2 22 Table 2 22 Carrier PCI Slots IDSEL Connected through resistor to a different AD line for each slot CLK Connected to a different COM Express PCI clock signal for each slot INTA INTB INTC INTD Connected to a different COM Express interrupt signal for each slot REQ Connected to a different COM Express request signal for each slot if used GNT Connected to a different COM Express grant signal for each slot if used Each signal connects differently for each of the four possible slots or devices as summarized in the following PCI Slots Devices Table 2 23 Table 2 23 Carrier PCI Slots Devices Interrupt Routing Table Advantech COM Express Carrier Board Design Guide Addendum mom 0c PE c EC RENI COM Express Module AD23 Pin C43 AD22 Pin Dio
29. the inputs due to the ground potential difference between the audio jacks ground and the codec s ground Figure 2 16 shows the grounding example for 97 Figure 2 16 AC 97 Audio Ground Guidelines 2 2 5 5 AC 97 Audio Mic Line In Aux In Considerations The back panel audio inputs Mic Line in Aux in should be independently routed The ground return paths should be isolated from the carrier board ground plane Use a capacitor to filter noise from the inputs bias net which may feed to all jacks Route the input traces as far as possible from other traces 24 Advantech COM Express Carrier Board Design Guide Addendum 2 3 Serial ATA COM Express Module provides up to four Serial ATA SATA interface depending on the chipset specs of the module 2 3 1 Schematic Guidelines 2 3 1 1 Serial ATA AC Coupling Requirements Both the TX and RX SATA differential pairs require AC coupling capacitors Figure 5 51 shows the connection for COM Express SATA signals All AC coupling capacitors on the transmitter TX and receiver RX are placed on the COM Express Module Do not place the AC coupling capacitors on the carrier board Figure 2 17 and Figure 2 18 show the connections Carrier board COM Express ICH6 M us RX SATA RX Connector RX SATA port gx TX TX Figure 2 17 SATA interconnect
30. 0 8 for the monitor timing specification 2 10 4 Schematic Guidelines The reference schematic of VGA is shown in FIG 2 48 The VGA_I2C_CK and 12 DAT signals must connect to the CRT monitor to detect the plug and play and monitor type info VCC3 3V DD1 MMBD7000LT1 VCC3 3V VCC3 3V DD2 1 2 MMBD7000LT1 DD3 MMBD7000LT1 1 D 2 SOT 28A gt SOT 23A SOT 23A GND_F CRTR x L12 y 0603A 75 FB 0603A 75 R73 R74 150 150 150 10 GND VCC3 3V CR R76 R77 2 2K_NL 2 2K_NL 6 VGAR 1 la Hox 9 j VGAG 2 o 12 DDDAR R78 CRT DDCDAT ves 1 0 3 13 VGAHSY RR79 33 CRT HSY VGAVSY RR80 DDCK R__R81 CRT_DDCGLK VGA C89 C90 DBVGA VF7M 68P 68P GND_F Figure 2 48 VGA reference schematic The DDC pulled up and ESD protection voltage could be 3 3V or 5V depends on the power map of the carrier board 2 10 5 Layout Guideline 2 10 5 1 RLC Components The RGB outputs are current sources and therefore require 150 load resistors from each RGB line to analog ground to create the output voltage approximately O to 0 7 volts These resistors should be placed near the VGA port a 15 pin D SUB connector Serial ferrite beads for the RGB lines should have high frequency characteristics to eliminate relative noise
31. 1 C3 0 tuF Touro LVDS1 40M TVDST ADP 1 051 5 LvDS1 A2M LVDST AZR LVDS1 CLKIM TVOST CLRTP_ 1 0 1 TO LVDS CONNECTOR R NTEL CH7308B TF of C356 epum FB10 1 FB 0603 pem alb 4 4 LVOS1 CLK2P IVDST CLEZM 1 051 7 5 7 LVDS1 A6P TVOST Aan LVDS1 A6P LVDS1 A4P LVDS1 A4MVSWING Me R397 2 4K al ao Figure 2 34 CH7308 Schematic The pulled up resistors of SDVO_DAT and SDVO_CLK should be populated on the carrier board to let COM Express Module enable the SDVO Contact Advantech for advanced technical support Polarity Inversion and Lane Reversal are NOT supported on SDVO signals which are sharing the PCI Express Graphics X16 interface pins For the application of all SDVO devices please refer to the schematic and layout guidelines from the SDVO device vendor and request Advantech technical support 38 Advantech COM Express Carrier Board Design Guide Addendum 2 7 PCI Bus COM Express provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2 3 The implementation is optimized for high performance data streaming when COM Express is acting as either the target or the initiator on the PCI bus For more details of the PCI Bus inte
32. 9 2K V VV NV SIDESURR ID CEN ID MIC2 JD LINE2 JD Figure 2 11 Jack Detection with sensing resistors The schematic of the evaluation board is shown in Figure 2 12 20 Advantech COM Express Carrier Board Design Guide Addendum R108 MICt VREFO R BD ent LINE2 VREFO C357 0 1 10K R110 5VA0 MIC2 VREFO C358 0 1u LINE1 VREFO L MIC1 VREFO R105 yy 0 MC1 VREFO L SenseB en SIDESURRJD 51 yy Rif R112 yy se ZN CEN JD 10K yy R113 FRONT L C105 C106 FRONTR T ion 10 12 g 3 3 3 4 4 99 g us 9 8398 zs aay a a X 43 md Y eth 5 868850992948 Senee lt A 646565 T LINE1 VREFO R E 288i mum ET LINE1 R 25 2 g LINE1 L 38 AVDD2 E H SURR L MIC1 R RU yy 391 sURR L Mict R 22 MIC1 L Soi 40 JDREF NC 21 SURR R CD R R118 yy 0 4 coa L2 lt AVSS2 ALC888 cp cnp S CD GND CEN CD L 43 co 18 C361 0 14 4 ire EZ MCeR D MIC2 R 29 SIDESURR L MIC2 L Ei REO 45 sipESURR L mice H
33. AD2I Pino AD20 Pin reo 49 INTB pincsol PCI Slot Device 0 PCI Slot Device 1 PCI Slot Device 2 PCI Slot Device 3 INTG pin pi INTD Pin D47 Pin Pin Pin 06 Pin 26 IDSEL IDSEL IDSEL IDSEL Pin A6 Pin A6 Pin A6 Pin A6 e e e e Pin 7 Pin 7 Pin B7 Pin B7 N e e ae e 4 24 Pin 7 Pin A7 Pin A7 7 e p Pin B8 Pin B8 Pin B8 Pin B8 e e e Figure 2 35 Interrupt Routing of PCI Slots Devices on carrier board Due to different system configurations IRQ line routing to the PCI slots should be made to minimize the sharing of interrupts between both internal chipset functions and PCI device functions In this case the INTA pin of the device should not necessarily be connected to the COM Express Connector INTA signal Please refer to Figure 2 35 The Pin is connected to INTA on Device 0 but INTD on Device 1 The Pin B7 is connected to INTB on Slot 0 but INTC on Slot 1 The schematic reference of INTx and IDSEL example are shown in Figure 2 36 41 Advantech COM Express Carrier Board Design Guide Addendum VOC3 3V VOC3 9 e voc 12V vec vcc 1 V 1011 ve veci o o o 1 B2 B3 VOCS 83 VOCS 63 1 B5 85 5V INTHA INTHB INT B NT Li D PCICLK2 PCIG
34. C Capacitor 75 nF 20 close to the transmit side between the differential 200 nF pairs 32 Advantech COM Express Carrier Board Design Guide Addendum 2 5 2 2 Bowtie Topology Considerations Untangling Nets is possible that when interconnecting PCI Express devices the bowtie or signal crossing scenarios might occur when the link is routed on the PCB There are three main types of these scenarios 1 TX TX crisscrossing within a pair 2 Crossing of transmitter and receiver pairs within a lane 3 Crossing of lanes within a link The PCI Express specification provides two different features Polarity Inversion and Lane Reversal Both features help to overcome the layout difficulties encountered in scenarios 1 and 3 The specification does not include any provisions to address scenario 2 e Polarity Inversion The PCI Express spec requires polarity inversion to be supported independently by all receivers across the link i e the positive signal from the transmitter TX can connect to the negative signal of the receiver RX in the same lane Of course that means the negative signal from the transmitter TX must now also connect to the positive signal of the receiver RX in such a scenario Figure 2 28 shows an example It is important that polarity inversion does not mean the direction inversion i e the TX differential pair from one device must still connect to the RX differential pair on the receiver devi
35. DAC output pins TV DAC A TV DAC B and TV DAC C There are two 1500 196 resistors in each signal One of the 150 1 parallel termination resistors is already implemented on the COM Express Module The other 150 196 parallel termination resistor should be implemented on the carrier board Figure 2 49 shows the connection diagram of TV out 55 Advantech COM Express Carrier Board Design Guide Addendum COM Express Carrier Board N TV DAC A Video Filter 150 ohm 150 ohm PN TV DAC B Video Chipset Filter onnector 150 ohm 150 ohm TV DAC Video ZS Filter 150 ohm lt 150 ohm Figure 2 49 Connection Diagram of TV out 2 11 2 2 ESD Diode ESD diodes are required for each TV DAC channel output The diodes should connect between the VCC power plane from the regulator and ground These diodes should have a low C rating 5 pF max and a small leakage current 10 uA at 120 C The diodes should be placed to keep the inductance of the VCC power rail connection as low as possible The diode placement should be similar for all three output signals and should not be close to any other signal especially video or clock signals In addition one decoupled capacitor C1 0 1 uF should be placed closely and across the ESD diodes to reduce noise on the VCC The VCC could be 3 3V or 5V power rail 2 11 2 3 TV DAC Video Filter A video filter is required fo
36. J45 connector should be made as short as practical For Ethernet connector placement place it as close as possible to the COM Express Module pins to shorten the routing lengths of all Ethernet signals Differential signal traces should be kept as short as possible to decrease the possibility of being 13 Advantech COM Express Carrier Board Design Guide Addendum affected by high frequency noise from other signals and power planes and capacitive loading is also reduced Please refer to the Advantech layout checklist for detail 2 1 4 1 Differential pairs design considerations 14 Maintain constant symmetry and spacing between the traces within a differential pair Keep the signal trace lengths of a differential pair equal to each other Do not use serpentines to try to match trace lengths in the differential pair Serpentines cause impedance variations causing signal reflections which can be a source of signal distortion Try to keep the length difference of the differential pair less than 5 mil The total length of each differential pair should be less than 4 inches Keep the length of each differential pair under 4 inches Figure 2 4 shows an example Please refer to the Advantech layout checklist for detailed length matching Do not route the transmit differential traces closer than 50 mils to the receive differential traces for 10 100 Mbps Do not route any other signal traces including other differential pairs parallel to
37. MP Tyco 3 1318491 6 0 5mm pitch Free Height 220 pin 8H Plug or equivalent AMP Tyco 8 1318491 6 0 5mm pitch Free Height 220 pin 8H Plug or equivalent same as previous part but with anti wicking solution applied 77 Advantech COM Express Carrier Board Design Guide Addendum A source for the combined 8mm stack height 440 pin plug composed of 2 pieces of the 220 pin plug held by a carrier is AMP Tyco 3 5353652 6 0 5mm pitch Free Height 440 pin 8H Plug or equivalent Note The part number above shown with a leading 8 has an anti wicking solution applied that may help in processing with an aggressive flux The other versions of the parts may also be made available with this solution by the vendor The Carrier Board connector is a plug by virtue of the vendor s technical definition of a plug and to some users it looks like a receptacle Figure 5 3 Carrier Board Plug 8mm Version 5 4 COM Express Connector PCB Pattern Module pln A1 C1 receptacle Carrier Board pin 81 01 plug 1 620 15 2 1 75 3 6 0 05 1 75 T Module pin 01 receptacle Corrier Boord pin A1 C1 plug All dimensions in mm Figure 5 4 COM Express Connector PCB Pattern To save design in time and ensure correct connections and dimensions Advantech provides a schematic and footprint library for COM Express connectors Please contact Advantech for technical support
38. NT O PCIGNT 1 PCIREQ O PCIREQ 1 PMER PME AD31 0 030 S HH AD28 H 28 ADI E ADI ADI AD24 024 C BEN3 R38 100 020 R39 100 Ba H AD22 022 4021 ADZO ADZO ADTS 18 ADIS ADI T FRAME IRDY TRDY amp TRDY amp DESEW T 1 STOP voc vac LOCK R40 5 6 H R43 5 6K PERRA M AM JT PAR R41 5 6K E PAR R42 5 6K aaa AD D E ADI3 012 E ADOS aar AD AD ND 09 09 ADS Pall C BEXO vec C BEND vec 11 253 1 1 464 ADE E ADB ADS 465 4 R44 R45 R4 5 6K 2 5 6K E AD2 5 6K ADI 268 1 ADU ADU 4 0 B60 60 REQ6480 REOQ6480 461 262 al Figure 2 36 Interrupt Routing and IDSEL Schematic Reference 2 7 4 2 PCI Clock and Clock Skew The trace length for all PCI clocks should be matched and controlled PCI clock routes should be separated as far from other signal traces as possible PCI clock signals should be routed as impedance controlled traces with trace impedance of 55 Only one PCI device or slot could be driven directly from the COM Express PCI clock output pin or the clock buffer should be implemented The
39. NTE i R72 IDE 6 PIDE AR 7 PIDE AH PIDE_CS 1 R Caran C PIDECS 3 R DASP S 0 Figure 2 24 IDE Connections 2 4 4 4 Compact Flash Socket Implementation Application Notes For the IDE application the Compact Flash CF card cannot be hot plugged If hot plug support is necessary the PCl based Card Bus controller chip can be integrated 29 Advantech COM Express Carrier Board Design Guide Addendum onto the carrier board and used to control the CF hot plug function The Figure 2 25 shows the CF schematics 26 PIDE D11 F FIDE DT2 R 33 ES vet IOR A Low R210 10K mm IRQ VCC al 2209 10 SE 52 HORST R R213 33 ina RES R211 10K NL veco vw Rector Figure 2 25 CF Connections The CF card can be configured as a slave device when the CSEL signal is set as non connection If two CF cards or one CF card and one hard drive are used in the master slave mode on the same IDE port the IDE CBLID Z and DASP S 0 pins on both devices must be connected The signal negotiates the communication between the master and slave devices 2 4 5 Layout Guidelines 2 4 5 1 IDE data and strobe routing guideline The IDE interface can be routed with 6 mil traces on 6 mil spaces dependent upon stack up parameters and must be less than 7 inches in length from COM Express connector to carrier board IDE connector The
40. ODEC analog I O DC specification Symbol Parameter AUXAL R Full scale input voltage Full scale input voltage SNDL R Full scale output voltage 2 2 3 97 Audio Spec Refer to Audio Codec 97 Revision 2 1 May 22 1998 Chapter 9 for digital signals AC spec and Chapter 10 for analog performance spec 18 Advantech COM Express Carrier Board Design Guide Addendum 2 2 4 Schematic Guidelines AC97 and HD Audio are the popular architectures for implementing audio modem and communications functionality in the IPC market The architecture of the COM Express HD Audio allows a maximum of three CODECs to be connected 2 2 4 1 Connection of AC 97 Audio and HD Audio 2 2 4 2 AC 97 Audio The Figure 2 9 shows the connections for COM Express AC 97 Audio signals with three Codecs AC MC AMC AC_RST gt COM Express AC SDOUT AC SYNC bl P 4 AC BITCLK CD C SDIN O 9966 gt gt gt Secondary gt Codec AC MC AMC p gt Tertiary Codec Figure 2 9 AC 97 Audio Connections The clock is provided from the primary codec on the link via AC_BITCLK and it is derived from a 24 576 MHz crystal or oscillator Refer to the primary codec vendor for crystal or oscillator requirement AC_BITCLK is a 12 288 MHz clock driven by the primary codec to the COM Express digital controller on board and to the other code
41. OM Magnetic RJ45 Module C onnector Express Transformer Route to Minimum inii MDI 0 TX TX Route to Minimum 1 MDI 0 TX TX 2 GBE MDI 1 RX RX 3 MDI 1 RX RX 6 4 4995 5 49 9ohm CT RX 3 ehm 2 NL CT RD a 7 x CT TD CT TX 8 0 10 NL 91 ow aT Excmo d 0 01 AKV 133V LED Q 330 ohm 0 ACT ANNA 330 ohm GBE0_LINK AWW 330 ohm GBE0_100 AWA Figure 2 6 10 100M Ethernet Interconnection 15 Advantech COM Express Carrier Board Design Guide Addendum RJ45 Connector COM Express Route to Minimum Route to Minimum GBE_MDI 0 TD4 MX4 DA GBE MDI 0 TD4 MX4 DA GBB MDI 1 TD34 MX3 GBE MDI 1 TD3 MX3 DC GBE_MDI 2 TD2 2 DC GBE MDI 2 TD2 MX2 DB GBE MDI 3 TDI MX1 DD GBE MDI 3 TD1 1 DD 0 01u 6V 75 4 TCT4 MCT4 ANN TCT3 MCT4 TCT2 MCT4 MCT4 0 01u 1IKV Magnetic Module Transformer LED 43 3V 330 ohm GBEO ACT JN dh GBEO LINK nh 1008 GBEO 10004 TAM 4 Figure 2 7 Gigabit Ethernet Interconnection 2 1 4 3 Power Considerations In general any section of traces that are intended for use with high speed signals should observe proper termination practices Many board layouts remove the ground plane underneath the transformer and the RJ 45 connector to minimize capacitive coupling of noise between the plane and the external Ethernet cable 2 1
42. OM Express LVDS signals Table 2 31 LVDS signals description Pin _ Signal Description 71 73 75 78 LVDS A 0 3 O LVDS Channel A differential pairs 72 74 76 79 LVDS A 0 3 A81 LVDS A CK A82 LVDS A CK B71 73 75 77 LVDS B 0 3 B72 74 76 78 LVDS B 0 3 B81 LVDS B B82 LVDS B CK 77 LVDS VDD EN LVDS BKLT EN LVDS BKLT CTRL LVDS Channel A differential clock LVDS Channel B differential pairs LVDS Channel B differential clock LVDS panel power enable LVDS panel backlight enable LVDS panel backlight brightness control LVDS 2 2C clock output for LVDS display use LVDS 2 DAT 2C data line for LVDS display use Note The LVDS 2 voltage level is 3 3V main power 0Co N BO wo o OJO O O O O oj 2 9 2 DC Specifications Table 2 32 LCD I O Voltage Max os 08 mputHignVotege 2 o lol 4 0mA 1 N 2 9 3 Schematic Guidelines The LVDS signals can be routed directly from the COM Express module to the LVDS connectors Figure 2 47 shows one pair of LVDS connections Each pair can use the common mode choke for EMI compliance if needed 3 LVDSO DO 4 LVDS A D LVDS 0 1 2 1 3m 90 100MHZ Figure 2 47 One LVDS Differential Pair with Choke Design 51 Advantech COM Express Carrier Board Design Guide Addendum 2 9 4 Layout Requirements The timing skew minimization requir
43. a signal to reset the system and carrier board The WDT pin is active high output for carrier board power management applications 67 Advantech COM Express Carrier Board Design Guide Addendum Chapter 3 Power Management and Power Delivery This chapter provides the ATX AT power supply design recommendations for customer s reference 3 1 Power Design Guidelines 3 1 1 ATX Power Delivery Block Diagram The general ATX power source can supply 12V 12V 5V 5V 3 3V 5VSB power If other voltage is required such as 3 3 VSB or LAN 2 5 on the carrier board the additional switching regulator or LDO should be implemented as Figure 3 1 COM Express LDO 3 3VSB 12V 12V 5V ATX Power Source 5V 3 3V 5VSB 5VSB POWER IN Switching regulator or LDO POWER OUT Figure 3 1 ATX Power Delivery Block Diagram 68 Advantech COM Express Carrier Board Design Guide Addendum 3 1 2 ATX power with Super If there is a Super I O as Nuvoton Winbond W83627HG on the carrier board of Advantech the PS ON is controlled by Super I O with proper BIOS While the power button designed as active high is pressed the Super will output an active low PWRBTN signal to COM E Module then the SLP_S3 will be output high by chipset on the module which will inform the Super I O output the PS ON active low to let the ATX power start supplying the main power 3 1 3 ATX power w o Supe
44. an 200 mils 75 ohm Coaxial Cable Carrier board COM Express Spacing DAC _A 280 mils MAX at Video i Filter 05 d A 1500hm Spacing 3 gt 40 mils 150ohm 20 75 ohm Y TV DAC B 2 Video em Chipset 2 500 T Filter r Spacing 1 NS a gt 40 mils 7 75 ohm 33V TV DAC C Zo 500 Y MAX 02 Video Filter 0 5 1500hm Spacing E r x gt 50 mils 1500hm ohm v Figure 2 51 TV DAC Schematic COM Express provides a LPC interface to some devices as Super I O FWH TPM and others 2 12 1 Signal Description Table 2 39 shows COM Express LPC signals Table 2 39 LPC signals description Pin Signal B4 5 6 7 LPC_AD 0 3 O LPC multiplexed address command and data bus 57 TV Advantech COM Express Carrier Board Design Guide Addendum LPC_FRAME O LPC frame indicates the start of an LPC cycle B8 B9 LPC_DRQ 0 1 O LPC serial DMA request LPC_SERIRQ LPC series interrupt LPC_CLK O LPC clock output 33MHz nominal 2 12 2 Schematic Guidelines The schematic guidelines are LPC_CLK should be connected to pin B10 of COM E connector LRESET should be connected to CB_RESET as pin B50 of COM E connector LPC_FRAME cycle termination is shared with FWH and the SIO Some legacy interfaces are using Sup
45. bles The USBOC signal is used to input over current conditions to the system hardware and software The over current protection mechanism typically allows relatively high currents to flow for small periods before the current goes over limit or is interrupted 48 Advantech COM Express Carrier Board Design Guide Addendum F1 USBVFBO L38 11P300S R49 470K R50 ers C74 400 USBVCC USBOCK lt lt Figure 2 43 Overcurrent Circuit The poly switch in Figure 2 43 generally could not switch off fast enough Over current caused by an external USB device may impact the power supply of the carrier board For fast response of sensing and power cutting the active protection circuits shown in Figure 2 44 are recommended These devices may be used for per port protection of the USB power lines and direct connected to the USB X X OC signal V5SB B8 V5SB 120_100MHz 2A R119 C137 9 4V5SB USBO 4 3V5SB USBO C 2 2K 0 1uF 50V 196 ew C138 220uF 470pF T iev sov ga USB_0_1_0c lt B9 am m 120 100 2 MICREL MIC2026 1YM V5SB_USB1 55 USB1 C C141 220uF 470pF T 16 sov p Figure 2 44 Power Switch with Overcurrent Protection Circuits The over current protection circuit is not implemented on the COM Express Module It should be implemented on the carrier board 2 8 5 Layout Guideline 2 8 5 1 Differential
46. c s on the carrier board 2 2 4 3 HD Audio Figure 2 10 shows the connections for COM Express HD Audio signals with three HD Codecs The clock of is provided from the COM Express module via AC_BITCLK signal The AC_BITCLK is a 24 MHz clock driven by the COM Express module as an output to the codec present on the carrier board 19 Advantech COM Express Carrier Board Design Guide Addendum AC MC AMC RST amp gt COM Express gt gt Primary AC_BITCLK gt Cod q AC_SDIN O 9952 SDIN 1 C SDIN 2 AC MC AMC gt P Secondary gt Codec AC MC AMC b Tertiary P Codec Figure 2 10 HD Audio Connections Note AC 97 Audio and HD Audio are mutually exclusive and cannot be used at the same time on a platform 2 2 4 4 HDA Audio Jack Detection Function The HDA audio jack connectors should be designed to detect and inform the operating system which jack is plugged or un plugged It can be done by the sensing resistors and the programmable GPIO pins Figure 2 11 shows the example of jack detection function with sensing resistors Please refer to the codec specification to get more information Network of Sense A To Sense A 5 1K 10K 20K 39 2K MN VV NN FRONT ID LINE1 JD MIC1 ID SURR JD Network of Sense Sense 5 1K 10K 20K 3
47. ce Correct Wrong RX TX RX RX RX TX RX TX TX TX RX TX TX Figure 2 28 Polarity Inversion on a TX to RX Interconnect e Lane Reversal Lane reversal allows the lane number to be switched from high to low and low to high For example the lane 15 from the COM Express would connect to lane 0 of the device and lane 0 from the COM Express would connect to lane 15 of the device The Lane reversal feature needs to be supported by one of the two devices The feature does not imply direction reversal i e the TX differential pair from an upstream device must still connect to the RX differential pair on the downstream device Figure 2 29 shows an example for both Lane Reversal and Polarity Inversion 33 Advantech COM Express Carrier Board Design Guide Addendum Device 1 Device 2 Device 1 Device 2 Device 1 Device 2 TX 0 Polarity TX 0 Lane TX 1 j Inversion Reversal RX 0 11 RX 0 RX 1 RX 1 RX 0 RX 1 RX 0 Figure 2 29 Lane Reversal and Polarity Inversion TX to RX Interconnect 2 5 2 3 Terminating Unused PCI Express Ports If PCI Express ports are not implemented on the carrier board design the PCIE _TX n and PCIE RX n signals should be left as Not Connected 34 Advantech COM Express Carrier Board Design Guide Addendum 2 5 3 Layout Guideli
48. de Addendum 2 1 3 Schematic Guidelines 2 1 3 1 Differential Pairs Designing for Gigabit Ethernet operation is very similar to the designing for 10 100 Mbps 10 100Mbps Ethernet has two differential pairs and Gigabit Ethernet has four differential pairs Figure 2 1 and Figure 2 2 show the 10 100M Ethernet and Gigabit Ethernet Connections COM LAN Connector Express Receive EX DELTA LF8505 GBEO MDI 1 Differential Pairs GBEO MDI 1 Magnetic Module Transformer GBEO MDI 0 gt RJ45 GBEO_MDI 0 Transmit Differential Pairs GBEO_ACT gt GBEO_LINK GBEO_LINK100 E GBEO LINK10002 Figure 2 1 10 100M Ethernet Connections COM LAN Connector Express GBEO MDI 0 GBEO MDI O GBEO MDI 1 Magnetic GBFEO MDI 1 Module GBEO MDI 2 Transforme RJ45 GBFO MDI 2 GBEO MDI 3 GBEO MDI 3 GBEO GBEO_LINK gt GBEO_LINK100 GBEO_LINK1000 lt Figure 2 2 Gigabit Ethernet Connections 2 1 3 2 Center Tap connection of Transformer The COM E signal GBEO CTREF pin A14 should be connected directly to the center tap of the transformer The center tap voltage is the output from the COM Express 12 Advantech COM Express Carrier Board Design Guide Addendum Module to the carrier board usually 1 8V 2 5V or another voltage depending on the LAN chip design 2 1 3 3 LAN Connector with Integrated Magnetic For simplifying the sc
49. e through hole connectors as an effective via If a layer change is necessary ensure that trace matching for either the TX or RX pair occurs within the same layer Do not route SATA traces under crystals oscillators clock synthesizers magnetic devices or ICs that use and or duplicate clocks e Avoid stubs whenever possible Utilize vias and connector pads as test points instead e The SATA differential trace impendence target is 100 20 Use an impedance calculator to determine the trace width and spacing required for the specific board stack up being used keeping in mind that the target is a 100 20 2 3 2 2 Serial ATA Trace length e The length of the SATA differential pairs should be designed as short as possible For direct connected topology where the SATA differential signal pair is routed directly to a mobile SATA connector It s recommended the trace length of SATA signals should be within 3 inches for better signal integrity e The SATA differential pair traces should be length matched The difference between two line traces of TX RX differential pairs should be restricted to less than 20 mils and less trace mismatch is recommended Figure 2 20 shows an example of SATA trace length pair matching LA must equal to La Lg must equal to Lg and so on It s recommended to avoid the vias for layer change ensuring that the differential pairs are equal if necessary 26 Advantech COM Express Carrier Board Design
50. er I O as Serial port Parallel port Floppy IR KBC via the LPC Bus of COM Express pins Figure 5 54 shows the architecture of the LPC interface More information can be found in the Super I O datasheet ISA optional PCl Host Bu Superl O Embedded KBC SP Controller PP FDC Figure 2 52 Architecture of LPC interface The address for Super I O is generally set as 4Eh by Advantech For example the W83627HG Pin 51 signal RTSA should be pulled high 4 7K ohm to 5V for I O address 4Eh strapping If another address is requested as 2Eh then a customized BIOS is needed Contact Advantech for any BIOS requests for specific Super configuration The reset signal of theL PC interface should be connected to the RESET Z pin of the COM Express Module 2 12 3 Layout Guidelines If there is a TPM device place it close to the other LPC peripherals such as FWH and Super 2 12 4 Application Notes for Super I O Functions 2 12 4 4 Serial Port For complying with EMI limits separate the digital ground to the frame ground by adding beads and capacitors to the carrier board Figure 2 53 shows the Serial Bus Connection with EMI considerations 58 Advantech COM Express Carrier Board Design Guide Addendum Com port Chassis ground COM 81 1 Head 2 mischen LPC 3 LPC AD 2 Super Head 4 D Sub 9 LPC_AD 3 Transmitter Head 5
51. es trace length matching between chipset die pad to the pins of the LVDS connector Match the package length difference between each signal group to minimize the timing variance The COM Express module has well designed routing lengths to compensate for the mismatch length of the chipset package Be sure to match the trace length on the carrier board Table 2 33 shows the LVDS Signals Trace Length Mismatch Mapping 2 33 LVDS Signals Trace Length Mismatch Mapping Clocks Data To Associated Clock Associated Ea with the Matching Clock ae Matching LVDS A O CHANNEL A LVDS Docs Pus mils LVDS pace usse 20 mils 20 mils LVDS mils LVDS A CK LVDS LVDS MN mils LVDS group Pair LVDS 0 LVDS B 1 LVDS B CK 20 mils 420 mils LVDS B 2 LVDS B 3 10 mils FEMME Each LVDS signal should be trace length matched to its associated clock strobe within 10 mils The Channel A clock strobe pair must also be trace length matched to the Channel B clock strobe pair within 10 mils Routing for LVDS transmitter signals of different traces are terminated across 1000 1596 and should be routed as following points e ltis necessary to maintain the differential impedance 1000 1596 where all traces are closely routed in the same area on the same layer e Isolate all other signals from the LVDS signals to prevent coupling from other sources to the LVDS lines
52. ess Modules provide a SMBus port for communication with external SMBus slave devices This port is also used internally in the COM Express Module to communicate with onboard SMBus devices such as the SPD EEPROMs on SO DIMMS clock generator chips and hardware monitoring devices The port is externally available on the COM Express pins SMB DAT and SMB CK The addresses for any external SMBus devices must be chosen so that they do not conflict with the addresses that are used internally on the COM Express Module If the device offers externally controllable address options it is desirable to implement carrier board resistor straps to allow the device to be set to at least two possible SMBus addresses Carrier board COM Express Module 4 SMB CLK 3 SMB DAT 2 4 SMB Connector Figure 2 60 SMB Bus Connections 2 14 5 1 Specifications Table 2 43 SMBus Voltage Symbol Unt Nore Min _ O Vit Input Low V Voltage Voltage 1 System Management Bus SMBus Specification v2 0 2 Vcc is the voltage which the pulled up resistor are connected 2 14 5 2 SMBus Spec Refer to System Management Bus SMBus Specification Version 2 0 August 3 2000 66 Advantech COM Express Carrier Board Design Guide Addendum 2 14 6 COM Express Module provides watch dog function the WDT To prevent the system from hanging for a long time the watchdog can generate
53. hematic and layout considerations of LAN connector it is strongly recommended to use the RJ45 LAN connector Figure 2 3 shows the integrated magnetic schematic 3 LAN ACT D 52 220 3 GBEO CTREF gt AM LAN_MDIOP_R LAN_MDION_R LAN_MDI1P_R LAN_MDI1N_R LAN_MDI2P_R LAN_MDI2N_R 5 0 1u LAN MDI3P R YE Le LAN MDI3N R 0 1uF 8 R64 0 TCT22 3 LAN LINK100 D 3 LAN_LINK1000 D R323 0 LINK1000 R140 220 Figure 2 3 Gigabit Ethernet Connections with Integrated Magnetic 2 1 3 4 Implementation of Ethernet LED indicators RJ 45 connector with LED indicators needs 3 3V to drive the LEDs The Link and activity LEDs can be implemented by using the COM Express Module s GBEO_ACT GBEO_LINK GBEO_LINK100 and GBEO LINK1000 pins The sink current is connected to the cathode of the LED and the anode of the LED should be pulled to 3 3V through a resistor as 220 2 1 4 Layout Guidelines Route the transmit and receive lines on the carrier board as differential pairs with a differential impedance of 100 PCB layout software allows determination of the proper trace width and spacing to achieve the impedance after the PCB stack up configuration The TX TX signal pair should be well separated from the RX RX signal pair Both pairs should be well separated from any other signals on the PCB The total routing length of these pairs from the COM Express Module to the Ethernet R
54. his drawing are intended for mounting the module heat spreader combination to the Carrier Board An independent implementation specific set of holes and spacers shall be used to attach the heat spreader to the module Figure 5 1 shows the COM Express Module board mechanical dimensions The unit is millimeters COM Express BP COM Ultra BP AN Figure 5 1 COM Express Module Board Mechanical Dimensions Tolerances shall be 0 25 0 010 unless noted otherwise The tolerances on the module connector locating peg holes dimensions 15 50 6 00 and 16 50 18 00 shall be 0 10mm 0 004 The 440 pin connector pair shall be mounted on the backside of the PCB and is seen through the board in this view The 5 mounting holes shown shall use diameter pads and shall have 2 7mm plated holes for use with 2 5mm hardware The pads shall be tied to the PCB ground plane 76 Advantech COM Express Carrier Board Design Guide Addendum 5 2 COM Express Module Connector The module connector for Pin out Type 2 shall be a 440 pin receptacle that is composed of 2 pieces of a 220 pin 0 5 mm pitch receptacle The pair of connectors may be held together by a plastic carrier during assembly to allow handling by automated assembly equipment The connectors shall be qualified for LVDS operation up to 6 25GHz to support PCI Express Generation 2 signaling speeds Sources for the individua
55. ion example CN32 SATA 2 TX _ SATALTXON C SATA 3 En 44 _ lt 5 RX SATA p 47 GND Serial ATA Figure 2 18 SATA Schematic Reference 2 3 1 2 Indicated LED Implementation COM Express Module provides a signal ATA_ACT to indicate the activity of the SATA devices It can be designed in conjunction with the LED signal of IDE PATA hard drives as DASP S 0 signal The example is shown in Figure 2 19 While the _ is active low it indicates the SATA device is active and then HD_LED is changed to low 25 Advantech COM Express Carrier Board Design Guide Addendum ATA ACT D 3 2 1 iH lt Ovecs 3V LED MMBD2835 DASP S 0 gt Figure 2 19 SATA LED Schematic Reference 2 3 2 Layout Guidelines 2 3 2 1 General routing and placement e Place the SATA connectors as closed as possible to the COM Express Module The routing length is recommended to be not more than 3 inches The Intra pair trace length distance matching should be less than 5 mils e SATA signals must be ground referenced e Route all traces over continuous GND planes with no interruptions Avoid crossing over anti etched areas if at all possible Any discontinuity or split in the ground plane can cause signal reflections and should be avoid Minimize layer changes Use as few vias per SATA trace as possible via count should includ
56. l 220 pin receptacle are AMP Tyco 3 1318490 6 0 5mm pitch Free Height 220 pin 4H Receptacle or equivalent AMP Tyco 8 1318490 6 0 5mm pitch Free Height 220 pin 4H Receptacle or equivalent same as previous part but with anti wicking solution applied A source for the combined 440 pin receptacle composed of 2 pieces of the 220 pin receptacle held by a carrier is AMP Tyco 3 1827231 6 with 0 5mm pitch Free Height 440 pin 4H Receptacle or equivalent Figure 5 2 COM Express Module Receptacle 5 3 COM Express Carrier Board Connector The Carrier Board connector for module Pin out Type 2 shall be a 440 pin plug that is composed of 2 pieces of a 220 pin 0 5 mm pitch plug The pair of connectors may be held together by a plastic carrier during assembly to allow handling by automated assembly equipment The connectors shall be qualified for LVDS operation up to 6 25GHz to support PCI Express Generation 2 signaling speeds The Carrier Board plugs are available in a variety of heights The Carrier Board shall use either the 5 mm or 8 mm heights A source for the individual 5mm stack height 220 pin plug is AMP Tyco 3 1327253 6 0 5mm pitch Free Height 220 pin 5H Plug or equivalent A source for the combined 5mm stack height 440 pin plug composed of 2 pieces of the 220 pin plug held by a carrier is AMP Tyco 3 1827233 6 0 5mm pitch Free Height 440 pin 5H Plug or equivalent A source for the individual 8mm stack height 220 pin plug is A
57. lane splits 72 Advantech COM Express Carrier Board Design Guide Addendum 4 1 1 Four layer board stack up Figure 4 1 illustrates an example of a four layer stack up with two signal layers and two power planes The two power planes are the power layer and the ground layer The layer sequence as component ground power solder is the most common stack up arrangement from top to bottom Table 4 1 Recommended Four Layer Stack Up Dimensions shows an example of general dielectric thickness with proper routing trace width spacing for impedance control Thickness 62 mils Core L3 Power Layer Figure 4 1 Four Layer Stack up Table 4 1 Recommended Four Layer Stack Up Dimensions Layer Dielectric Signal End Signals Differential Signals Differential Signals No Thickness Width Space Impedance Width Space Impedance Width Space Impedance yp mil mil Q mil Q mil Q 55 10 90 109 5 10 100 10 BS ee eee a 12 Ground 12 TT 1476 T T T t3 Power 1 2 0 0 1 14 Notes Target PCB Thickness total 62 mils 0 062 inches 10 73 Advantech COM Express Carrier Board Design Guide Addendum 4 1 2 Six layer board stack up Figure 4 2 illustrates an example of a six layer stack up with 4 signal layers and 2 power planes The two power planes are the power layer and the ground layer The
58. layer sequence of component ground IN1 IN2 power solder is the most common stack up arrangement from top to bottom Table 4 2 shows an example of general dielectric thickness with proper routing trace width spacing for impedance control Prepreg 4 4 CN Core L3 IN1 _ 3 Total Prepreg Thickness 62 mils L4 IN2 L5 Power Layer Prepre Figure 4 2 Six Layer Stack up Table 4 2 Recommended Six Layer Stack Up Dimensions Layer Dielectric Differential Signals T Thickness Width Space Impedance Width Space Impedance Width Space Impedance ype mil mil Q mil Q mil 100 10 4 _ T Pepeg 38 o q T 0 coe J4 2 WERDE t5 Power 12 Prepreg 4 0121 14414 22 Notes The general PCB thickness total 62 mils 0 062 inches 10 74 Advantech COM Express Carrier Board Design Guide Addendum 4 2 Alternate Stack Ups While the different stack ups are needed number of layers thickness trace width etc the following key points should be noted 1 2 Final post lamination post etching and post plating dimensions should be used for electrical model extractions All high speed signals should reference solid ground planes through the length of their routing and should not cross plane splits To guarantee this both planes surrounding strip lines sh
59. m a cost effectiveness point of view the four layer board is the target platform for the motherboard design For better quality the six layer or 8 layer board is preferred 4 1 Nominal Board Stack Up The trace impedance typically noted 55 10 is the nominal trace impedance for a 5 mil wide external trace and a 5 mil wide internal trace However some stack ups may lead to narrower or wider traces on internal or external layers in order to meet the 55 O impedance target that is the impedance of the trace when not subjected to the fields created by changing current in neighboring traces Note the trace impedance target assumes that the trace is not subjected to the EMI fields created by changing current in neighboring traces It is important to consider the minimum and maximum impedance of a trace based on the switching of neighboring traces when calculating flight times Using wider spaces between the traces can minimize this trace to trace coupling In addition these wider spaces reduce settling time Coupling between two traces is a function of the coupled length the distance separating the traces the signal edge rate and the degree of mutual capacitance and inductance In order to minimize the effects of trace to trace coupling the routing guidelines in this section should be followed Also all high speed impedance controlled signals should have continuous GND referenced planes and cannot be routed over or under power GND p
60. m is in Suspend to RAM state Active low output SUS_S4 o Indicates system is in Suspend to Disk state Active low output Indicates system is in Soft Off state Also known as PS ON pne and be used to control ATX power supply WAKEO PCI Express wake up signal General purpose wake up signals May be used to Implement WAREN wake up on PS2 keyboard or mouse activity A27 BATLOW Indicates that external battery is low Input from off module temp sensor indicating an over temp Tave Active low output indicating that the CPU has entered thermal THRMTRIP shutdown 2 13 1 Power Good Reset Input The COM Express Power PWR_OK input signal could be connected to an external power good circuit or used as a manual reset input by grounding the pin with a momentary contact push button switch If an external circuit asserts this signal it should be driven by an open drain driver and held low for a minimum of 15ms to initiate a reset The Figure 2 57 shows the application Use of this power input is optional The COM Express Module generates its own power on reset based on the internal monitor on the main input voltage and or the internal power supply 62 Advantech COM Express Carrier Board Design Guide Addendum COM Express PWR OK 5 or 3 3V 74 08 Power Good 4 7K 0 1u Reset Button Carrier board ATX Power or Power Circui
61. mit Pairs 16 through 31 These are same line as PEG_TX 0 15 and PCI Express Differential Receive Pairs 16 through 31 These are same line as 0 15 and Reference clock output for all PCI Express Graphics lanes EH E EH PCI Express wakeup signal Pm Signal PEG TX 0 15 PEG TX 0 15 PEG RX 0 15 RX 0 15 Ej PEG Description PCI Express Graphics Transmit Differential Pairs 0 through 15 Some of these are multiplexed with SDVO lines PCI Express Graphics Receive Differential Pairs 0 through 15 Some of these are multiplexed with SDVO lines PCI Express Graphics lane reversal input strap Pull low on the carrier board to reverse lane order Be aware that the SDVO lines that share this interface do not necessarily reverse order if this s strap is low Strap to enable PCI Express x16 external graphics interface Pull low to disable internal graphics and enable the x16 interface EXCD 0 1 CPPE PCI ExpressCard PCI Express capable card request active low one per card A48 47 EXCD 0 1 _RST PCI ExpressCard reset active low one card 31 Advantech COM Express Carrier Board Design Guide Addendum 2 5 2 Schematic Guidelines 2 5 2 1 PCI Express AC Coupling Capacitor Each PCI Express lane is AC coupled between its corresponding transmitter TX and receiver RX Figure 2 26 and Figure 2 27 shows the connec
62. mption to 25 watts from all power rails The system provides a total power budget for add in cards that can be distributed between connectors in an arbitrary way as Table 2 25 The PRSNTn pins on the connector allow the system to optionally assess the power demand of each add in card and determine if the installed configuration will run within the total power budget Table 2 25 PCI Add in Card Maximum Loading Current via Each Power Rail Power Rail Add in card 3 3 V 0 3 V 7 6 A Max System dependent 5 5 5 A Max System dependent 12 V 5 500 12 V 5 100 mA Max 2 7 4 6 COM Express PCI interface supply voltage The COM Express PCI interface is a 3 3V signaling environment with 5V tolerance for I O signals If a universal PCI connector is used at the carrier board a jumper design to select Vio for 5V and 3 3V is necessary Otherwise a suitable Vio voltage should be designed for the 5V or 3 3V connector Table 2 26 Add in Card Supplied Power Selection Symbol 3 3 V Connector 5 V Connector Universal Connector Jumper select Note 1 Note the riser card supply voltage and do not plug it into the wrong supply voltage If a universal connector is used make sure the Vio jumper setting is correct when plugged into the riser card 2 Advantech s demo carrier board provides a 5V connector and 5V Vio for PCI slots Plugging a 3 3 V riser card in the wrong direction will damage the carrier board or riser ca
63. nes This section shows the summary of the layout routing guidelines 2 5 3 1 Differential pairs The PCI Express signals should be routed as differential pairs The following is a summary of general routing guidelines for the differential pair traces In COM Express platforms the PCI Express differential trace impendence target is 100 2096 It is important to equalize the total length of the traces in the pair throughout the trace each segment of trace length should be equal along the entire length of the pair Figure 2 30 shows an example La must equal to La Lg must equal to Lg and so on It is preferable to route TX and RX differential pairs alternately on the same layer TX pair next to RX pair rather than another TX pair Tight coupling within the differential pair and increased spacing to other differential pairs helps to minimize EMI and crosstalk It is important to maintain routing symmetry between the two signals of a differential pair TX E LC LA 8 i RX LC RX ll T Stool te 5 Figure 2 30 Trace Length Matching Each Segment 35 Advantech COM Express Carrier Board Design Guide Addendum 2 5 3 2 Board Stack up Considerations Table 2 16 shows the PCI Express trace width and spacing for Micro st
64. om COM Express Module The RESET is the general reset for LPC PCIE or other devices if PCI and IDE is not used as the COM Express Type 1 2 14 Miscellaneous 2 14 1 Miscellaneous Signal Descriptions Table 2 41 Miscellaneous signal descriptions SPKR 26 CK B34 2 DAT o OD sourced through 3 3 V standby B32 B33 Module Please connect this signal to the speaker General purpose 2 port data I O line System Management Bus bidirectional data line Power sourced through 3 3 V standby System Management Bus Alert active low input can be used to generate a SMI System Management Interrupt or to wake the system Power sourced through 3 3V standby rail Module BIOS disable input Pull low to disable module BIOS Input to module from optional external keyboard controller that A86 KBD_RST can force a reset Pulled high on the module This is a legacy artifact of the PC AT Input to module from optional external keyboard controller that 87 KBD A20GATE can be used to control the CPU A20 gate line The A20GATE restricts memory access to the bottom megabyte and is a legacy artifact of the PC AT Pulled high on the module B27 Output indicating that a watchdog time out event has occurred B13 B B14 SMB DAT 15 B 2 14 2 SPKR The SPKR output from the COM Express Module is a CMOS level signal It can control an external FET o
65. ould be GND High speed signal routing should be done on internal strip line layers High speed routing on external layers should be minimized to avoid EMI Routing on external layers also introduces different delays compared to internal layers This makes it extremely difficult to do length matching if routing is done on both internal and external layers Two layer board stack up has poor EMI shielding and ESD protection characteristics so it is not recommended to be designed in 4 3 Differential Impedance Targets for Trace Routing Table 4 3 shows the target impedance of the differential signals The carrier board should follow the required impedance in this table Table 4 3 Differential Signals Impedance Requirement Signal Type GBE LAN 100 2096 LVDS 100 20 PCI Express 100 2096 SATA 100 2096 SDVO 100 20 30 n 209 For the basic routing rules please refer to the PICMG Carrier Design Guide 75 Advantech COM Express Carrier Board Design Guide Addendum Chapter 5 Mechanical Schematic Guidelines 5 1 COM Express Mechanical Dimensions The PCB size of the COM Express Modules are 125mm x 95mm for COM Express Basic Modules 95mm x 95mm for COM Micro Modules and 84mm x 55mm for COM Ultra Modules The PCB thickness is designed at 2 0mm to allow high layer stack ups and facilitate a standard z dimension between the Carrier Board and the top of the heat spreader The holes shown in t
66. p To mini PCI SIDESURR R LINE2 R RIO 48 siDESURR R UNEZ R H LINE R 29 LINE2 L 4 10K yy R2 41 sPDIFUEAPD unez H4 esse et E SenseA d 48 sePDIFO 5 Sense A 13 124 0 54K yy R127 FRONT JD 5 E 10 R125 LINE1JD B8eges BeBe bg 20K yy R128 MIC1 JD 6606488453852 8 1 ad od J J 1 39 2K 129 SURR JD VCC3 3V JP VDD3 3 128 TiP8008 OU RST 329 C20 22 100 12 SYNC 329 LD c97_SDINO 329 1122 c BITCLK 329 La acg7_spouT 3 29 MIC1 VREFO R CENTER LFE MIC1 VREFO L AUDIO CN12E c98 tu cot R106 R107 SURR R SURE R 115 1181028 SURR R2 EX 47K 4 7K FRONT_OUT AUDIO C100 tu SURR JP R105 E E2 CN12C SURR L L17 441181025 ROLA c97 tu 2 MIC1 R 1 1 L14 11810285 MICT RZ Ca C3 C103 c10 coo tu MIC1 JD C2 100p 100 MICT L MC141 L16 1181025 MICTIZ 100 100 SURROUND IN AUDIO AUDIO CN12D C109 tu cot C108 100uF 6 3V TC B 2 LFE LFE1 119 MM 11B1028 LFE2 04 FRONTR 1 4 2 FRONTR1 118 441181025 FRONT R2 B4 D3 TV X LB TV cit tu CEN JD D2 C110 100uF 6 3V TC B FRONT JD B2 CEN 1 121 pp 1181023 Di FRONTL 1 4 2 FRONT L1 120 1181025 FRONTA B1 N V cna cu 112 cn 100p 100p 100 LINE1 VREFO R LINE1 VREFO L R120 4 7K 4 7K GND SIDESURR LINE1_IN AUDIO AUDIO CN12F CN12A 117 tu cot
67. partitioned ground power plane Lower frequency I O ports may be bypassed with high frequency capacitors located near the connectors Trace routing on the PCB must be controlled to avoid coupling RF currents into the cable 60 Advantech COM Express Carrier Board Design Guide Addendum shield A clean ground must be located at the point where cables leave the system Both power and ground planes must be treated equally as these planes act as a path for RF return currents To implement a clean ground use of a partition or moat is required The clean area should be 1 100 isolated with signals entering and exiting via an isolation transformer or an optical device 2 Data line filtered 3 Filtered through a high impedance common mode inductor choke or protected by a ferrite bead on lead component 2 12 4 5 ESD Protection The PCB should be against the electro static discharge ESD events which might enter I O signal and electrical connection points In order to prevent component or system failures due to external ESD impulses that may be propagated through both radiated and conducted mechanisms For ESD protection that may be implemented on a PC for high level pulse suppression include the following components 1 High voltage disc ceramic capacitors must be rated at 1KV minimum Lower voltage capacitors may be damaged by the first occurrence of an ESD pulse This capacitor must be located adjacent to the I O connector 2 TVS
68. r I O If there is without Super I O to output the PS_ON signal to ATX power switch the SLP_S3 or SLP_S5 can be used to control the PS_ON through a switch as Figure 3 2 shows Pull up is not necessary if PS_ON connects to ATX power pin 16 directly 1uF NL 6 3V Reserved for Power Sequence adjustment Figure 3 2 power circuits for ATX power supply w o SIO If the system supports S3 operation the SLP_S3 should be used If S3 function is not needed the SLP_S5 should be used to control the PS by changing the resistor to connect SLP_S5 and to disconnect SLP_S3 in Figure 3 2 69 Advantech COM Express Carrier Board Design Guide Addendum 3 1 4 AT Power Delivery Block Diagram An AT power source can provide 12 V supply to the COM Express module or the battery may provide a wide range of power An additional switching regulator or LDO will be required to simulate the ATX power 5V 3 3V There will be no standby voltage when an AT power source is used as Figure 3 2 12V COM Express AT Power Source 3 3V 12V Switching regulator or LDO POWER OUT Figure 3 3 AT Power Delivery Block Diagram 70 Advantech COM Express Carrier Board Design Guide Addendum 3 1 5 AT Power Working as ATX Mode An AT power source generally provides 12V but without 5VSB standby power If the application is working in ATX mode using AT power there is a way to
69. r PCB 78 Chapter 1 Introduction Advantech COM Express Carrier Board Design Guide Addendum Chapter 1 Introduction This design guide addendum organizes and provides Advantech s COM carrier board design recommendations for COM Express Modules other Schematic Guidelines for the carrier board are applicable and can be found in the PICMG Design Guide V1 0 Please contact Advantech sales application engineer if there are any questions about designing the carrier board or you plan to use this processor in applications other than mobile or desktop platforms 1 4 COM Express Overview COM Express complies with COM Express standard from the PCI Industrial Computer Manufacturers Group PICMG which provides next generation performance of the smallest state of the art embedded modules Advantech s COM Design Support Services CDSS help customers develop and integrate their carrier board with Advantech s COM modules CDSS provides a series of valuable services such as Product Design Assistance Software and Thermal Solution services together they help reduce design risks when designing carrier boards For more details please visit http com advantech com Advantech offers a wide range of COM products to cater to each customer s demands The modular designs add more flexibility to the system The COM Express form factor allows the COM Express Modules to be easily and securel
70. r each TV DAC channel output signal This video filter is to be placed close to the TV connector The separation between each of the 3 video filters for the TV DAC channels should be far than a minimum of 50 mils or greater to minimize crosstalk This is especially important for the TVDAC B and TVDAC C channels S video signals Figure 2 50 shows the TV DAC Video Filter TV DAC Filter Input Figure 2 50 TV DAC Video Filter The video filter is designed for a cutoff frequency of at least 30 MHz and a gain of 3 dB Table 2 38 shows the TV DAC Video Filter component 56 Advantech COM Express Carrier Board Design Guide Addendum Table 2 38 TV DAC Video filter components 20 Ceramic 20 Ceramic 15000 4 2 11 3 Layout Guidelines 2 11 3 1 TV DAC routing The minimum spacing between each TV DAC signal is 40 mils but 50 mils is preferred A maximum amount of spacing should be used between each TV DAC signal as well as to all other toggling signals This helps prevent crosstalk between the TV DAC signals and other signals The routing for each TV DAC signal should also be matched and balanced All TV DAC signals should be routed on the same layer have a similar number of bends the same number of vias etc All routing should be done with ground referencing as well Figure 5 37 shows the TV DAC routing topology Total length of each signal should be less than 12 inches Intra pair length difference should be less th
71. r logic gate that drives an external PC speaker The SPKR output should NOT be directly connected to either a pulled up or a pulled down resistor The SPKR signal is often used as a configuration strapping for the chipset on the COM Express Modules A pulled up or pulled down resistor on SPKR may override the internal strapping on the module and result in malfunction 64 Advantech COM Express Carrier Board Design Guide Addendum 0035 1144148 R184 D 33 SPEAKER PT 9027 50 C180 T R183 SPKR C MW 2 Figure 2 58 Speaker Schematics 2 14 3 12 Bus Carrier board COM Express I2C CK I2C DAT gt N OURA 12C Figure 2 59 12 Bus Connections Most COM Express Modules provide a software driven I2C port for communication with external I2C slave devices The Vcc is 3 3V main power 2 14 3 1 DC Specifications Table 2 42 12 Voltage Symbol Parameter Min Max Vit Input Low 0 5 0 3Vcc Voltage Unt Note Yooo Input High 0 7Vcc 0 5 V Voltage VoL Output Low 0 4 V Voltage 1 The I2C Bus Specification V2 1 2 Vcc is the voltage which the pulled up resistor are connected 65 Advantech COM Express Carrier Board Design Guide Addendum 2 14 4 12C Spec Please refer to THE 2C BUS SPECIFICATION VERSION 2 1 JANUARY 2000 for the DAC AC Characteristics 2 14 5 SMBus Most COM Expr
72. rd 2 7 5 Layout Guidelines The following represents a summary of the routing guidelines for PCI devices Simulations assume that PCI cards follow the PCI Local Bus Specification Revision 2 3 trace length guidelines 2 7 5 1 PCI Bus Layout Example with IDSEL The following guidelines apply to platforms with nominal impedances of 55 10 Advantech COM Express Carrier Board Design Guide Addendum PCI AD Bus should be routed as daisy chain to PCI expansion slots 0 1 2 3 R IDSEL R IDSEL R_IDSEL R_IDSEL WI w2 wl w2 WI 2 WI w2 COM Express Connector L1 L2 L3 14 AD BUS AD BUS AD BUS ET AD BUS LESE PCI AD Bus should be routed as daisy chain to PCI expansion slots Figure 2 39 PCI Bus Layout Example with IDSEL Table 2 27 PCI Data Signals Routing Summary Trace PCI Routing Requirements Topology Maximum Trace Length Impedance unit inch ae t3 Ju 2 Slots 10 1 0 W12W2 70 5 550 5 mils width 5 mils spacing based inches 1096 on stack up assumptions R IDSEL 300 to 900 3 Slots 10 1 0 1 0 W1 2 0 5 inches R IDSEL 300 to 900 4 Slots 10 1 1 11 1 1 W1 2 0 5 inches R IDSEL 300 to 900 45 Advantech COM Express Carrier Board Design Guide Addendum 2 7 5 2 PCI Clock Layout Example COM Carrier E
73. re 2 3 Gigabit Ethernet Connections with Integrated Magnetic 13 Figure 2 4 Differential signals route example eese 14 Figure 2 5 Bend layout example enne nnne then nnn 15 Figure 2 6 10 100M Ethernet 15 Figure 2 7 Gigabit Ethernet Interconnection 16 Figure 2 8 cma ARM 17 Figure 2 9 Audio GOnfgellofis iii eoo Ina oneri 19 Figure 2 10 HD Audio Connections 20 Figure 2 11 Jack Detection with sensing 20 Figure 2 12 Reference Audio Schematic eese 21 Figure 2 13 HD Audio SDIN 22 Figure 2 14 HD Audio SDOUT AC SYNC AC BITCLK AC Topology uu III LM E 23 Figure 2 15 HD Audio AC_SDOUT AC_SYNC AC_BITCLK AC_RST Topology THEE T CC ME TU 24 Figure 2 16 AC 97 Audio Ground 24 Figure 2 17 SATA interconnection example 0 25 Figure 2 18 SATA Schematic 4 2 221 25 Figure 2 19 SATA LED Schematic
74. rface please refer to the PCI spec 2 7 1 Signal Description Table 2 19 shows the COM Express PCI bus signals Table 2 19 PCI Signal Description sonst o omen OSSO PCI PCI_CLK E PCI 33 MHz clock output PCI_CLKRUN 22 019 17520 PCLREQIO 3 20 18 PCI GNTIO 3 PCI_AD 0 31 026 33 PCI Bus Command and Byte Enables Bus command and byte PCI C BE O 3 enables are multiplexed in these lines for address and data C38 C44 phases respectively D D Bidirectional pin used to support PCI clock run protocol for mobile systems Bus Request signals for up to 4 external bus mastering PCI devices When asserted a PCI device is requesting PCI bus 4 ownership from the arbiter PCI master has been granted ownership of the PCI bus PCI Address and Data Bus Lines These lines carry the address o gt PCI PAR Parity bit for the PCI bus System Error Asserted for hardware error conditions such as parity errors detected DRAM PCI PERRA Parity Error For PCI operation per exception granted by PCI 2 1 Specification Power management event D i PCI_LOCK 10 Lock Resource Signal This pin indicates that either the PCI master or the bridge intends to run exclusive transfers D D C C15 Device Select active low When the target device has decoded PCI TRDY amp Target Ready This pin indicates that the ta
75. rget is ready to complete the current data phase of a transaction Initiator Ready This signal indicates that the initiator is ready to complete the current data phase of a transaction master stop the current transaction duration of a PCI access PCI PCI Bus Reset This is an output signal to reset the entire PCI puo um Module input signal indicates whether an off module PCI device is capable of 66 MHz operation Pulled to GND by Carrier Board device or by Slot Card if the devices are NOT capable of 66 MHz operation D49 PCI M66EN If the module is not capable of supporting 66 MHz PCI operation this input may be a no connect on the module If the module is capable of supporting 66 MHz PCI operation and if this input is held low by the Carrier Board the module PCI interface shall operate at 33 MHz 39 C C C 0 8 3 5 6 D35 7 D D36 3 5 32 3 34 3 3 3 3 34 3 2 C Advantech COM Express Carrier Board Design Guide Addendum 2 7 2 DC Specifications Table 2 20 DC specifications for 5V signaling of PCI Bus Symbol Parameter Mi max amutowvotae os os Vo cutputtighvotage 24 outputtowvotiage oss Table 2 21 DC specifications for 3 3V signaling of PCI Bus Symbol Parameter Min Supply Voltage T Ve inputPurupvotage OupuHgnVota Vo cutputtowvotage 1 This specification
76. ries Signal Impedance length Termination Length Resistance Matching 55 5 on 7 stripline 11 14 11 R12 33 596 N A 15 5 on 7 microstrip L2 0 5 R2 39 5 L3 1 15 R32 39 5 L4 1 5 5 lt 0 5 L6 5 Figure 2 15 and Table 2 8 show the layout topology 2 of AC SDOUT AC SYNC AC BITCLK and RST signals Carrier board L3 Audio Codec down Bi L2 e L8 _L2 L4 2 L5 Codec R4 R2 ape L2 L4 L6 2 17 Audio z R3 o Deck 23 Advantech COM Express Carrier Board Design Guide Addendum Figure 2 15 HD Audio AC_SDOUT AC_SYNC AC_BITCLK AC_RST Topology 2 Trace HD Audio Requirements Trace Series Signal Impedance length Termination Length Resistance Matching 550 5 on 7 stripline N A 15 5 on 7 microstrip Generally the trace length on the COM Express Module is around 5 inches The total trace length on the carrier board should be less than 15 inches Please refer to the Advantech layout checklist for details 2 2 5 4 Grounding Techniques Take care the grounding of the audio jacks especially the line in and microphone jacks Avoid grounding the audio jacks to the ground plane directly under the connectors Otherwise the potential of audio noise voltage will be induced into
77. rip and Strip line based on the six layer board stack up Keep the required trace impedance for better signal integrity Table 2 16 PCI Express Trace Width and Spacing for Micro strip and Strip line Trace Differential Adjacent Differential Breakout Nominal Width Pair Trace Pair Pair Length Guideline Trace Spacing Trace Matching Impedance Spacing Zo Micro 5 mils 10 mils 20 mils 5 mils 5 mil trace width 100 0 20 strip 10mil separation to Differential both the differential pair signals and adjacent traces for up to 250 mils Strip 5 mils 10 mils 20 mils 5 mils Only 5 mil trace width 100 0 20 line on 10 mils spacing is Differential allowed 2 5 3 3 PCI Express Topology 1 Device Down Routing Guidelines The device down topology as Figure 2 31 allows a maximum traces length of 15 inches from COM Express Module to the down device The max length takes into account all routing including the breakout region which should not exceed 0 25 inches per device The routing rules are shown in Table 2 17 COM Express TX Li PCI RX Express Device RX L3 L2 TX Figure 2 31 Topology 1 COM Express to PCI Express Device Down Table 2 17 COM Express to PCI Express D L1 L2 L3 Capacitor Value Max 15 inches Min 0 25 inches Max 15 inches L2 75 nF to 200 nF Max 14 75 inches Tolerance 20 The TX and RX pairs can be routed interleaved
78. riptions Table 2 1 shows COM Express Ethernet signals including pin number signal naming I O and descriptions Table 2 1 GBE signals 940 13 9 7 GBEO MDI 0 3 Gigabit Ethernet Controller 0 Media Dependent Interface A12 A10 A6 A2 GBEO MDI 0 3 Differential Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10 Mbit sec modes Some pairs are unused in some mode per the following 1000BASE T 100BASE TX 10 MDI O B1_DA TX TX MDI 1 B1_DB RX RX MDI 2 B1_DC MDI 3 B1_DD GBEO ACT Gigabit Ethernet Controller O activity indicator active low GBEO_LINK Gigabit Ethernet Controller 0 link indicator active low OD OD A4 GBEO_LINK100 Gigabit Ethernet Controller 0 100 Mbit sec link indictor EE active low A14 GBEO CTREF REF Reference voltage for Carrier board Ethernet channel 0 magnetics center tap The reference voltage is determined by the requirements of the module PHY and may be as low as 0 V and as high as 3 3 V The reference voltage output shall be current limited on the module In the case in which the reference is shorted to ground the current shall be limited to 250 mA or less 2 1 2 DC Specifications Table 2 2 Voltage Symbol Input Low Voltage 2 Note 1 Vcc is 3 3V from 3 0V min to 3 6V max 11 Advantech COM Express Carrier Board Design Gui
79. s 16 DT2 DT2 GND ale He SHIELD_GND SHIELD_GND 90 10 2 0 1 2 1 50 50V Figure 2 41 USB Connections 2 8 41 Low ESR Capacitor The hot plug function is one of the popular features of the USB devices The design of the USB power decoupling circuits must absorb the momentary current surge from hot plugging an unpowered device Reducing the capacity of decoupling capacitors is not recommended These USB power capacitors should be selected as low ESR and low inductance 2 8 4 2 ESD or EMI suppression components Additional ESD or EMI suppression components could be implemented on the USB data lines It s important to place the ESD and EMI components near the external USB connector and make it grounded by the low impedance ground plane The common mode choke is recommended to be used for USB2 0 EMI consideration Figure 2 42 shows the schematic of a typical common mode choke and ESD suppression component which are placed as close as possible to the USB connector signal pins Common Mode Choke mm 77 USB A Connector PulseGuard Components Figure 2 42 Common Mode Choke and ESD suppression design The ESD components are generally needed for ESD testing The common mode chocks are generally adopted for USB 2 0 interface 2 8 4 3 Over Current Protection The Over current protection on the external USB power lines is required to prevent the power faults from external USB devices or ca
80. so connected between master and slave devices The reference schematic is as Figure 2 22 PRIMARY IDE COMPACT FLASH DISK TYPE faster Master Slave PRIMARY IDEN x Figure 2 22 IDE Master Slave DASP S Signals Connection 28 Advantech COM Express Carrier Board Design Guide Addendum 2 4 4 2 UDMA Support COM Express Modules support UDMA ATA 33 66 100 data transfer modes If an advanced IDE data transfer mode such as UDMA 66 100 is required the 80 pin type IDE connector and cable are needed for signal integrity Total Max Length 7 inches a IDE cable COM HDD Express IDE bus Carrier Board Figure 2 23 IDE Bus Trace Length on Carrier Board 2 4 4 3 IDE interface connections All necessary pulled up down resistors are implemented on the COM Express Module Do not implement these resistors on the carrier board If there is no IDE device all IDE pins should be left as NC Not Connected HDD20x2 254D HORST R PIDE DAR OPE DIR MEL PIDE 08 PIDE D R C pqmnE ps PIDE_09 R PIDE_DS R TET PIDE_D10 R PIDED 4R O pp ene THETA PIDE_D11 R PIDE D3 R PIDE D12 R 02 8 O mpE pr PIDE D13 R PIDE Di R O sne ter PIDE D14 R PIDE D R C PIDE D15 R PIDE DRO R 211 TNI MEINER alt Resistor on Master PIDECIOR R 25 IDE R71 p i PIDE RDY R s PIDE Com I
81. t Figure 2 57 Power Good Reset Input Applications 2 13 2 Reset signals There are reset signals with inputs and outputs functions listed in the Table 2 40 Reset Signals Table 2 40 Reset Signals Pin Name Pin Pin Type Description Where Use Remark Reset button input Active low input System is held in svs 49 93VSB hardware reset while this From Reset Button to CMOS Module input is low and comes out of reset upon release Input to module from optional external Not Connected 1 3 3V keyboard controller that can if KBC is not KBD RST A86 CMOS force a reset Pulled high Keyboard Controller KBC implemented on the module This is a on the carrier legacy artifact of the PC board AT O 3 3V Reset output from module CB RESET B50 CMOS to Carrier Board active low LPC PCIE CPLD others 3 3 5V PCI Reset output active PCI RESET C23 tolerance low PCI CMOS IDE RESET D18 O 3 3V Reset output to IDE device IDE CF CMOS active low O 3 3V PCI ExpressCard slot 1 EXCDO_PERST A48 CMOS reset active low Express Card O 3 3V PCI ExpressCard slot 2 EXCD1_PERST 47 CMOS reset active low Express Card The reset signals input to COM Express Module as SYS_RESET and KBD RST can be Not Connected if not used 63 Advantech COM Express Carrier Board Design Guide Addendum Be sure to use the corresponding reset output fr
82. the differential traces or closer than 50 mils to the differential traces Figure 2 4 shows an example It s recommended to keep length L3 longer than 50 mils Keep separate traces within a differential pair as small as possible down to 5 to 8 Mils depending on the impedance control Close separation of the traces allow the traces to couple well to each other For high speed signals they should minimize the number of corners and vias If a 90 bend is required it is recommended to use two 45 bends instead Figure 2 5 shows the example COMExpress Carrier board On board LAN chip Transformer 4 RJ45 Differential Pairs Figure 2 4 Differential signals route example Advantech COM Express Carrier Board Design Guide Addendum Figure 2 5 Bend layout example 2 1 4 2 Transformer It s recommended to use the integrated Magnetic Modules RJ 45 LAN connectors If using the discrete Magnetic Modules and RJ 45 connector the transformer should be placed close to the RJ 45 LAN connector to reduce EMI emissions Each differential pair of data signals is required to be parallel to each other with the same trace length on the component top layer and to be parallel to a respective ground plane The connector with integrated magnetic is much simplified for layout The more complex layout as Figure 2 6 and Figure 2 7 shows the 10 100M and Gigabit Ethernet layout with discrete magnetic C
83. tion for COM Express signals and PCI Express connector The AC coupling capacitors of is present on COM Express Module The AC coupling capacitors of RX should be placed on the carrier board and closely to the transmitter pins of the PCI Express devices COM Express RX TX RX Express RX TX Add in RX TX Device ICH PCI TX RX Express RX TX Add in RX TX Device Figure 2 26 PCI Express Interconnect Example 1 B2 12V PRSNT1 lt B2 A2 12V 12V 3 9veazv RSVD 12v 5 GND GND SMB CI SME DAT SMCLK sTAG2 Fae SMB DAT lt SMDAT JTAG3 Fa GND JTAG4 gt VCC3 3V2 3 3V JYAG5 x JTAG1 3 3V jp evee sv VCCSB3 3VO 3 3VAUX 33v 10 PCIE WAKE lt WAKE PWRGD CB RESET RVSD GND 212 GND REFCLK 14 CLK_PCCIE_SLOP PCIE_TXOP D HSOPO REFCLK ags CCL _PCIE_SLON PCIE_TXON D HSONO GND Pate GND HSIPO 517 gt PCIE RX0P PRSNT2 HSINO ajg gt PCIE_RXON GND GND m PCI E 1X Figure 2 27 PCI Express Connector Schematic Reference Use the exact same package size for the capacitor on each signal in a differential pair Table 2 15 shows the PCI Express capacitor reference Table 2 15 PCI Express Capacitor Reference Length Matching Type Value Tolerance Placement Between Differential Pair Recommended to place As close as possible A
84. ue analog video output signals for CRT monitors designed to drive a 37 5 equivalent load Horizontal Sync This output supplies the horizontal synchronization VSACHSYNC pulse to the CRT monitor B94 VSYNC Vertical Sync This output supplies the vertical synchronization pulse to the CRT monitor B95 VGA I2C CK UO DDC clock line It can be used for a DDC interface between the graphics controller chip and the CRT monitor DDC data line It can be used for a DDC interface between the graphics controller chip and the CRT monitor 2 10 2 DC Specifications Table 2 35 Hsync and Vsync signals specification Symbol Input Low Voltage 20 Parameter Red analog video output signal 0 77 Max luminance voltage Green analog video output signal 0 665 0 77 V Max luminance voltage 77 Blue analog video output signal 0 665 0 V Max luminance voltage Red analog video output signal 0 Typical min luminance voltage Green analog video output signal O Typical min luminance voltage Blue analog video output signal 0 Typical min luminance voltage The HSYNC VSYNC are TTL signals RED GREEN BLUE are 0 7V peak to peak OV for black level 0 7V for full color intensity 53 Advantech COM Express Carrier Board Design Guide Addendum 2 10 3 Specifications Please refer to VESA and Industry Standards and Guidelines for Computer Display Monitor Timing Version 1 0 Revision
85. ure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 4 1 Figure 4 2 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Advantech COM Express Carrier Board Design Guide Addendum Architecture of LPC interface cccccccccccccecccceecceeeeeeeeeeeeeeeeeeeeeeeeees 58 Serial Bus 59 Keyboard and Mouse connection 22 222 11 2222 59 LPT Connection 60 Floppy eene tente 60 Power Good Reset Input 63 Speaker 5 65 2 Bus 65 SMB Bus 66 ATX Power Delivery Block Diagram eese 68 power circuits for ATX power supply w o 69 AT Power Delivery Block 70 ATX Working Model Based on AT Power Input Reference Schematics 71 Four Layer Stack up MIU 73 Six L yer Stak U Pernin nerit Mr 74 COM Express Module Board Mechanical Dimensions 76 COM Express Module Receptacle 77 COM Express Carrier Board Plug 8mm 78 COM Express Connecto
86. w Pin Count LPC Interface Specification for legacy I O has facilitated the industry s transition toward ISA less systems N D Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels TC LPC RIG RelTmeCok TMDS Transition Minimized Differential Signaling Television supports NTSC and PAL A universal asynchronous receiver transmitter that translates data UART between parallel and serial forms Universal Serial Bus Advantech COM Express Carrier Board Design Guide Addendum 1 3 Referenced Documents Table 1 2 Referenced Documents Document ACPI Advanced Configuration and Power http www acpi info Management Specification 5 AC 97 AUDIO p download intel com support motherboards desktop sb ac97 r23 APM Advanced Power http www microsoft com whac archive amp 12 mspx Management Specification COM Express Specification http Avww picmg org http standards ieee org getieee802 802 3 html http www pcisig com http www usb org home 10 Advantech COM Express Carrier Board Design Guide Addendum Chapter 2 Carrier Board Schematic Guidelines 2 1 Gigabit Ethernet GBE COM Express supports the IEEE802 3 network interface and flexible dynamically loadable EEPROM algorithm The network interface complies with the IEEE standard for 10BASE T 100BASE T and 1000BASE T Ethernet interfaces 2 1 1 Signal Desc
87. xpress board PCI slot 1 or Device 1 R1 W2 Clock PCI slot 2 Gan WA R2 8 or Device 2 AAA 5 m T ER E PCI slot 3 PCI or Device 3 COM ws PCI slot 4 Express 0 or Device On Board m 4 Chipset Figure 2 40 PCI Clock Layout Example Table 2 28 PCI Clock Signals Routing Summary Trace PCI Routing Requirements Topology Maximum trace Length Damping Impedance on Carrier Board Resistor 550 5 mils width 50 mils spacing 2 4 W3 15 inches 33 Q 10 based on stack up assumptions Devices R2 33 Q Note Clock skew between PCI slots devices should be less than 2 ns 33 MHz and 1 ns 66 MHz The recommended value of the clock trace tolerance of W3 a b c d is 5 inches Maximum 46 Advantech COM Express Carrier Board Design Guide Addendum 2 8 Universal Serial Bus USB The Universal Serial Bus USB provides a bi directional isochronous hot attachable Plug and Play serial interface for adding external peripheral devices such as game controllers communication devices and input devices on a single bus COM Express Modules provide up to eight USB 2 0 ports 2 8 1 Signal Description Table 2 29 shows COM Express USB signals including pin number signals 1 0 and descriptions Table 2 29 USB Signals Description USB 0 7 5 0 7 USB differential pairs channels 0 through 7 USB over current sense USB channels 0 and 1 A pull up for this
88. y mounted on a customized solution board The design and multiple processor choices eliminate CPU integration worries and allow fast application support for the most dynamic embedded needs Computer On Module Market Pro Customer Solution Board CPU Levels COMs are widely used modular CPU boards with high integration features COM Express supports a wide range of processor and chipsets They include technologies like PCI Express Serial ATA USB 2 0 etc Not only do COMs allow quick design they also provide the benefits of easy installation maintenance and upgrade ease Advantech COM Express Carrier Board Design Guide Addendum Though small in size COMs implement CPU architectures and basic common circuits Many system integrators find that Advantech COM solutions already cover around 80 of their feature requirements This makes COM products powerful time and cost savers 1 2 Terminology AC 97 Codec 97 Audio interface Microsoft Windows or MS DOS CPU CRT DVI DVO ESD PC cards supported both PCI Express FSB Advantech COM Express Carrier Board Design Guide Addendum Inter IC a two wire serial bus created by Philips IDE ATA Integrated Drive Electronics Advanced Technology Attachment An interrupt request signal where x stands for interrupts A B C and D LA A local area network LAN is a computer network covering a small physical area Liquid Crystal Display M R The Lo

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