Home

NI PXIe-6674T User Manual

1. Clock Gen Y Global Software Trigger Onboard Y Routing PXI_CLK10 PXIe_CLK100 OCXO or ClkGen is accomplished by setting the synchronization clock NI Sync Property Node to the desired clock source and then routing the synchronization clock as the source Route through the FPGA Route to PFI LVDS can be made through the FPGA when used as a trigger or through the PXIe DTARA network when used as a clock y xipuaddy suoyeooads NI PXle 6674T User Manual Frequency Measurement Maximum Measurable Frequency 006 200 MHz Reference Counter SOurce c cccccecessessesesseees PXIe_CIk100 Frequency Counter Sources All Trigger inputs plus Clock In and the OCXO Trigger Sync Clock Two independent synchronization clock zones Front Synchronization Clock for PFI Single Ended and PFI LVDS e Rear Synchronization Clock for PXI Star PXI Trigger and PXIe DStarB Synchronization clock sources oooonooninioninni PXI_CIk10 PXIe_Clk100 Clock In OCXO and Clock Generation Two division ratios can be specified in powers of 2 from 2 to 512 These ratios are used in all synchronization clock zones to divide down the selected full speed synchronization clock Physical Chassis require oococcccnnnononnnoconcnconononncononcnss One 3U PXI Express slot system timing slot Dimensions not including connectors 16cm x 10 cm 6 3 in x 3 9 in Front panel CONNECTOTS
2. oononcicnnninnnnnnononnoococencnns Stability vs temperature Tuning range ici ti Tuning DAC resolutiON oococnicnnonnnnnnnoninnnnnancnos Recommended calibration interval Maximum Phase Noise of the OCXO ESO ppb ESO ppb year lt 10 ppb peak to peak within 0 C to 55 C operating temperature range 1 5 ppm minimum E 2 ppm typical t 4 ppm max 16 bits 0 0625 ppb per step typical Offset Phase Noise 1 Hz 80 dBc Hz 10 Hz 120 dBc Hz 100 Hz 140 dBc Hz 1 kHz 145 dBc Hz 10 kHz 150 dBc Hz 1 After 72 hours of continuous operation A 4 ni com NI PXle 6674T User Manual Figure A 4 shows the phase noise on a representative module OCXO is routed to the ClkOut SMA measured in a NI PXIe 1082 chassis with low fan speed The integrated jitter from 10 Hz to 1 MHz is 507 fs rms Figure A 4 Phase Noise on a Representative Module with OCXO Routed to ClkOut SMA 80 85 4 90 4 95 4 100 4 105 4 110 5 115 4 120 125 4 130 135 4 140 1454 150 4 155 7 160 T T T T T T 1 10 100 1k 10k 100k 1M 2M Frequency Offset Hz dBc Hz 1 OCXO also driven to PXI_CLK10_IN National Instruments A 5 Appendix A Specifications Figure A 5 shows the phase noise on a representative module of PXI_CLK10 when OCXO is routed to PXI_CLK10_IN measured in a NI PXIe 1082 chassis with low fan speed Figure A 5 Phase Noise on a Repre
3. Chapter 3 Hardware Overview Table 3 3 Signal Descriptions Continued Signal Name Direction Description PXIe DSTARA Out The PXIe DSTARA lines connect the system timing to chassis module to each peripheral slot in a PXI Express chassis allowing the system timing module to distribute a clock signal to every slot PXIe_DSTARA uses differential LVPECL signaling and is capable of high speed clock distribution Refer to the PXIe DSTARA Network section for more information PXIe DSTARB Out The PXIe_DSTARB lines connect the system timing to chassis module to each peripheral slot in a PXI Express chassis allowing the system timing module to send out high speed triggers to every slot PXIe DSTARB uses differential LVDS signaling and is capable of sending out higher speed trigger signals PXIe_ DSTARC In The PXIe DSTARC lines connect each peripheral from slot in a PXI Express chassis to the system timing chassis module allowing the system timing module to receive high speed clock and trigger signals from every slot PXIe DSTARC uses differential LVDS signaling The remainder of this chapter describes how these signals are used acquired and generated by the NI PXIe 6674T hardware and explains how you can route the signals between various locations to synchronize multiple measurement devices and PXI chassis Generating and Routing Clocks The NI PXIe 6674T can generate two types of clock sign
4. The NI PXIe 6674T is shipped in an antistatic package to prevent electrostatic damage to the module Electrostatic discharge ESD can damage the module A Caution Never touch the exposed pins of connectors To avoid such damage in handling the module take the following precautions e Ground yourself using a grounding strap or by touching a grounded object Touch the antistatic package to a metal part of the computer chassis before removing the module from the package Remove the module from the package and inspect the module for loose components or any sign of damage Notify NI if the module appears damaged in any way Do not install a damaged module into the computer Store the NI PXIe 6674T in the antistatic envelope when not in use Software Programming Choices When programming the NI PXIe 6674T you can use NI application development environment ADE software such as LabVIEW or LabWindows CVI or you can use other ADEs such as Visual C C LabVIEW features interactive graphics a state of the art interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW LabWindows CVI is a complete ANSI C ADE that features an interactive user interface code generation tools and the LabWindows CVI Data Acquisition and Easy I O libraries Safety Information The following sect
5. asynchronous routing overview 3 24 sources and destinations 3 25 timing diagram 3 24 B block diagram NI PXIe 6674T functional overview 3 2 routing architecture 3 16 signal selection circuitry 3 17 C cable configuration 3 20 calibration additional information 4 1 factory calibration 4 1 OCXO frequency 4 1 PXI_CLK10 phase 4 1 CE compliance specifications A 27 changing the Active LED color tip 3 5 cleaning A 26 CLKIN connector description 3 5 location diagram 3 3 specifications A 2 CLKOUT connector description 3 5 location diagram 3 3 signal description table 3 6 Clock Generation circuitry 3 8 PFI synchronization clock 3 20 3 21 PXI_CLK10 and OCXO 3 9 PXI_TRIG PXI_STAR synchronization clock 3 22 signal description table 3 7 clock routing overview 3 8 color Access LED color explanation table 3 4 Active LED color explanation table 3 5 configuring the device Access LED 3 4 Active LED 3 5 overview 2 2 D destinations possible destinations table 3 18 A 23 documentation related documentation ix E electromagnetic compatibility A 27 environmental specifications A 25 equipment getting started 1 1 F factory calibration 4 1 front panel See also CLKIN connector connector descriptions 3 5 NI PXIe 6674T diagram 3 3 PFI 3 5 G generating a clock overview 3 8 getting started configuring the device 2 2 equipment 1 1 installing the hardware
6. at the connector with respect to the rising edge of PXI Clk10 at the backplane connector that it is synchronized to Refer to the Synchronous Routing section of Chapter 3 Hardware Overview for more information A 20 ni com Synchronized Trigger Setup and Hold Timing with Respect to PXI Clk10 NI PXle 6674T User Manual Table A 3 Synchronized Trigger Setup and Hold Timing With Respect to PXI_CIk10 Trigger Source Trigger Destination Setup Time Hold Timet Single Ended PFI Single Ended PFI 11 2 ns Typical 8 2 ns Typical 13 2 ns Max 1 1 ns Max Single Ended PFI LVDS PFI 11 2 ns Typical 8 5 ns Typical 13 5 ns Max 0 8 ns Max Single Ended PFI PXLT Trigger 11 3 ns Typical 7 5 ns Typical 14 2 ns Max 1 3 ns Max Single Ended PFI PXI Star 11 2 ns Typical 6 9 ns Typical 13 1 ns Max 2 0 ns Max Single Ended PFI PXIe DStarB 13 2 ns Typical 9 8 ns Typical 15 4 ns Max 0 4 ns Max LVDS PFI Single Ended PFI 0 6 ns Typical 0 4 ns Typical 4 0 ns Max 3 9 ns Max LVDS PFI LVDS PFI 0 3 ns Typical 1 2 ns Typical 4 3 ns Max 3 5 ns Max LVDS PFI PXI Trigger 0 2 ns Typical 1 1 ns Typical 3 6 ns Max 5 0 ns Max LVDS PFI PXI Star 0 1 ns Typical 1 4 ns Typical 3 7 ns Max 5 0 ns Max LVDS PFI PXIe DStarB 2 1 ns Typical 0 5 ns Typical 5 7 ns Max 2 6 ns Max PXI Trigger Single Ended PFI 11 ns Typical 9 5 ns Typical 17 5 ns Max 4 8 ns Max PXI Trigger LV
7. o PXI_CLK10 ven x 2M ey Sector Lo PXI_TRIG 7 CLKIN OCXO gt Clock Generation gt PXle CLK100 y gt ni com and PXle DSTARB lt 0 16 gt NI PXle 6674T User Manual Figure 3 5 provides a more detailed view of the Selection Circuitry referenced in Figure 3 4 Figure 3 5 Signal Selection Circuitry Diagram PFI lt 0 5 gt PXI_TRIG lt 0 7 gt PXI_STAR lt 0 16 gt PFI_LVDS lt 0 2 gt PXle DSTARB lt 0 16 gt SOURCE V vv vvovov Software Trigger GND gt DESTINATION a CLK gt CLK N oP CLOCKS CLK M gt SYNCHRONIZATION Determining Sources and Destinations All signal routing operations can be characterized by a source input and a destination In addition synchronous routing operations must also define a third signal known as the synchronization clock Refer to the Choosing the Type of Routing section for more information on synchronous versus asynchronous routing Table 3 9 summarizes the sources and destinations of the NI PXIe 6674T The destinations are listed in the horizontal heading row and the sources are listed in the column at the far left A Y in a cell indicates that the source and destination combination defined by that cell is a valid routing combination National Instruments 3 17 81 woJu Table 3 9 Sources and Destinations for NI PXle 6674T Signal R
8. Both PXIe_ DSTARB and PXIe_DSTARC are one directional The PXI Express Specification requires PXI Express chassis to limit the skew between any two PXIe_DSTAR routes to 150 ps National Instruments 3 23 Chapter 3 Hardware Overview The NI PXIe 6674T receives PXIe_DSTARC and can route it to both the PXIe DSTARA network for use as a clock source and to the FPGA for use as a trigger source The NI PXIe 6674T can independently select from the following sources to be routed to PXIe DSTARB e PFI lt O 5 gt PFI LVDS lt 0 2 gt PXI Triggers lt 0 7 gt PXI_TRIG lt 0 7 gt PXI Star Triggers PXI_STAR lt 0 16 gt PXIe DSTARC lt O 16 gt e Global Software Trigger Steady logic high or low e Backplane synchronization clock Refer to the Using the PXI Triggers section for more information on the backplane synchronization clock Choosing the Type of Routing The NI PXIe 6674T routes signals in one of two ways asynchronously or synchronously The following sections describe the two routing types and the considerations for choosing each type Asynchronous Routing Asynchronous routing is the most straightforward method of routing signals Any asynchronous route can be defined in terms of two signal locations a source and a destination A digital pulse or train comes in on the source and is propagated to the destination When the source signal goes from low to high this rising edge is transferred to the destination a
9. THE REMEDIES SET FORTH ABOVE ARE EXCLUSIVE AND THE CUSTOMER S SOLE REMEDIES AND SHALL APPLY EVEN IF SUCH REMEDIES FAIL OF THEIR ESSENTIAL PURPOSE EXCEPT AS EXPRESSLY SET FORTH HEREIN PRODUCTS ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND AND NI DISCLAIMS ALL WARRANTIES EXPRESSED OR IMPLIED WITH RESPECT TO THE PRODUCTS INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING THE USE OF OR THE RESULTS OF THE USE OF THE PRODUCTS IN TERMS OF CORRECTNESS ACCURACY RELIABILITY OR OTHERWISE NI DOES NOT WARRANT THAT THE OPERATION OF THE PRODUCTS WILL BE UNINTERRUPTED OR ERROR FREE In the event that you and NI have a separate signed written agreement with warranty terms covering the products then the warranty terms in the separate agreement shall control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation National Instruments respects the intellectual property of others and we ask our users to do the same NI software is protected by copyright and other intellectual property laws
10. 5 ns Figure A 13 Representative LVDS Output Operating at 100 MHz Differential Signal V gt gt Unit intervals 01 00 01 02 03 04 05 06 07 08 09 10 11 12 O National Instruments A 17 Appendix A Specifications Figure A 14 shows the representative LVDS output operating at 1 GHz 1 unit interval in the figure equals 500 ps Figure A 14 Representative LVDS output operating at 1 GHz SS 04 0 1 Differential Signal V O 02 0100 01 02 03 04 05 06 07 08 09 10 11 12 Unit Intervals PXI Triggers VO Voltage Level snesesseesreisrisiscsracasorek 3 3 V CMOS 5 V input tolerant PXI Star VO Voltage Ley llercian 3 3 V CMOS 5 V input tolerant PXle DStarB The PXIe DStarB signals are LVDS signals that allow the NI PXIe 6674T to route high speed trigger signals to any other PXIe slot ina chassis Each PXI Express slot in a chassis has its own PXIe DStarB connection with the System Timing Slot By default these are driven logic low until configured by software Maximum operating frequency eee 200 MHz PXle DStarC The PXIe DStarC signals are LVDS signals that come from other PXI Express slots in a chassis Each PXI Express slot in a chassis has a PXIe DStarC connection with the System Timing Slot These allow other modules in a PXIe Chassis to share a trigger or clock signal with the NI PXIe 6674T The NI PXIe 6674T can connect a signal received thr
11. CLKOUT Connector 4 PFI lt 0 5 gt Connectors 5 CLKIN Connector O National Instruments 3 3 Chapter 3 Hardware Overview Access LED The Access LED indicates the communication status of the NI PXIe 6674T Refer to Figure 3 2 for the location of the Access LED Table 3 1 summarizes what the Access LED colors represent Table 3 1 Access LED Color Indication Color Status Off Module is not yet functional Green Driver has initialized the module Amber Module is being accessed The Access LED flashes amber for 50 ms when the module is accessed Blinking Red Module has detected an over temperature condition Solid Red A hardware error has been detected A Caution Ifthe Access LED is observed to be blinking red the module has detected an over temperature condition Continued use ofthe NI PXIe 6674T in this condition is not recommended as product reliability may become comprised Since several common problems can cause an over temperature condition please investigate the following e Check that all chassis covers filler panels and or slot blockers are installed Make sure that the chassis fan speed is set to the highest setting e Ifapplicable check that the chassis fan air intake is not blocked and that the fan filters are clean Make sure that the ambient temperature around the chassis isn t above the rated temperature specifications If so move the chassis to a cooler ambient tem
12. DStarC Single Ended PFI 13 6 ns lt 5 ns PXIe DStarC LVDS PFI 7 2 ns lt 5 ns PXIe DStarC PXI Trigger 28 1 ns lt 1 5 ns National Instruments A 19 Appendix A Specifications Table A 1 Asynchronous Trigger Delays and Skew Values Continued Trigger Source Trigger Destination Typical Delay Typical Skewt PXIe DStarC PXI Star 16 8 ns lt 75 ns PXIe DStarC PXIe DStarB 13 0 ns lt 5 ns Typical Delay is measured from the input to the NI PXIe 6674T at the connector to the output at the connector For example Single Ended PFI to PXI Star is the delay from the Single Ended PFI SMA connector to the PXI Star at the backplane connector Y Typical Skew is defined as the difference in arrival time of a rising edge on a common source to two or more outputs with in a trigger destination as seen as the connector For example if Single Ended PFI 0 is asynchronously routed to all PXI Star lines the typical skew would be less than 75 ns Synchronized Trigger PXI_Clk10 to Out Table A 2 Synchronized Trigger PXI_CIk10 to Out Trigger Destination Clock to Out Time Single Ended PFI 11 2 ns Typical 19 9 ns Max LVDS PFI 9 8 ns Typical 14 8 ns Max PXI Trigger 28 2 ns Typical 30 2 ns Max PXI Star 14 8 ns Typical 24 5 ns Max PXIe DStarB 9 4 ns Typical 14 0 ns Max Clock to Out Time is the amount of time it takes for a logic change on a synchronous trigger to appear
13. Sync software will by default configure the attenuation to be enabled If the input signal supplied to CLKIN is less than 1 2 V the attenuation should be turned off in order to extend down the range of amplitudes CLKIN can receive 3 10 ni com NI PXle 6674T User Manual When using CLKIN for driving PXI_CLK10_IN please refer to the user manual for your PXI Express chassis for information on the frequency range your chassis is capable of receiving on PXI_CLK10_IN CLKIN can also be routed to the DSTARA network and be used as a trigger synchronization clock inside the FPGA 10 MHz PLL The NI PXIe 6674T features a phase locked loop PLL circuit for aligning the frequency of the OCXO with a reference clock supplied by the user from CLKIN In this configuration the OCXO is routed to the backplane on PXI_CLK10_IN The PXI Express backplane will in turn phase lock the PXI_CLK10 and PXIe_CLK100 signal to the PXI_CLK10_IN signal The NI PXIe 6674T uses the PXI_CLK10 signal it receives from the backplane as the feedback to the 10 MHz PLL circuitry The PLL circuitry controls the frequency of the OCXO by varying the tuning voltage used for the electronic frequency control By increasing or decreasing the frequency of the OCXO as needed the 10 MHz PLL of the NI PXIe 6674T is able to match the OCXO frequency to the reference clock supplied by the user from CLKIN Use of the 10 MHz PLL of the NI PXIe 6674T has advantages over using just CLKIN to
14. can generate and route clock signals between devices in multiple chassis providing a method to synchronize multiple devices in a multichassis PXI Express system This manual describes the electrical and mechanical aspects of the NI PXIe 6674T and contains information concerning its operation and programming National Instruments Documentation The MI PXTe 6674T User Manual is one piece of the documentation set for your measurement system You could have any of several other documents describing your hardware and software Use the documentation you have as follows e Measurement hardware documentation This documentation contains detailed information about the measurement hardware that plugs into or is connected to the computer Use this documentation for hardware installation and configuration instructions specifications about the measurement hardware and application hints e Software documentation Refer to the N Sync User Manual available at ni com manuals You can download NI documentation from ni com manuals Related Documentation The following documents contain information that you might find helpful as you read this manual PICMG 2 0 R3 0 CompactPCI Core Specification available from PICMG at www picmg org e PXI Specification Revision 2 1 available from www pxisa org e NI VISA User Manual available from ni com manuals e NI VISA Help included with the NI VISA software NESync User Manual availa
15. clock signals from the system timing slot to each PXI Express peripheral slot in a star configuration PXle DSTARA uses LVPECL signaling and closely matched trace lengths to achieve low skew high speed clock routing capabilities Refer to the PX Je_ DSTARA Network section for details on how the NI PXIe 6674T implements PXIe DSTARA National Instruments 3 11 Chapter 3 Hardware Overview PXIe DSTARB PXIe_DSTARB is used to send trigger signals from the system timing slot to each PXI Express peripheral slot in a star configuration PXIe_DSTARB uses LVDS signaling and closely matched trace lengths to achieve faster more precise triggering than is achievable with PXI_STAR or PXI_TRIG PXIe DSTARC PXIe DSTARC is used to send trigger signals from each PXI Express peripheral slot to the system timing slot in a star configuration PXIle DSTARC uses LVDS signaling and closely matched trace lengths and can be used to send a trigger signal or clock signal to the system timing slot module The NI PXIe 6674T receives each PXIe DSTARC signal and sends a copy to the PXle_ DSTARA network for clock sharing and to the FPGA for trigger routing PXle_DSTARA Network To achieve the high speed low skew routing performance required for PXIe_DSTARA the NI PXIe 6674T uses circuitry specifically designed for routing clock signals to PXIe DSTARA lt 0 16 gt NI Sync software automatically handles the routing through the PXIe DSTARA network However
16. drive PXI_CLKI0_IN Reference frequencies other than 10 MHz can be used The 10 MHz PLL includes internal dividers to divide both the reference from CLKIN and PXI_CLK10 down as needed in order to make both a common frequency This frequency is called the phase detector frequency as it is the frequency at which the PLL compares edge alignment to determine if it should speed up or slow down the OCXO NI Sync allows any reference frequency that is an integer multiple of 1 MHz to be used The 10 MHz PLL acts as a zero delay buffer between the CLKIN SMA and PXI_CLK10 PXIe_CLK100 at the backplane connector Because the 10 MHz PLL uses PXI_CLK10 for feedback it is able to create a known fixed phase relation between PXI_CLK10 and the reference supplied on CLKIN During manufacturing the phase relation the 10 MHz PLL maintains is adjusted so that a rising edge at the CLKIN SMA will align in time with a rising edge of PXI_CLK10 at the peripheral slot connector of the backplane This phase relation will remain in place regardless of the PXI Express chassis used allowing for simpler multi chassis system synchronization PXle_DSTARA PXle_DSTARB and PXle_DSTARC The PXI Express architecture includes a set of three high speed differential signal paths to connect the system timing slot to each PXI Express peripheral slot up to 17 peripheral slots These signals are PXle DSTARA PXIe_DSTARB and PXIe DSTARC PXIe DSTARA PXIe DSTARA is used to send
17. fixed installation and stationary motors with permanent connections to fixed installations Measurement Category IV is for measurements performed at the primary electrical supply installation typically outside buildings Examples include electricity meters and measurements on primary overcurrent protection devices and on ripple control units ni com Installing and Configuring This chapter describes how to install the NI PXIe 6674T hardware and software and how to configure the device Installing the Software Refer to the readme htm file that accompanies the N Sync CD for software installation directions Note Be sure to install the driver software before installing the NI PXIe 6674T hardware Installing the Hardware The following are general installation instructions Consult the chassis user manual or technical reference manual for specific instructions and warnings about installing new modules 1 Power off and unplug the chassis 2 Locate the system timing slot for your PXI Express chassis It is identified by the glyph shown in Figure 2 1 Figure 2 1 System Timing Slot Indicator Glyph 3 Remove the filler panel for the system timing slot if applicable 4 Ground yourself using a grounding strap or by touching a grounded object Follow the ESD protection precautions described in the Unpacking section of Chapter 1 Introduction 5 Carefully insert the NI PXIe 6674T into the system timing
18. for your PXI Express chassis for more information on how it uses PXI_CLK10_IN PXI_CLK10 In This signal is the PXI 10 MHz backplane clock This from signal is the output of the native 100 MHz oscillator chassis in the chassis divided by ten PXIe_CLK100 In This signal is the PXI Express 100 MHz backplane from clock PXIe_CLK100 offers tighter slot to slot timing chassis than PXI_CLK10 OCXO Clock Out This is the output of the 10 MHz OCXO The OCXO internal is an extremely stable and accurate frequency source CLKIN In CLKIN is the signal connected to the SMA input from front connector of the same name CLKIN can be routed panel directly to PXI_CLK10_IN to the 10 MHz PLL to PXIe_DSTARA or to the FPGA CLKOUT Out CLKOUT is the signal on the SMA output connector to front of the same name CLKOUT can be sourced from the panel OCXO PXI_CLK10 Clock Generation or from the PXIe_DSTARA network 3 6 ni com NI PXle 6674T User Manual Table 3 3 Signal Descriptions Continued Signal Name Direction Description Clock Generation Out Clock Generation refers to the clock signal coming internal from the onboard clock generation circuitry of the NI PXIe 6674T The clock generation circuitry can generate a clock from sub 1 Hz to 1 GHz with fine granularity and is automatically locked in phase to PXIe_CLK100 PFI lt 0 5 gt In Out The single ended Programmable Function Interface to from pins on the NI PX
19. generated frequency With FPGA divider oooccocnicninncccccnncnnnnn 0 2794 Hz Without FPGA divider cece 4 6875 MHz Maximum generated frequency c eee 1 GHz Frequency Accuracy is inherited from PXIe_Clk100 PXI_Clk10 Use OCXO for PXIe_Clk100 PXI_Clk10 replacement for improved frequency accuracy and phase noise N This is the frequency resolution of the DDS used in the Clock Generation circuitry For Clock Generation frequencies below 150 MHz this resolution is divided down and for frequencies above 300 MHz this resolution is multiplied up Refer to the Clock Generation section in Chapter 3 Hardware Overview for more details w When routed to ClkOut Low Speed or used as a trigger synchronization clock Clock Generation can be further divided by the FPGA by factors of two up to 24 This extends the Clock Generation range down to 4 6875 MHz 24 2794 Hz When routed to ClkOut High Speed the minimum frequency is 4 6875 MHz Use ClkOutHS as the destination terminal to force NI Sync to use the low speed driver below 50 MHz Note that AC coupling on ClkOut limits the minimum frequency which can be used a Clock Generation can be operated beyond the upper limit however NI does not guarantee performance beyond 1 GHz 2 GHz is the maximum output frequency by design A 10 ni com NI PXle 6674T User Manual Clock Generation Phase Noise Performance A Note All Phase Noise Measurements were made on a Representative Mod
20. loop See PLL physical specifications A 25 PLL routing from the CLKIN connector 3 5 power requirement specifications A 25 programmable function interface See PFI PXI star trigger bus See PXI_STAR PXI trigger bus See PXI_ TRIG PXI CLK10 clock generation 3 9 Clock Generation phase lock 3 7 phase calibration 4 1 routing to the CLKOUT connector 3 5 using front panel PFIs as LVDS triggers 3 21 using front panel PFIs as outputs 3 20 using the PXI triggers 3 22 PXI_CLK10_IN routing from the CLKIN connector 3 5 signal description table 3 6 PXI_CLK10_OUT signal description table 3 6 PXI_STAR asynchronous routing 3 25 signal description table 3 7 using front panel PFIs as LVDS triggers 3 21 using front panel PFIs as outputs 3 20 using the PXI star triggers 3 23 using the PXI triggers 3 22 PXI TRIG asynchronous routing 3 25 signal description table 3 7 using front panel PFIs as LVDS triggers 3 21 using front panel PFIs as single ended outputs 3 20 using the PXI star triggers 3 23 using the PXI triggers 3 22 PXI_TRIG PXI_STAR synchronization clock possible sources 3 22 using the PXI triggers 3 22 PXIe_CLK100 signal description table 3 6 PXIe_DSTARA signal description table 3 8 R reflections recommended cable configuration 3 20 related documentation ix resistors terminating signals note 3 20 routing a clock overview 3 8 routing architecture figure 3 16 NI PXle 6674T Use
21. measurements include signal levels special hardware limited energy parts of hardware circuits powered by regulated low voltage sources and electronics Measurement Category II is for measurements performed on circuits directly connected to the electrical distribution system MAINS3 This category refers to local level electrical distribution such as that provided by a standard wall outlet for example 115 AC voltage Measurement categories also referred to as overvoltage or installation categories are defined in electrical safety standard IEC 61010 1 and IEC 60664 1 Working voltage is the highest rms value of an AC or DC voltage that can occur across any particular insulation N w MATINS is defined as a hazardous live electrical supply system that powers hardware Suitably rated measuring circuits may be connected to the MAINS for measuring purposes O National Instruments 1 3 Chapter 1 Introduction 1 4 for U S or 230 AC voltage for Europe Examples of Measurement Category II are measurements performed on household appliances portable tools and similar hardware Measurement Category III is for measurements performed in the building installation at the distribution level This category refers to measurements on hard wired hardware such as hardware in fixed installations distribution boards and circuit breakers Other examples are wiring including cables bus bars junction boxes switches socket outlets in the
22. noncondensing Tested in accordance with IEC 60068 2 56 30 g peak half sine 11 ms pulse Tested in accordance with IEC 60068 2 27 Meets MIL PRF 28800F Class 2 limits 5 to 500 Hz 0 3 gims 5 to 500 Hz 2 4 gims Tested in accordance with IEC 60068 2 64 Nonoperating test profile exceeds the requirements of MIL PRF 28800F Class 3 Caution Clean the NI PXIe 6674T module with a soft nonmetallic brush Make sure that the device is completely dry and free from contaminants before returning it to service Note Specifications are subject to Safety change without notice This product is designed to meet the requirements of the following standards of safety for electrical equipment for measurement control IEC 61010 1 EN 61010 1 UL 61010 1 CSA 61010 1 and laboratory use Note For UL and other safety certifications refer to the product label or the Online Product Certification section A 26 ni com NI PXle 6674T User Manual Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement control and laboratory use EN 61326 1 IEC 61326 1 Class A emissions Basic immunity EN 55011 CISPR 11 Group 1 Class A emissions AS NZS CISPR 11 Group 1 Class A emissions e FCC 47 CFR Part 15B Class A emissions e ICES 001 Class A emissions Note Inthe United States per FCC 47 CFR Class A equipment is intended for use in c
23. not guaranteed the FPGA not the LVDS receiver Operation with greater voltage swing will not damage the device but performance characteristics are Y Maximum Input Voltage Range is any combination of input voltage swing and common mode voltage For example a 200 mV differential swing with common mode voltage of 100 mV is acceptable as the lowest applied voltage to the input would be 0 V A 200 mV differential swing with common mode less than 100 mV would cause the applied voltage to fall below 0 V and therefore would not be acceptable t Operation beyond 1 GHz is possible but performance is not guaranteed Operation beyond 200 MHz is possible but performance is not guaranteed This limitation comes from A 16 ni com Output Characteristics NI PXle 6674T User Manual Differential Output Voltage into 100 ohm differential load at DC 600 mV p typical Output Common Mode Voltage 1 125 V to 1 375 V Maximum Output Frequency Sourced from Cross Point Switch 1 GHz Maximum Output Frequency Sourced from FPGA 200 MHz Differential Rise and Fall Time 180 ps typical Operation beyond 1 GHz is possible but performance is not guaranteed the FPGA not the LVDS driver Operation beyond 200 MHz is possible but performance is not guaranteed This limitation comes from Figure A 13 shows the representative LVDS output operating at 100 MHz 1 unit interval in this figure equals
24. or down for any division or multiplication done to generate the requested frequency as shown in Table 3 4 Table 3 4 Resolution by Frequency Range Clock Generation Frequency Resolution 18 75 MHz to 37 5 MHz 0 355 uHz 37 5 MHz to 75 MHz 0 711 pHz 75 MHz to 150 MHz 1 42 uHz 150 MHz to 300 MHz 2 84 uHz 300 MHz to 600 MHz 5 68 Hz 600 MHz to 1 GHz 11 4 Hz Because the 800 MHz reference of the clock generation circuitry is phase locked to PXIe_CLK100 its frequency accuracy is inherited from PXle_CLK100 To give the best frequency accuracy the OCXO of the NI PXIe 6674T can be routed to PXI_CLK10_IN which the chassis can then use to lock PXIe_CLK100 and PXI_CLK10 In addition using the OCXO will also lower the phase noise of the generated clock frequency PXI_CLK10 and PXle_CLK100 The PXI Express architecture allows a module in the system timing slot to provide a 10 MHz reference clock to the backplane for use in creating PXI_CLK10 and PXIe_CLK100 This is done by using the PXI_CLK10_IN pin on the backplane connector Most PXI Express backplane architectures employ a PLL to lock a 100 MHz reference oscillator to the signal coming from PXI_CLK10_IN pin This 100 MHz reference is then used to directly create PXIe_CLK100 and is divided down by ten to create PXI_CLK10 This architecture has the advantage that PXI_CLK10 and PXIe_CLK100 are always sourced from the same reference oscillator and therefore it is
25. slot making sure to not scrape the module on any adjacent modules Use the injector ejector handle to fully insert the module into the chassis Screw the front panel of the device to the front panel mounting rail of the chassis If adjacent slots are not populated use EMC filler panels to cover the opening O National Instruments 2 1 Chapter 2 Installing and Configuring Caution To ensure the specified EMC performance you must install PXI EMC A filler panels National Instruments part number 778700 01 in all open chassis slots 8 Visually verify the installation Ensure that the module is fully inserted into the slot 9 Plug in and power on the chassis The NI PXIe 6674T is now installed Configuring the Module The NI PXIe 6674T is completely software configurable The system software automatically allocates all module resources The two LEDs on the front panel provide information about module status The front panel description sections of Chapter 3 Hardware Overview describe the LEDs in greater detail 2 2 ni com Hardware Overview This chapter presents an overview of the hardware functions of the NI PXIe 6674T Figure 3 1 provides a functional overview of the NI PXIe 6674T hardware O National Instruments 3 1 Chapter 3 Hardware Overview Figure 3 1 Functional Overview of the NI PXle 6674T AC Coupled PXI_CLK10_IN CEKIN Clock Detector PLL OCX
26. under a license from Microsoft Corporation Windows is a registered trademark of Microsoft Corporation in the United States and other countries Other product and company names mentioned herein are trademarks or trade names of their respective companies Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents Export Compliance Information Refer to the Export Compliance Information at ni com legal export compliance for the National Instruments global trade compliance policy and how to obtain relevant HTS codes ECCNs and other import export data WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS YOU ARE ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY AND RELIABILITY OF THE PRODUCTS WHENEVER THE PRODUCTS ARE INCORPORATED IN YOUR SYSTEM OR APPLICATION INCLUDING THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION PRODUCTS ARE NOT DESIGNED MANUFACTURED OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL SYSTEMS HAZARDOUS ENVIRONMENTS OR ANY OTHER ENVIRONMENTS REQUIRING FAIL SAFE PERFORMANCE INCLUDING IN THE OPE
27. 0 55 PN 60 A PXI_CLK10 with no reference used A 7 65 B Reference from CLKIN at PXI_CLK10_IN 10 MHz PLL not used ASA 70 C Resulting PXI_CLK10 with CLKIN routed to PXI_CLK10_IN 10 MHz PLL not used AV 75 D Resulting PXI_CLK10 with 10 MHz PLL used 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 T T T 1 10 100 1k 10k 100k 1M 2M Frequency Offset Hz dBc Hz 1 The PXIe backplane employs a PLL to phase lock PXI_CLK10 to the signal on PXI_CLK10_IN Asa result the phase noise of PXI_CLK10 above about kHz offset is unchanged regardless of reference used O National Instruments A 7 Appendix A ClkOut Specifications Low Speed CIkOut High Speed CikOut Coupling AC Coupled AC Coupled Expected Termination 50 Q or high impedance 50 Q Frequency Range 1 MHz to 50 MHz 1 MHz to 1 GHz Typical Amplitude 2 57 V y into 50 Q 800 mV pp 5 V pp into high Z Rising Falling Edge 270 ps typical 180 ps typical 20 80 45 to 55 45 to 55 Duty Cycle of output with Clock Generation as source Available Sources PXI CLK10 10 MHz OCXO Clock Generation up to 50 MHz Clock Generation PXIe DStarA Network Operation of low speed ClkOut above 50 MHz is possible however NI does not guarantee performance Use ClkOutLS as the destination terminal to force NI Sync to use the low spee
28. 2 1 installing the software 2 1 software programming choices 1 2 unpacking 1 2 National Instruments I 1 Index global software trigger using front panel PFIs as LVDS triggers 3 21 using front panel PFIs as outputs 3 20 using the PXI star triggers 3 23 using the PXI triggers 3 22 H hardware block diagram 3 2 calibration 4 1 configuring 2 2 connector descriptions 3 5 installing 2 1 overview 3 6 installation hardware 2 1 software 2 1 L LED Access LED 3 5 Active LED 3 5 M maximum signal rating caution 3 5 N NI PXIe 6674T configuration 2 2 connectors 3 5 functional overview 3 6 installation hardware 2 1 software 2 1 parts locator diagram 3 3 l 2 nicom O OCXO clock generation 3 9 frequency calibration 4 1 OCXO clock routing to the CLKOUT connector 3 5 oven controlled crystal oscillator See OCXO P PFI PFI lt 0 5 gt connector description 3 5 location diagram 3 3 signal description table 3 7 PFI lt 0 5 gt signals asynchronous routing 3 25 front panel PFIs as single ended inputs 3 20 using front panel PFIs as LVDS triggers 3 21 using front panel PFIs as single ended inputs 3 20 using front panel PFIs as single ended outputs 3 20 PFI synchronization clock 3 5 possible sources 3 20 3 21 using front panel PFIs as LVDS triggers 3 21 using front panel PFIs as outputs 3 20 PFI_LVDS lt 0 2 gt signal description table 3 7 phase locked
29. 6 PXle_DSTARA Divisions Bank 0 Bank 1 Bank 2 Bank 3 PXIe DSTARA PXIe DSTARA PXIe DSTARA PXIe DSTARA lt 0 3 gt lt 4 1 gt lt 8 11 gt lt 12 16 gt PFI_LVDS cross point PFI_LVDS cross point PFI_LVDS cross point Each one of the Banks can select from either Source A or Source B and all the PXIe DSTARA lines that a Bank drives out must share the same source Banks 0 1 and 2 send a copy of their output to the PFI_ LVDS cross point switch for routing out the front panel using the PFI lines in LVDS mode Refer to the PF_LVDS lt 0 2 gt section for more information Note Because a single integrated circuit is used to make the five outputs in each bank tighter skew is achieved within a single Bank than from Bank to Bank National Instruments 3 13 Chapter 3 Hardware Overview PFI_LVDS lt 0 2 gt To allow for sending and receiving signals between system timing modules that are too fast for single ended PFI signaling two PFI SMA connectors can be combined to send or receive LVDS signals Table 3 7 shows the relation between the front panel SMA connectors used for PFI and PFI LVDS Table 3 7 Combinations of PFI Lines for PFI_LVDS PFI Line PFI_LVDS Line PFIO PFI LVDS 0 Negative PFI 1 PFI LVDS 0 Positive PFI 2 PFI LVDS 1 Negative PFI3 PFI LVDS 1 Positive PFI4 PFI LVDS 2 Negative PFI5 PFI LVDS 2 Positive Each of the three PFI LVDS can be enabl
30. 6674T or any other source with a 50 Q output The voltage thresholds for the front panel PFI inputs are programmable The input signal is generated by comparing the input voltage on the PFI connectors to the voltage output of software programmable DACs The thresholds for the PFI lines are individually programmable which is useful if you are importing signals from multiple sources with different voltage swings Using Front Panel PFls as Single Ended Outputs The front panel PFI outputs are 3 3 V drivers with 50 Q output impedance The outputs can drive 50 Q loads such as a 50 Q coaxial cable with a 50 Q receiver This cable configuration is the recommended setup to minimize reflections With this configuration the receiver sees a single 1 6 V step a 3 3 V step split across the 50 resistors at the source and the destination You also can drive a 50 Q cable with a high impedance load The destination sees a single step to 3 3 V but the source sees a reflection This cable configuration is acceptable for low frequency signals or short cables You can independently select the output signal source for each PFI line from one of the following sources e Another PFI lt 0 5 gt Another PFI pair in LVDS mode PXI triggers lt 0 7 gt PXL TRIG lt 0 7 gt PXI STAR lt 0 16 gt e Global software trigger e PFI synchronization clock PXIe DSTARC Steady logic high or low The PFI synchronization clock may be any of the fol
31. DS PFI 10 9 ns Typical 9 8 ns Typical 18 1 ns Max 5 4 ns Max PXI Trigger PXLT Trigger 10 1 ns Typical 7 8 ns Typical 17 0 ns Max 3 6 ns Max PXI Trigger PXI Star 9 7 ns Typical 7 4 ns Typical 16 2 ns Max 3 1 ns Max National Instruments A 21 Appendix A Specifications Table A 3 Synchronized Trigger Setup and Hold Timing With Respect to PXI_CIk10 Continued 4 4 ns Max Trigger Source Trigger Destination Setup Time Hold Timet PXI Trigger PXIe DStarB 10 7 ns Typical 9 0 ns Typical 17 8 ns Max 5 1 ns Max PXI Star Single Ended PFI 3 9 ns Typical 2 5 ns Typical 10 9 ns Max 0 5 ns Max PXI Star LVDS PFI 3 9 ns Typical 3 1 ns Typical 11 1 ns Max 0 8 ns Max PXI Star PXI Trigger 2 7 ns Typical 0 9 ns Typical 9 9 ns Max 0 9 ns Max PXI Star PXI Star 2 0 ns Typical 0 1 ns Typical 9 6 ns Max 1 1 ns Max PXI Star PXIe DStarB 4 3 ns Typical 2 4 ns Typical 11 7 ns Max 1 1 ns Max PXIe DStarC Single Ended PFI 0 5 ns Typical 0 4 ns Typical 3 9 ns Max 3 7 ns Max PXIe DStarC LVDS PFI 0 3 ns Typical 0 5 ns Typical 3 1 ns Max PXIe DStarC PXI Trigger 1 1 ns Typical 2 8 ns Max 1 9 ns Typical 5 2 ns Max PXIe DStarC PXI Star 0 5 ns Typical 3 2 ns Max 3 1 ns Typical 4 9 ns Max PXIe DStarC PXIe DStarB 1 3 ns Typical 5 6 ns Max 0 2 ns Typical 2 4 ns Max information information Setup Time is the
32. I Input switching behavior is a function of both the threshold setting and hysteresis Input Voltage Swing below 400 mV may be possible but performance is not guaranteed Operation beyond 150MHz frequency may be possible but performance is not guaranteed Voltages beyond the maximum range may cause damage to the device PFI line will float to 0 45 V when configured in high impedance mode with no external signal E Ensure that the specifications of interest match the revision label on your board The location of the label is shown in Figure A 1 NJ PXTe 6674T Revision Label National Instruments A 15 Appendix A Specifications Output Characteristics Output Impedance 50 Q nominal Output Coupling DC Output Voltage Range into 50 Q load 0 V to 1 63 V typical Output Voltage Range into open load 0 V to 3 22 V typical Output Rising Falling Edge into 50 Q load 450 ps to 500 ps 20 80 typical Maximum Output Frequency DC to 150 MHz Operation beyond 150 MHz frequency may be possible but performance is not guaranteed PFI LVDS Input Characteristics Minimum Differential Input Voltage 100 mV jp Recommended Maximum Differential Input Voltage 1V Maximum Input Voltage Range 0Vto4V Differential Input Resistance 100 Q 10 Maximum Input Frequency Routed to DStarA 1 GHz Maximum Input Frequency Routed to FPGA 200 MHz
33. Ie 6674T route timing and front panel triggering signals between multiple PXI Express chassis A wide variety of input and output signals can be routed to or from the PFI lines PFI LVDS lt 0 2 gt In Out The LVDS Programmable Function Interface can be to from used to route timing and triggering signals between front panel multiple PXI Express chassis The use of LVDS logic allows much faster speeds than can be achieved with the single ended PFIs The LVDS PFIs when used as outputs can be sourced from the PXIle DSTARA network the FPGA or the clock generation circuitry As inputs the LVDS PFIs can be routed to the PXIe_ DSTARA network and to the FPGA PXI_TRIG lt 0 7 gt In Out The PXI trigger bus consists of eight digital lines to from shared among all slots in the PXI Express chassis chassis The NI PXIe 6674T can route a wide variety of signals to and from these lines Note PXI_TRIG lt 0 5 gt are also known as RTSI lt O0 5 gt in some hardware devices and APIs However PXI_TRIG lt 6 7 gt are not identical to RTSI lt 6 7 gt PXI_STAR lt O0 16 gt In Out The PXI star trigger bus connects the system timing to from slot to other peripheral slots in a star configuration chassis The electrical paths of each star line are closely matched to minimize intermodule skew An NI PXIe 6674T in the system timing slot can route signals to all available PXI_STARs in the PXI Express chassis National Instruments 3 7
34. O OCXO J g Clock Calibrati lt j alibration PXI_CLK10 CLKOUT PXle_CLK100 A Clock d 4 i Generation feren PXle_DSTARA gt PXle_DSTARA lt 0 16 gt Routing lt Clock Generation o a g o x Ww x o PXle_DSTARC lt 0 16 gt PXle_DSTARB lt 0 16 gt LVDS Driver Receiver Comparator PFIO nro noig e gt PFI 1 dE PFI lt 0 5 gt CLOCK and Driver TRIGGER PXI_STAR lt 0 16 gt Comparator Routing 11 Threshold DAC PFI 0 dp 001119 oTo Ox90 y Z i PXI_TRIG lt 0 7 gt Z fo a Q e Receiver PFI2 Driver Comparator PCI Express gt PFI2 Interface Threshold il PFI 3 dy PCI Express Driver Comparator Z i Threshold E g n g 3 a v ggn 1655 Receiver PFI4 Driver Comparator 1 PFI 4 Threshold PFI 5 lt gt Driver Comparator 4 yy i A PFI5 Threshold o gt R 3 2 ni com NI PXle 6674T User Manual NI PXle 6674T Front Panel Figure 3 2 shows the connectors and LEDs on the front panel of the NI PXIe 6674T Figure 3 2 NI PXle 6674T Front Panel Y NATIONAL 1 INSTRUMENTS NI PXle 6674T Timing Module 1 Access LED 2 Active LED 3
35. Off is the maximum input signal amplitude that the device can tolerate before damage might occur while in an unpowered state Note Input can be either square wave or sinusoidal A 2 ni com NI PXle 6674T User Manual Figure A 2 Maximum and Minimum Input Swing with Attenuation On 5 5 5 45 4 4 3 5 4 34 2 5 2 155 14 0 54 04 T T T T T T T T T 0 10 20 30 40 50 60 70 80 90 100 Input Duty Cycle Input Swing Vpp Minimum Input Swing Vpp Maximum Input Swing Vpp Figure A 3 Maximum and Minimum Input Swing with Attenuation Off 1 4 1 2 gt E 44 gt 2 084 067 aL 044 0 2 7 0 T T T T T T T T T 0 10 20 30 40 50 60 70 80 90 100 Input Duty Cycle Minimum Input Swing Vpp Maximum Input Swing Vpp Minimum frequency c ccccsescsesesesesesescseseeeees 1 MHz Maximum frequency To CIKLOPLE a s sss cassressedtesresresveds consescdesees 100 MHz TO FPGA cnica 200 MHz To PXTe DStar wscsscssssssssesssssessssssessessessees 1 GHz ClkIn to PXI_Clk10_In Delay PLL not used Typical at 25 Go ists decsesdeeateisieiss dao 6 75 ns Maximum over temperature c0c0 14 8 ns 1 The minimum frequency is limited by AC coupling National Instruments A 3 Appendix A Specifications OCXO Nominal frequency Accuracy within 1 year of calibration adjustment within 0 C to 55 C operating temperature range A EAT Long term stability
36. PXI Express NI PXle 6674T User Manual Timing and Synchronization Module for PXI Express May 2015 7 NATIONAL 3730890 01 INSTRUMENTS Worldwide Technical Support and Product Information ni com Worldwide Offices Visit ni com niglobal to access the branch office websites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support information refer to the MI Services appendix To comment on National Instruments documentation refer to the National Instruments website at ni com info and enter the Info Code feedback 2010 2015 National Instruments All rights reserved Legal Information Limited Warranty This document is provided as is and is subject to being changed without notice in future editions For the latest version refer to ni com manual s NI reviews this document carefully for technical accuracy however NI MAKES NO EXPRESS OR IMPLIED WARRANTIES AS TO THE ACCURACY OF THE INFORMATION CONTAINED HEREIN AND SHALL NOT BE LIABLE FOR ANY ERRORS NI warrants that its hardware products will be free of defects in materials and workmanship that cause the product to fail to substantially conform to the applicable NI published specifications for one 1 year from the date of invoice For a period of ninety 90 days from the dat
37. RATION OF NUCLEAR FACILITIES AIRCRAFT NAVIGATION AIR TRAFFIC CONTROL SYSTEMS LIFE SAVING OR LIFE SUSTAINING SYSTEMS OR SUCH OTHER MEDICAL DEVICES OR ANY OTHER APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH PERSONAL INJURY SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM COLLECTIVELY HIGH RISK USES FURTHER PRUDENT STEPS MUST BE TAKEN TO PROTECT AGAINST FAILURES INCLUDING PROVIDING BACK UP AND SHUT DOWN MECHANISMS NI EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH RISK USES Compliance Electromagnetic Compatibility Information This hardware has been tested and found to comply with the applicable regulatory requirements and limits for electromagnetic compatibility EMC as indicated in the hardware s Declaration of Conformity DoC These requirements and limits are designed to provide reasonable protection against harmful interference when the hardware is operated in the intended electromagnetic environment In special cases for example when either highly sensitive or noisy hardware is being used in close proximity additional mitigation measures may have to be employed to minimize the potential for electromagnetic interference While this hardware is compliant with the applicable regulatory EMC requirements there is no guarantee that interference will not occur in a particular installation To minimize the potential for the hardware to cause in
38. RM Ltd or its subsidiaries LEGO the LEGO logo WEDO and MINDSTORMS are trademarks of the LEGO Group TETRIX by Pitsco is a trademark of Pitsco Inc FIELDBUS FOUNDATION and FOUNDATION are trademarks of the Fieldbus Foundation EtherCAT is a registered trademark of and licensed by Beckhoff Automation GmbH CANopend is a registered Community Trademark of CAN in Automation e V DeviceNet and EtherNet IP are trademarks of ODVA Go SensorDAQ and Vernier are registered trademarks of Vernier Software amp Technology Vernier Software amp Technology and vernier com are trademarks or trade dress Xilinx is the registered trademark of Xilinx Inc Taptite and Trilobular are registered trademarks of Research Engineering amp Manufacturing Inc FireWire is the registered trademark of Apple Inc Linux is the registered trademark of Linus Torvalds in the U S and other countries Handle Graphics MATLAB Real Time Workshop Simulink Stateflow and xPC TargetBox are registered trademarks and TargetBox and Target Language Compiler are trademarks of The MathWorks Inc Tektronix Tek and Tektronix Enabling Technology are registered trademarks of Tektronix Inc The Bluetooth word mark is a registered trademark owned by the Bluetooth SIG Inc The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is under license The mark LabWindows is used
39. Where NI software may be used to reproduce software or other materials belonging to others you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction End User License Agreements and Third Party Legal Notices You can find end user license agreements EULAs and third party legal notices in the following locations Notices are located in the lt National Instruments gt _Legal Information and lt National Instruments gt directories EULAs are located in the lt National Instruments gt Shared MDF Legal license directory e Review lt National Instruments gt _Legal Information txt for information on including legal information in installers built with NI products U S Government Restricted Rights If you are an agency department or other entity of the United States Government Government the use duplication reproduction release modification disclosure or transfer of the technical data included in this manual is governed by the Restricted Rights provisions under Federal Acquisition Regulation 52 227 14 for civilian agencies and Defense Federal Acquisition Regulation Supplement Section 252 227 7014 and 252 227 7015 for military agencies Trademarks Refer to the NI Trademarks and Logo Guidelines at ni com trademarks for more information on National Instruments trademarks ARM Keil and Vision are trademarks or registered of A
40. als The first clock is generated using the onboard clock generation circuitry and the second is generated with a precise 10 MHz oscillator The following sections describe the two types of clock generation and explain the considerations for choosing either type Clock Generation The NI PXIe 6674T includes built in advanced clock generation circuitry for generating clock signals from below 1 Hz to 1 GHz with very fine frequency resolution The clock generation circuitry is based on a direct digital synthesis DDS with an 800 MHz reference phase locked to PXIe_CLK100 This allows the DDS to generate a 150 MHz 300 MHz signal with microhertz resolution The output from the DDS can then be divided down to lower frequencies used directly or multiplied up using a phase locked voltage controlled oscillator 3 8 ni com NI PXle 6674T User Manual The individual components which make up the clock generation circuitry are controlled by NI Sync software which allows the user to simply specify the frequency they wish the clock generation circuitry to produce NI Sync will then configure the clock generation circuitry to glve the closest possible frequency match to the requested frequency and do so with the configuration that gives the lowest possible phase noise The user may request a clock frequency up to 1 GHz frequencies beyond 1 GHz are possible but performance is not specified The precision of the frequency generated is that of the DDS scaled up
41. amount of time before a rising edge of PXI Clk10 at the backplane connector that a logic level must be valid on the trigger source at the connector in order for the trigger destination to update Refer to the Synchronous Routing section of Chapter 3 Hardware Overview for more Hold Time is the amount of time after a rising edge of PXI CIk10 at the backplane connector that a logic level must be valid on the trigger source at the connector in order for the trigger destination to update Refer to the Synchronous Routing section of Chapter 3 Hardware Overview for more A 22 ni com FPGA Functionality Trigger Routing Table A 4 shows the routes that can be made Table A 4 Sources and Destinations for NI PXle 6674T Signal Routing Operations Destinations Front Panel Backplane PFI PXI PXI Star PXI PXIe s CLK PFI LVDS CLK Trigger TRIG SYNC D STARA D STARB 8 OUT lt 0 5 gt lt 0 2 gt 10 IN lt 0 16 gt lt 0 7 gt CTRL lt 0 16 gt lt 0 16 gt 3 r a CLKIN Y lt amp PFI lt 0 5 gt E e PFI LVDS lt 0 2 gt s u wnysu JeuoneN ec W enue 19sn 17299 81Xd IN vow Wwo9o lu Table A 4 Sources and Destinations for NI PXle 6674T Signal Routing Operations Continued Destination PXI CLK 10 v PXI CLK Y 100 PXI STAR lt 0 16 gt Backplane PXI TRIG lt 0 7 gt DSTARC lt 0 16 gt Sources OCXO Y
42. are specific to earlier revisions of the NI PXIe 6674T module A label with revision information can be found on the module board as shown in Figure A 1 x denotes all letter revisions of the assembly Ensure the specifications of interest match the revision that is printed on the label Figure A 1 NI PXle 6674T Revision Label 4 1 110 0 ZZ661 a B y y y a BO 00000000000000 Es National Instruments A 1 Appendix A Specifications CLKIN Characteristics Input coupling cooooconicnccnoccnaconcnncononnnonconcon con nonos AC Input impedance ooconociccnicccnnonconconconconconconconc nos 50 Q nominal Minimum and Maximum Input Levels Attentuation Attentuation Setting Setting On Setting Off Attenuation Setting On default Off Attenuation Behavior 5 1 1 1 Minimum Input Swing with 50 Duty Cycle 750 mV 150 mV Maximum Input Swing with 50 Duty Cycle 5 0 Vop 1 2 Vip Absolute Maximum Input Powered On 5 6 Vip 2 8 Vip Absolute Maximum Input Powered Off 1 5 Vop information information A duty cycle other than 50 will increase the minimum input swing Refer to Figure A 2 for more A duty cycle other than 50 will increase the minimum input swing Refer to Figure A 3 for more Operation above the Absolute Maximum Input Powered On may cause damage to the device Absolute Maximum Input Powered
43. ation clock A digital signal comes in on the source and is propagated to the destination after the edge has been realigned with the synchronization clock Unlike asynchronous routing the output of a synchronous routing operation does not directly follow the input after a propagation delay Instead the output waits for the next rising edge of the clock before it follows the input Thus the output is said to be synchronous with this clock National Instruments 3 25 Chapter 3 Hardware Overview Figure 3 7 shows a timing diagram that illustrates synchronous routing Figure 3 7 Synchronous Routing Operation Setup Hold Time Time t tsetup thold lt lt Trigger Input Synchronization Clock i Clock to Output Time totog Trigger Output i Synchronous routing can send triggers to several places in the same clock cycle If a signal arrives at two chassis within the same clock cycle each NI PXIe 6674T realigns the signal with the synchronization clock and distributes it to the modules in each chassis at the same time Synchronous routing can thus remove uncertainty about when triggers are received If the delays through the system are such that an asynchronous trigger might arrive near the edge of the receiver clock the receiver might see the signal in the first clock cycle or it might see it in the second clock cycle However by synchronizing the signal you can eliminate the ambiguity a
44. ay along each star trigger line be matched to within 1 ns A typical upper limit for the skew in most NI PXI Express chassis is 500 ps The low skew of the PXI star trigger bus is useful for applications that require triggers to arrive at several modules nearly simultaneously The star trigger lines are bidirectional so signals can be sent to the system timing slot from a module in another slot or from the system timing slot to the other module You can independently select the output signal source for each PXI star trigger line from one of the following sources e PFI lt O 5 gt PFI LVDS lt 0 2 gt PXI triggers lt 0 7 gt PXL TRIG lt 0 7 gt Another PXI star trigger line PXI_STAR lt 0 16 gt e Global software trigger e Backplane synchronization clock PXIe DSTARC Steady logic high or low Refer to the Using the PXI Triggers section for more information on the backplane synchronization clock Using the PXle_DSTARB and PXle_DSTARC Triggers To improve beyond the performance the PXI Star triggers offer in low skew trigger routing PXI Express implements PXIe DSTARB and PXIe DSTARC triggers Each PXI Express peripheral slot in a PXI Express chassis has independent PXIe DSTARB and PXIe DSTARC connections with the system timing slot module This allows peripheral modules to send triggers to the system timing module using PXIe DSTARC and for the system timing module to send triggers to peripheral modules using PXIe DSTARB
45. because the PXIle DSTARA Network limits the number of connections that can be made it is important to understand the underlying hardware architecture Figure 3 3 provides an overview of the PXle DSTARA network Figure 3 3 PXle_DSTARA Network PXle DSTARA lt 0 3 gt Bank 0 Fanout Clock Generation PXle DSTARA lt 4 7 gt Bank 1 Fanout PXle_DSTARC lt 0 7 gt PXle DSTARA lt 8 11 gt Bank 2 Fanout Clock Generation PXle DSTARA lt 12 16 gt To PFI_LLVDS O J PFI_LVDS To PFI_LLVDS 1 Crosspoint To PFI_LVDS 2 Switch gt Clock Generation To CLKOUT e Bank 3 PXle_DSTARC lt 8 16 gt Fanout TE i T co 0 GH 3 12 ni com NI PXle 6674T User Manual The PXle_DSTARA network allows the user to select which source to route to the PXIe_DSTARA lines It does this by creating two intermediate sources Source A and Source B Source A and Source B are created by multiplexers with the source options shown in Table 3 5 Table 3 5 Sources for Source A and Source B Inputs to Source A Inputs to Source B CLKIN CLKIN PFI_LVDS lt O0 2 gt PFI_LVDS lt 0 2 gt Clock Generation Clock Generation PXIe_ DSTARC lt 0 7 gt PXIe DSTARC lt 8 16 gt To drive signals out on the PXIe DSTARA lines the PXIle_ DSTARA network divides the 17 PXIe DSTARA lines into four banks as shown in Table 3 6 Table 3
46. ble from ni com manuals NI PXTe 6674T Calibration Procedure available from ni com manuals O National Instruments ix Introduction The NI PXIe 6674T timing and synchronization module enables you to share clock and triggers between modules in a PXI Express chassis and other PXI chassis or non PXI systems The NI PXIe 6674T module generates and routes clock signals between devices in multiple chassis providing a method for synchronizing multiple devices in a PXI Express system It also features a precision OCXO for improving the stability and accuracy of the PXI Express backplane reference clocks What You Need to Get Started To set up and use the NI PXIe 6674T you need the following items NI PXIe 6674T Timing and Synchronization Module NI PXTe 6674T User Manual NESync CD One of the following software packages and documentation LabVIEW LabWindows CVI Microsoft Visual C MSVC PXI EMC filler panels National Instruments part number 778700 01 PXI Express chassis PXI Express embedded controller or a desktop computer connected to the PXI Express chassis using MXI Express hardware The N Sync User Manual offers more detailed information on the software used to program the NI PXIe 6674T You can find this manual on the N Sync CD or download it from ni com manuals National Instruments 1 1 Chapter 1 Introduction Unpacking
47. d driver above 50 MHz Operation above 1 GHz is possible but NI does not guarantee performance t Routing PXTe DStarA to ClkOut requires routing through either Banks 0 1 or 2 Refer to the PXIe DSTARA Network section of Chapter 3 Hardware Overview for additional information PXI_CLK10 to ClkOut Delay Typical at 25 C nicoicnsilsnido citada 20 2 ns Maximum over temperature 47 75 ns A 8 ni com NI PXle 6674T User Manual Figure A 7 shows the typical Low Speed ClkOut Amplitude performance with a sample size of 19 modules Figure A 7 Typical Low Speed ClkOut Amplitude Performance 2 8 2 75 sy 2 65 2 55 Amplitude Vpp nm o N a 2 45 2 4 0 10 20 30 40 50 60 70 80 90 100 110 Frequency MHz Figure A 8 shows the typical High Speed ClkOut Amplitude performance with a sample size of 19 modules Figure A 8 Typical High Speed ClkOut Amplitude Performance 1 0 95 0 9 0 85 0 8 0 75 Amplitude Vpp 0 7 0 65 0 6 100 150 200 250 300 450 400 150 500550 600 650 700 750 800 850 900 950 110 Frequency MHz National Instruments A 9 Appendix A Specifications Clock Generation Reference frequency source ccccceseseeeeeee PXIe_Clk100 Base frequency resolution 150 MHz to 300 MHZ eeeeseeeceereeeeteeees 2 84217 Hz Minimum
48. e PFL PFI PFI 3 16 PXI_CLK10 gt yy N 2 F ones 3 SYNCHRONIZATION CLOCKS for PXI_STAR lt 0 16 gt PXI_TRIG lt 0 7 gt Selection 7 LVDS 0 lt Circuitry yg __ m Selection Selection 4 6 PXI_STAR lt 0 16 gt PXI_TRIG lt 0 7 gt Circuitry PXle_DSTARB O LVDS 1 Circuitry PFl lt 0 5 gt PFI_LVDS lt 0 2 gt PXle_DSTARC lt 0 16 gt Steady Lhal z Selection 4 S Logic and Software Trigger are gt ra gt PXle_DSTARB 1 LVDS 2 Circuitry routed to SOURCE of each Selection lt Circuitry block o P di e e Selection PFI 0 lt Circuitry g e id HU Selection PFI1 lt aati Lp Circuitry gt PXle_DSTARB 16 ircuitry y i lt T Selecti Selection election PFI 2 lt Circuitry le 53 gt Circuitry gt PXI_LSTAR 0 SOURCE e h 3 Selection Selection BELO Circuitry le gt Circuitry gt PXI_STAR 1 PFI 4 lt 4 Selection 2 A Circuitry la E s gt Selection o p gt Selection PFI 5 lt H Circuitry bo CA Create gt PXILSTAR 16 SYNCHRONIZATION LL a CLOCKS for PFI lt 0 5 gt gt ae L gt PXI_TRIG 0 CLKIN and PFI_LVDS lt 0 2 gt pa y HP Selection __OCXO E Gracin gt PXI_TRIG 1 Clock Generation e e e PXle CLK100 ee gt gt 9N gt
49. e of invoice NI warrants that i its software products will perform substantially in accordance with the applicable documentation provided with the software and ii the software media will be free from defects in materials and workmanship If NI receives notice of a defect or non conformance during the applicable warranty period NI will in its discretion i repair or replace the affected product or ii refund the fees paid for the affected product Repaired or replaced Hardware will be warranted for the remainder of the original warranty period or ninety 90 days whichever is longer If NI elects to repair or replace the product NI may use new or refurbished parts or products that are equivalent to new in performance and reliability and are at least functionally equivalent to the original part or product You must obtain an RMA number from NI before returning any product to NI NI reserves the right to charge a fee for examining and testing Hardware not covered by the Limited Warranty This Limited Warranty does not apply if the defect of the product resulted from improper or inadequate maintenance installation repair or calibration performed by a party other than NI unauthorized modification improper environment use of an improper hardware or software key improper use or operation outside of the specification for the product improper voltages accident abuse or neglect or a hazard such as lightning flood or other act of nature
50. ect digital synthesis a method of creating a clock with a programmable frequency E EEPROM ESD F frequency frequency tuning word front panel H Hz in jitter L LabVIEW LED LVDS NI PXle 6674T User Manual electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed electrostatic discharge the rate of events or oscillations per second measured with a frequency counter or spectrum analyzer Frequency is the reciprocal of the period of a signal a number that specifies the frequency generated by a DDS the physical front panel of an instrument or other hardware hertz the number of scans read or updates written per second inch or inches the variation in time of a clock or oscillator from its ideal timing a graphical programming language light emitting diode a semiconductor light source Low Voltage Differential Signaling National Instruments G 3 Glossary M master Measurement amp Automation Explorer MAX N NI DAQ O OCXO oscillator output impedance P PFI PLL precision propagation delay PXI Express G 4 ni com the requesting or controlling device in a master slave configuration a controlled centralized configuration environment that allows you to configure all of your National Instruments DAQ GPIB IMAQ IVL Motion VISA and VXI devices National Instruments driver software f
51. ed for LVDS operation or used for two single ended PFIs When enabled for LVDS operation the PFI_ LVDS pair can be configured as either an input or an output PFI_LVDS lines can not be used as an input and output at the same time Because of the increased speed capabilities the PFI LVDS include additional routing capabilities not offered with the single ended PFI When used as in an input the PFL LVDS signal goes to both the FPGA for trigger routing and to the PXIle_ DSTARA Network for use in routing high speed clocks When used as an output the PFL_ LVDS can be sourced from the FPGA for trigger usage or from a 4x4 cross point switch which allows for any of the four inputs to be connected to any of the four outputs Table 3 8 shows the inputs and outputs of the cross point switch Table 3 8 Inputs and Outputs of the Cross Point Switch Inputs Outputs PXIe_ DSTARA Network Bank 0 PFI LVDS 0 PXIe_ DSTARA Network Bank 1 PFI LVDS 1 PXIe DSTARA Network Bank 2 PFI LVDS 2 Clock Generation High Speed CLKOUT 3 14 ni com NI PXle 6674T User Manual If the PFI_ LVDS output is used for trigger routing it is sourced from the FPGA and has all the same trigger routing characteristics as other trigger destinations Refer to the Using Front Panel PFIs for LVDS Triggers section for details on using PFI_LVDS for sending and receiving trigger signals CLKOUT The CLKOUT SMA connector on the front panel provides a means t
52. ee Using PX CURA TN citrico PXIe DSTARA PXIe_ DSTARB and PXIe DSTARC Routing Signals iia eet een beatae Determining Sources and Destinations cccsssseeseceseneeececeseeecsececeeceeeenseseeseees Using Front Panel PFIs as Single Ended Inputs eet eeeeeeeeeneeeceeeeeeeenee Using Front Panel PFIs as Single Ended Outputs coocociccncncononocacnnnccnnncononnnanns Using Front Panel PFIs for LVDS Triggers ooooncononicnnonncnnoncnnconconcnnccnconccnnonnonos Using the PXI Triggers Using the PXI Star Triggers Using the PXIe DSTARB and PXIe_DSTARC Triggers Choosing the Type of Routing ccccceceeseeceeecesceeeseesecseceeceecaseaaenseaaecsecneeseeneeas Asynchronous Routing ccccccsecsecssescesceseeseeseeeeeseceececeeceaeeseeaeeaeeaeeaeeaeeasenaeaes Synchronous ROUND econo ette ii tel National Instruments vii Contents Chapter 4 Calibration Factory Calibre atv ai hen Hie ees 4 1 OEXO Frequency diiniita ste cabeccadvaa vet causes A EEE EEE Eai 4 1 DRE CEKLO Phase ascii csuttec catasedivespatenctoveusvenveesigess dt eueaapiene lee 4 1 Additional Information sesiis a iai 4 1 Appendix A Specifications Appendix B NI Services Glossary Index viii ni com About This Manual Thank you for purchasing the National Instruments NI PXIe 6674T Timing and Synchronization Module The NI PXIe 6674T enables you to pass PXI timing and trigger signals between PXI Express chassis The NI PXIe 6674T
53. fter a propagation delay through the module Figure 3 6 illustrates an asynchronous routing operation Figure 3 6 Asynchronous Routing Operation Propagation Delay Trigger Input a oe Trigger Output 3 24 ni com NI PXle 6674T User Manual Some delay is always associated with an asynchronous route and this delay varies among NI PXIe 6674T modules depending on variations in temperature and chassis voltage Typical delay times in the NI PXIe 6674T for asynchronous routes between various sources and destinations are given in Appendix A Specifications Asynchronous routing works well if the total system delays are not too long for the application Propagation delay could be caused by the following reasons Output delay on the source e Propagation delay of the signal across the backplane s and cable s e Propagation delay of the signal through the NI PXIe 6674T Time for the receiver to recognize the signal Both the source and the destination of an asynchronous routing operation on the NI PXIe 6674T can be any of the following lines Any front panel PFI pin PFI lt 0 5 gt as single ended Any front panel PFI pin as LVDS PFL LVDS lt 0 2 gt Any PXI star trigger line PXI_STAR lt 0 16 gt Any PXI trigger line PXI_TRIG lt 0 7 gt Any PXIe DSTARB lt 0 16 gt Synchronous Routing A synchronous routing operation is defined in terms of three signal locations a source a destination and a synchroniz
54. he phase noise performance of these two drivers differs as shown in Figure A 11 Figure A 11 Phase Noise of Frequencies from DDS 80 85 7 90 7 95 7 100 105 4 110 115 4 120 1254 130 4 135 140 145 4 150 4 1554 160 4 165 4 170 dBc Hz A 10 MHz CIkOut Low Speed OT B 50 MHz ClkOut Low Speed A Y C 50 MHz CIkOut High Speed 1AN ANAY D 100 MHz CIkOut High Speed YAY E 200 MHz CIkOut High Speed DSS F 300 MHz ClkOut High Speed AN AN7 10 T T T T T 100 1k 10k 100k 1M 2M Frequency Offset Hz 1 Use ClkOutHS as the destination terminal to force NI Sync to use the high speed driver below 50 MHz National Instruments A 13 Appendix A Specifications PXle DStarA Figure A 12 PXle DStarA Topology PXle DSTARA lt O 3 gt Bank 0 Fanout PFI_LVDS lt 0 2 gt Clock Generation PXle DSTARA lt 4 7 gt Bank 1 PXle_DSTARC lt 0 7 gt Fanout PXle DSTARA lt 8 11 gt Bank 2 Fanout Clock Generation PXle DSTARA lt 12 16 gt _ gt PXle_DSTARC lt 8 16 gt Fanout T OF Of gH Clock Generation PXIe DStarA Maximum Frequency 1 GHz PXIe DStarA LVPECL Signal Characteristics To PFI_LLVDS O gt PFI_LVDS To PFI_LVDS 1 Crosspoint To PFI_LVDS 2 Switch To CLKOUT gt Min
55. ies as well as other environmental information not included in this document O National Instruments A 27 Appendix A Specifications Waste Electrical and Electronic Equipment WEEE Dd EU Customers At the end of the product life cycle all products must be sent to ana a WEEE recycling center For more information about WEEE recycling centers National Instruments WEEE initiatives and compliance with WEEE Directive 2002 96 EC on Waste and Electronic Equipment visit ni com environment weee EFAS mAh RE RoHS OO HEXZA National Instruments 46 t H EFIR Ar mhh ic add TUMS ROHS XF National Instruments i E ROHS AWESO EER ni com environment rohs_china For information about China RoHS compliance go to ni com environment rohs_china A 28 ni com NI Services National Instruments provides global services and support as part of our commitment to your success Take advantage of product services in addition to training and certification programs that meet your needs during each phase of the application life cycle from planning and development through deployment and ongoing maintenance To get started register your product at ni com myproducts As a registered NI product user you are entitled to the following benefits e Access to applicable product services Easier product management with an online account e Receive critical part notifications software updates and service expiration
56. impossible to lose PXI_CLK10 or PXIe_CLK100 by disconnecting the reference provided on PXI_CLK10_IN For the same reason it is also impossible for a runt pulse or glitch to occur on these lines as references are switched in and out protecting the integrity of digital circuitry operating on these clocks Another feature of this architecture is that the phase noise performance of PXI_CLK10 and PXIe_CLK100 is fixed beyond the bandwidth of the PLL loop of the backplane regardless of the quality of the reference used This is O National Instruments 3 9 Chapter 3 Hardware Overview advantageous if a reference with poor phase noise performance is used but it also means that supplying a high end low phase noise reference will not greatly improve PXI_CLK10 or PXIe CLK100 Using PXI_CLK10_IN The NI PXIe 6674T provides three options for driving a clock to the backplane using PXI_CLK10_IN OCXO CLKIN and 10 MHz PLL OCXO The NI PXIe 6674T features a precision 10 MHz Oven Controlled Crystal Oscillator OCXO The main source of frequency error in reference oscillators is temperature variation An OCXO minimizes this error by housing the crystal oscillator circuit inside a sealed oven which is maintained at a constant temperature higher than the ambient temperature external to the OCXO This results in a reference oscillator that is several orders of magnitude more stable and accurate than regular crystal oscillators Because the OCXO must warm
57. imum Typical Maximum Voltage High Output 2 155 V 2 280 V 2 405 V Voltage Low Output 1 355 V 1 530 V 1 700 V Rise Time Fall Time 20 80 125 ps 180 ps 275 ps ClkIn to PXIe DStarA Delay Typical at 25 Curico 4 21 ns Maximum over temperature PXIe DStarA to PXIe DStarA Skew A aiani lt 100 ps Maximum over temperatUlO ocooooccinccnoc 250 ps Maximum Frequency may exceed 1 GHz however performance is not guaranteed A 14 ni com Triggers PFI Single Ended Input Characteristics NI PXle 6674T User Manual Termination Setting High Impedance 50Q Input Impedance 10kQ 20 50 Q 5 Input Coupling DC DC Hysteresis 50 mV typical 58 mV typical Revision C and D 53 mV typical Revision E and later Adjustable Threshold Range 15 mV to 16 8 mV to 4 25 V Revision C 3 795 V and D 15 975 mV to 4 04 V Revision E and later Adjustable Threshold 15mV 16 8 mV Revision C and D Resolution 15 975 mV Revision E and later Adjustable Threshold Error 5mV 5mV Default Threshold Setting 1 005 V 1 008 V Revision C and D 1 006 V Revision E and later Minimum Input Voltage Swing 400 mV pp 450 mV jp Frequency Range DCto 150 MHz DCto 150 MHz Recommended Maximum 0 0 V to 5 0 V 0 0 V to 5 0 V Input Voltage Range Maximum Input Voltage O5Vto5 5V 0 5 V to 5 5 V Range PFI Open Circuit Voltaget 0 45 V typical N A connected as input PF
58. ion contains important safety information that you must follow when installing and using the product Do not operate the product in a manner not specified in this document Misuse of the product can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to National Instruments for repair Do not substitute parts or modify the product except as described in this document Use the product only with the chassis modules accessories and cables specified in the installation instructions You must have all covers and filler panels installed during operation of the product 1 2 ni com NI PXle 6674T User Manual Do not operate the product in an explosive atmosphere or where there may be flammable gases or fumes If you must operate the product in such an environment it must be in a suitably rated enclosure If you need to clean the product use a soft nonmetallic brush The product must be completely dry and free from contaminants before you return it to service Operate the product only at or below Pollution Degree 2 Pollution is foreign matter in a solid liquid or gaseous state that can reduce dielectric strength or surface resistivity The following is a description of pollution degrees e Pollution Degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence e Pollution Degree 2 means tha
59. is However this delay is not a problem for many applications You can independently select the output signal source for each PXI trigger line from one of the following sources e PFIS lt O 5 gt PFI LVDS lt 0 2 gt Another PXI trigger lt 0 7 gt PXI_TRIG lt O0 7 gt PXI_STAR lt O0 16 gt e Global software trigger e Backplane synchronization clock PXIe DSTARC Steady logic high or low The backplane synchronization clock may be any of the following signals e Clock Generation PXI_CLK10 PXIe CLK100 OCXO CLKIN e Any of the previously listed signals divided by the first frequency divider 2 up to 512 e Any of the previously listed signals divided by the second frequency divider 2 up to 512 Refer to the Choosing the Type of Routing section for more information about the synchronization clock 3 22 ni com NI PXle 6674T User Manual Note The backplane synchronization clock is the same for all routing operations in a which PXI_TRIG lt 0 7 gt PXIe_ DSTARB lt 0 16 gt or PXI_STAR lt 0 16 gt is defined as the output although the divide down ratio for this clock full rate first divider second divider may be chosen on a per route basis Using the PXI Star Triggers There are up to 17 PXI star triggers per chassis Each trigger line is a dedicated connection between the system timing slot and one other slot The PXI Specification Revision 2 1 requires that the propagation del
60. librated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the corrections that were needed to meet specifications are stored in the onboard nonvolatile memory EEPROM The driver software uses these stored values Factory Calibration The factory calibration of the NI PXIe 6674T involves calculating and storing four calibration constants These values control the accuracy of two features of the device which are discussed in the following sections OCXO Frequency The OCXO frequency can be varied over a small range The output frequency of the OCXO is adjusted using this constant to meet the specification listed in Appendix A Specifications PXI_CLK10 Phase When using the PLL to lock PXI_CLK10 to an external reference clock the phase between the clocks can be adjusted The time between rising edges of PXI_CLK10 and the input clock is minimized using this constant Note The PXI CLK10 phase is set during manufacturing and does not need to be recalibrated Additional Information Refer to ni com calibration for additional information on NI calibration services National Instruments 4 1 Specifications This appendix lists the system specifications for NI PXIe 6674T modules These specifications are typical at 25 C unless otherwise stated Ya Note Specifications are subject to change without notice A Note Some specifications
61. low The PFI synchronization clock is also used for the PFI_LVDS and as such may be one of the following signals e Clock Generation PXI CLK10 e PXIe CLK100 e OCXO CLKIN Any of the previously listed signals divided by the first frequency divider 2 up to 512 Any of the previously listed signals divided by the second frequency divider 2 up to 512 Refer to the Choosing the Type of Routing section for more information on the synchronization clock National Instruments 3 21 Chapter 3 Hardware Overview Note The PFI synchronization clock is the same for all routing operations in which a PFI lt 0 5 gt or PFI LVDS lt 0 2 gt is defined as the output although the divide down ratio for this clock full rate first divider second divider may be chosen on a per route basis Using the PXI Triggers The PXI triggers go to all the slots in the chassis All modules receive the same PXI triggers so PXI trigger 0 is the same for the system timing slot as it is for Slot 3 and so on This feature makes the PXI triggers convenient in situations where you want for instance to start an acquisition on several devices at the same time because all modules will receive the same trigger The frequency on the PXI triggers should not exceed 5 MHz to preserve signal integrity The signals do not reach each slot at precisely the same time A difference of several nanoseconds between slots can occur in an eight slot chass
62. lowing signals e Clock Generation PXI CLK10 PXle CLK100 e OCXO CLKIN 3 20 ni com NI PXle 6674T User Manual Any of the previously listed signals divided by the first frequency divider 2 up to 512 Any of the previously listed signals divided by the second frequency divider 2 up to 512 Refer to the Choosing the Type of Routing section for more information on the synchronization clock Note The PFI synchronization clock is the same for all routing operations in which PFI lt 0 5 gt or PFI LVDS lt 0 2 gt is defined as the output although the divide down ratio for this clock full rate first divider second divider may be chosen on a per route basis Using Front Panel PFls for LVDS Triggers To allow for sending and receiving signals between system timing modules that are too fast for single ended PFI signaling two PFI SMA connectors can be combined to send or receive LVDS signals Table 3 7 shows the relation between the front panel SMA connectors used for PFI and PFI LVDS When used for trigger routing the PFI LVDS signals are routed to and from the FPGA You can independently select the output signal source for each PFI_LVDS line from one of the following sources Another PFI lt 0 5 gt Another PFI pair in LVDS mode PXI triggers lt 0 7 gt PXI_TRIG lt 0 7 gt PXI STAR lt 0 16 gt e Global software trigger PFI synchronization clock PXIe DSTARC Steady logic high or
63. nd the signal will always be seen in the second clock cycle One useful feature of synchronous routing is that the signal can be propagated on either the rising or falling edge of the synchronization clock In addition the polarity of the destination signal can be inverted which is useful when handling active low digital signals Possible sources for synchronous routing include the following sources Any front panel PFI pin as single ended Any front panel PFI pin as LVDS Any PXI star trigger line PXI_STAR lt 0 16 gt Any PXI trigger line PXI_TRIG lt 0 7 gt Any PXIe DSTARB lt 0 16 gt e Global software trigger The synchronization clock itself 3 26 ni com NI PXle 6674T User Manual The synchronization clock for a synchronous route can be any of the following signals 10 MHz PXI CLK10 100 MHz PXIe CLK100 Clock Generation OCXO CLKIN One of two divided copies of any of the previously listed five signals The NI PXIe 6674T includes two clock divider circuits that can divide the synchronization clock signals by any power of 2 up to 512 Refer to Figures 3 4 and 3 5 for an illustration of how the NI PXIe 6674T performs synchronous routing operations National Instruments 3 27 Calibration This chapter discusses the calibration of the NI PXIe 6674T Calibration consists of verifying the measurement accuracy of a device and correcting for any measurement error The NI PXIe 6674T is factory ca
64. neration or from the PXIe_ DSTARA network e PFI lt 0 5 gt PFI_LVDS lt 0 2 gt Programmable Function Interface which can be individually configured for either single ended operation or LVDS operation In LVDS mode the connectors are paired and can be programmatically set as either inputs or outputs but not both simultaneously Refer to Figure 3 2 for a diagram showing the locations of these connections on the NI PXIe 6674T front panel Caution Connections that exceed any of the maximum ratings of input or output signals on the NI PXIe 6674T can damage the module and the computer NI is not liable for any damage resulting from such signal connections National Instruments 3 5 Chapter 3 Hardware Overview Hardware Features The NI PXIe 6674T performs two broad functions e Generating clock and trigger signals e Routing internally or externally generated signals from one location to another Table 3 3 outlines the function and direction of the signals discussed in detail in the remainder of this chapter Table 3 3 Signal Descriptions Signal Name Direction Description PXI_CLK10_IN Out This is a signal that can be used to provide the to chassis backplane with a reference 10 MHz signal from the system timing slot When a 10 MHz signal is connected to PXI_CLK10_IN the PXI Express chassis is required to derive PXI_CLK10 and PXIe_CLK100 from this reference Refer to the user manual
65. o export a clock signal from the NI PXIe 6674T to an external device or another system timing module The CLKOUT driver uses two separate circuits for driving CLKOUT one for low speed frequencies 50 MHz and below and one for high speed above 50 MHz The low speed driver uses 5 V CMOS logic with source impedance of 50 Q and is AC coupled The high speed driver produces an 800 mV y swing into a 50 Q load and is also AC coupled The sources available to be routed to CLKOUT differ depending on rather the low speed or high speed driver is used The sources available to the low speed driver are PXI_CLK10 OCXO and Clock Generation for generated frequencies 100 MHz and below Sources available to the high speed CLKOUT are Clock Generation and outputs from the PXIle DSTARA network through the PFI_ LVDS cross point switch NI Sync software will select the low speed or high speed driver automatically based on the source connected to CLKOUT O National Instruments 3 15 Chapter 3 Routing Signals Hardware Overview The NI PXIe 6674T has versatile trigger routing capabilities It can route signals to and from the front panel the PXI star triggers the PXI triggers and PXIe DSTARB PXIe DSTARC Figures 3 4 and 3 5 summarize the routing features of the NI PXIe 6674T The remainder of this chapter details the capabilities and constraints of the routing architecture Figure 3 4 High Level Schematic of NI PXle 6674T Signal Routing Architectur
66. o one technical support as well as exclusive access to online training modules at ni com self paced training NI also offers flexible extended contract options that guarantee your SSP benefits are available without interruption for as long as you need them Visit ni com ssp for more information Declaration of Conformity DoC A DOC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electromagnetic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification or contact your local office at ni com contact You also can visit the Worldwide Offices section of ni com niglobal to access the branch office websites which provide up to date contact information support phone numbers email addresses and current events B 2 ni com Glossary Symbol Prefix Value f femto 10 15 p pico 10 12 n nano 10 u micro 10 6 m milli 103 k kilo 103 M mega 106 G giga 10 Symbols percent plus or minus positive or plus negative or minus per 2 degree Q ohm A accumulator ADE asynchronous a part where numbers are totaled or stored application development environment a property of an event that occurs at an arbitrary time without synchronization to a reference clock O National In
67. odifications not expressly approved by National Instruments could void the user s right to operate the hardware under the local regulatory rules 1 The Declaration of Conformity DoC contains important EMC compliance information and instructions for the user or installer To obtain the DoC for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column Contents About This Manual National Instruments Documentation oooocoocccnonccoonacononccnnnononnncnnnnononnoronnarona conan ne ronnncnna non ix Related Documentation enraiar r S E SENEE ix Chapter 1 Introduction What You Need to Get Started viii iia Unpacking ninn Software Programming Choices ss Safety Informations aS ii A it Chapter 2 Installing and Configuring Tnstallino the SOftWare ia 2 1 Tnistalling the HardWare rito eresa minoria rro EKE iE EEES 2 1 Configuring the Modules mon meriiri aE E E E ENA 2 2 Chapter 3 Hardware Overview NI PXIe 6674T Front Panel Access LED ee ay Active LED aioin ennn Ean E e Site Maaieiees Mad Nahe die dockets COMME CTOTS AEE EEEE E E EE R patos pate ettees Hard ware Features io co 235 an E a Eeoa i E NE A e AE E E Generating and Routing Clocks seeseseesseseeeeessseserersesrererststsrerstststsrrersetrtresssreeeenenererees Clock Generation ninia ti PXI_CLK10 and PXTe CLK 100 ceeseeeecseeeeseneeesseseeecsaeesscnarecsassenecsesaee
68. ommercial light industrial and heavy industrial locations In Europe Canada Australia and New Zealand per CISPR 11 Class A equipment is intended for use only in heavy industrial locations A Note Group 1 equipment per CISPR 11 is any industrial scientific or medical equipment that does not intentionally generates radio frequency energy for the treatment of material or inspection analysis purposes Note For EMC declarations and certifications and additional information refer to the Online Product Certification section CE Compliance CE This product meets the essential requirements of applicable European Directives as follows e 2006 95 EC Low Voltage Directive safety e 2004 108 EC Electromagnetic Compatibility Directive EMC Online Product Certification To obtain product certifications and the Declaration of Conformity DoC for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column Environmental Management NI is committed to designing and manufacturing products in an environmentally responsible manner NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers For additional environmental information refer to the Minimize Our Environmental Impact web page at ni com environment This page contains the environmental regulations and directives with which NI compl
69. ooooncnocnoccoononnnacoononnonnono Eight SMA female 50 Q Front panel indicators Two tricolor LEDs green red and amber Wel Ghit sects ccceivedetvecsivedeleeten die cessesesgresice 349 g 12 3 oz Power Requirements SIs DoW Saltash A A IA 2 54 A max TIZ alta 2 25 A max S AU ss 0 A max Environmental Maximum altitude ccccccseseesceseeeeeeeseeeeees 2 000 m 800 mbar at 25 C ambient temperature Pollution Degree ceeesceecseeeceeseeeeeeeeenseeees 2 Indoor use only 1 Operation beyond 200 MHz is possible but performance is not guaranteed 2 Accuracy of frequency measurement is relative to the frequency accuracy of the reference counter source The frequency measure vi in NI Sync does not account for error from the reference source O National Instruments A 25 Appendix A Specifications Operating Environment Ambient temperature range Relative humidity range Storage Environment Ambient temperature range Relative humidity range Shock and Vibration Operating shock Random vibration Operating Nonoperating A 0 to 55 C Tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 Meets MIL PRF 28800F Class 3 low temperature limit and MIL PRF 28800F Class 2 high temperature limit 10 to 90 noncondensing Tested in accordance with IEC 60068 2 56 40 to 71 C Tested in accordance with IEC 60068 2 1 and TEC 60068 2 2 Meets MIL PRF 28800F Class 3 limits 5 to 95
70. or DAQ hardware oven controlled crystal oscillator a device that generates a fixed frequency signal An oscillator most often generates signals by using oscillating crystals but also may use tuned networks lasers or atomic clock sources The most important specifications on oscillators are frequency accuracy frequency stability and phase noise the measured resistance and capacitance between the output terminals of a circuit Programmable Function Interface phase locked loop the measure of the stability of an instrument and its capability to give the same measurement over and over again for the same input signal the amount of time required for a signal to pass through a circuit PCI eXtensions for Instrumentation An open implementation of CompactPCI Express that adds electrical features that meet the high performance requirements of instrumentation applications by providing triggering local buses and system clock capabilities PXI Express also offers two way interoperability with CompactPCI Express products PXI star PXIe_DStarA PXIe_DStarB PXle_DStarC R RTSI bus skew slave slot SMA synchronous system timing slot NI PXle 6674T User Manual a special set of single ended trigger lines in the PXI backplane for high accuracy device synchronization with minimal latencies on each PXI slot high speed differential signal paths that connect the system timing slot to each PXI Express peripheral slot u
71. ough PXIe DStarC to the PXIe DStarA network when sharing a clock signal or treat the PXIe DStarC as a trigger source Maximum operating frequency when used with the PXIe DStarA network ceeeeee 1 GHz Maximum operating frequency when used for triggering oooconccncononicnnonocnnanonnnno 200 MHz A 18 ni com Trigger Timing Asynchronous Trigger Delays and Skew NI PXle 6674T User Manual Table A 1 Asynchronous Trigger Delays and Skew Values Trigger Source Trigger Destination Typical Delay Typical Skewt Single Ended PFI Single Ended PFI 23 4 ns lt 5 ns Single Ended PFI LVDS PFI 22 4 ns lt 5 ns Single Ended PFI PXI Trigger 38 7 ns lt 1 5 ns Single Ended PFI PXI Star 26 8 ns lt 75 ns Single Ended PFI PXIe DStarB 23 2 ns lt 5 ns LVDS PFI Single Ended PFI 13 7 ns lt 5 ns LVDS PFI LVDS PFI 11 8 ns lt 5 ns LVDS PFI PXI Trigger 28 9 ns lt 1 5 ns LVDS PFI PXI Star 17 5 ns lt 75 ns LVDS PFI PXIe DStarB 13 8 ns lt 5 ns PXI Trigger Single Ended PFI 17 8 ns lt 5 ns PXI Trigger LVDS PFI 16 6 ns lt 5 ns PXI Trigger PXI Trigger 33 8 ns lt 1 5 ns PXI Trigger PXI Star 21 0 ns lt 75 ns PXI Trigger PXIe DStarB 15 9 ns lt 5 ns PXI Star Single Ended PFI 17 0 ns lt 5 ns PXI Star LVDS PFI 15 6 ns lt 5 ns PXI Star PXI Trigger 26 2 ns lt 1 5 ns PXI Star PXI Star 20 2 ns lt 75 ns PXI Star PXIe DStarB 16 0 ns lt 5 ns PXIe
72. outing Operations Sources Destinations lt 0 2 gt On Front Panel Backplane board PXI Star OCXO CLK PFI Trigger D STARB Ref E OUT lt 0 16 gt c 2 CLKIN Y c e PFI lt 0 5 gt re PFI LVDS Jeydeup MOINIIAO JEMPIEH sjuaun su Buonen 6L Table 3 9 Sources and Destinations for NI PXle 6674T Signal Routing Operations Continued Destinations PXI CLK 10 Y PXI CLK Y 100 PXI STAR lt 0 16 gt PXI TRIG lt 0 7 gt DSTARC lt 0 16 gt OCXO Y Clock Gen Y Global Software Trigger Backplane Sources Onboard Routing PXI_CLK10 PXIe_CLK100 OCXO or ClkGen is accomplished by setting the synchronization clock NI Sync Property Node to the desired clock source and then routing the synchronization clock as the source Route through the FPGA Route to PFI LVDS can be made through the FPGA when used as a trigger or through the PXIe DTARA network when used as a clock enue 1SN 17299 381Xd IN Chapter 3 Hardware Overview Using Front Panel PFls as Single Ended Inputs The front panel PFIs can receive external signals from 0 to 5 V They can be terminated programmatically with 50 Q resistances to match the cable impedance and minimize reflections Note Terminating the signals with a 50 Q resistance is recommended when the source is another NI PXIe
73. p to 17 peripheral slots Real Time System Integration bus the NI timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise synchronization of functions In a PXI or PXI Express system these are referred to as the PXI Triggers seconds the actual time difference between two events that would ideally occur simultaneously Inter channel skew is an example of the time differences introduced by different characteristics of multiple channels Skew can occur between channels on one module or between channels on separate modules intermodule skew a computer or peripheral device controlled by another computer the place in the computer or chassis in which a card or module can be installed sub miniature type A a small coaxial signal connector that features a threaded connection a property of an event that is synchronized to a reference clock the slot in a PXI Express system which can house a system timing module National Instruments G 5 Glossary T tctoQ thold ta TRIG trigger tsetup V VI G 6 ni com clock to output time hold time propagation delay time trigger signal a digital signal that starts or times a hardware event for example starting a data acquisition operation setup time volts virtual instrument Index A Access LED color explanation table 3 4 overview 3 4 Active LED color explanation table 3 5 overview 3 5
74. perature location A Caution Ifthe Access LED is observed to be solid red a hardware failure has been detected that may impact the performance of the NI PXIe 6674T Contact National Instruments for support 3 4 ni com NI PXle 6674T User Manual Active LED The Active LED indicates an error or phase locked loop PLL activity You can change the Active LED to amber unless an error overrides the selection Refer to Figure 3 2 for the location of the Active LED Q Tip Changing the Active LED color to amber is helpful when you want to identify devices in a multichassis situation or when you want an indication that your application has reached a predetermined section of the code Table 3 2 summarizes what the Active LED colors represent Table 3 2 Active LED Color Indication Active LED Color Status Off The 10 MHz PLL is not in use and no errors are present Green The 10 MHz PLL is active and locked Solid Amber The user can set the Active LED to amber through software Solid Red 10 MHz PLL is attempting to lock to the reference supplied on CLKIN Connectors This section describes the connectors on the front panel of the NI PXIe 6674T e CLKIN AC coupled 50 Q clock input CLKIN can be routed directly to PXI_CLK10_IN to the 10 MHz PLL to PXIe DSTARA or to the FPGA for use as a synchronization clock e CLKOUT AC coupled clock output CLKOUT can be sourced from the OCXO PXI CLK10 Clock Ge
75. r Manual routing signals front panel triggers using as LVDS triggers 3 21 using as single ended inputs 3 20 using as single ended outputs 3 20 overview 3 16 possible sources and destinations table 3 18 A 23 PXI star triggers 3 23 PXI triggers 3 22 types asynchronous 3 24 synchronous 3 25 RTSI signal names note 3 7 S safety specifications A 26 signal descriptions table 3 6 signal selection circuitry figure 3 17 signal source 3 17 possible sources table 3 18 A 23 software installing 2 1 programming choices overview 1 2 source possible sources table 3 18 A 23 signal 3 17 specifications CE compliance A 27 cleaning A 26 CLKIN characteristics A 2 electromagnetic compatibility A 27 environmental A 25 online product certification A 27 physical A 25 power requirements A 25 safety A 26 star triggers See PXI_STAR synchronization clock See also PXI TRIG PXI STAR synchronization clock overview 3 25 National Instruments 1 3 Index synchronous routing U overview 3 25 unpacking the device 1 2 possible sources and destinations 3 26 synchronization clock sources 3 27 V timing diagram 3 26 voltage thresholds programming 3 20 T terminating signals with resistors note 3 20 threshold voltage 3 20 trigger bus See PXI_TRIG l 4 nicom
76. rogram is the most effective way to increase application development proficiency and productivity Visit ni com training for more information The Skills Guide assists you in identifying the proficiency requirements of your current application and gives you options for obtaining those skills consistent with your time and budget constraints and personal learning preferences Visit ni com skills guide to see these custom paths Nloffers courses in several languages and formats including instructor led classes at facilities worldwide courses on site at your facility and online courses to serve your individual needs Technical Support Support at ni com support includes the following resources Self Help Technical Resources Visit ni com support for software drivers and updates a searchable KnowledgeBase product manuals step by step troubleshooting wizards thousands of example programs tutorials application notes instrument drivers and so on Registered users also receive access to the NI Discussion Forums at ni com forums NI Applications Engineers make sure every question submitted online receives an answer Software Support Service Membership the Standard Service Program SSP is a renewable one year subscription included with almost every NI software product including NI Developer Suite This program entitles members to direct access to NI Applications Engineers through phone and email for one t
77. s Log in to your National Instruments ni com User Profile to get personalized access to your services Services and Resources Maintenance and Hardware Services N helps you identify your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system Visit ni com services for more information Warranty and Repair All NI hardware features a one year standard warranty that is extendable up to five years NI offers repair services performed in a timely manner by highly trained factory technicians using only original parts at a National Instruments service center Calibration Through regular calibration you can quantify and improve the measurement performance of an instrument NI provides state of the art calibration services If your product supports calibration you can obtain the calibration certificate for your product at ni com calibration System Integration If you have time constraints limited in house technical resources or other project challenges National Instruments Alliance Partner members can help To learn more call your local NI office or visit ni com alliance National Instruments B 1 Appendix B NI Services For information about other technical support options in your area visit ni com services Training and Certification The NI training and certification p
78. sentative Module of PXI_CLK10 when OCXO is routed to PXI_CLK10_IN 60 4 A PXI_CLK10 with no reference used 44 ww 65 4 B NI PXle 6674T OCXO at PXI_CLK10_IN z AY 70 4 A C Resulting PXI_CLK10 with OCXO routed to PXILCLK10_IN AWAY T T T T T 1 10 100 1k 10k 100k 1M 2M Frequency Offset Hz 10 MHz PLL Reference frequency range from CIKIN ieesionnanado doin osado apnea sendos 1 MHz to 100 MHz in increments of 1 MHz Recommended ClkIn frequency oocicioininio 10 MHz Reference frequency required accuracy 1 5 ppm Reference Frequency Duty Cyecle 40 to 60 PLL Loop bandWidth ooooncccicnnnnnnnncnicnncncnnons 100 Hz 1 The PXIe backplane employs a PLL to phase lock PXI_CLK10 to the signal on PXI_CLK10_IN Asa result the phase noise of PXI_CLK10 above about 1 kHz offset is unchanged regardless of reference used 2 10 MHz PLL filter is designed for a 10 MHz phase detector frequency Any other reference frequency will default to a phase detector frequency of 1 MHz resulting in a slight degradation of PLL performance A 6 ni com NI PXle 6674T User Manual Figure A 6 shows the phase noise on a representative module of PXI_CLK10 when CLKIN is routed to PXI_CLK10_IN with and without the 10 MHz PLL measured in a NI PXIe 1082 chassis with low fan speed Figure A 6 Phase Noise on a Representative Module of PXI_CLK10 with CLKIN Routing to PXI_CLK10_IN 5
79. struments G 1 Glossary B backplane bus CLKIN CLKOUT clock CompactPCI D D A DAC DAQ DC DDS G 2 ni com an assembly typically a printed circuit board PCB with 96 pin connectors and signal paths that bus the connector pins PXI systems have two connectors called the J1 and J2 connectors the group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected An example of a PC bus is the PCI bus Celsius CLKIN isa signal connected to the SMA input pin of the same name CLKIN can serve as PXI_CLK10_IN or be used as a phase lock reference for the OCXO CLKOUT is the signal on the SMA output pin of the same name hardware component that controls timing for reading from or writing to groups a Eurocard configuration of the PCI bus for industrial applications digital to analog digital to analog converter an electronic device that converts a digital number into a corresponding analog voltage or current data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO devices plugged into a computer and possibly generating control signals with D A and or DIO devices in the same computer direct current dir
80. t only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation must be expected Pollution Degree 3 means that conductive pollution occurs or dry nonconductive pollution occurs that becomes conductive due to condensation You must insulate signal connections for the maximum voltage for which the product is rated Do not exceed the maximum ratings for the product Do not install wiring while the product is live with electrical signals Do not remove or add connector blocks when power is connected to the system Avoid contact between your body and the connector block signal when hot swapping modules Remove power from signal lines before connecting them to or disconnecting them from the product Operate the product at or below the measurement category marked on the hardware label Measurement circuits are subjected to working voltages and transient stresses overvoltage from the circuit to which they are connected during measurement or test Measurement categories establish standard impulse withstand voltage levels that commonly occur in electrical distribution systems The following is a description of measurement categories e Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage This category is for measurements of voltages from specially protected secondary circuits Such voltage
81. terference to radio and television reception or to experience unacceptable performance degradation install and use this hardware in strict accordance with the instructions in the hardware documentation and the DoC If this hardware does cause interference with licensed radio communications services or other nearby electronics which can be determined by turning the hardware off and on you are encouraged to try to correct the interference by one or more of the following measures e Reorient the antenna of the receiver the device suffering interference e Relocate the transmitter the device generating interference with respect to the receiver e Plug the transmitter into a different outlet so that the transmitter and the receiver are on different branch circuits Some hardware may require the use of a metal shielded enclosure windowless version to meet the EMC requirements for special EMC environments such as for marine use or in heavy industrial areas Refer to the hardware s user documentation and the DoC for product installation requirements When the hardware is connected to a test object or to test leads the system may become more sensitive to disturbances or may cause interference in the local electromagnetic environment Operation of this hardware in a residential area is likely to cause harmful interference Users are required to correct the interference at their own expense or cease operation of the hardware Changes or m
82. ule of various Clock Generation frequencies routed to ClkOut All Measurement made in an NI PXIe 1062 chassis with low fan speed and OCXO connected to PXI_CIk10_IN The phase noise performance of the clock generation circuitry varies depending on what elements are used to generate the requested frequency To generate frequencies above 300 MHz a PLL is used to multiply the DDS frequency up which results in increased phase noise versus when the DDS is used directly all frequencies below 300 MHz Figure A 9 Phase Noise Performance 80 85 4 A 300 0000000000 using the DDS 43944 B 300 0000000001 using the PLL ANA 90 95 7 100 105 110 1154 120 4 1254 130 4 135 7 140 4 145 150 dBc Hz _ A C I e l 5 10 100 1k 10k 100k 1M 2M Frequency Offset Hz O National Instruments A 11 Appendix A Specifications Figure A 10 shows the phase noise of various frequencies coming from the multiplying PLL Figure A 10 Phase Noise of Frequencies From the Multiplying PLL 0 A 300 MHz AAZ 754 B 500 MHz A AAN 80 5 c 1 GHz AAA 90 100 4 105 4 110 4 1154 120 1254 130 4 135 4 140 4 1454 150 T T T T T 5 10 100 1k 10k 100k 1M 2M dBc Hz Frequency Offset Hz A 12 ni com NI PXle 6674T User Manual At 50 MHz NI Sync software will automatically switch between the high speed and low speed ClkOut drivers T
83. up to a higher temperature than the ambient temperature around it there is a warm up time required to achieve the specified frequency accuracy For this reason to achieve the most stable operation of the OCXO it is desirable to avoid powering off the OCXO The OXCO used by the NI PXIe 6674T features electronic frequency control This allows the OCXO to be fine tuned by varying the control voltage to the OCXO The NI PXIe 6674T uses a 16 bit digital analog converter to give precise control of the tuning voltage While the tuning voltage can be varied by the user it is normally controlled automatically by software which sets it to the calibration tuning voltage The NI PXIe 6674T is calibrated during the manufacturing process and should be recalibrated annually to remove frequency error that accumulates over time such as crystal aging Refer to the MI PXTe 6674T Calibration Procedure at ni com calibration for more details The OCXO can also be routed to the CLKOUT SMA and be used as a trigger synchronization clock inside the FPGA CLKIN The NI PXIe 6674T allows the user to connect their own 10 MHz reference directly to PXI_CLK10_IN by using the CLKIN SMA on the front panel CLKIN is an AC coupled 50 Q terminated input to the NI PXIe 6674T In order to increase the amplitude of signals the CLKIN receiver can use the CLKIN circuitry features software enabled attenuation which when enabled will attenuate the input signal by a factor of five NI

NI PXIe-6674T User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents