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1. ol o olo o o Ro 0 Cursor position oO 0 Oj HH 0 OOH H o E o EE 0000 11 1 Notes 1 Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 3 bits 8 types 2 CGRAM address bits 0 to 2 designate the character pattern line position The 8th line is the cursor position and its display is formed by a logical OR with the cursor Maintain the 8th line data corresponding to the cursor display position at 0 as the cursor display If the 8th line data is 1 1 bits will light up the 8th line regardless of the cursor presence 3 Character pattern row positions correspond to CGRAM data bits 0 to 4 bit 4 being at the left 4 As shown Table 5 CGRAM character patterns are selected when character code bits 4 to 7 are all 0 However since character code bit has no effect the display example above can be selected by either character code or 08H 5 1 CGRAM data corresponds to display selection and 0 to non selection Indicates no effect 186 HITACHI HD44780U Table 5 Relationship between CGRAM Addresses Character Codes DDRAM and Character Patterns CGRAM Data cont For 5 10 dot character patterns Character Codes Character Pa
2. Left shift display 4 4C 4D 4 eee Right shift display c The relation between display position and DD RAM Since the increase can be 8 digits x 2 lines for each ad address when the number of display digits is increased ditional HD44100H up to 40 digits x 2 lines can be dis by using one 044780 and two or more HD44100H s played by connecting 4 HD44780 s externally can be considered an extension of b 12 3 4 5 6 7 8 9 1011 12 13 4 15 16 17 18 19 20 33 34 35 36 37 38 39 40 display position 1 1 t line 100 0102 031 04 05106107 08109 DD RAM address 2 line 13041722143 34145 46147 48 bud HD44780 display HD44100 1 HD44100H 2 HD44100H 4 display 3 display 4 Display position and DD RAM address for Character a 5 8 eL PIT BE DD RAM address _ ont ol 1 TUS 04 06 Note Shift display is as same as that a 3 char x 2 line type e Display position and DD RAM address for 1 2 3 4 5 6 8 9 10 11 12 13 M 15 16 display position 07 28 09 0B 0 00 OE OF DD RAM address 42 43 44 4A 4B 4C mn a 3 line I0 11 2113114115 16 21 18 119 tA IB IC ID IF i
3. M nn 2 Busy flag When the busy is 71 the 44780 is in the internal operation mode and the next instruction will not be ac cepted As Table 4 shows the busy flag is output to 08 when RS 0 and R W 1 The next instruction must be written after ensuring that the busy is 0 Higher order bits Lower order bits m ACO Hexadecimal Hexadecimal 1 line display 0 1 2 3 4 3 4 5 Address counter The address counter assigns addresses DD and RAMs When an instruction for address is written in IR the address information is sent from IR to AC Selection of either DD CG RAM is also determined concurrently by the instruction After writing into or reading from DD or CG RAM dis play data AC is automatically incremented by 1 or decremented by 1 AC contents are output 08 DB when RS 0 and R W 1 as shown in Table 4 Display data RAM DD RAM The display data RAM DD RAM stores display data re presented in 8 bit character codes Its capacity is 80 x 8 bits or 80 characters The display data RAM DD RAM that is not used for display can be used as a general data RAM Relations between DD RAM addresses and posi tions on the liquid crystal display are shown below The DD RAM address App is set in the Address Counter AC and
4. Sets interface data length 37 us set DL number of display lines N and character font F Set 0 0 0 1 ACG ACG ACG ACG Sets address 37 us CGRAM CGRAM data is sent and address received after this setting Set 0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address 37 us DDRAM DDRAM data is sent and address received after this setting Read busy 0 1 AC Reads busy flag BF us flag 8 indicating internal operation is address being performed and reads address counter contents 191 HITACHI HD44780U Table 6 Instructions cont Execution Time Code max when f or Instruction RS R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Description fosc is 270 kHz Write data 1 0 Write data Writes data into DDRAM or 37 us to CG or CGRAM tapo 4 Us DDRAM Read data 1 1 Read data Reads data from DDRAM or 37 us from CG or CGRAM Ls 8 DDRAM D 21 Increment DDRAM Display data RAM Execution time 0 0 Decrement CGRAM Character generator changes when S 1 Accompanies display shift RAM frequency changes S C 1 Display shift ACG CGRAM address Example S C 0 Cursor move ADD DDRAM address When f or f is R L 1 Shift to the right corresponds to cursor 250 kHz R L 0 Shift to the left address 270 DL 1 865 DL 0 4 bits AC Address counter used for 37 8 40 us N 1 2lines N 0 1 both DD and CGRAM F 1 5x 10 dots F 2 0 5x8 dots addresses B
5. dub c ee LCD V Drover Sl mm PRI Driver 1 51 Vs NS Sea M A ur 1 jJ RR RE TORT A es ann 1 Fig 1 Driver circuit block diagrem ETTINGER 2 2 Interfacing to MPU In the HD44780 data can be sent in either 4 bit 2 operation or 8 bit 1 operation so it can interface to both 4 and 8 MPU s 1 When interface data is 4 bits long data is transferred using only 4 buses DB DB are not used Data transfer between the HD44780 and the MPU completes when 4 bit data is transferred twice Data of the higher order 4 bits contents of when interface data is 8 bits long is transferred first then the RS R W lower order 4 bits content of OB DB when interface data is 8 bits long is transferred Check the busy flag after 4 bit data has been transferred twice one instruc tion A 4 bit 2 operation will then transfer the busy flag and address counter data XT Rs DULL DBs DX DBs CUR XUL DB XT Re 2 Insiructio write flay and address counter read Data register read Fig 2 4 bit data transfer example 2 When interface data is B long data is transferred using the 8 data buses of DB DB 2 3 Interface to MPU 1 Interface to 8 bit MPU t Tien Buss
6. EPROM Hitachi Yes Art work Yes Mass production Note For a description of the numbers used in this figure refer to the preceding page Figure 7 Character Pattern Development Procedure 181 HITACHI HD44780U e Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM The HD44780U character generator ROM can generate 208 5 x 8 dot character patterns and 32 5 x 10 dot character patterns for a total of 240 different character patterns Character patterns EPROM address data and character pattern data correspond with each other to form a 5 x 8 or 5 x 10 dot character pattern Tables 2 and 3 Table 2 Example of Correspondence between EPROM Address Data and Character Pattern 5 x 8 Dots EPROM Address Data LSB A11A10A9 A7 5 A4 A2 A1 AO 0403020100 O O a a O O O O O 2a O o mu o o OO O 4 Cursor position 0000 a OO O o O O O O O O O O O O O O O O O Line position Notes 1 EPROM addresses A11 to A4 correspond to a
7. 0 o o ol ooo 4 Cursor position 2 a O O o o 5 Line position EPROM addresses A11 to correspond to a character code EPROM addresses to 0 specify a line position of the character pattern EPROM data O4 to OO correspond to character pattern data Alit display position black corresponds to 1 4 2 3 4 EPROM data O5 to O7 must be specified as 0 5 6 Line 11 and the following lines must be blanked with Os for a5 x 10 dot character fonts 183 HITACHI HD44780U Table 4 Correspondence between Character Codes and Character Patterns ROM Code A00 Upper 4 bm sie 0000 001 oo10 0011 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CG e jab ATZE wee o ma S ey AC MIC Se ee e ee dec ge TEE fer eee ee wow s qRTLuS en ee ww e LE _ eos e ERNE ew o A a E en ee CO RURAL EE
8. Note 1 Note 2 i 7 Tm MMM i H Clears all d splay and returns the display 0 0 0109 0 0 0 1 cursor to the home position 82 us 1 64 ms 120 us 49 ms Address 0 l 1 1 x Returns the cursor to the home Address 0 Also returns the display being shifted to the original 40 1 6ms 120 us 48 ms Rexnhome 0 0 010 0 position DO RAM contents remain unchanged Sets the cursor move direction and Eawy mode specifies or not to shift the display i 0 0 0 0 0 0 011 4 ser nr These operations are performed 120 during data write and read 1 H i 1 1 d H 3 Sets ON OFF of all display 0 N Day ON OFF contro 0 0 0 0 0 011 cursor ON OFF and blink of 40 us 120 us i cursor position character 8 1 1 2 m j Conor ond Moves the cursor and shifts the diy shift 0 750 0 0 Q 1 S C 27 1 display without changing DO RAM 40 120 us j contents i 1 1
9. V4 V5 and each common signal pin COMI to COM 16 RSEG is the resistance between the power supply pins V2 V5 and each segment signal pin to SEG40 14 The following graphs show the relationship between operation frequency and current consumption 5V 3V 1 8 1 8 1 6 1 6 1 4 1 4 1 2 1 2 x gt 10 ma 1 0 8 0 8 8 0 8 0 6 WP 0 6 max 0 4 0 4 0 2 0 2 typ 0 0 0 0 0 100 200 300 400 500 0 100 200 300 400 500 fosc OF KHz fosc OF fep KHz 15 Applies to the pin 16 Each COM and SEG output voltage is within 0 15 of the LCD voltage V2 V4 V5 when there is no load 223 HITACHI HD44780U Load Circuits Data Bus DBO to DB7 For 4 5 to 5 5 V Test Vec 5V 9 point O 90 pF 4 11 kQ y 1520749 diodes External Driver Control Signals CL1 CL2 224 Test point O 30 pF HITACHI For Vcc 2 7 to 4 5 V Test point Q 50 pF HD44780U Timing Characteristics VIH1 VIH1 DBO to DB7 VIL1 Valid data VIL 1 lcycE Figure 27 Write Operation 080 to DB7 VOL Valid data VOL1 lcycE Note VOL1 is assumed to be 0 8 V at 2 MHz operation Figure 28 Read Operation 225
10. 4 Y 3 nr 2 1 Q8 E Fem iam 4 1 Hec wes RS ARES ea 5 a mn INS mn ET ne iM Ta AA LBS ESI e 6 T lake MARBLE DE 5 LCD MODULE DV series DV 1 61 00 16 chars x 1 line ABSOLUTELY MAXIMUM RATINGS Ls mw fee 12 09 Ee ad Ce i ow DIMENSION OUTLINE Anschlu LED Version 7 5 Ohm an Anode VR 10K 20 m m Supply Voltage for Voo vss 0 0 Input High Voltage _ 2 2 Ve V Supply Voltage for LCD Driver Voo ver 135 Input Low vu v Temp 0 Output tow Voltage va 94 Current voo s 0a 39 ma TN STN Reflective EL LED Backlight ELECTRICAL CHARACTERISTIC REFLECTIVE TYPE 10 29 Examples Temperature Compensation Circuits For Extended Temperature LCM Reference Data Figure 1 1 16 Duty 1 4 Bias Voo Module equivalent load Module RL Module equivalent toad DV series Befehlssatz Display clear Display ein aus Cursor Display shift CG RAM address set DD RA
11. Data set up time la 300 Data hold time ee 300 M delay time 1000 1000 Clock rise fall time t 100 Power Supply Conditions Using Internal Reset Circuit Item Symbol Min Typ Max Unit Test Condition Power supply rise time lc 0 1 10 ms Figure 30 Power supply off time 1 220 HITACHI Electrical Characteristics Notes 1 All voltage values are referred to GND 0 V Voc 1 V1 A v5 1 CC 77 Pin MOS without pull up A PMOS NMOS pull up MOS V5 V1 A215V lt 0 25 x A 2 V2 gt V3 gt 4 gt 5 must be maintained For die products specified up to 75 For d e products specified by the die shipment specification The following four circuits are I O pin configurations except for liquid crystal display output Pins RS R W MOS with pull up Voc Voc 3 E PMOS J PMOS pull up MOS NMOS Hr Voc T input circuit PMOS eo LoL m NMOS Vcc NMOS PMOS I of Data HD44780U The conditions of V1 and V5 voltages are for proper operation of the LSI and not for the LCD output level The LCD drive voltage conditi
12. COM1 COM8 SEG1 SEG40 Example of a 5 x 8 dot 8 character x 1 line display 1 4 bias 1 8 duty cycle HD44780 COM1 Leos 11 SEG SEG40 Example of a 5 x 10 dot 8 character x 1 line display 1 4 bias 1 11 duty cycle Figure 20 Liquid Crystal Display and HD44780 Connections 201 HITACHI HD44780U Since five segment signal lines can display one digit one HD44780U can display up to 8 digits for a 1 line display and 16 digits for a 2 line display The examples in Figure 20 have unused common signal pins which always output non selection waveforms When the liquid crystal display panel has unused extra scanning lines connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state Figure 21 HD44780 Example of a 5 x 8 dot 8 character x 2 line display 1 5 bias 1 16 duty cycle Figure 20 Liquid Crystal Display and HD44780 Connections cont Cursor FR 5 x 8 dot 5
13. ey 1 i t i Sets interface data length DL Fuon set 0 0 0 0 t DULIN 5 i number of display lines 1 and 40 120 character font i Sets the CG RAM address RAM 120 AcG data 15 sent and received after this setting Sets the DO RAM address DD RAM ADD data 15 sent and received after this setting 4 CUP Reads Busy BF indicating 0 1 BF internal operation is being performed b address and reads address counter contents RR Wee data to CG 1 0 Write Data RAM mn 0 00 re ne ______ Read data i BAM 10 Chor 1 A Dita 27 data from DD DO RAM E re SE UO Increment 1 1 0 0 Decrement 1 i DO RAM Display data Execution time changes when 5 x Accompanies display shift CG RAM Character generator RAM frequency changes i 5 1 Display shift S C 0 Cursor move CG RAM address Example R L 1 Shift to the right OD RAM address When fosc is 270 kHz RIL O Shit to the teft Corresponds cursor DU Bow OL 0 Abits address S 250 N l 2unes N 0 I Mine
14. ug ee es ex ee ee ja exe TELS Ga ee er 345 ex e Be es he ne er Do es ceo N o 1 Note The user specify any pattern for character generator 184 HITACHI HD44780U Correspondence between Character Codes and Character Patterns ROM Code A02 Table 4 wo e DR eet Ee s o 4 4 xxxx0101 T T ST A i i on ee Too dde gt 0 E cce ale LT 5 0001 1 000 1 100 185 HD44780U Table 5 Relationship between CGRAM Addresses Character Codes DDRAM and Character Patterns CGRAM Data For 5 X 8 dot character patterns Character Codes Character Patterns DDRAM data CGRAM Address CGRAM data T 0 5 4 3 2 T 0 5 43 2 76 5 4 3 2 1 0 High Low High Low High Low A Character pattern 1 0000 000 Cursor position lt Character 0000 001 pattern 2
15. Turns on display and cursor Entire display is in space mode because of initialization Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD CGRAM Display is not shifted Writes H The cursor is incremented by one and shifts to the right 209 HD44780U Table13 Bit Operation 8 Digit x 2 Line Display Example with Internal Reset Step Instruction No RS R W 087 DB6 DB5 DB4 DB2 DB1 Display 1 210 Power supply on the HD44780U is initialized by the internal reset circuit Function set 0 0 0 0 1 1 1 Display on off control 0 0 0 0 0 0 1 1 1 0 Entry mode 0 0 0 0 0 0 0 1 1 0 Write data to CGRAM DDRAM 1 0 0 1 0 0 1 0 0 0 Write data to CGRAM DDRAM 1 0 0 1 0 0 1 0 0 1 Set DDRAM address 0 0 1 1 0 0 0 0 0 0 HITACHI HITACHI_ HITACHI Operation Initialized No display Sets to 8 bit operation and selects 2 line display and 5 x 8 dot character font Turns on display and cursor All display is in space mode because of initialization Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD CGRAM Display is not shifted Writes H DDRAM has already been selected by initialization when the power was turned on The cursor is incremented by one and shifted to the right
16. moxmsxmo sesser orri Lees 5x9 ote ssesisocreo eet Ru L Dviene 622x179 295555 o oe Dues sxe 100 295x555 otre n exe ovino 614x250 225x475 _ 2020 5 7 1800 400 100 1490x230 600x988 5 0 ax 5x8 cas reor EET dv2e200 5x8 dois 945x100 320 555 5 0 KZ t mantso aanas F oone o L 1 x2 ov oo 15898 weoxsssxio 1540x165 320x555 0 5 0 for extended temperature LCD Twist nematic STN Supper twist nematic Extended temperature Reflective type EL with EL backlight LED with LED backlight DV 16252 13 Lt m ee ere DV 1623 VEU AS MEAE Meg Ye i gg eS RE 1 n x en i nn kj P i ORO RGR RSEN 24 CHARACTERS 2 LINES E DATA LISTON LCD MODULE HA sod CM 96 Www nn ur r e DV 20220 DV 24200 Consumption Control Method
17. 7 1 No data is displayed Crosstalk too No data is displayed Crosstalk too 15 the power supplied Vo and Supply the power Connect Vo to Vss then the power 15 supplied Is display crosstalk mode Yes Correct it Are interface pins set correctly in order Since is possible to be destroyed correct it immediately Is display crosstalk mode Y es No Is the supply current flown If so ICs and resistor are heated several times of its specified value dii Yes Within the Is the power ON sequence This does not apply to the specified value Turn the first side and case of a single power supply then the side Does fall or deviation OK exist in 2ebra inverse Yes _ e Turn on the power first from No the and then the side Reas After replacing check if the actual part 15 faulty Is display crosstalk made Is the current restored to normal conditions Still abnormal ___ EEE N ETTINGER 7 2 The system cannot be initialized or it is unstable The system cannot be initialized or it is unstable 15 the system initialized as described in the manual lof Is the systern operated while making a BUSY check make it operate after waiting for 5 times of the
18. Writes 1 Sets DDRAM address so that the cursor is positioned at the head of the second line HD44780U Table13 Bit Operation 8 Digit x 2 Line Display Example with Internal Reset cont Step Instruction No RS R W 087 DB6 DB5 DB4 DB3 DB2 1 DBO Display 9 Write data to CGRAM DDRAM HITACHI 1 0 0 1 0 0 1 1 0 1 M_ 10 11 Write data to CGRAM DDRAM HITACHI 1 0 0 1 0 0 1 1 1 1 MICROCO 12 Entry mode set HITACHI 0 0 0 0 0 0 0 1 1 1 MICROCO 13 Write data to CGRAM DDRAM ITACHI 1 0 0 1 0 0 1 1 0 1 ICROCOM 14 15 Return home HITACHI 0 0 0 0 0 0 0 0 1 0 MICROCOM HITACHI Operation Writes M Writes O Sets mode to shift display at the time of write Writes M Display is shifted to the left The first and second lines both shift at the same time Returns both display and cursor to the original position address 0 211 HD44780U Initializing by Instruction If the power supply conditions for correctly operating the internal reset circuit are not met initialization by instructions becomes necessary Refer to Figures 25 and 26 for the procedures on 8 bit and 4 bit initializations respectively Wait for more than 15 ms Wait for more than 40 ms after Vcc rises to 4 5 V after Vcc rises to 2 7 V RS R WDB7 DB6 DB5 DB4 DB3DB2 DB1 DBO BF cannot be checked before this instruction Uo cd 20 d soe ee 5 Function set Interface is
19. taDD 5 fep or fosc ETTINGER 2 When interface is 4 bits long Wait more than 15 ms after Vpp rises to 4 5V RS DB DB DB 0 0 0 0 1 Wait more than 4 1 ms RS RW DB DB DB DH 0 0 0 0 1 1 Wait more than 100 RS RW DB DB DB 0 0 0 0 1 1 RS RW DB DB DR 0 Initialization ends BF cannot be checked before this instruction Function set interface is 8 bits long BF cannot be checked before this instruction Function set interface is 8 bits long BF cannot be checked before this instruction Function set interface is 8 bits long BF can be checked after the following instructions When BF is not checked the waiting time between instructions is longer than the execution instruction time See Table 2 Function set set interface to be 4 bits long Interface is 8 bits long function set display OFF Interface is 4 bits long Specify the number of display lines and character display ON font The number of display lines and character font cannot be changed afterwards entry mode set P pee CTTINGER Table 2 Instructions Ce a aaraa py gap AA lt 999 i Code i Execution time Execution time j wetruction r Description when fosc is when fosc is 165 RW DB oss 063 082 222 1650 kHz
20. Fully compatible within the HD44780S 1 MHz FP 80 FP 80A HITACHI 1 MHz when V 2 MHz when V 5V FP 80B TFP 80F HD44780U HD44780U Pin Arrangement FP 80B 80 SEG23 79 SEG24 78 SEG25 77 SEG26 76 SEG27 75 SEG28 74 SEG29 73 SEG30 72 SEG31 71 SEG32 70 SEG33 69 SEG34 68 SEG35 67 SEG36 66 SEG37 65 SEG38 80 Top view 171 HITACHI 59 COM15 58 COM14 57 56 COM12 54 COM10 53 9 52 9 80 10 gt gt OO O O olo tos 48 COMA 46 COM2 45 HD44780U Pin Arrangement TFP 80F HD44780U 5 19 2 5 18 3 SEG17 4 5 16 5 SEG15 6 SEG14 7 SEG13 8 172 HITACHI HD44780U Pad Arrangement Chip size 4 90 x 4 90 mm Coordinate Pad center Origin Chip center Padsize 114x 114 um HD44780U HD
21. HITACHI HD44780U Figure 29 Interface Timing with External Driver 2 7 V 4 5 V tree 1 0 1 ms lt trec x10 ms torr gt 1 ms torr compensates for the power oscillation period caused by momentary power supply oscillations Specified at 4 5 V for 5 V operation and at 2 7 V for 3 V operation For if 4 5 V is not reached during 5 V operation the internal reset circuit will not operate normally In this case the LSI must be initialized by software Refer to the Initializing by Instruction section Figure 30 Internal Power Supply Reset 226 HITACHI
22. hexadecimal 40 41 42 43 44 67 Figure 4 2 Line Display Display position DDRAM address For shift left For shift right 6 Figure 5 2 Line by 8 Character Display Example 178 HITACHI HD44780U Case 2 For 16 character x 2 line display the HD44780 can be extended using one 40 output extension driver See Figure 6 When display shift operation is performed the DDRAM address shifts See Figure 6 Display position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DDRAM 000102 03 04 05 06 07 0809 OF address 40 4142 43 44 45 46 4748494 4 4 4 04 4 Y Y HD44780U display Extension driver display For 01 02 03 04 05 06 07 0BOCODOE shift left 41 42 43 44 45 46 47 4B4C4D4E For 00 01 02 03 04 05 09 0 shift right 67 40 4142 43 44 45 49 4 4 4 Figure 6 2 Line 16 Character Display Example 179 HITACHI HD44780U Character Generator ROM CGROM The character generator ROM generates 5 x 8 dot or 5 x 10 dot character patterns from 8 bit character codes Table 4 It can generate 208 5 x 8 dot character patterns and 32 5 x 10 dot character patterns User defined character patterns are also available by mask programmed ROM Character Generator RAM CGRAM In the character generator RAM the user can
23. more 4 bit operations then transfer the busy flag and address counter data e For 8 bit interface data all eight bus lines DBO to are used R7 X __ 186 X 182 Xaco 2 6 2 IR7 185 X XDR9 RA X IRo Instruction register IR Busy flag BF and Data register DR write address counter AC read read Figure9 4 Bit Transfer Example 189 HITACHI HD44780U Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the HD44780U when the power is turned on The following instructions are executed during the initialization The busy flag BF 15 kept in the busy state until the initialization ends BF 1 The busy state lasts for 10 ms after rises to 4 5 V 1 Display clear 2 Function set DL 1 8 bit interface data N 0 I line display 0 5 8 dot character font 3 Display on off control D 0 Display off 0 Cursor off 0 Blinking off 4 Entry mode set I D 1 Increment by 1 0 No shift Note the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met the internal reset circuit will not operate normally and will fail to initialize the HD44780U For such a case initial ization must be perf
24. time 15 the order of interface pins correct Signal system pins RS A W E and D8 No Still no good Good Is the assignment of RS or the setting of data correct Yes Correct it good Operation OK Try to replace it with another LCM There is a possibility of malfunction in the LCM Not caused by LCM Recheck the circuit and software Stil no good 7 3 The character display is erroneous The character display is erraneout When missed sccording to certain rule The character missing OCCULE every 4 characters for instance Characters are displayed but messing in some places Procead to Exampie input D solay When missed without any rule character ia missed random some where different each time HITACHI Proceed to uncertain that from where the 1st character starts Proceed 10 4 Address character other than specified are teveritten Proceed 3 5 Even when the 1st line becomes full in a 2 display LCM the line i not fed to the 2nd ling Same in a 4 line display LCM 9 When the fst line becomes Il in 4 line display the cnaracter writing starts from the line Although data 8 not displayed even if input found to b
25. 0 Sets 8 bit operation and selects 2 line display and 5 x 7 dot character font oo Turns on display and cursor All display is in space mode because of initialization Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD CG RAM Entry Mode 0 0 0 1 1 0 Display is not shifted i Write The DD RAM has already been selected by initialization when the power is The cursor is incremented by one and shifted to the right Write Data CG RAM DO RAM HITACHI ingri 1 0 0 1 0 1 90 1 Et uM Set DD RAM Address HITACHI Sets RAM address so that the cursor is 0 0 1 1 0 000 0 0 BEE positioned at the head of the 2nd line Write Data to CG RAM DD RAM HITACHI 1 0 0 1 0 0 1 EUN Write Data to CG RAM DD RAM HITACHI Writes 0 0 0 1 0 0 4 1 1 mn 0 0 9 1 1 1 Sets mode for display shift at the time of write ites Display is shift he right Write Data to RAM DD RAM TA CH He PEDI fotha right 0 1 0 0 1 The first and second lines shift are operated 1 CROCOM SEG 22 Write Data to CG RAM DO RAM 1 0 0 1 0 0 1 0 0 0 Return Home Returns both display and cursor to the original position Address 0 0 0 0 EITINGER 1 Precaution programming Instruction of function set Perform the func
26. 1 The display moves to the left 17 Cursor or display shift Shifts the display and cursor 0 0 0 0 0 1 1 1 position to the right 18 Cursor or display shift Essen Shifts the display and cursor 0 0 0 0 0 1 0 1 x position to the right 19 Write data to CGRAM DDRAM Writes M ICROCOM _ 1 0 0 1 0 0 1 1 0 1 20 21 Return home Tan Returns both display and cursor 0 0 0 0 0 0 0 0 1 0 u to the original position address 0 208 HITACHI HD44780U Table 12 4 Bit Operation 8 Digit x 1 Line Display Example with Internal Reset Step Instruction No RS R W DB7 DB6 DB5 DB4 Display Operation 1 Note Power supply on the HD44780U is initialized by the internal reset circuit Function set 0 0 0 0 1 0 Function set 0 0 0 0 1 0 0 0 0 0 Display on off control 0 0 0 0 0 0 0 0 1 1 Entry mode set 4 0 0 0 0 0 0 0 0 0 1 1 0 Write data to CGRAM DDRAM 1 0 0 1 0 0 1 0 1 0 0 0 The control is the same as for 8 bit operation beyond step 6 HITACHI Initialized No display Sets to 4 bit operation In this case operation is handled as 8 bits by initializa tion and only this instruction completes with one write Sets 4 bit operation and selects 1 line display and 5 x 8 dot character font 4 bit operation starts from this step and resetting is necessary Number of display lines and character fonts cannot be changed after step 3
27. 8 bits long Wait for more than 4 1 ms RS R WDB7 DB6 DB5 DB3 DB DB1 DBO BF cannot be checked before this instruction UM NEC MC Function set Interface is 8 bits long Wait for more than 100 us RS R WDB7 DB6 DB5 084 DB3 DB2 DB1 DBO BF cannot be checked before this instruction ud US D Function set Interface is 8 bits long BF can be checked after the following instructions When BF is not checked the waiting time between instructions is longer than the execution instuction time See Table 6 Function set Interface is 8 bits long Specify the RS R WDB7 086 DB5 084 DB3 DB2 DB1 DBO number of display lines and character font 0 0 0 1 1 number display lines and character font 0 0 0 cannot be changed after this point 0 0 0 0 1 0 0 0 0 0 1 Display clear Entry mode set Initialization ends Figure 25 8 Bit Interface 212 HITACHI HD44780U Power on Wait for more than 15 ms Wait for more than 40 ms after Vcc rises to 4 5 V after Vcc rises to 2 7 V RS RW DB7 DB6 DB5 284 BF cannot be checked before this instruction 0 0 0 0 1 1 Function set Interface is 8 bits long Wait for more than 4 1 ms RS RW DB7 DB6 DB5 BF cannot be checked before this instruction 0 0 0 0 1 1 Function set Interface is 8 bits long fo
28. Busy flag signal is output through DB as shown in Table 3 when RS 70 R W 1 and Enable 717 Input of unidentified instruction code Undefined instruction code of 44780 only as follows RS RW DB DB 0 0 0 Others are included to defined instruction When the undefined instruction code is loaded to HD44780 it accepts the code but does not change the internal states RAM and other status of Flags Busy state however continues for maximum 40 us by the acceptance of the code Table 3 The relation between the operation and the combination of RS R W NL J e a M JP OPERATION Write instruction code Read busy flag and address counter Write data Read data When performing data and instruction code by 4 bit transfer RS R W every time ETTINGER 7 How to check trouble Follow the flowchart below to check errors Error analysis flowchart Error analysis flow 15 display made Crosstalk included Immediately after POWER ON Proceed to 2 Crosstalk is output only in one line in display of 2 4 lines for example No Proceed to 72 Yes 15 character display erroneous in sequence for instance Is the system initialized or stabilized Yes M Proceed to G3 No No Proceed to Yes Are there any other erroneous operation Yes Proceed to 7 5 RN ETTINGER ETTINGER
29. The HD44780 functions must be set by Function Set data entered first can be output when the return home prior to display Since the display data RAM can store operation is performed B bit operation B digit 1 line display example using internal reset m 44 in tiali po 4 Power supply ON 780 15 initialized by the internal reset circuit i Function Set Sets to 8 bit operation and selects 1 line display i AS R W DB D6 lines and character font Number display lines and character fonts cannot be changed hereafter aaa Display ON OFF Controt 4 Turns on display and cursor Entire display is 0 0 0 Q 1 1 1 0 in space mode because of initialization I Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the RAM Display is not shifted Write H The DO RAM has already been selected by initialization when the power is turned on The cursor is incremented by one and shifted to the right r Entry Mode Ser 0 0 0000011 o E g i Write Data to RAM DD RAM 1 0 0 1 0 1 t HI Writes 717 i 1 l 1 1 0 0 1 0 0 1 0 0 1 Writes I E
30. busy BF that indicates the system is now internally operating by a previously received instruction BF 1 indicates that internal operation is in progress The next instruction will not be accepted until BF is set to 0 Check the BF status before the next wire opera tion At the same time the value of the address counter ex pressed in binary AAAAAAA is read out The address counter is used by both CG and RAM addresses and its value is determined by the previous instruction Address contents are the same as in Items 7 and 8 10 Write data to CG or OD RAM RS RW OB OB Higher Lower E Order Bits Order Bits Writes binary 8 bit data 00000000 to the CG or the DD RAM Whether the CG or DD RAM is to be written into is determined by the previous specification of CG RAM or DD RAM address setting After write the address is automatically incremented or decremented by 1 according to entry mode The entry mode also deter mines display shift ETTINGER 11 Read data from or DD RAM RS RW DB Higher Lower Order Bits Order Bits Reads binary 8 bit data DDDDDDDD from the CG or DD RAM The previous designation determines whether the CG or DD RAM is to be read Before entering the read instruction you must execute either the CG RAM or DD RAM address set instruction If you don t the first read data will be invalidated When serially executing the rea
31. driven by the voltage that ts equal to Vo when supplying power for liquid crystal display drive to terminal Since suitable voltage of power supply for LCD shifts cording to temperature change adjust supplying power to by referring to Fig 9 or Fig 10 ___ O ET ETTINGER 1 Example of variable driving voltage by a variable resistance VR The driving voltage can be changed by VR to compensate the influence of surrounding temperature GND Hecemmended Vic value Fig 9 Variable driving voltage circuit ee DECOR C a Recommended driving voltage Vno Vin V V V aM 2 Example of a thermal compensator circuit When setting the voltage refer to Table 1 Thermistor 15 75 C Theranstoc Ta 25 C Fig 10 Example of a thermal compensator circuit Typical circuit parameter R2 kQ _ R3 1 8 25 22023700 48 22 2 8 1 0 NE 0 402 2 mm 1 25 39 4 5 2 2 352 0 3 50 3 3 4 4 5 0 0 1 153 0 1 nn nn 2 2 e 4 Initialization 4 1 Initializing by internal reset circuit The HD44780 automatically initializes resets when power is turned on using the internal reset circuit The following in structions are executed in initialization The busy flag BF is kept in busy state until initialization ends BF 1 The
32. is represented in hexadecimal DD RAM address 4 79 80 display position 09 01 02 03 4F DD RAM address When the display characters are less than 80 the display begins at the head position using one HD44780 are displayed as 1 2 3 4 5 6 7 l line 00 01 address moves DUOODOLDDOUUDLD 8 When the display shift operation is performed the DD For example 8 characters display position DD RAM address Left shift display Right shift display ee b 16 character display using an 044780 and an HD44100H is as shown below 1 2 3 4 5 6 7 8 9 10 It 12 13 14 15 16 display position HD44780 display HD44100H display When the display shift operation is performed the DD RAM address moves as 0A 0B RE 06 07 08 09 0D 0 oF 10 Left shift display Right shift display The relation between display position and DD RAM Since the increase can be 8 digits for each additional address when the number of display digits is increased HD44100H up to 80 digits can be displayed by externally through the use of one HD44780 and two or more connecting 9 44100 5 44100 5 can be considered an extension of b 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 73 74 75 76 77 76 79 80 display pos
33. x 10 dot Alternating display character font character font Cursor display example Blink display example Figure 21 Using COM to Avoid Crosstalk on Unneeded Scanning Line 202 HITACHI HD44780U Connection of Changed Matrix Layout In the preceding examples the number of lines correspond to the scanning lines However the following display examples Figure 22 are made possible by altering the matrix layout of the liquid crystal display panel In either case the only change 15 the layout The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor Note that the display data RAM DDRAM addresses for 4 characters x 2 lines and for 16 characters x 1 line are the same as in Figure 20 Cursor FR m 5 x 8 dot 5 x 10 dot Alternating display character font character font Cursor display example Blink display example Figure 22 Changed Matrix Layout Displays 203 HD44780U Power Supply for Liquid Crystal Display Drive Various voltage levels must be applied to pins to V5 of the HD44780U to obtain the liquid crystal display drive waveforms The voltages must be changed according to the duty factor Table 10 VLCD is the peak value for the liquid crystal display drive waveforms and resistance dividing provides voltages V1 to V5 Figure 2
34. 1 and 6 2 to display character patterns stored in RAM Table 5 shows the relation between CG RAM addresses and data and display patterns As Table 5 shows an area that is not used for display can be used as a general data RAM Timing generation circuit The timing generation circuit generates timing signals to operate internal circuits such as RAM CG ROM and CG RAM RAM read timing needed for display and in ternal operation timing by MPU access are separately gen erated so they do not interfere with each other There fore when writing data to the DD RAM for example there will be no undesirable influence such as flickering in areas other than the display area This circuit also generates timing signals to operate the externally con nected driver LSI HD44100H AC6 ACS 4 BC SERE l 2 3 4 5 6 7 In a t line display 00 01 02 14 2 3 SEE CERA 1 line 00 0 02 In a 2 line display 4 40 i 4 42 8 9 ACO Liquid crystal display driver circuit The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal drivers When character font and number of lines are selected by a program the required common signal drivers auto matically output drive waveforms the other common signal drivers continue to output non selection waveforms The segment s
35. 3 Table 10 Duty Factor and Power Supply for Liquid Crystal Display Drive Duty Factor 1 8 1 11 1 16 Bias Power Supply 1 4 1 5 V1 V 1 4 VLCD 1 5 V2 V 1 2 VLCD 2 5 VLCD V3 1 2 VLCD Vic 3 5 VLCD V4 3 4 VLCD Vic 4 5 VLCD V5 VLCD 1 4 bias 1 5 bias 1 8 1 11 duty cycle 1 16 duty cycle Figure 23 Drive Voltage Supply Example 204 HITACHI HD44780U Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency The liquid crystal display frame frequencies of Figure 24 apply only when the oscillation frequency 15 2770 kHz one clock pulse of 3 7 us 1 8 duty cycle 400 clocks COM1 1 frame 1 frame 3 7 us x 400 x 8 11850 us 11 9 ms Frame frequency 84 3 2 11 9 ms 1 11 duty cycle 400 clocks TN COM 1 1 2 3 1 1 frame 3 7 us x 400 x 11 16300 16 3 ms Frame frequency M 6 61 4 Hz 16 3 ms 1 16 duty cycle 200 clocks COM1 Voc V1 V2 V3 V4 V5 1 frame 1 frame 3 7 us x 200 x 16 11850 us 11 9 ms Frame frequency l 84 3 Hz 11 9 ms Figure 24 Frame Frequency 205 HITACHI HD44780U Instruction and Display Correspondence 8 bit operation 8 digit x 1 display with internal res
36. 3 13 10 14 16 16 HD44780U AC Characteristics 4 5 to 5 5 V T 20 to 75 Clock Characteristics Item Symbol Min Typ External External clock frequency f 125 250 GOCE _ External clock duty Duty 45 50 operation External clock rise time bop External clock fall time Gs Clock oscillation frequency fosc 190 270 oscillation Max 350 55 0 2 0 2 350 Unit Test Condition Notes kHz 11 11 US 11 US 11 kHz 91 12 Vig 5 0 V Note Refer to the Electrical Characteristics Notes section following these tables Bus Timing Characteristics Write Operation Item Symbol Min Typ Enable cycle time Ege 500 m Enable pulse width high level PW 230 Enable rise fall time Address set up time RS R W to E t 40 Address hold time b 10 Data set up time Ds 80 Data hold time 10 Read Operation Item Symbol WMin Typ Enable cycle time Le 500 Enable pulse width high level PW 230 Enable rise fall time lets Address set up time RS R W to E t 40 Address hold time b 10 Data delay time loss Data hold time ac 5 HITACHI Max Max 160 Unit Test Condition ns Figure 27 Unit Test Condition ns Figure 28 219 HD44780U Interface Timing Characteristics with External Driver Item Symbol Min Typ Max Unit Test Condition Low level ioo 800 Clock set up time Dos 500
37. 313 35 665 2290 75 SEG28 539 2313 36 RS 832 2290 76 SEG27 755 2313 37 R W 1022 2290 77 26 970 2313 38 1204 2290 78 25 1186 2313 39 1454 2290 79 SEG24 1401 2313 40 DB1 1684 2290 80 SEG23 1617 2313 174 HITACHI Pin Functions No of Signal Lines RS 1 R W 1 E 1 DB4 to DB7 4 DBO to DB3 4 CL1 1 CL2 1 M 1 D 1 COM to COM16 16 to SEG40 40 V1 to V5 5 GND 2 5 1 OSC2 2 I O I O I O Device Interfaced with MPU MPU MPU MPU MPU Extension driver Extension driver Extension driver Extension driver LCD LCD Power supply Power supply Oscillation resistor clock HD44780U Function Selects registers 0 Instruction register for write Busy flag address counter for read 1 Data register for write and read Selects read or write 0 Write 1 Read Starts data read write Four high order bidirectional tristate data bus pins Used for data transfer and receive between the MPU and the HD44780U DB7 can be used as a busy flag Four low order bidirectional tristate data bus pins Used for data transfer and receive between the MPU and the HD44780U These pins are not used during 4 bit operation Clock to latch serial data D sent to the extension driver Clock to shift serial data D Switch signal for converting the liquid crystal drive waveform to AC Character pattern data corresponding to eac
38. 44780U 173 HD44780U HCD44780U Pad Location Coordinates Coordinate Coordinate Pad No Function X um Y um Pad No Function X um Y um 1 SEG22 2100 2313 41 DB2 2070 2290 2 SEG21 2280 2313 42 DB3 2260 2290 3 SEG20 2313 2089 43 4 2290 2099 4 SEG19 2313 1833 44 DB5 2290 1883 5 5 18 2313 1617 45 686 2290 1667 6 SEG17 2313 1401 46 DB7 2290 1452 7 SEG16 2313 1186 47 2313 1186 8 SEG15 2313 970 48 COM2 2313 970 9 SEG14 2313 755 49 COM3 2313 755 10 SEG13 2313 539 50 COM4 2313 539 11 SEG12 2313 323 51 COM5 2313 323 12 SEG11 2313 108 52 COM6 2313 108 13 SEG10 2313 108 53 COM7 2313 108 14 SEG9 2313 323 54 2313 323 15 SEG8 2313 539 55 2313 539 16 SEG7 2313 755 56 COM10 2313 755 17 SEG6 2313 970 57 11 2313 970 18 SEG5 2313 1186 58 COM 12 2313 1186 19 SEG4 2313 1401 59 2313 1401 20 SEG3 2313 1617 60 COM14 2313 1617 21 SEG2 2313 1833 61 15 2313 1833 22 SEG1 2313 2073 62 COM16 2313 2095 23 GND 2280 2290 63 SEG40 2296 2313 24 OSC1 2080 2290 64 SEG39 2100 2313 25 OSC2 1749 2290 65 SEG38 1617 2313 26 V1 1550 2290 66 SEG37 1401 2313 27 V2 1268 2290 67 SEG36 1186 2313 28 V3 941 2290 68 SEG35 970 2313 29 4 623 2290 69 SEG34 755 2313 30 V5 304 2290 70 SEG33 539 2313 31 48 2290 71 SEG32 323 2313 32 CL2 142 2290 72 SEG31 108 2313 33 Voc 309 2290 73 SEG30 108 2313 34 475 2290 74 29 323 2
39. 5 clock External clock duty Duty 45 operation External clock rise time External clock fall time t R Clock oscillation 190 oscillation frequency Typ 250 50 2 0 Max Unit Test Condition Note 350 kHz 11 55 0 2 US 0 2 US 350 kHz 75 12 Note Refer to the Electrical Characteristics Notes section following these tables Bus Timing Characteristics Write Operation Item Symbol Min Enable cycle time 1000 Enable pulse width high level PW 450 Enable rise fall time Address set up time RS R W to E t 60 Address hold time 20 Data set up time Lay 195 Data hold time 10 Read Operation Item Symbol Min Enable cycle time le 1000 Enable pulse width high level PW 450 Enable rise fall time lets Address set up time RS R W to E t 60 Address hold time b 20 Data delay time oss Data hold time ae 5 216 Test Condition ns Figure 27 25 Max Unit Test Condition ns Figure 28 25 360 HD44780U Interface Timing Characteristics with External Driver Item Symbol Min Typ Max Unit Test Condition Clock pulse width High level t 800 ns Figure 29 Lowlevel t 800 Clock set up time Lu 500 Data set up time I 300 Data hold time ar 300 M delay time a 1000 1000 Clock rise fall time t 200 Power Supply Conditions Usi
40. 80U 64x 8 bit character generator RAM 8 character fonts 5 x 8 dot 4 character fonts 5 x 10 dot 16 common x 40 segment liquid crystal display driver Programmable duty cycles 1 8 for one line of 5 x 8 dots with cursor 1 11 for one line of 5 x 10 dots with cursor 1 16 for two lines of 5 x 8 dots with cursor e Wide range of instruction functions Display clear cursor home display on off cursor on off display character blink cursor shift display shift e Pin function compatibility with HD44780S Automatic reset circuit that initializes the controller driver after power on e nternal oscillator with external resistors Low power consumption Ordering Information Type No Package CGROM HD44780UA00FS FP 80B Japanese standard font HCD44780UA00 Chip HD44780UA00TF TFP 80F HD44780UA02FS FP 80B European standard font HCD44780UA02 Chip HD44780UA02TF TFP 80F HD44780UBxxFS FP 80B Custom font HCD44780UBxx Chip HD44780UBxxTF TFP 80F Note xx ROM code No 168 HITACHI HD44780U HD44780U Block Diagram OSC1 OSC2 Reset circuit Tm ACL 9 Instruction register IR Display data RAM Common DDRAM signal 80 x 8 bits driver Address counter 40 bit Segment latch signal circuit driver Instruction decoder Input DBO to output 77 27 register j lt buffer DR LCD drive voltage selector Cha
41. AC Address counter used lor 5 10 05 0 5674015 both of and CG RAM 1 Internaliy aperating address 0 Can accept instruction gt 1 d mm a mamo aw mw ebe ie um DRM OP effect Notes 1 Applied to models driven by 1 8 duty or 1 1 1 duty 2 Applied to models driven by 1 16 duty ETTINGER a a un EN 5 2 Description of details 4 Display ON OFF control 1 Clear display 2 3 RS Writes space code 20 hexadecimal character pattern for character code 20 must be blank pattern into all DD RAM addresses Sets DD RAM address 0 in address counter Returns display to its original status if it was shifted In other words the display disappears and the cursor or blink go to the left edge of the display the first line if 2 lines are displayed Set 1 0 1 Increment Mode of Entry Mode S of Entry Mode doesn t change Return home RS RW 90 oTe BR D The display is ON when D 1 and OFF when D 0 When off due to D O display data remains in the DD RAM It can be displayed immediately by setting 1 The cursor displays when 1 and does not display when 0 Even if the cursor disappears the func tion of I D etc does no
42. ACTER CODES AND CHARACTER PATTERN 1 5x 10 dot applied type H2570 H2571 H2572 LMO27 LMO67 LEIS LAJA sasu 19 ult m ES e Note 1 CG RAM a character generator RAM having a storage function of character pattern which enable to change freely by users program Note 2 When line setting at initialization is 2 lines N 1 pattern becomes 5 x 7 dot ETTINGER 2 5x 7 dot applied type Character display modules including LED backlight versions 1771 00 EUM 100 HE IR Note a character generator RAM having storage function of character pattern which enable to change freely by users program Er en ETIINGER Table 6 Relation between CG RAM addresses and character code DD RAM and character pattern CG RAM data 1 For 5 x 7 dot character pattern Character Codes DD RAM Data 0 0 0 0 0 I Character 0 0 0 0 00 0 Pattern 10 Example 1 t 0 d La b Feilen 0 0 0 0 0 1 41 chars 1 0 Example 2 10 1 l T 0 0 0 0 No effect Note 1 Character code bits 0 2 correspond to CG RAM address bits 3 5 3 bits 8 types 2 CG RAM address bits 0 2 designate character pattern line position The 8th line is the cursor position
43. DDRAM To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM address setting After a write the address is automatically incremented or decremented by 1 according to the entry mode The entry mode also determines the display shift Read Data from CG or DDRAM Read data from CG or DDRAM reads 8 bit binary data DDDDDDDD from CG or DDRAM The previous designation determines whether DDRAM 15 to be read Before entering this read instruction either CGRAM or DDRAM address set instruction must be executed If not executed the first read data will be invalid When serially executing read instructions the next address data 1s normally read from the second read The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction when reading out DDRAM The operation of the cursor shift instruction is the same as the set DDRAM address instruction After a read the entry mode automatically increases or decreases the address by 1 However display shift is not executed regardless of the entry mode Note The address counter AC is automatically incremented or decremented by 1 after the write instructions to CGRAM or DDRAM are executed The RAM data selected by the AC cannot be read out at this time even if read instructions are executed Therefore to correctly read data execute either the address set instruction or cursor shift instru
44. F 1 Internally operating BF 2 0 Instructions acceptable Note indicates no effect After execution of the CGRAM DDRAM data write or read instruction the RAM address counter is incremented or decremented by 1 The RAM address counter is updated after the busy flag turns off In Figure 10 t is the time elapsed after the busy flag turns off until the address counter is updated Busy signal Busy state DB7 pin Address counter DBO to DB6 pins A 1 tapp Note tapp depends on the operation frequency tapp 1 5 or fosc seconds Figure 10 Address Counter Update 192 HITACHI HD44780U Instruction Description Clear Display Clear display writes space code 20H character pattern for character code 20H must be a blank pattern into all DDRAM addresses It then sets DDRAM address 0 into the address counter and returns the display to its original status if it was shifted In other words the display disappears and the cursor or blinking goes to the left edge of the display the first line if 2 lines are displayed It also sets I D to increment mode in entry mode 5 of entry mode does not change Return Home Return home sets DDRAM address 0 into the address counter and returns the display to its original status if it was shifted The DDRAM contents do not change The cursor or blinking go to the left edge of the display in the first line if 2 lines are displayed Entry M
45. M address set Busy flag lesen CG RAM DD RAM Daten schreiben CG RAM DD RAM Daten LI Anmerkung VD increment VD 0 decrement S 1 Display shift S D 1 Display 20 Display aus 1 0 Cursor aus I Zeichen in Cursorposition blinkt 5 1 Display shift S C 0 Cursor weiter 1 shift rechts R L 0 shift linlks DL 1 8 Bitbus DL 0 4 Bitbus 1 Abarbeitung intern 0 eingabebereit Fig 1 WRITE OPERATION Write data from MPU to LCM 0 Display freeze Zeichensatz Higher se Per pe pepee BERE alte ERE AES z UN E 2 READ OPERATION Pw teycle Read data from LCM to MPU nad teme een xen 2 Character LCM DV series N Model No Character Module Size View Area 222 char x line Fonts W x Hx Tmm W x Hmm W x Hmm W x Hmm Voo V usas wes n 5 635x158 320x555 ole __ 5 7 1220 220 100 990x130 404x000 50 wx axranssouer 120x440x100 903240 orae
46. OB to A register accumulator by execut ing In Out instruction After that busy flag can be easily checked by examining D84 LCM LCD 1 Fig 5 Example of connection with LCM being used as a part of memories on the determined address Figure 5 is an example of connection with LCD module being used as a part of memories on the determined address Generates RS signal Register Select signal by latching the content of AD at the rising edge of ALE signal By using this method you can obtain RS signal from the AD among bit addresses generated at the clock of the first machine cycle In case of using LCD module as an equipment chip select signal is necessarily activated when IO M signal is High level Furthermore by using for RS signal the interface is easily realized By both methods busy flag can be checked by storing status data into register Accumulator and examining the bit 7 by software ntm atii ap prt ___ ZEE 2 3 c uuu Interface to 4 bit MPU The HD44780 can be connected to a 4 bit MPU through the 4 bit MPU I O port If the I O port has enough bits data can be transferred in 8 bit lengths but if the bits are insufficient the transfer is made in two operations of 4 bits each with designation of interface data length for 4 bits In the latter case the timing sequence becomes RS Internal lmerpa
47. RAM data corresponds to display selection and 0 to non selection Indicates no effect 187 HITACHI HD44780U Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM CGROM and CGRAM RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other Therefore when writing data to DDRAM for example there will be no undesirable interferences such as flickering in areas other than the display area Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal drivers When the character font and number of lines are selected by a program the required common signal drivers automatically output drive waveforms while the other common signal drivers continue to output non selection waveforms Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RAM DDRAM Since serial data 1s latched when the display data character pattern corresponding to the starting address enters the internal shift register the HD44780U drives from the head display Cursor Blink Control Circuit The cursor blink control circuit generates the cursor or character blinking The cursor or the blinking will appear with the digit located at the display data RAM DDRAM addre
48. U By the register selector RS signal these two registers can be selected Table 1 Busy Flag BF When the busy flag 15 1 the HD44780U 15 in the internal operation mode and the next instruction will be accepted When RS 0 and R W Table 1 the busy flag is output to DB7 The next instruction must be written after ensuring that the busy flag 15 0 Address Counter AC The address counter AC assigns addresses to both DDRAM and CGRAM When an address of an instruction is written into the IR the address information 1s sent from the IR to the AC Selection of either DDRAM or CGRAM is also determined concurrently by the instruction After writing into reading from DDRAM or CGRAM the AC 15 automatically incremented by decremented 1 The AC contents are then output to DBO to DB6 when RS 0 and R W Table 1 Table 1 Register Selection RS R W Operation 0 IR write as an internal operation display clear etc 1 Read busy flag DB7 and address counter DBO to DB6 1 0 write as internal operation DR to DDRAM or 1 1 DR read as an internal operation DDRAM or CGRAM to DR 176 HITACHI HD44780U Display Data RAM DDRAM Display data RAM DDRAM stores display data represented in 8 bit character codes Its extended capacity is 80 x 8 bits 80 characters The area in display data RAM DDRAM that is not used for display can be used as general data RAM See Figure 1 for the
49. al Reset Operation Initialized No display Sets to 8 bit operation and selects 1 line display and 5 x 8 dot character font Number of display lines and character fonts cannot be changed after step 2 Turns on display and cursor Entire display is in space mode because of initialization Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD CGRAM Display is not shifted Writes H DDRAM has already been selected by initialization when the power was turned on The cursor is incremented by one and shifted to the right Writes l Writes l Sets mode to shift display at the time of write Writes a space 207 HD44780U Table 11 Bit Operation 8 Digit x 1 Line Display Example with Internal Reset cont Step Instruction No RS R W 087 DB6 DB5 DB4 DB2 DB1 DBO Display Operation 11 Write data to CGRAM DDRAM Writes M 1 0 0 1 0 0 1 1 0 1 5 E 9 12 13 Write data to CGRAM DDRAM Writes MICROKO_ 1 0 0 1 0 0 1 1 1 1 14 Cursor display shift Shifts only the cursor position to MICROKO 0 0 0 0 0 1 0 0 the left 15 Cursor or display shift Shifts only the cursor position to MICROKO 0 0 0 0 0 1 0 0 the left 16 Write data to CGRAM DDRAM ER Writes over 1 0 0 1 0 0 0 0 1
50. ame time the value of the address counter in binary AAAAAAA is read out This address counter 1s used by both CG and DDRAM addresses and its value is determined by the previous instruction The address contents are the same as for instructions set CGRAM address and set DDRAM address Table 7 Shift Function S C R L 0 Shifts the cursor position to the left AC is decremented by one 1 Shifts the cursor position to the right AC is incremented by one 1 0 Shifts the entire display to the left The cursor follows the display shift 1 1 Shifts the entire display to the right The cursor follows the display shift Table 8 Function Set No of Display Duty N Lines Character Font Factor Remarks 0 1 5 x 8 dots 1 8 0 1 5 x 10 dots 1 11 1 2 5 x 8 dots 1 16 Cannot display two lines for 5 x 10 dot character font Note Indicates don t care 196 HITACHI HD44780U SU NM RN 5 x 8 dot 5 x 10 dot Alternating display character font character font Cursor display example Blink display example Figure 13 Cursor and Blinking RS RW 087 DB6 DB5 DB4 DB3 082 DBO Set DDRAM address order bit order bit RS R W 087 DB6 DB5 DB4 DB3 082 DBO Read busy flag and address order bit order bit Figure 14 197 HITACHI HD44780U Write Data to CG or DDRAM Write data to CG or DDRAM writes 8 bit binary data DDDDDDDD to CG or
51. an now be read Is the other peripheral equipment i in contention with the data bus for a chip select problem Correct the chip select conditions Still no good The data can now be read Is the system operated while making BUSY check Make the BUSY check or operate system after waiting for 5 times of the BUSY time Still not good un The data can now Any other error exists in the software be read Yes The data can now read 7 5 Others Check tne following Use conditions Erroneous events Contents of operation before and after the error event occurrence Flowchar if possible The program if given can not be decoded ETTINGER 8 Block diagram and function of each block 8 1 Block diagram of HD44780 interior Vee GND gt OSC 7 5 un Address Timing generation 3 Ct counter AC Circuit sf 5 5 55 59 5 Display data I S RS Te RIN DD 5 COM n 80x8 bits 2 4 3 2 08 LES 4 OB 5 2 Character Character ROM ROM s SEG SEG CG RAM RAM 9 512 bits 7 i E 200 bits 40 Yi Power supply gt f
52. and display is performed in logical OR by the cursor Maintain the 8th line data corresponding to the cursor display position in the 0 state for cursor display When the 8th line data is 1 bit t lights up regardless of cursor existence 3 Character pattern row positions correspond to CG RAM data bits 0 4 as shown in the figure bit 4 being at the left end Since CG RAM data bits 7 are not used for display they can be used for the general data RAM 4 As shown in Tables 3 and 4 RAM character patterns are selected when character code bits 4 7 are all 70 However since ter code bit 3 is a ineffective bit the display the character pattern example is selected by character code 700 hexadecimal or 708 hexadecimal 5 1 for RAM data corresponds to selection for display and 0 for non selection meen __ __ eee ETTINGER 2 For 5 x 10 dot character pattern Character Codes DD RAM Data 1 6 5 4 3 2 1 0 Higher Lower Address 0 0 0 0 0 0 1 0 0 0 0 0 T 0 0 n TREY 0 gt Ma M 0 100 Pattern 00 0 x 0 0 0 1 0 1 0 11 0 Eo 4 4 1110 0 0 0 11001 0 0 0 rU on eps 1010 0 0 0 0 7 Position 5d 1 1 x 1100 212101 T 1 0 1 11 0 0 0 0 70 0 0 1 X effect Note 1 Character code bi
53. busy state is 10 ms after rises to 4 5 1 Display clear 2 Function set DL 1 8 bit long interface data N 20 tine display 0 5x 7 dot character font 3 Display ON OFF control D 0 Display OFF 0 Cursor OFF 50 Blink OFF 4 Entry mode set 1 increment 5 0 Noshift 5 Write DD RAM When the rise time of power supply 0 2 4 5 is out of the range 0 1 ms 10 ms or when the low level width of power OFF less than 0 2 is less than 1 ms the internal reset circuit will not operate normally In this case initialization will not be performed normally Initialize by MPU according to 4 2 initializing by instruc at the head of program ETIINGER 4 2 Initializing by instruction If the power supply conditions for correctly operating the internal reset circuit are not met initialization by instruction 15 required Use the following procedure for initialization 1 When interface is 8 bits long Wait more than 15 ms after Vpp rises to 4 5V 0 0 0 0 1 1 x x X x Function set interface is 8 bits long Wait more than 4 1 ms 0 0 0 0 1 1 x X x x Function set interface is 8 bits long 0 0 9 0 1 1 x Function set interface is 8 bits long BF can be checked after the following instructions When BF is not checked the waiting time between instructions is longer than the execution instruction tim
54. character code 2 EPROM addresses to AO specify a line position of the character pattern EPROM data O4 to OO correspond to character pattern data 4 EPROM data O5 to O7 must be specified as 0 5 A lit display position black corresponds to 1 6 Line 9 and the following lines must be blanked with Os for a 5 x 8 dot character fonts 182 HITACHI Table 3 Notes Handling unused character patterns HD44780U EPROM data outside the character pattern area Always input Os 2 EPROM data in CGRAM area Always input Os Input 0s to EPROM addresses 00H to FFH 3 EPROM data used when the user does not use any HD44780U character pattern According to the user application handled in one of the two ways listed as follows a When unused character patterns are not programmed If an unused character code is written into DDRAM all its dots are lit By not programing a character pattern all of its bits become lit This 1s due to the EPROM being filled with 1s after it is erased b When unused character patterns are programmed as 05 Nothing is displayed even if unused character codes are written into DDRAM This 1s equivalent to a space 5 x 10 Dots Example of Correspondence between EPROM Address Data and Character Pattern EPROM Address Data A11A10A9 7 5 A4 A2 A1 0 O4 O2 O1 OO LSB O O O O o o o o
55. ction only with DDRAM then just before reading the desired data execute the read instruction from the second time the read instruction is sent RS R W DB7 086 085 084 DB3 DB2 DBO Write data to Higher Lower order bits order bits RS RW DB7 DB6 085 084 DB3 082 DBO Read data from m Higher Lower order bits order bits Figure 15 198 HITACHI HD44780U Interfacing the HD44780U Interface to MPUs e Interfacing to an 8 bit MPU See Figure 17 for an example of using a I O port for a single chip microcomputer as an interface device In this example P30 to P37 are connected to the data bus DBO to DB7 and P75 to P77 are connected to E R W and RS respectively Internal operation unctioning Not DB7 Bata KLZ Busy Busy Daa Instruction Busy flag Busy flag Busy flag Instruction write check check check write Figure 16 Example of Busy Flag Check Timing Sequence H8 325 HD44780U COMI to P30 to P37 DBO to DB7 16 Figure 17 8 325 Interface Single Chip Mode 199 HITACHI HD44780U e Interfacing to a 4 bit MPU The HD44780U can be connected to the I O port of a 4 bit MPU If the I O port has enough bits 8 bit data can be transferred Otherwise one data transfer must be made in two operations for 4 bit data In this case the timing sequence becom
56. cy changes according to fosc or the reciprocal of 1 For example when f is 270 kHz 409 6 x 250 270 379 2 ms 193 HITACHI HD44780U Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data Table 7 This function is used to correct or search the display In a 2 line display the cursor moves to the second line when it passes the 40th digit of the first line Note that the first and second line displays will shift at the same time When the displayed data 15 shifted repeatedly each line moves only horizontally The second line display does not shift into the first line position The address counter AC contents will not change if the only action performed is a display shift Function Set DL Sets the interface data length Data is sent or received in 8 bit lengths DB7 to DBO when DL 15 1 and in 4 bit lengths DB7 to DB4 when DL is 0 When 4 bit length is selected data must be sent or received twice N Sets the number of display lines F Sets the character font Note Perform the function at the head of the program before executing any instructions except for the read busy flag and address instruction From this point the function set instruction cannot be executed unless the interface data length 1s changed Set CGRAM Address Set CGRAM address sets the CGRAM address binary AAAAAA into the address counter Data 1s then writte
57. d instruction the next address data is normally read from the second read The address set instruction need not be executed just before the read instruction when shifting the cursor by cursor shift instruction when reading out DD RAM The cursor shift instruction operation is the same as that of the DD RAM s address set instruction After a read the entry mode automatically increases or decreases the address by 1 However display shift is not executed no matter what the entry mode is Note The address counter AC is automatically incre mented or decremented by 1 after write instruc tions to either CG RAM or DD RAM RAM data selected by the AC cannot than be read out even if read instructions are executed The conditions for correct data read out are execute either the address set instruction or cursor shift instruction only with DD RAM just before reading out ex the read instruction from the second time the read instruction is serial lt ETTINGER 5 3 Instruction and display correspondence data for 80 characters as explained before the RAM can 1 8 bit operation 8 digit x 1 line display using internal be used for displays like the lightening board when com reset bined with display shift operation Following table shows an example of 8 bit x 1 line display Since the display shift operation changes display position in 8 bit operation only and OD RAM contents remain unchanged display
58. e See Table 2 RS R W DB DBs DBs DB DB DB function set Interface is 8 bits long h T display OFF Specify the number of ind RAE 0 0 0 0 1 1 N F x x 0 0 01 00 o display lines and character changed afterwards font 3 0 0 0 0 0 1 0 0 0 0 0 0 0 ID S entry mode set Initialization ends ETTINGER 5 Instruction 5 1 Outline Only two HD44780 registers the Instruction Register IR and the Data Register OR can be directly controlled by the MPU Prior to internal operation start control information is temporarily stored in these registers to allow interface from HD44780 internal operation to various types of MPUs which operate in different speeds to allow interface to peripheral control ICs HD44780 internal operation is determined signals sent from the MPU These signals include register selec tion signals RS read write signals and data bus signals DB DB and are called instructions here Table 2 shows the instructions and their execution time Details are ex plained in subsequent sections Instructions are of 4 types those that 1 Designate 44780 functions such as display format data length etc 2 Give internal RAM addresses 31 Perform data transfer with internal RAM 4 Others In normal use category 3 instructions are used most fre quently However automatic incrementing by 1 or decre men
59. e stored in DORAM when read from 5 d front different fram the listed n the character font table 15 disolayed There s an address in which no Proceed to character is disolayed roceed to gt Proceed to 3 1 ie Data is fed too fast Retry it while making a BUSY check It is still too fast even when the BUSY check is made The function of LCD MH is no good ERA 3 2 Data is fed too fast Retry it while making a BUSY check 3 3 The address Set command is not included in the initializa Although the address is so designed to be set to 700 at the power ON according to the Power ON Reset function of the LCD I itself this Power ON Reset function does not work in some cases according to the power conditions 3 4 When no error exists in the software the function of 5 no good The 2 line display LCM is electrically composed of 40 ters x 2 lines but it displays 16 characters or 20 characters Partly When 16 characters are written in the Ist line and the data at the 17th character is input as it is it is entered in the 17th character in the Ist line and its 16 neither dis played on the screen is therefore necessary to set the address LF between the 16th caracter and 17th character NECEM ine feed 13 6 The 4 line display LCM is composed as shown
60. es somewhat complex See Figure 18 See Figure 19 for an interface example to the HMCS4019R Note that two cycles are needed for the busy flag check as well as for the data transfer The 4 bit Operation is selected by the program Internal Funcion operation DB7 77 busy 868 22 Instruction Busy flag Busy flag Instruction write check check write Note IR7 IR3 are the 7th and 3rd bits of the instruction is the bit of the address counter Figure 18 Example 4 Bit Data Transfer Timing Sequence HMCS4019R HD44780 SEG1 to SEG40 R10 to R13 DB4 to DB7 Figure 19 Example of Interface to HMCS4019R 200 HITACHI HD44780U Interface to Liquid Crystal Display Character Font and Number of Lines The HD44780U can perform two types of displays 5 x 8 dot and 5 x 10 dot character fonts each with a cursor Up to two lines are displayed for 5 x 8 dots and one line for 5 x 10 dots Therefore a total of three types of common signals are available Table 9 The number of lines and font types can be selected by the program See Table 6 Instructions Connection to HD44780 and Liquid Crystal Display See Figure 20 for the connection examples Table 9 Common Signals Number of Lines Character Font Number of Common Signals Duty Factor 1 5 x 8 dots cursor 8 1 8 1 5 x 10 dots cursor 11 1 11 2 5 x 8 dots cursor 16 1 16 HD44780
61. et Refer to Table 11 for an example of an 8 digit x 1 line display in 8 bit operation The HD44780U functions must be set by the function set instruction prior to the display Since the display data RAM can store data for 80 characters as explained before the RAM can be used for displays such as for advertising when combined with the display shift operation Since the display shift operation changes only the display position with DDRAM contents unchanged the first display data entered into DDRAM can be output when the return home operation 1s performed 4 bit operation 8 digit x 1 display with internal reset The program must set all functions prior to the 4 bit operation Table 12 When the power is turned on 8 bit operation is automatically selected and the first write is performed as an 8 bit operation Since DBO to DB3 are not connected a rewrite is then required However since one operation is completed in two accesses for 4 bit operation a rewrite 15 needed to set the functions see Table 12 Thus DB4 to DB7 of the function set instruction is written twice 8 bit operation 8 digit x 2 line display For a 2 line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written Thus if there are only 8 characters in the first line the DDRAM address must be again set after the 8th character 1s completed See Table 13 Note that the display shift operation 15 pe
62. flag eher k Busy heck heck Instruction write Fig 3 Example busy flag check timing sequence 1 When connecting to 8 bit MPU through PIA Fig 4 is example of using a PIA or I O port for single chip microcomputer as an interface device Input and output of the device is TTL compatible In the example PB to PB are connected to the data buses DB to DB and PA to are connected to E R W and RS respectively Pay attention to the timing relation between and other signals when reading or writing data and using PIA as an interface COM COM Connected to LCD HD6 8800 HD 4 4780 SEC 10682 SEC Fig 4 Example of interface to HD68B00 using PIA HO68B21 Connecting directly to the 8 bit MPU bus line LCM COM E HD 780 Connected HD68 00 to LCD SEG SEG DB 3 Example of interfacing to the HD6805 LCM COM pee OB ro HDs4780 Connected HD6805 to LCD 4 Example of interfacing to the HD6301 COM 4 4780 Connected HD6301 to LCD ETTINGER Table 4 Register selection Operation IR write as internal operation Display clear etc Read busy flag 085 and address counter OR write as internal operation DR to OO or CG RAM cm read as internal operation 1 1 DO or CG RAM to DR
63. h segment signal Common signals that are not used are changed to non selection waveforms COM9 to COM16 are non selection waveforms at 1 8 duty factor and COM12 to COM16 are non selection waveforms at 1 11 duty factor Segment signals Power supply for LCD drive Voc 5 11 V max Vc 2 7V to 5 5V GND OV When crystal oscillation is performed a resistor must be connected externally When the pin input is an external clock it must be input to OSC1 175 HD44780U Function Description Registers The HD44780U has two 8 bit registers an instruction register IR and data register DR The IR stores instruction codes such as display clear and cursor shift and address information for display data RAM DDRAM and character generator RAM CGRAM The can only be written from the MPU The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM or CGRAM Data written into the DR from MPU 15 automatically written into DDRAM or CGRAM by an internal operation The DR is also used for data storage when reading data from DDRAM or CGRAM When address information 15 written into the IR data is read and then stored into the DR from DDRAM or CGRAM by an internal operation Data transfer between the MPU is then completed when the MPU reads the DR After the read data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MP
64. ignal driver has essentially the same configu ration a5 the driver LSI HD44100H Character pattern data is sent serially through a 40 bit shift register and latched when all needed data has arrived The latched data controls the driver for generating drive waveform outputs The serial data is sent to the 44100 externally nected in cascade used for display digit number extension Send of serial data always starts at the display data charac ter pattern corresponding to the last address of the display data RAM DD RAM Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register the 44780 drives the head display The rest displays corresponding to latter addresses are added with each additional 44100 Cursor Blink control eircuit This is the circuit that generates the cursor or blink The cursor or the blink appear in the digit residing at the display data RAM DD RAM address set the address counter AC When the address counter is 08 16 a cursor position 15 display position DD RAM address the cursor position Note The cursor or blink appears when the address counter AC selects the character generator RAM CG RAM But the cursor and blink are meaningless The cursor or blink is displayed in the meaningless position when AC is the CG RAM address Table 5 CORRESPONDENCE BETWEEN CHAR
65. in the right figure Consequently when written continuously from the Ist line the data is written as A When displayed in 4 lines the data is moved from the 1st line to the 3rd line It is therefore necessary to set the address of LF in this case 2 2 The display ON OFF is turned to the side This flag is by no means set unless turned to the ON side When employing the shift function together the screen is shifted each time a data is written and the data can seen on the screen in some cases It is therefare necessary to correct the application of the shift function 16 characters Left shift specified is input 2 et 2 co c Stored in DORAM ee Cursor 5 moved Screen is snifteg lelt eee Since this operation i5 carried out in a moment what can be seen is the status of and 4 only Although not displayed in appear ance the data ts stored in the DDRAM ew 2 Ge Defective CGROM font IC is faulty 3 95 If no error exists in the software the IC is faulty 3 1 0 Contact our agent for any other erroneous event EITINGER 7 4 Data cannot be read the connection and polarity of RS and R W are made as specified in the manual one Still no good e p i The data can now Is the timing deviated between the data display and b ten H Still no good a The data c
66. ion and cause poor reliability 214 HITACHI HD44780U DC Characteristics 2 7 to 4 5 V T 20 to 75 Item Symbol Min Typ Max Unit Test Condition Notes Input high voltage 1 0 7 Voc V 6 except OSC1 Input low voltage 1 0 3 0 55 6 except OSC1 Input high voltage 2 VIH2 0 7V Voc V 15 OSC1 Input low voltage 2 VIL2 0 2V V 15 OSC1 Output high voltage 1 VOH1 0 75V V 01 7 DBO DB7 Output low voltage 1 VOL 1 0 2V V 0 1 mA 7 DBO DB7 Output high voltage 2 VOH2 0 8V 0 04 8 except DBO DB7 Output low voltage 2 VOL2 0 2V V l 0 04mA 8 except DBO DB7 Driver on resistance Room 2 20 KO 14 0 05 mA 13 COM VLCD 24V Driver on resistance Fi is 2 30 KO 14 0 05 mA 13 SEG VLCD 4 Input leakage current 1 1 HA VIN OtoV 9 Pull up MOS current I 10 50 120 DBO DB7 RS R W Power supply current 0 15 0 30 mA oscillation 10 14 external clock Veo V fose 270 kHz LCD voltage VLCD1 3 0 11 0 V V V5 1 5 bias 16 VLCD2 3 0 11 0 V 75 1 4 bias 16 Note Refer to the Electrical Characteristics Notes section following these tables 215 HITACHI HD44780U AC Characteristics 2 7 to 4 5 V 20 to 75 Clock Characteristics Item Symbol Min External External clock frequency 12
67. it lengths DB when DL 0 When the 4 bit length is selected data must be sent or received twice N Sets number of display lines F Sets character font Note Perform the function at the head of the program before ex ecuting all instructions except Busy flag address read From this point the function set instruction cannot be executed unless the interface data length is changed N Remarks lines actor Sx Tan 01 1 5x 10dots 1 11 Cannot display 2 lines Te 2 with 5 x 10 dot charac No effect Character font 5x 7 dots ter font 7 Set RAM address RS R W D84 08 Lower Order Bits Order Bits Sets the CG RAM address into the address counter in binary AAAAAA Data is then written or read from the MPU for the CG RAM 8 9 Set OD RAM address RS RW 0B DB gt Higher lower Order Bits Order Bits Sets the DD RAM address into the address counter in binary AAAAAAA Data is then written or read from the MPU for theDD RAM However when N 0 1 line display AAAAAAA is 00 4F hexadecimal when N 1 2 line display AAAAAAA is 007 27 hexadecimal for the first line and 740 67 hexadecimal for the second line Read busy flag amp address RS RW 08 OB 4 Higher Lower Order Bits Order Bits Reads the
68. ition 1 j 4 40 DD RAM address 1 109 HD44780 display HD44100H 1 HD44100H 2 44100 9 display 8 display display 2 line display N 1 1 2 3 4 5 39 40 display position 1 00 01 02 a 26 27 1 DD RAM address jJine 40 41 42 43 401 omen 56 57 When the number of display characters ts less than 40 x 2 are not consecutive For example when an HD44780 is lines the 2 lines from the head are displayed Note that used 8 characters x 2 lines are displayed as the first line end address and the second line start address 1 2 3 4 5 6 7 8 display position DD RAM address When display shift is performed the DD RAM address move as 0l o2 03 04 05 06 I Left shift display b 16 character x 2 line are displayed when an HD44780 and an HD44100H are used 1 2 3 4 5 6 7 8 NES ae 00 04 os 06 2 line lt display 44100 display EE 9 __ ___ _ _ _ ETTINGER ey When display shift is performed the DD RAM address moves as follows 02 03 04 05 06 09 02 e 0E
69. l operation eee somewhat complex See Fig 6 Fig 7 shows an example of interface to the HMCS43C Note that 2 cycles are needed for the busy flag check as well as the data transfer 4 bit operation is selected by program No KZJ nus y ACAD A write Bus check IR7 R3 Note Busy flag check Inxttuctton write Instruction 7th bit 3rd bit Address counter 3rd bit Fig 6 An example of 4 bit data transfer timing sequence Fig 7 Example of interface to the HMCS43C Precautions on constituting hardwares 3 1 Chip select HD44780 has no CS chip select terminals Therefore when this LSI is connected directly to Data Bus line not through PIA and so on add the circuit that inhibits the output of Enable signal at the address which is not assigned for HD44780 Fig 8 Example of addresses 3000 amp 6 being assigned for HD44780 3 2 Ability of driving bus line DB to DB can drive one TTL or capacitance of 130 pF The data bus terminals have three state constructions and re main in high impedance state while Enable signal being low level Since the data bus has pull up MOS it outputs high level age during the data bus being opened 3 3 Power supply voltage for liquid crystal display drive At Interface of liquid crystal display module there are three power supply terminals GNO and LCD module is
70. line 150 oie 1 2 5A 58 sc sD sE f Display position and DD RAM address for 2 3 4 5 6 7 8 3 10 11 12 B 8 15 16 17 18 19 20 4 position I line 00 O1 02 03104 05 06 07 98 08 DD RAM address EEE 2 linei 40 41 a2 via 1 MEE UM SORT ONG ilc oe Se pa nl 5 16 16 aine 54 55 56 157 1 5a 59 3 58 Note Shift display is as same as 2 line type EEG EERE ETTINGER 5 6 7 Character generator ROM The character generator ROM generates 5 x 7 dotor 5x 10 dot character patterns from 8 bit character codes It can generate 160 types of 5 x 7 dot character patterns and 32 types of 5 x 10 dot character patterns Tables 5 1 and 5 2 show the relation between character codes and character patterns in the Hitachi standard HD44780A00 User defined character patterns are also available by mask programming ROM For details see LCD I HD44780 Breadboard User s Manual Character generator RAM CG RAM The character generator RAM is the RAM with which the user can rewrite character patterns by program With 5 x 7 dots 8 types of character patterns can be written and with 5 x 10 dots 4 types can be written Write the character codes in the left columns of Tables 6
71. n to or read from the MPU for CGRAM 194 HITACHI Clear display Entry mode set Display on off control Cursor or display shift Function set Set CGRAM address RS R W DB7 086 DB5 DB4 DB3 082 1 DBO RS R W 087 086 DB5 DB4 DB3 082 1 DBO RS R W 087 086 085 084 DB3 082 DBO RS R W DB7 086 DB5 DB4 DB3 082 1 DBO Figure 11 RS R W DB7 DB6 085 084 DB3 DB2 1 080 ce ole Tele le Ie e T mme RS R W DB7 DB6 085 084 DB3 DB2 DBO ed RS R W DB7 DB6 085 084 DB3 082 DBO Higher Lower order bit order bit Figure 12 HITACHI HD44780U 195 HD44780U Set DDRAM Address Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter Data is then written to or read from the MPU for DDRAM However when is 0 1 display AAAAAAA can be to 4FH When N is 2 line display AAAAAAA can be 00H to 27H for the first line and 40H to 67H for the second line Read Busy Flag and Address Read busy flag and address reads the busy flag BF indicating that the system 15 now internally operating on a previously received instruction If BF 15 the internal operation is in progress The next instruction will not be accepted until BF 15 reset to 0 Check the BF status before the next write operation At the s
72. needed Number of display lines and character fonts cannot be changed hereafter Turns on display and cursor Entire display is in space mode because of initialization Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the RAM Display is not shifted Writes The cursor is incremented by one and shifts to the right ETTINGER 3 8 bit operation 8 digit x 2 line display shift are performed In the example the display shift is For 2 line display the cursor automatically moves from performed when the cursor is on the second line How the first to the second line after the 40th digit of the 1st ever if shift operation is performed when the cursor is line has been written Thus if there are only 8 characters on the first line both the first and second lines move in the first line the DO RAM address must again be set together When you repeat the shift the display of the after the Bth character is completed See the following second display will only move within each line many table Note that the first and second lines of the display times B bit operation 8 digit x 2 line display example using internal reset initialized No display appears Power supply ON 044780 is initialized by the internal reset circuit Function Set RS R W 085 08 0 0 0 0 1 1 1 0 isplay Control 0 0 9 0 0 1 1 1
73. ng Internal Reset Circuit Item Symbol Min Typ Max Unit Test Condition Power supply rise time lok 0 1 10 ms Figure 30 Power supply off time 1 217 HITACHI HD44780U DC Characteristics 4 5 to 5 5 V T 20 to 75 Item Input high voltage 1 except OSC1 Input low voltage 1 except OSC1 Input high voltage 2 OSC1 Input low voltage 2 OSC1 Output high voltage 1 DBO DB7 Output low voltage 1 Output high voltage 2 except DBO DB7 Output low voltage 2 except DBO DB7 Driver on resistance COM Driver on resistance SEG Input leakage current Pull up MOS current DBO DB7 RS R Power supply current LCD voltage Note 218 Symbol VIH1 VIL 1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG VLCD1 VLCD2 Min 2 2 09 3 0 3 0 125 0 35 Voc 0 6 V CC 1 0 0 4 0 1 V 20 30 250 0 60 11 0 11 0 HITACHI Unit V V Test Condition 0 205 mA 1 2 mA 0 04 mA 0 04 mA 1 0 05 mA VLCD 24V 1 0 05 mA VLCD 24V VIN 0 to V V 5V oscillation external clock Voc 5 V f 270 kHz OSC V V5 1 5 bias V5 1 4 bias Refer to the Electrical Characteristics Notes section following these tables Notes 6 15 15 1
74. ng MPU with LCM 5 3 Instruction and display correspondence 2 1 Driver circuit block diagram 6 Precaution on programming 2 2 Interfacing to MPU 7 How to check trouble 23 Interface to MPU Error analysis 3 Precautions on constituting hardwares 7 1 data is displayed 3 1 Chip select ie ee ee ee 7 2 The system cannot be initialized or it is 3 2 Ability of driving bus unstable ee lt lt 3 3 Power supply voltage for liquid crystal 7 3 The character display is erroneous display drive 7 4 Data cannot be read 4 Initialization 2 5 Others iua 4 1 Intializing by internal reset circuit 8 Block diagram and functions of each block 4 2 Initializing by instruction se 8 1 Block diagram of 44780 5 Instruction 8 2 Function of each block 5 1 Outline of instruction ENGR er INTRODUCTION FEATURES The LCD D HD44780 is a dot matrix liquid crystal display Capable interfacing to 4 bit or 8 bit MPU controller amp driver LSI that displays alphanumerics kana Display data 80 x 8 bits characters and symbols It drives dot matrix liquid cry
75. ntry Mode 9 9 i rod HITACHI_ Sets mode for display shift at the time of write Write Data RAM DD RAM 1 20 0 0 1 0 0 0 Write Data to CG RAM OO RAM 0 1 0 0 1 4 0 t 0 0 1 0 O 4 0 0 1 write Data to CG RAM DO RAM Writes Space Writes Write Data CG RAM DD RAM 1 0 1 i 1 Writes 07 ispi hif p 14 2 gt A 3 1 0 0 5 MECROKO Shifts only the cursor position to the left i m Cursor or Display Shift d MICROKDO Shifts anly the cursor position to the left a er ER lcm Write Data CG RAM DD Writes The display moves to 1 0 0 1 0 0 0 0 1 1 poen the left Cursor or Diaplay Shift mi croco MICROCD 107 16 0 0 1 1 1 right 18 Cursor or Display Shift 1 l 4 RE SR TV a Write Data RAM DD RAM LE Weines 09 iy 1 Loess a eee ME NEL i 20 21 Return Home Returns both display and cursor to the original 0 0 0 0 0 po
76. ode Set I D Increments I D 1 or decrements I D 0 the DDRAM address by 1 when a character code 15 written into or read from DDRAM The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1 The same applies to writing and reading of CGRAM S Shifts the entire display either to the right I D 0 or to the left I D 1 when S is 1 The display does not shift 1f S 1s O If S 1s 1 it will seem as if the cursor does not move but the display does The display does not shift when reading from DDRAM Also writing into or reading out from CGRAM does not shift the display Display On Off Control D The display 15 on when D 15 and off when D is 0 When off the display data remains in DDRAM but can be displayed instantly by setting D to C The cursor is displayed when C is 1 and not displayed when C is 0 Even if the cursor disappears the function of I D or other specifications will not change during display data write The cursor is displayed using 5 dots in the 8th line for 5 x 8 dot character font selection and in the 11th line for the 5 x 10 dot character font selection Figure 13 B The character indicated by the cursor blinks when B is 1 Figure 13 The blinking is displayed as switching between all blank dots and displayed characters at a speed of 409 6 ms intervals when f or fosc is 250 kHz The cursor and blinking can be set to display simultaneously The blinking frequen
77. on for the LCD output level is specified as LCD voltage VLCD Output pin Pins CL2 M D Voc PMOS ot o NMOS Input enable Output enable NMOS HITACHI output circuit tristate 221 HD44780U 6 Applies to input pins and I O pins excluding OSC1 pin 7 Applies to I O pins 9 Applies to output pins 9 Current flowing through pull up MOSs excluding output drive MOSs 10 Input output current is excluded When input 15 at an intermediate level with CMOS the excessive current flows through the input circuit to the power supply To avoid this from happening the input level must be fixed high or low 11 Applies only to external clock operation Oscillator 0 7 Vo 0 5 Vec 0 3 Vec Open Duty x 100 Th TI 12 Applies only to the internal oscillator operation using oscillation resistor OSC1 75 2 when Vcc V 91 2 when Vcc 5 V Since the oscillation frequency varies depending the OSC1 OSC2 OSC2 pin capacitance the wiring length to these pins should be minimized Vcc 25 V 500 400 N N I 300 270 200 100 50 75 100 150 222 HD44780U 13 RCOM is the resistance between the power supply pins
78. or crystal 5 display drive Parallei serial data conversion Mi gt circuit 40 bit shift register D Paralia data seria deta 8 2 Function of each block 1 Register The HD44780 has two 8 bit registers an instruction re gister IR and data register DR The IR stores instruction codes such as display clear and Cursor shift and address information for display data RAM DD RAM and character generator RAM RAM The IR can be written from the MPU but not read by the MPU The DR temporarily stores data to be written into the DD RAM or the CG RAM and data to be read out from DD RAM or CG RAM Data written into the DR from the MPU is automatically written into the DD RAM or the CG RAM by internal operation The DR is also used for data storage when reading data from the DD RAM or the CG RAM When address information is written into the IR data is read into the DR from the DD RAM or the RAM by internal operation Data transfer to the MPU is then completed by the MPU reading DR After the MPU reads the DR data in the DD RAM or CG RAM at the next address is sent to the DR for the next read from the MPU Register selector RS signals make their selection from these two registers HD44780U LCD II Dot Matrix Liquid Crystal Display Controller Driver HITACHI Description The HD44780U dot matrix liquid crystal display controller and driver LSI displays alphanumerics Japanese kana charac
79. ormed by the MPU as explained in the section Initializing by Instruction Instructions Outline Only the instruction register IR and the data register DR of HD44780U can be controlled by MPU Before starting the internal operation of the HD44780U control information is temporarily stored into these registers to allow interfacing with various MPUs which operate at different speeds or various peripheral control devices The internal operation of the HD44780U is determined by signals sent from the MPU These signals which include register selection signal RS read write signal R W and the data bus DBO to DB7 make up the HD44780U instructions Table 6 There are four categories of instructions that e Designate HD44780U functions such as display format data length etc e Set internal RAM addresses e Perform data transfer with internal RAM e Perform miscellaneous functions 190 HITACHI HD44780U Normally instructions that perform data transfer with internal RAM are used the most However auto incrementation by 1 or auto decrementation by 1 of internal HD44780U RAM addresses after each data write can lighten the program load of the MPU Since the display shift instruction Table 11 can perform concurrently with display data write the user can minimize system development time with maximum programming efficiency When an instruction is being executed for internal operation no instruction other than the bu
80. r more than 100 us RS RW DB7 DB6 085 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 Function set Interface is 8 bits long RS R W DB7 DB6 DB5 DB4 BF can be checked after the following instructions 0 0 0 When BF is not checked the waiting time between instructions is longer than the execution instuction time See Table 6 Function set Set interface to be 4 bits long Interface is 8 bits in length Function set Interface is 4 bits long Specify the number of display lines and character font The number of display lines and character font cannot be changed after this point O olo oj oiz o OIO OIT O Display off Display clear Initialization ends Entry mode set Figure 26 4 Bit Interface 213 HITACHI HD44780U Absolute Maximum Ratings Item Symbol Power supply voltage 1 V Power supply voltage 2 Vs 5 Input voltage Vt Operating temperature Tx otorage temperature ds Value 0 3 to 7 0 0 3 to 13 0 0 3 to V 0 3 20 to 75 55 to 125 Unit Notes V 1 V 1 2 V 1 C C 4 Note Ifthe LSI is used above these absolute maximum ratings it may become permanently damaged Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation If these electrical characteristic conditions are also exceeded the LSI will malfunct
81. racter Character Cursor generator generator and RAM ROM blink CGRAM CGROM controller 64 bytes 9 920 bits Parallel serial converter and attribute circuit V2 V3 V4 V5 169 HITACHI HD44780U LCD II Family Comparison Item Power supply voltage 1 4 bias 1 5 bias Liquid crystal drive voltage VLCD Maximum display digits per chip Display duty cycle CGROM CGRAM DDRAM Segment signals Common signals Liquid crystal drive waveform Oscillator Clock source R oscillation frequency frame frequency resistance Instructions CPU bus timing Package 170 HD44780S 5 V 10 3 0 to 11 0V 4 6 to 11 0V 16 digits 8 digits x 2 lines 1 8 1 11 and 1 16 7 200 bits 160 character fonts for 5 x 7 dot and 32 character fonts for 5 x 10 dot 64 bytes 80 bytes 40 16 A External resistor external ceramic filter or external clock 270 kHz 30 59 to 110 Hz for 1 8 and 1 16 duty cycles 43 to 80 Hz for 1 11 duty cycle 91 2 HD44780U 2 7 to 5 5 V 3 0 to 11 0 3 0 to 11 0V 16 digits 8 digits x 2 lines 1 8 1 11 and 1 16 9 920 bits 208 character fonts for 5 x 8 dot and 32 character fonts for 5 x 10 dot 64 bytes 80 bytes 40 16 A External resistor or external clock 270 kHz 30 59 to 110 Hz for 1 8 and1 16 duty cycles 43 to 80 Hz for 1 11 duty cycle 91 2 when 75 296 when
82. relationships between DDRAM addresses and positions on the liquid crystal display The DDRAM address is set in the address counter AC as hexadecimal e line display N Figure 2 When there are fewer than 80 display characters the display begins at the head position For example if using only HD44780 8 characters are displayed See Figure 3 When the display shift operation is performed the DDRAM address shifts See Figure 3 High order Low order I bits gt bits gt Example DDRAM address 4E AC nnnm Figure 1 DDRAM Address Display position digit 79 80 1 2 3 4 5 DDRAM sedes 00 02 03 04 ef aF hexadecimal Figure2 1 Line Display Display position DDRAM 00 address For shift left 01102 03 04 05106 07 08 shift right 4 0001 02 0304 05 06 Figure 3 1 Line by 8 Character Display Example 177 HITACHI HD44780U 2 line display N 1 Figure 4 Case 1 When the number of display characters 15 less than 40 x 2 lines the two lines are displayed from the head Note that the first line end address and the second line start address are not consecutive For example when just the HD44780 15 used 8 characters x 2 lines are displayed See Figure 5 When display shift operation is performed the DDRAM address shifts See Figure 5 Display position 1 2 3 4 5 39 40 boram _ 0001 02 08 Q4 2827 address
83. rewrite character patterns by program For 5 x 8 dots eight character patterns can be written and for 5 x 10 dots four character patterns can be written Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM See Table 5 for the relationship between CGRAM addresses and data and display patterns Areas that are not used for display can be used as general data RAM Modifying Character Patterns e Character pattern development procedure The following operations correspond to the numbers listed in Figure 7 Determine the correspondence between character codes and character patterns Create a listing indicating the correspondence between EPROM addresses and data Program the character patterns into the EPROM Send the EPROM to Hitachi Computer processing on the EPROM 15 performed at Hitachi to create a character pattern listing which is sent to the user pa ee ee e 6 If there are no problems within the character pattern listing a trial LSI 15 created at Hitachi and samples are sent to the user for evaluation When it is confirmed by the user that the character patterns are correctly written mass production of the LSI proceeds at Hitachi 180 HITACHI HD44780U Hitachi Computer Determine processing character patterns Create character Create EPROM pattern listing address data listing Evaluate Write EPROM character patterns
84. rformed for the first and second lines In the example of Table 13 the display shift is performed when the cursor is on the second line However if the shift operation is performed when the cursor is on the first line both the first and second lines move together If the shift 15 repeated the display of the second line will not move to the first line The same display will only shift within its own line for the number of times the shift is repeated Note When using the internal reset the electrical characteristics in the Power Supply Conditions Using Internal Reset Circuit table must be satisfied If not the HD44780U must be initialized by instructions See the section Initializing by Instruction 206 HITACHI Table 11 4 Instruction RS R W 0 7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Display Power supply on tne HD44780U is initialized by the internal reset circuit Function set 0 0 0 0 1 Display on off control 0 0 0 0 0 Entry mode set 0 0 0 0 0 Write data to CGRAM DDRAM 1 0 0 1 0 Write data to CGRAM DDRAM 1 0 0 1 0 Write data to CGRAM DDRAM 1 0 0 1 0 Entry mode set 0 0 0 0 0 Write data to CGRAM DDRAM 1 0 0 0 1 1 0 1 0 u H_ 0 0 HI 0 1 0 1 1 1 0 0 HITACHI HD44780U 8 Operation 8 Digit x 1 Line Display Example with Intern
85. sition Address NER EMINER 2 4 bit operation 8 digit x 1 line display using internal reset The program must set functions prior to 4 bit operation The following table shows an example When power is turned on 8 bit operation is automatically selected and the first write is performed as an 8 bit operation Since 4 bit operation B digit 1 line display using internal reset Power supply ON 044780 is initialized by the internal reset circuit Function Set RS R W DB DB4 0 0 0 0 1 0 Function 0 0 0 0 1 0 0 0 0 lt Display Control 0 0 0 0 0 0 0 0 1 1 1 0 Entry Mode Set 0 0 0 0 0 0 Write Data CG RAM DD RAM 1 0 0 1 1 0 1 0 0 0 Hereafter contro is the same as 8 bit operation Display nothing is connected to DB a rewrite is then required However since one operation is completed in two access of 4 bit operation a rewrite is needed as a function see the following table Thus DB of the function set is written twice Initialized No display appears Sets to 4 bit operstion In this case operation is handled as 8 bits by initialization and only this instruction completes with one write Sets 4 bit operation and selects 1 line display and 5 x 7 dot character font 4 bit operation starts from this point on and resetting is
86. ss set in the address counter AC For example Figure 8 when the address counter 15 08H the cursor position is displayed at DDRAM address 08H 6 AC5 4 2 1 ACO ERE For a 1 line display Display position 1 2 3 4 5 6 7 8 9 10 11 DDRAM paara mm os or a8 ee on For a 2 line display cursor position Display position 1 2 3 4 5 11 DDRAM address hexadecimal cursor position Note The cursor or blinking appears when the address counter AC selects the character generator RAM CGRAM However the cursor and blinking become meaningless The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address Figure8 Cursor Blink Display Example 188 HITACHI HD44780U Interfacing to the MPU The HD44780U can send data in either two 4 bit operations one 8 bit operation thus allowing interfacing with 4 or 8 bit MPUs e For 4 bit interface data only four bus lines DB4 to DB7 are used for transfer Bus lines DBO to DB3 are disabled The data transfer between HD44780U and the MPU 15 completed after the 4 bit data has been transferred twice As for the order of data transfer the four high order bits for 8 bit operation DB4 to DB7 are transferred before the four low order bits for 8 bit operation DBO to DB3 The busy flag must be checked one instruction after the 4 bit data has been transferred twice Two
87. stal 80 characters max display under 4 bit or 8 bit microcomputer or microprocessor Character generator ROM control All the functions required for dot matrix liquid crys Character font 5x 7 160 characters tal display drive are internally provided on one chip Character font 5x 10 dots 32 characters The user can complete dot matrix liquid crystal display sys Both display data and character generator RAMs can be tems with less number of chips by using the LCD II 044780 read from the MPU If a driver 151 HD44100H is externally connected to the 9 Wide range of instruction functions 7 44780 up to 80 characters can be displayed Display clear Cursor home Display ON OFF Cursor The is produced in the CMOS process Therefore the ON OFF Display character blink Cursor shift Display combination of the with a CMOS microcomputer shift microprocessor can accomplish a portable battery drive Internal automatic reset circuit at power ON Internal device with lower power dissipation reset circuit 1 Applicable type 1 1 tine series 2 2 line series 3 4 line series 2 Connecting MPU with LCM 2 1 Driver circuit block diagram Figure 1 shows the driver circuit block diagram of LCM with built in controller LSI Controller LSI HD44780 is built in this LCM Also extended LCD driver LSI is built in the LCM that displays more than 16 digits Ligued erwul dispi module
88. sy flag address read instruction can be executed Because the busy flag is set to while an instruction is being executed check it to make sure it is 0 before sending another instruction from the MPU Note Be sure the HD44780U 15 not in the busy state BF 0 before sending an instruction from the MPU to the HD44780U If an instruction 15 sent without checking the busy flag the time between the first instruction and next instruction will take much longer than the instruction time itself Refer to Table 6 for the list of each instruc tion execution time Table 6 Instructions Execution Time Code max when or Instruction RS R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Description fosc is 270 kHz Clear 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets display DDRAM address 0 in address counter Return 0 0 0 0 0 0 0 0 1 Sets DDRAM address 0 1 52 ms home address counter Also returns display from being shifted to original position DDRAM contents remain unchanged Entry 0 0 0 0 0 0 0 1 D S Sets cursor move direction 37 us mode set and specifies display shift These operations are performed during data write and read Display 0 0 0 0 0 0 1 Sets entire display on off 37 us on off cursor on off C and blinking control of cursor position character B 0 0 0 0 0 1 S C R L Moves cursor and shifts 37 us display display without changing shift DDRAM contents Function 0 0 0 0 1 DL
89. t change during display data write The cursor is displayed using 5 dots in the 8th line when the 5 x 7 dot character font is selected and 5 dots in the 11th line when the 5 x 10 dot character font ts selected B The character indicated by the cursor blinks when B ore 1 The blink is displayed by switching between all Code blank dots and display characters at 409 6 ms interval No effect when fo c 250 kHz The cursor and the Sets the DD RAM address O in address counter Returns display to its original status if it was shifted DD RAM contents do not change The cursor or blink go to the left edge of the display the first line if 2 lines are displayed Entry mode set RS 084 Code 900000008 1 0 1 5 1 0 1 decrements 1 0 0 the DD RAM address 1 when a character code is written into or read from the DD RAM The cursor or blink moves to the right when incremented by 1 and to the left when decremented by 1 The same applies to writing and reading of CG RAM S Shifts the entire display either to the right or to the left when S is 1 to the left when 1 0 1 and to the right when 1 0 0 Thus it looks as if the cursor stands still and the display moves The display does not shift when reading from the DD RAM when writing into or reading out from the CG RAM does it shift when 5 0 x 7 dot character blink can be set to displa
90. ters and symbols It can be configured to drive a dot matrix liquid crystal display under the control of a 4 or 8 bit microprocessor Since all the functions such as display RAM character generator and liquid crystal driver required for driving a dot matrix liquid crystal display are internally provided on one chip a minimal system can be interfaced with this controller driver A single HD44780U can display up to one 8 character line or two 8 character lines The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace LCD II with an HD44780U The HD44780U character generator ROM is extended to generate 208 5 X 8 dot character fonts and 32 5 x 10 dot character fonts for a total of 240 different character fonts The low power supply 2 7V to 5 5V of the HD44780U is suitable for any portable battery driven product requiring low power dissipation Features 5x8 and 5 10 dot matrix possible Low power operation support 2 7 to 5 5V e Wide range of liquid crystal display driver power 3 0to e Liquid crystal drive waveform A One line frequency AC waveform Correspond to high speed MPU bus interface 2 MHz when 5V 4 bit or 8 bit MPU interface enabled 80x 8 bit display RAM 80 characters max e 9 920 bit character generator ROM for a total of 240 character fonts 208 character fonts 5 x 8 dot 32 character fonts 5 x 10 dot 167 HD447
91. ting by 1 of HD44780 internal RAM addresses after each data write lessens the MPU program load The display shift is especially able to perform concurrently with display data write enabling the user to develop systems in minimum time with maximum programming efficiency For an explana tion of the shift function in its relation to display see 5 3 When an instruction is executing during internal operation no instruction other than the busy flag address read instruction will be executed Because the busy flag is set to 717 while an instruction is being executed check to make sure it is on 1 before sending an instruction from the MPU Note 1 Make sure the HD44780 is not in the busy state BF 0 before sending the instruction from the MPU to the HD44780 f the instruction is sent without checking the busy flag the time between first and next instructions is much longer than the instruction time See Table 2 for a list of each instruction execution time Note 2 After executing instruction of writing data to CG DD RAM or reading data from CG DD RAM RAM address counter is automatically incremented by 1 or decrement ed by 1 in this case this shift is executed after Busy Flag is set to Low is stipulated the time from the fall edge of busy flag to the end of address counter s renewal Busy signal Busy Address counter m DB t ADD tADD depends on the operating frequency 1 5
92. tion at the head of program that accesses HD44780 before executing all instructions and not change the data of the Instruction Register in the pro gram The data of function register can be changed by the program as follows a eChanging of DL Data Length ePerform the instruction appointed in 4 2 2 when DL is changed from 8 bit length to 4 bit length mode ePerform the instruction appointed in 4 2 1 when DL ts changed from 4 bit length to 8 bit length mode b eChanging of Column Number ePerform the instruction of function set after execut ing instruction of display clear or display off In this case sequence of AC and DD RAM must be changed Thus rewrite the address set register after that eChanging Font There is no problem in this case but for dual line dis play the font mode of 5 x 11 cannot be selected this mode is forbidden by hardware When N or F is changed power supply voltage for LCD must be changed If not changed crosstalk wil appear or contrast will be poor 2 3 Busy flagcheck HD44780 is produced in the CMOS process therefore internal executing time is long Standard time is 40 us 1 6 ms This varies by instruction When the high speed MPU controls it check the busy flag before performing instruction or reading data While internal operation is active Enable signal is not ac cepted Enable signal at reading status register for check ing busy flag is accepted
93. ts 1 2 correspond to CG RAM address bits 4 5 2 bits 4 types 2 RAM address bits 0 3 designate character pattern line position The 11th line is the cursor position and display is performed in logical OR with cursor Maintain the 11th line data corresponding to the cursor display position in the 0 state for cursor display When the 11th line data i 1 bit 1 lights up regardless of cursor existence Since the 12th 16th lines are not used for display they can be used for the genera data RAM 3 Character pattern row positions are the same as 5 x 7 dot character pattern positions 4 RAM character patterns are selected when character code bits 4 7 are all 0 However since character code bit 0 and 3 ar ineffective bits display in the character pattern example is selected by character code 00 01 08 and 09 hexadecimal 1 for CG RAM data corresponds to selection for display and 0 non selection EITINGER 5 Example of interfacing to 280 MPU Above circuit is an example of connection with Z80 MPU and 44780 00 as an I O equipment It can be used as a part of memories by using MREQ signal b AO signal can be used for RS signal AQ 0 Instruction register is selected AQ 1 Data register is selected 6 Example of interfacing to 80 CPU family 80 Note 280 is the trademark of ZILOG U S A In order to check busy flag transfer the data of
94. tterns DDRAM data CGRAM Address CGRAM data 76543210 543210 76543210 High Low High Low High Low T 1 A Character 00 0 0 0 0 pattern 0 0 0 0 0 0 0 0 1 1 ooo o00o00o00 3 Cursor position 0 Oo Oj O O lt a 0000 T 1 Notes 1 Character code bits 1 2 correspond to CGRAM address bits 4 and 5 2 bits 4 types 2 CGRAM address bits 0 to 3 designate the character pattern line position The 11th line is the cursor position and its display is formed by a logical OR with the cursor Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display If the 11th line data is 1 1 bits will light up the 11th line regardless of the cursor presence Since lines 12 to 16 are not used for display they can be used for general data RAM 3 Character pattern row positions are the same as 5 x 8 dot character pattern positions 4 CGRAM character patterns are selected when character code bits 4 to 7 are all 0 However since character code bits 0 and 3 have no effect the P display example above can be selected by character codes 00H 01H 08H and O9H 5 1 CG
95. typ mW Duty Bias Page Model No none wenwe sve m wee I oven Euer wenns o is me 5 LSI oviese 06 18 092020 020 e e t 20400 DV 24210 here 1 160 1 48 DV 40200 id DV 40400 rn M ce ODD OOD Om u Seve cases us SEX DV 16230 DV 16235 224999 8 P 26535223 O C DV 24210 DV 40200 mv Inverter f r EL Passend f r transflektive Versionen mit Elektrolumineszenzfolie SDEC I001 SDEC I002 SDEC I003 re _ _ Pin 0 8 Pin 2 0 6 Pin 0 8 SDEC I001 G Arbeitstemperaturbereich 10 60 Celsius Lagertemperaturbereich 20 70 Celsius Ausgang f r EL Folie Gnd Eingang 5 V DC eee ES 4p EE ETTINGER HOW TO USE HITACHI S BUILT IN CONTROLLER DRIVER LCD II HD44780 DOT MATRIX LCD MODULE 1 Applicable type 5 2 Description of details 2 Connecti
96. y simultaneously The blink frequency changes according to the reciprocal 409 6 d of or Tage 270 379 2 ms when Alternating display 270 kHz IE Cursor ZZ 5 x 10 dot character font a Cursor Display Example b Blink Display Exampie 5 Cursor or display shift RS 6 6 DBg Code effect Shifts cursor position or display to the right or left with out writing or reading display data This function 15 used to correct or search for the display In a 2 line display the cursor moves to the 2nd line when it passes the 40th digit of the Ist line Notice that the Ist and 2nd line dis plays will shift at the same time When the displayed data is shifted repeatedly each line only moves horizontally The 2nd line display does not shift into the 1st line posi tion ETTINGER S C 0 0 Shifts the cursor position to the left AC is decremented by one 0 1 Shifts the cursor position to the right AC is incremented by one 1 0 Shifts the entire display to the left The cursor follows the display shift shifts the entire display to the right The cursor follows the display shift Address counter AC contents do not change if the only action performed is shift display 6 Function ser RS R W 08 coe fowler No effect DL Sets interface data length Data is sent or received in 8 bit lengths DB when DL 1 and in 4 b

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