SEED-DEC138
Contents
1. iP arty Network EME V SEED International Ltd TEXAS INSTRUMENTS SEED DEC138 Hardware User Manual 2010 07 DSP Development Systems Current version SEED DEC138 Hardware User Manual Document History 1 Board History 5 SEED DEC138 Hardware User Manual Version A 2010 11 http www seeddsp com SEED International reserves the right to make changes to its products or to discontinue any product or service without notice Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders Preface Read This Frist About This Manual This document describes the board level operations of the OMAP L138 The SEED DEC138 is based on the Texas Instruments OMAP processor The SEED DEC138 allows engineers and software developers to evaluate certain characteristics of the OMAP processor to determine if the processor meets the designers application requirements Evaluators can create software to execute on board or expand the system in a variety of ways Warranty The warranty period for all hardware and software products manufactured by SEED Electronic Technology Ltd is one year after shipment SEED Electronic Technology Ltd guarantees free of charge repair or replacement for the manufacturer caused damaged products during warranty period Software updates will be sent free of ch2. 2 2 2 3 DA Converter unsere aaa 2 2 2 2 4 Ethernet Interface A es 2 3 2 2 5 MMC SD Media Card 2 3 2 2 6 USB Interface cbe e E ets 2 3 2 2 7 DAT P URS 2 3 Pg SRA 2 3 2 2 9 JTAG Debugger Interface a2 a u 2 3 2 2 10 Expansi n eR RR DEPO 2 4 22 11 Gi ckand LED A ee states 2 4 Power Management 2 5 2 3 1 Power Management Layout and Application 2 5 2 3 2 Power SUpply sus a aaa 2 5 Physical DescriptiODi 3 1 3 1 GENE 3 2 3 2 1 J2 DA OUItpul rrr 3 4 3 2 2 Electrical Motor Interface and AD Input Interface 3 4 320 r MES E 3 4 3 2 4 BUS eee ee E 3 5 325 8 LCD terrace usina 3 8 3 2 6 POWER A ELO OH RS 3 8 3 2 7 JTAG Pin Definition and DIP Switch ee 3 9 3 2 8 J25 SATA dera iii edere 3 9 Figure List Figure SEEDJID EC nist t an a ri 1 2 Figure 2 Block Diagram of the SEED DECTB ik a 1 3 Figure SEED DEGT38 TOPE ae 3 1 Figure 4 SEED DEC138 Bottom Side Table List Table 1 Connector eene nenne ennt nnne nnn nnne n nnns nennt 3 3 APA 3 4 3 3 ERES 3 4 Table 4 J4 3 5 Table 5
3. 3 Physical Description 3 Physical Description 3 1 PCB Layout The top side of the SEE D DEC138 is shown as below N SEED2DEC138 d S Figure 3 SEED DEC138 Top Side The bottom side of the SEED DEC138 is shown as below 3 1 Chapter 3 Physical Description 6 66 E 5212214 Lil DER w afifi 1 us Jun 8 e 3 2 Connector J Jumper 4 J2 Connector Connector Connector Connector Connector Connector 1 Figure 4 S 22 RR Size Location 3 Top 5 Top Function MMC SD Select DA Output Electrical Motor Interface and AD Input Capture Interface USB Interface OTG Expansion Bus USB Interface HOST SEED DEC138 Hardware User Manual 11 3 Top RS232 RS485 Select J Jumper RS232 RS485 J12 Jumper Top Select RS232 RS485 Select 13 Top 16 0 Top J Jumper 3 9 Expansion 1 Connector 4 Bus J 5V Power Cord 17 3 Top 20 4 Top 4 Top J Connector J DIP Switch BOOT J 15V 5VPo wer Cord SD Connector 21 Connector SD 122 Connector 28 Bottom Expansion J23 Connector 90 Bottom Bus Expansion Bus SATA Interface J24 Connector 40 Bottom J25 Connector 22 Bottom Table 1 Connector 3 3 Chapter 3 Physical Description 3 2 1 J2 DA Output Table 2 J2 Definition 3 2 2 J3 Electri
4. 37 38 X2 39 40 1 LCD D6 A A x2 9 4 Y NC 4 42 NC Table 9 LCD Definition 3 2 6 Power Cord Power cord J17 definition Signal Pin uot 2 k DUNG 3 Table 10 J17 Definition 3 8 SEED DEC138 Hardware User Manual Power cord J21 definition Signal 15V 15V GND 45V Table 11 J21 Definition 3 2 7 JTAG Pin Definition and DIP Switch JTAG J19 pin definition 4 42 2 2 O A Table 12 DA Output Definition J20 BOOT mode selection Mode Switch 1 Switch 2 Emulation Debug ON 1 ON 1 NAND8 OFF 1 Default UARTO 1 Table 13 J20 Definition 3 2 8 J25 SATA Interface SATA J25 pin definition 3 9 Chapter 3 Physical Description Pin 2 2 Table 14 J25 Definition
5. HV 0 1 E CLKXO 9 10 E CLKRO L EXSX07 502 EFSRO 2 13 4 00 NC 15 16 NC E CLKX1 17 18 E CLKR1 9 4 20 A EDX 22 23 24 2 GN NC N I NC 29 30 NC CNT 5 9 STATA 33 55 So NC 5 6 NC 3 5 Nc ____ 33 _______39 4 33V Table 7 J16 Definition Expansion bus J24 definition Signal Pin Signal Pin ES gt GND 4 GND a A E EA TA NA ECIKRO 0 8 9 10 1 EDRO 13 ___ NC 15 6 NC 17 18 E CLKR1 E FSR1 19 20 E FSX1 E DHR1 21 22 E NC 23 24 NC E 3 7 Chapter 3 Physical Description GND 25 26 GND ______27 X28 Nc ____ A 8 N 31 32 CNTLO STTO 595 21285 36 2 Table 8 J24 Definition CNTL1 3 2 5 J8 LCD Interface J8 Definition Signal Pin Pin Signal 12 845 1 OO GND 3 ILCD Di 5 6 ILCD 7 LELCDDP2 797 1 LILcpp3 ILCD Did d 12 11000156 LCD 05 13 14 110005 __ LCD D5 5 16 DLCD 17 18 110008 ILCDD9 19 20 ILCD DO LCD DO 21 22 LCD DO LCD D 23 24 11 00 0 ILCD DI 25 26 ILCDD LCD D3 27 28 LCD D4 GND 29530 NC 31 32 LICcDHSYNC VSYNC 3 34 ICDENB NC 35 36 1
6. J6 Definition 3 6 Table 6 J23 Definitigm nnne nnns 3 7 1 6 26 Em 3 7 Table 8 424 DefinitlOni 4 oen e ete oce ens 3 8 Table 9 LCD nnns 3 8 Table 10 J17 Definition ni nuin recen teens 3 8 Table 14 21 Det 3 9 Table 12 DA Output Definition masse 3 9 Table 13 J20 3 9 Table 14 J25 DefinitlOri ttt eet e tts 3 10 SEED DEC138 Hardware User Manual Chapter 1 Functional Overview 1 Functional Overview Chapter 1 provides a description of the SEED DEC138 along with the key features and a block diagram of the circuit board 1 1 Key Features The SEED DEC138 uses OMAP L138 high performance processor from Texas Instruments The 1138 is a dual core device a 300 MHz ARM926EJ S MPU core and a 300 2 C6748 VLIW DSP core The SEED DEC138 board provides rich peripheral interfaces The SEED DEC138 adopts the SEED standard DEC serial board structure that suit a wide variety of application environments The SEED DEC138 operates from 5V and 15V external power supply The 5V input is converted into core voltage 1 2V 1 8V and 3 3V The 3 3V supply is used for the DSP s UO buffers and other chips on the board The 1 2V is the DSP core voltage 1 8V voltage is used for the USB and DDR2 CPU power rails are sequenced on the module panini ii Nar MISEED DEC138 762029701 un Chapt
7. 45 gt AD peoa Transceivers CARO B EXT 4 9 SN74LVTH16245A 4 9 om CES RS232485 44 22255 ek ranscelvers 0 DDR2 0 vona lt gt 0082 A P ETHPHY TS A 3 8 HARDDISK gt SATA gt MMC SDO lt gt T L gt gt SN74LVTH16245A Le LoD TSC 08820018 4 gt RTC USB1 1HOST 44 99 4 0 BOOT MODE 45V 433V 415V 10V POWERI gt POWERS 1 2V 15V 10V POWER gt gt POWERS 1 8V POWERS gt 1 3 SEED DEC138 Hardware User Manual Chapter 2 Board Components 2 Board Components This chapter describes the operation of the major board components on the SEED DEC138 It includes processors module interfaces module and power management module 2 1 OMAP L138 Processors Module 2 1 1 OMAP L138 Processor The SEED DEC138 uses OMAP L138 high performance processor from Texas Instruments The OMAP L138 is a dual core device a 300 MHz ARM926EJ S MPU core and a 300 MHz C6748 VLIW DSP core The OMAP L138 sits at the U25 on the board 2 1 2 DDR2 SEED DEC138 provides 512M DDR2 K4T51163QG HCF7 It is connected to the on chip DDR2 space and sits at the U21 on the board 2 1 3 NAND FLASH The SEED DEC138 provides 512Mb 8 bit NAND FLASH K9F4G0O8U0A PCBO It is connected to the on chip EMIFA space and sits at the U22 on the board 2 1 4 CPLD The CPLD is connected to the EMIFA space The CPLD is used to control peripherals allo
8. arge to the customer during warranty period Information about Cautions The Boards contains Electro static Discharge ESD sensitive devices Take proper precautions to ground yourself before handling the board This Document may contain cautions A caution statement describes a situation that could potentially damage your software or hardware or other equipment The information in a caution is provided for your protection Please read each caution carefully Trademarks SEED is trademark of SEED Electronic Technology Ltd XDS510 XDS560 are trademarks of Texas Instruments Related Documents Application Notes and User Guides Information regarding the OMAP L138 Processor can be found at the following Texas Instruments website http www ti com Information about this production if you need assistance can be found at the following Seed International website http www seeddap com 1 1 1 2 2 1 2 2 2 3 3 1 3 2 Contents Functional OvervieW fn AAA 1 1 Key Features C 1 1 Block DIA Mirada 1 3 Board Components aaa ia 2 1 OMAP L138 Processors Module ee 2 1 2 1 1 OMAR ETC o od 2 1 2 1 2 DORA are ee ee 2 1 2 1 3 NAND D 2 1 um m MM P M MM MI 2 1 SEED DEC138 Peripherals and 2 2 2 2 1 EG al 2 2 2 2 2 AD Data 2
9. cal Motor Interface and AD Input Interface Pin Signal PWMOA CPLDO CPLD1 CPLD2 OO amp Oo Po Table 3 J3 Definition 3 2 3 J4 Capture Interface 3 4 SEED DEC138 Hardware User Manual Table 4 J4 Definition 3 2 4 Expansion Bus Signal Pin Pin Signal 5V 2 5V NC 4 NC 6 10 11 12 NC y o O Ne 15 16 NG NC 17 ___ 18 NO ____ GND 9 5 2 022 Aa ED2 011 25 26 ED 9 3 ED6 E D5 1 32 E D4 E D3 E D2 E D10 33 34 E Di 35 36 E DO 37 38 3 3V NG 39 EA 4204540 EMS 42 EA 13 45 46 12 447448 7 EA 459 7 51 52 6 EA 5542 EM 5250 GD ____ E A3 57 58 E A2 EA 59 33V 62 6 423 2 GN D 64 ___ ____ D 65 D 7 68 9 70 1 72 3 3V WE 6 NC NC 6 NC C 7 3 5 Chapter 3 Physical Description GND 73 74 GND NC 79 80 NC NC NC NC 81 82 Table 5 J6 Definition Expansion bus J23 definition Signal Pin Signal Pin NC 9 10 NC NC NC 17 18 3 6 SEED DEC138 Hardware User Manual GND 73 74 GND 75 6 8 EE 7 NC 79 80 NC NC NC NC 81 82 85 284 WEST 2 87 GND 89 9 0 2 Table 6 J23 Definition Expansion J16 definition Signal Pin Pin Signal 15V 1 2 15V ENDE er 45V 05
10. cate interrupts sources and multiplex with logical controllers The CS2 CS4 CS5 they are the chip select signals from the EMIFA They are connected to the CPLD and control the external devices by selecting the address The CPLD also controls the enable signal for some other devices The CPLD also processes the interrupts between processor and peripherals The CPLD controls the peripheral logics of the SEED DEC138 2 1 Chapter 2 Board Components The CPLD logics include Interrupts status and handshaking signals are CPLD connected to the OMAP L138 Address coding Enable or select some signals 2 2 SEED DEC138 Peripherals and Interfaces 2 2 1 LCD The SEED DEC 138 is equipped with one LCD The signals from the OMAP L138 LCD controller are interfaced through the expansion connectors The SEED DEC138 uses 16bit digital mode TFT565 to control LCD To improve the signals driving power the signals from the are connected to the LCD via SN74LVTH16245A first The touch screen controller TSC on the SEED DEC138 is controlled by the TSC2046 This TSC2046 is used to support standard 4 wire resistive touch panels The TSC2046 is connected to the OMAP L 138 by the SPI1 interface 2 2 2 AD Data Acquisition The SEED DEC138 is integrated with one 3 channel AD data acquisition module ADS8556 It sits at the U11 on the board 2 2 3 DA Converter Module The SEED DEC138 is integrated with one 4 channel DA c
11. ce 5V power supply 2 2 9 JTAG Debugger Interface The SEED DEC138 supports the JTAG debugger interface The J17 is the JTAG debugger of the OMAP L138 and the debugging environment is CCStudio from Texas Instruments The SEED XDS560PLUS is used for debugging The JTAG debugger interface can be used for test debug program run trace and download 2 3 Chapter 2 Board Components 2 2 10 Expansion Bus Memory Bus Memory bus includes Memory interfaces 16 bit data bus 19 bit address bus 4 register space System interface 1 reset output 4 maskable interrupt input Main power supply 3 3V and GND The memory bus is realized through 90 pin 1 27mm x 1 27mm high density shield socket Peripheral Bus The peripheral bus includes On chip peripheral interfaces 2 McBSP Handshake interfaces 2 controller output 2 status input Supportive power supply 3 3V 5V and GND The peripheral bus is realized through 40 pin 1 27mm x 1 27mm high density shield socket 2 2 11 Clock and LED The clock of the SEED DEC138 contains crystal and 1 clocking processor CY22831 The input of the CY22381 is 10M outputs are 50M 31 5M and 100M The SEED DEC138 provides the following clocks Y1 10M crystal uses as the clock signal source for clock processor Y2 32 768K crystal uses as the clock signal for RTC 24M crystal uses as the clock signal for CPU 31 5M clock for CPLD frequency division fo
12. er 1 Functional Overview L u mes d wun Figure 1 SEED DEC138 The SEED DEC138 hardware key features include a 0000000000000 1 2 1138 from Texas Instruments a 300 MHz ARM926EJ S MPU and 300 MHz C6748 VLIW DSP 512Mb DDR2 K4T51163QG HCF7 4Gb NAND FLASH 400800 2 UART RS232 and RS485 RS232 jumper selection 2 USB port OTG2 0 and HOST MMC SD SATA 10 100 Mbps Port Ethernet Phy Motor port 2 group eHRPWM AD 6 channel 16 bit AD converter input voltage range 12V 12V DA 4 channel 12 bit DA converter output voltage range 10V 10V or OV 10V EXT_BUS data bus address bus control signals status signals chip select signal McBSPO McBSP1 and etc Interface voltage level 3 3V 45V LCD TFT565 1 2 Block Diagram SEED DEC138 Hardware User Manual The block diagram of the SEED DEC138 is shown as below Figure 2 Block Diagram of the SEED DEC138 BUS NAND ar 1 24 98 ES gt FLASH CP CE2 lt gt CE4 HRPWMO 1 BUS gt Transceivers DA CH F A 95232
13. onverter module DAC7724 Its features include 4 channel analogue output 12 bit resolution 15V power supply 10V signal range Oooo The high reference voltage of the DA converter module is 10V The low reference voltage can be selected at either OV or 10V Note 114 is connected 115 is empty 2 2 SEED DEC138 Hardware User Manual 10V L14 is empty L15 is connected The default voltage of the SEED DEC138 board is 10V 2 2 4 Ethernet Interface The SEED DEC138 incorporates an 10M 100M Ethernet interface KSZ8001 DP83640 multiplex RMII interface The RJ 45 jacks have 2 LEDs integrated into their connector The LEDs are green and yellow and provide link and transmit status from the ethernet controller 2 2 5 MMC SD Media Card Interfaces The SEED DEC138 supports a group of MMC SD interface four groups data line mode and 3 3V operating voltage 2 2 6 USB Interface The SEED DEC138 incorporates two on chip USB controllers USBO OTG interface USB1 HOST interface OTG power mode is realized by TPS2065D Each of the two USB interfaces are protected by the TPDEOO01RSE 0 2 2 7 UART The OMAP L138 supports 3 UARTs Since the pins are multiplexed the SEED DEC138 supports 2 UARTs UARTO and UART2 The UARTO is driven to J9 to realize the RS232 The UART2 is driven to J14 to realize the RS232 or RS485 The selection is through the jumper J11 J13 2 2 8 SATA The OMAP L138 supports 1 SATA interfa
14. r AD 50M clock for the Ethernet interface 100M for the SATA 0000000 SEED DEC138 provides 3 LED 0315 the indicator for the 3 3V power supply Di and D2 are the indicator for the program debugging 2 4 SEED DEC138 Hardware User Manual 2 3 Power Management Module 2 3 1 Power Management Layout and Application The SEED DEC138 provides two sources of power supply external power supply the electrical power being supplied from the external and the internal power supply it is generated from the on board power processor External power input 15V 15V 5V On board power supply 1 2V 1 2V_RTC 1 8V 3 3V 3 3VA 43 3 5 45V LCD 5V USB 10VA 10VA 15VA 15 EMAC_1 8V 1 8 1 8VALL The applications of these power supply include 3 3V DSP and external devices 5V SATA LCD USB and interfaces 1 2V DSP core 1 8V USB and DDR2 1 2V_RTC 3 3V_RTC RTC 10V 10V 15VA 15VA DA EMAC_1 8V 3 3VA EMAC_1 8VA EMAC_1 8VALL Ethernet interface 00000000 2 3 2 The SEED DEC138 incorporates three power processors TPS65053 TPS77001 and LM4040A10 The TPS65053 is powered by 5V input it converts to 1 8V 1 2V 3 3V and the 3 3V TPS77001 coverts the 3 3 to 1 2V_RTC The LM4040A10 generates the 10VA for the analogue module 2 5 SEED DEC138 Hardware User Manual Chapter
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