MK71050-03 Bluetooth Low Energy Wireless Module
Contents
1. EEPROM 128Kbit R4 pisino 1 i 1 1 LLYBOGA HH 2 v lt v c1 o o i N gt pisino gt R R c2 GND Package GND X1 26MH c12 PLLLPF J x a ALVDL3IH gt R R1 c5 9 c10 a c16 ik GOWINO wwe eee eee oQ INVINO Sara ress elnpou pisino NC ANT_GND z 2 23 FEDK71050 03 01 MK71050 03 M Pin assignment anony aNO LNY _ aN97LNv aNO LNY aN7LNv aNO LNY _ aN97LNv aNDTLNV anginy ANT_GND ANT_GND Ne ANT_GND ANT_GND _ ANT GND ANT_GND Nc Ne ANT_GND OUT_ANT Nc OUT MOD at GND Ao VDDCORE RESETB VDDBAT TMODE LPCLKBUS FETGATE LPCLKIN GPI03 PS_ CONTROL REGC GPIO2 1RQ EFUSE GPIO1 WAKEUP SPIDIN GPIOO RF_ACTIVE aNd aNd vas 199 LNOGIdS SOXIdS 10145 qx Lyvn GXH 14 TOP VIEW 3 23 M Pin definitions Pin Name Ana Dig I O type FEDK71050 03 01 MK71050 03 Function ANT_GND Antenna GND Refer to PIN descriptions NC No connection Refer to PIN descriptions ANT_GND Antenna GND Refer to PIN descriptions NC No connection Refer to PIN descriptions OUT2. SPIXCS 15 02 5 SPIDIN OUT_ANT 26 OUT_ MOD GPIO1 WAKEUP m ontrol Signal 32 GPIO2 IRQ AO 25 33 Ki GPIO0 RF ACTIVE HOST CPU 12 _Low Power Clock 9 VDDCORE LPOEKIN 5 32 768kHz 11 7 LPCLKBUS 10 i Power Supply 1 VDDBAT RESETB 31 2 Reset signal up 8 19 22 19 20 GND UART_TXD 21 4 UART RXD 10k Q 10uF 7777 scl SDA 28 GPIO3 PS_CONTROL FETGATE 29 1 SPIDOUT becomes Hi Z input when SPIXCS is High So please insert the pull up or pull down resister 2 Please be careful to satisfy the RESETB propagation delay time Tro And if the state of reset signal is undefined after power on reset of HOST CPU please insert the pull up or pull down resistor 15 23 FEDK71050 03 01 MK71050 03 M Appendix PCB Land Pattern 6 325 9 6 P0 8X12 6 325 0 8 8 6 4 9 35 m m m ch lh a il g H th o H O uj a gt R A A ul w 0 50 0 05 1 80 0 05 1 2540 05 Unit mm 16 23 FEDK71050 03 01 MK71050 03 Metal Keep Out Area Reference layout of RF trace line Metal exclusion zone to edge of board no metal on any layer except mechanical LGA pads 20 0mm min 5 775mm 4 925mm OD 22 AA EA zz 22 2mm max HE of RF trace line 5 Ll 5 12 co L J bd BOARD TOP V
3. VDD VDDBAT GND TRDL TRPLS RESETB Povver on reset function Reset function from RESETB pin t is possible to reset internal circuit by asserting RESETB after power supply is on It is possible to reset internal circuit by same way even if it is not power sequence Internal circuit will move to normal state after oscillation circuit become stable by clock stabilizing circuit after reset function Power on 20 to 70 deg C Item Symbol Condition Min Typ Max Unit A holies ot While power on VDD pin rising time TPWON VDD pins VDDBAT 0 2 1 5 ms Power off Time TPvvoFF VDD pins VDDBAT 10 m ms nitial povver level VBooT 1 VDD pins VDDBAT 0 3 V VDDBAT GND 0V 1 TPWOFF 12 23 FEDK71050 03 01 MK71050 03 M Operating mode Following 3 operating modes are available to use BACI Mode Application mode using SPI SLAVE interface HCI mode Bluetooth LE standard compliant using UART interface HCI Mode RAM Mode Function extention mode downloading user program to internal memory M Operating mode configuration Configuration of operating mode will be done by pin status shown in table below The symbol X is don t care it has to be used as normal function When configure operating mode reset has to be issued RAM mode and Debug mode is distinguished by configuration parameter 2 Pin confitions Operating mode UART_RXD BLI Mode Low HCI Mode 1 High RA
4. IO pins with Oz B symbol in pin definition 4 IO pins with laH Is XsH symbol in pin definition Recommended Operating Conditions Item Symbol Condition Min Typ Max Unit Power Supply VDD VDDBAT pin 1 8 3 3 3 6 V Ambient Temperature Ta 20 25 70 C Rising time digital input pins tIR1 Digital input inout pins 20 Ns Falling time digital input pins ties Digital input inout pins 20 Ns Load capacitance digital CDL Digital output inout pins 20 pF Lovv Povver Clock 250 250 32 768 kHz FLPCK1 LPCLKIN pin opm 32 768 ggm kHz Low Power Clock External input from LPCLKIN Input Duty Ratio DLPCK1 pCLKBUS pin left OPEN 39 2 R RF Channel frequency 1 FRF OUT_MOD pin 2402 2480 MHz RF input level PRFIN 70 10 dBm 1 Frequency range F 2402 2 x k MHz here k 0 1 2 39 8 23 Current consumption FEDK71050 03 01 MK71050 03 Ta 25 deg C Item Symbol Condition Min Typ Max Unit DBi Deep Sleep state External Lovv m 08 m GA Power Clock IDD2 Idle state mA Current Consumption DD RF RX state 5 mA RF TX state 6dBm 9 mA DD4 RF TX state 0dBm 10 9 mA note Condition Taz25dec C VDDBAT 3 3V DC characteristics Ta 20 to 70 deg C Item Symbol Condition Min Typ Max Unit H level Voltage Input vint 1 71 2 5 VDD v VDD L level Voltage input 1 2
5. ku Yokohama 222 8575 Japan http www lapis semi com en 23 23
6. no responsibility whatsoever for any dispute concerning such rights owned by third parties arising out of the use of such technical information 4 The Specification contains information related to the LAPIS Semiconductor s copyright and technical know how Any use of them other than pertaining to the usage of appropriate products is not permitted Further the Specification in part or in whole may not be reprinted or reproduced and disclosed to third parties without prior consent of LAPIS Semiconductor Precautions for the Products ePrecautions for Safety 1 The Products are designed and produced for application in ordinary electronic equipment AV equipment OA equipment telecommunication equipment home appliances amusement equipment etc 2 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representative transportation equipment i e cars ships trains primary communication equipment traffic lights fire crime prevention safety equipment medical systems servers solar cells and power transmission systems 3 Do not use our Products in applications requiring extremely high reliability such as aerospace equipment nuclear power control systems and submarine repeaters 4 The Products are designed for use in a standard environment and not in any special environments Application of the Products in a special envi
7. operating in conjunction with any other antenna or transmitter As long as the conditions above are met further transmitter testing will not be required However the OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed for example digital device emissions PC peripheral requirements etc IMPORTANT NOTE In the event that any of these conditions can not be met for example the reference trace specified in this manual or use of a different antenna then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product In these circumstances the OEM integrator will be responsible for re evaluating the end product including the transmitter and obtaining a separate FCC authorization CE R amp TTE MK71050 03 complies with the radio test requirements EN 300 328 V1 8 1 which is based on the R amp TTE Directive 1999 5 EC EMC and Safety test that is required for the CE marking should be done in the final end product Bluetooth SIG Qualification End Product MK71050 03 is listed on the Bluetooth SIG website as qualified End Products QDID 66491 External MCU Applications L BLE STACK Profiles BAS BLS DIS HRS HTS IAS LLS TPS MK71050 03 End Product QDID 66491 Component Tested QDID 47641 18 23 FEDK71050 03 01 MK71050 03 M Caution When implementing this prod
8. 5 0 X0 3 LPCLKIN pin s H level Voltage Input 3 1 VoD v LPCLKIN pin L level Voltage input ME 3 D m A VDD x H level Voltage Output VOH lOH 2mA 4 5 0 75 VDD V VDD x L level Voltage Output VOL 10 2mA 4 5 0 0 25 Input pin capacitance CIN F 1MHz 1 2 4 5 8 pF 1 10 pins with symbol in pin definition 10 pins with IPD symbol in pin definition IO pins with IsH symbol in pin definition 4 pins with Oz symbol in pin definition IO pins with Bz symbol in pin definition 9 23 RF Characteristics FEDK71050 03 01 MK71050 03 Ta 20 to 70 deg C Remarks All timing specification is defined at VDDIO x 20 and VDDIO x 80 SPIXCS input setup hold time have to be at least 1cycle of SPICLK clock frequency Measurement point 0 8VDDIO ____Measurement_ 0 8VDDlo 0 2VDDIO point 0 2VDDlo Item Symbol Condition Min Typ Max Unit TX Maxium TX power Pout OdBm setting 0 dBm Ip IUU Fcerr Master Clock tolerance 40 ppm 40 40 ppm Modulation data rate DRATE 1 Mbps Modulation index 0 45 0 50 0 55 Bandwidth bit rate products BT BT GFSK 0 5 RX Receiver Sensitivity Psens PER 30 8 1 85 70 dBm Maximum input level 2 PRxmax PER 30 8 1 m 10 dBm Prssimax Uppe
9. 71050 03 NC No connection Refer to PIN descriptions ANT_GND Antenna GND 5XRefer to PIN descriptions GND GND M PIN descriptions I O symbol F RF input output pin Digital input pin pd Digital input with pull down resistor AH Analog High voltage input pin lsH Low power clock input pin Low power clock oscillator pin Oz Digital output pin with 2mA load capability B2 Digital bidirectional pin with 2mA load capability B2Pu Digital bidirectional pin with 2mA load capability and pull up resistor RF Analog signals PINNAE Status Value Active Function at reset Level Output from Antenna rz OUT_ANT mum nr to be connected to OUT MOD by user s PCB Output from Module 9 OUT MOD e h na kross to be connected to OUT ANT by user s PCB 2 mo mz m analogtestno ba mz m lnalogtestpim 00000 6 XO LPXO signals Pin Name pias Valle Aave Function at reset Level SPI signals Pin Name SEEVE ONE Function at reset Level UART signals Pin Name s 5 Function at reset Level UART_TXD Output High Oz TXD output 5 23 FEDK71050 03 01 MK71050 03 2 signals Pin Name 550 at reset Level B2PU l2C SCL monitor pin Please use this pin open SDA Input Bau ZC SDA monitor pin Please use this pin open 6 GPIO sig
10. IEW 17 23 FEDK71050 03 01 MK71050 03 Radio certitication MIC JAPAN certification no 006 000238 MK71050 03 complies with MIC JAPAN radio certification certification no 006 000238 FCC FCC ID 2ACIJ71050 3 This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation The regulatory label on the final system must include the statement Contains FCC ID 2ACIJ71050 3 or using electronic labeling method as documented in KDB 784748 This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment The antenna used for this transmitter must not be collocated or operating in conjunction with any other antenna or transmitter within a host device except in accordance with FCC multi transmitter product procedures The final system integrator must ensure there is no instruction provided in the user manual or customer documentation indicating how to install or remove the transmitter module except such device has implemented two ways authentication between module and the host system OEM Responsibilities to comply with FCC Regulations This module has been certified for integration into products only by OEM integrators under the following condition The transmitter module must not be colocated or
11. M Mode X 1 Please fix wakeup pin to low level when using in HCI mode Please refer to ML7105C 001 data sheet and associtated documentation for more detail 13 23 FEDK71050 03 01 MK71050 03 E Module dimension 9 50 ek mi 9 10 0 8 8 64 008 10 70 28 13 6079 08 Detail B L 520 170 8 64 5 10 Detail C Substrate back side land pattern tolerance 0 10mm LAPIS Semiconductor Co Ltd ELH a 1 78 0 1515 Ny BU ES E PACKAGE CODE M FLGA52 10 7X13 6 0 80 9Y IRRE CHS PACKAGE BATERIA INIT m TERMINAL PLATING Au DWG No QSL 69255 T1 78 0 15 00 5 NOT INCLUDE WARP OF PACKAGE HA WERE 0 39 REVISION 1 IT 18 DENENSIONS INTERSECTION OF ONLY PACKAGE THICKNESS ist ISSUE Apr 07 2015 REVISED Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 14 23 FEDK71050 03 01 MK71050 03 M Application example MK71050 03 16 2 5 34 36 NC BACI Mode SPIDOUT bal 18 1 3 4 35 37 48 ANT GND SPICLK SPI Interface
12. ROHM GROUP LAPIS SEMICONDUCTOR FEDK71050 03 01 MK71050 03 Bluetooth Low Energy wireless module Overview MK71050 03 is a Bluetooth Low Energy here in after LE wireless module which is integrating ML7105C 001 Bluetooth LE SoC E2PROM 26 2 crystal oscillator 2 4GHz PCB pattern antenna and passive components It has Bluetooth LE compliant 2 4GHz band radio communication capability MK71050 03 is suitable for applications such as Healthcare device Remote Controller or PC peripherals M Features Bluetooth SIG Core Spec v4 0 compliant e Radio certification MIC JAPAN certification no 006 000238 FCC FCC ID 2ACIJ71050 3 CE R amp TTE e Bluetooth Qualification End Product QDID 66491 Integrating ML7105C 001 Bluetooth LE single mode LSI e Integrating 26MHz xtal oscillator e Integrating 128kbit EEPROM e Single power supply 1 8V to 3 6V e Operating Temperature 20 deg C to 70 deg C e Current Consumptions Deep Sleep Mode 0 8uA Typ with external Low Power Clock Idle Mode 3mA Typ TX mode 9mA Typ RX mode 9mA Typ Dimension 10 7mm VV x 13 6mm L x 1 78mm Pb Free RoHS compliant Product Name MK71050 03 ROHM SEMICONDUCTOR MK71050 03 FEDK71050 03 01 LAPIS Semiconductor Co Ltd E Schematics C15 1 GND 1 s 1 SDA UART_RXD UART_TXD 5 SPIXCS SPIDOUT SPIDIN VDDBAT dna
13. _ANT Output from Antenna to be connected to OUT_MOD by user s PCB OUT_MOD Output from Module to be connected to OUT_ANT by user s PCB GND GND VDDCORE Internally generated power supply VDDBAT Power supply 1 8 to 3 6V require 10uF capacitor LPCLKBUS Please use this pin open LPCLKIN Low Power clock input REGC REGOUT require 10uF capacitor EFUSE Control signal for EFUSE programming fix to GND for normal usage SPIDIN Data input for SPI slave SPIDOUT SPIXCS Data output for SPI slave Chip select for SPI slave SPICLK Clock input for SPI slave GND GND UART_TXD Data TX port for UART UART_RXD Data RX port for UART GND GND SDA SDA data port for 12C SCL SCL clock port for 12C GPIOO RF_ACTIVE GPIO inout RF_Active GPIO1 WAKEUP GPIO inout WAKEUP GPIOZ IRQ GPIO inout IRQ GPIO3 PS_CONTR OL GPIO inout external switch control Q1 To be connected to FETGATE by user s PCB FETGATE Gate control Pin of internal FET To be connected to PS_CONTROL by user s PCB TMODE Test mode control fix to GND for normal usage RESETB Reset low active AO Analog Test Pin0 A1 Analog Test Pin1 NC No connection XRefer to PIN descriptions ANT_GND Antenna GND 5XRefer to PIN descriptions 4 23 FEDK71050 03 01 MK
14. bel is only for internal use and please do not use at customer site It might contain internal products information that is inconsistent with product information e Precaution for Disposition When disposing Products please dispose them properly with a industry waste company e Prohibition Regarding Intellectual Property LAPIS Semiconductor prohibits the purchaser of the Products to exercise or use the intellectual property rights industrial property rights or any other rights that either belong to or are controlled by LAPIS Semiconductor other than the right to use 22 23 FEDK71050 03 01 MK71050 03 sell or dispose of the Products e The other precautions 1 Please use the Products in accordance with any applicable environmental laws and regulations such as the RoHS Directive For more details including RoHS compatibility please contact a ROHM sales office LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non compliance with any applicable laws or regulations 2 When providing our Products and technologies contained in the Specification to other countries you must abide by the procedures and provisions stipulated in all applicable export laws and regulations including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act Copyright 2015 LAPIS Semiconductor Co Ltd LAPIS Semiconductor Co Ltd 2 4 8 Shinyokohama Kouhoku
15. cient consideration to external conditions must be made e Precaution for Electrostatic This product is Electrostatic sensitive product which may be damaged due to Electrostatic discharge Please take proper caution during manufacturing and storing so that voltage exceeding Product maximum rating won t be applied to the Products Please take special care under dry condition Grounding of human body equipment solder iron isolation from charged objects setting of Ionizer friction prevention and temperature humidity control etc e Precautions for Storage Transportation 1 Product performance and connector mating may deteriorate if the Products are stored in the following places a Where the Products are exposed to sea winds or corrosive gases including Cl H2S NH3 SO and NO b Where the temperature or humidity exceeds those recommended by LAPIS Semiconductor Temperature 5 C to 40 C Humidity 40 to 60 c Storage in direct sunshine or condensation d Storage in high Electrostatic 2 Even under LAPIS Semiconductor recommended storage condition connector mating mountability and heat resistance of products over 1 year old may be degraded 3 Store transport cartons in the correct direction which is indicated on a carton as a symbol otherwise bent leads may occur due to excessive stress applied when dropping of a carton e Precaution for Product Label QR code printed on LAPIS Semiconductor product la
16. nals Pin Name A Function at reset Level 25 eri Output Low B GPIO inout RF_ACTIVE output default RF ACTIVE IRF_ACTIVE P P GPIO inout VVAKEUP input default WAKEUP 5 Output High B o inout IRQ output default IRQ fee inout Control signal for external Switch default B Output Low 2 PS_CONTROL 5 m To be connected to FETGATE by user s PCB Pin Name mu I O OE Function at reset Level 31 RESETB Reset input Low Reset 14 E Fuse writing voltage supply Fixed to Low 30 TESTMODE input Fixed to Low RER FET gate control input E ib To be connected to PS CONTROL by users PCB Pin Name 0 I O Function at reset Level Internally generated power supply REGC 1 2V WH Pin for de coupling capacitor require 10uF capacitor Status Value VO Active Function at reset Level Power supply 1 8 to 3 6V require 10uF capacitor 6 23 FEDK71050 03 01 MK71050 03 ANT_GND signals Pin Name s valle at reset Level Antenna GND pins 1 3 4 ANT_GND pins has to be connected to board but not to 35 ANT_GND be connected any components on board 37 48 Note The pins are connected to GND in the module but please use this pins open NC signals Pin Name I O AANS Function at reset Level NC pins has to be connected to board but not to be 2 5 NC connected any components on board 34 36 AC Please use this pins o
17. oduct reliability and quality semiconductors can break down and malfunction due to various factors Therefore if product malfunctions may result in serious damage including that to human life sufficient fail safe measures must be taken including the following a Installation of protection circuits or other protective devices to improve system safety b Installation of redundant circuits in the case of single circuit failure 10 Failure induced under deviant condition from what defined in the Specification can not be guaranteed 11 This product is a specification to radiate the radio wave It is necessary to acquire the attestation of decided Radio Law of each region used to use the equipment that radiates the radio wave Please inquire about the attestation of Radio Law that this product acquires 12 When product safety related problems arises please immediately inform to LAPIS Semiconductor and consider technical counter measure e Precautions for Reference Circuits 1 If change is made to the constant of an external circuit allovv a sufficient margin due to variations of the characteristics of the Products and external components including transient characteristics as vvell as static characteristics 2 The reference circuit examples their constants and other types of information contained herein are applicable only when the Products are used in accordance with standard methods Therefore if mass production is intended suffi
18. pen Unused pins Followings are recommendation for unused pins 2 5 34 36 NC OPEN NC pins has to be connected to board but not to be connected any components on board 1 3 4 35 Open ANT_GND pins has to be connected to board but not to be ANT_GND 271 48 connected 6 0 components on board 11 LPCLKBUS oem Ea O o GPIO1 WAKEUP Fix to High or Low O a section for 27 2 o Opn ee m CONTROL To be connected to FETGATE by user s PCB um FETGATE To be connected to PS CONTROL by user s PCB Remarks If input pins are left open with High Impedance status significant current consumption might be observed All input pins have to be fixed high or low level to avoid such current consumption 7 23 FEDK71050 03 01 MK71050 03 M Electrical Characteristics 6 Absolute Maximum Rating Item Symbol Condition Rating Unit Power supply 1 VDDBAT 0 3 to 4 6 V Digital input voltage 2 VDIN 0 3 to VDD 0 3 Digital output voltage 3 VDO 20 to 70 deg C 0 3 to VDD 0 3 Analog HV IO voltage 4 VAH GND 0V 0 3 to VDD 0 3 V Digital IO load current 2 3 DO 10 to 10 mA Analog IO current 4 IA 2 to 2 mA Power Dissipation PD T B D W Storage temperature Tstg 40 to 85 deg C 1 VDDBATpin 2 IO pins with I IPD Bz symbol in pin definition 3
19. r 50 dBm RSSI detection range z Prssimin Lower 80 dBm 1 PER 30 8 is corresponding to BER 0 1 2 Condition Ta 25 C VDDHV 3 3V SPI interface Ta 20 70 C Item Symbol Condition Min Typ Max Unit SPICLK Clock Frequency FSCLK 16 384 32 768 500 kHz SPIXCS input setup time TCESU 1 Fsclk m ms SPIXCS input hold time TCEH 1 Fsclk ms SPICLK high pluse width TWCKH 250 m ns SPICLK lovv pluse vvidth TVVCKL 250 ns SPIDIN input setup time TDISU 7 5 ns 20pF SPIDIN input hold time TDIH 250 ns SPICLK output delay time TCKOD m 250 ns SPIDOUT output hold time TDOH m ns SPIXCS output enable delay time TCEEN 0 300 ns SPIXCS output disable delay time TCEDIS 150 ns 10 23 FEDK71050 03 01 MK71050 03 SPIXCS SPICLK TCESU SPIDIN MSB IN b BITS6 1 TCEEN SPIDOUT SPIDOUT becomes Hi Z input when SPIXCS is High So please insert the pull up or pull down resister UART interface 20 to 70 deg C Item Symbol Condition Min Typ Max Unit Load capacitance Baud Rate FBAUD CL 20pF 57600 bps Hz FBAUD Data Bit 1 Data Bit 7 Data Bit 8 Serial Data One Character 11 23 FEDK71050 03 01 MK71050 03 Reset operation Ta 20 to 70 deg C Item Symbol Condition Min Typ Max Unit RESETB propagation delay time TRDL Start supplying power VDDBAT 20 m ms Povver on Reset pulse vvidth TRPLS RESETB pin 1 us
20. ronment can deteriorate product performance Accordingly verification and confirmation of product performance prior to use is recommended if used under the following conditions a Use in various types of liquid including water oils chemicals and organic solvents b Use outdoors where the Products are exposed to direct sunlight or in dusty places c Use in places where the Products are exposed to sea winds or corrosive gases including Ch H2S SO and NO d Use in places where the rPoducts are exposed to static electricity or electromagnetic waves e Use in environment subject to strong vibration and impact f Use in proximity to heat producing components plastic cords or other flammable items g Use involving sealing or coating the Products with resin or other coating materials h Use of the Products in places subject to dew condensation 5 The Products might receive the radio wave interference from electronic devices such as Wireless LAN devices Bluetooth devices digital cordless telephone microwave oven and so on that radiate electromagnetic wave 6 The Products are not radiation resistant 7 Verification and confirmation of performance characteristics of Products after on board mounting is advised 8 Confirm that operation temperature is within the specified range described in the Specification 21 23 FEDK71050 03 01 MK71050 03 9 Although LAPIS Semiconductor is continuously working to improve pr
21. uct to double sided printed board please do not implement this product for the first time reflow side Opposite side reflow is prohibited due to module weight Shield case may be discoloerd but there is no influence to the product performance and quality 19 23 M Revision History FEDK71050 03 01 MK71050 03 Page Document E No Date Previous Current Description Edition Edition FEDK71050 03 01 Apr 10 2015 m Final edition 1 20 23 FEDK71050 03 01 MK71050 03 Precautions for the Specification 1 Contents of the Specification are the information at the time of their issuance The information contained herein is subject to change without notice 2 LAPIS Semiconductor has used reasonable care in preparing the information included in the Specification but LAPIS Semiconductor does not warrant that such information is error free LAPIS Semiconductor assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products No license expressly or implied is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document therefore LAPIS Semiconductor shall have
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