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PMC520 User`s Manual

1. 2 3 eeW Se 8 25 8 8 8 8 83 19 8 8 5 8 8 8 8 8 5 18 8 8 68 55 8 N 0 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com 06 L6 LOST Sulvd G3LSIML PN OILIVA HOS oN 000000 L 2000000000090000000000000C 4 L2000000000000000000000000C ooooooooooboobooooooooood oooooooooodooPoooooooooocd n enn 030 13125 ATEWASSV 319199 Nid 89 ISOS 007 8005 1JIGON MAIA LNOYA LO OOOOOOOOOO OODOOOOOOCOOO_ 19 4 ooooooooooboobooooooooooc Boooooooooofocbooooooooooc PSoNoskSo8o8 5o8w9 a N a L 2000000000090000000000000C L 2000000000000000000000000C 4 5ooooocooooodoobooooooocoooc 20000c00coodocobooooooooooC ponn a pen K D SE Nid L Nid GE Nid LNd 20000000000900po0000000000C 2000000000000000000000000C E oooooooooodoobooooooooooC eee n 2000000000090000000000000C 2000000000000050000000000C oooooooooobooboooooooooo oooooooooo ooboooooooooo 0 n O000000000000000000000000000 080101 ooooooooooooooooooooDoDDDDODaDODO pea AD p 7 89 Nid Prnnnppnnnnnpnnnnnppnnnpnnnnnpnn YE Nid 89 Nd YE Nid o ooooooooooooobooooooooooc 20000000000d0
2. 21 LSR Line Status Register 22 MSR Modem Status Register 23 SCR Scratch Pad Register 24 FCTR Feature Control Register 24 EFR Enhanced Feature Register 25 TXCNT Transmit FIFO Level Counter 26 TXTRG Transmit FIFO Trigger Level 26 RXCNT Receive FIFO Level Counter 26 RXTRG Receive FIFO Trigger Level 27 XCHAR Register eene 27 XON XOFF 1 2 Registers 27 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD 3 Read RX FIFO Register 27 Write TX FIFO Register 27 TABLE OF Read RX FIFO with Errors Register 28 THE EFFECT OF RESET ene 28 CONTENTS PMC520 PROGRAMMING CONSIDERATIONS 29 FIFO Polled Mode 29 FIFO Interrupt Mode 29 Loopback Mode Operation 30 Software Flow Control 30 Hardware Flow Control 31 Programming Example 32 4 0 THEORY OF OPER
3. Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses This board operates in two different modes In one mode this device remains software compatible with the industry standard 16C550 family of UART s and provides double buffering of data registers In the FIFO Mode enabled via bit 0 of the FCR register data registers are FIFO buffered so that read and write operations can be performed while the UART is performing serial to parallel and parallel to serial conversions Two FIFO modes are possible FIFO Interrupt Mode and FIFO Polled Mode Some registers operate differently between the available modes and this is noted in the following paragraphs Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 4 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD DEVICE Note Only device configuration registers that are supported by the PMC520 CONFIGURATION are described in this section REGISTERS Global Interrupt Status Register READ Only This 32 bit wide register INTO INT1 INT2 and INT3 provides interrupt source and type information Each of the first 8 bits INTO represents a c
4. 02 occurs The interrupt is cleared when the Interrupt Status Register ISR is read The Transmit FIFO Level Counter TXCNT may be used to help determine the number of characters that can be written to the transmit FIFO when servicing this interrupt Loopback Mode Operation This device can be operated in a loopback mode useful for troubleshooting a serial channel without physically wiring to the channel Bit 4 of the Modem Control Register MCR is used to enable the local loopback feature for the UART channel All regular UART functions operate normally Transmit data from the transmit shift register output is internally routed to the receive shift register The TX RTS and DTR pins are held HIGH idle or de asserted and the CTS and DSR inputs are ignored The CTS and DSR input status bits MSR 5 4 reflect the states of the RTS and DTR bits MCR 1 0 respectively Software Flow Control Model PMC520 modules include support for software flow control Software flow control utilizes special XON and XOFF characters to control the flow of data for more efficient data transfer and to minimize overrun errors Software flow control sometimes called XON XOFF pacing sends a signal from one node to another by adding flow control characters to the data stream The receiving node will detect the XON or XOFF character and respond by suspending transmission of data XOFF turns the data flow off or resuming transmission of data
5. Software 00XX z No Transmit Flow Control Flow 10XX Transmit Xon1 Xoff1 Control 01XX Transmit Xon2 Xoff2 11XX Transmit Xon1 and Xon2 Xoff1 and Xoff2 XX00 No receive Flow Control XX10 Receiver Compares Xon1 Xoff1 XX01 Receiver Compares Xon2 Xoff2 1011 Transmit Xon1 Xoff1 Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 0111 Transmit Xon2 Xoff2 Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 1111 2 Transmit Xon1 and Xon2 Xoff1 and Xoff2 Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 0011 No transmit flow control Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 Enhanced 0 Disable and latch the enhanced Function functions the IER bits 4 7 ISR bits 4 5 Control FCR bits 4 5 MCR bits 5 7 default This feature prevents existing software from altering or overwriting the enhanced functions 1 Enables the enhanced functions Allows the IER bits 4 7 ISR bits 4 5 FCR bits 4 5 and MCR bits 5 7 to be modified Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 26 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD EFR Bit FUNCTION PROGRAMMING Disa p C E Enable special character detect Incoming receive characters are compared Control with Xoff 2 data If a match exists the receive data will be transferred to the FIFO and ISR bit 4 will be set to indicate detection of special character Bit 0 of the Xoff Xon rooster correspon
6. fetes ES 3 BST Header laeny Cache 4 debi Memory Base Address for 4KByle Block 5 10 NotUsed 1i SubsystemiD 0520 Subsystem VendorlD 16D5 12 NiUed Hs4 fResmwed o 15 Maia Men merPn Inter Line The memory space address map for the board is shown in Table 3 2 MEMORY MAP Note that the base address for the board in memory space must be added to the addresses shown to properly access the board registers Register accesses as 32 24 16 and 8 bit in memory space are permitted unless otherwise specified The memory space consists of two types of registers The first type is the Device Configuration Registers Table 3 3 These registers occupy 4K of memory space at Base Address 80H and are used for general device configuration and monitoring The second register type consists of each channel s UART configuration registers These are used to control and monitor the status of the individual channels Base Table 3 2 Memory Map UART Channel 0 READ RHR Bit 7 20 Channel 0 Receive Holding Register WRITE THR Channel 0 Transmit Holding Register READ WRITE DLL Channel 0 Divisor Latch Low READ WRITE DLM Channel 0 Divisor Latch High READ WRITE IER Channel 0 Interrupt Enable Register READ ISR Channel 0 Interrupt Status Register WRITE FCR Channel 0 FIFO Control Register READ WRITE LCR Channel 0 Line Cont
7. 50 feet 15M typical limited to a cable capacitive load of 2500pF Character Size Software Programmable 5 to 8 bits Parity Software Programmable odd even or no parity Stop Bits Software Programmable 1 1 1 2 or 2 bits Data Register Buffers The data registers are double buffered 16C450 mode or 64 byte FIFO buffered FIFO mode Interrupts Receiver Line Status Interrupt i e Overrun Parity or Framing error or Break Interrupt Received Transmit FIFO level reached or Character Time Out or Modem Status Xon Xoff Special Character Detect RS 232 Transmitter Outputs Output Voltage Swing 9 0V Minimum Loaded with 3KQ to ground Output Short Circuit Current 60mA Max 15mA Typical Output Resistance 300 Minimum Propagation Delay 1 5us Max R 3KQ C 2500pF Output Slew Rate 3 to 3V 3V us Min to 30V us Max C 2500pF R 3KO RS 232 Receiver Inputs Data Rate Up to 230 Kbps Input Voltage Range 30V DC Maximum Input High Threshold 2 4V Maximum Input Low Threshold 0 8V Typical Input Resistance 3KQ to 7KQ Propagation Delay H to L 14s Maximum Propagation Delay L to H 1us Maximum Note 1 Modules are tested to 230 4Kbps PCI Local Bus Interface PMC520 Compatibility Conforms to PCI Bus Specification Revision 2 3 and PMC Specification P1386 1 PCI Target Implemented by UART Exar XR17D158 4K Memory Space Required One Base Address Register PCI commands Supported Configuration
8. A pound sign is used to an active low signal 8 PMC520 User s Manual Front Panel Field I O Connector Table 2 1 Board Field VO Pin Connections The board has eight EIA TIA 232E serial communication channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD 0 On models with rear I O the J4 PMC connector provides the field I O Rear J4 Field I O interface connections This connector is a 64 pin female receptacle header Connector AMP 120527 1 or equivalent which mates to the male connector on the carrier CPU board AMP 120521 1 or equivalent All eight EIA TIA 232E serial communication channels for interfacing are shown in table 2 2 Each channel has six signals and are designated by channels 0 through channel 7 Table 2 2 Board Rear Field Pin Description I O Pin Connections TX0 RX0 The board has eight EIA TIA 232E serial communication channels A pound sign is used to indicate an active low signal The board is non isolated since there is electrical continuity between the Non lsolation logic and field I O grounds As such the field I O connections are not Considerations isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog inputs
9. CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PMC boards Acromag provides a software product sold separately consisting of BOARD QNX board QNX software This software Model PCISW API QNX is SOFTWARE composed of QNX real time operating system libraries for all Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PMC boards Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 7 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION re CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Configuration Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damag
10. DLM DLL 14 74MHz Clock Bit 7 1 Bit 7 0 pen HEX L m9 El ou 300 1200 768 600 2400 384 0 80 1200 4800 192 00 CO 9600 96 00 60 3600 14400 84 00 40 4800 19200 Co 30 28800 32 00 20 9600 38400 24 00 B 28 800 115 200 8 00 08 57600 230400 4 00 With respect to this device the baud rate may be considered equal to the number of bits transmitted per second bps The bit rate bps or baud rate defines the bit time This is the length of time a bit will be held on before the next bit is transmitted A receiver and transmitter must be communicating at the same bit rate or data will be garbled A receiver is alerted to an incoming character by the start bit which marks the beginning of the character It then times the incoming signal sampling each bit as near to the center of the bit time as possible IER Interrupt Enable Register Channels 0 7 R W The Interrupt Enable Register is used to independently enable disable the serial channel interrupt sources Each of the eight channels have seven unique interrupt sources which are all mapped to INTA of the PMC module An interrupt source is disabled by setting the corresponding IER bit to logic 0 and enabled by setting the IER bit to logic 1 Note that in order for channel interrupts to be seen by the system the multi purpose input output registers must be configured pr
11. Read Write memory Read Write 32 16 and 8 bit data transfer types supported Signaling Universal PCI Bus buffers Auto sense 3 3V or 5V operation Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 3 0 INTA Interrupt A is used to request an interrupt Source of interrupt can be from the Digital I O or Counter Timer Functions Access Times 8 PCI Clock Cycles for all register accesses Type Round shielded cable 34 twisted pairs SCSI 3 male connector at APPENDIX both ends The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision CABLE MODEL 5028 analog 1 0 432 SCSI 3 to Round Application Used to connect Model 5025 288 termination panel to the Shielded front panel of the Board Length Standard length is 2 meters 6 56 feet Consult factory for other lengths It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 68 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil braided shield inside a PVC jacket Connectors SCSI 3 68 pin male connector with backshell Keying The SCSI 3 connector has a D Shell Schematic and Physical Attributes See Drawing 4501 919 Electrical Specifications 30 VAC per UL and CSA SCSI 3 connector spec s 1 Amp maximum a
12. Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed at the bottom of this page When needed complete repair services are also available 3 6 PMC520 User s Manual 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP www acromag com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 3 6 0 SPECIFICATIONS PHYSICAL Connectors Table 6 1 Power Requirements 5V Maximum rise time of 100m seconds ENVIRONMENTAL CE MARK SPECIFICATIONS Reliability Prediction UART RS 232 Single PMC Board Height 13 5 mm 0 531 in Stacking Height 10 0 mm 0 394 in Depth 149 0 mm 5 866 in Width 74 0 mm 2 913 in Board Thickness 1 59 mm 0 062 in PCI Local Bus Interface Two 64 pin female receptacle header AMP 120527 1 or equivalent Universally keyed for 3 3V or 5V signaling Front Field I O 68 pin SCSI 3 female receptacle header AMP 787082 7 or equivalent for all front I O models Rear Field I O 64 pin female receptacle header AMP 120527 1 or equival
13. The most common asynchronous serial data format is 1 start bit 8 data bits and 1 stop bit with no parity The following table summarizes the available data formats START BIT Binary 0 a shift from Mark to Space 5 6 7 or 8 Bits ee DATA BITS 5 6 7 or 8 Bits PARITY Odd Even Stick or None STOP BIT Binary 1 1 1 1 2 or 2 Bit times With start stop and parity in mind for an asynchronous data byte note that at least one bit will be a 1 the stop bit This defines the break signal all 0 bits with a 1 stop bit lasting longer than one character A break signal is a transfer from mark to space that lasts longer than the time it takes to transfer one character Because the break signal doesn t contain any logical 1 s it cannot be mistaken for data Typically whenever a break signal is detected the receiver will interpret whatever follows as a command rather than data The break signal is used whenever normal signal processing must be interrupted In the case of a modem it will usually precede a modem control command Do not confuse the break signal with the ASCII Null character since a break signal is longer than one character time That is itis any space condition on the line that lasts longer than a single character including its framing bits and is usually 1 1 2 to 2 character times long The baud rate is a unit of transmission speed equal to the number of electrical signals signal level
14. and outputs when a high level of accuracy resolution is needed Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email salesQacromag com htip www acromag com 1 0 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD 3 0 PROGRAMMING This Section provides the specific information necessary to program and INFORMATION operate the board This board is a PCI Specification version 2 3 compliant PCI bus target only board The PCI bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCI bus memory space and configuration spaces only The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCI card As a Plug and Play card the board s base address and system interrupt request line are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCI bus configuration access is used to read write the PCI card s configuration registers PCI Configuration When the computer is first powered up the computer s system Address Space configuration software scans the PCI bus to determine what PCI devices are present The software also determines the configuration requirements of the PCI card The system software accesses the configuration registers to determine how many blocks of memory space the carrier requires It then programs the board s c
15. default 1 Enable Interrupt The UART issues an interrupt when the RTS DTR pin makes a transition The RTS or DTR output is selected via MCR bit 2 CTS DSR Input Interrupt Enable requires EFR bit 4 1 0 Disable Interrupt default 1 Enable Interrupt The UART issues an interrupt when the CTS DSR pin makes a transition The CTS or DSR input is selected via MCR bit 2 A pound sign is used to indicate an active low signal on the UART pin Note however that the handshake signals RTS CTS DTR and DSR are inverted prior to the field I O interface ISR Interrupt Status Register Channels 0 7 READ Only The Interrupt Status Register is used to indicate that a prioritized interrupt is pending and the type of interrupt that is pending The eight individual channels share the PMC module INTA signal Six levels of prioritized interrupts are provided to minimize software interaction Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced No other interrupts are acknowledged until the pending interrupt is serviced Whenever the interrupt status register is read the interrupt status is cleared Note only the current pending interrupt is cleared by the read A lower level interrupt may be seen after re reading the interrupt status bits Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 8 PMC520 User s Manu
16. is active 0 No transmit FIFO reset default 1 Reset the transmit FIFO pointers and FIFO level counter logic the transmit shift register is not cleared or altered This bit will return to logic 0 after resetting the FIFO DMA Mode Select DMA Not Supported Transmit FIFO Trigger Select These bits are used to set the trigger level for the transmit FIFO interrupt An interrupt will be issued when the number of characters in the FIFO drops below the selected trigger level or when the FIFO becomes empty in the case that it did not get filled over the trigger level on last reload FCTR bits 6 7 are used to select one of four trigger tables 1 default Programmable AN aa en Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD FCR BIT FUNCTION 7 6 Receive FIFO Trigger Select These bits are used to set the trigger level for the receiver FIFO interrupt In FIFO mode an interrupt is generated when the number of characters in the FIFO equals the programmed trigger level FCTR bits 6 7 are used to select one of four trigger tables eee A 0 0 1 Notes FIFO Control Register 1 Bits 4 and 5 are only programmable when the EFR bit 4 is set to 1 2 The receiver and transmitter cannot use different trigger tables The table selected last applies to both the RX and TX side LCR Line C
17. paths of each channel include generous 64 byte FIFO buffers to minimize CPU interaction Character size stop bits parity and baud rate are software configurable Prioritized interrupt generation is also supported for transmit receive line status and data set conditions The PMC520 utilizes state of the art Surface Mounted Technology SMT to achieve its wide functionality and is an ideal choice for a wide range of industrial communication interface applications that require a highly reliable high performance interface at a low cost Table 1 1 The PMC520 boards are available in Board FORT Description Temperature Factor standard and extended Range temperature ranges PMC520 kann MON ee 0 C to 70 C Operating PCI Mezzanine Eight EIA TIA 232E a RMGS20R kel ET PCI Mezzanine Eight EIA TIA 232E 5 PCI Mezzanine Eight EIA TIA 232E 5 a PMC520RE FC Mezzanine 40 C to 85 C KEY PMC520 High density Provides programmable control of eight EIA TIA 232E FEATURES serial channels e 64 Character FIFO Buffers Both the transmit and receive channels of each serial port provide 64 byte data buffering to reduce CPU interactions and interrupts This allows the external processor to handle more tasks within a given time e Programmable Character Size Each serial port is software programmable for 5 6 7 or 8 bit character sizes e Programmable Stop Bits Each serial port allows 1 1 1 2 or 2 stop bits t
18. register stores the low order byte of the divisor and DLM stores the high order byte These registers default to random values during upon power up and must be loaded during initialization Note that bit 7 of the LCR register must first be set high to access the divisor latch registers DLL and DLM during a read write operation The relationship between the baud rate prescaler divisor and the 14 7456MHz clock can be summarized in the following equations Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 6 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD Divisor eal ee ce Baud Ratex Prescaler With 8XMODE 0 ion 14 7456MH Divisor m Baud Ratex Prescaler With 8XMODE 1 The Prescaler term represents the state of MCR bit 7 as follows Prescaler 1 IfMCR bit 7 0 Prescaler 4 If MCR bit 7 1 The following table shows the correct divisor to use for generation of some standard baud rates based on the 14 7456MHz clock at 16X clock rate Note that baud rates up to 921 6K may be configured but the EIA TIA 232E drivers of this module limits data rates to 230Kbps maximum for performance within rated specifications A different external crystal can replace the 14 7456MHz crystal on the circuit board to obtain unique clock rates You may contact Acromag Applications Engineering to explore options in this area Table 3 4 Baud Rate Divisors BAUD RATE DIVISOR N IH MCR MCR
19. 00b0000000000C oooooooooodoobooooooooooC 20000000000900p0000000000C 20000000000000b0000000000CC 5oocooooooodoobooooocoocoooc 20000ccoocooqocopoooocoooooc 2000000000090000000000000C Bo eO mate E ld E Lo Ti3HS 0v8 03033105 Zd Ld OL SLOINNOO 31890 NO 073105 ANNOYD MAIA 01 Id SIHONI 00 O b SIHONI 22 82 ed x SYLIN z 9 2 0 2 8 5 18 6 3 8 9 8 8 9 5 8 8 8 6 8 5 8 8 8 8 5 8 NOTES EIA TIA 232E SERIAL COMMUNICATION BOARD 4 2 PMC520 User s Manual Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com MIIA 1NOH A HHLUUUUPDPHHHHHHHHHHHHHHHHHHHHHHHHHIF Seo an LZ SONDE VIN a W 89 79 99 S9 9 9 Z9 9 09 66 BS ZG 96 GG HG EG CS IS OS 67 8v 9v Sv Vv amp CV IT ILILILILILILILILILILILILILUI I ILILILILILILIT ve EE ZE LE VE 62 82 Ze 92 Sc ve ec 22 IZ OZ 6L 8L OL SL v
20. 10 Fax 248 624 9234 Email sales acromag com http www acromag com bits 1 4 Line Status Register LSR Bit FUNCTION PROGRAMMING Receive Data Ready Indicator Receiver Overrun Flag Receive Data Parity Error Flag Receive Data Framing Error Tag Receive Break Tag PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 23 Transmit This bit is the Transmit Holding Register Holding Empty indicator This bit indicates that the Register transmitter is ready to accept a new character Empty for transmission In addition this bit causes Flag the UART to issue an interrupt to the host when the THR interrupt enable is set The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host In FIFO mode this bit is set when the transmit FIFO is empty it is cleared when at least 1 byte is written to the transmit FIFO Transmit This bit is the Transmit Shift Register Empty Shift indicator This bit is set to a logic 1 whenever Register the transmitter goes idle It is set to logic 0 Empty Flag whenever the THR or TSR contains the data character In FIFO mode this bit is set to 1 whenever the transmit FIFO and transmit shift register are both empty Receiver 0 No FIFO error default FIFO Data 1 An indicator for the sum of all error
21. 100 131 100 131 180 1FF Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 1 3 D07 Comments Add MEMORY MAP WRITE Data Width Channel 1 Write FIFO 8 16 24 32 300 33F Reserved 340 37F READ Data Width Channel 1 Read FIFO with errors 16 32 380 3FF UART Channel 2 400 5FF UART Channel 3 600 7FF UART Channel 4 800 9FF UART Channel 5 A00 BFF UART Channel 6 C00 DFF UART Channel 7 E00 FFF Notes Table 3 2 1 To save user manual space the registers corresponding to channels 1 to 7 have not been individually shown The registers of channels 1 to 7 are in the address space shown above To access a register in channel 7 for example the offset of E00 hex is added to the address of the corresponding register given in table 3 2 All channels require a 512 byte memory block Byte 3 Byte 2 Byte 1 Byte 0 Base Table 3 3 Device Configuration REGISTER 31 24 23 16 15 8 7 0 8001 Registers shown in DWORD Global alignment Interrupt Status INT3 INT2 INT1 INTO 80 83 Read only Timer TIMER TIMER TIMER TIMER 94 97 Read Write MSB LSB reserved CNTL Ancillary1 REGA Read Write SLEEP RESET 8XMODE 88 8B Ancillary2 Read only MPIOINT REGB DVID DREV 8C 8F MPIO Read Write MPIOSEL MPIOINV MPIO3T MPIOLVL 90 93 This memory map reflects byte accesses using the
22. ARATION FOR USE uel naga UNPACKING AND INSPECTION 7 seer ee A ON r CARD CAGE CONSIDERATIONS 7 oo Wel May appear BOARD CONFIGURATION 7 this manual and makes no Default Configuration ee 7 commitment to update or Front Panel l O 8 KOAP a Rear J4 Field VO Connector 9 CORTIRED tis MANUAL NO Non Isolation Considerations 9 part of this manual may be copied or reproduced in any form without the prior written 3 0 PROGRAMMING INFORMATION consent of Acromag Inc PCI CONFIGURATION ADDRESS SPACE ERE 10 PCI CONFIGURATION REGISTERS 10 11 MEMORY MAP Global Interrupt Status Register 14 1 01010101013132131 1 1 14 RESE pg 1 1110101 14 Global Interrupt Enable 14 RHR Receive Holding Register 15 THR Receive Holding Register 15 DLL and DLM Divisor Latch Registers 15 IER Interrupt Enable Register 16 ISR Interrupt Status Register 17 FCR FIFO Control Register 19 LCR Line Control Register 20 MCR Modem Control Register
23. ATION EIA TIA 232E SERIAL INTERFACE 33 PMC520 OPERATION eren 35 LOGIC POWER INTERFACE e 35 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE 36 PRELIMINARY SERVICE PROCEDURE 36 WHERE TO GET HELP isk isit saa 36 6 0 SPECIFICATIONS PHYSICAL oiana 37 ENVIRONMENTAL 0 37 UART ente E 37 85 232 CHANNELS 0 38 85 232 TRANSMITTER OUTPUTS 38 RS 232 RECEIVER INPUTS senes 38 PCI LOCAL BUS INTERFACE enne 38 APPENDIX CABLE MODEL 5028 432 0 39 TERMINATION PANEL MODEL 5033 646 39 DRAWINGS 4502 022 PMC520 BLOCK DIAGRAM 40 4502 023 PMC520 RS232 DIAGRAM 41 4501 919 CABLE 5028 432 SHIELDED 42 4501 920 TERMINATION PANEL 5025 288 43 Trademarks are the property of their respective owners RELATED PUBLICATIONS The following datasheet provides additional information for in depth understanding of the PMC520 XR17D158 Datasheet http www exar com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com 4 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD 1 0 GENERAL The PMC520 board provides eight EIA TIA 232E serial communication INFORMATION channels from a single PMC socket The transmit and receive
24. Acromag l Series PMC520 Octal EIA TIA 232E Communication Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2004 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 755 B12D024 2 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY 520 FEATURES Lica nana nnn 4 may change without notice PCI INTERFACE FEATURES 5 Acromag makes no warranty SIGNAL INTERFACE PRODUCTS 5 of any kind with regard to this Board DLL Control Software 6 material including but not Board VXWORKS Software ss 6 limited to the implied Board QNX Software nnn 6 warranties of merchantability and fitness for a particular 2 0 PREP
25. DLL DLM Enable A detailed discussion of word length stop bits parity and the break signal is included in Section 4 0 Theory of Operation MCR Modem Control Register Channels 0 7 R W The Modem Control register is used for controlling the modem interface signals or general purpose inputs outputs Modem Control Register MCR Bit FUNCTION PROGRAMMING DTR Pins 0 Force DTR output HIGH default 1 Force DTR output LOW The DTR pin may be used for automatic hardware flow control if enabled by EFR bit 6 and MCR bit 2 1 If the modem interface is not used this output may be used for general RTS Pins 0 Force RTS output HIGH default 1 Force RTS output LOW The RTS pin may be used for automatic hardware flow control if enabled by EFR bit 6 and MCR bit 2 0 If the modem interface is not used this output may be used for general purpose DTR or RTS 0 Uses RTS and CTS pins for auto for Auto Flow hardware flow control Control 1 Uses DTR and DSR pins for auto hardware flow control This bit is only in effect when auto RTS DTR i is enabled by EFR bit 6 a OP2 Internal 0 Disabled internal loopback mode Loopback default Enable 1 Enabled internal loopback mode Xon Any 0 Disable Xon Any function default Enable 1 Enable any Xon any function In this mode any RX character received will enable Xon resume data transmission Infrared Infrared mode is not supported Encoder Deco
26. FO Data FIFO Data n 7 n 7 n 6 n 5 n 4 Etc Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 28 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD READ RX FIFO with Errors Channel 0 7 Read Only This register provides a faster alternative to reading data in 8 bit format from the receive holding register RHR and line status register LSR Using this register RX FIFO data and LSR status information is read out side by side The status and data bytes must be read in 16 or 32 bits format to maintain data integrity The status and data is formatted as follows READ RX FIFO with Byte 3 Byte 2 Byte 1 Byte 0 LSR Errors Read n 0 to FIFO Data LSR n 1 FIFO Data LSR n 0 n 1 n 1 n 0 Read n 2 to FIFO Data LSR n 3 FIFO Data LSR n 2 n 3 n 3 n 2 Etc THE EFFECT OF RESET The following table summarizes the effect of a reset on the various registers and internal and external signals UART Reset Conditions LSR Bits 7 6 3 0 logic 0 Bits 5 4 logic levels of the inputs SPR FCTR EFR TXCNT TXTRG RXTRG XCHAR XON1 XON2 XOFF1 E Dn E D oO o9 AT RXCNT Bits 7 0 0x00 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 2 0 PMC520 PROGRAMMING CONSIDERATIONS Each serial channel of this module is program
27. FO Register Transmission of serial data will take place on the TXO line If the receiving side cannot keep up with the data stream 0150 will be released and Auto CTS Flow Control will suspend transmission Transmission will automatically resume when CTSOH is reasserted 10 When there is no more data to transmit write OOH to the Interrupt Enable Register IER This prevents further TXRDY interrupts 4 0 THEORY OF OPERATION This section contains information regarding the EIA TIA 232E serial data interface A description of the basic functionality of the circuitry used on the board is also provided Refer to the Block Diagram shown in Drawing 4502 022 as you review this material RS232 SERIAL INTERFACE The Electronic Industries Association EIA first introduced the RS 232 standard in 1962 to standardize the serial binary data interface between Data Terminal Equipment DTE and Data Communication Equipment DCE By this definition DTE is used to represent the data source data sink or both DCE is used to represent the devices used to establish maintain and terminate a connection and to code decode the signals between the DTE and the transmission channel Most computers are considered DTE devices while modems are DCE devices The EIA TIA 232E interface is the fifth revision of this standard and defines an unbalanced single ended transmission standard for unidirectional point to point one direction at a time data transmiss
28. IFO Polled Mode In FIFO Interrupt Mode data transfer is initiated by reaching a pre determined trigger level or generating time out conditions In FIFO Polled Mode there is no time out condition indicated or trigger level reached The transmit and the receive FIFO s simply hold characters and the Line Status Register must be read to determine the channel status FIFO Polled Mode Resetting all Interrupt Enable Register IER bits to 0 with FIFO Control Register FCR Bit 0 1 puts the channel into the polled mode of operation The receiver and transmitter are controlled separately and either one or both may be in the polled mode In FIFO Polled Mode there is no time out condition indicated or trigger level reached the transmit and the receive FIFO s simply hold characters and the Line Status Register must be read to determine the channel status FIFO Interrupt Mode In FIFO Interrupt Mode data transfer is initiated by reaching a pre determined trigger level or generating a time out condition Please note the following with respect to this mode of operation When the receiver FIFO and receiver interrupts are enabled the following receiver status conditions apply 1 LSR Bit 0 is set to 1 when a character is transferred from the shift register to the receiver FIFO It is reset to 0 when the FIFO is empty 2 The receiver line status interrupt ISR 06 has a higher priority than the received data available interrupt ISR 04 3 T
29. L EL ZE LL OL 6 8 2 9 S v 2 Y SH3L3IAFTIIIAD SHON NISHVSNOISNAIVO MIIA dOL MIIA QIS TM A NN J HHzH TH8v1 bal 22 lt TVIYIS 3AqOWN 39V ld pA 92 98 e Ot e p A es T Y L Nid LE 8 7 zt A S o aA DAB H ma AAE a aE na AA ERLE H B AREA o Ir 5 wa at Y LOL6 879 Z QL 8LZ1 9L SL v OILIVA HOS TANVd NOILVNIWd LT 880 9005 1 dOW 8979 99 S9 79 9 Z9 19 09 6S 8G LG 9G SG HG EG CS LS OS Gr 8p Li 97 Sv vv Eb cy Lv Ov GE BE LE 9 SE YE EE ZE LE OF 66 82 Le 96 Sc vo EE 26 IZ 06 6 99 49 99 S9 v9 9 Z9 19 09 65 9S LG 9G SG HG EG ZE LS OS 67 87 ZP 97 97 vy Eb cV Lv Ov GE BE LE 9 GE YE EE ZE IE OF 66 86 72 9c Sc vc EZ GE lC 06 6L SIAL AP SL EL CL IL OLG 8729 S 7 Ir 00 6 LOST EIATIA 232E SERIAL COMMUNICATION BOARD 4 3 PMC520 User s Manual
30. Software Flow Control One or two sequential receive data characters are compared to a programmed Xon or Xoff character value Data transmission can be suspended or resumed via software flow control e Hardware RTS CTS or DTR DSR Flow Control The CTS DSR signal is monitored for remote buffer overflow indication and will suspend transmissions if it becomes active The RTS DTR signal is used to request the remote unit to suspend restart transmission to prevent overflow of the local FIFO e High density Single width PMC Target module PCI INTERFACE FEATURES e Field Connections All eight EIA TIA 232E serial channels connections are made through a single 68 pin SCSI 3 front panel I O connector Models PMC520R and PMC520RE only use 4 64 pin rear I O connector e 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCI memory space All registers can be accessed via 32 16 or 8 bit data transfers e Compatibility Complies to PCI Local Bus Specification Revision 2 3 Provides one multifunction interrupt Universal PCI Bus buffers Auto sense 3 3V or 5V operation Cables and a termination panel are also available to interface with this SIGNAL INTERFACE board via the 68 pin SCSI front panel connector PRODUCTS Cable Model 5028 432 A 2 meter round 68 conductor shielded cable with a male SCSI 3 connector at both ends and 34 twisted pairs The cable is used for connecting the boar
31. XON turns the data flow on Flow control is used frequently in data communications to prevent overrun errors or the loss of excess data For example a node might transmit the XOFF character to the host computer if the host is sending data too quickly to be processed or buffered thus preventing the loss of excess data The flow control characters are stored in the XON1 XON2 XOFF1 and XOFF2 registers Two XON and XOFF registers are provided because the flow control character may be 1 or 2 bytes long The contents of the XON and XOFF registers are reset to O upon power up or system reset and may be programmed to any value for software flow control Different conditions may be set to detect the XON XOFF characters or start stop the transmission When software flow control is enabled the UART of this model will compare single or dual consectutive received data bytes with Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 3 1 preprogrammed XOFF1 XOFF2 characters When an XOFF match is detected the UART will halt transmission after completing the transmission of the current character The Xoff Interrupt Status flag of the Interrupt Status register will be set ISR bit 4 is set to 1 when the XOFF character has been detected only if enabled via bit 5 of the Interrupt Enable register IER bit 5 is used to enable the received XOFF in
32. able D is selected these Flow Control bits select the auio RTS DTR flow control Hysteresis hysteresis The RTS DTR hysteresis is Select referenced to the RX FIFO trigger level 3 H R Hysteresis 0000 0 Auto RS485 EE SIEL nirarea Select Not supported Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 25 FUNCTION PROGRAMMING TX and RX 00 Table A FIFO Trigger 01 Table B Table Select 10 Table C 11 Table D When table A B or C is selected the auto RTS flow control trigger is set to next FIFO trigger level for compatibility to ST16C550 and ST16C650 series RTS DTRi triggers on the next level of the RX FIFO trigger level one FIFO level above and one FIFO level below For example if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes RTS DTR output will de assert at 60 and re assert when the level drops below 16 EFR Enhanced Feature Register Channels 0 7 Read Write The Enhanced Feature register is used to enable or disable the enhanced features software flow control and hardware flow control This register is also used to unlock access to programming the extended register functionality of IER bits 4 7 ISR bits 4 5 FCR bits 4 5 and MCR bits 5 7 Enhanced Feature Register EER Bit FUNCTION PROGRAMMING
33. ail sales acromag com http www acromag com 230138 ALNI FZEZ VIL VI3 00252502 PJ01d INVHOVIG 2018 02SOWd NONWAOO 1VNSIS 3HV v9 8 9 SNid Oruvau vr NONWOD 1VNOIS dV 89 9 Z9 v SNid Ol LNOSH La NOAWOO TWNOIS ON TANNVHO SYAANAOSNVYL FZEZ VIL VIF A 3092311001 21901 IOd HLIM Sd ldvn WLOO 9GLd LJX dO1YTIIOSO ZHN 9Sv vi FIVIYILNI SAB 19d 7000 17 AA SYOLOANNOO OWd EIA TIA 232E SERIAL COMMUNICATION BOARD 40 PMC520 User s Manual Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 9620 7 INVHOVICO 20193231101 252 OCSOINd L L LA Jal MeV J a 0 dup TLL TLL SL FOVAYALNI JHL LV JOVLIOA JALLVDIN V A8 q IN S dd H SI MYYN L 91907 v 31IHM DVLTOA 3AILISOd V Ad Q31N3S3Hd3H SI OVdS 0 91907 V ZEZ SU HOA LVHL ALON 5 8 T1JAJ7171VNDQIS JHL NIWd 1 OL NOWWOD OL LO3dS3H HLIM N3MVLL SI INIT VNDIS INO HO SDVLIOA 31 8 CYVGNVLS NOISSINSNVYL I30N3 315NIS AJONVIVANN NV 0328301581605 SI ZEZ SY 5 axd aNas OL YY19 SLO ANY ANES OL AQvau SLY dH V SINIT SMVHSGNVH 3HL AXL ANY QXU aav SANIT viva ZEZ SY a SALON STANNVHO ALG OML ONILO NNOO EIATIA 232E SERIAL COMMUNICATION BOARD 4 1 PMC520 User s Manual 08 5 8 9
34. al EIA TIA 232E SERIAL COMMUNICATION BOARD The following interrupt source table shows the data values bit 0 5 for the seven prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels Interrupt Status Register LEVEL Bit5 to 0 LSR Receiver Line Status Register see LSR bits 1 4 000100 RXRDY Received Data Read 001100 RXRDY Receive Data Time out 4 000010 TXRDY Transmitter Holding Register Empt 5 000000 MSR Modem Status Register NE E 010000 RXRDY Received Xon Xoff or Special Dee 7 100000 CTS DSR RTS DTR change of state 000001 None default Notes Interrupt Status Register 1 Bit 4 of the EFR Enhanced Feature Register must be set to a logic 1 to unlock access to bits 4 and 5 of the ISR register Note that ISR bit 0 can be used to indicate whether an interrupt is pending bit 0 is low when interrupt is pending ISR bits 1 2 and 3 are used to indicate the source for a pending interrupt at interrupt priority levels 1 2 3 and 4 Bit 4 set indicates a Xoff Xon or special character detected interrupt pending Reading the XCHAR register will indicate which character Xoff or Xon was received last Bit 5 indicates a pending interrupt due to a change of state on the CTS DSR or RTS DTR signals Bits 6 and 7 are set to a logic 0 when the FIFOs are disabled They are set to a logic 1 when the FIFOs are enabled interrupt Clearing LSR interrupt is cleared by a
35. at a complete byte has been received Thus 10 bits make up a data byte if the data character is 8 bits long and no parity is assumed Nine bits are required if only standard ASCII data is being transmitted 1 start bit 7 data bits 1 stop bit The character size for this module is programmable between 5 and 8 bits Parity is a method of judging the integrity of the data Odd even or no parity may be configured for this module If parity is selected then the parity bit precedes transmission of the stop bit The parity bit is a 0 or 1 bit appended to the data to make the total number of 1 bits in a byte even or odd Parity is not normally used with 8 bit data Even parity specifies that an even number of logical 1 s be transmitted Thus if the data byte has an odd number of 1 s then the parity bit is set to 1 to make the parity of the entire character even Likewise if the transmitted data has an even number of 1 s then the parity bit is set to 0 to maintain even parity Odd parity works the same way using an odd number of logical 1 s Thus both the DTE amp DCE must have the same parity If a byte is received that has the wrong parity an error is assumed and the sending system is typically requested to retransmit the byte Two other parity formats supported by this module are mark and space parity Mark parity specifies that the parity bit will always be a logical 1 space parity requires that the parity bit will always be 0
36. bits in Error Flag the RX FIFO At least one parity error framing error or break indication is in the FIFO data This bit clears when there is no more error s in the FIFO MSR Modem Status Register Channels 0 7 Read Only The Modem Status Register MSR provides the host CPU with an indication on the status of the modem input lines from a modem or other peripheral device This register allows the current state of CTS and DSR to be read and provides indication of whether the state of these lines has changed since the last read of the MSR Modem Status Register MSR Bit FUNCTION PROGRAMMING Delt p Input Flag E B The CTS input has state since the last time it was monitored A modem status interrupt will be generated if MSR interru pt E enabled IER bit 3 Delta DSR ange on Inp ult Input Flag The DSR input has changed state since the last time it was monitored A modem status interrupt will be generated if MSR interrupt is enabled IER bit 3 2 Delta RI ARI Not Supported MENN EE Hag Delta ACD Not Supported Input Fag pin may function as automatic hardware Status flow control signal input if it is enabled an selected by Auto CTS EFR bit 7 and RTS CTS flow control select MCR bit 2 Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS signal A logic 1 on the CTS pin will stop UART transmitter as soon as the current character has finis
37. changes sent on a line in one second It is thus the electrical signaling rate or frequency at which electrical impulses are transmitted on a communication line The baud rate is commonly confused with the bit transfer rate bits per second but baud rate does not equate to the number of bits transmitted per second unless one bit is sent per electrical signal However one electrical signal change in signal level may contain more than one bit as is the case with most phone modems While bits per second bps refers to the actual number of bits transmitted in one second the baud rate refers to the number of signal level changes that may occur in one second Thus 2400 baud does not equal 2400 bits per second unless 1 bit is sent per electrical signal Likewise a 1200bps or 2400bps modem operates at a signaling rate of only 600 baud since they encode 2 and 4 bits respectively in one electrical impulse through amplitude phase and frequency modulation techniques However for this device the baud rate is considered equivalent to the bit rate Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD 3 5 PMC520 OPERATION Connection to each serial channel is provided through connector P1 or J4 refer to Table 2 1 or 2 2 These pins are tied to the inputs and outputs of EIA TIA 232E line receivers and drivers The function of the line r
38. d to Model 5025 288 termination panels See the Appendix for For optimum performance use the shortest possible length of shielded further information on Inputeabie these products Termination Panel Model 5025 288 DIN rail mountable panel provides 68 screw terminals for universal field I O termination Connects to Acromag board via SCSI 3 to twisted pair cable described above Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 6 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD BOARD DLL CONTROL Acromag provides a software product sold separately to facilitate the SOFTWARE development of Windows 98 Me 2000 XP applications accessing Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a software product sold separately consisting of BOARD VxWORKS board VxWorks software This software Model PMCSW API VXW is SOFTWARE composed of VxWorksQ real time operating system libraries for all Acromag PMC MO board products PCI I O Cards and
39. der Enable Clock Prescaler 0 Divide by one The input clock from Select the crystal is fed directly to the Programmable Baud Rate Generator without further modifications i e divide by one default 1 Divide by four The prescaler divides the input clock from the crystal by four and feeds it to the Programmable Baud Rate Generator hence data rates become one forth Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com EIA TIA 232E SERIAL COMMUNICATION BOARD 2 2 PMC520 User s Manual Notes Modem Control Register 1 MCR Bit 4 provides a local loopback feature for diagnostic testing of the UART channel All UART functions operate normally Transmit data from the transmit shift register is internally routed to the receive shift register input allowing the system to receive the same data that it was sending The TX RTS and DTR pins are held de asserted and the CTS and DSR inputs are ignored 2 Bits 5 7 are only programmable when the EFR bit 4 is set to 1 The programmed values for these bits are latched when EFR bit 4 is cleared preventing existing software from inadvertently overwriting the extended functions LSR Line Status Register Channels 0 7 Read Write Restricted The Line Status Register LSR provides the status of data transfers between the UART and the host If IER bit 2 is set to a logic 1 an LSR interrupt will be generated immediately when any c
40. detected This bit is automatically Indicator cleared after being read 1 Xon ot d Detected n detected This bit is automatically Indicator p after being read 72 jNotused Pd XON XOFF 1 2 Registers Channel 0 7 R W These registers hold the programmed Xon and Xoff characters for software flow control Xon or Xoff characters may be 1 or 2 bytes long The UART compares incoming data to these values and restarts Xon or suspends Xoff data transmission when a match is detected READ RX FIFO Channel 0 7 Read Only This register provides a faster alternative to reading data in 8 bit format from the receive holding register RHR Using this register RX FIFO data can be read out using 32 bit read operations maximum 16 DWORD reads The data is formatted as follows READ RX FIFO Byte 3 Byte 2 Byte 1 Byte 0 Read n 0 to FIFO Data FIFO Data FIFO Data FIFO Data n 3 n 3 n 2 n 1 n 0 Read n 4 to FIFO Data FIFO Data FIFO Data FIFO Data n 7 n 7 n 6 n 5 n 4 Etc WRITE TX FIFO Channel 0 7 Write Only This register provides a faster alternative to writing data in 8 bit format to the transmit holding register THR Using this register TX FIFO data can be written using 32 bit write operations maximum 16 DWORD writes The data is formatted as follows WRITE TX FIFO Byte 3 Byte 2 Byte 1 Byte 0 Write n 0 to FIFO Data FIFO Data FIFO Data FIFO Data n 3 n 3 n 2 n 1 n 0 Write n 4 to FIFO Data FIFO Data FI
41. ds with the LSB bit for the receive character If flow control is set for comparing Xon1 Xoff1 then flow control and special character detect work normally However if flow control is set for comparing Xon2 Xoff2 then flow control works normally but Xoff2 will not go to the FIFO and both an Xoff interrupt and special character interrupt will be generated R 0 Auto DTR 1 Enable Automatic RTS flow control The Hardware RTS or DTR pin can be automatically Flow controlled to indicate local buffer overflows Control to remote units When Auto RTS DTR is enabled an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS DTR 16 will de assert HIGH at the next upper tigger or selected hysteresis leve DTR will return LOW when data is unloaded below the next lower trigger or selected hysteresis level The RTS or DTR output must be asserted OU before the auto RTS DTR can take efiect MCR bit2 selects RTS or DTR 0 DIS uto DSR Enable Atomatic CTS flow control The Hardware CTS pin can be monitored for remote Flow buffer overflow indication When Control automatic CTS DSR hardware flow control is enabled Transmission stops when CTS DSR pin de asserts HIGH Transmission resumes after the CTS DSR returns LOW MCR bit2 selects CTS or DSR TXCNT Transmit FIFO Level Counter Channels 0 7 Read Only This 8 bit register gives an indication of the transmit FIFO l
42. e application When the board is shipped from the factory it is configured as follows e The default configuration of the programmable software control register bits at power up are described in section 3 e The control registers must be programmed to the desired configuration before starting data input or output operation Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com EIA TIA 232E SERIAL COMMUNICATION BOARD The front panel connector provides the field I O interface connections It is a SCSI 3 68 pin female connector AMP 787082 7 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to Acromag termination panel 5025 288 from the front panel via round shielded cable Model 5028 432 All eight EIA TIA 232E serial communication channels for interfacing are shown in table 2 1 Each channel has six signals and are designated by RX4 CO o f Roue PE 0 RX5 O CTS5 RTS5 DSR5 DTR5 e CTS6 RTS6 DSR6 DTR6 m 4 5 n RX7 ap COMMON Pin 35 36 37 38 39 40 EH 42 43 ES 45 46 Eza 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 EE 65 66 67 68 channels 0 through channel 7 Pin Description RXO COMMON COMMON
43. eceivers is to convert the required EIA TIA 232E signals to the TTL levels required by the UART Universal Asynchronous Receiver Transmitter The line drivers convert the UART TTL levels to the EIA TIA 232E voltage levels The UART provides the necessary conversion from serial to parallel receive and parallel to serial transmit for interfacing to the data bus Additionally it provides data buffering and data formatting capabilities A programmable logic device is used to control the interface between the UART and the PMC bus Note that the field serial interface to the carrier board provided through connector P1 or J4 refer to Table 2 1 or 2 2 is NON ISOLATED This means that the field signal return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause errors in operation and with extreme abuse possible circuit damage Refer to Drawing 4501 710 for example communication wiring connections LOGIC POWER INTERFACE The logic interface to the carrier board is made through PMC connectors J1 J2 Not all of the PMC logic J1 J2 pin functions is used J1 J2 also provides 5V to power the module A programmable UART device installed on the PMC Module provides the control signals required to operate the board It decodes the selected addresses and produces the chip selects control signals and timing requi
44. ed or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier CPU board plus the installed boards within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering Remove power from the system before installing board cables termination panels and field wiring The board may be configured differently depending on th
45. ent for PMC rear I O models only Power Requirements Typical 146mA 5V 5 SAGE Operating Temperature Oto 70 C 40 C to 85 C E Version Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C 55 C to 105 C for PMC Models Non Isolated Logic and field commons have a direct electrical connection CE Mark All models are designed to comply with EMC Directive 89 336 EEC per European Standard EN 61000 6 1 2001 Electromagnetic compatibility EMC Part 6 1 Generic standards Immunity for residential commercial and light industrial environments and European Standard EN 61000 6 3 2001 Electromagnetic compatibility EMC Part 6 3 Generic standards Emission standard for residential commercial and light industrial environments Note No CE Mark at this time Mean Time Between Failure MTBF TBD hours calculated for PMC520 other models expected to be similar 25 C Using MIL HDBK 217F Notice 2 Exar XR17D158 Obtain data sheet at http www exar com Channel Configuration Eight independent non isolated EIA TIA 232E serial ports with a common signal return connection Data Rate 230K bits sec Maximum Limited by EIA TIA 232E transceivers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com 3 8 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD RS 232 Channels Interface Asynchronous serial only Cable Length
46. evel byte count 0 to 64 Due to the dynamic nature of the FIFO counters this register should be read until the same value is returned twice TXTRG Transmit FIFO Trigger Level Channels 0 7 Write Only When trigger table D is selected an 8 bit value written to this register sets the TX FIFO trigger level 0 to 64 If enabled an interrupt will be generated whenever the data level in the transmit FIFO falls below this preset trigger level RXCNT Receive FIFO Level Counter Channels 0 7 Read Only This 8 bit register gives an indication of the receive FIFO level byte count 0 to 64 Due to the dynamic nature of the FIFO counters this register should be read until the same value is returned twice Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 2 7 RXTRG Transmit FIFO Trigger Level Channels 0 7 Write Only When trigger table D is selected an 8 bit value written to this register sets the RX FIFO trigger level 0 to 64 If enabled an interrupt will be generated whenever the data level in the receive FIFO falls below this preset trigger level XCHAR Register Channels 0 7 Read Only When an Xoff Xon interrupt occurs ISR bit 4 is logic 1 reading the XCHAR register will indicate which character Xoff or Xon was received last XCHAR Register EFR Bit FUNCTION PROGRAMMING no Detected i E Xoff
47. hannel and indicates if that channel has requested service For example INTO bit 0 represents the interrupt status for channel 0 and INTO bit 7 represents the interrupt status for channel 7 An interrupt service routine can inspect INTO to determine that a channel requires service and then read the channel s Interrupt Status Register ISR to determine the source of the interrupt INT3 INT2 and INT1 31 8 provide a twenty four bit encoded interrupt indicator Each channel s interrupt is encoded into 3 bits for receive transmit and status Bits 10 8 represent channel 0 bits 13 11 represent channel 1 and so forth The table below shows the 3 bit encoding and priority order This interrupt source encoding provides much of the same interrupt source data that would be obtained by reading each channel s ISR Interrupt clearing is covered in the description of the Interrupt Status Register UART Channel 7 0 Interrupt Source Encoding Priority BitIN 2 Bit N 1 Bit N o Source ofthe Interrupt 0 0 0 Noe re n e er e d po 1 0 0 1 RXRDYandRXLineStatus TXHDY acre ES 1 TXRDYorTHRempty 3 VER RTS CTS or DIR DSR delta or Xoff Xon detected or special character detected 8XMODE Read Write Each bit of this 8 bit register selects an 8X or 16X sampling rate for the corresponding UART channel Channels 7 to 0 are configured using bit
48. haracter in the RX FIFO has an error parity framing overrun break Reading LSR will clear LSR 0 No data in the receive holding register or FIFO default 1 Data has been received and is saved in the receive holding register or FIFO 0 No overrun error default 1 Overrun error A data overrun error condition occurred in the receive shift register This happens when additional data arrives while the FIFO is full In this case the previous data in the receive shift register is overwritten Note that under this condition the data byte in the receive shift register is not transferred into the FIFO therefore the data in the FIFO is not corrupted by the error This bit is cleared after LSR is read 0 No parity error default 1 Parity error The received character in the RHR does not have the correct parity information and is suspect This error is associated with the character available for reading in RHR This bit is cleared after LSR is read 0 No framing error default 1 Framing error The receive character did not have a valid stop bit s This error is associated with the character available for reading in RHR This bit is cleared after LSR is read 0 No break condition default 1 The receiver received a break signal RX was a logic 0 for one character frame time In FIFO mode only one break character is loaded into the FIFO This bit is cleared after LSR is read Acromag Inc Tel 248 295 03
49. he receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the FIFO It is cleared when the FIFO drops below its programmed trigger level The receive data available interrupt indication ISR 04 also occurs when the FIFO reaches its trigger level and is cleared when the FIFO drops below its trigger level Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 3 0 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD When the receiver FIFO and receiver interrupts are enabled the following receiver FIFO character time out status conditions apply 1 A FIFO character time out interrupt occurs if the receive FIFO has not reached the programmed trigger level and the RX input has been idle for 4 character 12 bit times 2 From the clock signal input the character times can be calculated The delay is proportional to the baud rate 3 The time out timer is reset after the CPU reads the receiver FIFO or after a new character is received when there has been no time out interrupt 4 A time out interrupt is cleared by reading data until the RX FIFO is empty When the transmit FIFO and transmit interrupts are enabled FCR Bit 0 1 and IER Bit 1 1 a transmitter interrupt will occur as follows Whenever the THR becomes empty or the amount of data in the FIFO falls below the programmed trigger level the transmitter holding register interrupt ISR
50. hed transmission and a logic 0 will resume data transmission If automatic hardware flow control is not used MSR bit 4 is the compliment of the CTS input Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 24 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD MSR Bit FUNCTION PROGRAMMING aan ee DSR pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto DSR EFR bit 7 and DTR DSR flow control select MCR bit 2 Auto DSR flow control allows starting and stopping of local data transmissions based on the modem DSR signal A logic 1 on the DSR pin will stop the UART transmitter as soon as the current character has finished transmission and a logic 0 will resume data transmission If automatic hardware flow control is not used MSR bit 5 is the compliment of the DSR input Status Status Note that not all UART signal paths are used by this model and their corresponding UART pins are tied high 5V This includes RI Ring Indicator and CD Carrier Detect SCR Scratch Pad Register Channels 0 7 Read Write This 8 bit read write register has no effect on the operation of either serial channel It is provided as an aide to the programmer to temporarily hold data FCTR Feature Control Register Channels 0 7 Read Write Feature Control Register Bi FUNCTION PROGRAMMING Auto RTS DTR When Trigger T
51. ion As unbalanced this standard uses a voltage referenced to signal ground to denote the logical state of the data A logic 0 is represented by a driven voltage between 5V and 15V space and a logic 1 by a driven voltage between 5V and 15V mark At the receiving end a logic 0 is represented by a voltage between 3V and 15V space a logic 1 is represented by a voltage between 3V and 15V mark Voltages between 3V are undefined and lie in the transition region Note that at the interface a logic 0 is represented by a high voltage and a logic 1 by a low voltage The line drivers and receivers invert these signals to the conventional TTL level associations EIA TIA 232E BINARY 0 BINARY 1 SIGNAL SPACE OFF MARK ON TRANSMIT 5 to 15V DC 5 to 15V DC RECEIVE 3 to 13V DC 3 to 13V DC Start and stop bits are used to synchronize the DCE to the asynchronous serial data of the DTE The transmit data line is normally held in the mark state logical 1 The transmission of a data byte requires that a start bit a logical 0 or a transition from mark to space be sent first This tells the receiver that the next bit is a data bit The data bits are followed by a stop bit a logical 1 or a return to the mark state The stop bit tells the receiver Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 34 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD th
52. le the CTS DSR input pin is monitored to suspend resume the local transmitter Hardware flow control can be enabled by setting bits 6 and or 7 of the EFR register to logic 1 Bit 6 enables Auto RTS DTR Bit 7 enables Auto CTS DSR The state of Modem Control Register bit 2 determines which pins RTS and CTS OR DTR and DSR are used for auto hardware flow control Auto RTS flow control must be started by asserting the RTS output pin low MCR bit 1 1 Similarly Auto DTR flow control must be started by asserting the DTR output pin low MCR bit 0 1 When Auto RTS DTR is selected the RTS DTR signal will be forced to the de asserted state when the receiver FIFO reaches a programmed trigger level RTS DTR will re assert when the receiver holding register contents drops below the next lower trigger level The UART will accept additional data when the transmission is suspended during hardware flow control until all FIFO locations are filled When Auto CTS DSR is selected the UART will automatically suspend data transmission as soon as a complete character is transmitted and the CTS DSR input level changes from low to high de asserted Transmission will resume as soon as the CTS DSR signal changes to the low level asserted Two interrupts are associated with auto RTS CTS and DTR DSR flow control and may be used to give indication when the RTS DTR pin or CTS DSR pin are de asserted during operation Setting IER bit 6 wi
53. ll enable the RTS DTR interrupt when these pins are de asserted Setting IER bit 7 will enable the CTS DSR interrupt when these pins are de asserted Note that EFR bit 4 must be set to 1 to access IER bits 6 and 7 Both hardware and software flow controls can be enabled for automatic operation Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 32 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD Programming Example The following example will demonstrate transfer between channel 0 of the host PMC520 and another node using automatic hardware flow control Both nodes will use the FIFO mode of operation The baud will be set to 9600 The data format will use 8 bit characters odd parity and 1 stop bit The example assumes registers not mentioned are in their default states Please refer to Table 3 1 for address locations The H following data below refers to the Hexadecimal format 1 Write 80H to the Line Control Register LCR This sets the Divisor Latch Access bit to permit access to the two divisor latch bytes used to set the baud rate These bytes share addresses with the Receive and Transmit buffers and the Interrupt Enable Register IER 2 Write 00H to the Divisor Latch MSB DLM Write 60H to Divisor Latch LSB DLL This sets the divisor to 96 for 9600 baud i e 9600 14 7456MHz 16 x 96 3 Write OBH to the Line Control Register LCR This first tu
54. med by the control registers LCR IER DLL DLM MCR and FCR These control words define the character length number of stop bits parity baud rate and modem interface The control registers can be written in any order but the IER register should be written last since it controls the interrupt enables The contents of these registers can be updated any time the serial channel is not transmitting or receiving data The complete status of each channel can be read by the host CPU at any time during operation Two registers are used to report the status of a particular channel the Line Status Register LSR and the Modem Status Register MSR Serial channel data is read from the Receive Holding Register RHR and written to the Transmitter Holding Register THR Writing data to the THR initiates the parallel to serial transmitter shift register to the TX line Likewise input data is shifted from the RX pin to the Receive Holding Register as it is received This board operates in two different modes In one mode this device remains software compatible with the industry standard 16C550 family of UART s and provides double buffering of data registers In the FIFO Mode enabled via bit 0 of the FCR register data registers are FIFO buffered so that read and write operations can be performed while the UART is performing serial to parallel and parallel to serial conversions Two FIFO modes of operation are possible FIFO Interrupt Mode and F
55. o be added to or deleted from the serial data stream e Programmable Parity Generation amp Detection Even Odd or No Parity generation and detection is supported e Line Break Generation 8 Detection provision for sending and detecting the line break character is provided e False Start Bit Detection Prevents the receiver from assembling false data characters due to low going noise spikes on the RX input line e Programmable Baud Rate The internal baud rate generator allows the n 4K maximum baud rate to be divided by any divisor between 1 and 2 2 1 providing support for all standard baud rates e Interrupt Support Individually controlled transmit empty receive ready line status data set amp flow control interrupts may be generated e Individual Modem Control Signals Each serial channel includes a modem control and modem status register and provides EIA TIA 232E modem line support including RTS CTS DTR and DSR Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD 5 e Internal Diagnostic Capabilities Loopback controls for KEY PMC520 communication link fault isolation are included Break parity overrun FEATURES and framing error simulation are also possible e Compatible with Industry Standard UARTs Each UART of this PMC module has its own 16550 UART compatible configuration register set e
56. onfiguration registers with the unique memory base address The configuration registers are also used to indicate that the board requires an interrupt request line The system software then programs the configuration registers with the interrupt request line assigned to the board Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space and which interrupt line will be used PCI CONFIGURATION The PCI specification requires software driven initialization and REGISTERS configuration via the Configuration Address space This board provides 256 bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Channels The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base address assigned to the board and the interrupt request line that goes active on a board interrupt request Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 1 1 Table 3 1 Configuration 0 DevicelD 0520 VendoriD 16D5 Command Rev ID 02
57. ontrol Register Channels 0 7 Read Write The Line Control Register is used to specify the asynchronous data communication format The word length the number of stop bits and the parity are selected by writing the appropriate bits in this register Line Control Register LCR Bit FUNCTION PROGRAMMING 1 0 Word Lengt 00 t Sel 01 Data Bits 10 Data Bits 11 oe Bits 1 detault 1 5 Slop Bits if 5 data bits 2 Stop Bits if 6 7 or 8 data bits Selected Parity Enable 0 No Ai 1 A parity bit is generated during the transmission while the receiver checks for parity error of the data character received top Bit Select 4 Parity select a ODD Parity EVEN Parit orced Parity parity IS not forced ult Select 1 and LCR BIT 4 0 Dad bit i is forced to alogic 1 MARK for the transmit and received data 1 and LCR BIT 4 arity bit is forced to a logic 0 SPACE for the transmit and reeewed data ransmit Brea NO Enable 1 Forces the transmitter Oi space LOW for alerting the remote receiver of a line break condition This condition remains until disabled by setting LCR bit 6 to a logic 0 20 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 2 1 Bit FUNCTION PROGRAMMING Baud Rate 0 Data registers are selected default Divisor 1 Divisor latch registers are selected
58. operly see the Global Interrupt Enable section Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 1 7 Interrupt Enable Register IER BIT RHR Interrupt Enable 0 Disable Interrupt default 1 Enable Interrupt The receive data ready interrupt will be issued when RHR has a data character in the non FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode A receive data timeout interrupt will be issued in the FIFO mode when the receive FIFO has not reached the programmed trigger level and the RX input has been idle for 4 character 12 bit times THR Interrupt Enable 0 Disable Interrupt default 1 Enable Interrupt This interrupt is associated with bit 5 in the LSR register An interrupt is issued whenever the THR becomes empty or when data in the FIFO falls below programmed trigger level Receive Line Status Interrupt Enable 0 Disable Interrupt default 1 Enable Interrupt Any LSR register bits 1 2 3 or 4 will generate an LSR immediately when a character received in the RX FIFO has an error Modem Status Interrupt Enable 0 Disable Interrupt default 1 Enable Interrupt Xoff Interrupt Enable requires EFR bit 4 1 0 Disable the software flow control default 1 Enable the software flow control RTS DTR Output Interrupt Enable requires EFR bit 4 1 0 Disable Interrupt
59. ps to prevent the receiver from assembling an invalid data character due to a low going noise spike on the receive data line THR Transmit Holding Register Channels 0 7 WRITE Only The Transmitter Holding Register THR is a serial channel output data register that holds from 5 to 8 bits of data as specified by the character size programmed in the Line Control Register If less than 8 bits are transmitted then data is entered right justified to the LSB This data is framed as required then shifted to the transmit data line The THR is also the input register to the transmit FIFO when FIFO operation is enabled by FCR bit 0 The status of the THR is provided in the Line Status Register LSR The THR empty flag in the LSR register is set to a logic 1 when the last data byte is transferred from the THR to the transmit shift register DLL amp DLM Divisor Latch Registers Channels 0 7 R W Each channel has its own Baud Rate Generator BRG with a prescaler for the transmitter and receiver A software bit in the Modem Control Register MCR controls the prescaler The MCR register bit 7 sets the prescaler to divide the 14 7456MHz crystal by 1 or 4 The output of the prescaler clocks to the BRG The BRG further divides this clock by a programmable divisor between 1 and 25 to obtain a 16x or 8x sampling clock of the serial data rate Two 8 bit divisor latch registers per channel are used to store the divisors in 16 bit binary format The DLL
60. read of the LSR register e RXRDY is cleared by reading data until FIFO falls below the trigger level e RXRDY Time out is cleared by reading data until the RX FIFO is empty e TXRDY interrupt is cleared by a read of the ISR register MSR interrupt is cleared by a read of the MSR register e Xon or Xoff character interrupt is cleared by a read of the ISR register e Special character interrupt is cleared by a read of the ISR register or after the next character is received e RTS DTR and CTS DSR status change interrupts are cleared by a read to the MSR register Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 1 0 FCR FIFO Control Register Channels 0 7 WRITE Only This write only register is used to enable and clear the FIFO buffers and set the transmit receive FIFO trigger levels TX and RX FIFO Enable 0 Disable the transmit and receive FIFO default 1 Enables both the Tx and Rx FIFO s This bit must be a 1 when other FCR bits are written to or they will not be programmed RX FIFO Reset This bit is only active when FCR bit 0 is active 0 No receive FIFO reset default 1 Reset the receive FIFO pointers and FIFO level counter logic the receive shift register is not cleared or altered This bit will return to logic 0 after resetting the FIFO TX FIFO Reset This bit is only active when FCR bit 0
61. red by the communication registers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com EIA TIA 232E SERIAL COMMUNICATION BOARD Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board Whena board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at htip www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials
62. rns off the Divisor Latch Access bit to permit accesses to the Receiver and Transmit buffers and the Interrupt Enable Register It also sets the word length to 8 bits the number of stop bits to one and enables odd parity 4 Write 90H to the Enhanced Feature Register EFR This enables the enhanced function bits in the IER ISR FCR and MCR In addition this enables Auto CTS Flow control 5 Write 80H to the Feature Control Register FCTR This selects Trigger Table C 6 Write 25H to the FIFO Control Register FCR This enables and resets the TX FIFO It also sets the Transmit Trigger Level to 32 7 Write FEH to the Multipurpose Input Output Pin Select Register MPIOSEL and write 01H to the Multipurpose Input Output Level Control Register MPIOLVL This enables interrupts from any channel to reach the PCI bus 8 Write 02H to the Interrupt Enable Register IER After setting this bit an interrupt is issued whenever the data in the TX FIFO falls below the programmed trigger level Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 3 3 9 The interrupt service routine reads the Interrupt Status Register ISR to clear the TXRDY interrupt Data is added to the FIFO by repeatedly writing 8 bit values to the Transmit Holding Register THR Alternatively 16 or 32 bit values can be written to the channel s Write FI
63. rol Register READ WRITE MCR Channel 0 Modem Control Register READ LSR Channel 0 Line Status Register Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 2 PMC520 User s Manual EIA TIA 232E SERIAL COMMUNICATION BOARD MEMORY MAP mr m sens READ MSR Channel 0 Modem Status Register WRITE RS485 Channel 0 Turn Around Delay Register Not Supported READ WRITE SPR 07 Channel 0 Scratch Pad Register READ WRITE FCTR Channel 0 Feature Control Register READ WRITE EFR Channel 0 Enhanced Function Register READ TXONT Channel 0 Transmit FIFO Level Counter WRITE TXTRG Channel 0 Transmit FIFO Trigger Level READ RXCNT Channel 0 Receive FIFO Level Counter WRITE RXTRG Channel 0 Receive FIFO Trigger Level WRITE Channel 0 Xoff 1 Xoff Character 1 Xon Xoff RIO Xchar Rcvd Flags WRITE Channel 0 Xoff 2 Xoff Character 2 WRITE Channel 0 Xon 1 Xon Character 1 WRITE Channel 0 Xon 2 Xon Character 2 Reserved 10 7F DEVICE CONFIGURATION REGISTERS See Table 3 3 80 93 Reserved 94 FF READ Data Width Channel 0 Read FIFO 8 16 24 32 WRITE Data Width Channel 0 Write FIFO 8 16 24 32 Reserved 140 17F READ Data Width Channel 0 Read FIFO with errors 16 32 UART Channel 1 Channel 1 Registers 200 20F Reserved 210 2FF READ Data Width Channel 1 Read FIFO 8 16 24 32 300 33
64. s 7 to 0 respectively Logic 0 default selects normal 16X sampling while logic 1 selects 8X sampling rate Transmit and receive data rates will double by selecting 8X RESET Read Write UART channels 7 to 0 can be reset using bits 7 to 0 respectively After setting a bit to logic 1 all registers in the corresponding channel will be reset to the default condition Each bit is self resetting after it is written Global Interrupt Enable Read Write On the PMC520 the UART s multi purpose input output 0 MPIOO is used internally as a Global Interrupt Enable switch In order for any UART channel interrupts to be seen by the system the multi purpose input output registers must be configured as follows 1 The MPIOINT MPIO3T and MPIO3T registers should be left in their default states all bits low The MPIOSEL register should be set to FEH FFH is the default This configures MPIO pin 0 as an output MPIOLVL bits 7 to 1 should be left in their default state low MPIOLVL bit 0 now acts as the Global Interrupt Enable bit 0 Disable Interrupt 1 Enable Interrupt PO mw Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com http www acromag com PMC520 User s Manual EIATIA 232E SERIAL COMMUNICATION BOARD 1 5 RHR Receive Holding Register Channels 0 7 READ Only UART CONFIGURATION The Receive Holding Register RHR is a serial channel input data REGISTERS register that receives the input data from
65. t 5096 energized SCSI 3 connector SDeC S Operating Temperature 30 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL Type Termination Panel For 68 Pin SCSI 3 Cable Connection MODEL 5025 288 Application To connect field I O signals to the board Termination Panel Acromag Part 4001 066 The 5025 288 termination panel facilitates the connection of up to 68 field I O signals and connects to the board connectors only via a round shielded cable Model 5028 432 Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 68 correspond to field I O pins 1 68 on the board Each board has its own unique pin assignments Refer to the board manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 920 Field Wiring 68 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 0 pounds 0 5kg packaged Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email sales acromag com htip www acromag com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Em
66. terrupt An interrupt will then be generated After recognition of the XOFF character s the UART will compare incoming characters with the preprogrammed XON1 XON2 characters If a match is detected the UART will resume transmission When receiving data the UART will automatically send XOFF1 XOFF2 character s approximately 2 character times after the programmed RX FIFO trigger level is reached causing the host to suspend transmission The UART will then transmit the programmed XON1 XON2 character s when the RX FIFO level falls below the next lowest trigger level thus causing the host to resume transmission When single XON XOFF characters are selected the UART compares the received data to these values and controls the transmission accordingly XON restart transmission XOFF suspend transmission These characters are not stacked in the data buffer or FIFO Itis also possible to configure Special Character Detect which allows the Xoff2 value to be transferred to the FIFO This is configured using bit 5 of the Enhanced Feature Register When the XonAny function is enabled MCR bit 5 is set the UART will automatically resume transmission after receiving ANY character after having recognized XOFF and suspended transmission Hardware Flow Control Model PMC520 modules include support for hardware flow control via the RTS CTS or DTR DSR signals The RTS DTR output pin is used to request the remote unit to suspend resume data transmission whi
67. the receiver shift register and holds from 5 to 8 bits of data as specified by the character size programmed in the Line Control Register LCR bits 0 and 1 If less than 8 bits are transmitted then data is right justified to the LSB If parity is used then LCR bit 3 parity enable and LCR bit 4 type of parity are required Status for the receiver is provided via the Line Status Register LSR When a full character is received including parity and stop bits the data received indication bit bit 0 of the LSR is set to 1 The host CPU then reads the Receiver Buffer Register which resets LSR bit 0 low If the character is not read prior to a new character transfer between the receiver shift register and the receive holding register the overrun error status indication is set in LSR bit 1 If there is a parity error the error is indicated in LSR bit 2 If a stop bit is not detected a framing error indication is set in bit 3 of the LSR Serial asynchronous data is input to the receiver shift register via the receive data line From the idle state this line is monitored for a high to low transition start bit When the start bit is detected an internal receiver counter starts counting at the 16x or 8x clock rate After 8 or 4 clocks the start bit period should be at its center The start bit is judged valid if it is still low at this point This is known as false start bit detection By verifying the start bit in this manner it hel

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