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DesignWare Library Quick Reference Guide

1. Model Name Vendor Description Processor Models arm7tdmi fx ARM 32 Bit RISC Microprocessor mcf5307 fx Motorola MCF5307 Integrated Coldfire Microprocessor mpc7400_fz Motorola MPC7400 RISC Microprocessor mpc740_fx IBM PowerPC RISC Processor mpc750 12 fx IBM MPC750 RISC Microprocessor L2 cache mpc8260 fz Motorola MPC8260 Power Quic II Integrated PowerPC Processor mpc860 fx Motorola 32 Bit Quad Integrated Communications Controller ppc603e fx IBM PowerPC 603e RISC Microprocessor mpc603e fx Motorola tms320c6201 fx TI Digital Signal Processor 262 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Listing of FlexModels Table 1 Listing of FlexModels Continued Model Name Vendor Description vr5432 fx NEC MIPS RISC Microprocessor vr5464 fx NEC 64 bit Microprocessor Bus Models enetrx fx Ethernet Receives frame stores received data and updates status enettx fx Ethernet Handles data encapsulation and frame transmission enethub fx Ethernet Emulates the protocol of Ethernet Hub at the pin and bus cycle levels handles data routing from TX to RX rmiis fx Ethernet Interface between MII and reduced RMII interface ieee 1394a_fx IEEE1394a Emulates the IEEE1394a protocol and bus nodes ieee1394phy fx IEEE1394a Emulates multiple PHY layers connected to P1394a bus pcimaster fx PCI PCI X Emulates the protocol of PCI
2. Pin Name Width Direction Function clk 1 bit Input Clock cs_n 1 bit Input Chip select active low wr n bit Input Write enable active low rd addr ceil logs5 depth bit s Input Read address bus wr addr ceil log depth bit s Input Write address bus data in data width bit s Input Input data bus data out data width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data width to 256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 157 DesignWare IP Family Quick Reference Guide 100111001 DW ram 2r w s dff Synchronous Write Port Asynchronous Dual Read Port RAM Flip Flop Bas RAM DW ram 2r w s dff Synchronous Write Port Asynchronous Dual Read Port RAM Flip Flop Based e Parameterized word depth rdi addr rd2_addr e Parameterized data width wr_addr e Synchronous static memory data_in data rdi out e Parameterized reset mode synchronous or asynchronous Em e Inferable from Behavioral Compiler wr n Gata Jue pur e High testability using DFT Compiler Sak Table 1 Pin Description Pin Name W
3. 96 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide E b DWO02 sincos cos Combinational Sine Cosine DWO2 sincos Combinational Sine Cosine e Parameterized word length SIN COS A WAVE Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Angle in binary SIN COS l bit Input sine SIN_COS 0 or cosine SIN_COS 1 WAVE wave_width bit s Output sine or cosine value of A Table 2 Parameter Description Parameter Values Function A_width 2 to 34 _ Word length of A wave_width 2 to 34 Word length of WAVE Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 97 DesignWare IP Family Quick Reference Guide Datapath Sequential Overview Datapath Sequential Overview y This section documents the various Datapath Sequential IP found in the DesignWare Building Block IP 98 Synopsys Inc April 2003 f DW div seq Sequential Divider DesignWare IP Family Quick Reference Guide DW div seq Sequential Divider e Parameterized word length e Parameterized number of clock cycles e Unsigned and signed two s complement data multiplication e Registered or un registered inputs and outputs quotient remainder
4. PCI PCI X Bus Verification Models USB 1 1 2 0 Bus Host Interface Model DesignWare Memory Models DesignWare SmartModels SmartModel Features 1 2 eee rr nn SmartModel Types asosecosesavecssectkms SmartModel Timing Definitions Specific Model Information Chapter 4 Design Ware Cores 666i6s seu ceene ev cwes oanvwn wre BINE dae cn cad dees cdeas dwcore_blueiq_dev it s sc5a4asse0e dwcore ethernet oraaski te ackkkahe dwcore_ethernet_sub Loseeesioecesxsx dwcore_gig_ethernet cioe dwcore_gig_ethernet_sub en a4 asc d di EEEE UODB BUE TE UU rA de dd ae dwcore_pci_express Luasecxkeeird rhe aol Jb Olr ausieaseXxent sera dwcore_usbl_device ixss e d ER yw dwcore_usbl_host uaoessaeitexbbakg dwcore_usbl_hub Quaseskstaeksrax weer ub Dost i c p ERA GR dwcore_usb2_device oeseuseussx xo dwcore wsb2 ONY auunssksti esex a dwcore_1394_avlink ges csavesseses dweore 1394 device iossuses e Ren dwcore_1394_ohci caswetsee es cae an weer 13994 Cy occisi er RR dwcore_jvxtreme oocosusesessskk n A uoo Jes CONE ausc eeeiserexds wcore qpesz podes 4445554 Ke 5084 dwcore_jpeg2_encod xllnsesome sexa 8 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Contents Chapter 5 Deaan ate Sar ID duauaxueektcehibhebuAs ERE RANRERRYREERS AE RE RR KT 299 DN MAD ecoduads Adidas d X pd ER XR ER ERR AREE UR 300 DN VIUBS ea ee ee E Ed FE REED vd dE ERR 3
5. LAM 8b10b Decoder DW 8b10b dec 8b10b Decoder e Configurable data width data in data out e Configurable simplified Special Character indicator Peer ee k_char flags for protocols requiring only the K28 5 special ub rd init rd n character error rd err code err ret n enable e Synchronous initialization of Running Disparity with S cik design specified value e All outputs registered Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock input rst_n 1 bit Input Asynchronous reset input active low init rd n 1 bit Input Synchronous initialization control input active low init_rd_val 1 bit Input Value of initial Running Disparity data_in bytes X 10 bit s Input Input 8b 10b data for decoding error 1 bit Output Active high error flag indicating the presence of any type of error running disparity or coding in the information currently decoded on data_out rd 1 bit Output Current Running Disparity after decoding data presented at data_in to data_out k_char bytes bit s Output Special Character indicators one indicator per decoded byte data_out bytes x 8 bit s Output Decoded output data rd_err 1 bit Output Active high error flag indicating the presence of one or more Running Disparity errors in the information currently decoded on data_out code er 1 bit Output Active high error flag indicating the presence of a
6. Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n l bit Input Asynchronous reset active low init rd n 1 bit Input Synchronous initialization active low oin 1 bit Input Value of initial Running Disparity k char bytes bit s Input Special Character controls one control per byte to encode data in bytes x 8 bit s Input Input data for encoding rd 1 bit Output Current Running Disparity before encoding data presented at data_in data_out bytes x 10 Output 8b10b Encoded data bit s Table 2 Parameter Description Parameter Value Description bytes 1 to 16 Number of bytes to encode Default 2 k28_5_only Oor 1 Special Character subset control parameter Default 0 0 for all special characters available 1 for only K28 5 available when k_char HIGH regardless of the value on data_in Table 3 Synthesis Implementations Implementation Function License Required rtl Synthesis model DesignWare Foundation April 2003 Synopsys Inc 187 DesignWare IP Family Quick Reference Guide 00000000 oding DW 8b10b unbal DW 8b10b unbal 8b10b Coding Balance Predictor e Independent of Running Disparity data in unbal e Higher speed than a full encoder k char e Predicts balance for both data and special characters Table 1 Pin Description Pin Name Width Direction Function k ch
7. 128 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifo s2 sf Asymmetric Synchronous Dual Clock FIFO with Static Flags a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description data in width 1 to 256 Width of the data in bus data in width must in an integer multiple of data out width That is either data in width K x data out width or data out width 2 K x data in width where K is an integer data out width 1 to 256 Width of the data out bus data out width must be an integer multiple of data in width That is either data in width K x data out width or data out width 2 K x data in width where K is an integer depth 4 to 256 Number of words that can be stored in FIFO push ae Ivl 1 to depth 1 Almost empty level for the push_ae output port the number of words in the FIFO at or below which the push_ae flag is active push af lvl 1 to depth 1 Almost full level for the push_af output port the number of empty memory locations in the FIFO at which the push_af flag is active pop ae lvl 1 to depth 1 Almost empty level for the pop_ae output port the number of words in the FIFO at or below which the pop_ae flag is active pop af lvl 1 to depth 1 Almost full level for the pop_af output port the number of em
8. Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation el2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 175 DesignWare IP Family Quick Reference Guide R Data Integrity Data Integrity This section documents the various data integrity IP found in the DesignWare Building Block IP 176 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW crc p Universal Parallel Combinational CRC Generator Checker DW crc p Universal Parallel Combinational CRC Generator Checker e Parameterized arbitrary polynomial up to 64 bit e Parameterized data width up to 512 bits e Parameterized initial CRC value all ones or all zeroes e Parameterized inversion of generated CRC e Parameterized bit and byte ordering Table 1 Pin Description Pin Name Width Direction Function data_in data_width bit s Input Input data used for both generating and checking for valid CRC crc_in poly size bit s Input Input CRC value used to check a record not used when generating CRC from d
9. Table 3 Synthesis Implementations Implementation Name Implementation License Required str Synthesis model DesignWare Foundation 178 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW crc s Universal Synchronous Clocked CRC Generator Checker DW crc s Universal Synchronous Clocked CRC Generator Checker e Parameterized arbitrary polynomial up to 64 bit data in data out e Parameterized data width up to polynomial size init n draining e Parameterized register initialization all ones or all ld crc n grain done zeroes crc in crc ok e Parameterized inverted insertion of generated CRC drain i crc ou e Parameterized bit and byte ordering enable TP gt clk e Loadable CRC value for use in context switching of rt n interspersed blocks Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock input rst_n 1 bit Input Asynchronous reset input active low init_n 1 bit Input Synchronous initialization control input active low enable 1 bit Input Enable control input for all operations other than reset and initialization active high drain 1 bit Input Drains control input active high ld crc n 1 bit Input eee CRC register load control input active ow data_in data_width bit s Input Input data crc in poly size bit s Input Input CRC value to be loaded into the CRC register
10. 240 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW apb rap AMBA APB Remap and Pause DW apb rap AMBA APB Remap and Pause e Remap Control switches DW ahb e Pause mode puts DW ahb arbiter into address decoder from boot mode to low power pause mode nonna mode OPOIIHOR e Reset Status Register keeps track of e Identification code register status from up to eight separate system implements configurable read only ID reset signals register for accessing user defined e Component version ID register values DW apb rap scan mode Registers Sys resets por reset n Remap L remap n Pause prdata pause APB Interface Optional signals The DesignWare DW apb rap Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 241 DesignWare IP Family Quick Reference Guide DW apb rtc AMBA APB Real Time Clock DW apb rtc AMBA APB Real Time Clock e APB slave interface with read write coherency for registers e Incrementing counter and comparator for interrupt generation e User defined parameters o APB Data Bus Width o Counter Width o Clock relationship between bus clock and counter clock o Interrupt polarity level o Interrupt clock domain location o Counter enable mode Some uses of the DW apb rtc are e Real time clock used
11. divide by O complete clk Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low hold 1 bit Input Hold current operation 1 start 1 bit Input Start operation 1 A new operation is started by setting start 1 for one clock cycle a a width bit s Input Dividend b b width bit s Input Divisor complete bit Output Operation completed 1 divide by 0 1 bit Output Indicates if b equals 0 quotient a width bit s Output Quotient remainder b width bit s Output Remainder Table 2 Parameter Description Parameter Values Description a width 23 Word length of a b width 23 and Xa width Word length of b tc mode Oor 1 Two s complement control Default 0 0 unsigned 1 two s complement num cyc 23 and lt a_width User defined number of clock cycles to produce a valid Default 3 result The real number of clock cycles depends on various parameters April 2003 Synopsys Inc 99 DesignWare IP Family Quick Reference Guide DW div seq Sequential Divider Table 2 Parameter Description Continued Parameter Values Description rst mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset input_mode Oor 1 Registered inputs Default 1 0 no 1 yes output_mode Oor 1 Regist
12. pop req n 1 bit Input FIFO pop request active low diag n 1 bit Input Diagnostic control active low for err mode 0 NC for other err mode values data in data in width bit s Input FIFO data to push empty 1 bit Output FIFO empty output active high almost empty 1 bit Output FIFO almost empty output active high asserted when FIFO level xae level half full 1 bit Output FIFO half full output active high almost full bit Output FIFO almost full output active high asserted when FIFO level 2 depth af level full 1 bit Output FIFO full output active high ram full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part_wd 1 bit Output Partial word active high for data_in_width lt data_out_width only otherwise tied low data_out data_out_width bit s Output FIFO data to pop 124 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide TT DW asymfifo s1 sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags Table 2 Parameter Description Parameter Values Description data in width 1 to 256 Width of the data in bus data in width must be in an integer multiple relationship with data out width That is either data in width K x data out width or data out width K x data in width where K is an integer data out width 1 to 256 Width of the data out bus data out width must be in an integer multiple relationship with data
13. start 1 bit Input Start operation 1 A new operation is started by setting start 1 for one clock cycle a width bit s Input Radicand complete 1 bit Output Operation completed 1 root width 1 2 bit s Output Square root Table 2 Parameter Description Parameter Values Description width 26 Word length of a tc_mode Oor 1 Two s complement control Default 0 0 unsigned 1 two s complement num_cyc 23 and lt width User defined number of clock cycles to produce a valid Default 3 result The real number of clock cycles depends on various parameters rst_mode O or 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset April 2003 Synopsys Inc 103 DesignWare IP Family Quick Reference Guide DW sqrt seq Sequential Square Root x Table 2 Parameter Description Continued Parameter Values Description input mode Oor 1 Registered inputs Default 1 0 2 no yes output mode O0 or 1 Registered outputs Default 1 0 2 no yes early start Oor 1 Computation start Default 0 0 start computation in the second cycle 1 start computation in the first cycle Table 3 Synthesis Implementations Implementation Function License Required cpa Carry propagate adder synthesis model DesignWare Foundation 104 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Datapath Floating Point Overview Datapath Floating Point Ove
14. 1 0 no reset 1 asynchronous reset 2 synchronous reset 88 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW sqrt pipe Stallable Pipelined square root Table 3 Synthesis Implementations Implementation Name Implementation License Required str Pipelined str synthesis model DesignWare Foundation a One of rpl or cla implementation is selected based the constraints of the design April 2003 Synopsys Inc 89 DesignWare IP Family Quick Reference Guide DWO1 sub Subtractor DWO1 sub Subtractor e Parameterized word length e Carry in and carry out signals Table 1 Pin Description A CI DIFF p CO Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data CI 1 bit Input Carry in DIFF width bit s Output Difference of A B CI CO 1 bit Output Carry out Table 2 Parameter Description Parameter Values Description width 2l Word length of A B and DIFF Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none bk Brent Kung synthesis model DesignWare Foundation clf Fast carry look ahead synthesis model DesignWare Foundation csm Conditional sum synthesis model DesignWare Foundati
15. 1 bit Output Indicates that an error has been detected active high Location of error is specified by the error syndrome err multpl 1 bit Output Indicates that the error detected is a multiple bit error and therefore uncorrectable dataout width bits Output Output data May be corrected if an error is detected and correct n is asserted chkout chkbits bits Output When gen 1 chkout contains the check bits generated from datain When gen 0 and synd sel 0 chkout is the corrected or uncorrected data from chkin When gen 0 and synd_sel 1 chkout is the error syndrome value April 2003 Synopsys Inc 181 DesignWare IP Family Quick Reference Guide DW ecc Error Checking and Correction Table 2 Parameter Description Parameter Values Description width 8 to 502 Width of input and output data buses chkbits 5 to 10 Width of check bits input and output buses calculated from width synd sel Oor 1 Selects function of chkout when gen 0 If synd sel 0 and gen 0 then chkout is the corrected or uncorrected data from chkin If synd sel 1 and gen 0 then chkout is the error syndrome value Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 182 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWOA par gen Parity Generator and Checker DWO04A par gen Parity
16. 4 timer intr n timer intr flag timer intr flag n The DesignWare DW apb timers Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 245 DesignWare IP Family Quick Reference Guide DW apb uart AMBA APB Universal Asynchronous Receiver Transmitter DW apb uart AMBA APB Universal Asynchronous Receiver Transmitter 246 Functionality is based on the industry standard 16550 AMBA 2 0 compliant APB Interface with synthesis selectable prdata amp pwdata bus widths 8 16 32 Synthesis selectable IrDA 1 0 SIR Mode support with up to 115 2 Kbaud data rate Programmable FIFO disabling Modem and status lines are independently controlled External memory read enable signals for RAM wake up when external RAMs are selected Synthesis selectable transmit and receive FIFO depths Synthesis selectable internal DesignWare D flip flop based RAM Programmable FIFO disabling Synthesis selectable Programmable Transmitter Holding Register THRE Interrupt Mode Synopsys Inc Synthesis selectable synchronous or asynchronous external Read Port RAM interface when external RAMs are selected Synthesis selectable asynchronous serial clock support pclk or pclk and sclk Synthesis selectable lock up latch insertion before clock boundary crossing in two clock implementations for test purposes Synthesis selectable 16750 compatible Programmable Auto Flow
17. April 2003 Synopsys Inc 255 DesignWare IP Family Quick Reference Guide DesignWare VMT Models VMT Verification Modeling Technology models are bus functional models and monitors that can be instantiated in VERA or HDL testbenches All VMT models have a common command interface style that allows you to easily integrate standard bus protocol devices into your system testbenches All VMT models support these features e Multiple command streams Switch command control conditionally or unconditionally Execute Master and Slave command streams Stop command execution until new command streams are loaded e Verilog VHDL or VERA testbenches VMT models run on these simulators Synopsys VCS MTI Verilog Cadence NC Verilog and Verilog XL Synopsys Scirocco MTI VHDL and Cadence NC VHDL e Configurable message formatting Enable or disable o Message types Errors Warnings Timing X handling Notes Protocol o Message logs Simulator transcript window and or log files o Message features Building blocks of message content e Interrupt driven testbenches Waits for an event from the model and blocks commands until the event happens Some VMT models support additional features Consult model feature lists in this quick reference or model datasheets for supported features e Multiple command channels Simultaneously send and receive data full duplex operation e Constrained random test Conf
18. I S Slave 1 T l L T I l l r l 1 I 1 AHB gt AHB Master n 1 Z Slaven l l Write Mux I iere i l l We ea ke Bates i X l l l ps e Arbiter lt e E EE Low 3 I I Y Y Y YYY I Used when the d C sii 2 M Used when the Master is being C ACT Monitor ede being certified Dummy Master Default Slave Arbiter Decoder Write Mux and Read Mux are part of the AHB Bus VIP model This component is licensed separately from the DesignWare Library or DesignWare Verification Library The DesignWare AHB Verification IP Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 259 DesignWare IP Family Quick Reference Guide AMBA APB Models apb master vmt apb slave vmt apb monitor vmt AMBA APB Models apb master vmt apb slave vmt apb monitor vmt All Models APB Slave e Multiple command streams e Data Address width 8 32 bits e Verilog VHDL or VERA testbenches e Configurable memory fill patterns e Configurable message formatting e Big endian or little endian e Interrupt driven testbenches e FIFO memory at any memory location APB Master APB Monitor e 1 16 Slaves e Transaction logging e Data Address width 8 32 bits e Protocol checking e Constrained random test transactions e Incremental coverage reporting e Internal or external data mux e Error injection capab
19. P clk pop pop af pop full pop error ret n e Parameterized reset mode synchronous or asynchronous memory array initialized or not Table 1 Pin Description Pin Name Width Direction Function clk push 1 bit Input Input clock for push interface clk pop 1 bit Input Input clock for pop interface rst n bit Input Reset input active low push req n 1 bit Input FIFO push request active low flush n 1 bit Input Flushes the partial word into memory fills in 0 s for empty bits for data_in_width lt data_out_width only active low pop_req_n 1 bit Input FIFO pop request active low data_in data_in_width bit s Input FIFO data to push April 2003 Synopsys Inc 127 DesignWare IP Family Quick Reference Guide DW asymfifo s2 sf Asymmetric Synchronous Dual Clock FIFO with Static Flags n Table 1 Pin Description Continued Pin Name Width Direction Function push empty 1 bit Output FIFO empty output flag synchronous to clk push active high push ae bit Output FIFO almost empty output flag synchronous to clk_push determined by push ae Ivl parameter active high push_hf 1 bit Output FIFO half full output flag synchronous to clk push active high push af bit Output FIFO almost full output flag synchronous to clk push determined by push af lvl parameter active high push full bit Ou
20. Pin Description Pin Name Width Direction Function rst n bit Input Reset active low cs n 1 bit Input Chip select active low wr n 1 bit Input Write enable active low test_mode 1 bit Input Enables test_clk test_clk 1 bit Input Test clock to capture data during test_mode rdi addr ceil logo depth bit s Input Read1 address bus rd2_addr ceil logo depth bit s Input Read2 address bus wr addr ceil log depth bit s Input Write address bus data in data width bit s Input Input data bus data rdl out data width bit s Output Output data bus for read1 data rd2 out data width bit s Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data width 1to256 Width of data in and data out buses depth 2to 256 Number of words in the memory array address width rst mode Oor 1 Determines if the rst n input is used O rst ninitializes the RAM 1 2rst nis not connected 166 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 RAM DW_ram_2r_w_a_dff 01101001 Write Port Dual Read Port RAM Flip Flop Based Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 167 DesignWare IP Family Quick Reference Guide 100111001 RAM DW ram 2r w a l
21. Synthesizable USB 2 0 Host Controller The Synopsys DesignWare USB Host Controller UHOST2 is a set of synthesizable building blocks that ASIC FPGA for implementing a complete USB 2 0 host for 480 Mbps speeds The UHOST2 can be customized and optimized as a stand alone host chip or as an integrated ASIC for applications such as game consoles set top boxes PCs PDAs and telecommunications equipment In addition the design can be easily processed in most technologies and can be easily bridged to any industry standard bus and includes both the PCI and ARM AHB interfaces The application interface screens USB host controller design complexities making it easy to integrate the UHOST2 device to customer target applications Other features include the following e USB 2 0 EHCI and OHCI e Simple application interface facilitates specification compliant bridging the controller to other system e High speed 480 Mbps full speed buses 12 Mbps and low speed 1 5 Mbps e PCI and AHB interfaces available capability e Approximately 130K gates for a e Configurable root hub supporting up typical two port implementation to 15 downstream ports with 1 1 or 2 0 rs e Compatible with Synopsys speed capability High Speed Certified USB 2 0 PHY e Choice of micro frame or frame e Verilog source code caching of data structures EHCI e Test Environment includes EHCI compliance test and BFMs The dwcore usb2 host data sheet 1s available at http www
22. asynchronous reset 1 synchronous reset tst_mode Oor 1 Test Mode Default 0 0 test input not connected 1 lock up latches inserted for scan test Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple Carry synthesis model DesignWare Foundation el2 Full Carry lookahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 154 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 RAM Memory Synchronous RAMs Memory Synchronous RAMs This section documents the various memory synchronous RAMs DesignWare Building Block IP April 2003 Synopsys Inc 155 DesignWare IP Family Quick Reference Guide 100111001 DW ram r w s dff RAM Synchronous Write Port Asynchronous Read Port RAM Flip Flop Based 01101001 DW ram r w s dff Synchronous Write Port Asynchronous Read Port RAM Flip Flop Based e Parameterized word depth rd addr wr addr e Parameterized data width alacin e Synchronous static memory data o t la e Parameterized reset mode synchronous or asynchronous cs n wr n e Inferable from Behavioral Compiler e High testability using DFT Co
23. coding error in at least one byte of information currently decoded on data_out enable 1 bit Input Enables register clocking April 2003 Synopsys Inc 185 DesignWare IP Family Quick Reference Guide 00000000 oding DW 8b10b dec 8b10b Decoder 1010110001 Table 2 Parameter Description Parameter Values Description bytes 1 to 16 Number of bytes to encode Default 2 k28 5 only Oor 1 Special Character subset control parameter Default 0 0 for all special characters decoded 1 for only K28 5 decoded when k char HIGH implies K28 5 all other special characters indicate an error en mode Oor 1 Enable control Default 0 0 the enable input port is not connected backward compatible with older components 1 when enable 0 the decoder is stalled Table 3 Synthesis Implementations Implementation Name Function License Required rtl Synthesis model DesignWare Foundation 186 Synopsys Inc April 2003 00000000 11111111 odin 1010110001 DW 8b10b enc 8b10b Encoder e Configurable data width e Configurable simplified Special Character control for protocols requiring only the K28 5 special character e Synchronous initialization of Running Disparity with DesignWare IP Family Quick Reference Guide DW 8b10b enc 8b10b Encoder data in k char data out init rd val init rd n design specified value clk rst_n e All outputs registered
24. dwcore pci Synthesizable Universal PCI Controller dwcore pci Synthesizable Universal PCI Controller Corg The Synopsys DesignWare PCI intellectual property IP products are Verilog RTL synthesizable modules that provide an interface between the application and the PCI bus Features include the following e PCI specification 2 3 compliant e Support for Memory Read Line e 15 application optimized PCI IP Multiple and Memory Write and available in Verilog Invalidate commands e Silicon proven 33 MHz and 66 MHz e Dual Address cycles performance e Loadable configuration space e 32 bit or 64 bit PCI bus path e Universal configuration optimized for e 32 bit or 64 bit application data path use in both Host Bridge and Add in e Zero Latency Fast Back to Back Cant desine transfers e Delayed Read support e Zero Wait State Burst Mode transfers e PCI power management support e PCI multifunction support The dwcore pci data sheet is available at http www synopsys com products designware docs ds c dwcore_pci pdf 280 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Cor dwcore_pcix S Synthesizable PCI X Controller and Test Environment dwcore pcix Synthesizable PCI X Controller and Test Environment The Synopsys DesignWare PCI X Controller is a set of Verilog RTL synthesizable building blocks ASIC designers use to implement a complete PCI X interface PCI X is highly suitable in a wide range of applications such as
25. page 294 Synthesizable RTL JPEG Cores dwcore jpeg codec JPEG CODEC page 295 Synthesizable RTL dwcore jpeg2 codec JPEG2000 CODEC page 296 Synthesizable RTL dwcore jpeg2 encod JPEG2000 Encoder page 297 Synthesizable RTL Also visit the DesignWare Cores web page at http www synopsys com products designware dwcores html 24 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DesignWare Star IP Synopsys offers DesignWare Library users the ability to evaluate and design easily at their desktop using the following high performance high value IP cores from leading Chapter 1 Overview Star IP providers Component Name Component Description Component Type DW IBM440 PowerPC 440 Microprocessor Core from Synthesizable RTL Available Q2 03 IBM page 300 Verification Model DW V850E Star V850E Processor Core from NEC page 302 Synthesizable RTL Verification Model DW_C166S 16 bit Processor from Infineon page 304 Synthesizable RTL Verification Model DW TriCorel TriCorel 32 Bit Processor Core from Synthesizable RTL Infineon page 306 Verification Model DW MIPSAKE Processor Core Family from MIPS Synthesizable RTL page 308 Verification Model Mezoe Interface Express Interface Express Toolkit including Software BlueStack Protocol stack with Profiles and ProtoDeveloper Software page 310 Source Code SMSC USB 2 0 PHY Standard Microsystems Corporation GT3100 USB
26. 14 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 1 Overview 1 Overview The DesignWare family of products provides designers with a comprehensive portfolio of synthesizable and verification IP solutions targeting ASIC SoC amp FPGA designs DesignWare products offer an unparalleled advantage by providing engineers with thoroughly tested silicon proven IP all from a single provider ensuring complete interoperability The DesignWare family includes the following products e DesignWare Library on page 16 most commonly used design building blocks such as FIFO FIFO Controllers CRC ECC 8b10b as well as comprehensive AMBA On Chip Bus synthesizable and verification IP solution and more e DesignWare Verification Library on page 21 a subset of the DesignWare Library and contains reusable pre verified verification IP of the industry s most popular bus and interface standards such as AMBA PCI PCI X PCI Express USB 2 0 e DesignWare Cores on page 23 silicon proven digital and analog standards based connectivity IP such as PCI PCI X PCI Express USB 2 0 On the Go OTG USB 2 0 PHY e DesignWare Star IP on page 25 high performance high value IP microprocessor cores from leading Star IP providers such as IBM Infineon Technologies MIPS Technologies and NEC April 2003 Synopsys Inc 15 Chapter 1 Overview DesignWare IP Family Quick Reference Guide DesignWare L
27. 2 stall mode 0 or 1 Stall mode Default 1 0 non stallable 1 stallable rst_mode 0 to 2 Reset mode Default 1 0 no reset 1 asynchronous reset 2 synchronous reset sum_width 2 1 Word length of sum Default None Table 3 Synthesis Implementations Implementation Name Implementation License Required a str Pipelined str synthesis model Design Ware Foundation a One of csa wall or nbw implementation is selected based on the constraints of the design 80 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO1 satrnd Arithmetic Saturation and Rounding Logic DWO1 satrnd Arithmetic Saturation and Rounding Logic e Parameterized word length e Dynamically or statically configurable e Arithmetic saturation clipping or wrap around for MSB truncation e Round to nearest logic for LSB truncation e Signed and unsigned data operation Table 1 Pin Description Pin Name Width Direction Function din width bit s Input Input data tc 1 bit Input Two s complement control 0 2 unsigned 1 signed sat 1 bit Input Saturation enable 0 no saturation 1 enable saturation rnd 1 bit Input Rounding enable 0 no rounding 1 enable rounding OV 1 bit Output Overflow status dout msb out sb out 1 bit s Output Output data Table 2 Parameter Description Parameter Values Description wi
28. 2 0 PHY Star IP MacroCell page 311 Hard IP a Verification models of these cores are included in the DesignWare Library Synthesizable RTL of these cores are available through the Star IP Program Also visit the DesignWare Star IP web page at http www synopsys com products designware star ip html April 2003 Synopsys Inc 25 Chapter 1 Overview DesignWare IP Family Quick Reference Guide 26 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 2 DesignWare Library Synthesizable IP 2 DesignWare Library Synthesizable IP This chapter briefly describes theDesignWare Library synthesizable IP in the following subsections e Building Block IP Datapath Data Integrity Test e AMBA On Chip Bus Logic and Peripherals IP page 231 e Memory IP Memory BIST Memory Controller page 249 e Bus and I O Standards PCI PCI X PCI Express USB 2 0 Building Block IP The DesignWare Building Block IP formally called Foundation Library is a collection of over 140 technology independent high quality high performance IP Most of these IP elements include multiple implementations to provide a variety of performance and area tradeoff options DesignWare Building Block IP has superior datapath capabilities based on the Synopsys datapath generator technology The datapath generator feature of the DesignWare Library automatically produces complex datapath IP elements with better quality of
29. 21 Word length of A B_width 2 For csa architecture A width B_width 48 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation str Booth recoded Wallace tree synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A width and B width 348 bits as it has no area benefit beyond 48 bits April 2003 Synopsys Inc 67 DesignWare IP Family Quick Reference Guide DWO02 mult 3 stage Three Stage Pipelined Multiplier DWO02 mult 3 stage Three Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation e Three stage pipelined architecture e Automatic pipeline retiming Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A_width B width bit s Output P
30. 226 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW arbiter fcfs Arbiter with First Come First Served Priority Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 park mode 0or 1 park mode 1 includes logic to enable parking when no clients are Default 1 requesting and 2T park mode 0 contains no logic for parking park index 0 to nd Index of the client used for parking Default 0 output mode 0 or 1 output mode 1 includes registers at the outputs Default 1 output mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Required cla Carry look ahead synthesis model DesignWare Foundation clas Carry look ahead select synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 227 DesignWare IP Family Quick Reference Guide DW arbiter sp Arbiter with Static Priority Scheme DW arbiter sp Arbiter with Static Priority Scheme e Parameterizable number of clients e Programmable mask for all clients e Park feature default gra
31. 254 April 2003 Synopsys Inc Chapter 2 DesignWare Synthesizable IP 253 DesignWare IP Family Quick Reference Guide DW8051 8051 Microcontroller DW8051 8051 Microcontroller e Standard 8051 instruction set e Configurable full duplex serial ports e High speed architecture e Parameterizable RAM address range e Parameterizable ROM address range e Fully static synchronous design Internal RAM DW8051 Control l Main Registers Decoder Internal ROM o O Con e Integration of user defined peripherals through external Special Function Register SFR interface e Enhanced memory interface with 16 bit address bus e Variable length MOVX to access fast slow RAM peripherals Timer 2 Timers 0 and 1 optional Serial Port 0 optional Interrupt Unit Serial Port 1 optional The DesignWare DW 8051 MacroCell Databook is available at http www synopsys com products designware docs 254 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 3 DesignWare Library Verification IP 3 DesignWare Library Verification IP Overview The Designware Library Verification IP Intellectual Property is divided into the following categories e DesignWare VMT Models on page 256 e DesignWare FlexModels on page 262 e DesignWare SmartModels on page 268 e DesignWare Memory Models on page 267
32. AHB Bus Verification Model ahb master vmt AHB Master Verification Model ahb monitor vmt AHB Monitor Verification Model ahb slave vmt AHB Slave Verification Model AMBA APB Models refer to page 260 apb master vmt APB Master Verification Model apb monitor vmt APB Monitor Verification Model apb slave vmt APB Slave Verification Model April 2003 Synopsys Inc 21 Chapter 1 Overview DesignWare IP Family Quick Reference Guide DesignWare Bus amp I O Standards enettx fx enetrx fx enethub fx rmiirs fx IEEE 802 3 Transmitter Receiver RMII Interface Reconciliation Sublayer page 264 Verification Models pciexpress vmt PCI Express Verification Model pcimaster fx pcislave fx and pcimonitor fx PCI PCI X 32 bit and 64 bit 33 Mhz and 66 Mhz PCI Simulation Model and Test Suite page 265 Verification Models usbhost fz USB 2 0 Transceiver Macrocell Interface amp Universal Serial Bus 2 0 Host page 266 Verification Model 1eee1394a fx IEEE 13944 PHY LINK Verification Model Sio txrx vmt sio monitor vmt Serial Input Output Interface Models page 261 DesignWare Design Views of Star IP Microprocessors Verification Models DW IBMA440 Available Q2 03 PowerPC 440 Microprocessor Core from IBM page 300 Verification Model DW V850E Star V850E Processor Core from NEC page 302 Verificati
33. Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock cs_n 1 bit Input Chip select active low Wr n 1 bit Input Write enable active low rw addr ceil logo depth bit s Input Address bus data in data width bit s Input Input data bus data out data width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data width to 256 Width of data in and data out buses depth 2to256 Number of words in the memory array address width Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Components 162 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 RAN Memory Asynchronous RAMs Memory Asynchronous RAMs This section documents the various memory asynchronous RAMs found in the library of DesignWare Building Block IP April 2003 Synopsys Inc 163 DesignWare IP Family Quick Reference Guide A DW ram r w a dff RAM Asynchronous Dual Port RAM Flip Flop Based 01101001 DW ram r w a dff Asynchronous Dual Port RAM Flip Flop Based F wr_addr e Parameterized word depth id addr e Parameterized data width data in data_out e Asynchronous static memory cs n wr n e Parameterized reset implementation i An test mode e High testabilit
34. DOSE a I uasdaeqadadeeso kc qX RARE ERA Ve RERESGCP YE RASA QA A 23 ds doces adl PPP 25 Chapter 2 DesignWare Library SynthesizableIP eere 27 Building DIOGE IP isessdquet bes E REA X ARCLERA NER E Ru Rr d RAO EORR 27 Building Block IP DICENDUM ins 545 4 op or RAO eere pH inn oen 28 Building Block IP in FPGA Compiler II QuickStart 30 Datapath Generator Overview ceaauecaabeTsetasduuaRiqhecedeba adea 32 Datapaih Arithmetic Overview od e qr or dee e e Pa e aede a Reirs Epi 33 DWO SUM LacodaeXqadutusedsdqsdum kVbdetixdasdEa RV bd e AE E 34 DAU BB saquexeudeeeserquxsecetesberetdeeLviaibesrerdeLceadxes 33 DO SIUS 11 od qaia dci ed re ea d ae oro die ot rna 37 LN mAb dE quaeso uxo UA AEVO HOSE EE Ge RUE ap d ck 39 LOU ui4beebeidqu xauadedabdqxadesdasceaixbd34xndedadqadets 4 Ui 4 o oo APTITUDES 42 EUIS ee ee ee ee eee ee ee ee eee ee AREE ERES 43 DCL seredip Xe adei quer deira deip beidio nti 45 April 2003 Synopsys Inc 3 Contents DesignWare IP Family Quick Reference Guide I UNIO rcr 46 DA DUE UE Losexardadoos3 9 EN Arp Eotab doi dos rdiet do os P ox 48 EN COME SIE eeuaasi ext pEOXAE yp CREER ARO HOE EUR CREER RES S 50 DM wv CIT rrr a1 ik UNS TP rrr 52 PIE EEE E E E 8S E T E E E es 53 A SC aaauaqieen dada dedsdende cesses rete do Ede ae es 55 D EDIDI AE E E Garces Enad ont dad ud alea vnus ddui dad diotsad 37 EWOL JUS axeeuusdsdcitues 93Jed4Edd S KE bd eq a Il E LES 58 LESE IBN uaec
35. DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide 52 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW div Combinational Divider DW div Combinational Divider e Parameterized word lengths e Unsigned and signed two s complement data operation e Remainder or modulus as second output 2 quotient e remainder m divide by O0 Table 1 Pin Description Pin Name Width Direction Function a a width bit s Input Dividend b b width bit s Input Divisor quotient a width bit s Output Quotient remainder b width bit s Output Remainder modulus divide by 0 bit Output Indicates if b equals 0 Table 2 Parameter Description Parameter Values Description a width 22 Word length of a Default None b
36. Dynamic Fair Among Equal Scheme e Parameterizable number of clients e Programmable mask for all clients e Park feature default grant when no requests are pending e Lock feature ability to lock the currently granted client Registered unregistered outputs request mask lock priority grant grant index locked granted parked clk rst_n Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Active low input reset request n bit s Input Input request from clients priority nx p_width Input Priority vector from the clients of the arbiter bit s lock n bit s Input Active high signal to lock the grant to the current request By setting lock i 1 the arbiter is locked to the request 7 if it is currently granted For lock 7 0 the lock on the arbiter is removed mask n bit s Input Active high input to mask specific clients By setting mask 7 1 request 7 is masked For mask i 0 the mask on the request 7 is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to park index granted 1 bit Output Flag to indicate that arbiter has issued a grant to one of the clients locked 1 bit Output Flags that the arbiter is locked by a client grant n bit s Output Grant output grant index ceil log5n bit s Output Index of the reques
37. E Load Store Queues m Program arit or PU Y a D Cache Controller o Auxiliary FPU Branch Unit o Processor Instruction Unit Target gt 4K DCR Bus e Unit Address t BHT s p 4SICC IrDA APU Dispatch Dispatch Cache Trace 9 o v Y D Firewire Interrupt p GPR PR and 2 Integer File Integer ME 9 Load Timers o vA Yni DEP SmartCard O MAC P P OPB Momt Master PowerPC 440 OPB Slave DesignWare IBM PowerPC 440 Block Diagram Also see the following web page for additional information http www synopsys com products designware starip ibm_powerpc html April 2003 Synopsys Inc 301 DesignWare IP Family Quick Reference Guide DW V850E Star V850E Processor Core from NEC DW V850E Star V850E Processor Core from NEC Sta 5 The NEC V850E is a highly configurable fully synthesizable RISC architecture microcontroller The V850E core is ideal for applications that require high performance low cost and minimum power consumption In addition the excellent processing horsepower of this 32 bit processor is perfect for new applications that need more than a 16 bit processor can provide Other features include the following e Fully compatible with V850EI instruction set e Supports 32 bit and 16 bit instruction formats e 64 MB linear address program memory space e 4 GB linear address data memory space e V850E1 CPU o Five stage pipel
38. External or External or Module RX j Internal Internal sir in RX Memory TX Memory Receive Data Sync eae Serial Interface Parameter pelk Selected sclk Cross Clock Opticon Locku Latches 247 DesignWare IP Family Quick Reference Guide DW apb wdt APB Watchdog Timer DW apb wdt APB Watchdog Timer Configurable APB data bus widths of 8 16 and 32 bits Configurable watchdog counter width of 16 to 32 bits Counter counts down from a pre set value to zero to indicate the Occurrence of a timeout Programmable timeout range period The option of hard coding this value during configuration is available to reduce the register requirements After a timeout the DW apb wdt can perform one of the following operations o Generate a system reset o First generate an interrupt and if this is not cleared by the time a second timeout occurs then generate a system reset Component version ID register DW apb wdt Optional external clock enable signal to control the rate at which the counter counts Optional dual programmable timeout period used when the duration waited for the first kick is different than that required for subsequent kicks The option of hard coding these values is available Programmable and hard coded reset pulse length Prevention of accidental restart of the DW apb wdt counter Prevention of accidental disabling of the DW apb wdt Optional support for Pause mode wi
39. Family Quick Reference Guide dwcore 1394 ohci Synthesizable IEEE 1394 OHCI Link dwcore 1394 ohci Synthesizable IEEE 1394 OHCI Link Corg The Synopsys DesignWare IEEE 1394 OpenHCI OHCI Link enables PC host computers to communicate with 1394 peripherals via a standardized 13942 2000 physical layer PHY and a common software driver set The IEEE 1394 OHCI can be used in a standalone ASIC or it can be integrated into an ASIC with a PHY targeted for high volume cost effective 1394 applications The IP technology is well suited for computer multimedia and mass storage applications requiring high bandwidth Other features include the following e Complete IEEE 1394a 2000 and 1394 e 2 KB asynchronous transmit FIFO OpenHCI standard rev 1 0 support e 4 KB receive FIFO e 100 200 400 Mbps bus speeds e VSIA compliant Virtual Component e Eight isochronous transmit and eight Interface VCI for application isochronous receive DMA channels backend e 128 byte zero wait state burst e OHCI driver support in Microsoft operations Windows 986 second edition e 2 KB isochronous transmit FIFO e Verilog source code The dwcore 1394 ohci data sheet is available at http www synopsys com products designware docs ds c dwcore 1394 ohci pdf 292 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Cor dwcore 1394 cphy S Synthesizable IEEE 1394 Cable PHY dwcore 1394 cphy Synthesizable IEEE 1394 Cable PHY The Synopsys
40. Generator and Checker e Generates parity for given input data datain parity e Supports even and odd parity selectable via a parameter e Supports variable word widths e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function datain width bit s Input Input data word to check or generate parity parity 1 bit Output Generated parity Table 2 Parameter Description Parameter Values Description width 1 to 256 Defines the width of the input bus par type Oor 1 Defines the type of parity a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model Design Ware Foundation April 2003 Synopsys Inc 183 DesignWare IP Family Quick Reference Guide 00000000 odin Data Integrity Coding Group Overview 1010110001 Data Integrity Coding Group Overview The Coding Group consists of a set of IP that encode and or decode data for use in data communications and data storage applications Currently the 8B 10B coding scheme used in standard data communication and networking protocols such as Gigabit Ethernet and Fiber Channel is embodied in the Coding Group IP 184 Synopsys Inc April 2003 00000000 11111111 odin DesignWare IP Family Quick Reference Guide DW 8b10b dec
41. Get Descriptor command can be decoded by the application Supports vendor specific commands e Maintains address pointer for endpoint O transaction The dwcore usb2 device data sheet 1s available at 288 http www synopsys com products designware docs ds c dwcore usb2 device pdf Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Co dwcore usb2 phy S Synthesizable USB 2 0 Transceiver Macrocell Interface PHY dwcore_usb2_phy Synthesizable USB 2 0 Transceiver Macrocell Interface PHY The USB 2 PHY includes all the required logical geometric and physical design files to implement USB 2 0 capability in a System on Chip SOC design and fabricate the design in the designated foundry The initial foundry process for the USB 2 PHY is the 0 18 micron CMOS digital logic process Alternatively design services are available for porting the USB 2 PHY to other semiconductor processes The USB 2 PHY integrates high speed mixed signal custom CMOS circuitry compliant with the UTMI Specification version 1 04 supports the USB 2 0 480 Mbps protocol and data rate and is backward compatible to the USB 1 1 legacy protocol at 1 5 Mbps and 12 Mbps Other features include the following e Complete mixed signal physical layer e Designed for minimal power PHY for single chip USB 2 0 dissipation for low power and applications bus powered devices e USB 2 0 Transceiver Macrocell e Low power design enables host Interface UTMI
42. Guide DW inc gray Gray Incrementer DW inc gray Gray Incrementer e Parameterized word length e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Gray coded input data ci 1 bit Input Carry in Z width bit s Output Gray coded output data Table 2 Parameter Description Parameter Values Description width 21 Input word length Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cla Carry lookahead synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 61 DesignWare IP Family Quick Reference Guide DWO02 mac Multiplier Accumulator DWO02 mac Multiplier Accumulator e Parameterized word length e Unsigned and signed two s complement data operation Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand C A_width B_width bit s Input Addend TC 1 bit Input Two s complem
43. I O Standards listing 20 VMT Models overview 256 April 2003 Synopsys Inc Index 317 Index DesignWare IP Family Quick Reference Guide 318 Synopsys Inc April 2003
44. Implementation Name Function License Required mx2 Implement using 2 1 multiplexers only DesignWare Foundation mx2i Implement using 2 1 inverting DesignWare Foundation multiplexers and 2 1 multiplexers mx4 Implement using 4 1 and 2 1 DesignWare Foundation multiplexers mx8 Implement using 8 1 4 1 and 2 1 DesignWare Foundation multiplexers a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 43 DesignWare IP Family Quick Reference Guide DWO1 bsh Barrel Shifter 44 Table 4 Sample Parameter Values A width SH width 1 2 1 3 4 2 5 8 3 9 16 4 17 32 5 33 64 6 Synopsys Inc April 2003 DW01 cmp2 2 Function Comparator e Parameterized word length e Unsigned and signed two s complement data DesignWare IP Family Quick Reference Guide DWO01 cmp2 2 Function Comparator operation Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data LEQ 1 bit Input Output condition control TC 1 bit Input Two s complement control 0 unsigned 1 signed LT_LE 1 bit Output Less than less than or equal output c
45. Input Parallel input shift n bit Input Shift enable active low load n bit Input Parallel load enable active low p out length bit s Output Shift register parallel output Table 2 Parameter Description Parameter Values Description length 21 Length of shifter Table 3 Synthesis Implementations License Required Implementation Name Function str Synthesis model DesignWare Foundation 116 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO4 shad reg Shadow and Multibit Register DW04 shad reg Shadow and Multibit Register e Captures the state of system registers dynamically during system operation e Serial access on shadow register to scan out the state of captured data e Constructed with multibit flip flop cells where possible can be used as a simple non shadowed multibit register e Parameterized width and number of registers one or two datain Sys out SI shad out Table 1 Pin Description Pin Name Width Direction Function datain width bit s Input Data input driving the input to the system register sys_clk 1 bit Input Clock that samples the system register positive edge triggered shad_clk 1 bit Input Signal that clocks the output of the system register into the shadow register positive edge triggered reset 1 bit Input Asynchronous reset signal that cl
46. Memory Management Unit with separate instruction and data micro TLB s Extensive hardware debug facilities incorporated into the IEEE 1149 1 JTAG port Timer facilities o 64 bit time base o Decrementer with auto reload capability o Fixed interval timer FIT o Watchdog timer with critical interrupt and or auto reset Multiple core interfaces defined by IBM s CoreConnect on chip system architecture o Processor local bus PLB interfaces o Auxiliary Processor Unit APU Port o Device Control Register DCR interface for independent access to on chip control registers JTAG Debug Reset and Trace interfaces Clock and power management CPM interface External interrupt controller EIC interface O O O O O O O O 0 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW IBM440 DesignWare IBM PowerPC 440 Star IP Core NN M NR DC DMA OCM Memory LCD OPB Controller Controller Controller Controller Bridge J i1 1 i Processor Local Bus PLB gt 2C Instruction Cache Data Cache PLB With Parity With Parity PLB iss Floating i f y FU I Cache Controller M entry with gt
47. Meta Software ModelAccess ModelExpress ModelTools PathBlazer PathMill Physical Compiler PowerArc PowerMill PrimeTime RailMill Raphael RapidScript Saber SmartLogic SNUG SolvNet Stream Driven Simulator Superlog System Compiler TestBench Manager Testify TetraMAX TimeMill TMA VERA and VeriasHDL are registered trademarks of Synopsys Inc Trademarks TV Active Parasitics AFGen Apollo Apollo Il Apollo DPII Apollo GA ApolloGAIl Astro Astro Rail Astro Xtalk Aurora AvanTestchip AvanWaves BCView Behavioral Compiler BOA BRT Cedar ChipPlanner Circuit Analysis Columbia Columbia CE Comet 3D Cosmos Cosmos SE CosmosLE Cosmos Scope Cyclelink Davinci DC Expert DC Expert Plus DC Professional DC Ultra DC Ultra Plus Design Advisor Design Analyzer DesignerHDL DesignTime DFM Workbench DFT Compiler SoCBIST Direct RTL Direct Silicon Access DW8051 DWPCI Dynamic Macromodeling Dynamic Model Switcher ECL Compiler ECO Compiler EDAnavigator Encore Encore PQ Evaccess ExpressModel Floorplan Manager Formal Model Checker FormalVera FoundryModel FPGA Compiler Il FPGA Express Frame Compiler Frameway Gatran HDL Advisor HDL Compiler Hercules Hercules Explorer Hercules ll Hierarchical Optimization Technology High Performance Option HotPlace HSPICE Link Integrator Interactive Waveform Viewer iQBus Jupiter Jupiter DP JupiterXT JupiterXT ASIC JVXtreme Liberty Libra Passport Library Compiler L
48. Operator Inference assign PROD mult tc IN1 IN2 Function Inference DWOl1 mult 8 8 Ul A B TC PRODUCT Instantiation Details about inference and instantiation in VHDL and Verilog are in the following directory SSYNOPSYS dw examples Synthesizing DesignWare Building Block IP Design Compiler automatically selects the best implementation for combinational DesignWare Building Block IP You can also force Design Compiler to select the implementation of your choice either by adding Synopsys Compiler directives or by using the following commands dc shell set dont use standard sldb DWO1 add rpl dc shell set implementation clf add 68 Simulating DesignWare Building Block IP Synopsys VCS simulator uses the default setup file while simulating DesignWare Building Block IP Use the following options to simulate DesignWare Building Block IP with a Verilog simulator y SSYNOPSYS dw sim ver libext v April 2003 Synopsys Inc 29 Chapter 2 DesignWare Library Synthesizable IP DesignWare IP Family Quick Reference Guide Technical Support or Further Information For information on how to contact us refer to Getting Help on page 13 Building Block IP in FPGA Compiler Il QuickStart The following topics provide the basic information to get started using the DesignWare Building Block IP with FPGA Compiler II Updating FPGA Compiler Il FPGA Compiler II versions 3 2 and later support insta
49. Pin Name Width Direction Function data width bit s Input Input data load 1 bit Input Input load data to counter active low cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 bit Input Asynchronous reset active low count width bit s Output Output count bus Table 2 Parameter Description Parameter Values Description width 1 to 50 Word length of counter a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 215 DesignWare IP Family Quick Reference Guide DWOS3 Ifsr updn fo LFSR Up Down Counter DWOS3 Ifsr updn LFSR Up Down Counter e High speed area efficient e Pseudorandom sequence generator tercnt e Up down count control e Asynchronous reset clk reset e Terminal count flag Table 1 Pin Description Pin Name Width Direction Function updn bit Input Input high for count up and low for count down cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 bit Input Asynchronous reset active low count width bit s Output Output count bus tercnt 1 bit Output Output terminal count Table 2 Parameter Description Parameter Values Description width 2
50. Point Adder Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand or fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Input data B e f 1 bits Input Input data Z e f 1 bits Output Sum of A B STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point numbers A B and Z f 2 to 253 bits Word length of fraction field of floating point numbers A B and Z arch 0 Architecture implementation a The DW add fp component contains only one architecture therefore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Required arch Synthesis model DesignWare Foundation 106 Synopsys Inc April 2003 1 293307 DesignWare IP Family Quick Reference Guide x 2 182 2 2v Y DW cmp fp Floating Point Comparator Module Compiler Only DW cmp fp Floating Point Comparator Module Compiler Only e The precision format is
51. RC RON 207 DWO BU UND a wn ea OE VR PLE REAE QE DEC ee eaten QE ex ERO 208 DYOS DIUI SQUE oo tae se kra demus ens dd y dior d ha ux VERA 209 DNUS bitr decode ueoxexos S43 XsXAXRRAa ERRARE KERR 210 DOS La ixueebqSserddub ERGO REPE IE PR EE ad PES ERU RE ERE 211 DAOS Mer JOMO Lais 1 993 90 479 X EE HORAE R A 213 ONOS 4 o Ae 214 OSO IE MOM dua4uasa rELes QE PER pe KP xRTEORSE RO eSQERdd E rihi 215 DVDS UE updi ote cere atn na ere rog o o Rod RR AR Sones 216 DWO updn GU iosuosusas ask 4s bE 4S 8484 0d es PERS RATER G 217 6 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Contents Application Specific Interface Overview elleleeees 218 DO CUS ossesrdm esos En dp dob dicho a edo i odeur hn d 219 Application Specific Control Logic 2issaesss aea E ERG RE RR RAS 221 EN IDE M ee ee ee ee ee ee ee ee ee ERE 222 a pe ba OHS ee Bows Ea Rea bee eae OES 224 DW amer Tois Ss ne cide nee cys aped wactr ado eU a eh evo RSs 226 EUM a uoa PERSA RUECE eu SLE RSEN eed Gwe E REqEQE DERE E edis 228 DSP Library Overview dosaascrdhEnmadeerzeds pa dun arx reed REST ERA 230 GTECH Library Overview sorrsireisanrt dart A RA ERA RARO ARR 230 AMBA On Chip Bus Logic and Peripherals IP 0 000020 ee 231 DOO 3p she exire edidpitoqd RR 4 pii eR E S 232 anm mu Am r Hos 234 EV Sh e oes ea VER e TRE ERE qd XV REPAIR OE P 235 Ew abb M uisesadded Gase nA RP deb Side afpidib
52. Reference Guide DW_rambist Memory Built In Self Test e Default sequence or run time selection of individual test e Improved test execution time through reduced memory read write cycles each access to synchronous memory occurs in one clock cycle e Configuration of Mode Register reset value to provide easy power up tests e Higher speed clock frequency Supported Memories e Synchronous and asynchronous SRAM e Asymmetrical pipelining support up to four stages e Support for 32 memories per BIST controller e Highly configurable memory interface to suit most types of memories Supported Memory Configurations e True at speed testing of memories in parallel e Memory array test via single port and multi port e Ability to enable disable testing of individual memories e Multiple controller scheduling e Support for incomplete address space Synopsys Inc 251 DesignWare IP Family Quick Reference Guide DW rambist Memory Built In Self Test Design for test Design for Verifiability e Configuration of shadow logic capture e Sample script for scan chain creation and connection part of example design verification of very large system level interconnection e Integration with DFT Compiler BSD TAP Serial or Parallel I F Compiler and TetraMax Mao Coy e simulation_mode signal to provide configurations and to quickly check DW_rambist monitor_bus BIST I F
53. Required str Synthesis model DesignWare Foundation 204 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide M DWO1 mux any Universal Multiplexer DWO01 mux any Universal Multiplexer e Parameterized word lengths e Saves coding time by eliminating the need to A MUX code muxes explicitly SEL Increases design abstraction e Uses 8 to 1 muxes where possible Table 1 Pin Description Pin Name Width Direction Function A A width Input Data input bus SEL SEL width Input Select input MUX MUX width Output Multiplexed data out Table 2 Parameter Description Parameter Values Description A width 21 Word length of A SEL width 21 Word length of SEL MUX width 2 A SEL 1 x MUX width 1 downto SEL MUX width Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 205 DesignWare IP Family Quick Reference Guide DWO1 prienc Priority Encoder DWO1 prienc Priority Encoder e Parameterized word length e Inferable using a function call Table 1 Pin Description L5 A INDEX Pin Name Width Direction Function A A width Input Input data INDEX INDEX width Output Binary encoded output data Table 2 Parameter Description Parameter Values Description A
54. SIO Verification IP Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 261 Listing of FlexModels DesignWare IP Family Quick Reference Guide DesignWare FlexModels FlexModels are binary simulation models that represent the bus functionality of microprocessors cores digital signal processors and bus interfaces FlexModels utilize the industry standard SWIFT interface to communicate with simulators FlexModels have the following features e Built with a cycle accurate core and a controllable timing shell so that you can run the model in function only mode for higher performance or with timing mode enabled when you need to check delays You can switch between timing modes dynamically during simulation using simple commands in your testbench e Feature multiple different control mechanisms You can coordinate model behavior with simulation events synchronize different command processes and control several FlexModels simultaneously using a single command stream e Allow you to use different command sources You can send commands to FlexModels using processes in a Verilog or VHDL testbench a C program or a VERA testbench You can switch between the HDL or VERA testbench and a compiled C program as the source for commands Listing of FlexModels Table 1 lists the FlexModels that are available including a brief description Table 1 Listing of FlexModels
55. Specification enumeration of an unpowered device compliant e Sea wall and decoupling structures e 8 bit interface at 60 MHz operation reduce on chip noise and 16 bit interface at 30 MHz e Suspend Resume and Remote operation chip Wakeup mode support e Compatible with the Synopsys USB e USB 2 0 test mode support 2 0 Device and Host components l a e Additional built in analog testability e USB 2 0 Device automatic switching features DEDWESIL E a TIUS e USB Implementers Forum certified e Host Device automatic switching between full high and low speed modes The dwcore usb2 phy data sheet is available at http www synopsys com products designware docs ds c dwcore usb2 phy pdf April 2003 Synopsys Inc 289 DesignWare IP Family Quick Reference Guide dwcore 1394 avlink Synthesizable IEEE 1394 AVLink dwcore 1394 avlink Synthesizable IEEE 1394 AVLink Corg The Synopsys DesignWare IEEE 1394 AV Link intellectual property IP is a set of highly configurable blocks that implements complete 1394 interface functions tailored to support audio visual AV oriented IEC 61883 applications Configured through our RapidScript utility this device can also be optimized to act as a generic 1394 device controller Therefore AVLink can be effectively used in a wide range of applications such as digital still cameras video conferencing cameras printers scanners digital audio devices electronic musical instruments digital VCRs
56. There are thousands of pre verified memory models to choose from supporting over 25 memory vendors The models integrate with the simulator through the de facto industry standard SWIFT interface which is supported by all Synopsys simulators and by all other major simulator vendors Smarter verification is achieved by using the models debugging utilities You can search through the thousands of memory models using the memory model search capabilities offered as part of DesignWare Memory Central at http www synopsys com memorycentral DesignWare Memory Models provide the following capabilities in your simulation environment e Dynamically managed 4 state 0 1 X or U data storage Models efficiently allocate workstation memory for all designs whether low density or memory intensive e Word storage address ranges from 0 to 2N 1 where N is an integer in the range 2 through 64 Supports integral word widths from 1 through 2048 bits e Unloading of a range of memory addresses Unloaded memory addresses return to the uninitialized state and return the workstation memory associated with those addresses e Loading memory contents from or dumping memory contents to external files e Continuous control of model messages e Creation and deletion of traces on a range of addresses When the simulation run performs a read or a write operation on a traced address the model causes an event and provides the memory instance address data an
57. Users Guide b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide 92 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO2 tree Wallace Tree Compressor DWO2 tree Wallace Tree Compressor e Parameterized word length Table 1 Pin Description Pin Name Width Direction Function INPUT num inputs X input width bit s Input Input vector OUTO input width bit s Output Partial sum OUTI input width bit s Output Partial sum Table 2 Parameter Description Parameter Values Description num inputs 21 Number of inputs input width 21 Word length of OUTO and OUTI Table 3 Synthesis Implementations Implementation Name Function License Required wallace Wallace tree synthesis model DesignWare Foundation April 2003 Synopsys Inc 93 DesignWare IP Family Quick Reference Guide SIN b COS Datapath Trigonometric Overview Datapath Trigonometric Overview The trigonometric IP many of which are inferred are applicable to ASIC or FPGA designs These IP
58. VTRs and storage devices Other features include the following Silicon proven IEEE 1394 Link Layer Controller for both audio visual A V and non A V applications Support for common isochronous packet CIP headers time stamping and padded zeros for A V data transactions IEEE 1394 1995 and 1394a 2000 specification compliance IEC 61883 requirement for A V data streaming compliance Supports 100 200 400 Mbps data rates Full link layer implementation e Asynchronous isochronous and PHY packet transmit and receive operations Cycle master and node controller capability Automatic isochronous resource manager detection Automatic acknowledge packet generation for received asynchronous packets Automatic 32 bit CRC generation and error detection interface Flexible 32 bit Virtual Component Interface VCI for host asynchronous and isochronous FIFO interface with burst and non burst access modes Multi speed concatenated isochronous packet support Configurable number of isochronous transmit receive channels Status reporting by extensive maskable interrupt register set Supports inbound and outbound single phase retry protocol RapidScript custom IP configuration Verilog source code e Optional 1394 simulation models The dwcore 1394 avlink data sheet is available at 290 http www synopsys com products designware docs ds c dwcore 1394 avlink pdf Synopsys Inc April 2003 C eg DesignWare IP Fa
59. be a whole Clock rate in MHz number Default 1 baud rate 300 600 1200 2400 Sets the baud rate of the UART 4800 9600 or 19200 Default 19200 mark parity Oor 1 Sets the fixed value of the parity bit from Default 1 the UART transmitter April 2003 Synopsys Inc 219 DesignWare IP Family Quick Reference Guide DW debugger On Chip ASCII Debugger Table 3 Synthesis Implementations 220 Implementation Name Function License Required str Synthesis model DesignWare Foundation Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Application Specific Control Logic Application Specific Control Logic The Control Logic IP consist of a family of arbiters DesignWare Building Block IP of the arbiter family are distinguished from each other primarily by the arbitration scheme they embody The IP DW arbiter sp and DW arbiter dp are based on the static fixed priority scheme and dynamically programmable priority scheme respectively Each of these IP has multiple architectural implementations optimized for timing or area The number of clients connected to the arbiter is parametrizable from 2 to 32 Other features like parking and locking are available through parameter selection April 2003 Synopsys Inc 221 DesignWare IP Family Quick Reference Guide DW arbiter 2t Two Tier Arbiter with Dynamic Fair Among Equal Scheme DW arbiter 2t Two Tier Arbiter with
60. bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low diag n 1 bit Input Diagnostic control active low ae_level ceil logo depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost_empty flag is active af_thresh ceil logo depth bit s Input Almost full threshold the number of words stored in the FIFO at or above which the almost_full flag is active data_in width bit s Input FIFO data to push empty 1 bit Output FIFO empty output active high almost empty 1 bit Output FIFO almost empty output active high half full 1 bit Output FIFO half full output active high April 2003 Synopsys Inc 131 DesignWare IP Family Quick Reference Guide DW fifo s1 df Synchronous Single Clock FIFO with Dynamic Flags n Table 1 Pin Description Continued Pin Name Width Direction Function almost full 1 bit Output FIFO almost full output active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high data_out width bit s Output FIFO data to pop Table 2 Parameter Description Parameter Values Description width 1 to 256 Width of data in and data_out buses Default 8 depth 2 to 256 Number of memory elements used in FIFO Default 4 err_mode 0 to 2 Error mode Default 0 0 underflow overflow and pointer latched checki
61. bit s Output Index of the requesting client that has been currently granted or the client designated by park index in park mode 224 Synopsys Inc April 2003 DW arbiter dp 3 DesignWare IP Family Quick Reference Guide Arbiter with Dynamic Priority Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 park mode Oor 1 park mode 1 includes logic to enable parking when no clients Default are requesting and E park mode 0 contains no logic for parking park index 0 to nd Index of the client used for parking Default 0 output mode Oor 1 output mode 1 includes registers at the outputs Default 1 output_mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Required cla Carry look ahead synthesis model DesignWare Foundation clas Carry look ahead select synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 225 DesignWare IP Family Quick Reference Guide DW arbiter fcfs Arbiter with First Come First Served Priority Scheme DW arbiter
62. bits Configurable system address width of 32 or 64 bits Configuration of system endianness Big or Little Endian Optional Arbiter Slave Interface Programmable arbitration scheme Weighted Token Programmable or Fixed priority Fair Among Equals Arbitration for up to 15 masters Optional Bus decoder External debug mode signal Synopsys Inc Individual grant signals for each master Support for split burst and locked transfers Optional support for early burst termination Configurable support for termination of undefined length bursts by masters of equal or higher priority Configurable or hardcoded priority assignments to masters Disabling of masters and protection against self disable Optional support for AMBA memory remap feature Optional support for pausing of the system Contiguous and non contiguous memory allocation options for slaves Component version ID register April 2003 DesignWare IP Family Quick Reference Guide DW ahb Advanced High performance Bus DW ahb Parameterizable Parameterizable Master Ports Arbiter Slave Ports Master 1 Slave 1 Master 2 Slave2 Address and control MUX Write data MUX Master i lt gt Slavej Read data MUX i upto 15 j upto 15 Decoder internal The DesignWare DW_ahb Data
63. control and memory FIFO RAM Controller Controller Diffused Latch or or Metal Programmable Flip Flop RAM Based RAM on chip or off chip For shallow FIFOs lt 256 bits For large FIFOs gt 256 bits Self contained RAM storage array Interfaces to dual port static RAMs Figure 1 Memory FIFOs and FIFO Controllers All FIFOs and Controllers support full empty and programmable flag logic Programmable flag logic may be statically or dynamically programmed When statically programmed the threshold comparison value is hardwired at synthesis compile time When dynamically programmed it may be changed during FIFO operation April 2003 Synopsys Inc 119 DesignWare IP Family Quick Reference Guide DW asymfifo s1 df AIT Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag DW_asymfifo_s1 df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag e Fully registered synchronous flag output ports Pe data out ata in e D flip flop based memory array for high testability Posh ram full e All operations execute in a single clock cycle Be level D u e FIFO empty half full and full flags af thresh almost full e Parameterized asymmetric input and output bit widths flush n half full must be integer multiple relationship diag n almost empty e Word integrity flag for empty data in width lt data out width S clk eb error e Flushing out partial word for data_in_width lt data_out_width
64. count a 3 e put p data in push empty e Single clock cycle push and pop operations push req n Push ae push hf push af push full push error e Parameterized word width P clk push e Parameterized word depth e Separate status flags for each clock system pop req n data out e FIFO empty half full and full flags pop word count pop empty e Parameterized almost full and almost empty flag P clk pop pop a thresholds pop hf e FIFO push error overflow and pop error underflow MT pop Tu flags pop error test ret n Table 1 Pin Description Pin Name Width Direction Function clk push 1 bit Input Input clock for push interface clk pop 1 bit Input Input clock for pop interface rst n 1 bit Input Reset input active low push req n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low data_in width bit s Input FIFO data to push push empty 1 bit Output FIFO empty output flag synchronous to cIk push active high push ae l bit Output FIFO almost empty output flag synchronous to clk push active high determined by push ae lvl parameter push hf l bit Output FIFO half full output flag synchronous to clk push active high push af l bit Output FIFO almost full output flag synchronous to clk push active high determined by push af lvl parameter push full I bit Output FIFO full output flag synchronous to clk push active high
65. count e Asynchronous and synchronous reset e Count enable Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset asynchronous active low init_n 1 bit Input Reset synchronous active low load_n 1 bit Input Enable data load to counter active low data width bit s Input Counter load input cen 1 bit Input Count enable active high count width bit s Output Gray coded counter output Table 2 Parameter Description Parameter Values Description width 21 Word length of counter Table 3 Synthesis Implementations Implementation Name Function rpl cla License Required Ripple carry synthesis model DesignWare Foundation Carry lookahead synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 50 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO1 csa Carry Save Adder DWO01 csa Carry Save Adder e Parameterized word length e Carry in and carry out signals Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data b width b
66. in width That is either data in width K x data out width or data out width K x data in width where K is an integer depth 2 to 256 Number of memory elements used in the FIFO addr width ceil log gt depth ae level 1 to depth 1 Almost empty level the number of words in the FIFO at or below which the almost empty flag is active af level 1 to depth 1 Almost full level the number of empty memory locations in the FIFO at which the almost full flag is active err mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 to 3 Reset mode Default 1 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory byte_order Oor 1 Order of send receive bytes or subword subword lt 8 bits gt Default 0 subword within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position valid for data in width data out width April 2003 Synopsys Inc 125 DesignWare IP Family Quick Reference Guide DW asymfifo s1 sf AT Asymmetric I O Synchronous Single Clock FIFO with Static Flags Table 3 Synthesis Implementations Implementation Name Function License Re
67. industry proven DesignWare 1394 Cable Physical Layer CPHY enables devices to interface with the 1394 serial bus The 1394 CPHY is a synthesizable RTL design that provides all the necessary features to implement the complete IEEE 1394a specification for the digital portion of the cable PHY The CPHY can be combined with an analog PHY and used in a standalone ASIC or it can be integrated into an ASIC with a Link Layer controller CPHY is well suited for multimedia and mass storage applications requiring high bandwidth and is suitable for a wide range of applications from basic low cost devices 1 port to sophisticated high performance ASICS up to 16 ports Other features include the following e Complete IEEE 1394a support e Supports Link On LPS protocol e Supports 100 200 400 Mbps bus e RapidScript configuration utility for speeds design customization e Configurable number of ports 1 to 16 Simple silicon proven interface to e Synthesis scripts e mixed signal analog circuitry e e Verilog source code Approximately 14K gates 3 port e Supports suspend resume protocol Proves ASIC applications The dwcore 1394 cphy data sheet is available at http www synopsys com products designware docs ds c dwcore 1394 cphy pdf April 2003 Synopsys Inc 293 DesignWare IP Family Quick Reference Guide dwcore jvxtreme Or es Synthesizable Java Acceleration dwcore jvxtreme Synthesizable Java Acceleration The Synopsy nex
68. information http www synopsys com products designware starip smsc_ip html April 2003 Synopsys Inc 311 DesignWare IP Family Quick Reference Guide SMSC USB 2 0 PHY Standard Microsystems Corporation GT3100 USB 2 0 PHY Star IP 312 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Index Index A ahb act montitor vmt 258 ahb bus vmt 258 ahb master vmt 258 ahb monitor vmt 258 ahb slave vmt 258 AMBA On Chip Bus IP listing 17 apb master vmt 260 apb monitor vmt 260 apb slave vmt 260 B Board and FPGA Verification IP listing 21 Building Block IP application specific control logic 221 application specific interface 218 data integrity 176 data integrity coding overview 184 datapath arithmetic overview 33 datapath floating point overview 105 datapath sequential 98 datapath trigonometric overview 94 datapath generator overview 32 logic combinational overview 202 logic sequential overview 207 memory asynchronous RAMs 163 memory FIFO overview 119 memory registers 113 memory stacks 171 overview 27 test JTAG overview 189 C Cores overview 271 D datapath generator overview 32 Design Compiler 29 April 2003 DesignWare Building Block IP See also Building Block IP DesignWare Core dwcore blueiq devkit 275 DesignWare Cores overview 271 DesignWare DSP Library 230 DesignWare FlexModels listing 262 DesignWare FlexModels overview 262 DesignWare Found
69. is available at http www synopsys com products designware pciexpress html 282 Synopsys Inc April 2003 April 2003 C eg dwcore usb otg e The data buffer configurable through RapidScript sizes FIFOs to specification allowing further performance enhancement and gate count minimization e Flexible endpoint configuration allows designers to design one chip for each product or single chips with alternate configurations that can be used in many products such as a printer chip or a chip for use in printers scanners and multifunction printer fax scanners e The testbench proves the configured controller s USB and OTG compliance Tests are designed for straightforward porting to an integrated design The dwcore_usb_otg data sheet is available at DesignWare IP Family Quick Reference Guide dwcore usb otg Synthesizable USB 2 0 Full Speed On The Go Controller Subsystem Synthesizable USB 2 0 Full Speed On The Go Controller Subsystem Extensive USB compliance and interoperability testing in simulation Hardware state machines maximize Full Speed USB transaction throughput as compared to slower software based solutions Configurable data buffer and threshold options enable gate count fine tuning and performance maximization in one or many designs Flexible endpoint configuration allows one design for multiple applications or for only one application Testbench is designed to enable porting of tests
70. p 8 Sy p g push error 1 bit Output FIFO push error overrun output flag synchronous to clk push active high April 2003 Synopsys Inc 135 DesignWare IP Family Quick Reference Guide DW fifo s2 sf Synchronous Dual Clock FIFO with Static Flags n Table 1 Pin Description Continued Pin Name Width Direction Function pop empty 1 bit Output FIFO empty P output flag synchronous to clk_pop active high pop ae l bit Output FIFO almost empty output flag synchronous to clk pop active high determined by pop ae lvl parameter pop hf l bit Output FIFO half full output flag synchronous to clk pop active high pop af l bit Output FIFO almost full output flag synchronous to clk pop active high determined by pop af lvl parameter pop full l bit Output FIFO full output flag synchronous to clk pop active high pop error 1 bit Output FIFO pop error underrun output flag synchronous to clk_pop active high data_out width bit s Output FIFO data to pop a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description width 1 to 256 Width of the data_in and data_out buses Default 8 depth 4 to 256 Number of words that can be stored in FIFO Default 8 push ae lvl 1 to depthd Almost empty level for the push ae output port the
71. parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand or fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Floating point number B e f 1 bits Input Floating point number ALTB 1 bit Output High when A is less than B AGTB 1 bit Output High when A is greater than B AEQB 1 bit Output High when A is equal to B Z0 e f 1 bits Output Optional floating point output of e f 1 bits Zl e f 1 bits Output Optional floating point output of e f 1 bits STATUSO optional 8 bits Output Status flags corresponding to Z0 STATUS optional 8 bits Output Status flags corresponding to Z1 MAX optional 1 bit Input Determines Min Max operation of ZO and Z1 Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent field of floating point number A f 2 to 256 bits Word length of fraction field of floating point number A arch 0 Architecture implementation a This component contains only one architecture Therefore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Required archO Synthesis mod
72. provide you with the best architecture for your design goals All components have a parameterized word length 202 Synopsys Inc April 2003 L5 DWO1 binenc Binary Encoder DesignWare IP Family Quick Reference Guide e Parameterized word length e Inferable using a function call DWO1 binenc Binary Encoder A ADDR Table 1 Pin Description Pin Name Width Direction Function A A width Input Input data ADDR ADDR width Output Binary encoded output data Table 2 Parameter Description Parameter Values Description A width 21 Word length of input A ADDR width gt ceil loga A width 1 Word length of output ADDR Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 203 DesignWare IP Family Quick Reference Guide DWO1 decode TE Decoder DW01_decode Decoder e Parameterized word length e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function A width Input Binary input data B qwidth Output Decoded output data Table 2 Parameter Description Parameter Values Description width 21 Word length of input A is width Word length of output B is 24 Table 3 Synthesis Implementations Implementation Name Function License
73. ram rw s dff 161 DWO2 prod suml 77 DW ram rw s lat 162 DWO2 sin 96 DW rambist 251 DW02_sincos 97 DW shifter 83 DWO2 sum 92 DW sqrt 87 DWO2 tree 93 DW sqrt pipe 88 DWO3 bictr dcnto 208 DW sqrt seq 103 DWO3 bictr decode 210 DW square 85 DWO3 bictr scnto 209 DW squarep 86 DWO3 Ifsr dento 213 DW stack 172 DWO3 Ifsr load 215 DW stackctl 174 DW03_lfsr_scnto 214 DW tap 190 DWO3 Ifsr updn 216 DW tap uc 192 DWO3 pipe reg 114 DW TriCorel 306 DWO3 reg s pl 115 DW V850E Star 302 DWO3 shftreg 116 DWOI absval 34 DWO3 updn ctr 217 DWOI add 35 DWO4 par gen 183 DWOI addsub 37 DW OA shad reg 117 DWOI ash 41 DW8051 254 DWOI binenc 203 dwcore 1394 avlink 290 DWOI bsh 43 dwcore 1394 cphy 293 DWO1_cmp2 45 dwcore_1394_device 291 DWO1_cmp6 46 dwcore 1394 ohci 292 April 2003 Synopsys Inc 315 Index dwcore blueiq 273 dwcore blueiq devkit 275 dwcore ethernet 276 dwcore ethernet sub 277 dwcore gig ethernet 278 dwcore gig ethernet sub 279 dwcore jpeg codec 295 dwcore jpeg2 codec 296 dwcore_jpeg2_encod 297 dwcore_jvxtreme 294 dwcore pci 280 dwcore pci express 282 dwcore pcix 281 dwcore usb otg 283 dwcore usbl device 284 dwcore usbl host 285 dwcore usbl hub 286 dwcore usb2 device 288 dwcore usb2 host 287 dwcore usb2 phy 289 DWMM See also Memory IP E enethub fx 264 enetrx fx 264 enettx fx 264 Ethernet Verification Models 264 F FlexModels 262 Foundation Library See also Building Block IP FPGA Comp
74. relationship with data out width That is either data in width K x data out width or data out width K x data in width where K is an integer data out width 1to256 Width of the data out bus data out width must be in an integer multiple relationship with data in width That is either data in width K x data out width or data out width 2 K x data in width where K is an integer depth 2 to 22 Number of memory elements used in the FIFO addr_width ceil log gt depth err_mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 1 0 asynchronous reset 1 synchronous reset byte_order 0 or 1 Order of bytes or subword Default 0 4bword lt 8 bits gt subword within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cll Partial carry look ahead model Design Ware Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more de
75. synopsys com products designware docs ds c dwcore usb2 host pdf April 2003 Synopsys Inc 287 DesignWare IP Family Quick Reference Guide dwcore usb2 device Synthesizable USB 2 0 Device Controller dwcore usb2 device Synthesizable USB 2 0 Device Controller Corg The USB 2 0 Device Controller UDC20 features industry standard interfaces that easily integrate the USB 2 0 transceiver and application logic The RapidScript utility builds the core and test environment in source code for the targeted application Other features include the following Certified High Speed USB 2 0 Device Controller Supports 480 Mbps 12 Mbps and 1 5 Mbps devices Supports USB 2 0 Transceiver Macrocell Interface UTMI Available in Verilog Interfaces to any application bus Supports Virtual Component Interface VCI to application logic Optional support for AHB and DMA engine Programmable number of endpoints Flexible endpoint configuration with Windows 98 ME 2000 XP Host Class Drivers Process independent and portable Fully synchronous design e Microprocessor and tool independent Backward USB 1 1 Specification compliant Supports up to 16 configurations 16 interfaces per configuration and 16 alternate settings per interface Easily configurable endpoint configuration Supports chirp sequences Supports Ping protocol Suspend resume logic provided Supports UTMI compliant and Philips ISP1501 Peripheral Transceivers
76. tdo si 1 bit Input Serial path from the previous boundary scan cell data_in l bit Input Input data from system input pin SO 1 bit Output Serial path to the next boundary scan cell data_out l bit Output Output data Table 2 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Test IEEE STD 1149 1 198 Synopsys Inc April 2003 DW bc 5 Boundary Scan Cell Type BC 5 DesignWare IP Family Quick Reference Guide DW bc 5 Boundary Scan Cell Type BC 5 e IEEE Standard 1149 1 compliant e Synchronous or asynchronous scan cells with respect to tck e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ data in data out si SO intest mode shift dr capture en update en update clk pcapture clk Table 1 Pin Description Pin Name Width Direction Function capture clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en l bit Input Enable for data clocked into the capture stage active low update_en l bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mod
77. that used to share the e Three speeds C bus o Standard mode 100 Kb s o Fast mode 400 Kb s o High speed mode 3 4 Mb s e Transmit and receive buffers e Interrupt or polled mode operation e Simple software interface consistent e Master or slave IC operation with DesignWare APB peripherals e 7 or 10 bit addressing e Digital filter for the received SDA and e Component version ID register SOL lines DW apb i2c APB Slave Interface Ic Master Slave Interrupts RX Filter Pc Debug Clock Generator The DesignWare DW apb i2c Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 239 DesignWare IP Family Quick Reference Guide DW apb ictl APB Interrupt Controller DW apb ictl APB Interrupt Controller e 2 to 64 IRQ normal interrupt sources e Priority filtering optional e to 8 FIQ fast interrupt sources e Masking optional e Scan mode e Yectored mtean optional e Component version ID register SEEDS e Component version ID register gt Note DW_apb_ictl is an exact replacement for the original component DW_amba_ictl name change only DW apb ictl IRQ Generation Interrupt FIQ Registers Generation Vector Generation amp Masking The DesignWare DW_apb_ictl Databook is available at http www synopsys com products designware docs
78. width 21 Word length of input A INDEX_width 2 ceil logo A width 1 Word length of output INDEX Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 206 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide i Logic Sequential Overview The sequential components consist of high performance counters many with either dynamic or static count to flags Components in this category have multiple architectures for each function architecturally optimized for either performance or area to provide you with the best architecture for your design goals All components have a parameterized word length Logic Sequential Overview April 2003 Synopsys Inc 207 DesignWare IP Family Quick Reference Guide DWO3 bictr dcnto Up Down Binary Counter with Dynamic Count to Flag DWO3 bictr dcnto Up Down Binary Counter with Dynamic Count to Flag 208 Parameterized word length Terminal count flag for count to comparison Pin programmable count to value Up down count control Asynchronous reset Synchronous counter load Synchronous count enable data count count to up dn tercnt cen load clk reset Table 1 Pin Description Pin Name Width Direction Fun
79. 0000e04ede0e8ereessanerws 94 n 10 5 COS rer 95 DEW ANC Lasscideixet ezebtee bebe n einem eed qx qx xd et dide 96 EDU DUE x be tee i x De Renae o1 n dear uie ben ee Saba EE 97 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Contents Datapath Sequential Overview Luces aec aids AO OR ERROR KC IO RO ERROR 98 EE ME oen aoo hn 573 E E EE E IE E busters eens 99 DW MME SO os x56 e kw 5x5 649 428 HERS AREATA X Sd FC ARR HOA 101 EN NM EH ee es ee ee ee RD e ao nd 103 Datapath Floating Point Overview roseese serae x ERREUR RR Rm 105 ED adl DS ivedudnsene Rv ene ces 0 dm CU S pini ap eR XR ape cael 106 LU OUID JR ias acad dE dE A E PORRO 3 OE REC EROR E DIOE ed 107 EM UD calc vb EA SUR EE Had Rub dd ud doi dtaudt s dpi dam uiis 108 EN ID ouesud dodzd dRAuREESERDUXANAETARARESJ dq RR A EE HOS 110 DS IUD oebetedesaerdtWwateseseteubcietadAaLesexddesc ades 111 o oM TP r HR 112 Memory ROMO Louaedckr wee ord O9 See RO a Ab Rc C UR b ORS on eRe as 4 113 OSOS BD I LiosSquaASeEKERS QE EKREA DUR E qua Pd iS dedi rid d Rd 114 ESUS SE A IL Losub sxt tss dona edidi ved tna died d e Ras 115 De AME 224455 G5 Ta RRAAKRAXASUPESEANASEASIAWARNN RU REN HOA 116 EVO a ee re ee FEE HR EC RR d E ORG ld 117 Memory FIFO Overview Luosssesereenxtado ka n RO A CRORAEOORAHRORA RR RA 119 ON sl dU aoouexkesaucisa dm E adhue aede XR ded eii 120 LUV BOUE UE ME oua t revera Ee dx Cice d d Oed eid 123 AE aosadesuqetnndonesbesatesra
80. 02 EM CLIBBN mataa s ado dbi OP VORHER n och Hoa t 304 U ANI e 0 TEE 306 DW MIPMBB isauw dudxaudseuaesadan duducixadikdsasdeddecd edes 308 Mezoe Init fase BEBIOSE cbse des oxo oak d de oa Rn Rr RR ERE ERA 310 SOC VOR CPE ausaodeazuexs3daxsa Uxsazuxasdat Ul ee need ed 311 INE G eREEARPROREREREEK XERRXIRRKRRRRZATEARRARSEMEPZRQE EEE CP PERRA 313 April 2003 Synopsys Inc 9 Contents DesignWare IP Family Quick Reference Guide 10 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide About This Manual Manual Overview Preface This manual is a brief overview of the DesignWare Library of synthesizable and verification IP For detailed product information refer to individual product databooks and manuals mentioned in the following chapters Manual Overview This manual contains the following chapters Preface Chapter 1 Overview Chapter 2 DesignWare Library Synthesizable IP Chapter 3 DesignWare Library Verification IP Chapter 4 DesignWare Cores Chapter 5 DesignWare Star IP April 2003 Describes the manual and typographical conventions and symbols tells how to get technical assistance Contains an overview and general description of the DesignWare Library product offering Contains a brief description of each DesignWare Library Synthesizable IP Describes the available DesignWare Library verification models Contains a brief description of each DesignWare Co
81. 1 Pin Description Pin Name Width Direction Function d width bit s Input Input data bus clk 1 bit Input Clock reset_N 1 bit Input Synchronous reset enable 1 bit Input Enables all operations q width bi s Output Output data bus Table 2 Parameter Description Parameter Values Description width 1 to 31 Width of d and q buses Default 8 reset_value 0 to 24 when width 31 Resets to a constant 0 when width 2 32 Default 0 Table 3 Synthesis Implementations Implementation Name Function License Required str Single bit flip flops synthesis model DesignWare Components mbstr Multiple bit flip flops synthesis model DesignWare Components a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 115 DesignWare IP Family Quick Reference Guide DWOS3 shftreg Shift Register DWOS3 shftreg Shift Register e Parameterized word length e Active low shift enable e Active low load enable load n shift n Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock s in 1 bit Input Serial shift input pin length bit s
82. 1 bit Output FIFO almost empty output flag synchronous to clk pop active high determined by pop ae lvl parameter pop hf 1 bit Output FIFO half full output flag synchronous to clk_pop active high pop_af 1 bit Output FIFO almost full output flag synchronous to clk pop active high determined by pop af lvl parameter April 2003 Synopsys Inc 145 DesignWare IP Family Quick Reference Guide DW asymfifoctl s2 sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags n Table 1 Pin Description Continued Pin Name Width Direction Function pop full 1 bit Output FIFO s RAM full output flag excluding the input buffer of FIFO controller for case data in width lt data out width synchronous to clk pop active high pop error 1 bit Output FIFO pop error underrun output flag synchronous to clk pop active high wr data max data in width Output FIFO controller output data to RAM data out width bit s wr addr ceil logs depth bit s Output Address output to write port of RAM rd addr ceil log depth bit s Output Address output to read port of RAM data out data out width bit s Output FIFO data to pop a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description data
83. 1 bit Input Clock PRODUCT A_width B width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_width gt 1 For csa architecture A width B_width x48 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation str Booth recoded Wallace tree synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A_width and B width lt A8 bits as it has no area benefit beyond 48 bits April 2003 Synopsys Inc 69 DesignWare IP Family Quick Reference Guide DWO02 mult 5 stage Five Stage Pipelined Multiplier DWO02 mult 5 stage Five Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation Five stage pipelined architecture Automatic pipeline retiming e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Mu
84. 2 3z compliant GMII Corg Supports CSMA CD protocol in Half Duplex mode Supports 1 Gbps frame bursting in Half Duplex mode Supports IEEE 802 3 flow control for Full Duplex operation Automatic Pause Frame generation in Full Duplex mode Back pressure support in Half Duplex mode Supports magic frame and wake on LAN frame detection Ethernet frame statistic support for Management Information Base MIB Automatic CRC and pad generation Options to insert CRC and pad for Transmit frames Options for automatic pad stripping for Receive frames Supports jumbo framesSupports internal loopback on the GMII MII interface for debugging Supports a variety of flexible address filtering modes Separate 32 bit status returned for transmit and receive frames The dwcore gig ethernet data sheet is available at http www synopsys com products designware docs ds c dwcore gig ethernet pdf 278 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Cor dwcore gig ethernet sub S Synthesizable Gigabit Ethernet Subsystem dwcore gig ethernet sub Synthesizable Gigabit Ethernet Subsystem The Synopsys DesignWare Gigabit Ethernet MAC GMAC Subsystem enables the host to communicate data using the Gigabit Ethernet protocol IEEE 802 3 The GMAC Subsystem is composed of three main layers the Gigabit Ethernet Media Access Controller GMAC the MAC Transaction Layer MTL and the MAC DMA Controller MDC Other features in
85. 2003 Synopsys Inc 91 DesignWare IP Family Quick Reference Guide DWO2 sum Vector Adder DW02 sum Vector Adder e Parameterized number of inputs INPUT SUM m e Parameterized word length e Multiple synthesis implementations Table 1 Pin Description Pin Name Width Direction Function INPUT num_inputs X input_width bit s Input Concatenated input data SUM input_width bit s Output Sum Table 2 Parameter Description Parameter Values Description num_inputs 21 Number of inputs input width 2 Word length of inputs and sum Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation clsa MC inside DW DesignWare Foundation carry look ahead select fastcla gt MC inside DW fast carry look ahead DesignWare Foundation mccsa MC inside DW carry select DesignWare Foundation pprefixP MC inside DW flexible parallel prefix DesignWare Foundation ripple MC inside DW ripple carry DesignWare Foundation rpl Ripple carry synthesis model DesignWare Foundation wall Wallace tree synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP
86. 256 bits Word length of fraction field of floating point number A arch 0 Architecture implementation Table 3 Synthesis Implementations Implementation Name Function License Required archO Synthesis model DesignWare Foundation April 2003 Synopsys Inc 111 DesignWare IP Family Quick Reference Guide DW mult fp Floating Point Multiplier Module Compiler Only DW mult fp Floating Point Multiplier Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand or fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Multiplier B e f 1 bits Input Multiplicand Z e f 1 bits Output Product of A x B STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point numbers A B and Z f 2 to 253 bits Word length of fraction field of floating point numbers A B and Z arch 0 Architecture implementation a This component contains only one architecture therfore the arch parameter should be s
87. 4 bit version number Default 0 April 2003 Synopsys Inc 193 DesignWare IP Family Quick Reference Guide DW tap uc TAP Controller with USERCODE support Table 2 Parameter Description Continued Parameter Values Description part 0 to 65535 16 bit part number Default 0 man num 0 to 2047 11 bit JEDEC manufacturer identity code man num z 127 Default 0 sync mode Oor 1 Determines whether the bypass device identification and Default 0 instruction registers are synchronous with respect to tck 0 asynchronous synchronous Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 194 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW bc 1 Boundary Scan Cell Type BC 1 DW bc 1 Boundary Scan Cell Type BC 1 e IEEE Standard 1149 1 compliant data in data out s i so e Synchronous or asynchronous scan cells with respect to tck si mode e Supports the standard instructions EXTEST SAMPLE shift dr PRELOAD and BYPASS T e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ capture en update en gt update clk pcapture clk Table 1 Pin Description Pin Name Width Direction Function capture clk 1 bit Input Clocks data into the capture stage update clk 1 bit Input Clo
88. Architecture implementation 1 MC divider architecture 1 producing 1 bit per iteration 2 MC divider ROM based architecture producing 1 bit per iteration 3 MC divider architecture 3 producing 2 bits per iteration Divider operands can be of any width for archz1 and arch 3 but should be less than 10 bits for arch 2 For details see divide function of Module Compiler reference manual Table 3 Synthesis Implementations Implementation Name Function License Required archO Synthesis model Design Ware Foundation April 2003 Synopsys Inc 109 DesignWare IP Family Quick Reference Guide DW fit2i fp Floating Point to Integer Converter Module Compiler Only DW flt2i fp Floating Point to Integer Converter Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits a FU e Significand or fractional part of the floating point number can STATUS range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Floating point number Z 3 to 512 bits Output Two s complement integer number STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description P
89. Building Block IP in FPGA Compiler II versions 3 2 and later by direct instantiation For example In Verilog DWO2 mult inst_A_width inst B width Ul A inst A B inst B TC inst TC PRODUCT inst PRODUCT In VHDL Ul DWO2 mult generic map A width gt inst A width B width gt inst B width port map A gt inst A B gt inst B TC gt inst TC PRODUCT inst PRODUCT Currently FPGA Compiler II does not support inference of DesignWare Building Block IP Synthesizing DesignWare Building Block IP in FPGA Compiler Il FPGA Compiler II versions 3 2 and later automatically select the implementation for the chosen FPGA technology It understands and takes advantage of vendor specific architectures to provide the best quality of results QoR for most DesignWare Building Block IP Note that some DesignWare Building Block IP are implemented using generic gates but improvement in QoR can be expected in future releases Simulating DesignWare Building Block IP FPGA Compiler II has the ability to generate synthesized netlists in Verilog and VHDL Just right click on the optimized chip select Export Netlist and then select Verilog or VHDL as the desired output format The netlists generated are structural netlists which can be simulated with VCS or VSS Further Information For further information on using DesignWare in FPGA Compiler II e Visit our Web site at http www synopsys com products fpga fpga_solution ht
90. Control Mode Auto CTS and Auto RTS Support for any serial data baud rate subject to the serial clock frequency as follows baud rate serial clock frequency 16 divisor Extended diagnostic Loopback Mode allows testing more Modem Control and Auto Flow Control features April 2003 DesignWare IP Family Quick Reference Guide DW apb uart AMBA APB Universal Asynchronous Receiver Transmitter DW apb uart Two Clock Domains Note Generalized internal diagram not all signals are shown here The DesignWare DW apb uart Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc Modem Status Level Sync Module lg Modem Registers Status and APB Control Intertace n lt q p ontro j gt and Module Shean pus Character Registers Timeout 1 Level Sync jag m Character TX Module Timeout FIFO p gt Detection Control Character MEM MODE Timeout RBR Level Sync Baud Clock Module Generator RX Character FIFO Timeout e Control Clear MEM MODE Data Sync 9 7 TX THR Module sir out n Transmit Data Sync 1 sin
91. Controller Table 1 Pin Description Continued Pin Name Width Direction Function sync capture en bit Output Enable for synchronous capture sync update dr 1 bit Output Enables updating new data in synchronous mode Table 2 Parameter Description Parameter Values Description width 2 to 32 Width of instruction register Default None id Oor 1 Determines whether the device identification register is Default 0 present 0 not present 1 present version 0 to 15 4 bit version number Default 0 part 0 to 65535 16 bit part number Default 0 man num 0 to 2047 11 bit JEDEC manufacturer identity code man num z 127 Default 0 sync mode Oorl Determines whether the bypass device identification and Default 0 instruction registers are synchronous with respect to tck 0 asynchronous synchronous Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 191 DesignWare IP Family Quick Reference Guide DW tap uc TAP Controller with USERCODE support DW tap uc TAP Controller with USERCODE support e IEEE Standard 1149 1 compliant e Synchronous or asynchronous registers with respect to t ck e Provides interface to supports the standard IEEE 1149 1 and optional instructions e Optional use of device identification register and IDCODE i
92. DesignWare IP Family Quick Reference Guide Cor dwcore_ethernet_sub S Synthesizable Ethernet Subsystem dwcore ethernet sub Synthesizable Ethernet Subsystem The Synopsys DesignWare Ethernet Media Access Controller MAC Subsystem enables the host to communicate data using the Ethernet protocol IEEE 802 3 The subsystem is composed of three main layers the DMA the Transaction Layer Interface TLI and the Media Access Controller MAC The Synopsy Ethernet MAC Subsystem enables Ethernet functionality for switch NIC and system on chip applications Ethernet MAC implements more than the traditional functionality of standard MACs including a MAC Host Station Management Address Check and Control Status Register CSR blocks These additional blocks provide the higher level system functionality that is traditionally implemented in firmware or using separate products With these additional capabilities the Ethernet MAC simplifies the system implementation effort Features include the following e Generic 32 bit single channel DMA e Supports 10 100 Mbps data transfer engine rates e Available in PVCI or AHB Interface e IEEE 802 3 Media Independent e Uses descriptor architecture for Interface MII RMII and Serial minimum CPU intervention Interface e Supports programmable interrupt Supports Full and Half duplex options for different operational operations conditions e Virtual LAN VLAN support e Includes two dual port FIFOs one for
93. Inc April 2003 DesignWare IP Family Quick Reference Guide DW gray2bin Gray to Binary Converter DW gray2bin Gray to Binary Converter e Parameterized word length e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function g width bit s Input Gray coded input data b width bit s Output Binary coded output data Table 2 Parameter Description Parameter Values Description width 21 Input word length Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model Design Ware Foundation cla Carry lookahead synthesis model DesignWare Foundation April 2003 Synopsys Inc 57 DesignWare IP Family DWO1 inc Incrementer DWO1 inc Incrementer Quick Reference Guide e Parameterized word length Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data SUM width bit s Output Increment A 41 Table 2 Parameter Description Parameter Values Description width 2l Word length of A and SUM Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare Foundatio
94. Input Almost full threshold the number of words stored in the FIFO at or above which the almost full flag is active w en 1 bit Output Write enable output for write port of RAM active low empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output active high asserted when FIFO level xae level half full 1 bit Output FIFO half full output active high almost full 1 bit Output FIFO almost full output active high asserted when FIFO level af_thresh full 1 bit Output FIFO full output active high ram_full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part_wd 1 bit Output Partial word active high for data_in_width lt data_out_width only otherwise tied low wr data max data in width Output FIFO controller output data to RAM data out width bit s wr addr ceil logo depth bit s Output Address output to write port of RAM rd addr ceil log depth bit s Output Address output to read port of RAM data out data out width bit s Output FIFO data to pop April 2003 Synopsys Inc 139 DesignWare IP Family Quick Reference Guide DW asymfifoctl s1 df Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic F n Table 2 Parameter Description Parameter Values Description data in width 1to256 Width of the data in bus data in width must be in an integer multiple
95. Input Two s complement 0 unsigned 1 signed SUM SUM width bit s Output Sum of products Table 2 Parameter Description Parameter Values Description A width 21 Word length of A B width 2 Word length of B SUM width 21 Word length of C and output SUM a For nbw implementation A_width B_width 36 Due to concern of implementation selection run time a limitation is set for A_width and B_width Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model Design Ware Foundation wall Booth recoded Wallace tree synthesis Design Ware Foundation model nbw Non Booth recoded Wallace tree Design Ware Foundation synthesis model April 2003 Synopsys Inc 77 DesignWare IP Family Quick Reference Guide DWO2 prod sum1 Multiplier Adder a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b In most cases the wall implementation generates both faster and smaller circuits for medium to large sized multipliers c In most cases the nbw implementation generates both faster and smaller circuits for small to medium sized multipliers 78 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW pr
96. PCI X initiators at the pin and bus cycle levels Initiates read and write cycles pcislave fx PCI PCI X Responds to cycles initiated by the pcimaster_fx model or by the user s PCI master device pcimonitor_fx PCI PCI X Monitors logs and arbitrates activity on the PCI or PCI X bus usbhost_fz USB 1 1 2 0 Emulates the functions and timing of the Universal Serial Bus USB Host utmi_fz USB 2 0 Intel USB 2 0 Transceiver Macrocell Interface UTMI specifications from Intel USB 2 0 interface between the Serial Interface Engine SIE and Macrocell Support Models sync8_fx Synopsys 8 bit synchronization model The individual DesignWare FlexModel databooks can be found with each model at http www synopsys com products designware ipdir The FlexModel User s Manual is available at http www synopsys com products designware docs April 2003 Synopsys Inc 263 DesignWare IP Family Quick Reference Guide Ethernet Verification Models A enettx fx enetrx fx enethub fx rmiirs fx S Ethernet Verification Models enettx fx enetrx_fx enethub fx rmiirs fx The Synopys Ethernet Model set consists of four models and system testbenches in VERA Verilog C and VHDL e enettx fx The enettx fx FlexModel is the bus functional model BFM for the Transmitter part of the IEEE 802 3 Ethernet MAC This model is also compatible with the 802 3ab specification e enetrx fx The enetrx fx FlexModel is the bus functional mod
97. Parameter Values Function width 21 Word length of A and SUM Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare Foundation clsa MC inside DW carry look ahead select DesignWare Foundation csa MC inside DW carry select DesignWare Foundation fastcla MC inside DW fast carry look ahead DesignWare Foundation pprefix MC inside DW flexible parallel prefix DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 59 DesignWare IP Family Quick Reference Guide DWO1 incdec Incrementer Decrementer b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide 60 Synopsys Inc April 2003 DesignWare IP Family Quick Reference
98. SCSI Fibre Channel Gigabit Ethernet and graphics Other features include the following PCI X 1 0a compliant Dual Address Cycles DAC Host Bridge functionality Message Signaled Interrupts MSI PCI 2 3 compliant External EEPROM support 32 bit or 64 bit PCI X bus path Comprehensive Test Environment 64 bit application data path Device Under Test linkable to the test Supports 0 133 MHz PCI X bus PEE Supports up to 32 outstanding delayed split transactions e RapidScript parameterized configuration for fast customization e Synthesizable Verilog source code The dwcore_pcix data sheet is available at http www synopsys com products designware docs ds c dwcore_pcix pdf April 2003 Synopsys Inc 281 DesignWare IP Family Quick Reference Guide dwcore pci express Synthesizable PCI Express Core dwcore pci express Synthesizable PCI Express Core eg The DesignWare PCI Express Implementation IP Core is a synthesizable end point solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following e Designed to PCI Express specification e PIPE PHY connectivity for end point solution e Lane and polarity reversal in the e Configurable lane width x1 x4 125 physical and link layer MHz x1 x8 250MHz e Early detection of framing errors e Flexible buffer configuration e 64 bit bi directional application bus More information
99. SYNOPSYS DesignWare IP Family Quick Reference Guide DesignWare IP Family Quick Reference Guide Copyright Notice and Proprietary Information Copyright 2003 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys AMPS Arcadia C Level Design C2HDL C2V C2VHDL Calaveras Algorithm CoCentric COSSAP CSim DelayMill Design Compiler DesignPower DesignWare Device Model Builder Enterprise EPIC Formality HSPICE Hypermodel I InSpecs in Sync LEDA MAST Meta
100. Ware Building Block IP User Guide 40 Synopsys Inc April 2003 DWO01 ash Arithmetic Shifter e Parameterized word length DesignWare IP Family Quick Reference Guide DWO1 ash Arithmetic Shifter A e Parameterized shift coefficient width DATA TC B e Inferable using a function call SH SH TC Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Input data DATA TC 1 bit Input Data two s complement control 0 unsigned 1 signed SH SH width bit s Input Shift control SH_TC 1 bit Input Shift two s complement control 0 unsigned 1 signed B A_width bit s Output Output data Table 2 Parameter Description Parameter Values Description A_width 22 Word length of A and B SH_width 21 Word length of SH Table 3 Synthesis Implementations Implementation Name Function License Required mx2 Implement using 2 1 multiplexers only DesignWare Foundation mx2i Implement using 2 1 inverting multiplexers DesignWare Foundation and 2 1 multiplexers mx4 Implement using 4 1 and 2 1 multiplexers DesignWare Foundation mx8 Implement using 8 1 4 1 and 2 1 multiplexers Design Ware Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For
101. Web at http www synopsys com products designware ipdir SmartModel Features e Support for Windows allowing you to view and change internal register values e Consistent SWIFT interface across most simulators e Simulation efficient behavorial level models e Industry standard as well as configurable timing behavior SmartModel Types There are two basic types of SmartModels e Full functional Models FFMs simulate the complete range of device behavior e Bus Functional Models BFMs simulate all device bus cycles FlexModels are a type of BFM in the SmartModel Library which you can control using Verilog VHDL VERA or C For some devices more than one type of model may be available but these are exceptions not the general rule For detailed information about a specific SmartModel including FlexModels refer to the model s datasheet For an overview of the FlexModels see DesignWare FlexModels on page 262 268 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide SmartModel Timing Definitions SmartModel Timing Definitions All SmartModels have at least one timing version To see what timing versions are available for a particular model use the Browser tool to display a list of timing versions for that model If you need a timing version that is not supplied with the library or if you want to back annotate customized delays into the model s simulation you can create a custom timing version
102. XO OUR DW ram rw a lat RAM Asynchronous Single Port RAM Latch Based 01101001 DW ram rw a lat Asynchronous Single Port RAM Latch Based e Parameterized word depth rw addr e Parameterized data width data in data out e Asynchronous static memory cs n e Parameterized reset implementation wr n ret n Table 1 Pin Description Pin Name Width Direction Function rst n bit Input Reset active low cs n bit Input Chip select active low wr n bit Input Write enable active low rw addr ceil logo depth bit s Input Address bus data in data width bit s Input Input data bus data out data width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data width 1to 256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width rst mode Oor 1 Determines if the rst n input is used 0 2 rst n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model Design Ware Foundation 170 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Memory Stacks Memory Stacks This section documents the various memory stacks found in the library of DesignWare Building Block IP April 2003 Synopsys Inc 171 De
103. _0 2 o E Shadow Capture 0 o 4 o lt n o 3 le NL debug so oO 3 o iB z o lt e o 3 P number of ports 0 lt P lt 3 Mode Register width 1 0 z N Memory number 0 lt N lt 31 2 Address width 1 0 ___ conditional blocks 3 Number of Memories 1 0 gt conditional signals These signals are for simulation purposes and should be left unconnected at the system level More information on the DW rambist MacroCell can be found at 252 http www synopsys com products designware docs ds i DW rambist ds Synopsys Inc bist mode debug o ut N mode reg out mode reg so pdf April 2003 DesignWare IP Family Quick Reference Guide Microprocessors Microcontroller Cores Synthesizable RTL of these cores are available through the Star IP Program The components detailed in this section contain a page reference in the following table For more information on this program visit http www synopsys com designware Component Name Component Description DW IBM440 Available Q2 03 PowerPC 440 Microprocessor Core from IBM page 300 DW VS850E Star V850E Processor Core from NEC page 302 DW C166S 16 bit Processor from Infineon page 304 DW TriCorel TriCorel 32 Bit Processor Core from Infineon page 306 DW MIPSAKE Processor Core Family from MIPS page 308 DWS8051 8 bit Microcontroller See page
104. able RTL of these cores are available through the Star IP Program which has more information at http www synopsys com designware star ip html April 2003 Synopsys Inc 18 Chapter 1 Overview DesignWare IP Family Quick Reference Guide Memory IP Component Name Component Description Component Type DesignWare Memory DesignWare contains thousands of pre verified Verification Models Models memory models with over 10 000 devices from more than 25 vendors page 267 DW memctl Memory Controller page 250 Synthesizable RTL DW rambist DesignWare Memory BIST solution page 251 Synthesizable RTL DW Memory Building DesignWare Building Block IP contains many Synthesizable RTL Block IP memory related IP page 113 To view the complete DesignWare memory portfolio refer to the following http www synopsys com memorycentral Verification Models of Bus and I O Standards Component Name Component Description Component Type AMBA See AMBA On Chip Bus on page 17 Verification Models pciexpress_vmt PCI Express Verification Model enettx_fx enetrx_fx enethub fx rmiirs fx IEEE 802 3 Transmitter Receiver RMII Interface Reconciliation Sublayer page 264 Verification Models pcimaster fx pcislave fx and pcimonitor fx PCI PCI X 32 bit and 64 bit 33 Mhz and 66 Mhz PCI Simulation Model and Test Suite page 265 Verification Models usbhost
105. able early burst termination and undefined length burst termination AHB Master e Data width 8 1024 bits e Single or burst transfers e Burst rebuild capability AMBA Compliance Test bench e Constrained random test transactions ACT e Compare with expected data Note This component is licensed separately from the DesignWare Library or DesignWare AHB Slave Verification Library e OK Error Retry or Split responses e Configurable memory fill patterns 2 0 specification e FIFO memory at any memory location Generates compliance certificate as e Constrained random test transactions defined by ARM and Synopsys e Multiple components may be certified AHB Monitor during a single session e Cycle based or transaction based event Programmable coverage to reflect user monitoring configuration e Protocol checking e Re certifies in customer environment e Incremental coverage reporting without requiring an ACT license e Coverage API enables self checking from the test bench e Checks for protocol violations 258 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AMBA AHB Models ahb master vmt ahb slave vmt ahb monitor vmt ahb bus vmt Dummy Default M Decoder aster Slave Read AHB iuc Lind AHB Master 1 4
106. aeebeseeets er h FPeLeRddwbqeddsbesetdewbp amp ece ts 59 EU Mg BENE Loon diues id oe bk Oe Fah ddr di qr RAO HERE RE dEU HERO ened 61 ENDE DUUM ra oun dob e 9 ee E93 dob ud rss bs debel E ER e ap REOR ed 62 ERU UM Sh es Saeed oo ee oe didus ee dd Pd 63 oie ca ban ened E see de ede PT E 64 DWO MUI 00564 ecvs a5 645408 HH EES HS 4G KES HOR KEE ES AR REE ES ES 66 EO SUE erir dride enrddubpsdeseievieatestect 67 DWO SUN 3 Stage 6 cake 8s ge Qe xd AD AHORA AO CR e pin 68 BWO nad J HABE SisekwsqusdinaS dE ehe d iR Xx doe dci ies 69 EVO AquUE 1 3988 AoeHrd gesexrdekean Qe bxiiaiadeen de ucc eser es 70 DEUS GUN D SO uuodiegaq texdesute pid d d renasci uber ate E 71 EM AH A uuecsduasquia AnRFRESQSERSATESSREGyiImeRatetmitsfoh ds 72 LN Te eaiet pert 4 RPEREE Rd RE be REX ECRIRE ERES 73 DIU prod SUME 1qduredours ur IIR IHRER EIER EE ERREUR ERR eg 75 DOS pod snil nk os ees os EROR oS wh Ud OE CR CB et i T7 OY prod I cence teks eh hanes eee eee chee es 79 DWOIL co PPM T TP paw enees 81 Ino Ao AMMMT c c m 83 LEY SOUS cise ec weiter PLE OC RERO KE daba aeo gy d Ce yd dor 85 DA o rrr 86 D A e e m m 87 LU SOn ppe a esea nie RI PCR KORCER OR GIG neien CE OA GIHEE RH ER 88 ENDE UB ocak bre ie vod ale Rd TR ERA RP S dpi p Xd dp 90 DCL BUDE ixcixegqe4LAERERDASRUAR RANA ARAM i E RRIXGerUba qid nds 92 t o2loNGI Terr 93 Datapath Trigonometric Overview 244 c
107. al output condition NE 1 bit Output Not equal output condition Table 2 Parameter Description Parameter Values Description width 21 Word length of A and B Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none bk Brent Kung synthesis model DesignWare Foundation cla Carry look ahead synthesis model DesignWare Foundation 46 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO1 cmp6 6 Function Comparator a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 47 DesignWare IP Family Quick Reference Guide DW cmp dx Duplex Comparator DW cmp dx Duplex Comparator e Selectable single full width Compare or two smaller width Compare operations duplex e Selectable number system unsigned or two s complement e Parameterized full word width e Parameterized partial word width allowing for asymmetric partial width operations e Separate flags for Less Than Equal To and Greater Than e Two sets of flags for duplex operation Table 1 Pin Description Pin Name Width Direction F
108. all primitive polynomials include the coefficient which is equivalent to x9 c CCITT CRC16 polynomial is X9 X EXP thus poly_coef0 2 25 1 4129 Table 3 Synthesis Implementations Implementation Name Implementation License Required str Synthesis model DesignWare Foundation 180 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW ecc Error Checking and Correction DW ecc Error Checking and Correction e Parameterized word width e Generates check bits for new data written and corrects corrupt data for read and read modify write cycles e Supports scrubbing e Flags to indicate if an error was detected and if the error is not correctable e Flow through architecture for speed and flexibility gen err detect correct n err multpl datain dataout chkin chkout e Error syndrome output for error logging Table 1 Pin Description Pin Name Width Direction Function gen 1 bit Input Suppresses correction in write mode gen 1 and generates check bits Enables correction when in read mode gen 0 and correct n is asserted low correct n 1 bit Input Enables correction of correctable words active low datain width bits Input Input data word to check check mode or data from which check bits are generated generate mode chkin chkbits bits Input Check bits input for error analysis on read err detect
109. amily Quick Reference Guide 100111001 RAM DW_ram_rw_a_dff 01101001 Asynchronous Single Port RAM Flip Flop Based DW ram rw a dff Asynchronous Single Port RAM Flip Flop Based e Parameterized word depth rw addr data in e Parameterized data width es n e Asynchronous static memory wr Qe eur e Parameterized reset implementation test mode e High testability using DFT Compiler gt test clk rst n Table 1 Pin Description Pin Name Width Direction Function rst n 1 bit Input Reset active low cs n bit Input Chip select active low wr n 1 bit Input Write enable active low test_mode 1 bit Input Enables test_clk test_clk 1 bit Input Test clock to capture data during test_mode rw_addr ceil log depth bit s Input Address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines if the rst_n input is used 0 rst_n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 169 DesignWare IP Family Quick Reference Guide
110. ar l bit Input Special character control input LOW for data characters HIGH for special characters data_in 8 bits Input Input for 8 bit data character to be encoded unbal 1 bit Output Unbalanced code character indicator LOW for balanced HIGH for unbalanced Table 2 Parameter Description Parameter Values Description k28 5 mode 0 or 1 Special Character subset control parameter Default 0 0 for all special characters available 1 for only K28 5 available when k char HIGH regardless of the value on data in Table 3 Synthesis Implementations Implementation Name Function License Required rtl Synthesis model DesignWare Foundation 188 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Test JTAG Overview Test JTAG Overview The JTAG IP consist of a set of boundary scan IP The boundary scan IP include a parameterized Test Access Port TAP controller DW tap plus a set of boundary scan cells that you can use to implement a custom IEEE 1149 1 boundary scan test solution for your ASIC April 2003 Synopsys Inc 189 DesignWare IP Family Quick Reference Guide DW tap TAP Controller DW tap TAP Controller e IEEE Standard 1149 1 compliant e Synchronous or asynchronous registers with respect to tck e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instruct
111. arameter Values Description e 3 to 31 bits Word length of biased exponent of floating point number A f 2 to 256 bits Word length of fraction field of floating point number A arch 0 Architecture implementation a This component contains only one architecture Therefore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Required archO Synthesis model DesignWare Foundation 110 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW i2flt fp Integer to Floating Point Converter Module Compiler DW i2flt fp Integer to Floating Point Converter Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits I2FLT e Significand or fractional part of the floating point number can STATUS range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A 3 to 512 bits Input Two s compliment integer number Z e f 1 bits Output Floating point number STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point number A f 2 to
112. are docs ds c dwcore blueiq devkit pdf April 2003 Synopsys Inc 275 DesignWare IP Family Quick Reference Guide dwcore ethernet On es Synthesizable Ethernet Core dwcore ethernet Synthesizable Ethernet Core The Synopsys DesignWare Media Access Controller MAC includes the MAC and the MAC test environment Features include the following e Collision detection in Half Duplex e IEEE 802 3 Media Independent mode CSMA CD protocol Interface MID Reduced Media e Support for control frames in Independent Interface RMII and Full Duplex mode IEEE 802 3x General Purpose Serial Interface e Preamble generation and removal Supports Full and Half Duplex e Automatic 32 bit CRC generation and iD checking e Virtual LAN VLAN support e Configurable counters for remote e Power management supports remote monitoring RMON monitoring RMON LAN and magic k e Complete status for transmission and pac u reception packets e RapidScript utility for fast RMON customization e Optimized for switching routing network interface card and system on chip applications e Compliant with IEEE 802 3 and 802 3u specifications e Supports 10 100 Mbps data transfer rates Virtual Component Interface VCI Available in Verilog Application integration support Approximately 12K gates The dwcore ethernet data sheet is available at http www synopsys com products designware docs ds c dwcore_ethernet pdf 276 Synopsys Inc April 2003
113. are docs ds c dwcore_blueiq pdf 274 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Cor dwcore blueiq devkit S Bluetooth Development Kit dwcore blueiq devkit Bluetooth Development Kit The Synopsys DesignWare Bluetooth Development Kit is a device used to develop applications for hardware platforms containing the DesignWare BlueIQ Core It contains the DesignWare BlueIQ Core implemented in an FPGA and the Silicon Wave SiW1701 Radio Modem It can be connected to any PC or workstation over a standard USB or RS232 connection Other features include the following e Simple serial connection to PC or e Compatible with any Bluetooth upper other host development platform stack software or development through UART or USB platform e Headset port for audio connection e Includes Silicon Wave SiW1701 radio e Flash memory can be reprogrammed modem allowing firmware updates to the e Includes an evaluation copy of the BlueIQ Core Mezoe Interface Express e FPGA can be reprogrammed allowing incorporating BlueStack and Proto hardware updates to the BlueIQ Core Developer software for rapid application development e Debug connection provides access to PP P menu of debugging commands Headset Debug HCI 4 HCI Boot DesignWare BluelQ Power Supply Bluetooth Development Kit The dwcore blueiq devkit data sheet is available at http www synopsys com products designw
114. are high performance trigonometric implementations based on a fast carry look ahead architecture 94 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide i b DW02 cos COS Combinational Cosine DW02 cos Combinational Cosine e Parameterized word length A COS Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Angle in binary COS cos width bit s Output Cosine value of A Table 2 Parameter Description Parameter Values Description A width 2 to 34 Word length of A cos width 2 to 34 Word length of COS Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 95 DesignWare IP Family Quick Reference Guide SIN DWO2 sin Combinational Sine COs DW02_sin Combinational Sine e Parameterized word length A SIN Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Angle in binary SIN sin_width bit s Output Sine value of A Table 2 Parameter Description Parameter Values Description A_width 2 to 34 Word length of A sin_ width 2 to 34 Word length of SIN Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation
115. as commanded by the ld crc n control input draining 1 bit Output Indicates that the CRC register is draining inserting the CRC into the data stream drain done 1 bit Output Indicates that the CRC register has finished draining crc ok 1 bit Output Indicates a correct residual CRC value active high data out data_width bit s Output Output data crc_out poly_size bit s Output Provides constant monitoring of the CRC register April 2003 Synopsys Inc 179 DesignWare IP Family Quick Reference Guide DW crc s Universal Synchronous Clocked CRC Generator Checker Table 2 Parameter Description Parameter Values Description data width 1 to poly size Width of data in and data out also the number of bits per clock Default 16 poly size 2 to 64 Size of the CRC polynomial Default 16 crc cfg 0 to 7 CRC initialization and insertion configuration Default 7 bit order 0 to 3 Bit and byte order configuration Default 3 poly coef 0 to 65535 Polynomial coefficients 0 through 15 Default 4129 poly coefl1 0 to 65535 Polynomial coefficients 16 through 31 Default 0 poly coef2 0 to 65535 Polynomial coefficients 32 through 47 Default 0 poly coef3 0 to 65535 Polynomial coefficients 48 through 63 Default 0 a The data width value must be chosen such that poly size is a multiple of data width b The poly coef value must be an odd number since
116. as described in User Defined Timing in the Smartmodel Library User s Manual Specific Model Information SmartModel datasheets provide specific user information about each model in the library The model datasheets supplement but do not duplicate the manufacturer s datasheets for the hardware parts In general the model datasheets describe e Supported hardware IP and devices e Bibliographic sources used to develop the model specific vendor databooks or datasheets e How to configure and operate the model e Any timing parameters that differ from the vendor specifications e How to program the device if applicable or otherwise use it in simulation e Differences between the model and the corresponding hardware device Models are partitioned by function including e Processors VLSI e Programmables e Memories e Standards Buses e General Purpose SmartModel datasheets have standard sections that apply to all models and model specific sections whose contents depend on the model type April 2003 Synopsys Inc 269 Specific Model Information DesignWare IP Family Quick Reference Guide 270 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 4 DesignWare Cores 4 DesignWare Cores DesignWare Cores provide system designers with silicon proven digital and analog connectivity IP Provided as heavily annotated synthesizable RTL source code or in GDS format these cores enable you to design i
117. at Write Port Dual Read Port RAM Latch Based DW ram 2r w a lat Write Port Dual Read Port RAM Latch Based e Parameterized word depth rdi addr rd2 addr wr addr data in e Parameterized data width i data rd1 out e Asynchronous static memory a data rd2 out e Parameterized reset implementation cs n wr n rst n Table 1 Pin Description Pin Name Width Direction Function rst n 1 bit Input Reset active low cs n 1 bit Input Chip select active low wrn bit Input Write enable active low rdi addr ceil log 5 depth bit Input Read1 address bus rd2_addr ceil logs depth bit Input Read2 address bus wr addr ceil logo5 depth bit Input Write address bus data in data width bit Input Input data bus data rdl out data width bit Output Output data bus for read1 data rd2 out data_width bit Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data width 1 to 256 Width of data in and data out buses depth 2to 256 Number of words in the memory array address width rst mode Oor 1 Determines if the rst n input is used 0 rst_n initializes the RAM 1 2rst nis not connected Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 168 Synopsys Inc April 2003 DesignWare IP F
118. ata_in crc_ok 1 bit Output Indicates a correct residual CRC value active high crc_out poly_size bit s Output Provides the CRC check bits to be appended to the input data to form a valid record data in and crc in Table 2 Parameter Description Parameter Values Description data width to 512 Width of data in i e the amount of data that CRC Default 16 will be calculated upon poly size 2 to 64 Size of the CRC polynomial and thus the width of Default 16 crc in and crc out crc cfg 0 to 7 CRC initialization and insertion configuration Default 7 bit order 0 to 3 Bit and byte order configuration Default 3 poly coef0 1 to 65535 Polynomial coefficients 0 through 15 Default 4129 poly coefl 0 to 65535 Polynomial coefficients 16 through 31 Default 0 April 2003 Synopsys Inc 177 DesignWare IP Family Quick Reference Guide DW crc p Universal Parallel Combinational CRC Generator Checker Table 2 Parameter Description Continued Parameter Values Description poly coef2 0 to 65535 Polynomial coefficients 32 through 47 Default 0 poly coef3 0 to 65535 Polynomial coefficients 48 through 63 Default 0 a poly coef0 must be an odd number since all primitive polynomials include the coefficient 1 which is equivalent to x9 b CCITT CRC16 polynomial is X16 X12 X5 1 thus poly coef 212 25 1 4129
119. atic Flags e Fully registered synchronous flag output ports push req n data out e D flip flop based memory array for high testability ind ram full e All operations execute in a single clock cycle MM acd usn n e FIFO empty half full and full flags T almost full half full almost empty empty error e Parameterized asymmetric input and output bit widths diag n must be integer multiple relationship e Word integrity flag for gt clk rst_n data_in_width lt data_out_width e Flushing out partial word for data_in_width lt data_out_width e Parameterized byte or subword order within a word e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous memory array initialized or not April 2003 Synopsys Inc 123 DesignWare IP Family Quick Reference Guide DW asymfifo s1 sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst mode 1 push req n 1 bit Input FIFO push request active low flush n 1 bit Input Flushes the partial word into memory fills in 0 s for data in width lt data out width only
120. ation Library See also Building Block IP DesignWare GTECH Library 230 DesignWare IP Family overview 15 DesignWare Library Synthesizable IP 27 AMBA On chip Bus Logic and Peripherals 231 Building Block IP 27 DW ahb 232 DW ahb h2h 234 DW ahb icm 235 DW ahb ictl 236 DW apb 237 DW_apb_gpio 238 DW apb i2c 239 DW apb ictl 240 DW apb rap 241 DW apb rtc 242 DW apb ssi 243 DW apb timers 245 DW apb uart 246 DW apb wdt 248 DW memctl 250 DW rambist 251 DW8051 254 Memory IP 249 DesignWare Library Verification IP overview 255 DesignWare Memory Models data storage 267 features 267 overview 267 Synopsys Inc 313 DesignWare IP Family Quick Reference Guide Index DesignWare Star IP overview 299 DW apb uart 246 DesignWare Synthesizable Core DW apb wdt 248 dwcore 1394 avlink 290 DW arbiter 2t 222 dwcore 1394 cphy 293 DW arbiter dp 224 dwcore 1394 device 291 DW arbiter fcfs 226 dwcore 1394 ohci 292 DW arbiter sp 228 a DC sara dwcore ethernet sub 277 AU e dwcore gig ethernet 278 un ea 138 dwcore gig ethernet sub 279 D W Soy niot E dwcore jpeg codec 295 DW asymfifoctl sl sf 141 dwcore jpeg2 codec 296 DW asymfifoctl s2 sf 144 dwcore_jpeg2_encod 297 DW bc 1 195 dwcore jvxtreme 294 DW bc 2 196 dwcore pci 280 DW bc 3 197 dwcore pci express 282 DW bc 4 198 dwcore pcix 281 DW bc 5199 dwcore usb otg 283 DW bc 7 200 dwcore usbl device 284 DW bin2gray 42 dwcore usbl host 285 DW C166S 304 dwcore_usb1_hub 286 dwcore usb2 devi
121. bit address and data paths Five stage pipelined CPU Compatible with standard MIPS32 instruction set with optional support for MIPS16 instructions User defined instructions optional Configurable instruction and data cache sizes MIPS R4000 style Privileged Resource Architecture Synchronous system EC bus interface Memory management unit o Translation lookaside buffer TLB in 4KEc configuration o Fixed address mapping in 4KEm and 4KEp configurations Synopsys Inc Scratchpad RAM support optional Coprocessor 2 interface optional Multiply divide unit o High performance implementation in 4KEc and 4KEm configurations o Area efficient implementation in 4KEp configuration Power management Enhanced JTAG EJTAG debug support Support for a variety of third party development and debugging tools the current list of support tools is available at http www mips com April 2003 DesignWare IP Family Quick Reference Guide q 5 DW_MIPS4KE Processor Core Family from MIPS COP2 I F COP2 I F Logic Data Cache System I F Execution Cache Instruction Unit Controller Cache use n I F ISPRAM I F gt Bus EC I F Interface EJTAG I F Unit gt EJTAG Trace I F Trace Control gt Block DW_MIPS4KE Block Diagram Also see the following web page for additional information http www synopsys com products designware starip mips_4ke html April 2003 Syno
122. book is available at http www synopsys com products designware docs April 2003 Synopsys Inc 233 DesignWare IP Family Quick Reference Guide DW ahb h2h AMBA AHB to AHB Bridge DW ahb h2h AMBA AHB to AHB Bridge e Asynchronous clocks any clock ratio e Bursts forwarded as single NSEQ e Synchronous clocks any integer clock Beate ratio e Self timedl low gate count e Any address bus width data bus width implementation any endianness e Internal timeout counters for deadlock protection e No split capable slave e Synchronizers bypass selection pin DW ahb h2h AHB bus secondary AHB bus RS primary Se The DesignWare DW_ahb_h2h Databook is available at http www synopsys com products designware docs 234 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW ahb icm AMBA AHB Multi layer Interconnection Matrix DW ahb icm AMBA AHB Multi layer Interconnection Matrix Layer arbitration and master Some uses of the DW_ahb_icm are multiplexing e An add on interface for AHB slaves to Input stage address and control allow them to be used in a multi layer holding registers for each layer system Mapping of slave response onto e Support for an AHB master to operate correct layer in an AMBA Lite mode within a multi layer system Returning of splits onto the correct yer SY layer Common clock and reset shared amongst all layers DW ahb m X Laye
123. can be stored in FIFO Default 8 push ae lvl 1todepth 1 Almost empty level for the push ae output port the number Default 2 s in the FIFO at or below which the push ae flag is April 2003 Synopsys Inc 153 DesignWare IP Family Quick Reference Guide DW fifoctl s2 sf uis Synchronous Dual Clock FIFO Controller with Static Flags Table 2 Parameter Description Continued Parameter Values Description push af lvl l1todepth 1 Almost full level for the push af output port the number of Default 2 empty memory locations in the FIFO at which the push af flag is active pop ae lvl ltodepth 1 Almost empty level for the pop ae output port the number Default 2 of words in the FIFO at or below which the pop ae flag is active pop af lvl l to depth 1 Almost full level for the pop af output port the number of Default 2 empty memory locations in the FIFO at which the pop af flag is active err mode Oor 1 Error mode Default 0 0 stays active until reset latched 1 active only as long as error condition exists unlatched push sync 1 to3 Push flag synchronization mode Default 2 1 single register synchronization from pop pointer 2 double register 3 triple register pop sync 1 to3 Pop flag synchronization mode Default 2 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode Oor 1 Reset mode Default 0 0
124. carry look ahead synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 217 DesignWare IP Family Quick Reference Guide Application Specific Interface Overview Application Specific Interface Overview The Interface IP consist of the DW debugger IP 218 Synopsys Inc April 2003 DW debugger On Chip ASCII Debugger e Low gate count e Parameterized data widths DesignWare IP Family Quick Reference Guide DW debugger On Chip ASCII Debugger rd bits wr bits rxd Bd div bypass mode p clk reset N Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock reset_N 1 bit Input Synchronous reset active low rd_bits rd_bits_width bit s Input Input data bus rxd 1 bit Input Receive data wr_bits wr bits width bit s Output Output data bus txd 1 bit Output Transmit data div bypass mode 1 bit Input Clock Divider Bypass Control active high Table 2 Parameter Description Parameter Values Description rd bits width 8 to 2048 Width of rd bits Default 8 wr bits width 8 to 2048 Width of wr bits Default 8 clk freq 2 must
125. ccess on wide AMBA bus DW memctl MacroCell Address Decoder SDRAM Controller SDRAM State Machine Interface Host Interface Unit HIU Static memory Controller Static State Machine Memory Interface Control Registers Refresh Unit The DesignWare DW memctl MacroCell Databook is available at http www synopsys com products designware docs 250 Synopsys Inc April 2003 20 o Coy DW_rambist Memory Built In Self Test Interfaces e IEEE 1149 1 TAP controller interface e Two clock interface one for a slower TAP I F second for at speed BIST execution e Optional MUX block that supports either embedded multiplexers inside the memories or user specified multiplexers e Flexible configuration for embedded MUX block providing a better interface to memory control signals with different widths and polarities Error Diagnostics e Pause on first and subsequent failures mode serial debugging e Failing address and data may be scanned out for examination e Quick debug mode continue on failures mode failing addresses not recorded e Parallel debug port to observe the failing memory data bits BIST Tests e User choice of March LR 14n March C 10n and MATS 6n e Custom user defined patterns option e Optional SRAM retention test Sn delay auto pause mechanism e Selection of background and complement background data patterns April 2003 DesignWare IP Family Quick
126. ce 288 I i dwcore usb2 host 287 DW cntr erav 50 dwcore usb2 phy 289 DW d DesignWare VMT Models overview 256 Be 179 DSP Library Overview 230 pv OE DW 8b10b dec 185 DW sc Dus BET AAR DW_8b10b_enc 187 US EUNT DW 8b10b unbal 188 E DW add fp 106 DW div pipe 55 DW addsub dx 39 ud DW ahb 232 DW dpll sd 211 DW ahb h2h 234 P A DW ahb icm 235 DW fifo sl df 131 DW ahb jctl 236 DW fifo s1 sf 133 DW apb 237 DW fifo s2 sf 135 DW apb spio 238 DW fifoctl s1 df 148 DW apb i2c 239 DW fifoctl s1 sf 150 DW apb ic 240 DW fifoctl s2 sf 152 DW apb rap 2A DW flQ2i fp 110 DW apb rtc 242 DW ernyebun ur DW apb sa 243 DW 12flt fp 111 DW apb timers 245 DANCERS April 2003 Synopsys Inc 314 DesignWare IP Family Quick Reference Guide Index DW inc gray 61 DWOI csa 51 DW memctl 250 DWOI dec 52 DW minmax 63 DWOI decode 204 DW MIPSAKE 308 DWOI inc 58 DW mult dx 72 DWO1I incdec 59 DW mult fp 112 DWO01 mux any 205 DW mult pipe 73 DWOI prienc 206 DW mult seq 101 DWOI satrnd 81 DW prod sum pipe 79 DWOI sub 90 DW ram 2r w a dff 166 DW02_cos 95 DW ram 2r w a lat 168 DWO02 mac 62 DW ram 2r w s dff 158 DWO02 mult 64 DW ram 2r w s lat 160 DWO02 mult 2 stage 67 DW ram r w a dff 164 DWO02 mult 3 stage 68 DW ram r w a lat 165 DWO02 mult 4 stage 69 DW ram r w s dff 156 DWO02 mult 5 stage 70 DW ram r w s lat 157 DWO02 mult 6 stage 71 DW ram rw a dff 169 DWO02 multp 66 DW ram rw a lat 170 DWO02 prod sum 75 DW
127. chronous address and flag output push req n ae orts op req n EA s f i rd_addr e All operations execute in a single clock cycle de ave e FIFO empty half full and full flags af thresh almost full CNET half full e FIFO error flag indicating underflow overflow and diag n almost empty pointer corruption Simply e Dynamically programmable almost full and almost D emor empty flags e Parameterized word depth e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst mode 1 push req n 1 bit Input FIFO push request active low pop req n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control for err_mode 0 NC for other err_mode values active low ae_level ceil logs depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost empty flag is active 148 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AT DW fifoctl s1 df Synchronous Single Clock FIFO Controller with Dynamic Flags Table 1 Pin Description Pin Name Width Direction Function af thresh ceil log depth bit s Inp
128. ck IP on page 27 Component Group Description Component Type Datapath Arithmetic floating point trigonometric and Synthesizable RTL sequential math IP page 32 Memory Registers FIFO synchronous and asynchronous Synthesizable RTL RAM and stack IP page 113 Data Integrity Data integrity IP such as CRC ECC 8b10b Synthesizable RTL page 176 Test JTAG IP such as boundary scan TAP controller Synthesizable RTL page 189 Logic Combinational sequential and control IP page 221 Synthesizable RTL Interface Debugger IP page 218 Synthesizable RTL DSP Digital FIR filter IP page 230 Synthesizable RTL GTECH Technology independent IP library to aid users in Synthesizable RTL developing technology independent parts page 230 AMBA On Chip Bus AMBA is a standard bus architecture system developed by ARM for rapid development of processor driven systems AMBA also allows a number of bus peripherals and resources to be connected in a consistent way The following Synopsys AMBA components are AMBA 2 0 compliant Component Name AMBA 2 0 Component Description Component Type DW ahb AHB bus arbitration decode and control logic Synthesizable RTL page 232 DW ahb h2h AHB to AHB Bridge page 234 Synthesizable RTL DW ahb icm AHB Multi layer Interconnection Matrix page 235 Synthesizable RTL April 2003 Synopsys Inc 17 Chapter 1 Overview Desig
129. ck Reference Guide Microprocessors Microcontroller Cores Synthesizable RTL of these cores are available through the Star IP Program To search for specific devices of the processor models visit http www synopsys com ipdirectory Chapter 1 Overview Component Name Component Description Component Type DW IBM440 PowerPC 440 Microprocessor Core from IBM Synthesizable RTL Available Q2 03 page 300 Verification Model DW V850E Star V850E Processor Core from NEC page 302 Synthesizable RTL Verification Model DW_C166S 16 bit Processor from Infineon page 304 Synthesizable RTL Verification Model DW TriCorel TriCorel 32 Bit Processor Core from Infineon Synthesizable RTL page 306 Verification Model DW MIPSAKE Processor Core Family from MIPS page 308 Synthesizable RTL Verification Model DW8051 8 bit Microcontroller page 254 Synthesizable RTL AMD Processor Models Verification Models ARM Processor Models Verification Models Fujitsu Processor Models Verification Models IBM Processor Models Verification Models IDT Processor Models Verification Models Infineon Processor Models Verification Models MIPS Processor Models Verification Models Motorola Processor Models Verification Models NEC Processor Models Verification Models TI Processor Models Verification Models a Verification models of these cores are included in the DesignWare Library Synthesiz
130. cks data into the update stage capture en bit Input Enable for data clocked into the capture stage active low update en 1 bit Input Enable for data clocked into the update stage active high shift dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data out is controlled by the boundary scan cell or by the data in signal si 1 bit Input Serial path from the previous boundary scan cell data in bit Input Input data data out 1 bit Output Output data So 1 bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Test IEEE STD 1149 1 April 2003 Synopsys Inc 195 DesignWare IP Family Quick Reference Guide DW bc 2 Boundary Scan Cell Type BC 2 DW bc 2 Boundary Scan Cell Type BC 2 e IEEE Standard 1149 1 compliant data in data out s i so e Synchronous or asynchronous scan cells with respect to tck SI mode e Supports the standard instructions EXTEST SAMPLE shift dr PRELOAD and BYPASS T e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ capture en update en gt update clk pcapture clk Table 1 Pin Description Pin Name Width Direction Function capture clk 1bit Input Clocks data into the cap
131. clude the following Implements the IEEE 802 3z and 802 3u specifications that define the 10 Mbps 100 Mbps and 1 Gbps Ethernet standards Generates and accepts Control Frames in Full Duplex Mode IEEE 802 3x Includes configurable counters for statistical network management support Provides complete status for transmission and reception packets Highly programmable DMA engine to meet optimal bus performance Programmable descriptor interrupt architecture minimizes CPU overhead Supports programmable interrupt options for different operational conditions Includes two dual port RAM based FIFOs one for transmission and one for reception Optimized for switching routing network interface card and system on chip applications Compliant with IEEE 802 3z and 802 3u specifications Supports 10 100 Mbps and 1 Gbps data transfer rates IEEE 802 3z Gigabit Media Independent Interface GMIT IEEE 802 3z Physical Coding Sublayer PCS with Ten Bit Interface TBI that supports autonegotiation optional Supports Full and Half Duplex operations in all speed modes Supports Virtual LAN VLAN Detection Power management support Remote Wake up LAN and magic packets Synthesizable Verilog source code The dwcore gig ethernet sub data sheet is available at April 2003 http www synopsys com products designware docs ds c dwcore gig ethernet sub pdf Synopsys Inc 279 DesignWare IP Family Quick Reference Guide
132. ction data width Input Counter load input count to width Input Count compare input up dn 1 Input High for count up and low for count down load 1 Input Enable data load to counter active low cen 1 Input Count enable active high clk 1 Input Clock reset 1 Input Counter reset active low count width Output Output count bus tercnt 1 Output Terminal count flag active high Table 2 Parameter Description Parameter Values Description width 21 Width of data input bus Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Synopsys Inc April 2003 i DWO3 bictr scnto Up Down Binary Counter with Static Count to Flag e Parameterized word length Parameterized count to value Up down count control Asynchronous reset Loadable count register Terminal count flag Counter enable DesignWare IP Family Quick Reference Guide DWO3 bictr scnto Up Down Binary Counter with Static Count to Flag count up dn tercnt cen load clk reset Table 1 Pin Description Pin Name Width Direction Function data width Input Counter load input up_dn 1 bit Input High for count up and low for count down load 1 bit Input Enable data load to counter active low cen 1 bit Input Count enable active high clk 1 bit Input Clock reset 1 bit Input Counter reset active low c
133. ctive low we_n 1 bit Output Write enable output for write port of RAM active low empty 1 bit Output FIFO empty output active high almost empty 1 bit Output FIFO almost empty output asserted when FIFO level xae level active high half full 1 bit Output FIFO half full output active high almost full 1 bit Output FIFO almost full output asserted when FIFO level depth af level active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high 150 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW fifoctl s1 sf Synchronous SingleClock FIFO Controller with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function wr addr ceil log5 depth bit s Output Address output to write port of RAM rd addr ceil log5 depth bit s Output Address output to read port of RAM Table 2 Parameter Description Parameter Values Function depth 2 to 224 Number of memory elements used in FIFO used to size Default 4 the address ports ae_level 1 to depth 1 Almost empty level the number of words in the FIFO at Default 1 or below which the almost empty flag is active af level l to depth 1 Almost full level the number of empty memory locations Default 1 in the FIFO at which the almost fu
134. cts Booth recoding or non Booth recoding depending on constraints e This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide April 2003 Synopsys Inc 65 DesignWare IP Family Quick Reference Guide DWO2 multp Partial Product Multiplier DWO02 multp Partial Product Multiplier e Parameterized word lengths e Parameterized sign extension of partial product outputs for use in summing products e Unsigned and signed two s complement data operation Table 1 Pin Description Pin Name Width Direction Function a a width bit s Input Multiplier b width bit s Input Multiplicand tc 1 bit Input Two s complement 0 unsigned 1 signed outO out width bit s Output Partial product of a x b out out width bit s Output Partial product of a x b Table 2 Parameter Description Parameter Values Description a width 21 Word length of a b_width 21 Word length of b out_width 2a width b width 2 Word length of outO and out Table 3 Synthesis Implementations Implementation Name Function License Required
135. d reset mode no reset asynchronous or synchronous reset e Automatic pipeline retiming Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall_mode 1 0 stall 1 load tc 1 bit Input Two s complement control 0 unsigned 1 signed a a_width bit s Input Multiplier b b_width bit s Input Multiplicand product a_width b_width bit s Output Product a x b April 2003 Synopsys Inc 73 DesignWare IP Family Quick Reference Guide DW mult pipe Stallable Pipelined multiplier Table 2 Parameter Description Parameter Values Description a width 21 Word length of a Default None b_width 21 Word length of b Default None num stages 2 Number of pipeline stages Default 2 stall mode O or 1 Stall mode Default 1 0 non stallable 1 stallable rst mode 0to2 Reset mode Default 1 0 no reset 1 asynchronous reset 2 synchronous reset Table 3 Synthesis Implementations Implementation Name Implementation License Required str Pipelined str synthesis model Design Ware Foundation a One of csa wall or nbw implementation is selected based on the constraints of the design 74 Synopsys Inc April 2003 DesignWare IP Fam
136. d type of access e Means of interrogating and controlling the models through functions implemented as Verilog tasks VHDL procedures C functions or VERA methods The Memory Model documentation is available at http www synopsys com products designware docs April 2003 Synopsys Inc 267 SmartModel Features DesignWare IP Family Quick Reference Guide DesignWare SmartModels The SmartModel Library is a collection of over 3 000 binary behavioral models of standard integrated circuits supporting more than 12 000 different devices The library features models of devices from the world s leading semiconductor manufacturers including microprocessors controllers peripherals FPGAs CPLDs memories and general purpose logic SmartModels connect to logic simulators through the SWIFT interface which is integrated with over 30 commercial simulators including Synopsys VCS and Scirocco Cadence Verilog XL and Mentor Graphics QuickSim II Instead of simulating devices at the gate level SmartModels represent integrated circuits and system buses as black boxes that accept input stimulus and respond with appropriate output behavior Such behavioral models are distributed in object code form because they provide improved performance over gate level models while at the same time protecting the proprietary designs created by semiconductor vendors All SmartModels and model datasheets are listed in the IP Directory which you can find on the
137. dation Synopsys Inc tercnt April 2003 iS DW dpll sd Digital Phase Locked Loop e Parameterizable divisor ratio of reference clock to baud rate e Multichannel data recovery recovery of channels that accompany the locked channel e Stall input for power saving mode and or prescaler allowing one DW dpll sd to recover data at multiple rates e Squelch input for ignoring phase information when channel data is unknown or unconnected e Sampling window control to aid data recovery under harsh conditions DesignWare IP Family Quick Reference Guide DW dpli sd Digital Phase Locked Loop data in data Out mm window bit ready squelch stall clk out clk e Parameterizable gain selection to meet a variety of application needs e Parameterizable filter controls phase correction reactiveness from minor phase errors Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Reference clock rst_n 1 bit Input Asynchronous reset active low stall 1 bit Input Stalls everything except synchronizer active high squelch 1 bit Input Turns off phase detection When high no phase correction is carried out leaving DPLL free running active high window ceil log2 windows Input Sampling window selector data_in width bit s Input Serial input data stream clk_out 1 bit Output Recovered Clock bit ready 1 bit Output Output data ready f
138. dth 22 Word length of din Default 16 msb out width 2 msb out gt lsb out dout MSB position after Default 15 truncation of din MSBs Isb out msb out gt lsb out 2 0 dout LSB position after Default 0 truncation of din LSBs April 2003 Synopsys Inc 81 DesignWare IP Family Quick Reference Guide DWO1 satrnd Arithmetic Saturation and Rounding Logic 82 Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW shifter Combined Arithmetic and Barrel Shifter DW shifter Combined Arithmetic and Barrel Shifter e Dynamically selectable arithmetic or barrel shift mode data in e Parameterized input control inverted and non inverted logic data tc e Parameterized padded logic value control for arithmetic shift sh data out only sh tc e Parameterized data and shift coefficient word lengths de e Inferable using a function call support for inv mode 0 ui only Table 1 Pin Description Pin Name Width Direction Function data in data width bit s Input Input data data tc bit Input Two s complement control on data in 0 unsigned data in 1 signed data in sh sh width bit s Input Shift control sh tc 1 bit Input Two s complement control on sh 0 unsigned sh 1 si
139. e 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal intest 1 bit Input INTEST instruction signal Si 1 bit Input Serial path from the previous boundary scan cell data_in Ibit Input Input data from system input pin data_out 1 bit Output Output data SO l bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Test IEEE STD 1149 1 April 2003 Synopsys Inc 199 DesignWare IP Family Quick Reference Guide DW bc 7 Boundary Scan Cell Type BC 7 DW bc 7 Boundary Scan Cell Type BC 7 e IEEE Standard 1149 1 compliant e Synchronous or asynchronous scan cells with respect to tck e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ shift dr mode1 ic input mode2 data out si SO pin input control out output data O capture en update en gt update clk pcapture clk Table 1 Pin Description Pin Name Width Direction Function capture clk 1 bit Input Clocks data into the capture stage update clk 1 bit Input Clocks data into the update stage capture en bit Input Enable for data clocked into the capture stage activ
140. e DesignWare DW apb Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 237 DesignWare IP Family Quick Reference Guide DW apb gpio General Purpose Programmable I O DW_apb_gpio General Purpose Programmable I O e APB interface to from APB Bridge e Separate data registers and data e Up to 128 independently configurable SECGHORACOR Ue Targach Pot pins e Separate auxiliary data input data output and data control for each I O in e Up to four ports A to D which are ae a Coito mod separately configurable e Configurable debounce logic with an external slow clock to debounce interrupts e Port A can be configured to act in interrupt mode e Configurable hardware and software Option to generate single or multiple control for each part ne 8 g P interrupts e GPIO ID e Component version ID register DW apb gpio External Data wr Port xpins 1 0 7 8 Interface APB APB m Interface AuxData p a Interrupt ite Detection The DesignWare DW_apb_gpio Databook is available at http www synopsys com products designware docs 238 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW apb i2c APB I C Interface DW_apb i2c APB I C Interface e Two wire IC serial interface e Ignores CBUS addresses an older ancestor of C
141. e Parameterized byte or subword order within a word e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Dynamically programmable almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous memory array initialized or not 120 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifo s1 df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push req n 1 bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for data in width lt data_out_width only pop req n 1 bit Input FIFO pop request active low diag n 1 bit Input Diagnostic control active low for err mode 0 NC for other err mode values data in data in width bit s Input FIFO data to push ae level ceil logs depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost empty flag is active af thresh ceil log depth bit s Input Almost full threshold the number of words stored in the FIFO at or above which the almost full flag is active empty 1 bit Output FIFO empty output acti
142. e Parameterized data width e Synchronous static memory e Inferable from Behavioral Compiler 100111001 RAM rd1_ addr rd2_addr wr_addr data_in data rd1 out cs n wrn data rd2 out Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rdi addr ceil log depth bit Input Read1 address bus rd2 addr ceil log5 depth bit s Input Read2 address bus wr addr ceil log5 depth bit s Input Write address bus data in data width bit s Input Input data bus data rd out data width bit s Output Output data bus for readl data rd2 out data width bit s Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data width 1 to 256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 160 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 DW ram rw s dff Synchronous Single Port Read Write RAM Flip Flop Based DW ram rw s dff Synchronous Single Port Read Write RAM Flip Flop Based e Parameterized word depth rw addr data in e Parameterized data width
143. e Power management supports remote transmission and one for reception wake up LAN and magic packets e Optimized for switching routing e RapidScript utility for fast network interface card and customization system on chip applications e Compliant with IEEE 802 3 and e HomePNA 2 0 support with specific 802 3u specifications HPNA PHYs e Available in Verilog The dwcore ethernet sub data sheet 1s available at http www synopsys com products designware docs ds c dwcore ethernet sub pdf April 2003 Synopsys Inc 277 DesignWare IP Family Quick Reference Guide dwcore gig ethernet Synthesizable Gigabit Ethernet Core dwcore gig ethernet Synthesizable Gigabit Ethernet Core e Collision detection and auto retransmission on collisions in Half Duplex mode CSMA CD protocol e Flow control using backpressure in Half Duplex mode and flow control frames IEEE 802 3x in Full Duplex mode e Preamble generation and removal e Automatic 32 bit CRC generation and checking e Configurable counters for remote monitoring RMON and Simple Network Management Protocol SNMP optional e Complete status for transmission and reception frames e Compliant with IEEE 802 3 802 3u and 802 3z specifications e Supports 10 100 Mbps and 1 Gbps data transfers in Full Duplex and Half Duplex modes e Supports rate selection 10 100 1000 post silicon e Supports IEEE 802 3q e Virtual LAN VLAN tagged frame detection e IEEE 80
144. e Synchronous static memory VENDUE e Parameterized reset mode asynchronous or synchronous e Inferable by Behavioral Compiler e High testability using DFT Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rw_addr ceil logo depth bit s Input Address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oorl Determines the reset methodology 0 rst n asynchronously initializes the RAM 2rst n synchronously initializes the RAM Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Components April 2003 Synopsys Inc 161 DesignWare IP Family Quick Reference Guide 100111001 DW ram rw s lat RAM Synchronous Single Port Read Write RAM Latch Based 01101001 DW ram rw s lat Synchronous Single Port Read Write RAM Latch Based e Parameterized word depth rw adar e Parameterized data width data in data out Synchronous static memory cs n wr n e Inferable from
145. e enassutess cens 127 DW Alio sl Of aeusqesuit utes 9149 ddc b d RE Ed IE od EROR REE RTS 131 EV ILU uazessbesesi e d aee ee ee ee re ee 133 DA OS rrr rrr PPP 135 DW anos di go cg 00s as O48 0 9965 24 aR ER XR ERAT 138 EY A sl SE das desesdak edb4eduresidk esQ Air RR 141 LES ee ET M occ rane ener dasieads tneee tad RRERERCL E23 144 DW oU Sl d 2455 5 65 8 ie 00S 1S ERAS OH ON OHS 1 OREO aS OES REM 148 E Te RD 2a ce tes eed ceed Q4RERU er idei hEr bride pEr 150 DA Nx pn ks cabo ae Paw dsGaR IR OPA RRR SER SAAR ORS 152 Memory Synchronous RAMS o6 4cbc as eus a eeve wees danke sae ARA RA 135 Ew A MM cake bee eu eed ten oe S dE XE RRSANQE ERE ER dI 156 EN Pa 068 NE bak n 8 PER Dd EUR Seded ants Dei 137 DW oum Now db loezezesos 223 X24XxAA A REOR AREE SEE CR 158 EST NUN QUA ee ee ee ee eS pete qe Rd qub Rex 160 DW XT EE 5 oo hah ohh qa ddr EIRGE RARE ERRREERE RRS OEE 161 DW tam DA X BH uasdsa cheney 4654 60 4096566055 ACE apiid ds 162 Memory Asynchronous RAMS Lisssiesasakrtenk3 koX A WEXAzzE VEA RA 163 DW NET M JE uoadugscioels gna op tam Sich Mart d emitur d dos eoo tos 164 DW tam rt w a lat nko oak oe ews xp deeb aoe Rx RE dA RAE EXER RES 165 EW dg EAM oeses4sdeEtePENE e Edquebpiadbededaubssdxs 166 April 2003 Synopsys Inc 5 Contents DesignWare IP Family Quick Reference Guide LT gH D E N Lied eee hw ieee eens en ERE REEWCRCRE SE dE 168 DA OLTRE UM asuaedesiccle ewe p donde dido Umi door Pn om 169 EN UE IS A NE uusseszebten
146. e low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo model 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the output_data signal mode2 1 bit Input Determines whether ic_input is controlled by the boundary scan cell or by the pin_input signal si bit Input Serial path from the previous boundary scan cell pin input 1 bit Input IC system input pin control out 1 bit Input Control signal for the output enable output data 1 bit Input IC output logic signal ic_input 1 bit Output IC input logic signal data_out 1 bit Output Output data SO 1 bit Output Serial path to the next boundary scan cell 200 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW bc 7 Boundary Scan Cell Type BC 7 Table 2 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Test IEEE STD 1149 1 April 2003 Synopsys Inc 201 DesignWare IP Family Quick Reference Guide Logic Combinational Overview Logic Combinational Overview The combinational components consist of high performance logical components Most components in this category have multiple architectures for each function architecturally optimized for either performance or area to
147. ears the system and shadow registers SI 1 bit Input Serial scan input clocked by shad_clk when SE is high SE 1 bit Input Serial scan enable signal active high Enables scan only on the shadow register Sys out width bit s Output Output of the system register shad out width bit s Output Parallel output of the shadow register that lags the system register by one cycle SO 1 bit Output Serial scan output from shadow register When SE is low represents the state of the MSB of the shadow register When SE is high each successive bit is shifted up one and SI is clocked into the LSB Table 2 Parameter Description Parameter Values Description width 1 to 5122 Defines the width of the system and shadow registers and the input and output buses bld shad reg Oor1 Defines whether to build both the system and shadow registers bld shad reg 1 or just the system register bld shad reg 0 a The upper bound of the legal range is a guideline to ensure reasonable compile times April 2003 Synopsys Inc 117 DesignWare IP Family Quick Reference Guide DWO4 shad reg Shadow and Multibit Register Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 118 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Memory FIFO Overview The FIFOs in this category address a broad array of d
148. ected in a consistent way The following Synopsys AMBA 2 0 compliant components are briefly described in this section Table 1 Alphabetical List of the AMBA Synthesizable IP Name and Page Description DW ahb page 232 Advanced High performance Bus AHB DW ahb h2h page 234 AHB to AHB Bridge DW ahb icm page 235 AMBA AHB Multi layer Interconnection Matrix DW ahb ictl page 236 AHB Interrupt Controller DW apb page 237 Advanced Peripheral Bus APB DW apb gpio page 238 General Purpose Programmable I O DW apb ictl page 240 APB Interrupt Controller DW apb i2c page 239 APB IC Interface DW apb rap page 241 Remap and Pause DW apb rtc page 242 APB Real Time Clock DW apb ssi page 243 APB Synchronous Serial Interface DW apb timers page 245 Programmable Timers DW apb uart page 246 Universal Asynchronous Receiver Transmitter DW apb wdt page 248 APB Watch Dog Timer A brief introduction to the AMBA On Chip Bus can be found at the following location http www synopsys com products designware dw amba html April 2003 Synopsys Inc 231 DesignWare IP Family Quick Reference Guide DW ahb Advanced High performance Bus DW ahb Advanced High performance Bus 232 Configuration of AMBA Lite system Configuration of up to 15 masters in a non AMBA Lite system Configuration of up to 15 slaves ina non AMBA Lite system Configuration of data bus width of up to 256
149. ed for internal interrupts Synopsys Inc 16 level 8 group level interrupt priority Up to 16 interrupt driven peripheral event controller PEC channels Power reduction modes Programmable watchdog timer Debug interface that supports hardware software and external breakpoints and provides access to internal registers and memory through a JTAG module Support for a wide variety of third party development and debugging tools the current list of support tools is available at http www infineon com Asynchronous synchronous serial channel ASC High speed synchronous serial channel SSC General purpose timer block GPT12E Ports I O module that provides programmable external bus or general purpose I O port functionality April 2003 DesignWare IP Family Quick Reference Guide DW C166S 16 Bit Processor from Infineon PAD interface External Bus Memory XBus Periph Local Memory LM66 Control Signals Dedicated Pins C166S Core Clock Enable Generator Subsystem Control Block Interrupt Requests 4 PDBus Peripherals Interfaces Debug JTAG Module Clock Interface T Clock Enables C166S Subsystem Block Diagram Also see the following web page for additional information http www synopsys com products designware starip infineon c166s html April 2003 Synops
150. efficient and designed for low to medium sampling rates It processes one filter tap per clock cycle An N order filter therefore processes one sample every N clock cycles The processor consists of a finite state machine coefficient and data memory and an arithmetic datapath Both components have parameterized data coefficient and accumulator word lengths parameterized filter order and serially loadable coefficients For more information about the DSP IP refer to the DesignWare DSP and GTECH Libraries Databook GTECH Library Overview Synopsys provides the GTECH technology independent library to aid users in developing technology independent parts Also DesignWare IP often use these cells for their implementation This generic technology library called gtech db contains common logic elements gtech db can be found under the Synopsys root directory in libraries syn Simulation models are located under the Synopsys root directory in packages gtech src VHDL and packages gtech src ver Verilog For more information about the GTECH IP refer to the DesignWare DSP and GTECH Libraries Databook 230 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 2 DesignWare Synthesizable IP AMBA On Chip Bus Logic and Peripherals IP AMBA is a standard bus architecture system developed by ARM for rapid development of processor driven systems AMBA also allows a number of bus peripherals and resources to be conn
151. el BFM for the Receiver part of the IEEE 802 3 Ethernet MAC The following types of operations are performed by the enetrx_fx model during decapsulation Address recognition Frame check sequence validation and Frame disassembly e enethub fx The enethub fx FlexModel provides the functionality of the 10 100 MBPS MII The following types of operations are performed by the model acts as a common PHY for all MACS connected on its MII ports and propagates the transmitted data from the transmitting MAC to all the MACS in the system e rmiirs fx The RMII interface is a low pin count MII interface intended for use between the ethernet PHY and switch or repeater ASICSs The interface has the following features supports 10 Mb s and 100 Mb s data rates single clock reference is sourced from the MAC to PHY or from an external source and independent 2 bit wide transmit and receive paths HUB in full Duplex Mode rmiirs fx rmiirs fx rmii 2 rmii 2 enethub fx H 1 The individual DesignWare FlexModel databooks can be found with each model at http www synopsys com products designware ipdir 264 Synopsys Inc April 2003 by DesignWare IP Family Quick Reference Guide Q Mog PCI PCI X Bus Verification Models Ss pcimaster_fx pcislave_fx and pcimonitor_fx PCI PCI X Bus Verification Models pcimaster_fx pcislave_fx and pcimonitor_fx The Synopsys PCI PCI X FlexModel set consists of three
152. el DesignWare Foundation April 2003 Synopsys Inc 107 DesignWare IP Family Quick Reference Guide DW div fp Floating Point Divider Module Compiler Only DW div fp Floating Point Divider Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand and fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard TE Note OH The Floating Point Divider is designed specially for Module Compiler and does not work with Design Compiler Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Dividend B e f 1 bits Input Divisor Z e f 1 bits Output Quotient of A B STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point numbers A B and Z f 2 to 253 bits Word length of fraction field of floating point numbers A B and Z 108 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW div fp Floating Point Divider Module Compiler Only Table 2 Parameter Description Continued Parameter Values Description arch 1 2 and3
153. el DesignWare Foundation cl2 Full carry look ahead model Design Ware Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 130 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AT DW fifo s1 df Synchronous Single Clock FIFO with Dynamic Flags DW fifo s1 df Synchronous Single Clock FIFO with Dynamic Flags e Fully registered synchronous flag output ports push req n data i e D flip flop based memory array for high testability US pop req n data out e All operations execute in a single clock cycle ae level full e FIFO empty half full and full flags af thresh almost full E ii i half full e FIFO error flag indicating underflow overflow and diag n almost empty pointer corruption empty e Dynamically programmable almost full and almost gt clk joues A empty flags e Parameterized word width e Parameterized word depth e Parameterized reset mode synchronous or asynchronous memory array initialized or not Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 or 2 synchronous if rst mode 1 or 3 push_req_n 1
154. ementation Table 1 Pin Description Pin Name Width Direction Function rst n bit Input Reset active low cs n bit Input Chip select active low wr n bit Input Write enable active low rd addr ceil log5 depth bit s Input Read address bus wr addr ceil log5 depth bit s Input Write address bus data in data width bit s Input Input data bus data out data width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data width 1to256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width rst mode O or 1 Determines if the rst_n input is used O rst n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 165 DesignWare IP Family Quick Reference Guide A DW_ram_2r_w_a_dff RAM Write Port Dual Read Port RAM Flip Flop Based 01101001 DW ram 2r w a dff Write Port Dual Read Port RAM Flip Flop Based e Parameterized word depth rdi addr rd2_addr e Parameterized data width wr_addr data_in e Asynchronous static memory data rdi out cs n data rd2 out e Parameterized reset implementation Wen e High testability using DFT Compiler test mode i test clk rst n Table 1
155. ementations Implementation Name Implementation License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none bk Brent Kung architecture synthesis model DesignWare Foundation clf Fast carry look ahead synthesis model DesignWare Foundation csm Conditional sum synthesis model DesignWare Foundation rpcs Ripple carry select architecture Design Ware Foundation clsat MC inside DW carry look ahead select DesignWare Foundation April 2003 Synopsys Inc 37 DesignWare IP Family Quick Reference Guide DWO01 addsub Adder Subtractor Table 3 Synthesis Implementations Continued Implementation Name Implementation License Required csa MC inside DW carry select DesignWare Foundation fastcla MC inside DW fast carry look ahead Design Ware Foundation pprefix MC inside DW flexible parallel prefix DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The performance of the csm implementation is heavily dependent on the use of a high performance inverting 2 to 1 MUX in the technology library In such libraries the csm implementation exhibits a superior area delay product Although the csm i
156. ent control 0 2 unsigned 1 signed MAC A width B width bit s Output MAC result A x B C Table 2 Parameter Description Parameter Values Description A width 21 Word length of A B width gt 1 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation wall synthesis model Booth recoded Wallace tree DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP 62 User Guide Synopsys Inc April 2003 MAC DesignWare IP Family Quick Reference Guide DW minmax Minimum Maximum Value DW minmax Minimum Maximum Value e Parameterized number of inputs value e Parameterized word length le min max index e Unsigned and signed two s complement data operation e Dynamically selectable mode minimum or maximum e Additional output gives an index of the minimum or maximum input e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function a num inputs X width bit s Input Concatenated input data tc 1 bit Input Two s complement control min max bit Input Minimum maximum con
157. er e Parameterized word lengths e Unsigned and signed two s complement data operation Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Multiplier ic 1 bit Input Two s complement control 0 unsigned 1 signed out0 width x 2 Output Partial product of a x a bit s outl width x 2 Output Partial product ofa x a bit s Table 2 Parameter Description Parameter Values Description width 21 Word length of signal a Table 3 Synthesis Implementations Implementation Name Function License Required wall Wallace tree synthesis mode DesignWare Foundation 86 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW sqrt Combinational Square Root DW sqrt Combinational Square Root e Parameterized word length e Unsigned and signed two s complement square root computation Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Radicand root int width 1 2 bit s Output Square root Table 2 Parameter Description Parameter Values Description width 22 Word length of a tc mode 0 or 1 Two s complement control Default 0 0 unsigned 1 signed Table 3 Synthesis Implementations Implementation Name Function License Required rpl Restoring ripple carry synthesis model DesignWare Foundation cla Restori
158. er Values Description A width 21 Word length of A B width 21 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model none nbw Non Booth recoded Wallace tree synthesis Design Ware Foundation model wall Booth recoded Wallace tree synthesis model DesignWare Foundation mcarch MC inside DW Wallace tree Design Ware Foundation csmult MC inside DW flexible Booth Wallace DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 64 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO02 mult Multiplier b In most cases the nbw implementation generates the fastest and smallest circuits for small to medium sized multipliers For multipliers having products larger than 41 bits such as A width B width gt 41 the nbw implementation would prove of no benefit So for products larger than 41 bits the nbw implementation will produce a Booth recoded multiplier identical to the wall implementation c In most cases the wall implementation generates faster and smaller circuits for medium to large sized multipliers d Automatically sele
159. er Description Parameter Values Description n 2to 32 Number of arbiter clients Default 4 park mode Oorl park mode 1 includes logic to enable parking when no Default 1 clients are requesting and park mode 0 contains no logic for parking park index O to nd Index of the client used for parking Default 0 output mode O0 or 1 output mode includes registers at the outputs Default 1 output mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple synthesis model DesignWare Foundation cla Carry look ahead synthesis model DesignWare Foundation April 2003 Synopsys Inc 229 DSP Library Overview DesignWare IP Family Quick Reference Guide DSP Library Overview The DesignWare DSP Library consists of two digital FIR filter components designed for applications requiring programmable coefficients and either high speed or area efficient filtering DWO 7 fir100 is a high speed FIR Filter with a word parallel transposed canonical architecture It processes one sample per clock cycle Because of its inherent pipelining the clock rate is essentially independent of the filter order allowing for the implementation of very large order filters It is also easily cascaded to help partition large order filters DWO 7 fir110 is an FIR Filter processor with a word serial architecture that is area
160. er features include the following The dwcore jpeg codec data sheet is available at April 2003 100 baseline ISO IEC 10918 1 JPEG compliant Verified in hardware 8 bit channel pixel depths Up to four programmable quantization tables Single clock Huffman coding and decoding Fully programmable Huffman tables two AC and two DC Fully programmable Minimum Coded Unit MCU Encoding decode support non simultaneous Single clock per pixel encoding and decoding according to the JPEG baseline algorithm Support for up to four channels of component color Four channel interface e Simple external interface Low gate count total gate count is 33K gates Stallable design e Hardware support for restart marker insertion Support for single grayscale components e Internal register interface Fully synchronous design Available as fully functional and synthesizable VHDL or Verilog e Includes testbench Individual Encoder and Decoder products are available from Synopsys http www synopsys com products designware docs ds c dwcore_jpeg_codec pdf Synopsys Inc 295 DesignWare IP Family Quick Reference Guide dwcore jpeg2 codec Synthesizable JPEG2000 CODEC dwcore jpeg2 codec Synthesizable JPEG2000 CODEC e Significantly crisper graphics and text than with JPEG even at compression ratios exceeding 60 1 e On the fly lossless and lossy compression applications through the reversible 5 3 wavel
161. er with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function wen 1 bit Output Write enable output for write port of RAM active low push empty 1 bit Output FIFO empty output flag synchronous to clk push active high push ae 1 bit Output FIFO almost empty output flag synchronous to clk push active high determined by push ae lvl parameter push hf 1 bit Output FIFO half full output flag synchronous to clk push active high push af 1 bit Output FIFO almost full output flag synchronous to clk push active high determined by push af lvl parameter push full 1 bit Output FIFO s RAM full output flag including the input buffer of FIFO controller for data in width lt data out width synchronous to clk push active high ram full 1 bit Output FIFO s RAM excluding the input buffer of FIFO controller for data in width data out width full output flag synchronous to clk push active high part wd 1 bit Output Partial word accumulated in the input buffer synchronous to clk push active high for data in width data out width only otherwise tied low push error 1 bit Output FIFO push error overrun output flag synchronous to clk push active high pop empty 1 bit Output FIFO empty 5 output flag synchronous to clk pop active high pop ae
162. ered outputs Default 1 0 2 no 1 yes early_start Oor 1 Computation start Default 0 0 start computation in the second cycle 1 start computation in the first cycle Table 3 Synthesis Implementations Implementation Function License Required cpa Carry propagate adder synthesis model Design Ware Foundation 100 Synopsys Inc April 2003 f DW mult seq Sequential Multiplier e Parameterized word length e Parameterized number of clock cycles e Unsigned and signed two s complement data multiplication e Registered or un registered inputs and outputs DesignWare IP Family Quick Reference Guide DW mult seq Sequential Multiplier Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low hold 1 bit Input Hold current operation 1 start 1 bit Input Start operation 1 A new operation is started again by making start 1 for one clock cycle a a_width bit s Input Multiplier b b_width bit s Input Multiplicand complete 1 bit Output Operation completed 1 product a_width b_width bit s Output Product a x b Table 2 Parameter Description Parameter Values Description a_width 23 and lt b_width Word length of a b_width 23 Word length of b tc mode Oor 1 Two s complement control Default 0 0 unsigned 1 two s complement num_cyc 23 and Xa width User defined n
163. error e Parameterized reset mode synchronous or asynchronous e Interfaces with common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst mode 1 push req n 1 bit Input Stack push request active low pop_req_n 1 bit Input Stack pop request active low we_n 1 bit Output Write enable for RAM write port active low empty 1 bit Output Stack empty flag active high full 1 bit Output Stack full flag active high error 1 bit Output Stack error output active high wr addr ceil log5 depth bit s Output Address output to write port of RAM rd addr ceil log5 depth bit s Output Address output to read port of RAM 174 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW stackctl Synchronous Single Clock Stack Controller Table 2 Parameter Description Parameter Values Function eu 2 to 274 Number of memory elements in the stack used to Default None size the address ports err mode Oor 1 Error mode Default 0 0 underflow overflow error hold until reset 1 underflow overflow error hold until next clock rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset
164. esign requirements FIFOs which include dual port RAM memory arrays are offered for both synchronous and asynchronous interfaces The memory arrays are offered in two configurations latch based to minimize area and D flip flop based to maximize testability These two configurations also offer flexibility when working under design constraints such as a requirement that no latches be employed Flip flop based designs employ no clock gating to minimize skew and maximize performance All FIFOs employ a FIFO RAM controller architecture in which there is no extended fall through time required before reading contents just written Also offered are FIFO Controllers without the RAM array They consist of control and flag logic and an interface to common ASIC dual port RAMs Choosing between the two is typically based on the required size of the FIFO For shallow FIFOs less than 256 bits synchronous or asynchronous FIFOs are available which include both memory and control in a single macro These macros can be programmed via word width depth and level almost full flag parameters Memory FIFO Overview For larger applications greater than 256 bits you can use the asynchronous FIFO Controller with a diffused or metal programmable RAM See Figure 1 Technology independent FIFO FIFO Controller to be used with a that includes control and memory technology specific vendor supplied RAM Synthetic Designs FIFO Synthetic Designs includes
165. et to 0 Table 3 Synthesis Implementations Implementation Name Function License Required archO Synthesis model DesignWare Foundation 112 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Memory Registers Memory Registers This section documents the various memory registers found in the library of DesignWare Building Block IP April 2003 Synopsys Inc 113 DesignWare IP Family Quick Reference Guide DWOS3 pipe reg Pipeline Register DWO3 pipe reg Pipeline Register 114 e Parameterized data width and depth clk Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data bus clk 1 bit Input Clock B width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description depth 21 Depth of registers width 21 Width of A and B buses Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWOS3 reg s pl Register with Synchronous Enable Reset DWOS reg s pl Register with Synchronous Enable Reset e Parameterizable data width d e Parameterized reset to any constant value enable e Multiple synthesis implementations gt clk reset_N Table
166. et transform e Fully compliant with the ISO IEC JTC 1 SC 29 WG 1 ITU T SG8 specification e JPEG2000 encoding and decoding operations e Reduced gate count through real time configuration of modules for encoding or decoding e Programmable pixel depths for up to 10 bits per component e Simple and efficient flow control for variable rate pixel and code input to the CODEC e Configurable maximum tile and precinct dimensions Co Ys Programmable code block size precinct size number of levels of decomposition and quantization tables on individual tile basis to allow for customizable compression ratios Generates and parses inbitstream markers to minimize external header processing e Packet header coding and decoding Arithmetic encoding termination at the end of each code block for higher compression ratios Easy to integrate CPU interface that allows access to all programmable registers Available in fully functional and synthesizable Verilog RTL Comprehensive test environment Fully synchronous design The dwcore jpeg2 codec data sheet is available at http www synopsys com products designware docs ds c dwcore jpeg2 codec pdf 296 Synopsys Inc April 2003 C eg dwcore jpeg2 encod Synthesizable JPEG2000 ENCODER DesignWare IP Family Quick Reference Guide dwcore jpeg2 encod Synthesizable JPEG2000 ENCODER The Synopsys DesignWare JPEG2000 Encoder compresses input image tiles and generates pac
167. fcfs Arbiter with First Come First Served Priority Scheme e Parameterizable number of clients e Programmable mask for all clients e Park feature default grant when no requests are pending e Lock feature ability to lock the currently granted client Registered unregistered outputs request mask lock grant grant index granted Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Active low input reset request n bit s Input Input request from clients lock n bit s Input Active high signal to lock the grant to the current request By setting lock i 1 the arbiter is locked to the request i if it is currently granted For lock i 0 the lock on the arbiter is removed mask n bit s Input Active high input to mask specific clients By setting mask 7 1 request i is masked For mask i 0 the mask on the request 7 is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to park_index granted 1 bit Output Flag to indicate that arbiter has issued a grant to one of the clients locked 1 bit Output Flags that the arbiter is locked by a client grant n bit s Output Grant output grant index ceil log5n bit s Output Index of the requesting client that has been currently granted or the client designated by park index in park mode
168. fz USB 2 0 Transceiver Macrocell Interface amp Universal Serial Bus 2 0 Host page 266 Verification Model 1eee1394a fx IEEE 13944 PHY LINK Verification Model Sio txrx vmt sio monitor vmt Serial Input Output Interface Models page 261 Verification Models 20 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Board and FPGA Verification IP The DesignWare Library contains over 18 500 simulation models for ASIC SoC FPGA and Board verification For a complete search visit http www synopsys com ipdirectory Chapter 1 Overview Component Group Component Reference VMT Models Refer to DesignWare VMT Models on page 256 FlexModels Refer to DesignWare FlexModels on page 262 DesignWare Memory Models Refer to DesignWare Memory Models on page 267 SmartModel Library Refer to DesignWare SmartModels on page 268 DesignWare Verification Library The DesignWare Verification Library a subset of the DesignWare Library contains reusable pre verified verification IP of the industry s most popular bus and interface standards Design Views for Star IP processor cores and over 10 000 memory models The following table identifies the various components that make up this library Component Name Component Description Component Type AMBA AHB Models refer to page 258 ahb bus vmt
169. gned sh sh mode bit Input Arithmetic or barrel shift mode 0 barrel shift mode 1 arithmetic shift mode data out data width bit s Output Output data Table 2 Parameter Description Parameter Values Description data width 22 Word length of data in and data out sh width 1 to ceil logs data_width 1 Word length of sh inv mode 0 to3 logic mode Default 0 0 normal input 0 padding in output 1 normal input 1 padding in output 2 inverted input 0 padding in output 3 inverted input 1 padding in output a Inverted input refers to sh sh tc and data tc pins only April 2003 Synopsys Inc 83 DesignWare IP Family Quick Reference Guide DW shifter Combined Arithmetic and Barrel Shifter 84 Table 3 Synthesis Implementations Implementation Name Function License Required mx2 Implement using 2 1 multiplexers only DesignWare Foundation mx2i Implement using 2 1 inverting DesignWare Foundation multiplexers and 2 1 multiplexers mx4 Implement using 4 1 and 2 1 DesignWare Foundation multiplexers mx8 Implement using 8 1 4 1 and 2 1 Design Ware Foundation multiplexers Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW square Integer Squarer DW square Integer Squarer e Parameterized word length 2 tc e Unsigned and signed two s complement da
170. ibra Visa LRC Mars Mars Rail Mars Xtalk Medici Metacapture Metacircuit Metamanager Metamixsim Milkyway ModelSource Module Compiler MS 3200 MS 3400 NanoSim Nova Product Family Nova ExploreRTL Nova Trans Nova VeriLint Nova VHDLlint OpenVera Optimum Silicon Orion ec Parasitic View Passport Planet Planet PL Planet RTL Polaris Polaris CBS Polaris MT Power Compiler PowerCODE PowerGate ProFPGA Progen Prospector Proteus OPC Protocol Compiler PSMGen Raphael NES RoadRunner RTL Analyzer Saber Co Simulation Saber for IC Design SaberDesigner SaberGuide SaberRT SaberScope SaberSketch Saturn ScanBand Schematic Compiler Scirocco Scirocco i Shadow Debugger Silicon Blueprint Silicon Early Access SinglePass SoC Smart Extraction SmartLicense SmartModel Library Softwire Source Level Design Star Star DC Star Hspice Star HspiceLink Star MS Star MTB Star Power Star Rail Star RC Star RCXT Star Sim Star Sim XT Star Time Star XP SWIFT Taurus Taurus Device Taurus Layout Taurus Lithography Taurus OPC Taurus Process Taurus Topography Taurus Visual Taurus Workbench Test Compiler TestGen TetraMAX TenX The Power in Semiconductors TheHDL TimeSlice TimeTracker Timing Annotator TopoPlace TopoRoute Trace On Demand True Hspice TSUPREM 4 TymeWare VCS VCS Express VCSi Venus Verification Portal VFormal VHDL Compiler VHDL System Simulator VirSim and VMC are trademarks of Synopsys Inc Serv
171. ibrary The DesignWare Library provides designers with a comprehensive collection of synthesizable and verification IP The library contains the following principal ingredients for ASIC SoC and FPGA design and verification e Building Block IP Datapath Data Integrity Test e AMBA On Chip Bus Logic Peripherals amp Verification Models e Complete Memory Portfolio Memory Models Memory BIST Memory Controller e Verification Models of the most popular Bus and I O Standards PCI PCI X PCI Express USB 2 0 e Popular Processor Cores from Industry Leading IP Vendors IBM Infineon MIPS NEC e Board and FPGA Verification IP A single license gives you access to all the IP in the library For more information on the DesignWare Library refer to the following http www synopsys com products designware or send email at designware synopsys com For a detailed search of the available IP refer to the following http www synopsys com ipdirectory 16 Synopsys Inc April 2003 DesignWare IP Fami ly Quick Reference Guide Building Block IP The DesignWare Building Block IP is a collection of over 140 technology independent high quality high performance IP Most of these IP elements include multiple implementations to provide a variety of performance and area tradeoff options Chapter 1 Overview Component groups for the Building Block IP are identified in the following table For more detail refer to Building Blo
172. ice Marks SV DesignSphere SVP Caf and TAP in are service marks of Synopsys Inc SystemC is a trademark of the Open SystemC Initiative and is used under license All other product or company names may be trademarks of their respective owners Printed in the U S A 2 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Contents Contents l l lo EUM 11 About Ths Mammal oc evs eds Reus v5 A TRERENSRRECREPIXA CUN REX T EU R 11 Manual EVIE 6455 64a 6h Se Gs 6 naie EE he diced 11 Typographical and Symbol Conventions isses raa d rax eR HIER aen 12 Synopsys Common Licensing SCL qasscassesuh sake REA RR RA RES ass 12 Po es uera bl edd t DIY eee ere eee ere ee eee ee er rer re 13 Additional Information 1 accessit eh eee ee ee eae dad Re 13 COMMEN ee ee ee ee rene eer ee Sere abd er ree Sarre err ee ere 13 Chapter 1 DWOFVIEW ee ee ee ee ee eee er ee eer AO rr eee eee C 15 Be GLO 1455000 4ee teed d Hebr aon EE Rh E e 16 Building Block IP uouodqeua uw xir wen dcr ids kE REAREA wh RRR eRe 17 AMBA Unt np BUS duasewrdatkeer dub ada t Tap Ead add Rt deda dads 17 Microprocessors Microcontroller Cores sass 44 4 xr RO o ERR RE OO 19 Memory MP aaasesq e Xo d euadere S aeu dorda qa xe wea eqdceua di henna 20 Verification Models of Bus and I O Standards 000 20 Des and FPGA VEHI BUR IP 4 4 3 a Ro CR ER ERR RO GE DECOR Rea 21 DesignWare Verification Library quesa ukeSeeXs4AxGureedE eh QESATY des ERE 21
173. idth Direction Function clk 1 bit Input Clock rst n bit Input Reset active low cs n bit Input Chip select active low wr n 1 bit Input Write enable active low rdl addr ceil log depth bit s Input Read1 address bus rd2_addr ceil log depth bit s Input Read2 address bus wr addr ceil log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data rdl out data width bit s Output Output data bus for read1 data rd2 out data width bit s Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data width to 256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width rst mode Oor 1 Determines the reset methodology 0 rst n asynchronously initializes the RAM 1 rst_n synchronously initializes the RAM 158 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 RAM DW_ram_2r_w_s_dff 01101001 Synchronous Write Port Asynchronous Dual Read Port RAM Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 159 DesignWare IP Family Quick Reference Guide DW ram 2r w s lat Synchronous Write Port Asynchronous Dual Read Port RAM Latch Based DW ram 2r w s lat Synchronous Write Port Asynchronous Dual Read Port RAM Latch Based e Parameterized word depth
174. igure testbenches to execute transactions transaction sequences or transaction choice sets weighted by any configurable parameter Provide file or random payloads for those transactions The following list identifies the VMT models that are part of the DesignWare AMBA On Chip Bus OCB solution e AMBA Advanced High Performance Bus AHB Models ahb master vmt ahb slave vmt ahb monitor vmt ahb bus vmt ahb act monitor vmt See page 258 e AMBA Advanced Peripheral Bus APB Models apb master vmt apb slave vmt apb monitor vmt See page 260 256 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide The following list identifies additional VMT models e pciexpress vmt e sio txrx vmt sio monitor vmt See page 261 A brief introduction to the AMBA On Chip Bus can be found at the following location http www synopsys com products designware dw amba html April 2003 Synopsys Inc 257 DesignWare IP Family Quick Reference Guide AMBA AHB Models ahb master vmt ahb slave vmt ahb monitor vmt ahb bus vmt AMBA AHB Models ahb master vmt ahb slave vmt ahb monitor vmt ahb bus vmt ahb act monitor vmt All Models AHB Bus e Multiple command streams Up to 15 Masters and 15 Slaves Verilog VHDL or VERA testbenches Unlimited Slave memory maps Configurable message formatting Priority based arbitration algorithm Interrupt driven testbenches All types of Master transfers All types of Slave responses Configur
175. iler II 30 FPGA Verification 21 G GTECH Library Overview 230 H Help with products 13 316 Synopsys Inc DesignWare IP Family Quick Reference Guide Interfaces SWIFT connection for SmartModels IP Synthesizable See also DesignWare Library Synthesizable IP L Licensing for Synopsys products 12 M Memory IP 249 Memory IP listing 20 Memory Models See also DesignWare Memory Models Mezoe Interface Express 310 Microprocessors Microcontroller Cores Microprocessors Microcontroller Cores listing 19 Models behavioral 268 FlexModels 262 SmartModel behavioral simulation 268 VMT 256 Module Compiler 105 P PCI PCI X Bus Verification Models 265 pcimaster fx 265 pcimonitor fx 265 pcislave fx 265 rmiirs fx 264 S SCL 12 sio monitor vmt 261 sio txrx vmt 261 April 2003 DesignWare IP Family Quick Reference Guide SmartModel Library SWIFT interface connection through 268 SmartModels listed in IP Directory Web site 268 SMC USB 2 0 PHY 311 Star IP Core DW CI166S 304 DW IBMA40 300 DW MIPSAKE 308 DW TriCorel 306 DW V850E Star 302 Mezoe Interface Express 310 SMSC USB 2 0 PHY 311 Star IP overview 299 SWIFT interface connection between SmartModels and simulators 268 Synopsys Common Licensing 12 Synthesizable IP See also DesignWare Library Synthesizable IP U USB 1 1 2 0 Bus Host Interface Model 266 usbhost fz 266 V Verification IP overview 255 Verification Models of Bus and
176. ility APB Monitor AAAAAA APB APB a dE EN Slave 1 Slave 2 APB Master Ve AHB APB Bridge Slave 3 Slave 4 The DesignWare APB Verification IP Databook is available at http www synopsys com products designware docs 260 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Serial Input Output Interface Models sio txrx vmt sio monitor vmt Serial Input Output Interface Models sio txrx vmt sio monitor vmt SIO TxRx Model SIO Monitor Model e Full duplex operation e Protocol checking e Fully configurable serial interface e Transaction logging e Both GPIO and SIO port interfaces e Watchpoint monitoring e Configurable receive FIFO depth e Configurable to match TxRx model e Configurable internal baud clock e Configurable internal baud clock e Programmable hardware flow control e Programmable hardware flow control e IrDA SIR infrared mode support e IrDA SIR infrared mode support e Error generation injection capability e Parity generation and checking e Parity generate check odd even none e Command set control e Robust command set control sin lt q ___ _______ sout sout sin cts n 8 rts_n rts n J cts n l DW apb uart sio txrx vmt or DUT i gpo n i pin presetn T rst n 0v Y Y N C sio monitor vmt The DesignWare
177. ily Quick Reference Guide DWO2 prod sum Generalized Sum of Products DWO02 prod sum Generalized Sum of Products e Parameterized number of inputs TC e Parameterized word length A SUM Table 1 Pin Description Pin Name Width Direction Function A A width x num inputs bit s Input Concatenated input data B B width x num inputs bit s Input Concatenated input data TC 1 bit Input Two s complement 0 2 unsigned 1 signed SUM SUM_width bit s Output Sum of products Table 2 Parameter Description Parameter Values Description A_width gt 1 Word length of A B width gt 18 Word length of B num_inputs 21 Number of inputs SUM_width 21 Word length of SUM a For nbw implementation A_width B_width 36 Due to concern of implementation selection run time a limitation is set for A_width and B_width Table 3 Synthesis Implementations Implementation Function License Required csa Carry save array synthesis model Design Ware Foundation wall Booth recoded Wallace tree synthesis model Design Ware Foundation nbw Non Booth recoded Wallace tree synthesis model DesignWare Foundation mcarch MC inside DW Wallace tree Design Ware Foundation csmult MC inside DW flexible Booth Wallace Design Ware Foundation April 2003 Synopsys Inc 75 DesignWare IP Family Quick Reference Guide DWO2 prod sum Generalized Sum of Products a During syn
178. in Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall mode 1 0 stall 1 load a a_width bit s Input Dividend b a_width bit s Input Divisor quotient a_width bit s Output Quotient a b remainder b width bit s Output Remainder Table 2 Parameter Description Parameter Values Description a_width gt 2 Word length of a Default None b_width gt 2 lt a width Word length of b Default None tc_mode O or 1 Two s complement control Default 0 0 unsigned 1 signed April 2003 Synopsys Inc 55 DesignWare IP Family Quick Reference Guide DW div pipe Stallable Pipelined Divider Table 2 Parameter Description Continued Parameter Values Description rem mode 0 or 1 Remainder output control Default 1 0 modulus 1 remainder num stages 2 Number of pipeline stages Default 2 stall mode 0or 1 Stall mode Default 1 0 non stallable 1 stallable rst_mode 0 to 2 Reset mode Default 1 0 no reset 1 asynchronous reset 2 synchronous reset Table 3 Synthesis Implementations Implementation Name Implementation License Required str Pipelined str synthesis model DesignWare Foundation a One of rpl cla or cl2 implementation is selected based the constraints of the design 56 Synopsys
179. in width 1 to 256 Width of the data in bus data in width must be in an integer multiple relationship with data out width That is either data in width K x data out width or data out width K x data in width where K is an integer data out width 1 to 256 Width of the data out bus data out width must be in an integer multiple relationship with data in width That is either data in width K x data out width or data out width K x data in width where K is an integer depth 4 to 224 Number of words that can be stored in FIFO push ae lvl 1 to depth 1 Almost empty level for the push ae output port the number of words in the FIFO at or below which the push ae flag is active push af lvl 1 to depth 1 Almost full level for the push af output port the number of empty memory locations in the FIFO at which the push af flag is active pop ae lvl 1 to depth 1 Almost empty level for the pop ae output port the number of words in the FIFO at or below which the pop ae flag is active pop af lvl 1 to depth 1 Almost full level for the pop af output port the number of empty memory locations in the FIFO at which the pop af flag is active err mode Oor 1 Error mode 0 stays active until reset latched active only as long as error condition exists unlatched 146 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifoctl s2 sf Asymmetric Synchronous Dual Clock FIFO Contro
180. ine o 32 bit datapath o Simultaneous transfer of instruction and data on separate e buses Harvard architecture o RISC architecture plus special E instructions for saturation bit manipulation and multiply using integrated hardware multiplier o 32 general purpose 32 bit registers See the block diagram on the following page 302 Synopsys Inc Instruction cache optional Data cache optional e Integrated 4 channel DMA optional Integrated interrupt controller supporting 3 external non maskable interrupts NMIs and up to 64 external maskable interrupts Integrated run control unit optional Separate interfaces to internal ROM and RAM V850E System Bus VSB interface to high speed peripherals NEC Peripheral Bus NPB interface to low speed peripherals Power management through HALT instruction and hardware or software generated stop mode implemented by standby control unit STBC Fully synchronous design April 2003 Sta lp System Config VFB Data Cache VDB DMA Interrupt System Control Clock and Reset Instruction Queue Program Counter General Purpose Registers System Registers Data Cache Interface DMA Control Unit DMAC Interrupt Control Unit INTC Standby Control Unit STBC System Controller DesignWare IP Family Quick Reference Guide Multiplier 32x32 gt 64 Barre
181. int Data formats bit byte 8 bits half word 16 bits word 32 bits double word 64 bits Zero overhead loop Instruction types arithmetic address comparison address comparison logical MAC shift coprocessor bit logical branch bit field load store packed data system MMU specific instructions Addressing modes absolute circular bit reverse long amp short base offset base offset with pre amp post update Multiply amp Accumulate MAC instructions dual 16 x 16 16 x 32 32x 32 On Chip Debug Support OCDS Levels 1 amp 2 April 2003 DesignWare IP Family Quick Reference Guide yp ID DW_TriCore1 TriCore1 32 Bit Processor Core from Infineon Program Tag Coprocessor Data Tag Interface Interface Interface Program Data Memory Memory Interface PMI CPU DMI tenets Local Memory Memory Bus BIST Lue Interface Interface Interrupt Controller Interrupt Interface Clock Reset and Control Debug Interface FPI Bus Interface Also see the following web page for additional information http www synopsys com products designware starip infineon_tricore1 html April 2003 Synopsys Inc 307 DesignWare IP Family Quick Reference Guide DW MIPSAKE Processor Core Family from MIPS DW_MIPS4KE Processor Core Family from MIPS Sta 5 The highly configurable MIPS32 4KE family represents the next generation of 32 bit MIPS cores Features include the following 308 32
182. ion option selects the serial clock phase of the SPI format directly after reset 243 DesignWare IP Family Quick Reference Guide DW apb ssi AMBA APB Synchronous Serial Interface DW apb ssi Transmit FIFO Shift APB Interface Control Control Logic Receive FIFO Control Register EIUS Transmit Interrupt FIFO Logic Memory Receive FIFO Memor 4 Clock Pre scale FSM Control The DesignWare DW_apb_ssi Databook is available at http www synopsys com products designware docs 244 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW apb timers AMBA APB Programmable Timers DW apb timers AMBA APB Programmable Timers e Upto eight programmable timers e Configurable option for a single or e Configurable timer width 8 to 32 bits SQUIDIN EAE a e Configurable option to have read write e Support for two operation modes free PP P coherency registers for each timer running and user defined count e Configurable option to include timer toggle output which toggles each time counter reloads e Support for independent clocking of timers e Configurable polarity for each individual interrupt e Component version ID register DW apb timers pclk p presetn APB psel Interface paddr __ timer N clk timer en timer N resetn timer intr scan mode
183. ions IDCODE INTEST RUNBIST CLAMP and HIGHZ e Optional use of device identification register and IDCODE instruction e Parameterized instruction register width clock dr shift dr update dr sync update dr tdo tdi tdo en SO sync capture en tck tms bypass sel tap state sentinel val extest samp load instructions j trst n Table 1 Pin Description Pin Name Width Direction Function tck bit Input Test clock trst n bit Input Test reset active low tms 1 bit Input Test mode select tdi 1 bit Input Test data in So 1 bit Input Serial data from boundary scan register and data registers bypass sel 1 bit Input Selects the bypass register active high sentinel val width 1 bit s Input User defined status bits clock dr 1 bit Output Clocks in data in asynchronous mode shift dr 1 bit Output Enables shifting of data in both synchronous and asynchronous mode update dr 1 bit Output Enables updating data in asynchronous mode tdo 1 bit Output Test data out tdo en bit Output Enable for tdo output buffer tap state 16 bits Output Current state of the TAP finite state machine extest 1 bit Output EXTEST decoded instruction samp load bit Output SAMPLE PRELOAD decoded instruction instructions width bit s Output Instruction register output 190 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW tap TAP
184. it s Input Input data c width bit s Input Input data ci 1 bit Input Carry in carry width bit s Output Carry output data sum width bit s Output Sum output data co 1 bit Output Carry out Table 2 Parameter Description Parameter Values Description width 21 Word length of a b c sum and carry Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 51 DesignWare IP Family Quick Reference Guide DWO1 dec Decrementer DWO01 dec Decrementer e Parameterized word length Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data SUM width bit s Output Decremented A 1 Table 2 Parameter Description Parameter Values Description width 21 Word length of A and SUM Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare Foundation clsa MC inside DW carry look ahead select DesignWare Foundation csa MC inside DW carry select DesignWare Foundation fastcla MC inside DW fast carry look ahead DesignWare Foundation pprefixP MC inside DW flexible parallel prefix
185. kets of coded data performing all computationally intensive tile encoding processes as specified in the JPEG committee standard ISO IEC JTC 1 SC 29 WG 1 ITU T SG8 The simplicity and configurability of the design facilitate easy System on Chip SoC integration and high compression quality making it ideal for color printing applications such as facsimile and scanning and digital image applications including Internet photography remote sensing mobile wireless medical and e commerce markets Other features include the following Significantly crisper graphics and text than with JPEG even at compression ratios exceeding 50 1 Fully compliant with the ISO TEC JTC 1 SC 29 WGI1 ITU T SG8 standard Supports lossless and lossy compression applications through the reversible 5 3 wavelet transformer 10 bit pixel depths Simple and efficient flow control supports variable rates of pixel input to the encoder Configurable maximum tile and precinct dimensions Code block size precinct size number of decomposition levels and quantization tables are programmable on an individual tile basis enabling customizable compression ratios Generates in bit stream markers to minimize external header processing Supports packet header information coding Arithmetic encoder termination at the end of each code block for higher compression ratios Easily integrated CPU interface allows access to all programmable registers Available as fu
186. ks When the APB clock pclk and the DW_apb_ssi serial clock ssi_clk are synchronous meta stable flip flops are not used when bringing control signals across these clock domains Component version ID register DesignWare IP Family Quick Reference Guide DW_apb ssi AMBA APB Synchronous Serial Interface e Programmable features O Serial interface operation User can choose from Motorola SPI Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire Clock bit rate User can dynamically control the serial bit rate of the data transfer Used only in serial master mode of operation Data frame size 4 to 16 bits The frame size of each data transfer is under the control of the programmer e Configurable features O Synopsys Inc FIFO depth User can configure the depth of the transmit and receive FIFO buffers to 1 to 256 words deep The FIFO width is fixed at 16 bits Number of slave select outputs When operating as a serial master 1 to 16 serial slave select output signals can be generated Hardware software slave select Dedicated hardware slave select lines can be used or software control can be used to target the serial slave device Combined or individual interrupt lines The user may choose to bring all individual interrupt lines or one combined interrupt line from the MacroCell to the interrupt controller Interrupt polarity This configurat
187. l Shifter DW_V850E Star V850E Processor Core from NEC Run Control Unit RCU Instruction Cache Interface Bus Control Unit BCU V850E Star Block Diagram Also see the following web page for additional information http www synopsys com products designware starip nec_v850e html April 2003 Synopsys Inc N Wire Interface Instr Cache VSB NPB 303 DesignWare IP Family Quick Reference Guide DW C166S 16 Bit Processor from Infineon DW C166S 16 Bit Processor from Infineon Ss 5 The Infineon C166S is a highly configurable fully synthesizable processor core based on the successful C166 microcontroller IC family and is 100 instruction set compatible Other features include the following 304 Four stage pipelined fully static 16 bit CPU CPU speed up to 80 MHz in 0 18 micron technology Compatible with standard C166 instruction set Up to 16 MB addressable memory space Optional multiplier accumulator MAC unit Integrated On Chip Debugging System OCDS Most instructions execute in a single instruction cycle 2 CPU clock cycles Multiple register banks with single instruction cycle context switching 16x16 multiplication in 5 instruction cycles 32 16 division in 10 instruction cycles Multiple high bandwidth internal data buses also available externally XBus Local Memory bus Dual Port RAM bus PDBus Up to 112 interrupt nodes 15 of which are us
188. lag data out width bit s Output Recovered output data stream a The minimum value must be 1 April 2003 Synopsys Inc 211 DesignWare IP Family Quick Reference Guide ae DW_dbpll_sd Digital Phase Locked Loop Table 2 Parameter Description Parameter Values Description width 1 to 16 Number of input serial channels Default 1 divisor 4 to 256 Determines the number of samples per input clock cycle Default 4 gain 1 to2 Phase correction factor for the absolute value of clock phase Default 1 error greater than Ill 1 5096 phase correction 2 100 phase correction filter 0 to 8 Phase correction control for 1 clock phase error region Default 2 0 no correction 1 always correct For integer N gt 1 correct after N samples at a current phase such as N consecutive samples at 1 or N consecutive samples at 1 windows 1 to divisor 1 2 Number of sampling windows for the input serial data stream Default 1 Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple synthesis model DesignWare Foundation cla Carry look ahead architecture DesignWare Foundation synthesis model a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details
189. ll flag is active err mode 0to2 Error mode Default 0 0 underflow overflow and pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cll Partial carry look ahead model Design Ware Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 151 DesignWare IP Family Quick Reference Guide DW fifoctl s2 sf Synchronous Dual Clock FIFO Controller with Static Flags DW fifoctl s2 sf Synchronous Dual Clock FIFO Controller with Static Flags e Fully registered synchronous flag output ports e Single clock cycle push and pop operations e Separate status flags for each clock system e FIFO empty half full and full flags e FIFO push error overflow and pop error underflow flags e Parameterized word depth e Parameterized almost full and almost empty flag thresholds e Interfaces to common hard macro or compiled ASIC dual port s
190. ller with Static Flags Table 2 Parameter Description Continued Parameter Values Description push sync 1 to3 Push flag synchronization mode 1 single register synchronization from pop pointer 2 double register 3 triple register pop sync 1 to3 Pop flag synchronization mode 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode Oor 1 Reset mode 0 asynchronous reset 1 synchronous reset byte_order Oor 1 Order of bytes or subword within a word Default 0 0 first byte is in most significant bits position 1 first byte is in the least significant bits position Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 147 DesignWare IP Family Quick Reference Guide DW fifoctl s1 df nnn Synchronous Single Clock FIFO Controller with Dynamic Flags DW fifoctl s1 df Synchronous Single Clock FIFO Controller with Dynamic Flags e Fully registered syn
191. lly functional and synthesizable source code Includes a comprehensive test environment Fully synchronous design The dwcore_jpeg2_encod data sheet is available at April 2003 http www synopsys com products designware docs ds c dwcore jpeg2 encod pdf Synopsys Inc 297 DesignWare IP Family Quick Reference Guide dwcore jpeg2 encod Synthesizable JPEG2000 ENCODER 298 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 5 DesignWare Star IP o DesignWare Star IP Design engineers who use the DesignWare Library have the ability to evaluate and design easily at their desktop using the following high performance high value IP cores from leading Star IP providers Component Name Component Description Component Type DW IBMA440 PowerPC 440 Microprocessor Core from Synthesizable RTL Available Q2 03 IBM page 300 Verification Model DW V850E Star V850E Processor Core from NEC page 302 Synthesizable RTL Verification Model DW_C166S 16 bit Processor from Infineon page 304 Synthesizable RTL Verification Model DW TriCorel TriCorel 32 Bit Processor Core from Synthesizable RTL Infineon page 306 Verification Model DW MIPSAKE Processor Core Family from MIPS Synthesizable RTL page 308 Verification Model Mezoe Interface Express Interface Express Toolkit including Software BlueStack Protocol stack with Profiles and ProtoDeveloper Software page 310 S
192. lso applied to reduce the number of carry propagations in magnitude comparisons of complete sum of products Resource and common subexpression sharing allow for further area savings The datapath generators then perform a constraint and technology driven synthesis of the extracted sum of product and product of sum blocks Enhanced algorithms are used to construct optimized adder reduction trees and carry propagate adders to meet the given timing constraints with minimal area requirements for the specified technology and conditions A smart generation feature selects the best among alternative implementation variants Special datapath library cells are automatically used where available and beneficial Optimized structures are generated for special arithmetic operations like constant multiplication or squaring 32 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 2 Datapath Arithmetic Overview Datapath Arithmetic Overview The datapath arithmetic DesignWare Building Block IP many of which are inferred are applicable to ASIC or FPGA designs These IP are high performance arithmetic implementations based on a fast carry look ahead architecture to augment those in the Basic IP Library The Basic IP Library is included in your V HDL Compiler product Most IP in this category have multiple architectures for each function architecturally optimized for either performance or area This provides you with the best archi
193. ltiplicand TC 1 bit Input Two s complement 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B width 2 For csa architecture A width B width x48 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation str Booth recoded Wallace tree synthesis model Design Ware Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A width and B width 348 bits as it has no area benefit beyond 48 bits 70 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO02 mult 6 stage Six Stage Pipelined Multiplier DWO02 mult 6 stage Six Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation e Six stage pipelined architecture e Automatic pipeline retiming e Inferable from Behavioral Compiler Table 1 Pin De
194. memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 137 DesignWare IP Family Quick Reference Guide DW asymfifoctl s1 df nn Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic F DW asymfifoctl s1 df Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic Flags e Fully registered synchronous address and flag output push req n data out ports data in Mrd TE d dat wr_cata e All operations execute in a single clock cycle HERE w en op req n e FIFO empty half full and full flags Boies C TUER ram full e Asymmetric input and output bit widths must be nece part wd integer multiple relationship ar ihrash full e Word integrity flag for flush n uc data in width lt data out width diag n amesten e Flushing out partial word for empty data in width lt data out width Em error e Parameterized byte order within a word e FIFO error flag indicating underflow o
195. mily Quick Reference Guide dwcore_1394 device Synthesizable IEEE 1394 Device Link Controller dwcore 1394 device Synthesizable IEEE 1394 Device Link Controller The Synopsys DesignWare IEEE 1394 Device Controller Link is a set of configurable blocks that ASIC FPGA designers can use to implement a complete 1394 interface function for a target or host design It can be effectively used in a wide range of applications such as digital still cameras video conferencing camera printers scanners digital audio devices electronic music instruments digital VCRs VTRs and storage devices Other features include the following Silicon proven IEEE 1394 Device Controller IEEE 1394 1995 and 1394a compliant Supports 100 200 400 Mbps 1394 bus rates Full implementation of Link layer Supports asynchronous isochronous and PHY transmit and receive packets Automatic 32 bit CRC generation and error detection Simple 8 16 32 bit application and isochronous interface with burst and non burst access modes RapidScript configuration for customization Synthesis scripts provided Cycle master capable Automatic IRM detection Hardware implementation of CSRs Power management features on application side Verilog source code e Optional 1394 simulation models The dwcore 1394 device data sheet is available at April 2003 http www synopsys com products designware docs ds c dwcore_1394_device pdf Synopsys Inc 291 DesignWare IP
196. ml e e mail the Synopsys Support Center at support_center synopsys com e Call 800 245 8005 toll free in the United States April 2003 Synopsys Inc 31 DesignWare IP Family Quick Reference Guide Datapath Generator Overview Datapath Generator Overview The new datapath generators improve the quality of synthesized datapaths in two steps 1 By using more sophisticated extraction and partitioning of datapaths from RTL code 2 By improved synthesis of the extracted datapaths The following figure shows the flow for datapath synthesis After the RTL code is analyzed and elaborated by the Presto Verilog VHDL Compiler the datapath portions of the RTL are extracted by DC Ultra and then synthesized by the datapath generators in the DesignWare Library RTL Verilog VHDL Presto Verilog VHDL Compiler unmapped db DC Ultra Datapath Extraction DesignWare Library Datapath Generator Logic Optimization mapped db DC Ultra partitions datapaths that are extracted from RTL into large sum of product and product of sum blocks This reduces the number of expensive carry propagations to a minimum resulting in faster and smaller circuits In sum of products a multiplication can be followed by an addition without a carry propagation before the addition Similarly in product of sums an addition can be followed by a multiplication without a carry propagation before the multiplication The same techniques are a
197. more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 41 DesignWare IP Family Quick Reference Guide DW bin2gray Binary to Gray Converter DW bin2gray Binary to Gray Converter e Parameterized word length e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function width bit s Input Binary coded input data width bit s Output Gray coded output data Table 2 Parameter Description Parameter Values Description width 21 Input word length Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model Design Ware Foundation 42 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide M DWO1 bsh Barrel Shifter DWO1 bsh Barrel Shifter e Parameterized data and shift coefficient word lengths B e Inferable using a function call SH Table 1 Pin Description Pin Name Width Direction Function A A_width Input Input data SH SH width Input Shift control B A_width Output Shifted data out Table 2 Parameter Description Parameter Values Description A width 21 Word length of A and B SH width Sceil logo A width for mx2 mx2i Word length of SH gt 1 for mx4 mx8 Table 3 Synthesis Implementations
198. mpiler Dck rstn Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low cs n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rd_addr ceil log depth bit s Input Read address bus wr_addr ceil log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data out data width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data width 1to256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width rst mode Oorl Determines the reset methodology 0 rst_n asynchronously initializes the RAM rst n synchronously initializes the RAM Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 156 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 DW ram r w s lat Synchronous Write Port Asynchronous Read Port RAM Latch Based DW ram r w s lat Synchronous Write Port Asynchronous Read Port RAM Latch Based e Parameterized word depth rd addr wr addr e Parameterized data width dalacin e Synchronous static memory data_out cs_n e Inferable from Behavioral Compiler wr n Table 1 Pin Description
199. mplementation does not always surpass the delay performance of the clf implementation it is much lower in area c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide 38 Synopsys Inc April 2003 DW addsub dx Duplex Adder Subtractor with Saturation and Rounding DesignWare IP Family Quick Reference Guide DW addsub dx Duplex Adder Subtractor with Saturation and Rounding Selectable single full width Add Sub simplex or two smaller width Add Sub operations duplex Selectable saturation mode Selectable average mode Selectable number system unsigned or twos complement Parameterized full word width Parameterized partial word width allowing for asymmetric partial width operations Carry out signals one for lower half and one for full and upper half that numerically extend the calculated sum maintaining full precision Carry in signals one for full and lower half and one for upper half Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data b width bit s Input Input data cil 1 bit Input Full or part1 carry inp
200. n clsa MC inside DW carry look ahead select DesignWare Foundation csa MC inside DW carry select DesignWare Foundation fastcla gt MC inside DW fast carry look ahead DesignWare Foundation pprefixP MC inside DW flexible parallel prefix DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide 58 Synopsys nc April 2003 DWO01 incdec DesignWare IP Family Quick Reference Guide Incrementer Decrementer e Parameterized word length DWO1 incdec Incrementer Decrementer Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data INC DEC 1 bit Input Increment control 0 increment A 1 1 decrement A 1 SUM width bit s Output Increment A 1 or decrement A 1 Table 2 Parameter Description
201. n Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 149 DesignWare IP Family Quick Reference Guide DW fifoctl s1 sf nnn Synchronous SingleClock FIFO Controller with Static Flags DW fifoctl s1 sf Synchronous SingleClock FIFO Controller with Static Flags e Fully registered synchronous address and flag output push req n Wiad ports we_n pop_req_n rd_addr e All operations execute in a single clock cycle 2 diag n e FIFO empty half full and full flags almost full half full almost empty empty rst n error e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst mode 1 push req n 1 bit Input FIFO push request active low pop req n 1 bit Input FIFO pop request active low diag n 1 bit Input Diagnostic control for err_mode 0 NC for other err_mode values a
202. n about using Synopsys products please consult product documentation that is installed on your network or located at the root level of your Synopsys product CD ROM if available You can also access documentation for DesignWare products on the Web e Product documentation for many DesignWare products http www synopsys com products designware docs e Navigate to individual DesignWare IP component datasheets http www synopsys com designware You can also contact a Synopsys Support Center online or by phone e http www synopsys com support support html e United States Call 1 800 245 8005 from 7 AM to 5 30 PM Pacific Time Mon Fri e Canada Call 1 650 584 4200 from 7 AM to 5 30 PM Pacific Time Mon Fri e All other countries Find other local support center telephone numbers at the following URL http www synopsys com support support_ctr Additional Information General information about Synopsys and its products is available at the following URL http www synopsys com Comments To report errors or make suggestions please send e mail to doc synopsys com To report an error that occurs on a specific page select the entire page including headers and footers and copy to the buffer Then paste the buffer to the body of your e mail message This will provide us with information to identify the source of the problem April 2003 Synopsys Inc 13 Additional Information DesignWare IP Family Quick Reference Guide
203. nWare Building Block IP Updating Building Block IP To get the latest version and receive the best performance install the Electronic Software Transfer EST release of DesignWare from the following Web site http www synopsys com designware dwest If you prefer you may also send an email to dw_EST synopsys com with EST in subject line In that email send the following information in the body of the message in the following format Site Id gt Synopsys Release gt For example if your site id is 555 and you want to install the EST for use with the 2000 11 version of the Synopsys Synthesis CD write the following two fields in the body of the message separated by a few blank spaces 595 2000 11 28 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 2 DesignWare Library Synthesizable IP Setting Up DesignWare Building Block IP Include the following lines in your synopsys dc setup file and ensure that you have a valid DesignWare license synthetic library dw foundation sldb link library target library synthetic library search path search path synopsys root dw sim ver synlib wait for design license DesignWare Accessing DesignWare Building Block IP You can access DesignWare Building Block IP either by operator or functional inference or by instantiating the component directly The example below shows how to access these IP Verilog assign PROD IN1 IN2
204. nWare IP Family Quick Reference Guide ahb act monitor vmt DW abb ictl AHB Interrupt Controller page 236 Synthesizable RTL DW apb APB bus decode and bridge page 237 Synthesizable RTL DW apb gpio APB GPIO page 238 Synthesizable RTL DW apb i2c APB C Interface page 239 Synthesizable RTL DW_apb_ictl APB Interrupt Controller page 240 Synthesizable RTL DW_apb_rap APB Remap amp Pause page 241 Synthesizable RTL DW_apb_rtc APB Real Time Clock page 242 Synthesizable RTL DW_apb_ssi APB Synchronous Serial Interface page 243 Synthesizable RTL DW_apb_timers APB Timer page 245 Synthesizable RTL DW apb uart APB UART page 246 Synthesizable RTL DW apb wdt APB Watch Dog Timer page 248 Synthesizable RTL DW memctl Memory Controller page 250 Synthesizable RTL AMBA Compliance Test benchTM ACT This component is licensed separately page 258 Verification Model ahb bus vmt AHB Bus page 258 Verification Model ahb master vmt AHB Master page 258 Verification Model ahb monitor vmt AHB Monitor page 258 Verification Model ahb slave vmt AHB Slave page 258 Verification Model apb master vmt APB Master page 260 Verification Model apb monitor vmt APB Monitor page 260 Verification Model apb slave vmt APB Slave page 260 Verification Model 18 Synopsys Inc April 2003 DesignWare IP Family Qui
205. nWare USB Hub UHO01 is a set of synthesizable building blocks that ASIC FPGA for implementing a complete USB hub The RapidScript utility enables designers to easily configure the device by setting the number of downstream ports The Synopsys UHOI product consists of the Hub Repeater and the Hub Controller The Hub Repeater is responsible for connectivity setup and tear down and supports exception handling such as bus fault detection recovery and connect disconnect detect The Hub Controller provides the mechanism for host to hub communication Hub specific status and control commands permit the host to configure a hub and to monitor and control its individual downstream ports Other features include the following e Silicon proven e Supports suspend resume for power e USB 1 1 compliant management e Available in Verilog e Supports one interrupt endpoint in iti e Supports low speed and full speed adition eee e Approximately 12K gates for four ports devices on downstream ports e Integrated DPLL for clock and data recovery e Test Environment includes USB compliance tests and Bus Functional e Downstream device connect Models disconnect detection The dwcore_usb1_hub data sheet is available at http www synopsys com products designware docs ds c dwcore_usb1_hub pdf 286 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Cor dwcore_usb2_host S Synthesizable USB 2 0 Host Controller dwcore usb2 host
206. ng 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst mode 0to3 Reset mode Default 0 0 2 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cli Partial carry look ahead model DesignWare Foundation cl2 Full carry look ahead model Design Ware Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 132 Synopsys Inc April 2003 n DW fifo s1 sf DesignWare IP Family Quick Reference Guide DW fifo s1 sf Synchronous Single Clock FIFO with Static Flags Synchronous Single Clock FIFO with Static Flags e Fully registered synchronous flag output ports de tie ata_in e D flip flop based memory array for high testability pop_req_n data_out e All operations execute in a single clock cycle full e FIFO empty half full and full flags ce alf fu e FIFO error flag indicating underflow overflow and diag n alm
207. ng carry lookahead synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 87 DesignWare IP Family Quick Reference Guide DW sqrt pipe Stallable Pipelined square root DW sqrt pipe Stallable Pipelined square root e Parameterized word length e Unsigned and signed two s complement data operation e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset e Automatic pipeline retiming Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall_mode 1 0 stall 1 load a width bit s Input Radicand root width 1 2 bit s Output Square root Table 2 Parameter Description Parameter Values Description width 22 Word length of a Default None num stages 22 Number of pipeline stages Default 2 stall mode 0or 1 Stall mode Default 1 0 non stallable 1 stallable rst mode 0to2 Reset mode Default
208. nnovative cost effective systems on chip and embedded systems DesignWare Cores are licensed individually on a fee per project business model The following table identifies the Synopsys Cores offering Component Name Component Description Component Type Bluetooth Core dwcore blueiq Bluetooth Baseband and Link Manager Synthesizable RTL page 273 dwcore blueiq devkit Bluetooth Development Kit page 275 Hardware Ethernet Cores dwcore ethernet Ethernet MAC 10 100 Mbps Operation Synthesizable RTL page 276 dwcore ethernet sub Ethernet MAC Subsystem page 277 Synthesizable RTL dwcore gig ethernet Gigabit Ethernet MAC 10 100 Mbps and Synthesizable RTL 1 Gbps Operation page 278 dwcore gig ethernet sub Gigabit Ethernet MAC GMAC Subsystem Synthesizable RTL page 279 PCI Cores dwcore pci 32 64 bit 33 66 MHz PCI Core page 280 Synthesizable RTL dwcore pcix 32 64 bit 133 MHz PCIX Core page 281 Synthesizable RTL dwcore pci express Synthesizable PCI Express Core page 282 Synthesizable RTL April 2003 Synopsys Inc 271 Chapter 4 DesignWare Cores DesignWare IP Family Quick Reference Guide USB Cores dwcore usb otg USB 2 0 Full Speed On The Go Controller Synthesizable RTL Subsystem page 283 dwcore usbl device USB 1 1 Device Controller page 284 Synthesizable RTL dwcore usbl host USB 1 1 OHCI Hos
209. nous if rst_mode 1 push req n bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for data_in_width lt data_out_width only pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control active low for err_mode 0 NC for other err_mode values data_in data in width bit s Input FIFO data to push April 2003 Synopsys Inc 141 DesignWare IP Family Quick Reference Guide DW asymfifoctl s1 sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Flag n Table 1 Pin Description Continued Pin Name Width Direction Function rd data max data in width Input RAM data input to FIFO controller data out width bit s w en 1 bit Output Write enable output for write port of RAM active low empty 1 bit Output FIFO empty output active high almost empty 1 bit Output FIFO almost empty output active high asserted when FIFO level xae level half full 1 bit Output FIFO half full output active high almost full 1 bit Output FIFO almost full output active high asserted when FIFO level 2 depth af level full 1 bit Output FIFO full output active high ram full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part wd 1 bit Output Partial word active high for data in width data out width only otherwi
210. nstruction and support of USERCODE instruction e User defined opcode for IDCODE e Parameterized instruction register width e External interface to program device identification register tck clock dr tms shift dr tdi update dr SO sync update dr bypass sel tdo sentinel val tdo en device id sel user code se aP_State user code val ver sync capture en ver sel instructions part_num part_num_sel mnfr id mnfr id sel trst n Table 1 Pin Description Pin Name Width Direction Function tck 1 bit Input Test clock trst n bit Input Test reset active low tms 1 bit Input Test mode select tdi 1 bit Input Test data in SO 1 bit Input Serial data from boundary scan register and data registers bypass sel 1 bit Input Selects the bypass register active high sentinel val width 1 bit s Input User defined status bits device id sel 1 bit Input peer the device identification register active 18 user code sel bit Input Selects the user code val bus for input in to the device identification register active high user code val 32 bits Input 32 bit user defined code ver 4 bits Input 4 bit version number 192 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW tap uc TAP Controller with USERCODE support Table 1 Pin Description Continued Pin Name Width Direction Function ver sel bit Input Select
211. nt to a client when no requests are pending e Lock feature ability to lock the currently granted client e Registered unregistered outputs request mask lock grant grant index granted parked Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Active low input reset request n bit s Input Input request from clients lock n bit s Input Active high signal to lock input By setting lock i 1 the arbiter is locked to the request 7 if it is currently granted For lock 7 0 the lock on the arbiter is removed mask n bit s Input Active high input to mask specific clients By setting mask 7 1 request 7 is masked For mask i 0 the mask on the request 7 is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to park index granted 1 bit Output Flag to indicate that arbiter has issued a grant to one of the clients locked 1 bit Output Flags that the arbiter is locked by a client grant n bit s Output Grant output grant index logon bit s Output Index of the requesting client that has been currently issued the grant or the client designated by park index in park mode 228 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW arbiter sp Arbiter with Static Priority Scheme Table 2 Paramet
212. ntiated DesignWare Building Block IP Install the latest release of FPGA Compiler II to get the best performance as well as access to the latest FPGA technologies FPGA Compiler II customers who are on active maintenance will automatically receive CDs for the latest major release or from any Synopsys sales office or at the following location http www synopsys com products fpga Setting Up DesignWare Building Block IP in FPGA Compiler Il DesignWare Building Block IP are automatically installed by default during the installation of FPGA Compiler II versions 3 2 and later You can choose to not install DesignWare Building Block IP by unchecking DesignWare in the FPGA Vendors dialog box during installation Otherwise there is nothing equivalent to the synopsys_dc setup file for Design Compiler to modify License Requirement FPGA Compiler II versions 3 2 to 3 3 require a valid DesignWare license in order to implement all DesignWare Building Block IP Beginning in FPGA Compiler II version 3 5 DesignWare Building Block basic IP can be implemented without the requirement of a DesignWare license The basic IP include the following DWO0O1_cmp2 DWOl cmp6 DWOI absval DWOI add DWOI sub DWO1_addsub DWOI inc DWOI dec DWOI1 incdec DWO02 mult 30 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 2 DesignWare Library Synthesizable IP Accessing DesignWare Building Block IP in FPGA Compiler Il You can access DesignWare
213. number of Default 2 Words in the FIFO at or below which the push ae flag is active push af lvl 1 to depthd Almost full level for the push af output port the number of Default 2 empty memory locations in the FIFO at which the push af flag is active pop ae lvl 1 to depth Almost empty level for the pop ae output port the number of Default 2 words in the FIFO at or below which the pop ae flag is active pop_af_Ivl 1to depth Almost full level for the pop af output port the number of Default 2 empty memory locations in the FIFO at which the pop af flag is active Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AT DW fifo s2 sf Synchronous Dual Clock FIFO with Static Flags Table 2 Parameter Description Continued Parameter Values Description err mode Oor 1 Error mode Default 0 0 stays active until reset latched 1 active only as long as error condition exists unlatched push sync 1to3 Push flag synchronization mode Default 2 1 single register synchronization from pop pointer 2 double register 3 triple register pop sync 1 to3 Pop flag synchronization mode Default 2 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode 0 to 3 Reset mode Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding
214. od sum pipe Stallable Pipelined Generalized Sum of Products DW prod sum pipe Stallable Pipelined Generalized Sum of Products e Parameterized word length rsen a r aixbi b X aix bi e Unsigned and signed two s complement data operation tc sum e Parameterized number of pipeline stages n e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset e Automatic pipeline retiming Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall mode 1 0 stall 1 load tc 1 bit Input Two s complement control 0 unsigned 2 signed a a width x num inputs bit s Input Concatenated input data vector b b width x num inputs bit s Input Concatenated input data vector sum sum width bit s Output Pipelined data summation April 2003 Synopsys Inc 79 DesignWare IP Family Quick Reference Guide DW prod sum pipe Stallable Pipelined Generalized Sum of Products Table 2 Parameter Description Parameter Values Description a width 21 Word length of a Default None b width 21 Word length of b Default None num inputs gt 1 Number of inputs Default 2 num stages 2 Number of pipeline stages Default
215. ode 0to2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 or 1 Reset mode Default 1 0 asynchronous reset 1 synchronous reset byte_order Oor 1 Order of bytes or subword subword lt 8 bits gt subword within Default 0 a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Components ell Partial carry look ahead model Design Ware Components cl2 Full carry look ahead model Design Ware Components a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 143 DesignWare IP Family Quick Reference Guide DW asymfifoctl s2 sf AIT Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags DW asymfifoctl s2 sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags e Parameterized asymmetric input and output bit data in iE widths must be integer multiple relationship E e Parameterized word dep
216. of the csm implementation is heavily dependent on the use of a high performance inverting 2 to 1 multiplexer in the technology library In such libraries the csm implementation exhibits a superior area delay product Although the csm implementation does not always surpass the delay performance of the clf implementation it is much lower in area c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell variable dw_prefer_mc_inside must be set to true For more details see the DesignWare Building Block IP Users Guide 36 Synopsys Inc April 2003 DWO01 addsub Adder Subtractor e Parameterized word length e Carry in and carry out signals DesignWare IP Family Quick Reference Guide DWO01 addsub Adder Subtractor Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data CI 1 bit Input Carry borrow in ADD SUB 1 bit Input Addition subtraction control SUM width bit s Output Sum A B 4CI or difference A B CT CO 1 bit Output Carry borrow out Table 2 Parameter Description Parameter Values Description width 2l Word length of A B and SUM Table 3 Synthesis Impl
217. on rpcs Ripple carry select synthesis model DesignWare Foundation clsat MC inside DW carry look ahead select DesignWare Foundation csa MC inside DW carry select DesignWare Foundation fastcla MC inside DW fast carry look ahead Design Ware Foundation pprefix MC inside DW flexible parallel prefix DesignWare Foundation 90 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO01 sub Subtractor a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The performance of the csm implementation is heavily dependent on the use of a high performance inverting 2 to 1 multiplexer in the technology library In such libraries the csm implementation exhibits a superior area delay product Although the csm implementation does not always surpass the delay performance of the clf implementation it is much lower in area c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide April
218. on Model DW C166S 16 bit Processor from Infineon page 304 Verification Model DW TriCorel TriCore1 32 Bit Processor Core from Infineon page 306 Verification Model DW MIPSAKE Processor Core Family from MIPS page 308 DesignWare Memory Access to the full suite of memory IP is made available through DesignWare Memory Central a memory focused Web site that lets designers download DesignWare Memory IP and documentation Visit Memory Central at http www synopsys com products designware memorycentral Verification Model Also visit the DesignWare Verification Library web page at http www synopsys com products designware dwverificationlibrary html 22 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DesignWare Cores The DesignWare Cores shown in the following table provide system designers with silicon proven digital and analog connectivity IP DesignWare Cores are licensed individually on a fee per project business model Chapter 1 Overview Component Name Component Description Component Type Bluetooth Core dwcore blueiq Bluetooth Baseband and Link Manager Synthesizable RTL page 273 dwcore blueiq devkit Bluetooth Development Kit page 275 Hardware Ethernet Cores dwcore ethernet 10 100 Mbps Operation page 276 Synthesizable RTL dwcore ethernet sub Ethernet MAC S
219. ondition GE_GT 1 bit Output Greater than or equal greater than output condition Table 2 Parameter Description Parameter Values Description width 21 Word length of A and B Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none bk Brent Kung synthesis model DesignWare Foundation cla Carry look ahead synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 45 DesignWare IP Family Quick Reference Guide DWO1 cmp6 6 Function Comparator DWO01 cmp6 6 Function Comparator e Parameterized word length e Unsigned and signed two s complement data comparison Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data TC 1 bit Input Two s complement control 0 unsigned 1 signed LT 1 bit Output Less than output condition GT 1 bit Output Greater than output condition EQ 1 bit Output Equal output condition LE 1 bit Output Less than or equal output condition GE 1 bit Output Greater than or equ
220. ost Controller Interface Host Controller Interface Link Manager Link Controller Baseband RF Interface Radio DesignWare IP Family Quick Reference Guide dwcore blueiq Synthesizable Bluetooth Baseband and Link Manager e Small gate count and memory footprint Three voice channels and optional PCM hardware encryption and flexible memory interface for RAM ROM and Flash configurations Bluetooth development kit available on PC or other UART or USB equipped hardware platform Qualified to Bluetooth v1 1 specification Host CPU User Application UART 68HC11 DesignWare BluelQ Baseband Controller Bluetooth System Block Diagram April 2003 Synopsys Inc 273 DesignWare IP Family Quick Reference Guide dwcore blueiq Or es Synthesizable Bluetooth Baseband and Link Manager Program Memory Watchdog Reset Bootloader UART Memory 6811 Debug Micro and Bus UART icro e processor Deae UART and UART Standby BBC Controller Interrupt EE PCM Controller Baseband MC145483 HCI Logic mua E E CPU Radio Modem Interface SiW1701 Bluetooth Optional block Packet FIFOs 2 BluelQ Top Level Block Diagram The dwcore_blueiq data sheet is available at http www synopsys com products designw
221. ost empty pointer corruption empty e Parameterized word width gt ck bp EA e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous memory array initialized or not Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 or 2 synchronous if rst mode 1 or 3 push req n 1 bit Input FIFO push request active low pop req n 1 bit Input FIFO pop request active low diag n 1 bit Input Diagnostic control active low data in width bit s Input FIFO data to push empty 1 bit Output FIFO empty output active high almost empty 1 bit Output FIFO almost empty output active high half full 1 bit Output FIFO half full output active high almost full 1 bit Output FIFO almost full output active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high data out width bit s Output FIFO data to pop April 2003 Synopsys Inc 133 DesignWare IP Family Quick Reference Guide DW fifo s1 sf Synchronous Single Clock FIFO with Static Flags Table 2 Parameter Description Parameter Values Function width 1 to 256 Width of the data in and data out buses Default 8 depth 2 to 256 Number of memory elements used in FIFO Default 4 addr width ceil log depth ae level 1 to depth 1 Almos
222. ount width Output Output count bus tercnt 1 bit Output Terminal count flag Table 2 Parameter Description Parameter Values Description width 1 to 30 Width of data and count count_to to 2idth 1 Count to value Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 209 DesignWare IP Family Quick Reference Guide DWOS3 bictr decode Up Down Binary Counter with Output Decode DWO3 bictr decode Up Down Binary Counter with Output Decode 210 Up down count control Asynchronous reset Loadable count register Counter enable Terminal count flag count dec up dn cen load clk reset Table 1 Pin Description Pin Name Width Direction Function data width Input Counter load input up dn 1 Input High for count up and low for count down load 1 Input Enable data load to counter active low cen 1 Input Count enable active high clk 1 Input Clock reset 1 Input Counter reset active low count dec gwidth Output Binary decoded count value tercnt 1 Output Terminal count flag Table 2 Parameter Description Parameter Values Function width 2 Width of data input bus Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foun
223. ource Code SMSC USB 2 0 PHY Standard Microsystems Corporation GT3100 USB 2 0 PHY Star IP MacroCell page 311 Hard IP a Verification models of these cores are included in the DesignWare Library Synthesizable RTL of these cores are available through the Star IP Program April 2003 Synopsys Inc 299 DesignWare IP Family Quick Reference Guide S DW_IBM440 R4 o DesignWare IBM PowerPC 440 Star IP Core DW IBM440 DesignWare IBM PowerPC 440 Star IP Core The PPC440x5 core is a high performance low power engine that implements the flexible and powerful Book E Enhanced PowerPC Architecture Other features include the following 300 High performance dual issue superscalar 32 bit RISC CPU o Superscalar implementation of the full 32 bit Book E Enhanced PowerPC Architecture Seven stage highly pipelined micro architecture Dual instruction fetch decode and out of order issue Out of order dispatch execution and completion High accuracy dynamic branch prediction utilizing a Branch History Table BHT Three independent pipelines Combined complex integer system and branch pipeline e Simple integer pipeline e Load store pipeline Single cycle multiply Single cycle multiply accumulate new DSP instruction set extensions Full support for both big and little endian byte order Extensive power management designed into core for maximum performance power efficiency Separate 32 KB instruction and data caches
224. please refer to the DesignWare Building Block IP User Guide 212 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide foe DWO3 Ifsr dcnto B LFSR Counter with Dynamic Count to Flag DWO3 Ifsr dcnto LFSR Counter with Dynamic Count to Flag e Dynamically programmable count to value that data indicates when the counter reaches a specified value count m count to e High speed area efficient tercnt e Asynchronous reset e Terminal count clk reset Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data count_to width bit s Input Input count_to_bus load 1 bit Input Input load data to counter active low cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 bit Input Asynchronous reset active low count width bit s Output Output count bus tercnt 1 bit Output Output terminal count Table 2 Parameter Description Parameter Legal Range Description width 1 to 50 Word length of counter a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation April 2003 Synopsys Inc 213 DesignWare IP Family Quick Reference Guide DWO3 Ifsr scnto LFSR Counter with Static Coun
225. psys Inc 309 DesignWare IP Family Quick Reference Guide 4 Mezoe Interface Express Qr Ts Interface Express Toolkit including BlueStack Protocol Stack with Mezoe Interface Express Interface Express Toolkit including BlueStack Protocol Stack with Profiles and ProtoDeveloper Software Mezoe s Interface Express Toolkit includes a full Bluetooth upper layer stack OBEX stack Bluetooth profiles and source application examples allowing you to create working Bluetooth applications in just minutes Mezoe s Bluetooth software connects directly and easily to the DesignWare BlueIQ Core and Bluetooth Development Kit through the standard HCI over UART transport Even designers with little or no Bluetooth experience gain the freedom to quickly create and test their own custom Bluetooth applications on working silicon when used with the DesignWare Bluetooth Development Kit These applications may then be implemented in silicon with the DesignWare BlueIQ Core Serial Port OBJ Push File Transfer Sync LAN SDAP Headset Cordless DUN Audio Gateway Telephone OPP FTP Sync OBEX Cordless SPP DUN FAX OBEX IAS HFree Headset LAN Telephone GAP amp SDAP amp Intercom CPE CM APE SM MN During development designers may use Interface Express on a PC to create applications and immediately test them through an attached DesignWare Bluetooth Development Kit Mezoe s Bluetooth software together with the DesignWare Bluetooth De
226. pty memory locations in the FIFO at which the pop_af flag is active err mode Oor 1 Error mode 0 stays active until reset latched 1 active only as long as error condition exists unlatched push sync 1 to3 Push flag synchronization mode 1 single register synchronization from pop pointer 2 double register 3 triple register pop sync 1 to3 Pop flag synchronization mode 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode 0 or 3 Default 1 Reset mode 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory April 2003 Synopsys Inc 129 DesignWare IP Family Quick Reference Guide DW asymfifo s2 sf Asymmetric Synchronous Dual Clock FIFO with Static Flags Table 2 Parameter Description Continued byte order Oor 1 Parameter Values Description Default 0 Order of bytes or subword within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position a Valid depth values include binary numbers from 8 to 256 i e 8 16 32 64 etc and all odd values between 8 and 256 Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis mod
227. quired rpl Ripple carry synthesis model DesignWare Foundation cll Partial carry look ahead model DesignWare Foundation cl2 Full carry look ahead model Design Ware Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 126 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifo s2 sf Asymmetric Synchronous Dual Clock FIFO with Static Flags DW asymfifo s2 sf Asymmetric Synchronous Dual Clock FIFO with Static Flags e Parameterized asymmetric input and output bit data in stas widths must be integer multiple relationship AE push_ae e Fully registered synchronous flag output ports piens flush n push af e Separate status flags for each clock system push full P clk push ram full e FIFO empty half full and full flags part wd e Parameterized almost full and almost empty flags Push eror e FIFO push error overflow and pop error eer underflow flags pop req n pop empty pop ae e D flip flop based memory array for high testability pop hf e Single clock cycle push and pop operations e Word integrity flag for data in width lt data out width e Partial word flush for data in width lt data out width e Parameterized byte order within a word
228. r 1 EN M M EAT DW ahb Msn 74 Slave 7 PA DW ahb t USD Layer N The DesignWare DW ahb icm Databook is available at http www synopsys com products designware docs April 2003 Synopsys Inc 235 DesignWare IP Family Quick Reference Guide DW ahb ictl AHB Interrupt Controller DW ahb ictl AHB Interrupt Controller e 2 to 64 IRQ normal interrupt sources e Priority filtering optional e to 8 FIQ fast interrupt sources e Masking optional e Optional scan mode e Vectored interrupts optional e Software interrupts DW ahb ictl IRQ Generation Interrupt FIQ Registers Generation Vector Generation amp Masking The DesignWare DW_ahb_ictl Databook is available at http www synopsys com products designware docs 236 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW apb Advanced Peripheral Bus DW apb Advanced Peripheral Bus Incorporates APB Bridge and APB bus e Supports Little Endian APB slaves pune omality e Supports 32 64 128 256 AHB data AHB Slave buses Support for up to 16 APB slaves e Support for single and burst AHB Supports synchronous hclk pclk hclk asics is an integer multiple of pclk Configurable papa Slave Ports up to 16 4 Slave 0 Address AHB Slave Decoder AHB lt 4 gt Interface Read Data MUX lt gt Slavej ja upto 15 Th
229. re Contains a brief description of each DesignWare Star IP core Synopsys Inc 11 Typographical and Symbol Conventions DesignWare IP Family Quick Reference Guide Typographical and Symbol Conventions Table 1 lists the conventions that are used throughout this document Table 1 Documentation Conventions Convention Description and Example Represents the UNIX prompt Bold User input text entered by the user cd LMC_HOME hd1 Monospace System generated text prompts messages files reports No Mismatches 66 Vectors processed 66 Possible Italic or Italic Variables for which you supply a specific value As a command line example setenv LMC HOME prod dir In body text In the previous example prod dir is the directory where your product must be installed Vertical rule Choice among alternatives as in the following syntax example effort level low medium high Square brackets Enclose optional parameters pinli pin2 pinN In this example you must enter at least one pin name pin but others are optional pin2 pinN TopMenu gt SubMenu Pulldown menu paths such as File Save As Synopsys Common Licensing SCL You can find general SCL information on the Web at http www synopsys com keys T2 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Additional Information Getting Help If you have a questio
230. re_usb1_device pdf 284 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Cor dwcore_usb1_host S Synthesizable USB 1 1 OHCI Host Controller dwcore usb1 host Synthesizable USB 1 1 OHCI Host Controller The Synopsys DesignWare USB Host Controller UHOSTI Synthesizable IP is a set of synthesizable building blocks that ASIC FPGA for implementing a complete USB OHCI Host Controller function Features include the following e Silicon proven e Single 48 MHz input clock e USB 1 1 Compliant e Simple application interface facilitates e VCI AHB or Native interface bridging the host to other system bus such as PCI and the integration of the controller with chipsets and microcontrollers e Integrated DPLL e Support for SMI interruptspproximately 25K gates with e Configurable root hub supporting up 2 ports to 15 downstream ports e Compatible with Open HCI 1 0 specification e Available in Verilog e Supports low speed and full speed devices e Test Environment includes USB e Configuration data stored in Port compliance tests and Bus Functional Configurable Block Models The dwcore usbl1 host data sheet is available at http www synopsys com products designware docs ds c dwcore_usb1_host pdf April 2003 Synopsys Inc 285 DesignWare IP Family Quick Reference Guide C dwcore usbi hub Or es Synthesizable USB 1 1 Hub Controller dwcore usb1 hub Synthesizable USB 1 1 Hub Controller The Synopsys Desig
231. results and significantly shortens synthesis run times Since the DesignWare Library is tightly integrated with Synopsys synthesis tools such as Design Compiler and Physical Compiler the synthesis tool automatically picks the right architecture with the best speed and area optimizations In many cases there is significant improvement on the quality of results automatically because DesignWare infers these arithmetic IP elements without intervention through Design Compiler April 2003 Synopsys Inc 27 Chapter 2 DesignWare Library Synthesizable IP DesignWare IP Family Quick Reference Guide This library contains high performance implementations of Basic Library IP plus many IP that implement more advanced arithmetic and sequential logic functions The DesignWare Building Block IP consists of e Basic A set of IP bundled with HDL Compiler that implements several common arithmetic and logic functions e Datapath Arithmetic trigonometric and sequential math IP e Memory Registers FIFOs and FIFO controllers synchronous and asynchronous RAMS and stack IP e Data Integrity CRC ECC 8b10b and other IP e Test JTAG IP e Logic Combinational sequential and control IP e Interface Debugger IP e DSP Digital FIR filter IP e GTECH Technology independent IP library to aid users in developing technology independent parts Building Block IP QuickStart The following topics provide the basic information to get started using the Desig
232. roduct A x B Table 2 Parameter Description Parameter Values Description A_width gt 1 Word length of A B_width 2 1 For csa architecture A width B_width lt A48 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation str Booth recoded Wallace tree synthesis model Design Ware Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A width and B width x48 bits as it has no area benefit beyond 48 bits 68 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO02 mult 4 stage Four Stage Pipelined Multiplier DWO02 mult 4 stage Four Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation Four stage pipelined architecture Automatic pipeline retiming e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Multiplier B B width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed CLK
233. rview K Note The Floating Point IP are designed specifically for Module Compiler and do not work with Design Compiler The Floating Point IP are included in the DesignWare Building Block IP set as a convenience You can find the Floating Point DesignWare Building Block IP group download request instructions at the following web address http www synopsys com products designware dwest dwfloating_form html The Floating Point DesignWare Building Block IP group is a library of functions used to synthesize floating point computational circuits in high end ASICs The functions mainly deal with arithmetic operations in floating point format format conversions and comparison functions The main features of this library are as follows e The format of the floating point numbers that determines the precision of the number that it represents is parametrizable The user can select the precision based on either IEEE single or double precision or custom format defined by you e The parameter range for exponents is from 3 to 31 bits e The parameter range for the significand or the fractional part of the floating point number is from 2 bits to 256 bits e The parameter range for integers is from 3 to 512 bits e Accuracy conforms to the definitions in the IEEE 754 Floating Point standard April 2003 Synopsys Inc 105 DesignWare IP Family Quick Reference Guide DW add fp Floating Point Adder Module Compiler Only DW add fp Floating
234. s used in the FIFO addr_width ceil log5 depth err_mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 to 3 Reset mode Default 1 0 2 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory byte order 0 or 1 Order of send receive bytes or subword subword 8 bits subword Default 0 Within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position valid for data in width data_out_width Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model Design Ware Foundation cll Partial carry look ahead model DesignWare Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 122 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AT DW asymfifo s1 sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags DW asymfifo s1 sf Asymmetric I O Synchronous Single Clock FIFO with St
235. s version from the parameter or the ver input port 0 version parameter 1 ver input port part num 16 bits Input 16 bit part number part num sel 1 bit Input Selects part from the parameter or the part num from the input port 0 part parameter part num input port mnfr id 11 bits Input 11 bit JEDEC manufacturer s identity code mnfr id 127 mnfr id sel bit Input Selects man num from the parameter or mnfr id from the input port 0 2 man num parameter 1 mnfr id input port clock dr 1 bit Output Clocks in data in asynchronous mode shift dr 1 bit Output Enables shifting of data in both synchronous and asynchronous mode update dr 1 bit Output Enables updating data in asynchronous mode tdo 1 bit Output Test data out tdo en bit Output Enable for tdo output buffer tap state 16 bits Output Current state of the TAP finite state machine instructions width bit s Output Instruction register output sync capture en 1 bit Output Enable for synchronous capture sync update dr 1 bit Output Enables updating new data in synchronous mode Table 2 Parameter Description Parameter Values Description width 2 to 32 Width of instruction register Default None id Oor1 Determines whether the device identification register is Default 0 present 0 not present 1 present idcode opcode to width 1 Opcode for IDCODE Default 1 version 0 to 15
236. scription Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A width 21 Word length of A B width gt For csa architecture A width B_width 48 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Required csa Carry save array synthesis model DesignWare Foundation str Booth recoded Wallace tree synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A width and B width lt A8 bits as it has no area benefit beyond 48 bits April 2003 Synopsys Inc 71 DesignWare IP Family Quick Reference Guide DW mult dx Duplex Multiplier DW mult dx Duplex Multiplier Selectable single full width multiplier simplex or two parallel smaller width multiplier duplex operations Area and delay are similar to those of the DWO2 mult wallace architecture Selectable number sy
237. se tied low wr data max data in width Output FIFO controller output data to RAM data out width bit s wr addr ceil logs depth bit s Output Address output to write port of RAM rd addr ceil logs depth bit s Output Address output to read port of RAM data out data out width bit s Output FIFO data to pop 142 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide TT DW asymfifoctl s1 sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Table 2 Parameter Description Parameter Values Description data in width 1 to 256 Width of the data in bus Values for data in width must be in an integer multiple relationship with data out width That is either data in width K x data out width or data out width K x data in width where K is an integer data out width 1 to 256 Width of the data out bus data out width must be in an integer multiple relationship with data in width That is either data in width K x data out width or data out width K X data in width where K is an integer depth 2 to 224 Number of memory elements used in the FIFO addr width ceil log depth ae level 1 to depth 1 Almost empty level the number of words in the FIFO at or below which the almost empty flag is active af level 1 to depth 1 Almost full level the number of empty memory locations in the FIFO at which the almost full flag is active err m
238. separate PCI PCI X FlexModels and a set of system level testbenches e pcimaster_fx Performs timing violation checks and emulates the protocol of PCI PCI X initiators at the pin and bus cycle levels Initiates read and write cycles In PCI X mode pcimaster_fx can function as a target for split transactions e pcislave_fx Responds to cycles initiated by the pcimaster_fx model or by the user s PCI master device In PCI X mode the pcislave_fx also functions as an initiator for split transactions e pcimonitor_fx Monitors logs and arbitrates activity on the PCI or PCI X bus e PCI and PCI X system testbenches Provides ready to use example testbenches for both conventional PCI mode and PCI X mode Each system testbench uses two pcimaster_fx models two pcislave_fx models and a pcimonitor_fx model PCI system level testbench HDL control cimaster_fx C or Vera command stream gt P B control file Design Under Test HDL control P pcislave fx C or Vera command stream p control file HDL control cimonitor fx C or Vera command stream aug control file bus trace output file The individual DesignWare FlexModel databooks can be found with each model at http www synopsys com products designware ipdir April 2003 Synopsys Inc 265 DesignWare IP Family Quick Reference Guide USB 1 1 2 0 Bus Host Interface Model usbhost f
239. signWare IP Family Quick Reference Guide DW stack Synchronous Single Clock Stack DW stack Synchronous Single Clock Stack e Parameterized word width and depth data in data out e Stack empty and full status flags push req n zii e Stack error flag indicating underflow and overflow pop req n empty e Fully registered synchronous flag output ports error e All operations execute in a single clock cycle e D flip flop based memory array for high testability e Parameterized reset mode synchronous or asynchronous Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 or 2 synchronous if rst mode 1 or 3 push req n 1 bit Input Stack push request active low pop_req_n 1 bit Input Stack pop request active low data_in data_width bit s Input Stack push data empty 1 bit Output Stack empty flag active high full 1 bit Output Stack full flag active high error 1 bit Output Stack error output active high data_out data_width bit s Output Stack pop data 172 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW stack Synchronous Single Clock Stack Table 2 Parameter Description Parameter Values Description width to 256 Width of data in and data out buses Defa
240. stem unsigned or two s complement Parameterized full word width Parameterized partial word width allowing for asymmetric partial width operations Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data b width bit s Input Input data tc 1 bit Input Two s complement control dplx 1 bit Input Duplex mode select active high product width x 2 bit s Output Product s Table 2 Parameter Description Parameter Values Description width gt 4a Word width of a and b pl width 2 to width 2b Word width of Part1 of duplex multiplier a Due to the limitation of memory addressing ranges of the computer operating system there is an upper limit for parameter width b For the best performance of DW mult dx p width should be set in the range width 2 width 2 Table 3 Synthesis Implementations Implementation Name Function License Required wall Booth recoded Wallace tree synthesis model DesignWare Foundation 72 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW mult pipe Stallable Pipelined multiplier DW mult pipe Stallable Pipelined multiplier e Parameterized word length e Unsigned and signed two s complement pipelined multiplication e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterize
241. synchronous to clk push active high push error 1 bit Output FIFO push error overrun output flag synchronous to clk push active high pop empty 1 bit Output FIFO empty output flag synchronous to clk pop active high pop ae l bit Output FIFO almost empty output flag synchronous to clk pop active high determined by pop ae lvl parameter pop hf l bit Output FIFO half full output flag synchronous to clk pop active high pop af l bit Output FIFO almost full output flag synchronous to clk pop active high determined by pop af lvl parameter pop full l bit Output FIFO full output flag synchronous to clk pop active high pop error 1 bit Output FIFO pop error underrun output flag synchronous to clk pop active high wr addr ceil logs depth bit s Output Address output to write port of RAM rd addr ceil log depth bit s Output Address output to read port of RAM push word count ceil logo5 depth 1 bit s Output Words in FIFO as perceived by the push pop interface pop word count ceil log5 depth 1 bit s Output Words in FIFO as perceived by the push pop interface test 1 bit Input Active high test input control for inserting scan test lock up latches a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description depth 4 to 224 Number of words that
242. t Clocks data into the capture stage capture en bit Input Enable for data clocked into capture stage active low shift dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data out is controlled by the boundary scan cell or by the data in signal si 1 bit Input Serial path from the previous boundary scan cell data in 1 bit Input Input data from system input pin data out 1 bit Output Output data to IC logic SO 1 bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Test IEEE STD 1149 1 April 2003 Synopsys Inc 197 DesignWare IP Family Quick Reference Guide DW bc 4 Boundary Scan Cell Type BC 4 DW bc 4 Boundary Scan Cell Type BC 4 e IEEE Standard 1149 1 compliant data in data out e Synchronous or asynchronous scan cells with respect to tck e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS Oo capture en pcapture clk Table 1 Pin Description Pin Name Width Direction Function capture clk 1 bit Input Clocks data into the capture stage capture_en l bit Input Enable for data clocked into the capture stage active low shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output
243. t Controller page 285 Synthesizable RTL dwcore usbl hub USB 1 1 Hub Controller page 286 Synthesizable RTL dwcore usb2 host USB 2 0 Host Controller UHOST2 page 287 Synthesizable RTL dwcore usb2 device USB 2 0 Device Controller page 288 Synthesizable RTL dwcore usb2 phy USB 2 0 PHY page 289 Hard IP IEEE 1394 Cores dwcore 1394 avlink IEEE 1394 AVLink page 290 Synthesizable RTL dwcore 1394 device IEEE 1394 Device Link Controller page 291 Synthesizable RTL dwcore 1394 ohci IEEE 1394 OHCI Link page 292 Synthesizable RTL dwcore 1394 cphy IEEE 1394 Cable PHY page 293 Synthesizable RTL Java Acceleration Core dwcore jvxtreme Java Accelerator page 294 Synthesizable RTL JPEG Cores dwcore jpeg codec JPEG CODEC page 295 Synthesizable RTL dwcore jpeg2 codec JPEG2000 CODEC page 296 Synthesizable RTL dwcore jpeg2 encod JPEG2000 Encoder page 297 Synthesizable RTL Synopsys Inc April 2003 dwcore blueiq Synthesizable Bluetooth Baseband and Link Manager Provides two CPU architecture for ease of integration Includes 6811 compatible microcontroller that offloads host processor of 100 of baseband and link manager processing Designed for low power and low system cost Simple HCI over UART interface that allows connection to any host Optimized connection to Silicon Wave SiW1701 radio modem Host Application Profile s RFComm TCS SDP Device Manager L2CAP H
244. t empty level the number of words in the FIFO at Default 1 or below which the almost empty flag is active af level 1 to depth 1 Almost full level the number of empty memory locations Default 1 in the FIFO at which the almost full flag is active err mode 0to2 Error mode Default 0 0 underflow overflow and pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 to3 Reset mode Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cll Partial carry look ahead model DesignWare Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 134 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AT DW fifo s2 sf Synchronous Dual Clock FIFO with Static Flags DW fifo s2 sf Synchronous Dual Clock FIFO with Static Flags Fully register nchronous flag output ports push word
245. t generation DesignWare Java accelerator JV Xtreme is provided as synthesizable Verilog RTL for system integration Features include the following e Used for set top boxes game e Interfaces with any CPU and is consoles and web phones terminals compatible with any OS and Java as well as mobile information devices Virtual Machine JVM such as PDAs mobile phones and e Accelerates Java while preserving all smart cards previous CPU operating system and e Accelerates CPU performance for software application capabilities Java applications by up to 90x e Better performance than a peak and 15x average Just in Time JIT compiler without e Low power consumption with an JIT latency code bloating or memory average power of 200 uW MHz in a requirements 0 18 um process e Synthesizable Verilog source code e Silicon efficient design 27K gates 4 memory The dwcore_jvxtreme data sheet is available at http www synopsys com products designware docs ds c dwcore_jvxtreme pdf 294 Synopsys Inc April 2003 C eg dwcore jpeg codec Synthesizable JPEG CODEC DesignWare IP Family Quick Reference Guide dwcore jpeg codec Synthesizable JPEG CODEC The Synopsys DesignWare JPEG CODEC is part of an SoC based multimedia solution that enables fast and simple image compression and decompression The simplicity of the design allows for easy SoC integration high speed operation and suitability for multimedia and color printing applications Oth
246. t to Flag DWOS3 Ifsr scnto LFSR Counter with Static Count to Flag 214 Parameterized count to value to indicate when the counter reaches a specified value Parameterized word length High speed area efficient Asynchronous reset Terminal count flag Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data load 1 bit Input Input load active low cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 Input Asynchronous reset active low count width bit s Output Output count bus tercnt 1 bit Output Output terminal count Table 2 Parameter Description Parameter Values Function width 2 to 50 Word length of counter count to 1 to 2Width 2 count_to bus a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Synopsys Inc April 2003 i DWO3 Ifsr load DesignWare IP Family Quick Reference Guide LFSR Counter with Loadable Input e Parameterized word length e Loadable counter registers e High speed area efficient e Asynchronous reset e Terminal count DWOS3 Ifsr load LFSR Counter with Loadable Input Table 1 Pin Description
247. ta operation X lt square a Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data tc 1 bit Input Two s complement control 0 unsigned 1 signed square 2 X width bit s Output Product of a x a Table 2 Parameter Description Parameter Values Description width 21 Word length of a Table 3 Synthesis Implementations Implementation Name Function License Required wall Wallace tree synthesis model DesignWare Foundation mcarch MC inside DW Wallace tree DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b Automatically chooses Booth recoding or non Booth recoding architecture depending on constraints c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell variable dw_prefer_mc_inside must be set to true For more details see the DesignWare Building Block IP Users Guide April 2003 Synopsys Inc 85 DesignWare IP Family Quick Reference Guide DW squarep Partial Product Integer Squarer DW squarep Partial Product Integer Squar
248. tails please refer to the DesignWare Building Block IP User Guide 140 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifoctl s1 sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static DW_asymfifoctl_s1_sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Flags e Fully registered synchronous address and flag output data_out push_req_n wr_addr ports e All operations execute in a single clock cycle e FIFO empty half full and full flags e Asymmetric input and output bit widths must be pop_req_n integer multiple relationship e Word integrity flag for data_in_width lt data_out_width e Flushing out partial word for data_in_width lt data_out_width wr_data w en rd addr data in rd data ram full part wd flush n full almost full diag n half full almost empty empty rS eror e Parameterized byte order within a word e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchro
249. tecture for your design goals All IP have a parameterized word length April 2003 Synopsys Inc 33 DesignWare IP Family Quick Reference Guide DWO1 absval Absolute Value DWO1 absval Absolute Value e Parameterized word length A ABSVAL Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data ABSVAL width bit s Output Absolute value of A Table 2 Parameter Description Parameter Values Function width 21 Word length of A and ABSVAL Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 34 Synopsys Inc April 2003 DWO1 Adder DesignWare IP Family Quick Reference Guide DWO01 add Adder add e Parameterized word length e Carry in and carry out signals e e Module Compiler Architectures sum B CO Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B
250. th the use of external pause enable signal Test mode signal to decrease the time required during functional test APB Register Interface Block Interrupt amp System Reset Control The DesignWare DW apb i2c Databook is available at 248 http www synopsys com products designware docs Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide Chapter 2 DesignWare Synthesizable IP Memory IP The following Memory IP are briefly described in this section Component Name Component Description Component Type DW memctl Memory Controller page 250 Synthesizable RTL DW rambist DesignWare Memory BIST solution page 251 Synthesizable RTL To view the complete DesignWare memory portfolio refer to the following http www synopsys com products designware memorycentral April 2003 Synopsys Inc 249 DesignWare IP Family Quick Reference Guide DW memctl Memory Controller DW memctl Memory Controller e AMBA AHB bus compatible e SDR SDRAM MOBILE SDRAM e AHB dita widths of 30 64 or 128 bits SyncFlash or Static memory interface e AHB address width of 32 bits e Separate or shared address and buses between SDRAM and Static memories e 1 1 or 1 2 ratios with AHB data width e Busy and early terminations for SDRAM interface e Data width to 16 32 64 or 128 e 1 1 to 1 16 ratios with AHB data width for Static memory interface e Narrow a
251. th push_req_n ee e Fully registered synchronous flag output ports shi ipt e Separate status flags for each clock domain push full e FIFO empty half full and full flags gt ck push fase e Parameterized almost full and almost empty flags Pua an e FIFO push error overflow and pop error puse underflow flags oid e Single clock cycle push and pop operations pop req n pin e Parameterized byte order within a word pop af e Word integrity flag for f cik pop Mr i pop error data in width lt data out width rst n e Partial word flush for data in width lt data out width e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk push 1 bit Input Input clock for push interface clk pop bit Input Input clock for pop interface rst n 1 bit Input Reset input active low push req n 1 bit Input FIFO push request active low flush n 1 bit Input Flushes the partial word into memory fills in O s for data in width lt data out width only pop_req_n lbit Input FIFO pop request active low data in data in width bit s Input FIFO data to push rd data max data in width Input RAM data input to FIFO controller data out width bit s 144 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifoctl s2 sf Asymmetric Synchronous Dual Clock FIFO Controll
252. thesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b In most cases the wall implementation generates both faster and smaller circuits for medium to large sized multipliers c In most cases the nbw implementation generates both faster and smaller circuits for small to medium sized multipliers d Automatically chooses Booth recoded or non Booth recoded architectures depending on constraints e This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc shell variable dw prefer mc inside must be set to true For more details see the DesignWare Building Block IP Users Guide 76 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO2 prod sum1 Multiplier Adder DWO02 prod sum1 Multiplier Adder e Parameterized number of inputs TC e Parameterized word length A B SUM C Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Input data B B width bit s Input Input data C SUM width bit s Input Input data TC 1 bit
253. ting client that has been currently granted or the client designated by park index in park mode 222 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW arbiter 2t Two Tier Arbiter with Dynamic Fair Among Equal Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 p width 1 to5 Width of the priority vector of each client Default 2 park mode Oorl park mode 1 includes logic to enable parking when no clients are Default 1 requesting and park_mode 0 contains no logic for parking park index 0 ton Index of the client used for parking Default 0 output mode 0 or 1 output mode 1 includes registers at the outputs Default 1 output mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Required cla Carry look ahead synthesis model DesignWare Foundation clas Carry look ahead select synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 223 DesignWare IP Family Quick Reference Guide DW arbiter dp Arbiter with Dynamic Priori
254. to 50 Word length of counter a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation 216 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide foe DWOS3 updn ctr Up Down Counter DWOS3 updn ctr Up Down Counter e Up down count control e Asynchronous reset e Loadable count register e Counter enable e Terminal count flag clk reset Multiple synthesis implementations Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data bus up_dn 1 bit Input Count up up_dn 1 or count down up_dn 0 load 1 bit Input Counter load enable active low cen 1 bit Input Counter enable active high clk 1 bit Input Clock reset 1 bit Input Asynchronous counter reset active low count width bit s Output Output count bus tercnt 1 bit Output Terminal count flag Table 2 Parameter Description Parameter Value Function width 21 Width of count output bus Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cla Carry look ahead synthesis model Design Ware Foundation clf Fast
255. to a target environment for faster verification Verified in silicon http www synopsys com products designware docs ds c dwcore usb otg pdf Synopsys Inc 283 DesignWare IP Family Quick Reference Guide dwcore usb1 device Or es Synthesizable USB 1 1 Device Controller dwcore usb1 device Synthesizable USB 1 1 Device Controller The Synopsys DesignWare USB Device Controller UDC is a set of synthesizable building blocks for implementing a complete USB device interface Features include the following e 32 bit Virtual Component Interface e Programmable number of endpoints VCI e Easily configurable endpoint e Maintains address pointer for endpoint organization 0 transactions e Supports up to 15 configurations up e Silicon proven to 15 interfaces per configuration and e USB 1 1 compliant up to 15 alternate settings per interface e AHB Interface amp DMA Engine e Supports all USB standard commands Options e Easy to add vendor class commands e Standard register set Specification e Suspend resume logic provided available e Approximately 12K gates for 5 e Applications supported include physical endpoints pointing devices SCAnnersS Carmerds e Test Environment includes USB faxes printers speakers monitor compliance tests and Bus Functional e Available in Verilog Models e Supports low speed and full speed devices The dwcore usbl1 device data sheet is available at http www synopsys com products designware docs ds c dwco
256. tput FIFO s RAM full output flag including the input buffer of FIFO for data in width lt data out width synchronous to clk push active high ram full 1 bit Output FIFO s RAM excluding the input buffer of FIFO for data in width lt data out width full output flag synchronous to clk push active high part wd bit Output Partial word accumulated in the input buffer synchronous to clk push for data in width lt data out width only otherwise tied low active high push error 1 bit Output FIFO push error overrun output flag synchronous to clk push active high pop empty 1 bit Output FIFO empty output flag synchronous to clk_pop active high pop_ae 1 bit Output FIFO almost empty output flag synchronous to clk_pop determined by pop ae lvl parameter active high pop hf 1 bit Output FIFO half full output flag synchronous to clk_pop active high pop_af 1 bit Output FIFO almost full output flag synchronous to clk_pop determined by pop_af_lvl parameter active high pop_full 1 bit Output FIFO s RAM full output flag excluding the input buffer of FIFO for case data_in_width lt data_out_width synchronous to clk_pop active high pop_error 1 bit Output FIFO pop error underrun output flag synchronous to clk_pop active high data_out data_out_width bit s Output FIFO data to pop
257. trol 0 minimum a 2 maximum a value width bit s Output Minimum maximum value index ceil logo num inputs bit s Output Index of minimum maximum input Table 2 Parameter Description Parameter Values Description width 21 Input word length num_inputs 22 Number of inputs Default 2 Table 3 Synthesis Implementations Implementation Name Function License Required cla Carry lookahead tree synthesis model DesignWare Foundation clas Carry lookahead select tree synthesis model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 63 DesignWare IP Family Quick Reference Guide DWO02 mult Multiplier DWO02 mult Multiplier e Parameterized word length A T e Unsigned and signed two s complement data operation x gt lt PRODUCT B Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Multiplier B B width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed PRODUCT A width B width bit s Output Product A x B Table 2 Parameter Description Paramet
258. ture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal Si 1 bit Input Serial path from the previous boundary scan cell data_in 1 bit Input Input data data_out 1 bit Output Output data so l bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Required str Synthesis model DesignWare Foundation Test IEEE STD 1149 1 196 Synopsys Inc April 2003 DW bc 3 Boundary Scan Cell Type BC 3 e IEEE Standard 1149 1 compliant DesignWare IP Family Quick Reference Guide DW bc 3 Boundary Scan Cell Type BC 3 data in data out e Synchronous or asynchronous scan cells with respect to t ck si 9 e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ mode shift dr q capture en pcapture clk Table 1 Pin Description Pin Name Width Direction Function capture clk 1 bit Inpu
259. ty Scheme DW arbiter dp Arbiter with Dynamic Priority Scheme e Parameterizable number of clients request kf ll cli mask grant e Programmable mask for all clients lock grant index e Park feature default grant when no requests are priory pending locked e Lock feature ability to lock the currently granted client granted arked e Registered unregistered outputs rst n Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Input reset active low request n bit s Input Input request from clients priority n ceil logan bit s Input Priority vector from the clients of the arbiter lock n bit s Input Signal to lock the grant to the current request By setting lock i 1 the arbiter is locked to the request 7 if it is currently granted For lock i 0 the lock on the arbiter is removed mask n bit s Input Input to mask specific clients By setting mask i 1 request i is masked For mask i 0 the mask on the request i is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to client designated by park index granted 1 bit Output Flag to indicate that the arbiter has issued a grant to one of the requesting clients locked 1 bit Output Flag to indicate that the arbiter is locked by a client grant n bit s Output Grant output grant index log n
260. ubpsni ds nu dm 236 EN BUD usque quAXSAMAATYAqASAA XP AATUSAEIDULE RE AER ARE ER UR 237 EY NOD E TEE E E 238 EAM UND EE E E E E qx Did TA EE qu E 239 US om ccm 240 LE FOR swe kwh au dd esque eqR QE DIEN e ee Dici gae 241 ES UNE TE cun soedenzad 63v v bona d oae d did Ed aerea E T o Rh 242 EV BDD BS ouauus 0445455 45 RS JOH EUER a CR E dU cR A n Rcs 243 En x06 DURER Leiqereribesi reet det p QR d DES RR E RECOGE Y GRE 245 lcm o c cererea i a A A A 246 BW ub WU uacenes tueid euurtes s sU EE S a AR a Hes 248 MOMON IP sqadazduet ber qEbCKECqU PEDE E C db EC ER RECEN POE ROG PR ORG 249 UA UNDE Lcctetasa et en fado es appo bepat Dieiede dpt eia dide Ais 250 DW rambist oan eda edce dese oe Xd dad RR XR ace d feces ARD Rs 251 Microprocessors Microcontroller Cores 6 cigs tew d C ese C RO Ep 233 og M 254 Chapter 3 DesignWare Library Verification IP eeeeeeeernnnn 255 fe aerea pad Pes ERE dd Ri qP EE RE REGERE A X dades d dde c 299 Dea Ware YMT Modeli auudtudit debi eee HEN EI PR Ra er ILI PT TELS 256 AMBA AHB Mod ls seceded xk ER VAS RR RR SCR CEP RR dd o 258 AMBAS APB MOI daresbsgeetevasues s PER RES TP rE EEE RR AA 260 Serial Input Output Interface Models 2 055 do o r3 Rt ER 261 April 2003 Synopsys Inc 7 Contents DesignWare IP Family Quick Reference Guide Design Ware FlexModel i12 ur e wa Listing of Pies Models occ cnsescxetewews Ethernet Verification Models
261. ubsystem page 277 Synthesizable RTL dwcore gig ethernet 10 100 Mbps and 1 Gbps Operation page 278 Synthesizable RTL dwcore gig ethernet sub Gigabit Ethernet MAC GMAC Subsystem Synthesizable RTL page 279 PCI Cores dwcore pci 32 64 bit 33 66 MHz PCI Core page 280 Synthesizable RTL dwcore_pcix 32 64 bit 133 MHz PCIX Core page 281 Synthesizable RTL dwcore_pci_express Synthesizable PCI Express Core page 282 Synthesizable RTL USB Cores dwcore_usb_otg USB 2 0 Full Speed On The Go Controller Synthesizable RTL Subsystem page 283 dwcore usbl device USB 1 1 Device Controller page 284 Synthesizable RTL dwcore usb host USB 1 1 OHCI Host Controller page 285 Synthesizable RTL dwcore usbl hub USB 1 1 Hub Controller page 286 Synthesizable RTL dwcore usb2 host USB 2 0 Host Controller UHOST2 page 287 Synthesizable RTL dwcore usb2 device USB 2 0 Device Controller page 288 Synthesizable RTL dwcore usb2 phy USB 2 0 PHY page 289 Hard IP April 2003 Synopsys Inc 23 Chapter 1 Overview DesignWare IP Family Quick Reference Guide IEEE 1394 Cores dwcore 1394 avlink IEEE 1394 AVLink page 290 Synthesizable RTL dwcore 1394 device IEEE 1394 Device Link Controller page 291 Synthesizable RTL dwcore 1394 ohci IEEE 1394 OHCI Link page 292 Synthesizable RTL dwcore 1394 cphy IEEE 1394 Cable PHY page 293 Synthesizable RTL Java Acceleration Core dwcore jvxtreme Java Acceleration
262. ult None depth 2 to 256 Depth in words of memory array Default None err mode Oor 1 Error mode Default 0 0 underflow overflow error hold until reset 1 underflow overflow error hold until next clock rst_mode 0 to 3 Reset mode Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation cl2 Full carry look ahead model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 173 DesignWare IP Family Quick Reference Guide DW stackctl Synchronous Single Clock Stack Controller DW stackctl Synchronous Single Clock Stack Controller e Parameterized word width and depth wr addr e Stack empty and full status flags pus eden wem pop req n rd addr e Stack error flag indicating underflow and overflow e Fully registered synchronous address and flag output fall ports empty Ik e All operations execute in a single clock cycle dis rstn
263. umber of clock cycles to produce a valid Default 3 result The real number of clock cycles depends on various parameters rst_mode O or 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset April 2003 Synopsys Inc 101 DesignWare IP Family Quick Reference Guide DW mult seq Sequential Multiplier aa Table 2 Parameter Description Continued Parameter Values Description input mode 0 or 1 Registered inputs Default 1 0 2 no 1 yes output_mode Oorl Registered outputs Default 1 0 no yes early start O or 1 Computation start Default 0 0 start computation in the second cycle 1 start computation in the first cycle Table 3 Synthesis Implementations Implementation Function License Required cpa Carry propagate adder synthesis model DesignWare Foundation 102 Synopsys Inc April 2003 f DW sqrt seq Sequential Square Root e Parameterized word length e Parameterized number of clock cycles e Unsigned and signed two s complement data multiplication e Registered or un registered inputs and outputs DesignWare IP Family Quick Reference Guide DW sqrt seq Sequential Square Root Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low hold 1 bit Input Hold current operation 1
264. unction a width bit s Input Input data b width bit s Input Input data tc 1 bit Input Two s complement control dplx 1 bit Input Duplex mode select active high Iti 1 bit Output Part1 less than output condition eql 1 bit Output Part equal output condition gtl 1 bit Output Part1 greater than output condition It2 bit Output Full width or part2 less than output condition eq2 1 bit Output Full width or part2 equal output condition gt2 1 bit Output Full width or part2 greater than output condition Table 2 Parameter Description Parameter Values Description width 24 Word width of a and b pl width 2 to width 2 Word width of part1 of duplex compare Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model DesignWare Foundation bk Brent Kung synthesis model DesignWare Foundation 48 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DW cmp dx Duplex Comparator a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide April 2003 Synopsys Inc 49 DesignWare IP Family Quick Reference Guide DW cntr gray Gray Code Counter DW cntr gray Gray Code Counter e Gray encoded output data
265. ut ci2 1 bit Input Part2 carry input addsub 1 bit Input Add subtract select input 0 performs add 1 performs subtract tc 1 bit Input Two s complement select active high sat 1 bit Input Saturation mode select active high avg 1 bit Input Average mode select active high dplx 1 bit Input Duplex mode select active high sum width bit s Output Output data April 2003 Synopsys Inc 39 DesignWare IP Family Quick Reference Guide DW addsub dx Duplex Adder Subtractor with Saturation and Rounding Table 1 Pin Description Continued Pin Name Width Direction Function col 1 bit Output Partl carry output co2 1 bit Output Full width or part2 carry output Table 2 Parameter Description Parameter Values Description width 24 Word width of a b and sum pl width 2 to width 2 Word width of part1 of duplex Add Sub Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple Carry Synthesis Model DesignWare Foundation rpcs Ripple Carry Select Synthesis Model DesignWare Foundation csm Conditional Sum Synthesis Model DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the Design
266. ut Almost full threshold the number of words stored in the FIFO at or above which the almost full flag is active we n bit Output Write enable output for write port of RAM active low empty 1 bit Output FIFO empty output active high almost empty 1 bit Output FIFO almost empty output active high half_full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high wr addr ceil logo depth bit s Output Address output to write port of RAM rd addr ceil logo depth bit s Output Address output to read port of RAM Table 2 Parameter Description Parameter Values Description depth 2 to 274 Number of memory elements used in FIFO used to size the address ports err mode 0 to 2 Error mode Default 0 0 underflow overflow and pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple Carry synthesis model Design Ware Foundation cll Partial Carry lookahead model DesignWare Foundation cl2 Full Carry lookahead model Design Ware Foundation a During synthesis Desig
267. ve high almost empty 1 bit Output FIFO almost empty output active high asserted when FIFO level xae level half full 1 bit Output FIFO half full output active high almost full bit Output FIFO almost full output active high asserted when FIFO level 2 af thresh full 1 bit Output FIFO full output active high ram full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part wd 1 bit Output Partial word active high for data in width data out width only otherwise tied low data out data out width bit s Output FIFO data to pop April 2003 Synopsys Inc 121 DesignWare IP Family Quick Reference Guide DW asymfifo s1 df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag n Table 2 Parameter Description Parameter Values Description data in width 1to256 Width of the data in bus data in width must be in an integer multiple relationship with data out width That is either data in width K x data out width or data out width K x data in width where K is an integer data out width 1 to 256 Width of the data out bus data out width must be in an integer multiple relationship with data in width That is either data in width K x data out width or data out width 2 K x data in width where K is an integer depth 2 to 256 Number of memory element
268. velopment Kit allows designers to focus on their application and get their Bluetooth products quickly to market Also see the following web page for additional information http www synopsys com products designware starip mezoe_ip html 310 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide SMSC USB 2 0 PHY Standard Microsystems Corporation GT3100 USB 2 0 PHY Star IP SMSC USB 2 0 PHY Standard Microsystems Corporation GT3100 USB 2 0 PHY Star IP MacroCell Synopsys provides simulation and timing models for the Standard Microsystems Corporation SMSC GT3100 and GT3200 The GT3100 USB 2 0 PHY Core created by SMSC is a USB IF Hi Speed certified USB 2 0 physical layer PHY transceiver available as an intellectual property IP core for system on a chip developers of USB 2 0 applications The GT3200 also from SMSC is a discrete IC implementation of this PHY core and is also Hi Speed certified The SMSC GT3100 and GT3200 incorporate robust clock and data recovery circuitry with integrated termination providing seamless integration into a wide variety of USB 2 0 applications as well as backward compatibility with existing USB 1 1 protocol devices At 165mW absolute maximum power dissipation the GT3100 operates within the 100mA limit imposed by the USB 2 0 standard The GT3100 and GT3200 connect directly to a USB SIE via the industry standard 16 bit UTMI interface Also see the following web page for additional
269. verflow and pointer corruption e Parameterized word depth e Dynamically programmable almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push req n 1 bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in O s for data in width lt data out width only pop req n 1 bit Input FIFO pop request active low diag n 1 bit Input Diagnostic control active low for err mode 0 NC for other err mode values data in data in width bit s Input FIFO data to push 138 Synopsys Inc April 2003 n DesignWare IP Family Quick Reference Guide DW asymfifoctl s1 df Asymmetric I O Synchronous Single Clock FIFO Controller with Table 1 Pin Description Continued Pin Name Width Direction Function rd_data max data in width Input RAM data input to FIFO controller data out width bit s ae level ceil log 5 depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost empty flag is active af thresh ceil log depth bit s
270. wall Booth recoded Wallace tree synthesis model Design Ware Foundation nbw Non Booth recoded Wallace tree synthesis mdl DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b In most cases the wall implementation generates both faster and smaller circuits for medium to large sized multipliers c In most cases the nbw implementation generates both faster and smaller circuits for small to medium sized multipliers 66 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DWO02 mult 2 stage Two Stage Pipelined Multiplier DWO02 mult 2 stage Two Stage Pipelined Multiplier Parameterized word length Unsigned and signed two s complement data operation Two stage pipelined architecture Automatic pipeline retiming Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A width bit s Input Multiplier B B width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A width
271. width 22 Xa width Word length of b Default None tc mode 0 or 1 Two complement control Default 0 rem mode Oorl1 Remainder output control Default 1 Table 3 Synthesis Implementations Implementation Name Function License Required rpl Restoring ripple carry synthesis model DesignWare Foundation cla Restoring carry look ahead synthesis model DesignWare Foundation cla2 Restoring carry look ahead 2 way DesignWare Foundation overlapped synthesis model April 2003 Synopsys Inc 53 DesignWare IP Family Quick Reference Guide DW div Combinational Divider a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 54 Synopsys Inc April 2003 DW div pipe Stallable Pipelined Divider e Parameterized word length e Parameterized unsigned and signed data operation e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset e Automatic pipeline retiming DesignWare IP Family Quick Reference Guide DW div pipe Stallable Pipelined Divider Table 1 Pin Description P
272. width bit s Input Input data CI 1 bit Input Carry in SUM width bit s Output Sum of A B CD CO 1 bit Output Carry out Table 2 Parameter Description Parameter Values Description width 21 Word length of A B and SUM Table 3 Synthesis Implementations Implementation Name Function License Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare Foundation bk Brent Kung architecture synthesis model DesignWare Foundation csm Conditional sum synthesis model DesignWare Foundation rpcs Ripple carry select architecture DesignWare Foundation clsa MC inside DW carry look ahead select DesignWare Foundation csat MC inside DW carry select DesignWare Foundation fastcla MC inside DW fast carry look ahead DesignWare Foundation April 2003 Synopsys Inc 35 DesignWare IP Family Quick Reference Guide DWO1 add Adder Table 3 Synthesis Implementations Implementation Name Function License Required pprefix MC inside DW flexible parallel prefix DesignWare Foundation a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The performance
273. with software for keeping track of time e Long term exact chronometer When clocked with a 1 Hz clock it can keep track of time from now up to 136 years in the future e Alarm function generates an interrupt after a programmed number of cycles e Long time base counter clocked with a very slow clock signal e Counter wrap mode DW apb rtc APB Interface Register Block Read Write Coherency Counter Synchronization Interrupt Generation Up Counter The DesignWare DW apb rtc Databook is available at http www synopsys com products designware docs 242 Synopsys Inc April 2003 DW apb ssi AMBA APB Synchronous Serial Interface April 2003 AMBA APB interface Allows for easy integration into an AMBA SoC implementation Scalable APB data bus width APB data bus widths of 8 16 and 32 are supported Serial Master or serial slave operation Enables serial communication with serial master or serial slave peripheral devices Independent masking of interrupts Master collision transmit FIFO overflow transmit FIFO empty receive FIFO full receive FIFO underflow and receive FIFO overflow interrupts can all be masked independently Multi master contention detection Informs the processor of multiple serial master accesses on the serial bus Bypass of meta stability flip flops for synchronous cloc
274. xsA3 hA dadukan aaae EE EE ACER UR 170 JUG lg Maes sr a es ee ee ee es eee 171 EU e oy ie oe hehe P3 ioe PH hn Dd dH dO EE qu oes 172 UI GCA HEP 174 Data MECI gcc wnesaesian eee rneeawndep de trcee chins ee eerceness 176 E E E olin E TE oan eye kena Gs baa ea dit d en RS 177 D q v rr 179 LEM did 4 eek ene sheet eu esa see dE EAqueEddubgsxd diesstdeubpsdq es 181 DO DA DE ond 5 can eek a oor QR ERE dE ACE RrHERERUEH HEU eos 183 Data Integrity Coding Group Overview 0c cece eee ee eee 184 Ew Pee dlekgqROSRqiesdqkdsEdadddds MEO E dR dX CIC wees 185 EN BIB EE uuseedadq 239 3 9 Motdo doird der d lero Rie or hom 187 LW ODLO BAD ausscasqdUtakes34XeR 34 US ICIERDERACR HERRERA eens A 188 fi WE eee uou MTM 189 c o ea reor 190 US X modem 192 EW BB xerpebcpedadid da bowed ound an dadas E A EE 195 EM DE E ER E E A dA dii eed oxud ipid d ido addi dia uo MR 196 EN DA ee ee ee re er qaia ee eee ee E E dE K t 197 EN DET eee ee eee ee t eee ee ee ee ee eee ee ee 198 a dA s HTTP ND TTD 199 g o TT vc 200 Logic Combinational Overview Loss akdewex ex RERO dA 202 DWO PIT erento ram i ona qp Hon oid dos dli hae ddoicdbdor n ees 203 OWOL Jode ee ee ae XRAVASESQEDEE E ee ree 204 ONUL MU HUY cirseridsirariedeiridei YR EC RR qud E OR eee 205 UI QUUM P oes 206 Logic Sequential Overview cuoaesusasRR ER VARY ARE REX GR X
275. y using DFT Compiler S test clk rst n Table 1 Pin Description Pin Name Width Direction Function rst n bit Input Reset active low cs n 1 bit Input Chip select active low wr n 1 bit Input Write enable active low test mode 1 bit Input Enables test clIk test clk bit Input Test clock to capture data during test mode rd addr ceil logo depth bit s Input Read address bus wr addr ceil logo depth bit s Input Write address bus data in data width bit s Input Input data bus data out data width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data width to 256 Width of data in and data out buses depth 2 to 256 Number of words in the memory array address width rst mode Oor 1 Determines if the rst n input is used 0 rst_n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Required str Synthesis model Design Ware Foundation 164 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide 100111001 RAM DW ram r w a lat 01101001 Asynchronous Dual Port RAM Latch Based DW ram r w a lat Asynchronous Dual Port RAM Latch Based wr_addr rd_addr data_in e Parameterized word depth e Parameterized data width e Asynchronous static memory cs_n e Parameterized reset impl
276. ynchronous RAMs wen wr addr push word count push empty push ae push hf push af push full push error push req n gt clk push pop req n rd addr pop word count pop empty pop ae pop hf pop af pop full pop error ret n clk pop test Table 1 Pin Description Pin Name Width Direction Function clk push 1 bit Input Input clock for push interface clk pop 1 bit Input Input clock for pop interface rst n 1 bit Input Reset input active low push req n 1 bit Input FIFO push request active low pop req n 1 bit Input FIFO pop request active low we n 1 bit Output Write enable output for write port of RAM active low push empty 1 bit Output FIFO empty output flag synchronous to clk push active high push ae l bit Output FIFO almost empty output flag synchronous to clk push active high determined by push ae Ivl parameter push hf l bit Output FIFO half full output flag synchronous to clk push active high push af l bit Output FIFO almost full output flag synchronous to clk push active high determined by push af Ivl parameter 152 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide AT DW fifoctl s2 sf Synchronous Dual Clock FIFO Controller with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function push full l bit Output FIFO full output flag
277. ys Inc 305 DesignWare IP Family Quick Reference Guide DW TriCore1 TriCore1 32 Bit Processor Core from Infineon DW TriCore1 TriCore1 32 Bit Processor Core from Infineon Sv 5 The Infineon TriCorel is the first unified MCU DSP architecture in a single core ideally suited to SoC applications that require both microcontroller and DSP functionality With high performance low cost and minimal power consumption the 32 bit TriCorel superscalar processor meets the needs of automotive industrial mass storage communications and other applications that require DSP and more processing power than a 16 bit processor can provide Other features include the following 306 2 bit load store architecture Dual instruction use 4 GB address range General Purpose Register Set GPRS o Sixteen 32 bit data registers Dx o Sixteen 32 bit address registers Ax o Three 32 bit status amp program counter registers PSW PC PCX Shadow registers for fast context switching Automatic context save on entry and restore on exit for subroutine interrupt amp trap Two memory protection register sets Instruction formats 16 bit and 32 bit Byte amp bit addressing Saturation integer arithmetic Packed data Data and instruction caches optional Synopsys Inc Data types boolean integer with saturation bit array signed fraction character double word signed unsigned integers IEEE 754 single precision floatingpo
278. z USB 1 1 2 0 Bus Host Interface Model usbhost fz Emulates the functions and timing of the Universal Serial Bus USB Host Supports Revisions 1 1 and 2 0 of the USB Specification Split Control Interrupt Isochronous and Bulk transactions High speed full speed and low speed transactions CRC generation on transmission CRC checking on reception Error generation injection for the following fields Sync PID CRC5 in NRZI encoding with bit stuffing Automatic bit rate change after preamble packet Programmable resume suspend time One downstream port Three port states awake default suspend and resume Dynamic attach or detach bus enumeration using the usbhost attach detach command Internal data banks used by the model to perform bulk data transfers token packet CRC16 in data packet Status indication for IN and OUT EOP and Bit stuffing e Status indication for IN an usbhost fz functionality Root Hub The individual DesignWare FlexModel databooks can be found with each model at http www synopsys com products designware ipdir 266 Synopsys Inc April 2003 DesignWare IP Family Quick Reference Guide DesignWare Memory Models DesignWare Memory Models DesignWare Memory Models are pre verified simulation models of memory devices The DesignWare Memory Models are built on top of the Synopsys MemPro memory model technology thus ensuring model accuracy quality and reliability

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