User manual MSC TDC10000, Rev. 2.3
Contents
1. MSC User Manual MSC TDC10000 Page 7 of 47 4 Package and Pin Configuration 4 1 Package 23 8 gt 20 0 ss xj A lo 64 41 A e 65 40 o TDC10000 PQFPS0 g 2 Top View 80 25 V1 24 Y Y 0 8 08 9 y e MEN YY i N Figure 4 1 Package Dimensions in mm 4 2 Pin Configuration Table 4 1 shows the TDC s pin configuration Pin No _ Pinname__ VO__ Function 5 11 20 25 33 VDD Supply voltage 51 53 73 80 4 8 12 13 21 VSS Ground 26 29 32 39 41 50 52 54 64 72 76 79 TDC10000RefManEngV23 doc Version 2 3 tdcfamsc ge com WWW msc ge com Author UW AP MSC User Manual MSC TDC10000 Page 8 of 47 3 22605 QUnmoneced 0 0 ENOSZ In Enable calibration clock input 0 CALCLK input enabled can be disabled enabled by software 1 CALCLK input disabled cannot be enabled by soft ware Rate 4mA 9 OSZ ke Inverted output of the on chip oscillators CALCLK Calibration clock input 500 kHz 10 MHz2. CAL2 with auto noise CAL2 different offsets generated by auto noise unit VAL with auto noise m VAL CALI with auto noise CALI OFFSET with auto noise OFFSET offset enlargement by delaying the stop signal tCALI tVAL Figure 6 5 Influence of the Auto Noise Unit on the Characteristic of the TDC Measuring Core If the auto noise unit is enabled a channel specific delay is generated by a pseudo random number generator This delay is changed with every new measurement and added to the already existing offset of the respective channel The auto noise unit is available only in the measurement modes 0 and 3 TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 20 of 47 6 3 4 Delay Line When the delay line is enabled by software an additional offset of approx 100ns 5V typ is gen erated for both channels Due to transient effects delaying the channel s stop signal often leads to a higher precision accuracy when measuring time differences 20ns An enabled delay line will also increase the channel s dead time by the amount of offset 6 3 5 Measuring Core The measuring core of a channel determines the time interval between a start and a stop signal with a typical resolution of 60ps 5V 25 C The measuring core then provides measurement or calibra tion values a
3. Reads the internal multiplication factor of the resolution lock unit s Latch 8 RDKOMO Reads the value of the characteristic quantity MO of channel 0 If 16 fold accuracy is selected this value is 16 times as large as with 1 fold accuracy RDK1M0 Reads the value of the characteristic quantity MO of channel 1 If 16 fold accuracy is selected this value is 16 times as large as with 1 fold accuracy WRLOCKMOD Writes the LOCKMOD Register of the resolution lock unit WRLOCK Writes the external multiplication factor into the LOCKREG Register of the resolu tion lock unit WRDAISY Starts the daisy chain configuration cycle and the chip number assignment SETTOKEN Sets the token This instruction must always be local RESTOKEN Resets the token set by SETTOKEN default DAIRDON Turns on the daisy chain read mode DAIRDOFF Turns off the daisy chain read mode default EXOSZON Enables the calibration clock input CALCLK default if not disabled by pin ENOSZ EXOSZOFF Disables the calibration clock input CALCLK HOLD Switches the resolution lock unit to Hold Mode TRACK Switches the resolution lock unit to Track Mode default INVALID Invalid opcode no operation is executed COMABORT Aborts the read instructions RDKO and RDKI even when the corresponding FIFO isn t empty If only a part of a measurement result is read e g the fractional por tion in the 16 bit mode before COMABORT is executed the
4. 0 Now a new instruction is accepted by the TDC If not all of the measurement results have to be read the instruction can be aborted by the instruction COMABORT Opcode31 If not reading out a measurement result immediately after a measurement but waiting until another measurement is completed and stored in the Result FIFO then both results can be read without having to rewrite RDKO RDK1 Reads the measurement results form channel 1 This read instruction is only activated if the FIFO of channel has at least one valid measurement result for readout and the flag VALIDI is set to 1 The instruction remains active until the last measurement result of channel 1 is read out and VALIDI is cleared to 0 Now a new instruction is accepted by the TDC If not all of the measurement results have to be read the instruction can be aborted by the instruction COMABORT Opcode31 If not reading out a measurement result immediately after a measurement but waiting until another measurement is completed and stored in the Result FIFO then both results can be read without having to rewrite RDK1 RDSTAT Reads the Status Register RDMREG O Reads register MODREGO of channel 0 RDMREGI Reads register MODREGI of channel 1 RDGREGO Reads register GLOBREGO RDGREGI Reads register GLOBREGI TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 35 of 47 RDLOCK
5. 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 33 of 47 7 1 1 List of Instructions Opcodes x Reser 0o Software Reset of all registers except GLOBREGO 1 1 CYCLE us oo dia LwmwREGI 4 wieMoDREGIdumd 23 CYCLES gt CYCLES RE KO Ki WRGREGI l6 Write GLOBREGI 2 5 CYCLES 2 CYCLES WROFFO Write OFFSETO channel 0 2 3 CYCLES 2 CYCLES LwmOFE 8 WiiteOFFSETI chamai 25 C CLES 2 CYCLES RDKO 9 Read measurement results chameto 5 CYCLES 2 CYCLES oe oo JONES ue oe os o 18 RDKIMO Read MO channel 1 3 4 CYCLES 2 CYCLES 0 1 2 3 4 5 6 7 8 9 1 CYCLE SETTOKEN Set token by software DAIRDON EA Turn on daisy chain read mode VOYGDE 1 CYCLE DAIRDOFF 24 Turn off daisy chain read mode EXE 1 CYCLE WRLOCKMOD Write register LOCKM OD of the resolution lock unit 2 3 CYCLES 2 CYCLES WRLOCK Write external multipl factor of the resolution lock unit 2 3 CYCLES 2 CYCLES WRDAISY Start daisy chain config cycle chip number assignment 2 3 CYCLES 2 CYCLES Rn EXOsZOFF 27 Disbeciibr ondodeipuCALCLK 2 CYCLES 1 CYCLE HOLD 28 switch esotuionockunitonoLD CYCLES 1 CYCLE a LNVAUD 30 inaigopcope noain d IE Notes 8 Bit Mode First number is the number of cycles needed as global instruction second number is the number of cycles needed as local instruction RDKO and
6. P1 0 SERM g P1 1 RLOCKON fae STOINHO D lt 8 15 gt PiS Start 1 S PLS D STARTI BIT816 A P16 Stop 1 STOP P16 pios P0 4 STOINHI P0 5 P0 6 INHMD P0 7 PSEN ALE PROG TOKOUTO TOKOUTI WAIT lOuF Vcc ni Vec Dedel E 3 3k vi rtiai pi ol 47k 33R S6k 47yF HEKO 9 1k i Figure 8 4 TDC10000 Single Chip with AT89C51 Notes 8 bit data bus for AT89C51 External PLL wiring Resolution lock unit activated by software On chip oscillator generates calibration clock All unused outputs should be left unconnected TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com
7. detailed description of the individual register bits is given in Chapter 7 3 1 Mode Registers MODREGO 6 6 3 Global Registers There are two Global Registers for configurations concerning both channels The width of these registers is 8 bit Here the division factor for the calibration clock divider is selected the automatic MO measurement can be disabled and the resolution lock unit is activated Furthermore the daisy chain is configured here For detailed information on the individual register bits refer to Chapter 7 3 2 Global Register GLOBREGO and Chapter 7 3 3 Global Register GLOBREGI 6 6 4 Offset Registers There is one Offset Register for each channel The width of these registers is 8 bit Here a correction value is stored for the ALU to prevent the ALU going into overflow when measuring very small time differences on the respective channel see also Chapter 7 3 4 Offset Registers OFFSETO 1 6 6 5 Status Register The Status Register of the TDC reflects the present status of the TDC It contains six status flags which are described in detail in Chapter 6 8 2 Status Flags 6 6 6 MO Registers Both measurement channels have their own MO Register in which the characteristic quantity MO generated by the respective measuring core is stored for further processing by the ALU If MO is not generated automatically during a measurement then MO can also be generated and stored executing a separate MO measurement TDC10000RefManE
8. LASTCHIP and TKSEL in the register GLOBREGI to 1 will configure this chip to hold the WAIT line at 0 after the last measurement result is read out It has to be taken into account that in this configuration the token is supplied by the output TOKOUTI TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 29 of 47 6 9 2 Daisy Chain Read Mode The daisy chain is read out in a similar way as it is configured After a measurement several chips have one or more valid measurement results ready for readout Writing the global instruction DAIRDON all TDCs are set to the daisy chain read mode available only in the 16 bit mode In the daisy chain read mode every chip waits for the token The first chip selected to be read which does not have to be the first chip of the daisy chain receives the token from one of the tokenin pins or by the local software instruction SETTOKEN If no measurement results are ready for readout the token is passed on to the next chip in the chain immediately with a delay of approx 10ns SV typ If the chip has valid measurement results for readout the chip retains the token and its data are read out with every read strobe in the following order First the measurement results of channel 0 are read if there are any then the measurement results of channel 1 and finally a special status word if the special daisy read mode is selected withi
9. This signal can be used low pass filtered as analog con trolled variable of the analog part of the PLL which has to be realised externally With the TDC external analog part controlling the supply voltage of the TDC10000 and the frequency of the ring TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 22 of 47 oscillator the loop control of the PLL is closed When the temperature is falling on the chip the supply voltage will decrease when the temperature is rising the supply voltage will rise too Int Ext Val Ext O 8 5 MUX O oo 2 1 8 z g Load 21 oo ON OFF _ Ringosz Phasen OO Puk diskr CLK REF Divider Control s Unit Track Hold Figure 6 6 TDC internal Part of the PLL The value of the Latch 8 can be read out via the processor interface Furthermore there is the possi bility of using an external multiplication factor instead of the internal value of Latch 8 This exter nal factor has to be written into the register LOCKREG Using an external multiplication factor some interesting applications are possible e Once adjusted the resolution is accurately reproducible quartz accuracy at any time by re writing the same multiplication factor In this way different envi
10. independently for both channels in the measurement modes 0 and 1 measurement range I TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 19 of 47 6 3 3 Auto Noise Unit The characteristic of the TDC is a straight line with offset and upward gradient which due to the digital measurement procedure possesses quantisation stages so called LSBs Least Significant Bits with the width of the resolution For a single measurement one therefore gets a quantisation error of up to one quantisation stage at ideal quantisation This precision is sufficient for most ap plications A higher precision can be achieved when the measurement of the same time is repeated several times and statistical methods are used Changing the existing offset of the characteristic for each single measurement by delaying the stop signal according to Figure 6 5 causes sampling at different positions of the characteristic especially when measuring very constant time differences of a low noise signal If the same offset shift is still present during generation of the calibration values for the associated measurement value the total offset is eliminated during the time difference calculation according to the formulas 1 and 2 When averaging all the single measurements there quantisation errors are averaged as well quantisation stage Measurement result width resolution
11. out of the last chip Otherwise the processor would remain in the Wait State After turning on the daisy chain read mode the WAIT line remains 0 and isn t pulled up to 1 until the first rising edge of the read strobe So if the WAIT control is used for reading out the daisy chain the following steps are to be executed for each read sequence Turn on the daisy chain read mode 2 Setthe token via tokenin pin or by instruction 3 Wait for 10ns number of chips 5V typ so that the token has time to reach a chip with valid measurement results or to drop out of the last chip in the chain if no valid results are available 4 Read out the daisy chain until the token drops out of the last chip 5 Turn off the daisy chain read mode 6 Remove token If the WAIT control is not used the daisy chain read mode may remain active and the token may be removed and set again before starting the next read sequence TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 30 of 47 6 9 3 Processorless Mode For single chip applications the Processorless Mode is selectable by setting pin NOPROC to 1 In this mode no configuration of the TDC is possible All measurements are performed in measure ment mode 0 the Default Mode So before switching to the Processorless Mode be sure to execute a power on reset guaranteeing the TDC to be in default state
12. the bits 4 0 the opcode of the instruction is stored If the instruction is an in struction with two or more cycles the corresponding number of read or write strobes has to fol low Global 16 bit instruction One word is written into the TDC with bit 5 GLOBAL BIT set to 1 Bits 4 0 contain the op code of the instruction All other bits doesn t care If the instruction is an instruction with two or more cycles the corresponding number of read or write strobes has to follow Important notes 1 If several TDCs share a common bus a global read instruction may have fatal effects If all TDC10000 connected to the common bus access at the same time bus conflicts will occur and the TDCs or other components may be corrupted Therefore after power on a daisy chain con figuration cycle should be executed so that each chip gets its unique chip number see Chapter 6 9 1 This chip number must not be 31 TDCs having a chip number different from 31 ignore global read accesses After chip number assignment bus conflicts are impossible 2 If a TDC10000 is operated as single chip all instructions can be executed as global instructions because no bus conflicts are possible Global read instructions are only accepted if a TDC has the default chip number 31 Therefore a stand alone TDC with the chip number left unchanged within the register GLOBREGI1 after power on will accept all global read instructions TDC10000RefManEngV23 doc Version
13. 0000 Page 26 of 47 6 8 1 Data and Control Lines 6 8 1 1 Overview The TDC 10000 provides the following data and control lines e D 15 0 Bi directional data bus e CS Chip select low active e RD Read strobe low active e WR Write strobe low active e BUSDIR Indicates the current bus direction For optimal adjustment to the data structure of the connected processor and its data bus width the width of the TDC s data bus is set to 8 bits 8 bit mode or 16 bits 16 bit mode by the pin BUS816 6 8 1 2 Timing Diagrams Figure 6 9 shows the timing for read and write cycles Please notice that in 8 bit mode the data lines D 15 8 remain High Z at all times WRITE Timing Dat Chipselect gt 20ns fF xa Write Read Figure 6 9 READ and WRITE Timing of the Processor Interface typical at 5V 25 C TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com User Manual MSC TDC10000 MSC Page 27 of 47 6 8 2 Status Flags For interrupt generation at the connected processor the TDC provides six status pins READYO READYI VALIDO VALIDI SYSERR CALM Channel 0 ready for measurement Channel 1 ready for measurement Channel 0 has valid measurement results for readout Channel 1 has valid measurement results for readout Overflow error channel independent TDC is calm no measurement is running at the moment All status pins are d
14. 14 TH In Track hold selection for PLL 0 Track Mode default 1 Hold Mode 16 RLOCKON In Resolution lock unit 0 off default 1 on 17 INHMD In Automatic MO measurement 0 off 1 on default 18 STOINHO In Stop inhibit channel 0 0 STOPO input enabled 1 STOPO input disabled STOINHI In Stop inhibit channel 1 0 STOPI input enabled 1 STOP1 input disabled Start input channel 1 Stop input channel 1 Enable channel 1 0 channel 1 disabled cannot be enabled by software 1 channel 1 enabled can be disabled enabled by software Processor interface ENAI BUS816 0 16 bit data bus 1 8 bit data bus Write strobe low active In STARTI STOPI RD ALU speed 0 fast default 1 slow Processorless mode 0 off default 1 on WAIT Out Open WAIT output for daisy chain read sequence Drain 8mA DO Bidi 8mA_ BitO data bus Bidi 8mA Bitl data bus Bidi 8mA Bit2 data bus TOKINO TOKINI NOPROC TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 9 of 47 48 D6 Bidi 8mA__ BitOdatabus o o O 5 D8 Bidi 8mA Bit8 databus O 56 D9 Bidi 8mA Bit9 databus 00 D13 Bidi 8mA jBil3daabus o O Out Open Bus direction indicator Drain 8mA 0 when RDN 0 data direction is Out HiZ else data direction is In pull up resistor necessary EM cil oris BN Speed 4mA Speed 4mA P EN a 0 n
15. 3 Bit2 Bitl Bit Function x x x x x x O internal multiplication factor is used x x x o jo 0 x Reference clock divider 1 64 x x x fo fo fi fx Reference clock divider 1 128 __ _ x x x o i fo fx Reference clock divider 1 256 x x x jo I i fx Reference clock divider 1 512 x x x 1 fo fo fx Reference clock divider 1 1024 x x x 1 fo i fx Reference clock divider 1 2048 x x x 1 l fo fx Reference clock divider 1 4096 o O jo x x x x intemal ringoscillator clock divider 1 16 o fo i fx fx fx x intema ringoscillator clock divider 1 32 o I fo x x x jx intema ringoscillator clock divider 1 64 o I I x fx x x intemal ringoscillator clock divider 1 128 1 fo fo fx x fx x intemal ringoscillator clock divider 1 256 1 o 1 x fx x jx intemal ringoscillator clock divider 1 512 Ho 1 fo x fx fx jx intema ringoscillator clock divider 1 1024 Note If the clock dividers factors of reference clock and ring oscillator clock are identical examples and then the reference clock is the ringoscillator clock divided by four Table 7 2 LOCKMOD Register of the Resolution Lock Unit BitO of LOCKREG selects whether the unit is to be operated with the internal or with the external multiplication factor Bits 1 2 and 3 adjust an additional division factor for the reference clock Bits 4 5 and 6 adjust an additional division factor for the i
16. 6 5 4 3 2 1 0 p321 10 9 8 7 6 5 4 3 2 1 0 Example 689 68023 689 11145 16384 16384 2 2 14 1j0 1jo 1j1 0j0j0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 T INTEGER 689 FRACTION 11145 Figure 7 2 Read Registers and Data Format of Measurement Results TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 37 of 47 7 3 Write Registers The default value of all write registers is 0 The default chip number of the Global Register GLOBREGI is 31 The only register having no default is the LOCKMOD Register When writing new data into these registers in 16 bit mode be sure to provide them via data lines D 7 0 of the data bus 7 3 1 Mode Registers MODREG0 1 Channel 0 is configurated by MODREGO channel 1 is configurated by MODREGI These registers are identical and independent of each other Bit1 and Bit MEASUREMENT MODE MESSMODE1 MESSMODEO0 Binary coded measurement mode 00 Measurement mode 0 default 10 Measurement mode 2 01 Measurement mode 1 11 Measurement mode 3 Bit2 SEPARATE MO MEASUREMENT MO GEN Setting this bit to 1 generates a new characteristic quantity MO for the respective channel no matter if the channel is disabled or not by software or pin MO is generated with 1 fold accuracy or 16 fold accuracy depending on the configuration and stored in the appropriate MO Register After completion of the separate MO measurement thi
17. A ppp interface TOKOUTT I 0 ENAI STOINHI CLKR PHASE TH RLOCKON WAIT Figure 3 1 TDC10000 Block Diagram The TDC offers two independent measurement channels 0 and 1 for time measurement between the rising falling edge of a signal at the start input and the rising falling edge of a signal at the stop in put with a typical resolution of 60ps 5V 25 C The measured values are processed within the ALU Arithmetic Logical Unit Up to four measurement values can be stored in the channel s Re sult FIFO and read out via the processor interface The configuration of the TDC as well as the selection of the measurement mode and range is done by writing the TDC registers via the processor interface Status information can be accessed by reading the TDC registers The resolution lock unit is used for stabilisation the TDC s resolution The daisy chain interface allows cascading of up to 31 TDCs The calibration clock necessary for the calibration of the measurement values has to be supplied by an external oscillator clock at the input CALCLK The calibration clock is divided by the inter nal clock divider TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com
18. DC oscillator circuit consists of an inverting amplifier element only The external components consist of one quartz crystal two capacitors C1 and C2 and one resistor Rf Disable i CALCLK Cl CALCLK TDC10000 i amplifier quartz W Rf C2 ji OSZ Dx CALCLK Figure 6 1 On Chip Oscillator If the on chip oscillator is not used then an externally generated clock has to be connected to pin CALCLK In this case the pin OSZ is not connected The calibration clock input CALCLK is en abled or disabled by the pin ENOSZ If the calibration clock input is enabled by ENOSZ it can also be enabled and disabled by software 6 2 Calibration Clock Divider Figure 6 2 shows the principle function of the calibration clock divider CALCLK CALCLKI mnnnr PE 1 16 Figure 6 2 Calibration Clock Divider TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 17 of 47 The external calibration clock CALCLK is divided by the TDC s calibration clock divider The division factors are programmable and can be 1 4 8 and 16 Since calibration measurements are always done by a TDC s measuring core it is necessary to en sure that the clock period of the divided calibration clock is not larger than 3us 5V typ otherwise the measurement of two calibration clock periods would cause a measurement range overflow In order to achieve high precisio
19. In the Processorless Mode there is no the need of any opcode or chip number and the TDC can be controlled using just simple logic The measurement results can be read out using only the correct number of read strobes according to the selected bus width First the measurement results of chan nel 0 are read if there are any then the measurement results of channel 1 When the last result has been read further read strobes will cause the measurement results to be read again however this data will not be valid signified by the VALID flags set to 0 TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 31 of 47 7 Programming of the TDC10000 All instructions written into the TDC s Instruction Register are decoded by the TDC If meant for it the instructions are executed 7 1 Execution of Instructions The following steps are necessary so that the TDC10000 executes an instruction At first the TDC must recognise that an instruction is meant for it This is done by either addressing the chip directly or by selecting all chips connected to a bus The TDC is addressed directly by a local instruction that contains the opcode of the instruction and a chip number see Figure 7 1 If this chip number corresponds to the chip number assigned to the TDC during the daisy chain configuration cycle then the TDC executes the instruction In 8 bit mode the chip number and the opcod
20. LAY LINES DELAY 0 off default 1 on Bit4 MEAS CALC SUPPRESSION INHM 0 Simultaneous measurements and ALU calculations allowed default 1 Either measurements or ALU calculations Bit6 and Bits CALIBRATION CLOCK DIVIDER CALDIV1 CALDIVO 00 1 1 default 10 1 8 Ol 1 4 11 1 16 Bit7 RESOLUTION LOCK UNIT RESLOCK 0 off if pin RLOCKON 0 default 1 on TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 39 of 47 7 3 3 Global Register GLOBREG1 GLOBREGI is the configuration register of the daisy chain interface Bit4 to Bit0 CHIPNUMBER After power on reset the default chip number is 31 TDCs having this chip number ac cept all global instructions even the read instructions This is useful for single chip ap plications because no chip number has to be assigned when global instructions are used Bits TOKENOUT SELECT TKSEL This bit selects which output will pass on the token Setting the bit to 0 selects TOKOUTO setting the bit to 1 selects TOKOUTI Bit6 LASTCHIP This bit acts in combination with the WAIT line If the daisy chain read mode is con trolled by the WAIT this bit and bits TKSEL have to be set to 1 during the configu ration of the last chip of the chain so that the connected processor doesn t remain in the Wait State after all results are read out Bit7 SPECIAL DAISY READ STA
21. ML Hyg EM EM ALIE LII User Manual MSC TDC10000 Version 2 3 Date 2010 01 13 MSC Vertriebs GmbH IndustriestraDe 16 76297 Stutensee Germany Author UW AP Phone 49 7249 910 205 Fax 49 7249 910 268 Email UW msc ge com MSC All rights reserved Although great care has been taken in preparing this document MSC can not be held responsible for any errors or omissions All information in here is subject to change without notice All hardware and software names used are trade names and or trademarks of the respective owners tdcfamsc ge com www msc ge com MSC User Manual MSC TDC10000 Page 2 of 47 Contents 1 INIBODUCTIQON aateissisettxin tebke ete XE EH RN P0 RE centasosenatenseedecedscensseasastonsesdendeaosstasd scenceenseainses 4 2 FEATURES m 5 3 OBLOCK DIAGRANI iainirieeh ie eR RIVE EE UNIO UD REPREHENE HPV EN TERRAS EE PIRE 6 4 PACKAGE AND PIN CONFIGURATION ecce esee esee en seen essen setas tasses estos esteso 7 4 1 PACKAGE TO EEES 7 S2 PIN CONFIGURATION L2 cisctbeieaSutusduiuc abii ite ne isea i a UP Ed duse iSS E eS Ma edet E 7 5 MEASURING PROCEDURE iisrh bir etpe tio ERR ERER SFr E ERN FERE RUPP FERRE YE LIU RPXE EIER XY FUR Do ODER EK ERI 10 5 1 TIME DIFFERENCE MEASUREMENT sesssssssssseseesseseeestessesetsstesesetsstessesetsstensessessrenseestese
22. Now all chips wait for the token and a simultaneous write strobe to store their daisy chain configuration and chip number The token is sent to the first chip by setting one of the tokenin pins to 1 With the rising edge of the following write strobe the 8 lower data bus lines are written into the register GLOBREGI This register contains the information about the chip number which token output is used and how the chip will react when the chain is read out A description of the individual bits of GLOBREGI is to be found in Chapter 7 3 3 Global Register GLOBREGI Then the token is passed on to the next chip This sequence is continued until the token drops out of the last chip in the chain This event can be set up to interrupt the connected processor which ends the configuration cycle by removing the token from the first chip After configuration each chip should have its unique chip number which will enable direct ad dressing The chip numbers should be assigned in a descending order in which the chip number 0 has to be assigned to the last chip in the chain If for example all possible 31 numbers are assigned the chips should be numbered descending from 30 down to 0 If the WAIT outputs of the TDCs pins WAIT are used for the control of the connected processor the last chip in the daisy chain has to be configured especially so that the processor doesn t remain in the Wait State after reading the last measurement result Setting the bits
23. R 47k 10R from uC gt a a 9 1k Figure 6 7 TDC external Part of the PLL 6 5 5 Power Consumption Normally when the resolution lock unit isn t enabled the quiescent current of the TDC10000 is in the range of nanoamperes When the resolution lock unit is activated the ring oscillator will cause a quiescent current consumption of approx 20mA In addition the external circuit will increase the quiescent current consumption TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 24 of 47 6 6 TDC Registers 6 6 1 Instruction Register The configuration of the TDC the readout of measurement results or the TDC s status is controlled by instructions that are written into the Instruction Register A detailed description of the TDC in structions can be found in Chapter 7 1 Execution of Instructions 6 6 2 Mode Registers The TDC provides two Mode Registers one for the configuration of channel 0 and one for the con figuration of channel 1 The width of the registers is 8 bit In these registers the measurement mode as well as the edges of the start and stop signals on which the respective channel will trigger are selected So it s possible to set up one channel to measure a large time difference and at the same time the other channel to measures the pulse width of the much shorter start or stop pulse A
24. RDK1 Minimum number of cycles needed for these opcodes see Chapter 7 1 2 RESTOKEN 25 Reset token set by software a a i Ex E o amp Table 7 1 List of Instructions Opcodes TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 34 of 47 7 1 2 Description of the Instructions RESET Software Reset Resets the chip to its default state except of GLOBREGO GLOBREGI and the MO Registers RESKO Software Reset Channel 0 Resets Channel 0 and MODREGO to the default state Meas urement results already stored in the Result FIFO of channel 0 are not deleted RESK1 Software Reset Channel 1 Resets Channel 1 and MODREGI to the default state Meas urement results already stored in the Result FIFO of channel 1 are not deleted WRMREGO Writes Mode Register MODREGO of channel 0 WRMREGI Writes Mode Register MODREGI of channel 1 WRGREG0O Writes Global Register GLOBREGO WRGREGI Writes Global Register GLOBREGO WROFFO Writes Offset Register OFFSETO of channel 0 WROFFI Writes Offset Register OFFSET1 of channel 1 RDKO Reads the measurement results form channel 0 This read instruction is only activated if the FIFO of channel O has at least one valid measurement result for readout and the flag VALIDO is set to 1 The instruction remains active until the last measurement result of channel 0 is read out and VALIDO is cleared to
25. TUS WORD SDRSW If this bit is set to 1 then during a daisy chain read sequence a special status word SDRSW is read instead of measurement results from chips still running measurements or chips with the overflow bit set This status word has its highest bit set to 1 Bit relevant only for 16 bit mode 7 3 4 Offset Registers OFFSETO 1 In these registers correction values are stored for ALU calculations preventing the ALU to go into overflow when measuring very small time differences A wrong value written into an offset register may cause the ALU to go Out of Range Therefore it s highly recommended not to change the default value 0 of the offset registers If changing nevertheless then the 8 bit value to be written is a two s complement Values of 30 shouldn t be exceeded If measurement errors of 10ns or more should occur during measurement then please change the value of the respective Offset Register to smaller absolute values TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 40 of 47 7 3 5 LOCKMOD Register This register is the configuration register of the resolution lock unit It has no default settings Therefore this register has to be initialised before activating the resolution lock unit When using a 4 MHz reference clock and the internal multiplication factor 0 is recommended for initialisation Bit Bits Bit4 Bit
26. a Mode Register is to be written then the TDC expects a further write strobe to store the new data provided on the data bus In doing so the execution of the instruction is completed and after this the TDC accepts a new instruction The same procedure applies to a read The TDC after decoding the opcode for reading e g the Status Register expects a read strobe to put the contents of the Status Register on the bus In accordance with Figure 7 1 there are four types of instructions Local 8 bit instruction Writing a local 8 bit instruction into the TDC needs two write cycles 1 Bit 6 of the first byte has to be set to 1 indicating the five lower bits to be the chip number Bit 5 is set to 0 2 The five lower bits of the second byte contain the opcode of the instruction The three upper bits should be set to 0 If the instruction is an instruction with three or more cycles the corresponding number of read or write strobes has to follow Global 8 bit instruction Writing a global 8 bit instruction into the TDC needs only one write cycle Bit 5 GLOBAL BIT is set to 1 and bit 6 is set to 0 The five lower bits contain the opcode of the instruction If the instruction is an instruction with two or more cycles the corresponding number of read or write strobes has to follow Local 16 bit instruction One word is written into the TDC with bit 5 GLOBAL BIT set to 0 Bits 12 8 contain the chip number in
27. amsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 42 of 47 8 2 Accuracy of Measurement 8 2 1 Measurements in Measurement Mode 0 Default Mode When measuring in measurement mode 0 immediately after time measurement a calibration meas urement is executed Caused by the preceding measurement the supply voltage of the TDC10000 is still unstable during generation of the first calibration value If the calibration clock is generated using the on chip oscillator see standard wiring the interference is passed to the oscillator which reacts with higher jitter Thus an additional error of up to several hundred picoseconds may be added to the result of the first calibration value Therefore measurement mode 0 is not recom mended for reaching the highest possible measurement accuracy when using the on chip oscillator This effect can be reduced significantly when using an external calibration clock instead of the on chip oscillator In this measurement mode measurements with a standard deviation of approx 85ps in the single shot mode can be achieved 8 2 2 Measuring with highest possible Accuracy For getting the highest possible measurement accuracy the following proceeding is recommended Measurement mode 1 is used for time measurements The calibration measurements are executed separately in regular intervals via measurement mode 2 In order to achieve high quality calibration values averaged calibration values are used exec
28. ate calibration I CALI CAL2 measurement VALI VAL2 CALI CAL2 PRE Table 5 1 Measurement Modes Notes 1 After power on reset the TDC is in measurement mode 0 2 In the measurement mode 1 separate calibration measurements have to be executed via measurement mode 2 3 In measurement mode 2 the channel switches to the default mode measurement mode 0 after completion the gen eration of the calibration values Since measurement mode 2 co operates with measurement mode 1 you have to re new mode 1 via software 4 The precounter value PRE is stored in a separate register 5 The readout of the results in measurement mode 3 has to be performed En Bloc This means that no readout should take place until the stop value VAL2 is stored in the Result FIFO even though the VALID signal is set to 1 indicating that the start value VALI is present in the Result FIFO Reason When reading out VALI too early the Result FIFO runs empty and causes the read instruction to be cancelled When the read instruction is renewed for reading out the remaining measurement results the precounter value is lost and can t be read out TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 16 of 47 6 Functional Description 6 1 On Chip Oscillator For the generation of the calibration clock the TDC provides a so called on chip oscillator As re presented in Figure 6 1 the T
29. commended Operating Conditions esssseseeeeeeeeneee nennen 4 8 1 2 Absolut Maximum AUT S sisisi etine erias iise 41 8 2 ACCURACY OF MEASUREMENT sseesseseesseseersttsstteeettesrtsrtestessesttestessttetestensetetesteeseesteseeeset 42 8 2 1 Measurements in Measurement Mode 0 Default Mode eese 42 8 2 2 Measuring with highest possible Accuracy aiios visti pe ki Me ur ERAS PEE NS eH REYERRU pu EE ERES IN 42 8 3 MEASUREMENTS WITH RESOLUTION LOCK esee nennen ennemi 42 8 3 1 Example of Activating the Resolution Lock Unit eee 43 5 4 DEAD TIMES ce cae et otis ee cecal Ed cp led ana ce dacs a uda ODD DURAN D tad 43 8 5 BEHAVIOR OP THE TDC AT S Y SERRE dicsccssdcuigetncctagnataringstacsncdasceangeulenedtacvedentagendcuadoesecdgeees 44 8 6 POWEBSDN CHARACTERISTICS i cesset db dotes pectet Duae o pue deas YER a eere ae b ieies 44 8 7 APPLICATION NOTES e bt il eM TEs aE EEES ESAn END aa iadaaa 45 8 7 1 Standard Wiring of the TDCTOOQ Q iiiiesi s eerte rrt tata rnit eara enhn eae rta een 45 8 7 2 Wiring for Measurement MOOD uude etd rident exierit Her items ie rr es 46 8 7 3 Wiring for Measurement Mode 1 nerd eret et REIP eter RA Ces te e em M ra pIR RR EO duN 47 TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 4 of 47 1 Introduction MSC Vertriebs GmbH has many years of expe
30. d the next rising edge of the calibration clock is measured using the measuring core once more The measured time tyar is calculated using the clock period time tcar of the divided calibration clock and the TDC s measurement results VAL1 VAL2 PRE CALI and CAL2 in accordance with the TDC characteristic see Figure 5 2 as follows _ VAL1 VAL2 3 tva CAL2 CAL1 PRE to TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 14 of 47 5 5 Measurement Modes Figure 5 1 shows the general measurement cycle including the ALU processing for both measure ment ranges A time measurement is completed by the occurrence of a start signal followed by a stop signal De pending on the measurement mode a calibration measurement follows automatically It s also pos sible to execute a calibration measurement separately without a prior time measurement time measurement calibration measurement Meas range I VAL MO ALU CAL1 MO ALU CAL2 MO ALU F time measurement pee calibration measurement Meas range II START JS C RN taeaa e VAL Generation of measurement value VAL in measurement range I VALI VAL2 Generation of measurement values VALI and VAL2 in measurement range II PRE Generation of precounter value PRE in measurement range II M0 Generation of TDC characteristic quantit
31. danas mst tul euh tut tsi ean RUD ups 28 6 9 1 Daisy Chain Configuration Cycle and Chip Number Assignment 28 6 9 2 Daisy Chain Read Mode e eoe tes inei a ox tU ieu IR s tana plu SM I TREGUA E UIN ieu DUE 29 6 9 3 Processorless MORE dior opted tareas aun P a VER REQUE EEUU ra S EE EE E E 30 7 PROGRAMMING OF THE TDC10000Q e eere ee ee ee eene etes seen setas ena sensa seta setas tnase 31 7 1 BXECUTION OF INSTRUCTIONS 1ieeit sanske aE AEE AE IRENE EAE E 31 7 1 1 List of Instructions COOKIES orcs acis danas vecacuces Venestas nnwsnnncuutcnagaeaashaaivaastasaedaateqeuionaateancsavene 33 7 1 2 Description of th Ist CU ONS aduocatus epit rente sa estt p petis tus spes tue Pa ris ids irens ids 34 7 2 READ REGISTERS AND DATA FORMAT OF MEASUREMENT RESULTS eene 36 due WRITEREGISTERS see recesses cc Ota DENM Fen scene gus E ufta sfondi 37 Jl Mode Registers MOBDREGO L S icassteco eH be I pUD V mde ixi dace E e UM dde 37 Tae Global Register GLOBREGO reescrito ie direia a EEA ERE E Y pe Peau E 38 7 3 3 Global Register GLOBREG lv ssoserrveosssevrsrro iness seod orei Hd eE aas ar esasa 39 Tuae Offset Resister OBS B TO T sicccacccacosdscectoiecnanceueranpenicausesoia casapucengetane EEEIEE 39 Deed LOCKMOD Reviste ariens EE E DM E REE 40 7 3 0 LOCKREG Register PNE 40 AE uu DI b EE A T E E E E TA 41 8 1 ELECTRICAL SPECIFICATIONS 242 ielizaset ous nU E E AE TEER Us Dale a a ed 41 8 1 1 Re
32. e are written separately 2 write cycles in 16 bit mode writing an instruction takes only one cycle If an instruction is marked as global by setting the GLOBAL BIT Bit5 then it is accepted by all TDCs 16 bit Instruction local and global BITI5 BITI4 BITI3 BITI2 BITII BITIO BIT9 BIT8 X X X CHIP NUMBER 31 0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO X X t OPCODE 31 0 When global 16 bit instruction the chip number doesn t care because all TDCs accept the instruction 8 bit Instruction local and global 1 part 8 bit Instruction CHIP NUMBER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO X 1 0 CHIP NUMBER 31 0 2 part 8 bit Instruction OPCODE BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO X S OPCODE 31 0 When global 8 bit instruction the first part of the instruction chip number is not necessary because all chips accept the instruction Figure 7 1 Format of Instructions TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 32 of 47 There are instructions that are executed immediately after writing the instruction register e g RE SET see Chapter 7 1 1 and there are instructions that expect further actions for completion These actions can be write or read cycles If for example
33. ensee 10 5 2 GENERATING CALIBRATION VALUES sciigetessendececsceraczcadhetideisdedenteudecesascagceeacbadeceaciedaceasteends 11 5 3 MO MEASUREMEN T RR Tc e dinat 12 Det MEASUREMENT RANGES aiiis eet iod uides ticae Gic ua tatu Rees R qd biS sd 12 5 4 1 Measurement Procedure in Measurement Range I esee 12 5 4 2 Measurement Procedure in Measurement Range II eene 13 5 5 MEASUREMENT MODBS ise E bre Eet pos ER Ee etd SE EHE R UH asiasia nii nee RO arrian anait 14 6 FUNCTIONAL DESCRIP DION ssicssscsscssivcsrsssasssosssonscnacsuvassnsnsacssvcueiscnsstbasensssucasvnasbedeseeaxtoens 16 6 1 ON CHIPOSCGIEEATOR oot inuasit inches etia beo ui Mud M iuda t dude 16 6 2 CALIBRATION CLOCK DIVIDER a niic pe iet ese Gea toe nes iiiaae aeiae Sanksies 16 6 3 MEASUREMENT CHANNELS ERI SEE Ebr ei ABIRE en as idls eset e pU M EL ehani iiaia 17 6 3 du Teo 18 6 32 JOetrxesr LIU Loses otc onis a ores Codici ee eects 18 ES MEE Vio Alu e 19 et ME Pu antes 20 6 33 Mie aS UCI Core UP 20 6 3 0 sien NET EER S 20 6 4 ARITHMETICAL LOGIC UNIT CALI suiietbsecetd3estcu debi gucus tuERUM sath IM RR ER Mesa RE paa ieas 20 0 5 RESOLUTON LOCK UNIT iie ret Ete Ec Hii tend lbi d du amu E es a pee et eels 21 63 1 Principle Pyne ase Head xia oeceassactaaseegaieacsatenseuasacdeniattinead ue pha b adiui tni MI aes 21 pod Operating Seguente souci
34. escribed in Table 6 1 They are identical with the status flags of the Status Re gister and therefore can be read by software too Channel not ready measurements cannot be started because start input STARTO is disabled Channel is ready for measurement default and waits for a start signal If the retrigger unit is enabled the channel remains ready until a stop signal occurs Result FIFO of channel 0 is empty No measurement results for readout default Result FIFO of channel 0 has at least one valid measurement result VAL VAL1 VAL2 CALI CAL2 PRE for readout No overflow error default READYI VALIDI 0 Channel not ready measurements cannot be started because start input START1 is disabled Channel is ready for measurement default and waits for a start signal If the retrigger unit is enabled the channel remains ready until a stop signal occurs Result FIFO of channel 1 is empty No measurement results for readout default Result FIFO of channel 1 has at least one valid measurement result VAL VALI VAL2 CALI CAL2 PRE for readout Overflow of one or both channels If the retrigger unit is enabled the next retriggering start signal clears SYSERR to 0 At least one measurement is running at the moment TDC is calm No measurement is running at the moment default PRE is stored in a separate register Table 6 1 Description of the Status Flags TDC10000RefManE
35. h of one and two periods of the divided calibration clock tcati tcAr2 are measured and the resulting calibration values CALI and CAL2 are stored just like the measurement value VAL in the Result FIFO of the respective measurement channel The time values tcar and tcap2 2 tcAr are well known TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 12 of 47 5 3 M0 Measurement Measurement and calibration values of each channel are standardized in the ALU using the TDC specific internal characteristic quantity called MO MO is generated using the measuring core of the appropriate channel In order to minimize the influences of temperature and supply voltage and to optimize the precision of measurement a MO measurement has to be executed just like a calibration measurement in cy clic temporal distances 5 4 Measurement Ranges The TDC provides two measurement ranges individually programmable for each channel e Rangel uses the TDC core for short time measurement 4ns 6us e Range II uses the TDC core and the precounter for long time measurement 500ns 8ms typical at 5V 25 C Measurement range depends on period of calibration clock 5 4 1 Measurement Procedure in Measurement Range I In the measurement range I the measurement value VAL between the start and the stop signal of a time measurement is determined using the measuring core of
36. hannels can be disabled No stop signals will be passed to the measuring core e Polarity Start Polarity Stop The edge sensitivities of the start and stop inputs are adjusted independently from each other and separately for the two channels by software The input unit of each channel therefore triggers on rising or falling edges of the start and stop signals depending on the configuration Furthermore the input unit decides which signal start stop or calibration clock has to be passed on as a Start or stop signal to the measuring core depending on the measurement mode and on the partial step of the measurement cycle 6 3 2 Retrigger Unit If the retrigger unit is enabled the measurement is re started at the appearance of every start at the channel s start input as long as no stop has been detected at the channel s stop input As shown in Figure 6 4 the determined time difference is the time between the ast start signal and the stop sig nal If the Retrigger Unit isn t enabled then the time between the first start and the stop signal is measured I f O Leet OA UR STOP Ll tvar Without retrigger unt tvar With retrigger unit Figure 6 4 Measurement with and without Retrigger Unit Please note that a retriggering start signal should occur 30ns 5V typ after a previous start signal at the earliest The retrigger unit can be enabled by software
37. hown in Table 8 3 are maximum times The actual dead time of a measurement can be substantially shorter It varies as a function of the measured time difference measurement and MO generation 1 fold minimum 1200ns measurement and MO generation 16 fold minimum 5000ns Table 8 3 Dead Times typical at 5V 25 C TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 44 of 47 8 5 Behavior of the TDC at SYSERR If the maximum measurement period of a measurement range is exceeded or the stop signal is missing completely the measurement channel overflows The channel is disabled the flag SYSERR is set to 1 and all further start or stop signals are ignored Resetting the channel clears this error condition and SYSERR is set to 0 If the retrigger unit is en abled also the next retriggering start signal clears SYSERR to 0 and the measurement is restarted If an overflow has occurred and SYSERR is set to 1 then the Status Register may report that only the flag SYSERR is set and no valid measurement results are ready for readout although this is not correct There is a simple way to find out the truth Step 1 Software Resets on both channels Opcode 1 and 2 So the SYSERR is cleared if it was caused by a channel s overflow The measurement results stored in the Result FIFOs are not deleted by this Software Resets Step 2 Read out the Sta
38. internal ALU calcu lates the measurement value VAL which is stored in the Result FIFO of the appropriate channel TDC 10000 VAL Figure 5 1 Time Difference Measurement The measurement value VAL is dependent on the temperature and the supply voltage It therefore has to be weighted according to the TDC characteristic measurement straight Figure 5 2 Offset and grade of the characteristic have to be determined by a so called calibration measurement This can be executed immediately after every time measurement TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 11 of 47 Measurement result Call value measurement value Cal2 value CAL2 es y uem VAL P E CAL1 400 ee sa qu pe deem a OFFSET t gt t tcari tvaL tcar2 Figure 5 2 Characteristic of the TDC Core 5 2 Generating Calibration Values Only one calibration clock CALCLK has to be provided for calibration measurements of both chan nels This clock is the absolute time reference and therefore must have the precision of a quartz crystal The calibration clock is divided by an internal calibration clock divider The resulting clock CALCLKI is used as internal reference clock and measured by both measuring cores CALI CAL2 CALCLKI tcaL1 tcAL2 l Figure 5 3 Calibration Measurement During the calibration measurement the lengt
39. ix Ei e tdl qp a GND i W4 1d12 phase x z W dl3 amp enosz W di4 Ve Og gt L di5 GND __ busdir sinkO x amp ust csinkO Li stO o g GND Lo 5 A a sta 233263 359 88 Be d i a 33 1 PEST 3 SETS I 8 X 8 8 8 gt 7805 DL le ue in g E H H H E amp x o Fu Figure 8 2 Standard Wiring of the TDC10000 TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 46 of 47 8 7 2 Wiring for Measurement Mode 0 SHANTA coccoccc lt oocoococo S ERREEE FII IET Dist weve TDC10000 5 Start 0 STARTO uPD783xx 0 Stop 0 STOPO SPEED ENAO RLOCKON STOINHO D lt 8 15 gt Start 1 STARTI BIT816 Stop 1 STOP1 ENA1 BUSDIR STOINH1 WR INHMD RD TOKINO TOKINI TOKOUTO TOKOUTI WAIT ED External vl p DarLos pem Clock Figure 8 3 TDC10000 Single Chip with uPD783xx Notes 16 bit data bus for uPD78366 External calibration clock for the TDC10000 The resolution lock unit cannot be used because there is no external PLL wiring A All unused outputs should be left unconnected TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 47 of 47 8 7 3 Wiring for Measurement Mode 1 Vec Start 0
40. led any measurements on both channels are suppressed during running ALU calculations as well since both measurement channels are disabled during this time TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 21 of 47 6 5 Resolution Lock Unit The TDC10000 provides a resolution lock unit This unit allows the TDC s resolution to be kept almost constant approx 0 003 K by using a closed loop control of the supply voltage If the resolution lock unit is activated the calibration values once generated can be used further on Cali bration measurements are no longer required if large variations in temperature do not occur 6 5 1 Principle Function In order to keep the temperature and voltage dependent resolution of the TDC constant one needs a run time sensor on the chip which recognizes and compensates for any fluctuations For this pur pose a ring oscillator is used Its frequency is temperature and voltage dependent in the same man ner as the resolution of the measuring cores The ring oscillator is used as the VCO of a PLL and the generated clock is compared with a quartz exact clock supplied externally via pin CLKR So the clock of the ring oscillator and the resolution of the TDC are kept constant by a controlled vari able for the supply voltage derived from the PLL 6 5 2 Operating Sequence Figure 6 6 shows the TDC internal part of the PLL The res
41. ls two independent channels Resolution 5V typ Measurement ranges SV typ Measurement modes Calibration clock Calibration measurement Voltage range Temperature range Processor interface Internal memory Configuration Measurement improvement Resolution stabilisation Package each with one Start and one Stop input programmable edge sensitivity of the inputs retriggerable Start inputs 60ps range I short time measurement 4ns 6us range II long time measurement 500ns 8ms 4 external oscillator clock 500 kHz 10 MHz internal programmable clock divider automatically after time measurement or stand alone 2 7V 5 5V 40 C 85 C 8 16 bit selectable status flags for interrupt generation daisy chain for cascading of up to 31 TDCs FIFO for up to 4 measurement values per channel software and hardware configurable Auto Noise Unit Resolution Lock Unit PQFP80 with 0 8 mm pitch Measurement range depends on period of calibration clock TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 6 of 47 3 Block Diagram ENAO STOINHO SPEED NOPROC oic channel 0 SYSERR STOPO CALM READYO READYI ERE VALIDO VALIDI CALCLK on chip clock ENOSZ oscillator divider BUSDIR D 15 0 STARTI channel 1 RD STOPI d TDC registers CS PURES BUS816 resoluta daisychain TOKIN 1 0 lock unit
42. n Lock Unit In the following the operating sequence of activating the resolution lock unit is shown in an exam ple Global instructions are used The GLOBAL BIT is set see Chapter 7 1 Execution of Instructions In addition the internal multiplication factor is used as well as a 4 MHz reference clock 1 Write LOCKMOD Register of the resolution lock unit WRITE_TDC 51 global write decimal of register LOCKMOD 32 19 WRITE TDC 0 value that is stored in the register LOCKMOD 2 Prepare Track Mode TH pin 14 to 0 WRITE TDC 61 switch to Track Mode by software for safety s sake 32 29 3 Enable resolution lock unit in the register GLOBREGO enable Track Mode WRITE TDC 37 opcode for writing to GLOBREGO 32 5 WRITE TDC 128 set bit 7 to 1 all other bits to 0 4 Switch to Hold Mode Wait for a short time e g 1 second and then switch TH pin 14 to 1 Now the control loop is closed The pin PHASE pin 7 indicates whether the PLL has locked or not Here a clock with a pulse mark ratio of approx 1 1 should be generated Cooling down the chip the 1 phase of the clock should be reduced visibly Important Note If the suggested analog external circuit with the LM7805 is used see Figure 6 7 it is not recom mended to use the software instruction to switch to the Hold Mode since the circuit will lock then hardly never 8 4 Dead Times The values s
43. n a E E O a RO 21 6 5 3 Resolution Lock Unit Registers ssseeseseseseseeesseeesstssrrsseresetesstetsstesseessreeseeesssressrest 23 Ok LOCRKMOD REG IGE sisenes 23 po LOCKREG Re ait Sese eo n E E 23 6 5 4 External Analog Circuit TH 23 6 3 5 Power Consumption usus oc pea opia ie EVEN REORUM VER IUE ES EYED D EEE E EEE Eaa 23 6 6 TDC REGISTERS e 24 6 6 1 DisttucHon BOPISIBE essere herd pomme pod do ane E dM NIRE E d 24 60 2 Mod Registers eost ted e MR IE BRUN Gi ta ru ander rite nea 24 6 0 5 Global Registers iioii a oet bn Hv Pri reus ba vuv ie NUR uae ra Rene eu D ut a RE UR RES RETE 24 6 64 Offset RES ISUCES NEUE MM 24 6 0 3 Status SU oue pope NUN ui SM vos UU Mu Drs Mem DE epu M EE 24 AGGER c uir Pr MH 24 TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 3 of 47 6 7 PF OW POS Pe HR 29 6 8 PROCESSOR INTEBP ADE qaa diiaten tei deck intei Ir occ enia Qt eiu p tin tsi EE c ipie 25 6 8 1 Data and Control Lines iioi ipe Rete PEE irits tiesin esi AR ANNE NUS pU e Va EIN TR ERE d aeaiia 26 LI ONES UU C EE 26 68 12 Timing De AS opcodes Ip RID DP DIR a ME 26 6 8 2 Status Flad Suscipe MS DU eE Yd uU aa E eae ee dic PI MERE 27 09 DAISY CHAIN INTERFACE uenenum cebat eS Se
44. n accuracy when measuring in the measurement range I the divi sion factor should be selected in such a way that the time difference tyar to be measured is in the range of two calibration clock periods To achieve best measurement results in the measurement range II the period of the divided calibra tion clock should be as long as possible 6 3 Measurement Channels Figure 6 3 shows the block diagram of the measurement channels Channel Disable Polarity Start Enable Stop Polarity Stop Retrigger Enable START Start on measuring TOP Auto Noise Delay Line STO retrigger Enable Enable core unit Stop zB auto noise CALCLKI unit precounter gt PRE raw values MO Figure 6 3 Measurement Channel Block Diagram TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 18 of 47 6 3 1 Input Unit The input unit handles the incoming start stop and calibration clock signals using the following control signals e Channel Enable The measurement channels are enabled disabled using the pins ENAO and ENA If a channel is disabled no start stop or calibration clock signals will reach the measuring core and no meas urement will take place If the measurement channels are enabled by ENAO and ENAI they can also be enabled disabled by software e Inhibit Stop With the pins STOINHO and STOINHI the stop inputs STOPO and STOPI of the c
45. n the register GLOBREGI When all available data is read the token is passed on to the next chip This sequence is continued until the token drops out of the last chip in the chain This event can be used to signal the completion of the daisy read sequence The daisy chain read mode is turned off by the global instruction DAIRDOFF and the token has either to be removed from the pin or reset by the local instruction RESTOKEN If a large number of consecutive chips in the daisy chain doesn t contain valid data then the time between the readout of two chips having valid measurement results may be longer than the time between two read strobes of a fast processor If so the WAIT outputs of the TDCs can be used All WAIT pins are driven by open drain buffers and have to be connected to a shared pull up resistor This WAIT line can be connected to the WAIT input of a processor When the daisy chain read mode is turned off then the WAIT line is drawn to 0 When the daisy chain read mode is turned on then the WAIT outputs of all chips are HiZ and the pull up resistor pulls the WAIT line to 1 as long as the token is not retained by a chip This means that during the time when the token is passed on and no valid data is available the processor is kept in the Wait State until the token has come to a chip with valid data for readout As mentioned before the last chip has to operate in a special mode drawing the WAIT line to 0 when the token drops
46. n this part is read out later once again Available only in 16 bit mode TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 36 of 47 7 2 Read Registers and Data Format of Measurement Results Readout data on 8 bit data bus Data bits gt 7 6 5 4 3 2 1 0 GLOBREGI SDRSW LASTCHIP_ TKSEL CHIP NUMBER 0 31 GLOBREGO SLOCK CALDIV CALDIVO INHM DELAY SPEED 16 M AUTO_MO MODREGO NOISE MESSMODED MODREGI NOISE MESSMODEO STATUSREG Lo lam vamp lvanpo lezapy lepro lovam MULTIPLICATION FACTOR OF RESOLUTION LOCK UNIT BITS lt 7 0 gt A FRACTIONAL PORTION BITS lt 13 6 gt UPPER BITS 2 VALUE INTEGER PORTION BITS 7 0 LOWER BITS FRACTIONAL PORTION BITS 5 1 LOWER BITS CHANN PRECOUNTER BITS lt 7 0 gt LOWER BITS io o o o PRECOUNTER BITS 11 8 UPPER BITS MO BITS 7 0 LOWER BITS cuo 3e ooa MO BITS 12 8 UPPER BITS Readout data on 16 bit data bus Daten Bis 15 14 13 12 11 109 8 7 6 5 4 3 GLOBREGI SAME AS GLOBREGO WITH 8 BIT SAME AS MODREGO WITH 8 BIT SAME AS STATUSREG WITH 8 BIT SAME AS STATUSREG WITH 8 BIT FRACTIONAL PORTION BITS 13 0 INTEGER PORTION BITS 9 0 ofo PRECOUNTER BITS lt 11 0 gt o Mo BITS lt 12 0 gt SDRSW cui numsero 31 Kio kookimkom o 0 o o 0 Note Measurement value or calibration value Data format measurement values calibration values INTEGER FRACTION 98 7
47. ngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 28 of 47 6 9 Daisy Chain Interface The TDC provides a daisy chain interface for cascading of up to 31 TDC10000 in a chain So it s possible to get very fast and efficiently access to the measurement results of all chips TokeninO Tokenoutd Tokenout ae AA E gt gt gt gt Daisy Daisy Daisy eee Daisy Tokenin 5 Control gt gt Control 3 Control gt Control Tolerout y gt 5V TDC 10000 TDC10000 TDC10000 TDC10000 Tokenout1 m Wait e eo gt Figure 6 10 Daisy Chain Interface The TDC10000 can be chained as represented in Figure 6 10 using the tokenin and tokenout pins Since each TDC has two tokenin pins and two tokenout pins the chips can be cross connected in such a way that tokenoutO leads to the next chip and tokenoutl leads to the chip after next With the possibility to select the output the token is passed on chips which are not to be read out can be masked 6 9 1 Daisy Chain Configuration Cycle and Chip Number Assignment After power on reset all chips have the default chip number 31 At the beginning of the daisy chain configuration cycle the global instruction WRDAISY is sent to all chips
48. ngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 25 of 47 6 7 Result FIFOs Both measurement channels have a Result FIFO for up to 4 measurement results measurement and or calibration values calculated by the ALU and stored for readout via the processor interface When a FIFO is full the corresponding channel is disabled until at least one measurement result is read out When a FIFO is empty the read instruction for the corresponding channel is ignored 6 8 Processor Interface For the communication with a microprocessor the TDC provides a processor interface shown in Figure 6 8 READYO VALIDO Result FIFOs READY VALIDI CALM SYSERR FIFO channel 0 io boy de BUSDIR FIFO channel 1 D 15 0 processor interface TDC registers WR K BUS816 Instruction Register Status Register Figure 6 8 Block Diagram Processor Interface Via the processor interface the access to all TDC registers Instruction Register Mode Registers Global Registers Status Register Offset Registers and MO Registers is performed as well as the access to the registers of the resolution lock unit and the Result FIFOs of both channels In addition to data and control lines the processor interface provides six status flags for interrupt generation at the connected processor TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC1
49. nternal ringoscillator clock Bit 7 should be set to 0 when initialising the register 7 3 6 LOCKREG Register If the resolution lock unit is to be operated using an external multiplication factor then this factor has to be written into the register LOCKREG as 8 bit UNSIGNED INTEGER value before switch ing to the external factor TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 41 of 47 8 Appendix 8 1 Electrical Specifications 8 1 1 Recommended Operating Conditions Beyond these ranges a stable operation of the TDC10000 cannot be guaranteed Parameter _ Symbol Conditions min max Unit Supply Voltage WDD 27 55 V InpuSignaVolage Vi 0 VDD V Ambient Temperature trnns eee Input Voltage High TTL VIH 45VsVDD lt 55V 22 VDD V Input Voltage Low TIL VIL 45VsVDDssSV 0 08 v Input Rise Fall Time wt o 20 m Table 8 1 Recommended Operating Conditions 8 1 2 Absolute Maximum Ratings Operating the chip beyond these values could destroy the device immediately Symbol Supply Voltage VDD 05 465 1O Voltage Vivo 05 VDD 40 5 IOL min 9 0 mA Operating Temperature Topt 40 85 Storage Temperature Tstg 65 150 Table 8 2 Absolute maximum Ratings TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcf
50. o measurement is running at the moment mo quee um Chamel o ready Tor measurement o O 1 channel 0 ready for measurement 1 channel 1 ready for measurement 1 overflow error channel independent 1 channel 0 has valid measurement results for readout 0 channel 1 has no valid measurement results for readout In 1 channel 1 has valid measurement results for readout PURES In Power on reset high active 78 ENAO In Enable channel 0 0 channel 0 disabled cannot be enabled by software 1 channel 0 enabled can be disabled enabled by software Remarks e Connect all unused inputs to GND e Data bus DATA 15 0 is not allowed to float please pull up or down with e g 10kQ e Donot connect unused outputs e All inputs are TTL Table 4 1 Pin Description TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 10 of 47 5 Measuring Procedure The TDC10000 provides two identical measurement channels each with a typical resolution of 60ps at 5V and 25 C The figures of the user manual always refer to channel 0 however they apply equally well to channel 1 5 1 Time Difference Measurement As shown in Figure 5 1 per channel one edge sensitive start and one edge sensitive stop input are used for measuring the time difference tvar The time measurement in the measuring core of the respective channel is started by a start signal and ended by a stop signal The
51. olution lock unit has two functional modes Track and Hold These modes are selected by pin TH or by software Activating the resolution lock unit is done either by software within the register GLOBREGO or by setting pin RLOCKON to 1 Track Mode This mode is used for the adjustment of the PLL in the Hold Mode The period of the reference clock CLKR divided by four is counted out by the ring oscillator clock The determined multipli cation factor of the ring oscillator clock to the reference clock is stored in the Latch 8 with about 8 bits of precision Latch 8 is updated each period of the reference clock 4 When the temperature is rising on the chip the multiplication factor will decrease when the temperature is falling the factor will rise During Track Mode the resolution lock function is not activated A rectangle waveform with a pulse mark ratio of 1 1 is generated at the phase discriminator output pin PHASE Its frequency is 1 8 of the reference clock For thermal stabilisation of the chip it makes sense to activate this mode approx 5 minutes before changing to the Hold Mode Hold Mode In this mode the PLL is active The value stored in the Latch 8 is used as multiplication factor for the ring oscillator clock The clock is multiplied by this factor and compared with the reference clock 4 within the phase discriminator The result forms the phase discriminator output signal It s a rectangle with variable pulse mark ratio
52. rience in the development of high precision Time to Digital Converters TDCs MSC s first TDC was developed in 1990 and implemented in a cost effective Gate Array technology Similar to the terms ADC DAC etc MSC established the term TDC Time to digital Converter This manual describes the TDC10000 which is implemented in a 0 8um CMOS process tech nology featuring 2 7V 5V operation The chip is delivered in a QFP80 0 8mm fine pitch package Supplied with 5V the TDC10000 achieves a typical resolution of 60ps This resolution cannot be achieved using conventional time measurement components The multi channel function of the TDC10000 allows simultaneous measurement of time differences on two independent measurement channels The integrated measurement principle together with the technology used allows high precision time difference measurement at low power consumption The integration of the TDC10000 in bat tery powered applications has become to a common procedure The TDC10000 is perfectly suited for measurement of time differences Applications like distance measurement using laser phase measurement ultrasonic positioning temperature measurement etc have been implemented successfully with our TDCs many times Please contact us We are keen on satisfying your wishes TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 5 of 47 2 Features Channe
53. ronmental conditions can be compensated for a whole series of measurements e For multi TDC applications it is possible to tune the resolution of several TDC10000 with a pre cision of up to 0 5 to each other TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 23 of 47 6 5 3 Resolution Lock Unit Registers The resolution lock unit has two registers for configuration 6 5 3 1 LOCKMOD Register In this register the usage of the internal or external multiplication factor is selected and the resolu tion lock unit is adapted to the reference clock and to the external loop filter The width of this reg ister is 8 bit For detailed information on the individual register bits refer to Chapter 7 3 5 LOCKMOD Register 6 5 3 2 LOCKREG Register When using an external multiplication factor instead of the internal value of Latch 8 this factor has to be written into the LOCKREG Register The width of the register is 8 bit see also Chapter 7 3 6 LOCKREG Register 6 5 4 External Analog Circuit The PLL consists of internal and external components The loop filter and the closed loop voltage control of the TDC10000 have to be realised with external components Figure 6 7 shows a possible external analog circuit designed for 12V supply voltage 220 uF 220 uF 3 3k 10uF 47
54. s bit is cleared automatically During the separate MO measurement the channel is not ready for measurement Bit3 RETRIGGER UNIT RETRIGGER 0 off default 1 on Bit4 EDGE SENSITIVITY START START INV 0 Start input triggers on rising edge default Start input triggers on falling edge Bit5 EDGE SENSITIVITY STOP STOP INV 0 Stop input triggers on rising edge default 1 Stop input triggers on falling edge Bit6 DISABLE KANAL DIS CHAN 0 Measurement channel enabled if pin ENAO 1 resp ENAI 1 default 1 Measurement channel disabled er Bit7 AUTO NOISE UNIT NOISE 0 off default on Before changing the edge sensitivity the respective channel has to be disabled via software or pin Bitrelevant only for measurement modes 0 and 1 Have to be set to 0 for modes 2 and 3 Bitrelevant only for measurement modes 0 and 3 Have to be set to 0 for modes 1 and 2 TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 38 of 47 7 3 2 Global Register GLOBREGO GLOBREGO is for configurations concerning both channels Bit0 AUTOMATIC MO MEASUREMENT AUTO M0 0 on if pin INHMD 1 default 1 off Bit1 MO ACCURACY 16 M0 0 MO generation with 1 fold accuracy default 1 MO generation with 16 fold accuracy Bit2 ALU SPEED SPEED 0 fast if pin SPEED 0 default 1 slow Bit3 DE
55. s raw values to the ALU for further processing In addition depending on the TDC s configuration the core generates the TDC specific characteris tic quantity MO for each raw value MO is stored in the MO Register of the respective channel for further processing by the ALU It can be selected by software whether the measuring core generates MO with 1 fold or with 16 fold accuracy The generation of MO with 16 fold accuracy takes 16 times longer than the generation of MO with 1 fold accuracy Higher accuracy of MO thus causes a greater dead time of the measure ment 6 3 6 Precounter Within the measurement range II the precounter of each measurement channel counts the clock pe riods tcar of the divided calibration clock CALCLKI between the start signal and the stop signal of the time measurement The precounter value PRE is 12 bit This results in a maximum measurement period of tea 2 in the measurement range II 6 4 Arithmetical Logic Unit ALU The ALU is a flash based ALU It calculates the measurement and calibration values of both chan nels using the raw values of a measurement and the associated characteristic quantity MO The re sults are stored in the Result FIFO of the respective channel In order to exclude an influence on measurements by ALU calculations taking place at the same time in the measurement range I a suppression of ALU calculations can be enabled during running measurements by software If suppression is enab
56. the respective channel measurement VAL START STOP tvaL Figure 5 4 Measurement in Measurement Range I i The measured time tyar is calculated using the clock period time tcr of the divided calibration clock and the TDC s measurement results VAL CAL1 and CAL2 in accordance with the TDC characteristic see Figure 5 2 as follows TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 13 of 47 VAL Offset 1 t t D NAL CAL2 CALI A 2 Offset 2 CALI CAL2 5 4 2 Measurement Procedure in Measurement Range II In the measurement range II a time measurement is divided into three partial measurements in ac cordance with Figure 5 5 1 part of 2 part of measuring 3 part of measuring measuring VALI CALCLKI Precounter 0 0 1 PRE 1 PRE value START STOP Figure 5 5 Measurement in Measurement Range II In the first part of measurement the value VAL representing the time between the start signal and the next rising edge of the divided calibration clock is measured using the measuring core of the respective channel In the second part of measurement the integral number PRE of calibration clock periods between the start and the stop signal is determined by the so called precounter of the channel In the third part of measurement the measurement value VAL 2 which represents the time between the stop signal an
57. tus Register once again to find out if there are valid measurement results for readout Step 3 If so read out the results of the appropriate channel s 8 6 Power On Characteristics The minimum pulse width of a high active power on reset pulse connected to pin PURES is 100us Figure 8 1 shows a possible reset circuit RC circuit VDD TDC o C 100nF PURES VSS Figure 8 1 Reset Circuit After a power on reset the TDC is in the default state Both channels are ready for measurement if they are not disabled by pin Both channels are in measurement mode 0 the default mode TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 45 of 47 8 7 Application Notes 8 7 1 Standard Wiring of the TDC10000 zum Prozessor not connected LL zum Prozessor wait S speed 3 cc D Ms Vee 248 o g pE O 8 ge 52802759253 9 E E E c 5 0 stol GND q stal NT do csinkl a tal X GND a Vee og gt _ stoinh W e stoinh0 inhmd o8 mau gt amp rlockon z GND E q 5 lt lt g o Vee elkr __ 8 gt GND th g amp 1 Voc Q 4 go 3 4 GND z amp GND a 4 GND LU tag LE Vece e 9 v 98 g 3 calclk q W dio L 327 E r OSZ n
58. uting multiple calibration measurements within a calibration cycle Averaging factors of 16 up to 32 have proved well in practice In nearly all cases one calibration cycle per second is sufficient In this measurement mode measurements with a standard deviation of approx 60ps in the single shot mode can be achieved 8 3 Measurements with Resolution Lock If the measurement task does not allow the execution of regular calibration measurements it is pos sible to operate the chip in the resolution lock mode In this case it is most favourable to generate very exact calibration values by executing multiple calibration measurements while the chip oper ates in the resolution lock mode Calibration values once generated can be used further on and cali bration measurements are needed no longer Please note that in spite of using resolution lock the resolution can t kept constant infinitely Huge variations in temperature and long measurement times may cause deviations of up to several LSBs A 50K change in temperature will cause an error of approx 0 15 0 003 K for instance That results in an error of 1 5 ns us measurement time Operating in the resolution lock mode measurements with a standard deviation of approx 60ps in the single shot mode can be achieved TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 43 of 47 8 3 1 Example of Activating the Resolutio
59. y MO CALI Generation of calibration value CAL1 CAL2 Generation of calibration value CAL2 ALU ALU processing taeaa dead time of measurement Figure 5 1 General Measurement Cycle Normally after generating a measurement or calibration value a new MO is generated too This automatic MO measurement can be disabled by software If doing so separate MO measurements have to be performed via software similar to separate calibration measurements As shown in Figure 5 1 the TDC has got a so called dead time taeaa after the arrival of the time measurement s stop signal During this dead time all start and stop signals are ignored due to the measurement principle of the TDC10000 Depending on the configuration and the measurement mode selected this time differs within a wide range After dead time the channel is ready again for measurement at the earliest and accepts start and stop signals for a new measurement The maxi mun dead times expected are shown in Chapter 8 4 Dead Times TDC10000RefManEngV23 doc Version 2 3 Author UW AP tdcfamsc ge com WWW msc ge com MSC User Manual MSC TDC10000 Page 15 of 47 In Table 6 1 all measurement modes of the TDC10000 are shown They are selectable for each channel independently by software Measurement mode Measurement Calibration Sequence of the measurement range measurement results stored in the Result FIFO 0 Default Mode VAL CALI CAL2 1 High Speed Mode 2 Separ
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