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USER`S MANUAL

1. e EED m PL OG sol E A m mo CE i pul bue bua pus sei fom 8 een ont B B kees Lug DIE Jte ak el m x in m dii i 3 2 5 5 bel EN a JE l S Li EEE CESE ad 3 ka Ah AB T v T TUT Im K s Tren EUNT 4 EL zr Faire O e SCH L do o E is dere U39 3 E jgE a j E HE rez B sl ER La SECH i 420 la i e SS Je Ka 1 E kan EER E O O Ong CH O Oo Es po PS o Fig 2 1 shows the jumper switch and connector locations on the XVME 689 VR7 Installation and Setup Jumper Settings The following table Lists XVME689 VR7 jumpers their default positions and their functions Table 2 1 XVME 689 VR7 Jumper Settings Jumper Position Funion XVME 689 VR7 cannot generate SYSFAIL H XVME 689 VR7 generates SYSFAIL normally Disables system resources no auto SYSCON y Enables system resources auto SYSCON y XVME 689 VR7 can reset VMEbus XVME 689 VR7 cannot reset VMEbus 4 Normal Clear CMOS y Boot from FLASH Boot from ROM Orb ground not connected to logic ground y Orb ground connected to logic ground ey Normal Video out Front Panel VGA Video re routed to P2 connector no video out front panel SIO_COM_RXD 4 RXD4 JP60 SIO_COM_RXD 4 RXD422 SIO_COM_RXD 4 RX
2. 1 9 connectors CPU fan power 2 17 keyboard port esses 2 6 PM titt IE EE ne 2 16 RJ 45 10 100 Base T 2 20 5 11 Univeral Serial Bus USB 2 9 5 8 Index NGA nut Meter rete deret AER en 2 8 5 12 K l node een 2 12 XVME 973 1 PERSE Ge SE oe 5 2 Pda EA EE 5 6 IN etes eet t tet 5 7 CPU fan power connector 2 17 drivers loading Ethernet 2 20 drives Compact Flash esses 1 4 Hoppy een 1 3 5 6 Hard eee 1 3 5 2 5 7 Ethernet driver loading 2 20 expansion PEO oia 1 5 PCI MR AE AE Ghee Aa tas 1 5 PEM Es otto Let Ee 1 5 MERE EE RA N 1 5 Short IS A deed 1 5 Expansion Options esse 1 10 Flash Paging and Byte Swap register 2 5 4 9 4 10 floppy ALIVE esse see se ee Sk Se ee 1 3 3 2 front panel merosiga i 2 19 hard drive und 1 3 hardware specifications sss 1 9 OS EE EK A 4 1 installation SDRAM dete rented eee 1 XVME 073 1 ecient ient 5 1 interrupt generation VMEbus 4 7 interrupt handling K 4 6 TRO MADE eterne ner 4 3 OIE Ree 4 6 jumper settings J3 mainboard 3 24 4 5 keyboard interface esse 1 5 keyboard port connector 2 6 LED BIOS register esse esse es see see se 2 4 Index memory MAP iese ee se nennen 4 1 memor
3. The following table describes the settings associated with the POST setup menu s Memory Test section 3 9 BIOS Setup Menus Low Memory Standard Test Enable basic memory confidence test of memory below 1MB address boundary conventional memory or memory normally used by DOS Low Memory Exhaustive Test Enable exhaustive memory confidence test of memory below 1MB address boundary High Memory Standard Test Enable basic memory confidence test of memory between IMB and 4 2GB address boundaries extended memory High Memory Exhaustive Test Enable exhaustive memory confidence test of memory between 1MB and 4 2GB address boundaries Huge Memory Standard Test Enable basic memory confidence test of memory above 4 2GB address boundary available using PAE technology Huge Memory Exhaustive Test Enable exhaustive memory confidence test of memory above 4 2GB address boundary Click During Memory Test Enable disable speaker click when testing each block Clear Memory During Test Enable storing O s in all memory locations tested Only necessary when some legacy DOS programs are run as they may rely on cleared memory to operate properly The following table describes the settings associated with the POST setup menu s Error Control section Pause on POST Errors Enable pause when errors are detected during POST so that the user can view the error message a
4. IDI IDI IDI IDI IDI IDI Type Mode Type Mode Type Mode Type 0 Master Configuration 1 44MB 3 5 E Drive Configuration E 0 Autoconfig Multi word DMA mode Autoconfig Multi word DMA mode Autoconfig Fastest support mode Autoconfig This is the order in which the BIOS will look for the Operating System Place the device to which you want to Boot at the top on the list The device Names are loaded by the BIOS as it finds the hardware Not Installed 360KB 5 25 1 2MB 5 25 720KB 3 5 1 44MB 3 5 and 2 88MB 3 5 AutoConfig AutoConfig Physical AutoConfig LBA AutoConfig Phoenix and Not Installed PIO Mode MULTI Word DMA Mode UDMA Mode 40 Conductor Cable UDMA Mode 80 Conductor Cable Fastest Supported Mode AutoConfig AutoConfig Physical AutoConfig LBA AutoConfig Phoenix and Not Installed PIO Mode MULTI Word DMA Mode UDMA Mode 40 Conductor Cable UDMA Mode 80 Conductor Cable Fastest Supported Mode AutoConfig AutoConfig Physical AutoConfig LBA AutoConfig Phoenix and Not Installed PIO Mode MULTI Word DMA Mode UDMA Mode 40 Conductor Cable UDMA Mode 80 Conductor Cable Fastest Supported Mode AutoConfig AutoConfig Physical AutoConfig LBA AutoConfig Phoenix and Not Installed 3 7 BIOS Setup Menus IDE 3 Mode Fastest support mode PIO Mode MULTI Word DMA Mode
5. Compact Flash y PCI Mezzanine Card Site PO IDE 6300ESB 82546GB HD CD VO Controller Hub 30 100 1000 BaseT Ethernet User VO SATAOP2 P2 I User VO amp Switches EIDE E EEN Kor AM Expansion PClbus FWH Universe IID Flash gt PCI to VME BIOS LPC Bus interface SCH3114 FPGA Super VO Byte Swapping VMEbus buffers PS2 Keyboard COM2 4 LPTt cones m ll Teater Front Panel Reset Abort Front Panel y Front Panel LEDs Switch Environmental Specifications Introduction The XVME 689 VR7 will meet the following environmental requirements Environmental Specification Operating Non Operating Thermal 40 to 85 C Humidity 10 to 90 RH 1096 to 9096 RH non non condensing condensing Shock 30 g peak 50 g peak acceleration msec duration Vibration 0 015 0 38mm 0 030 0 76mm peak to peak 5 9000 Hz peak to peak displacement 5 g maximum displacement 2 5g acceleration maximum acceleration Emissions EN 55022 EN 55022 Immunity EN 50082 2 EN 50082 2 1 7 Introduction Hardware Specifications Characteristic Specification Power Specifications 5 4 A typical 10 5 A maximum Voltage Specifications 5V 12V 12V all 5 2 5 CPU speed Intel Celeron M Low Power 1 8 GHz Processor Onboard memory SDRAM up to 2 GB one 200 pin SODIMM Integrated Graphics Controller 1600 x 1200 maximum resolution 24 bit color maximum 4 MB Shared memory Eth
6. If your application requires the external drives to be mounted in a location that requires a long cable run the SATA drives are better suited to that application SATA cable can be up to 1 meters or 39 long EIDE have be less than 18 long On Board Hard Drive Optional module XVME 913 The on board hard drive resides as a master on the secondary EIDE port The XVME 913 is a kit of parts including 1 8 hard drive cable 4 brackets screws and standoffs There are no unique drivers required The XVME 689 VR7 can be booted from the on board hard drive if configured in the BIOS Boot menu NOTE The XVME 689 VR7 module can accept either an on board 1 8 hard drive XVME 913 or the Compact Flash carrier XVME 912 but not both Compact Flash Site Optional module XVME 912 The compact flash socket on the optional carrier module will support type I or type II Compact Flash cards The compact flash resides as a master on the secondary IDE port There are no unique drivers required The XVME 689 VR7 can be booted from the compact flash drive if configured in the BIOS Boot menu NOTE The XVME 689 VR7 module can accept either an on board 1 8 hard drive XVME 913 or the Compact Flash carrier XVME 912 but not both VMEbus Interface The XVME 689 VR7 uses the PCI local bus to interface to the VMEbus via a PCI to VME bridge device Tundra Universe IID The VMEbus interface supports full DMA to and from the VMEbus integral FIFOs for posted writes
7. block mode transfers and read modify write operations The interface contains one master and eight slave images that can be programmed in a variety of modes to allow the VMEbus to be mapped into the XVME 689 VR7 local memory This makes it easy to configure VMEbus resources in protected and real mode programs The X VME 689 VR7 also incorporates onboard hardware byte swapping see Table 1 2 For a complete API the Xembedded Board Support Packages tailored to your operating system will allow quick programming of your application Introduction Serial and Parallel Ports XVME 689 VR7 includes four high speed 16550 compatible serial ports RS 232C with Com 4 capable of RS 232 and RS 422 485 configurations The Parallel port can be configured for ECP or EPP parallel port This is done in the SMC SCH3114 LPC Super I O and programmed via the BIOS Com ports 1 and 4 are RJ 45 s on the front panel and Com 2 and 3 are available out the P2 VMEbus The COM 4 port differ from front to back P2 the front COM port 4 CAN NOT be configured as a RS 232 422 485 but the rear P2 COM port 4 can be configured in this way Keyboard Mouse Interface A combined keyboard and mouse port PS 2 connector is provided on the front panel A PS 2 splitter cable part number 140232 provided with the module may be used to separate the two ports so that both devices may be simultaneously connected to the module IF a mouse is not required a keyboard can be connected directly to
8. 1 8259 equivalent note 3 040 05F Timer 8254 2 equivalent 060 06F 8742 equivalent keyboard 070 07F Real Time Clock bit 7 NMI mask note 3 080 091 DMA page register note 3 92 Fast GateA20 and Fast CPU Init 93 9F DMA page register note 3 OAO OBF Interrupt controller 2 8259 equivalent note 3 OGO ODF OFO OF 1 OF2 OFF 170 177 1F0 1F7 219 234 235 277 278 27F 280 2F7 2F8 2FF 300 36F 376 378 37F 380 3BF 3C0 3DF 3E0 3EF 3F0 3F5 3F6 3F8 3FF 400 47F 480 4BF 4DOh 4D1h CF8 CF9 CFC Rear Transition Module DMA controller 2 8237A 5 equivalent note 3 N A N A N A Secondary IDE Controller Generates CS1 Primary IDE Controller Generates CS1 Xembedded LED control register Byte Swap port Available Parallel Port 2 note 1 Available Serial Port 2 note 1 Available Secondary IDE Controller Generates CS3 Parallel Port 1 note 1 Available VGA EGA 2 note 2 Available Primary Floppy disk controller Primary IDE Controller Generates CS3 Serial port 1 note 1 Industry Pack IP VO Industry Pack IP ID ELCR1 Edge or level triggered ELCR2 Edge or level triggered PCI configuration address register note 4 Reset Control Register PCI configuration data register note 4 Note 1 The serial and parallel port addresses may be changed or the port may be disabled Therefore these address maybe used for some applications and not for others Note 2 Reference the Intel 855GME datasheet for detailed
9. ADVISED THAT THIS FEATURE COULD CAUSE DATA LOSS AT YOUR SOLE EXPENSE ACCORDINGLY IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND ALWAYS BACKUP YOUR DATA BEFORE PERFORMING DIAGNOSTICS ON ANY SYSTEM AS THEY COULD CAUSE DATA LOSS 3 23 BIOS Setup Menus 3 10 VMEbus Master System Controller Submenu The XVME 689 VR7 automatically provides slot 1 system resource functions The system resource functions are explained in the Universe manual Contact Tundra at www tundra com for a PDF version of the Universe manual This function can be disabled using XVME 689 VR7 jumper J3 Refer to Jumper Settings in Chapter 2 p 2 2 for more information System resources are VMEbus Arbiter BERR timeout SYSCLK and IACK daisy chain driver These resources must be provided by the module installed in the system controller slot left most slot The status of the XVME 689 VR7 system resources is reported in a read only field Note The BERR timeout is the VMEbus error timeout value System Configuration Utility Features Misc VME Master VME Slave FrontPanelConfig System Controller Master Resources is this board Syscon Enabled BERR Timeout 16 us Arbitration Mode Round Robin aster Interface Request Level Level 3 Request Mode Demand Slave cycle byte swapping Byte swap disabl Release Mode When Done aster cycle byte swapping Byte swap disabl Embedded BIOS 200
10. General Software Inc Figure 3 2 Slave Interface Submenu 3 26 BIOS Setup Menus Table 3 1 Slave Interface Submenu Option Description O Slave Interface Address Modifiers Address Space Base Address High Nibble Base Address Med Nibble Base Address Low Nibble Used to turn the slave interface boot state On or Off default When turned Off other VME masters cannot access memory on the XVME 689 VR7 Determines which type of VMEbus slave access is permitted to read or write to the XVME 689 VR7 dual access memory The first field determines whether the slave interface responds to Data access only default Program access only or Both The second field determines whether the slave interface responds to Supervisory access only Non Privileged access only default or Both Determines if VME masters access the slave s dual access memory in the VMEbus Standard A24 or VMEbus Extended A32 address space The default is VMEbus Extended Determines the amount of dual access memory that is available to external VMEbus masters The slave memory size cannot be more than the total memory size or greater than 16 MB for VMEbus Standard Address Space The choices are 1MB default 2MB 4MB 8MB 16MB and 32MB unavailable for VMEbus Standard Address Space These fields determine the base VMEbus address prefix for the first 12 bits of the address to which the VMEbus slave interface will respond The three fields are
11. PMC VO 1 GND N C PMC VO 18 PMC l O2 IDE PDDCSI1 N C PMC VO 19 PMC 1 0 3 IDE_PDDAO N C PMC VO 33 PMC I O 4 IDE_PDDA1 N C PMC VO 20 PMC VO 5 IDE_IRQ14 N C PMC VO 34 PMC l O 6 OO GO Inn IDE PIORDY N C PMC VO 21 PMC VO 7 IDE_PIORDR IDE_PDCS3 PMC I O 22 PMC I O 8 IDE_PIORDW IDE_PDA2 PMC VO 23 PMC VO 35 IDE_PDDO IOCS16 PMC VO 24 PMC VO 9 IDE PDD1 IDE PDD15 PMC VO 25 PMC VO 10 IDE PDD2 IDE PDD14 PMC l O 26 PMC VO 11 IDE PDD3 IDE PDD13 GND PMC VO 12 IDE PDD4 IDE PDD12 PMC VO 27 PMC VO 13 IDE PDD5 IDE PDD11 PMC VO 28 PMC VO 14 IDE PDD6 IDE PDD10 PMC l O 29 GND IDE PDD7 IDE PDD9 PMC VO 30 PMC VO 15 IDE PDRST IDE PDD8 PMC VO 31 PMC VO 16 2 14 Installation and Setup 80pin PCI connector P3 The P3 high speed micro strip connector has all the PCI signals along with 2 separate PCI clocks and the 2 request and grants predefined The CPU board and the Interface boards will be keyed for either 3 3V or 5V signaling The keying mechanism is based on standoffs At this point all CPU boards will be 5V PCI signaling The V IO pins on the connector are used to define the signaling level to the other PCI boards This connector is used to attach the XVME 976 209 dual PMC carrier The XVME 97
12. Paging and Byte Swap Register This register controls access to the Flash paging and byte swapping functions Table 2 6 Flash Paging and Byte Swap Register Settings Bt signal Deep O o Feas FlashaddessT5 pageconmlbi Do not use Unused set to 0 Do not use Unused set to 0 Do not use 6 SWAPS 1 No swapping data invariant occurs during slave cycles SWAPM 1 No swapping data invariant occurs during master cycles Front Panel Layout Ethernet port 1 and 2 men Greente ER SE Com 1 and Com 4 Keyboard a Mouse PS 2 me A SOO wer PMIC Site Indicator LEDs Panel LEDs and Switch Reset sys Switch controller Pass Fail LED LED The reset switch can be enabled to reset see the setup of Sw 1 shown in Figure 2 2 and table 2 2 This switch can be configured to either just reset the XVME 689 VR7 or to reset both the VMEbus and the XVME 689 VR7 The green pass and red fail LEDs are used as an indication of board health during the BIOS boot up Both the green pass and red fail LEDs will light during the POST of the board As the BIOS complete the POST the red fail LED will be turned off This is an indication the XVME 689 VR7 has passed the POST The Green SYS Controller LED is lit when the XVME 689 VR7 is configured as the VMEbus system controller This is the function that grants bus ownership to multiple bus VME masters and provides the 16MHz clock signal on the back plane 2 5 Installation and Setu
13. UDMA Mode 40 Conductor Cable UDMA Mode 80 Conductor Cable Fastest Supported Mode Embedded BIOSG 2000 V6 0 5 Copyright 2006 General Software Inc ENE EE GENE NEE In addition to the boot device list there are two more sections in the BOOT menu namely the Floppy Drive Configuration and IDE Drive Configuration sections Both of these sections tell the BIOS what kind of equipment is connected to the motherboard so that the BIOS can inspect the equipment For example the floppy drive section allows you to specify whether a floppy drive is a 54 360KB floppy a 5 2MB floppy a 3 7 720KB floppy or a 34 1 44MB floppy the first three are largely supplied for compatibility since these floppy drives are no longer available in stores Similarly the IDE Drive Configuration section describes the type of hard drive equipment that is connected to the motherboard including the cable type IDE drives or actually more properly Parallel ATA PATA drives are connected to the motherboard with a flat cable with either 40 or 80 wires running in parallel hence Parallel ATA as opposed to Serial ATA The 40 pin connector supports speeds up to UDMA 2 whereas 80 pin cables are needed for higher transfer rates to eliminate noise The BIOS can be told what type of cable is available so that it knows whether higher transfer rates are allowed or it can be told to autodetect the cable type in which case the drive and the motherboard
14. Universe chip the data must be passed straight through the byte swapping hardware To do this maintaining numeric consistency enable the straight through buffers by setting bits 6 and 7 of the Flash Paging and Byte Swap register register 234h to 1 see p 2 4 Note With the straight through buffers enabled the XVME 689 VR7 does not support unaligned transfers Sixteen bit or 32 bit transfers must have an even address 4 9 Rear Transition Module Address Consistency Address consistency or address coherency refers to communications between the XVME 689 VR7 and the VMEbus in which both architectures addresses are the same for each byte In other words the XVME 689 VR7 and the VMEbus memory images appear the same Address consistency is desirable for byte oriented data such as strings or video image data Consider the example of transferring the string Text to the VMEbus memory using a 32 bit transfer in Figure 4 4 Pentium Register 32 bit VMEbus Byte swapping Hardware Address M M 1 M 2 M 3 XVME 690 Figure 4 4 Maintaining Address Consistency Notice that the data byte at each address is identical To achieve this the data bytes need to be swapped as they are passed from the PCI bus to the VMEbus To maintain address consistency enable the byte swapping buffers by setting bits 6 and 7 of the Flash Paging and Byte Swap register register 234h to see p 2 4 4 10 0 Appendix A SDRAM and Battery Insta
15. VME64 VMEbus interface with programmable hardware byte swapping Architecture CPU Chip The Intel Celeron M processors have a new micro architecture but remain software compatible with previous members of the Intel microprocessor family The Celeron M has longer pipeline stages and thus does more per clock cycle which allows it to run at a lower clock frequency thus saving power The Celeron M has a large L2 cache 1MB on 160nm which boosts performance A Celeron M is comparable in performance to a Pentium 4 running at 5096 higher clock rate but dissipates less than half the power With a junction temperature range of 0 to 100C and a max power dissipation ranging from 10W to 24Watts the Celeron M is capable of withstanding a great deal of thermal stress while reducing the overall power dissipation for the product PCI Local Bus Interface The Intel 855GME 6300ESB chipset supports the Celeron M processors with up to 400MHz front side bus The XVME 689 VR7 incorporates one PCI X bus which is used to service the two Intel 82546EB Ethernet controllers and the on board PMC site The PMC site supports both 32 bit 33MHz and 64 bit 66MHz bus speeds with 5V I O support The XVME 689 VR7 supports on PCI bus for 32 bit 33MHz operation this bus services the PCI to VME bridge chip known as the tundra Universe II chip and the 80 pin expansion connector used to connect the XVME 976 209 Dual PMC carrier modules These carrier modules can be stacked to all
16. VR7 and first XVME 976 209 to five PMC card sites Watchdog Timer The XVME 689 VR7 has a long duration watchdog timer which can count from 1 to 255 seconds or from 1 to 255 minutes The BIOS supports various system events which can be routed to the watchdog timer The timer when enabled can generate either an interrupt or a master reset depending on how the watchdog timer is configured Note The timeout range is from 1 0 second to 2 25 seconds it will typically be 1 6 seconds Software Support The XVME 689 VR7 is fully PC compatible and will run off the shelf PC software but most packages will not be able to access the features of the VMEbus To solve this problem Xembedded has developed extensive Board Support Packages BSPs that simplify the integration of VMEbus data into PC software applications Xembedded s BSPs provide users with an efficient high level interface between their Introduction applications and the VMEbus to PCI bridge device Board Support Packages are available for MS DOS Windows NT Windows 2000 Windows XP Windows XP Embedded Linux VxWorks and QNX Operational Description Figure 1 1 XVME 689 VR7 Block Diagram Celeron M Care SS T oltage LT FLEX700 Regulator i IMVP IV 400 MHz FSB Front panel VGA Connector Video Analog VGA 855GME DDR 266 333 MHz DDR SDRAM MUX 200 pin SODIMM GMCH 256 512MB 1GB VGA P2 Hublink 1 5 1 8inch IDE PCI X bus Hard Drive PMC
17. information Note 3 Reference the Intel 6300ESB datasheet for detailed information Note 4 Reference The PCI local bus specification rev 2 3 6300ESB datasheet for PCI configuration information 4 2 Rear Transition Module IRQ Map Table 4 2 IRQ Map INTA Function IROO System Timer IRQ1 Keyboard IRQ2 Interrupt Cascade reserved IRO3 COM2 IRQ4 COM1 IRQ5 Ethernet 1 IRO5 PCI Expansion to PMC 2 IRQ6 Floppy IRQ7 Parallel Port LPT1 IRO8 Real Time Clock IRQ9 Universe IID IRQ9 PCI X Video IRQ10 Onboard PMC X IRQ11 PCI Expansion to PMC 1 IRQ11 Ethernet 2 IRQ12 Mouse IRQ13 Math Coprocessor reserved IRQ14 Primary IDE IRQ15 Secondary IDE The above interrupt mapping is one possible scenario The user or operating system may choose a different mapping for some of these interrupts based on what devices are actually in the system and require interrupts If COM2 or LPT1 are not used then these would free up IRQ3 and IRQ7 respectively 4 3 PCI Device Map Table 4 3 PCI device Map Rear Transition Module Device ID MFG CF8 DWORD R G INTA ABCD AD Line Devic 82546GB Ethernet1 1079 8086 Ethernet Controller Function 0 8000 8000 PCI X R G 0 PX_IRQ 0 AD 20 09H 82546GB Ethernet2 1079 8086 Ethernet Controller Function 1 8000 8000 PCI X R G 0 P
18. providing a simplified method of connecting up to two IDE devices and one external floppy drive The secondary IDE master signals support the optional on board hard drive or on board Compact Flash site and the secondary IDE slave signals are not supported The XVME 689 VR7 is NOT compatible with the XVME 977 and or the XVME 979 mass storage modules Introduction Caution The IDE controller supports enhanced PIO modes which reduce the cycle times for 16 bit data transfers to the hard drive Check with your drive manual to see if the drive you are using supports these modes The higher the PIO mode the shorter the cycle time As the IDE cable length increases this reduced cycle time can lead to erratic operation As a result it is in your best interest to keep the IDE cable as short as possible The PIO modes can be selected in the BIOS setup The Auto configuration will attempt to classify the connected drive if the drive supports the auto ID command If you experience problems change the Transfer Mode to Standard Caution The total cable length must not exceed 18 inches Also if two drives are connected they must be no more than six inches apart See SATA below for longer cable lengths Serial ATA Hard Drive The XVME 689 VR7 features two 2 SATA 150 drive interfaces out the rear P2 VMEbus connector The use of the optional rear transition module XVME 990 VR7 allows for the connection of two drives using standard SATA cables
19. site and Ethernet 31 1 or rear RJ 45 Ethernet XVME 990 VR7 2 Drive Adapter Module for external drives cables out back of VME backplane Primary PIDE 2 PIDE Floppy COM2 Only RS 232 two ports of SATA 150 LPT1 1 USB port Audio in out and Analog Video out XVME 976 209 PMC Carrier module with two PMC module sites The XVME 976 209 allows for stacking of a second XVME 976 209 this combination will accommodate a total of five PMC modules XVME 977 011 Not Compatible with the XVME 689 VR7 XVME 979 1 Not Compatible with the XVME 689 VR7 XVME 979 2 Not Compatible with the XVME 689 VR7 XVME 979 3 Not Compatible with the XVME 689 VR7 XVME 979 4 Not Compatible with the XVME 689 VR7 XVME 979 5 Not Compatible with the XVME 689 VR7 XVME 979 6 Not Compatible with the XVME 689 VR7 XVME 9000 EXF Not Compatible with the XVME 689 VR7 The XVME 990 VR7 is described in Error Reference source not found Installation and Setup Chapter 2 Installation and Setup Board Layout This chapter provides information on configuring the XVME 689 VR7 modules It also provides information on installing the XVME 689 VR7 into a backplane and enabling the Ethernet controller
20. the high H middle M and low L nibbles of these 12 bits The address is HMLOOOOOh In the default screen configuration H is A M is A and L is 4 so the address is AA400000h The values change depending on the Size and Address Space field values When the Address Space value is VMEbus Standard the dual access memory must be located on a 1 MB boundary and the upper two nibbles are ignored so the high and medium nibbles are changed to 0 and are made read only When the Address Space value is VMEbus Extended the slave address must be a multiple of the slave memory size When the Size is greater than 1 MB the low nibble is truncated to an even value Note The address that is set with these fields is the address that is used by the VMEbus processors The PC AT processor on the XVME 689 VR7 will see a translated address This translation and the amount of translation is calculated by the BIOS and is not user configurable in the BIOS setup See p 4 5 for a discussion of translation addresses 3 27 BIOS Setup Menus 3 12 Front Panel resources control Use this menu to select front panel or rear I O for the Video and the two Ethernet ports System Configuration Utility Features Misc VME Master VME Slave FrontPanelConfig Front Panel Config Video routed to front VGA Port or rear Overridded by JP8 on Video Routed to Front or Rear Board Default front LAN Port A Routed to Front or Rear Embedded BIOSG 2000 V6
21. 0 5 Copyright 2006 General Software Inc 3 28 Rear Transition Module Chapter 4 Programming Memory Map The preliminary memory map of the XVME 689 VR7 as seen by the CPU is shown below The I O designation refers to memory which is viewed as part of the AT bus or as part of VMEbus depending on how the Universe is programmed XVME 689 VR7 MEMORY MAP Table 4 1 Memory Map ADDRESS RANGE HEX SIZE DEVICE FFFCO0000 FFFFFFFF 256K SYSTEM BIOS end of DRAM FFFBFFFF OOK UO MEMORY 00100000 end of DRAM OOK DRAM 000F0000 000FFFFF 64K SYSTEM BIOS 000E0000 OOOEFFFF 64K SYSTEM BIOS 000D8000 000DFFFF 32K Universe Real Mode Window 000D0000 000D7FFF 32K Open memory block 000CC000 000CFFFF 16K Open memory block 000C0000 000C7FFF 32K VGA BIOS 000A0000 000BFFFF 128K VGA DRAM MEMORY 00000000 0009FFFF 640K DRAM See Intel 6300ESB data sheet for a description for optional settings for setting memory holes or gaps within Memory map area The PCI devices are located at the very top of memory just below the system BIOS VO Map This Preliminary VO map for the XVME 689 VR7 contains I O ports of the IBM AT architecture plus some additions for PCI VO registers and Xembedded specific VO registers Hex Range Device 000 01F DMA controller 1 8237A 5 equivalent 020 021 Interrupt controller 1 8259 equivalent 022 023 Available 025 02F Interrupt controller
22. 0 V6 0 5 Copyright 2006 General Software Inc Figure 3 10 System Controller VMEbus Master setup 3 24 BIOS Setup Menus Option Description This read only field displays the status Enabled or Disabled of the XVME 661 system resources This value is automatically detected This field is used to set the VMEbus error timeout Choices are 16us 32us 64us default 128us 256us 512us 1024us and Disabled Arbitration Mode This field is used to set the VMEbus arbitration mode Choices are Priority Single default or Round Robin Note These fields are only referenced if the board is the system controller If it is not the setup field values are ignored BERR Timeout is set to Disabled 0 and Arbitration Mode is set to Round Robin with an Arbitration timeout value of 0 Disabled 3 25 BIOS Setup Menus 3 11 VMEbus Slave Configuration The VMEbus slave setup allows configuration of the XVME processor board s VMEbus slave interfaces Note When the Slave 1 amp 2 Operational Mode setting is Compatible slave images 0 and 1 are reserved for BIOS use See p Error Bookmark not defined for more details System Configuration Utility Features Misc VME Master VME Slave FrontPanelConfig lave lt E lave VME salve enable and disable lave lave lave lave lave 0 0 OO Oo 0 0 0 0 JO OD DU N H S S S S S S S S lave Embedded BIOSG 2000 V6 0 5 Copyright 2006
23. 2 1 XVME 689 VR7 Jumper Settings essere 2 2 Table 2 202 XVME 689 VR7 PMC Host Connector 2 Pin out 2 17 Table 3 1 Slave Interface Submenu se ee ee Ge Ge GRA GRA RA GR E a E a Re ee ee ee 3 27 vii Introduction Chapter 1 Introduction The XVME 689 VR7 VMEbus Intel Celeron M PC compatible VMEbus processor module combines the high performance and ruggedized packaging of the VMEbus with the broad application software base of the IBM PC AT standard It integrates the latest processor and chipset technology The XVME 689 VR7is the lowest power draw of any of our processors while maintaining a very high level of processing power NOTE The VR7 is a replacement board that is designed to fit into the same chassis as a SBS built VR7 Xembedded has no RTM for the rear I O If you find you need an RTM please contact the factory Module Features The XVME 689 VR7 offers the following features The XVME 689 VR7 is configured with the Intel Celeron M Celeron M Processor at 1 0GHZ Both processor models can be configured with 256MB to 2GB SDRAM 1Mb on die level 2 cache on Celeron M 1 0GB running at the speed of the processor Integrated Video controller using shared system DRAM for VRAM Enhanced IDE controller capable of driving two EIDE devices on P2 NOT compatible with the XVME 977 or XVME 979 Two channels of SATA 150 out P2 Use the XVME 990 VR7 to provide the connectors needed to co
24. 3 BIOS Setup Menus The XVME 689 VR7 customized BIOS is designed to surpass the functionality provided for normal PCs The custom BIOS allows access to the value added features on the XVME 689 VR7 Some of the on board features of the XVME 689 VR7 can also be setup via on board jumpers most of the time if a feature can be setup either way the jumper takes priority over the BIOS settings Navigation moving your cursor around selecting items and changing them is easy in the Setup system The following chart is a helpful user reference Table 3 1 BIOS Keyboard navigation UP key also E Move the cursor to the line above scrolling the window as necessary DOWN key also X Move the cursor to the line below scrolling the window as necessary LEFT key Go back to the menu to the left of the currently displayed menu in the menu bar RIGHT key Go forward to the menu to the right of the currently displayed menu in the menu bar PGUP key Move the cursor up several lines a full window s worth scrolling the window as necessary PGDN key Move the cursor down several lines a full window s worth scrolling the window as necessary HOME key Move the cursor to the first configurable field in the current menu scrolling the window as necessary END key Move the cursor to the last configurable field in the current menu scrolling the window as necessary ESC key Exit the Setup system disca
25. 4 DD6 24 DD1 14 IORDY 4 DASP 33 DD9 23 DD14 13 GROUND 3 3 3V 32 DD5 22 DDO 12 DMACK 2 3 3V 31 DD10 21 DD15 11 INTRQ 1 DEVADR Installation and Setup VMEbus Connectors VMEbus P1 Connector Table 2 16 P1 Connector Pin out Pn z a B ET D i MPR Doo BBSY mm Le 2 GND boi BCLR Dog GND pe GND Do5 BaiN Dis Vi 7 MMD Dos BGIOUT Did v2 8 GND Do7 mea Dis RSVU2 12 GND Ds BRo SYSRESET 14 GND WRITE me AMS 16 GND DIAC amo A2 y Pf Ld8 GEND ASE PANES EN Age EEN 20 GND lack eno Aa os GND JACKQUI NO Ale e 24 GND A0 mr as TI 25 RSVBUSE we me a RSvBU4 Hos GNE A05 H 5 Ae po o 0 Lar asveuss ao oe an wr 28 oun A0 mas mato o ASVBUSTO Ao iom MS 76 so eno A0 mar A08 31 RSVBUS my NC nx GND Some pins in columns Z and D are use internally as test points these are denoted by italics These pins are not intended to drive any external devices and MUST not be used for any purpose 2 12 Installation and Setup VMEbus P2 Connector wel omma NE mm IE 1 FD_DRVO VGA RED 5bV USBO FDINDX VGA GREEN Pepe __ FONE 2 GND _ 4 GND VGAHSYN A24 USBi amp FDSTEP 5 FD
26. 6 209 can support one additional carrier module stacked to create a three slot set of boards that can support five PMC cards Table 2 18 PCI bus interconnect for optional carrier module P3 Pin Number P3 Pin Number 1 STOLK PD TRST P D l6 8 E NC PCLKS3 note 1 PIRQA NC PCLKS2 note 1 Although not shown the P3 connector supplies Vi o 5v VCC 5V and GND through the center pins Notes 1 PCICLK2 and PCICLK3 are not supplied by the XVME 689 VR7 These clocks were needed for on board PCI devices and were not used by any currently supported daughtercards 2 15 Installation and Setup PMC Host Connectors PMC Host Connector 1 Table 2 19 XVME 689 VR7 Daughterboard PMC Host Connector 1 Pin out 7 21 22 Signal TK 3 pa GND EE l 2X CI RSVD14A CICLK reno og or reno V VO 10 11 12 13 14 15 16 17 19 20 Pin 6 Es 8 EA 10 wA 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 23 24 25 26 27 28 29 30 31 32 Signal G G G D C BE A A A V R ADS PADS D GND EQ64 ND ND 5V ND AR ND D 15 D 12 D 11 D 9 Die D 5 D 4 ND DS D 2 D 1 D 0 ND 2 16 Installation and Setup PMC Host Connector 2 Table 2 202 XVME 689 VR7 PMC Host Connector 2 Pin out CPU Fan Power Conne
27. Acromag ld THE LEADER IN INDUSTRIAL LO XVME 689VR7 6U VME Intel Celeron M Processor Board USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 978D Revision Description Init Errors in J2 and PO pin out Error Correction Error Correction Part Number 74689 VR7 Trademark Information Brand or product names are trademarks or registered trademarks of their respective owners Intel and Pentium are registered trademarks and Celeron is a trademark of Intel Corporation Windows Windows NT Windows 2000 and Windows XP are registered trademarks of Microsoft Corporation in the US and in other countries Copyright Information This document is copyrighted by Xembedded Incorporated Xembedded and shall not be reproduced or copied without expressed written authorization from Xembedded The information contained within this document is subject to change without notice Xembedded does not guarantee the accuracy of the information WARNING This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures Warning for European Users Electromagnetic Compatibility European Union Directive 89 336 EEC
28. D485 1 2 DCD4 485TXD DSR4 485TXD RI4 485RXD DTR4 485RXD AN RS 232 JPe2 BE RS 422 RS 485 Y denotes default D SIDD SIDD SIDD ID gt DS DS a 2 2 Installation and Setup Switch Settings The XVME 689 VR7 has one four pole switch SW1 shown in Figure 2 2 The switches functions are explained in table 2 2 This switch controls the system response to the front panel Abort switch Figure 2 2 shows the switch settings required to reset on the XVME 689 VR7 CPU to reset only the VME backplane or to reset both The XVME 689 VR7 is shipped with all four switches in the closed position which causes the push button reset switch to reset both the XVME 689 VR7 and the VME backplane Figure 2 2 SW1 XVME 689 VR7 has a 4 position DIP switch to control the following functions Table 2 2 Four Pole Switch SW1 Functions Position Open Closed 1 Do not respond to SYSRESET Respond to SYSRESET 2 Toggle switch does not cause SYSRESET Toggle switch causes SYSRESET 3 SYSFAIL asserted on Power Up SYSFAIL not asserted on Power 4 No local reset Toggle switch causes local reset Registers The XVME 689 VR7 modules contain the following Xembedded defined I O registers 218h 219h 233h and 234h Register 218h Abort CMOS Clear Register This register controls the abort toggle switch and allows you to read the CMOS clear jumper main board J21 Table 2 3 Abort CMOS Clear Register Setti
29. E THE OEM S ADAPTATION AND OTHER FACTORS ARE BEYOND GENERAL S CONTROL YOU ARE ADVISED THAT THIS FEATURE COULD CAUSE DATA LOSS AT YOUR SOLE EXPENSE ACCORDINGLY IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND ALWAYS BACKUP YOUR DATA BEFORE PERFORMING DIAGNOSTICS ON ANY SYSTEM AS THEY COULD CAUSE DATA LOSS Floppy Disk Read Stimulation Enables System Monitor s read of a preconfigured number of sectors from a location on the first floppy disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first floppy drive is configured in the BBS list as a USB floppy drive Floppy Disk Write Stimulation Enables System Monitor s write of a preconfigured number of sectors to a location on the first floppy disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first floppy drive is configured in the BBS list as a USB floppy 3 22 BIOS Setup Menus drive Please note that when this parameter is selected the system automatically enables reading so that the stimulation of the system includes reading a range of sectors into a memory buffer and writing the same data back to the same range of sectors for safety Thus this feature is theoretically nondestructive WARNING BECAUSE THE OEM S ADAPTATION AND OTHER FACTORS ARE BEYOND GENERAL S CONTROL YOU ARE
30. K Example VMEbus Slave Image 0 BS 0000000h BD A0000h TO 0000000h The second VMEbus Slave Image must have the Base register set to be contiguous with the Bound register from the first VMEbus Slave Image The Bound register is limited by the Total XVME 689 VR7 DRAM The Translation Offset register is offset by 384K which is equivalent to the A0000h FFFFFh range on the XVME 689 VR7 board Example VMEbus Slave Image 1 BS A0000h BD 400000h TO 060000h This rather awkward mapping defined by the PC AT architecture can also be over come if the VMEbus Slave Image window is always configured with a 1Mbyte Translation Offset From a user and software standpoint this is always more desirable because the interrupt vector table system parameters and communication buffers keyboard are placed in low DRAM This provides for more system protection Caution When setting up slave images the address and other parameters should be set first Then only after the VMEbus slave image is set up correctly should the VMEbus slave image be enabled If a slave image is going to be remapped disable the slave image first then reset the address After the image is configured correctly enable the image again The VMEbus slave cycle becomes a master cycle on the PCI bus The PCI bus arbiter is the 6300ESB chip It arbitrates between the various PCI masters the Pentium and the Local bus IDE bus mastering controller Because the VMEbus can not be retried all VMEb
31. Network Stack Disabled rmbase User Shell Disabled rmbase Application Suite Disabled Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc N Figure 3 8 Firmbase Technology Configuration The following table presents the settings that enable high level features enabled by Firmbase Technology Legacy USB Enables BIOS support for USB keyboards and mice Up to 8 USB keyboards and 8 USB mice may be supported at a time Use of PS 2 keyboard and mouse concurrently with USB devices is discouraged as the legacy PS 2 keyboard controller cannot easily separate simultaneous data streams from both device classes USB Boot Enables BIOS support for accessing USB mass storage devices and emulating legacy floppy hard drive and CDROM drive devices with them 3 19 BIOS Setup Menus Enable this option in order for USB devices to be supported in the BBS device list see the BOOT menu EHCI USB 2 0 Enables EHCI Firmbase Technology driver allowing USB Boot feature to use high speed transfers on USB 2 0 ports in the system Firmbase Disk I O Enables Firmbase Technology FAT file system driver so that Firmbase applications such as Boot Security Platform Update Facility and HA Monitor as well as the HA and TCB components of the kerne have access to files residing on drives containing FAT file systems Also turn on this option if you wish to run Firmbase applications from FAT fil
32. OS settings that don t easily fit in any other category They include Cache Control Keyboard Control Debugger Settings and System Monitor Utility Configuration parameters Figure 3 9 shows the Misc Setup men 3 20 BIOS Setup Menus System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase Cache Control CPU Cache System Cache Keyboard Control Keyboard Numlock LI Disabled Typematic Rate 30 sec Typematic Delay 250ms Miscellaneous BIOS Configuration Lowercase Hex Displays Disabled Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc Figure 3 9 Misc Setup Menu The following table presents the settings in the Misc Setup menu System Cache Enables POST s support for cache in the system Modern processors virtually require cache to be enabled to achieve acceptable performance However to diagnose certain problems related to caching in the system such as multiprocessing systems it may be desirable to disable this setting Keyboard Numlock LED Enables the Numlock key when POST initializes the PS 2 keyboard Typematic Rate Specify the rate at which the PS 2 keyboard controller repeats characters when most keys are pressed down USB typematic is automatic and does not use this parameter Typematic Delay Specifies the amount of time a repeating key may be pressed on a PS 2 keyboard until the key repeat feature begins repeating the keystr
33. PDF version of the Universe manual Figure 4 2 shows address invariant translation between a PCI bus and a VMEbus Pentium Register 32 bit VMEbus Address M M 1 M 2 M 3 XVME 689 690 VMEbus Figure 4 2 Address Invariant Translation Notice that the internal data storage scheme for the PCI Intel bus is different from that of the VME Motorola bus For example the byte 78 the least significant byte is stored at location M on the PCI machine while the byte 78 is stored at the location M 3 on the VMEbus machine Therefore the data bus connections between the architectures must be mapped correctly 4 8 Rear Transition Module Numeric Consistency Numeric consistency or data consistency refers to communications between the XVME 689 VR7 and the VMEbus in which the byte ordering scheme described above is maintained during the transfer of a 16 bit or 32 bit guantity Numeric consistency is achieved by setting the XVME 689 VR7 buffers to pass data straight through which allows the Universe chip to perform address invariant byte lane swapping Numeric consistency is desirable for transferring integer data floating point data pointers etc Consider the long word value 12345678h stored at address M by both the XVME 689 VR7 and the VMEbus as shown in Figure 4 3 Pentium Register 32 bit VMEbus Byte swapping Hardware Address M M 1 M 2 M 3 XVME 690 VMEbus Figure 4 3 Maintaining Numeric Consistency Due to the
34. PMM SMBUS SMBIOS Manufacturing Mode Splash Screen Console Redirection and others added by the OEM Figure 3 7 shows a typical Setup System Configuration Utility Main Exit Boot Post PnP BIOS Feature Configuration Interrupt Processing POST Memory Manager SMBUS API Console Redirection P7 Geyserville Enab Microcode Update Enabl Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software APIC Mode Disabled Disabled Automatic ed ed SIO Misc gt Select APIC mode to Support APIC aware Operating Systems Features Firmbase Ene Figure 3 7 BIOS Feature Configuration The following table describes each setting in the Features menu Quick Boot Enable time optimized POST causing certain preconfigured OEM optimizations to be made when the system boots Depending on the system Quick Boot can reach the DOS prompt in as little as 85ms milliseconds Advanced Power Management APM Enable legacy power management used by the system when an ACPI aware operating system is not running during POST such as when the system is running the preboot environment or while running DOS Windows95 Windows98 or Linux kernels below version 2 6 Uses the SMM feature see Firmbase to operate properly 3 17 BIOS Setup Menus ACPI Enable ACPI system description and power management ACPI replaces PnP and APM Used with ACPI aware OSes such as Linux kern
35. T Driver PRI SGL RRS Arbiter RWD ROR bus release Form Factor DOUBLE 233 7 mm x 160 mm 9 2 x 6 3 System Configuration and Expansion Options Tables Table 1 2 XVME 689 VR7 CPU configurations Ordering CPU Type Number XVME 689 VR7AXY Intel Celeron M 1 0GHz Handle and PO configurations Memory configurations Y 1 VME 64 IEEE 1101 1 Std legacy handles w o Xz1 for 256 MB ECC DRR SDRAM VMEbus PO Y 2 VME 64 IEEE 1101 10 Compact PCI type handles X 2 for 512 MB ECC DRR SDRAM w o VMEbus PO Y 3 VME 64 IEEE 1101 1 Std legacy handles with the X 2 3 for 1 GB ECC DRR SDRAM VMEbus PO Y 4 VME 64 IEEE 1101 10 Compact PCI type handles with the VMEbus PO Note Some features on the XVME 689 VR7 are only available in a 160 pin 5 Row VMEbus P2 backplane The ordering number is broken into two parts The model number is the 689 VR7 The tab number is the three digits after the slash For the XVME 689 VR7 the tab number indicates the CPU type amount of SDRAM memory the middle digit and the ejector handle type and optional PO connector Introduction Table 1 3 XVME 689 VR7 Expansion Module Options Ordering Number Description XVME 990 VR7 1 Drive Adapter Module for external drives cables out back of VME backplane Primary PIDE 2 PIDE Floppy COM2 Only RS 232 two ports of SATA 150 LPT1 1 USB port Audio in out and Analog Video out plus PO for rear VO from PMC
36. WGAT GND v A255 VGAVSYN FDWDAT 6 Lon AUDLINE INL A NC DI 9 LPTIAFED AUD LINE OUT R JA29 JNC J LPTI STRO 10 GND GND ABO GND J LPTI DO 11 PT ERRO SATA TXPO A31 SATATXP LPT DI 12 GND SATA TXNO GND SATATXN LPT D2 13 LPTi INT Town 5V GND LPT DS 14 GND SATARXPO0 VDi6 SATARXPi1 LPT1 D4 15 LPTi SLIN SATA RXNO VDi7 SATARXNi LPT1 D5 16 GND GND VDi8 GND LPT D6 18 GND KYBDDATA VD20 KYBDCLK LPT1_BUSY 19 LPTi SLCT MOUSEDATA VD21 MOUSECLK X LPTI PE 20 GND ETH2PINT TXA VD22 ETH2PINZ TXA WDG REL 21 COMS DSR ETH2 PIN 3 RXA VD23 ETH2PIN4 NC COM3 DCH LAN ETH2 PIN 5 NC ETH2 PIN 6 RXA COM3 RXD 23 COMS3 TXD ETH2 PIN 7 NC VD24 ETH2 PIN 8 NC COMS3 RTS 24 GND _ COM1_DSR VD25 COM1 DCD COMS3 CTS 25 COM3 RI COM1 RTS VD26 COM1 RXD COMS3 DTR ree COM1 CTS VD27 COM1 TXD COM4 DCD C4 TXD COMA RXD COM1 RI VD28 COM1_DTR COM4_DSR C4_TXD GND COM2 DCH VD29 GND COM4RTS ha ie CTS VD30 COM2 DSR COM2 RXD COM4_TXD Em TXD VD31 COM RTS COM4 DTR C4 RXD Nl oca RKC se ie DTR COM CTS EH GND SV COM RI EC Table 2 17 VMEbus P2 Connector 2 13 VMEbus PO Connector IDE PDDACK N C N C Installation and Setup PMC VO 32 IDE PDDREQ N C PMC VO 17
37. X IRO 1 AD 20 09H PMC XVME 689 VR7 PMC X site 8007 8000 PCI R G 1 3012 AD 26 OFH 855GME 3580 8086 3584 8086 3885 8086 Host Hub interface DDR SDRAM I F Legacy control Device 0 Host to AGP Bridge Virtual PCI to PCI Device 1 Intel 855GME GMCH Only Integrated Graphics Controller IGD Device 2 0000 0000 6300ESB 244e 25A1 25A2 25A9 25AD 25A4 25A6 25A7 Hub to PCI bridge LPC Interface IDE Controller USB UHCI Controller USB EHCI Controller SMBus Controller AC 97 Audio AC 97 Modem Watchdog Timer APIC1 HUB to PCI X Bridge Serial ATA Controller Universe IID PCI VMEbus Bridge 8000 5000 PCI R G 0 OAH PMC 1 70976 201 8000 A000 R G 2 14H PMC 1 70976 2083 8000 A000 R G 2 14H PMC 2 70976 203 8000 9000 R G 3 12H PCI Card 70976 205 8000 A000 R G 2 DOOD gt OD OO D OMOU O TOP O 14H 4 4 Rear Transition Module VME Interface The VME interface is the Tundra Universe IID chip which is a PCI bus to VMEbus bridge device The XVME 689 VR7 implements a 32 bit PCI bus and a 32 64 bit VMEbus interface The Universe chip configuration registers are located in a 4 KB block of PCI memory space This memory location is programmable and defined by PCI configuration cycles The VMEbus controller has four main functions System Resources or the traffic cop
38. Y format on which the OEM built the system BIOS binary file System BIOS Size Size of BIOS exposed in low memory below the 1MB boundary Commonly 128KB would mean that the BIOS is visible in the address space from E000 0000 to F000 FFFF CPM CSPM BPM Modules Indicates the names of the key architectural modules used to create the system BIOS binary file The CPM module provides the CPU family support the CSPM module provides the northbridge support and the BPM module provides the board level support Option Description Real Time Clock Sets the real time clock for hour HH minute MM and HH MM SS seconds SS The hour is calculated according to the 24 hour military clock 00 00 00 through 23 59 59 Use TAB or ENTER to move the cursor right and SHIFT TAB to move it left Use the number keys 0 9 to change the field values It is not necessary to enter the seconds or type zeros in front of numbers Real Time Clock MM DD YY YY Sets the real time clock for the month MM day DD and year YY YY The valid values in this field are 01 01 1981 through 12 31 2099 Use TAB or to ENTER move the cursor right and SHIFT TAB to move it left Use the number keys 0 9 to change the field values It is not necessary to type zeros in front of numbers The CPU information is automatically obtained The system memory information does not describe physical RAM rather 1t describes the RAM as configure
39. ctor The fan 12 V and 5 V supplies are protected with a polyswitch This device will open up if 12 V or 5 V is shorted to GND Once the shorting condition is removed the polyswitch will allow current flow to resume Table 2 21 CPU Fan Power Connector Pin out Pi Signal 12V fused 5V pullup 2 17 Installation and Setup Installing the XVME 689 VR7 into a Backplane This section provides the information necessary to install the XVME 689 VR7 into the VMEbus backplane The XVME 689 VR7 is a double high single slot VMEbus module Note Xembedded modules are designed to comply with all physical and electrical VMEbus backplane specifications of VME64x Note The XVME 689 VR7 is available from the factory in two basic configurations with PO and without PO The without PO would normally be used in a legacy system since most of these racks are equipped with a stiffener bar in the PO location Also note that to use the extended features of the XVME 689 VR7 the backplane must use 160 pin P1 and P2 Caution Do not install the XVME 689 VR7 on a VMEbus system without a P2 backplane Warning Never install or remove any boards before turning off the power to the bus and all related external power supplies 1 Disconnect all power supplies to the backplane and the card cage Disconnect the power cable Make sure backplane 5 rows 160 pin connectors P1 and P2 are available Verify that all jumper settings are corr
40. d subtracting RAM used for System Management Mode Shadowing Video buffers and other uses This provides realistic values about how much memory is actually available to operating systems and applications The Real Time Clock fields are editable with keystrokes To navigate through the MM DD Y Y YY and HH MM SS fields use the TAB and BACKTAB keys The hours are normally specified in military time thus 13 means 1pm or one hour after noon whereas 01 means lam or one hour after midnight When the cursor leaves RTC fields they either affect the battery backed RTC right away allowing the system to continue with your new settings or they revert back to old values if the new values are not valid entries 3 3 BIOS Setup Menus 3 2 Exit Menu The Exit menu provides methods for saving changes made in other menus discarding changes or reloading the standard system settings This menu is shown in Figure 3 2 below System Configuration Utility Main Exit Boot Post PnP SILO Features Firmbase Misc Save Settings and Restart Enter Press ENTER to save Change and reboot Exit Setup Without Saving Changes Enter System Reload Factory Defaults and Restart Enter Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc N Figure 3 2 Save Restore and Restart Menu To select any of these options position the cursor over the option and press the ENTER key Pressing the ESC key at any time within the Setup system
41. data straight through or to swap the data bytes as they are passed through Note The configurable byte swapping hardware does not support 64 bit byte swapping If needed this should be implemented through software Byte Ordering Schemes The Motorola family of processors stores data with the least significant byte located at the highest address and the most significant byte at the lowest address This is referred to as a big endian bus and is the VMEbus standard The Intel family of processors stores data in the opposite way with the least significant byte located at the lowest address and the most significant byte located at the highest address This is referred to as a little endian or PCI bus This fundamental difference is illustrated in Figure 4 1 which shows a 32 bit quantity stored by both architectures starting at address M 4 7 Rear Transition Module Address INTEL MOTOROLA Low Byte M High Byte High Byte Figure 4 1 Byte Ordering Schemes Note The two architectures differ only in the way in which they store data into memory not in the way in which they place data on the shared data bus The XVME 689 VR7 contains a Universe chip that performs address invariant translation between the PCI bus Intel architecture and the VMEbus Motorola architecture and byte swapping hardware to reverse the Universe chip byte lane swapping Contact Tundra at www tundra com for a
42. ddress All PCI slave images are located in the PCI bus Memory Space The master cycles are all byte swapped maintaining address coherency Caution PCI slave images mapped to a system DRAM area will access the system DRAM not the PCI slave image Also the Universe configuration register has a higher priority than the PCI slave images This means if the PCI slave image and the Universe configuration registers are mapped in to the same memory area the configuration registers will take precedence VMEbus Slave Interface The XVME 689 VR7 can be either a VMEbus slave by being accessing a VMEbus slave image or the DMA channel initiates a transaction There are eight PCI slave images The first slave image has a 4K resolution the others 2 4 6 8 have 64K resolution Slave images 1 8 have been implemented on the XVME 689 VR7 The slave can respond to A16 A24 A32 VMEbus cycles for each VMEbus 4 5 Rear Transition Module slave image The address mode and type are also programmed on a VMEbus slave image basis The VMEbus memory address location for the VMEbus slave cycle is specified by the Base and Bound address The PCI address is calculated by adding the Base address to the Translation offset address The XVME 689 VR7 DRAM memory is based on the PC AT architecture and is not contiguous The VMEbus Slave Images may be setup to allow this DRAM to appear as one Contiguous block The first VMEbus slave Image must have Base and Bound register set to 640
43. e eke 2 8 5 12 VME interface iese esse esse ses se de Se a 4 5 VMEbus compliance ee ee ee RA RA 1 9 interface maseira ee EEN 1 5 interrrupt handling 4 6 interrupt Generation 4 7 reset OPLIONS ee eeeeeeeeseereeereeeneeeeeees 4 7 VMEbus connectors ce sesse se se ee see 2 12 VMEbus slave interface 3 26 VMEbus system resources 3 24 watchdog mer 1 5 watchdog timer register 2 4 XVME 9000 EXF esse esse esse ee 1 10 XVME 973 1 eese 1 3 1 10 5 1 XVMBE 073 5 teens 1 10 XV MIER 1 meet deine 1 5 1 10 XVMB 0T7T ee oge Es dese nitent 1 3 1 10 XVME 979 eene 1 3 1 10
44. e etit toa NE EE RE N EA N 1 9 System Configuration and Expansion Options Tables eese 1 9 Chapter 2 Installation and Setup ccccccccsssseeeeeeeeeeeeeeseeeeeeeeeeeeeeeeeesesseeeeeeeeeeesseeeseeenees 2 1 3Juriper EDERT heute de eee me EE AE EE 2 2 Witch Stun GS EE ER AE tage ee ee dt ceded edet oe eed ttd 2 3 I Ou o CA RE A N 2 3 Front Panel Layout 2 3 pee ER EE EE EN 2 5 UE 2 6 COMI and COM4 J4 Pin Defmong cono ee ee Ge Ge Ge GRA GRA GR ee iea 2 10 purpose VMEbus P2 Connector EE 2 12 VMEbus E EE 2 13 Installing the XVME 689 VR7 into a Backplane 00 ese sees se ee se ee ek GR ee ee ee ee ee ee 2 18 Enabling the PCI Ethernet Controller esse ese ee Ge Ge GR GR GR ee ee ee ee ee 2 20 Chapter 3 BIOS Setup Menu issie ie Se SEKER ER rere KEN Be Eie sl EER EKEN Re Gee GENRE ER EN Ee EE EE 3 1 3 1 Main Setup Merl neret gne OE EE OE 3 2 PAS AE AA EE EE NR on eei ccs 3 4 3 3 ystem Boot Me ii tte AA et Bact ee ttn be ette tet een esca 3 5 3 4 POST Memory Tests die teer e n He er ert NE N eb ere AE OE 3 9 3 5 Plug and Play Configuration Men 3 12 3 6 BIOS Super VO Configuration Menu 3 15 3 7 BIOS Super VO Configuration Menu 3 17 3 8 Firmbase Technology Configuration iese esse esse ee se ee ee ee ee ee ee ee Ge ee ee ee Ge ed 3 19 3 9 Mise n nina EE EE EE EE 3 20 35 10 VM LASER oa MEE MR eon Eb EE EE OE N TE 3 24 3 12 Front Panel reso rces control si ste
45. e over a serial port Automatic causes POST the debugger and the preboot environment to use the system s first serial port COMI when an RS232 cable is detected with DSR and CTS modem signals active indicating a terminal emulation program is likely to be attached ot the other end of the cable Always causes the BIOS to always use the serial port as the console without testing for the presence of the terminal emulation program Never causes the BIOS to never invoke console redirection but instead always use the main keyboard and video display If there is no keyboard or video display the system operates headless 3 18 BIOS Setup Menus 3 8 Firmbase Technology Configuration This menu is highly configurable by the OEM who may elect to eliminate some of the Firmbase Technology tuning parameters in more fixed function devices To illustrate what all of the standard Firmbase Technology configuration parameters are System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase Misc Firmbase Technology Configuration Enable to provide SMM Support necessary for Firmbase Technology Enabled Legacy USB USB boot Firmbase And some other features Firmbase Features Enabled by Firmbase Technology Legacy USB Enabled USB Boot Enabled EHCI USB 2 0 Enabled rmbase Disk I O Disabled rmbase User Registry Disabled rmbase User Section Disabled rmbase
46. e systems on either ATA or USB mass storage devices Firmbase User Registry Enables execution of the USER Firmbase registry section which is preconfigured by the OEM This may run OEM specific applications Firmbase Network Stack Enables Firmbase Technology internet protocol stack including MAC driver for the platform TCP UDP as well as presentation level drivers configured by the OEM which may include SNMP SMTP TELNETD and HTTP server Firmbase Desktop Enables Firmbase Technology graphical shell Firmbase User Shell Enables Firmbase Technology command line interpreter a multi user command shell with DOS like and Unix like command structure can be used to start Firmbase applications written with the Firmbase SDK a General Software product Firmware Application Suite Enables Firmbase applications configured for the system by the OEM Typically includes Boot Security Platform Update Facility and High Availability Monitor Firmbase Technology Enables Firmbase Technology as a whole the industry s most comprehensive and full featured System Management Mode SMM operating environment Some hardware platforms require Firmbase Technology to run as they may use it to virtualize hardware such as virtual video and audio PCI devices Some BIOS features such as ACPI and APM may require Firmbase Technology to operate 3 9 Misc Menu The Misc menu provides for configuration of BI
47. e terminated directly to the metal connector shell shield ground drain wires alone are not adequate VME panel mount connectors that provide interface to external cables e g RS232 USB keyboard mouse etc must have metal housings and provide direct connection to the metal VME chassis Connector ground drain wires are not adequate Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible Many of the components used structural parts printed circuit boards connectors batteries etc are capable of being recycled Final disposition of this product after its service life must be accomplished in accordance with applicable country state or local laws or regulations Table of Contents Table of Contents XVME 689 V R TE OO ER EE EE N i Table ot Contents ore tero ERE QU Et ter N LE N EE OE v Tabl of Figures and Tables iuris t een ieee E niea vii Chapter 1 Introducido EE EE 1 1 Module Features c oO tee EE EE AE OE ete ei b 1 1 ATOhIteCtute xit SE A teer Rte dete A tp be hr IP RENE EH 1 2 Software SUDDORL ee erdt te cte Lie ettet eta NE RE N NOR EE aee ooa 1 5 Operational Descriptions ir ere erg ee eee O tete tse 1 6 Environmental Specifications iss ees EER ede Lees gee desee pe ee dant do eaa ee Ge BEER de ea ea donee ee ee se De Ee Gee ge eia 1 6 Hardware Speciications aiii ete iUd eie etre EE ee oder tu diee cus 1 8 VMEbus Specification eode et
48. eallocated by the system BIOS so that it can be used by the OS when it boots To reenter the Setup system after boot simply press the reset on the front panel or cycle the system power Note The default values given in the descriptions are for the XVME 689 VR7 board with no peripheral devices attached If drives are connected their values will be shown 3 1 Main Setup Menu This Main menu System Summary provides information about the BIOS processor system memory and allows the setup of date and time Only the date and time fields are user definable in this menu System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase Misc General Software R System BIOS BIOS Version 6 0 Use TAB to switch between Point OEM Versions 5 3 Month day and year and OEM Board Version 3 Hour Minute and Second BIOS Build Date MM DD YYYY Use digits and BKSP System BIOS Size 128KB To change field CPM CSPM BPM Modules P7C7 855 X689 VR7 Processor CPU Intel Pentium M Processor 1 00GHz System Memory RAM Low Memory KB 628 Extended Memory KB 1035136 Real Time Clock RTC RTC Date MM DD YYYY RIC Time HH MM SS Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc N Figure 3 1 Main Setup Menu BIOS Setup Menus BIOS Version Indicates the major and minor core architecture versions 6 x where x is a number from 0 to 999 BIOS Build Date Date in MM DD Y
49. ect Verify that the card cage slot is clear and accessible UU SECUS Install the XVME 689 VR7 in the card cage by centering the unit on the plastic guides in the slots P1 connector facing up Push the board slowly toward the rear of the chassis until the P1 and P2 connectors engage The board should slide freely in the plastic guides Caution Do not use excessive force or pressure to engage the connectors If the boards do not properly connect with the backplane remove the module and inspect all connectors and guide slots for damage or obstructions 6 Secure the module to the chassis by tightening the machine screws at the top and bottom of the board 7 Connectall remaining peripherals by attaching each interface cable into the appropriate connector on the front of the XVME 689 VR7 board as shown in Table 2 2 18 Installation and Setup 8 Turn on power to the VMEbus card cage Table 2 22 Front Panel Connector Labels VGA USE PMC 2 19 Installation and Setup Enabling the PCI Ethernet Controller Loading the Ethernet Driver To enable the Ethernet controller you must load the applicable Ethernet driver for your operating system from the Documentation and Support Library CD included with the XVME 689 VR7 For best results always use the supplied drivers Ethernet RJ 45 10 100 1000 BaseT Connector P12 Table 2 23 RJ 45 10 100 1000 BaseT Connector Pin out 2 20 BIOS Setup Menus Chapter
50. els version 2 6 and above Windows XP and Windows Vista Commonly also uses the SMM feature see Firmbase to operate properly POST Memory Manager PMM Enable memory allocation services for option ROMs especially network cards running PXE Some option ROMs may use this interface incorrectly causing system crashes Other PXE option ROMs may not run if PXE is not supported Because of the state of these option ROMs the setting is provided as an option to the user SMBUS API Enable INT 15h services that permit certain software to access devices on the system s SMBUS without having knowledge of the SMBUS controller itself Such devices include TV radio tuners volume controls brightness and contrast controls etc SMBIOS Enable System Management BIOS interface specification support exposing information about the type of hardware including the chassis motherboard layout type of CPU and DRAM sticks to applications such as WfM which runs on PXE in the preboot environment Manufacturing Mode Enable automatic entry into manufacturing mode when POST encounters a critical error Used in closed device settings such as smart phones that need access to docking stations when they don t boot Splash Screen Enable graphical POST including animation sound icons advertisements and other multimedia objects that may be configured by the OEM Console Redirection Configure the console redirection featur
51. er tiet eet es ee soge ended ge tue e age be gee Ee 3 28 Ch pter 4 Programmi iioii a 4 1 Memory Mapa ada 4 1 lied RE RM OE N oce RE N ME id 4 1 RE EE 4 3 Table of Contents PCI Device Map EE EE RR EE diia 4 4 MME Interface E 4 5 Software Selectable Byte Swapping Hardware 4 7 Appendix A SDRAM and Battery Installation essere nnn 1 Memory Bur 1 Installing SDRAM 32 eet tete ut et este Nt tod tate tu 1 Module Battery Mstallation sien n ei e ene ee OE Ee 2 DAE EE ee EE EE EE NE EE ER EE 4 vi Table of Contents Table of Figures and Tables Figure 1 1 XVME 689 VR7 Block Diagram sesse esse ese ese es se ese ee Ge de Ge de GR GRA GRA Ge ee ee ee ee 1 6 Figure 3 1 Main Setup Menu deett teneo soes bes ek orga pte dose eb gade beso obe ee Longe 3 2 Figure 3 2 Slave Interface Submenu esee ener Re ee ee ee 3 26 Figure 4 1 Byte Ordering SCHEMES esse see se see ee ee ee ee Ge Ge Ge GRA nono Ge Ge GRA RA Ge ee 4 8 Figure 4 2 Address Invariant Translation eese eene nnne 4 8 Figure 4 3 Maintaining Numeric Consistency ee ee ee ee Ge Ge nennen nennen rennen 4 9 Figure 4 4 Maintaining Address Consistency esse esse ee ee Se eene nennen 4 10 Table 1 1 Maximum Video Modes Supported sese nennen 1 3 Table 1 2 XVME 689 VR7 CPU configurations eese ener nennen 1 9 Table 1 3 XVME 689 VR7 Expansion Module Options eene 1 10 Table
52. erial Port Connector Pin out for Comm 1 and 4 2 10 Installation and Setup On Board Hard Drive Compact Flash Site J17 A horizontal ZIF connector is used on the board Samtec part number ZF5 40 01 TM WT The connector on the board has a reverse pin out because of the connector orientation relative to the hard drive This allows the flex cable to loop up to the hard drive with the connector side facing the board Table 2 14 On Board storage devices us the J17 1 8inch Hard Drive Connector pin assignment Pin Description Pin 8 Description Pin Description Pin z Description 1 factory use 11 DD4 21 GROUND 31 DA1 2 factory use 12 DD11 22 DMARQ 32 PDIAG 3 RESET 13 DD3 23 GROUND 33 DAO 4 GROUND 14 DD12 24 DIOW 34 DA2 5 DD7 15 DD2 25 DIOR 35 CS0 6 DD8 16 DD13 26 GROUND 36 CS1 7 DD6 17 DD1 27 IORDY 37 DASP 8 DD9 18 DD14 28 GROUND 38 3 3V 9 DD5 19 DDO 29 DMACK 39 3 3V 10 DD10 20 DD15 30 INTRQ 40 DEVADR The Hitachi CAK60 CE has a 40 pin ZIF connector Table 2 15 1 8inch Hard Drive Connector pin assignment on hard drive Pin Description Pin Description Pin 4 Description Pin Description 40 factory use 30 DD4 20 GROUND 10 DA1 39 factory use 29 DD11 19 DMARQ 9 PDIAG 38 RESET 28 DD3 18 GROUND 8 DAO 37 GROUND 27 DD12 17 DIOW 7 DA2 36 DD7 26 DD2 16 DIOR 6 CSO 35 DD8 25 DD13 15 GROUND 5 CS1 3
53. ernet Controllers 2 Intel 82546GB 10 100 1000Base TX Gigabit Ethernet RJ 45 Mass Storage Integrated SATA 150 Controller SATAO and SATA1 via P2 EIDE Ultra DMA 100 interface 2 channels via P2 One 1 8 on board EIDE via optional carrier module Compact Flash One on board Compact flash site via optional carrier module Floppy Drive Via P2 to XVME 977 PMC Site On board 66 MHz 64 Bit PMC PCI X with front and PO VO Access Site is 3 3V interface level Optional 32bit 33 MHz sites available via XVME 976 209 2 sites total 3 and XVME 976 210 4 sites total 5 Stereo Audio AD1981B AC97 CODEC Line Level Stereo Input and Output Via P2 USB One USB 2 0 via Front panel Two USB 2 0 via P2 Serial Ports RS 232C 16550 compatible 4 COM1 Front Com 2 and 3 Rear VO Com 4 can be configured for RS 232 422 485 but only the COM 4 out the P2 Com 2 and 3 are RS 232 only The COM 4 out the front is RS 232 data leads only Parallel Interface EPP ECP compatible 1 Keyboard and Mouse Via Front Panel Regulatory Compliance European Union CE Electromagnetic Compatibility 89 336 EEC RoHS Compliant product available Introduction VMEbus Specification VMEbus Compliance Complies with VMEbus Specification ANSI VITA 1 1994 A32 A24 A16 D64 D32 D16 D08 EO DTB Master A32 A24 A16 D64 D32 D16 D08 EO DTB Slave R 0 3 Bus Requester Interrupter 1 1 1 7 DYN IH 1 IH 7 Interrupt Handler SYSCLK and SYSRESE
54. guration ENE EE SCH3114 Devices Parallel Port E Address IRQ DMA Mode Pri Serial Port 1 E Address IRQ Serial Port 2 E Address IRQ Serial Port 3 E 1 Address IRQ E AAA Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc Figure 3 6 BIOS Super VO Configuration Menu The following table provides the basic types of devices that might appear in a typical SIO menu Parallel Port Enable parallel LPT printer port Legacy VO addresses are 378h 278h and 3bch IRQ7 was originally used on the IBM PC Serial Port Enable serial COM communications port Legacy VO addresses and IRQs are as follows COMI VO 3f8h IRQ4 COM 2 VO 2f8h IRQ3 CONG VO 3e8h IRQ4 COMA VO 2e8h IRQ3 It should be noted that these are not the only possible addresses but they are the ones that will ensure compatibility with the most legacy software 3 15 BIOS Setup Menus especially early DOS programs that do not use BIOS to access the COM ports Keyboard Enable PC AT or PS 2 keyboard controller Mouse Enable PC AT or PS 2 mouse portion of keyboard controller GPIO device name Enable GPIO device ACPI device name Enable ACPI device 3 16 BIOS Setup Menus 3 7 BIOS Super VO Configuration Menu The Features menu is used to configure the system BIOS major features including Quick Boot APM ACPI
55. is equivalent to requesting Exit Setup without Saving Changes All three options request verification before performing the selected action otherwise the system configuration might be saved or lost by accident Figure 3 3 illustrates the verification popup for saving and exiting the other options are similar BIOS Setup Menus 3 3 System Boot Menu The Boot menu allows the system s boot actions and boot devices to be configured This menu is shown in Figure 3 3 System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase Misc System Boot Configuration Select Initialization And boot priority for All devices Boot Device Prioritization BBS 0 Fixed USB 0 Backspace deletes 1 2 3 IDE 0 Pri Master Selection Space Floppy 0 Bar and change None Selections loppy Drive Configuration loppy 0 1 44MB 3 5 E Drive Configuration ype toconfig ode 1ti word DMA model ype toconfig ode 1ti word DMA model ype toconfig ode Fastest support model ype Autoconfig Hi Hi Hi Hi Hi Hi Hi Hi FH ode Fastest support mode Figure 3 3 System Boot Configuration Menu When the BIOS completes POST it follows this list attempting to process each item Some items are drives such as an ATA IDE drive or a USB hard disk or CDROM The ordering of the drives in the list the BIOS controls the process in several ways First it is the li
56. llation Appendix A SDRAM and Battery Installation Memory Type The XVME 689 VR7 has one 200 pin DDR333 SDRAM memory module SODIMM site in which memory is inserted The XVME 689 VR7 supports 256MB 512MB 1MB and 2MB of PC2700 SDRAM Table A 1 lists the SODIMM configurations Table A 1 SDRAM SODIMM Configurations Xembedded Part Number Device Type and Size Vendor Vendor part number 200193 SODIMM 256MB DDR333 Micron MT9VDDT3272HY 335F2 Virtium VL485L3223C B3 200194 SODIMM 512MB DDR333 Micron MT9VDDT6472HY 335F2 Virtium VL485L6523C B3 200195 SODIMM 1GB DDR333 Micron MT18VDDT12872HY 335F 1 Virtium VL485L2925C B3 200196 SODIMM 2GB DDR333 Virtium Installing SDRAM Follow these steps to install the SODIMM n7 d 1 Follow standard antistatic procedures using a wrist strap to minimize the chance of damaging the XVME 689 VR7 and its components jae 2 Power off the XVME 689 VR7 remove it from the VME backplane and place it on a safe antistatic grounded surface 3 Remove all connectors if not already removed po 4 Locate the PX connector on the XVME 689 VR7 pen o t slightly in front of the P1 VME backplane connector 5 Pull the metal clips on either side of the SODIMM until it pops up at an angle roughly 30 from horizontal 6 Grasping the upper two corners or the edges of the SODIMM gently pull it out of the socket and set it to the side 7 I
57. must both support the hardware protocol used to autodetect the drive s cable type IDE CABLE SETTINGS PATA cable autodetection sometimes fails with older drives so 40 pin is the default to ensure data integrity If higher performance is desired and it normally is you should change this setting to 80 pin or AUTO if you re sure an 80 pin cable is installed 3 8 BIOS Setup Menus 3 4 POST Memory Tests The POST menu is used to configure POST This menu is shown in Figure 3 4 scrolled down more so the full set of options can be seen System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase Misc mory Tests Enable basic memory Confidence test below Low Memory Standard Test j 1 1MB during POST Low Memory Exhaustive Test High Memory Standard Test High Memory Exhaustive Test Click During Memory Test Clear Memory During Test Error Control e on POST Errors Enabled User Interface Enabled Enabled SEENEN Display PnP Devices Enab POST Debugging POST Debugger Breakpoints Disabled POST Slow Reboot Cycle Disabled POST Fast Reboot Cycle Disabled Device Initialization POST Floppy Seek Disabled POST Hard Disk Seek Enabled Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc Figure 3 4 POST memory test Menu Display Messages Operator Prompt Display PCI Devices
58. nd enter Setup or continue to boot the OS The following table describes the settings associated with the POST setup menu s POST User Interface section POST Display Messages Enable display of text messages during POST When disabled POST is quiet POST Operator Prompt Enable operator prompts if POST is configured to ask interactive questions of the user about whether to load specific features i e whether or not to load SMM POST Display PCI Devices Enable display of PCI devices POST Display PnP Devices Enable display of ISA PnP devices The following table describes the settings associated with the POST setup menu s Debugging section POST Debugger Breakpoints Enable processing of INT 3 breakpoint instructions embedded into option ROMs When enabled if an INT 3 instruction is encountered control is transferred to the BIOS debugger so that the option ROM can be debugged When disabled these instructions perform no action 3 10 BIOS Setup Menus POST Fast Reboot Cycle Enable early reboot in POST allowing service technician to verify that the hardware can reboot very guickly many times in succession Platform will continue to reboot after every boot until the system s CMOS is reset as there is no way to enter Setup from this early point during POST POST Slow Reboot Cycle Enable late reboot in POST allowing service technician to cause the
59. ngs Bit Signal Resut aw 0 RESERVED Reserved gt 1 RESERVED Reserved 2 RESERVED Reserved gt o 3 RESERVED Reserved 000000 ABORT STS 1 Abort toggle switch caused interrupt R 5 ABORT CLR 0 Clear and disable abort R W 1 Enable abort 6 RESERVED Reserved N 7 CLRCMOS 0 Clear CMOS 1 CMOS okay 2 3 Installation and Setup Register 219h Flash Control Register This register controls the following LEDs and signals Table 2 4 LED BIOS Register Settings al CIN Re RW FAULT 0 Fault LED on RAN 12 Fault LED off 1 PASS 0 2 PASS LED off RAN 12 PASS LED on EMM E ERC 4 RESERVED Resme O O Oo OOTO S RESERVED Resme 6 RESERVED Resme T 7 RESERVED Resme O o To Register 233h Watchdog Timer Register This register controls watchdog timer operation Table 2 5 Watchdog Timer Register Settings Bk Sue Re o RESERVED Resme 5 MRESET EN 1 Timeout generates 0 Timeout generates IRQ10 6 WDOG STS Watchdog timer status bit 7 WDOG CLR Toggling this bit clears the watchdog timer back to a zero count Note Before enabling the watchdog timer for the first time it is necessary to reset the count back to zero by toggling bit 7 WDOG CLR Toggling implies changing the state of bit 0 to 1 or 1 to 0 2 4 Installation and Setup Register 234h Flash
60. nnect external SATA drives Floppy disk controller capable of driving one floppy drive on P2 NOT Compatible with XVME 977 Dual 10 100 1000 Base T Ethernet controllers with front panel RJ 45 connectors with isolated ground or selectable out the PO to support rear Ethernet or Vita 31 1 Type VII Compact Flash site on optional carrier VME64X VMEbus interface with programmable hardware byte swapping Support for Vita 31 1 Switch Fabric in complaint back planes Four serial ports e Two RS 232 serial port on front panel Com 1 and 4 two RS 232 serial port Com 2 and 3 on P2 NOTE COM 4 is also available out the P2 and can be configured for RS 232 422 485 Three Universal Serial Bus USB 2 0 port one on front the other two out P2 EPP ECP configurable parallel port P2 on 26 pin header on the XVME 990 VR7 Combined PS 2 compatible keyboard mouse port on front panel PCI 80 pin Expansion Connectors NOT Compatible with X VME 976 01 thru XMVE 976 205 Carriers must use the XVME 976 209 PMC PCI Mezzanine Card site with front panel I O 32 64 bit 33 66MHz with rear I O using optional PO connector This site is on the internal PCI X bus 1 1 Introduction e Front panel ABORT RESET switch with indicating lights Red for fail and green for pass e Electrical isolation and noise immunity on the Ethernet ports Serial Port and PMC site e Ejector type handles in IEEE 1101 10 Compact PCI type or IEEE 1101 1 legacy VME type e
61. nsert the new SODIMM until seated into the connector assuring it fits snugly into the connector retainer clips 0 Appendix A SDRAM and Battery Installation 8 Gently push the SODIMM down until the metal clips snap into place to hold it If you cannot gently push the SODIMM into position you may need to redo step 7 9 Replace the XVME 689 VR7 module reconnect all connectors etc 10 Power up the unit and make sure that the memory is recognized during boot up on the Boot time diagnostic screen that can be turned on in the BIOS see p Error Bookmark not defined Module Battery Installation During battery replacement polarity must be observed in installing the coin battery Please be sure to dispose of the spent battery in an environmentally correct manner The replacement battery must be a CR2032 or equivalent type EY Top ts marked positive y iy N Ka Side in or out EE IN A C 2 A V F E e ge SS A Pd m Bottom iz nagawa _ Index Abort toggle switch se se 4 6 Abort Clear CMOS register 2 3 backplane installing XVME 689VR7 2 18 BIOS menus IE AAA tente a 3 2 VMEbus menu Slave Interface submenus 3 26 System Controller submenu 3 24 block diagram sesse esse ese ee ee ee ee 1 6 byte swapping 2 5 4 7 4 9 4 10 Compact Flash drive 1 4 compliance VMEbus
62. of the bus Master interface which starts conversation on the bus Slave interface which responds to a bus master s question and the interrupt functions which uses seven 7 levels of interrupt control Note For your frame of reference the left side below is the XVME 689 VR7 board and the right side below is the VMEbus PCI memory slave access VMEbus master access PCI memory master access VMEbus slave access System Resources The XVME 689 VR7 automatically provides slot 1 system resource functions also referenced as SysCon if the Bus Grant 3 jumpers are set correctly on the VMEbus backplane The system resource functions are explained in the Universe manual Contact Tundra at www tundra com for a PDF version of the Universe manual This function can be disabled using the XVME 689 VR7 s jumper J3 See Jumper Settings in Chapter 2 p 2 2 VMEbus Master Interface The XVME 689 VR7 can be either a VMEbus master by accessing a PCI slave channel or the DMA channel initiates a transaction There are 8 PCI slave images The first PCI slave image has a 4K resolution the other have 64K resolution The master can generate A16 A24 A32 VMEbus cycles for each PCI slave image The address mode and type are also programmed on a PCI slave image basis The PCI memory address location for the VMEbus master cycle is specified by the Base and Bound address The VME address is calculated by adding the Base address to the Translation offset a
63. oke USB typematic is automatic and does not use this parameter Lowercase Hex Displays Enables the display of hexadecimal numbers in the debugger with lowercase letters instead of 3 21 BIOS Setup Menus uppercase letters ie 2f8ah instead of 2F8AH Proprietary Stimulation Enables System Monitor s callout to the OEM s BPM adaptation code to execute code that causes stimulation of the SMM environment for measurement purposes Hard Disk Read Stimulation Enables System Monitor s read of a preconfigured number of sectors from a location on the first hard disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first hard drive is configured in the BBS list as a USB hard drive Hard Disk Write Stimulation Enables System Monitor s write of a preconfigured number of sectors to a location on the first hard disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first hard drive is configured in the BBS list as a USB hard drive Please note that when this parameter is selected the system automatically enables reading so that the stimulation of the system includes reading a range of sectors into a memory buffer and writing the same data back to the same range of sectors for safety Thus this feature is theoretically nondestructive WARNING BECAUS
64. ow for up to five 5 PMC sites on one XVME 689 VR7 PCI X or PCI extended is an enhanced version of PCI Peripheral Component Interconnect computer bus Although PCI X is backward compatible with traditional PCI devices and systems this specification implements additional features and performance improvements include 3 3V signaling increased speed grades and adaptation to other form factors PCI X effectively doubles the speed and amount of data exchanged between the computer processor and peripherals PCI X bus was designed for and is ideally suited for server cards such as Fibre Channel RAID high speed networking and other demanding devices Onboard Memory SDRAM Memory The XVME 689 VR7 has a socket for a single 200 pin SODIMM providing 256 MB 512MB 1GB and 2GB of ECC DDR 266 333MHz SDRAM Approved SDRAM suppliers are listed in 0 Flash BIOS The XVME 689 VR7 system BIOS is contained in a 1MB flash device to facilitate system BIOS updates Contact Xembedded support for available updates at support xembedded com if needed Be sure to record your current version number and the reason for the request Video Controller Introduction The 855GME Graphics and Memory Controller Hub GMCH has a built in 2D 3D graphics controller The maximum video modes supported are listed in the following table The highest supported interlaced monitor mode is 1280x1024 16 bit 65k color and 43 Hz Video output is available on the front panel th
65. p Connectors This section provides pin outs for the XVME 689 VR7 connectors Refer to the EMC warning at the beginning of this manual before attaching cables Keyboard Mouse Port Connector P7 Keyboard Data Mouse Data GND 5V ea ow oo o ooo 6 MouseCiook 2 6 Installation and Setup Front panel P12 or Rear Ethernet Port and Vita 31 1 Ethernet The Ethernet ports on the XVME 689 VR7 are switch able between the front and the rear of the X VME 689 VR7 When in the rear mode the Ethernet port can use the PO connector for either Vita 31 1 switch fabric over the Vita 31 1 compliant backplane or Ethernet out the rear or the module Table 2 8 RJ 45 10 100 1000 BaseT Connector Pin out Figure 2 8 RJ 45 10 100 1000Mbps 2 7 Installation and Setup VGA Connector P9 The video is BIOS selectable and is available on either the front panel on a standard SVGA connector or out the VMEbus P2 The table below shows the pin out of the VMEbus P2 pin out for the rear access of video Figure 2 9 SVGA Connector Table 2 9 VGA Connector Pin out SVGA VMEbus P2 Pin out RED N C NIC N C 2 8 Installation and Setup USB Port Connector J5 USB provides an expandable hot pluggable Plug and Play serial interface that ensures a standard low cost connection for peripheral devices Devices suitable for USB range from simple input devices such as keyboards mice and joysticks to advanced devices such a
66. rding all changes except date time changes which take place on the fly TAB key Move the cursor down to the next configurable field Shift TAB key backtab Move the cursor up to the last configurable field key Toggle an Enable Disable field or increase a numeric field s value key Toggle an Enable Disable field or decrease a numeric field s value SPACE key Toggle an Enable Disable field BKSP key Reset an Enable Disable or multiple choice field or back up in numeric or string fields Digits 0 9 Used to enter numeric parameters Alphabetic A Z a z Used to enter text data on ASCII fields such as email addresses Special symbols amp _ etc Used to enter special text on ASCII fields that permit these characters The basic idea when using the Setup system is to navigate to the menus containing fields you want to review and change those fields as desired When your settings are complete navigate to the EXIT menu BIOS Setup Menus and select Save Settings and Restart This causes the settings to be stored in nonvolatile memory in the system and the system will reboot so that POST can configure itself with the new settings After rebooting it may be desirable to reenter the Setup system as necessary to adjust settings as necessary Once the system boots the Setup system cannot be entered this is because the memory used by the BIOS configuration manager is d
67. requires that this apparatus comply with relevant ITE EMC standards EMC compliance demands that this apparatus is installed within a VME enclosure designed to contain electromagnetic radiation and which will provide protection for the apparatus with regard to electromagnetic immunity This enclosure must be fully shielded An example of such an enclosure is a Schroff 7U EMC RFI VME System chassis which includes a front cover to complete the enclosure The connection of non shielded equipment interface cables to this equipment will invalidate European Free Trade Area EFTA EMC compliance and may result in electromagnetic interference and or susceptibility levels that are in violation of regulations which apply to the legal operation of this device It is the responsibility of the system integrator and or user to apply the following directions as well as those in the user manual which relate to installation and configuration All interface cables should be shielded both inside and outside of the VME enclosure Braid foil type shields are recommended for serial parallel and SCSI interface cables Where as external mouse cables are not generally shielded an internal mouse interface cable must either be shielded or looped 1 turn through a ferrite bead at the enclosure point of exit bulkhead connector External cable connectors must be metal with metal back shells and provide 360 degree protection about the interface wires The cable shield must b
68. rough a standard 15 pin D shell connector The graphics controller is in the 855GME which uses up to 64MB main memory as video memory The 855GME has a built in 3D graphics engine and its display render core frequency is up to 200MHz Table 1 1 Maximum Video Modes Supported Resolution Bit Depth Colors Vertical Refresh 640x480 24 bit 16M color 100 Hz 800x600 24 bit 16M color 100 Hz 1024x768 24 bit 16M color 100 Hz 1280x1024 24 bit 16M color 75 Hz 1600x1200 16 bit 65k color 60 Hz Ethernet Controller The 82546GB dual Giga bit Ethernet controller provides a pair of 10 100 1000baseT Ethernet interfaces The 82546GB contains both the MAC and the physical layer The RJ 45 connectors on the module s front panel provide auto sensing for 10Base T 100Base and 1000Base TX connections Each RJ 45 connector has two indicator lights When mounted vertically the top light is the link activity light and the bottom light the one closer to the COM ports is the 10Base T 100Base TX indicator When it is off the connection is 10Base T when it is on the connection is 100Base TX When the Ethernet is switched to the rear optional PO no lights are available to indicate link or speed Storage Devices Hard Drive Floppy Compact PCI and On Board Drive EIDE and Floppy Drives The XVME 689 VR7 primary IDE and floppy drive signals are routed through the P2 connector inner three rows available in a legacy 96 pin back plane
69. rrupt Example In the BIOS setup menu map the VMEbus IRQ 1 to PCI IRQ 11 VMEbus Interrupt Generation The XVME 689 VR7 can generate VMEbus interrupts on all 7 levels There is a unique STATUS ID associated with each level The upper bits are programmed in the STATUS ID register The lowest bit is cleared if the source of the interrupt is a software Interrupt and set for all other interrupt sources Consult the Universe Users Manual for a more in depth explanation VMEbus Reset Options When the front panel Reset switch is toggled the XVME 689 VR7 can perform the following reset options 1 Resetthe VME backplane only 2 Resetthe XVME 689 VR7 CPU only 3 Reset both 4 Reset neither See Switch Settings in section 3 of this manual for information on how to configure SW1 for the Reset options Software Selectable Byte Swapping Hardware The VMEbus can be used to communicate to either Intel based modules or a Motorola based modules these two companies have created data transaction that use different byte ordering in their data storage A hardware approach to swapping these byte orders is a faster solution when compared to a software only byte swapping method Software selectable byte swapping hardware is integrated into the XVME 689 VR7 to allow for the difference between the Intel and Motorola byte ordering schemes allowing easy communication over the VMEbus The byte swapping package incorporates several buffers either to pass
70. s printers scanners storage devices modems and video conferencing cameras USB 2 0 has a raw data rate at 480Mbps and it is rated 40 times faster than its predecessor interface USB 1 1 which tops at 12Mbps USB port 1 is available on the front panel using a standard connector as shown in Figure 2 10 below The other two USB ports USB 2 and 3 are routed out the VMEbus P2 connector and can be accesses either directly off the VMEbus P2 connector using the pin assignment shown in Fig 2 10 The USB 3 V supplies are protected with a polyswitch This device will open up if 5 V is shorted to GND Once the shorting condition is removed the polyswitch will allow current flow to resume Figure 2 10 USB Connector P2 row z 20 P2 row z 21 USB3 P2 row z 22 P2 row z 23 USB3_PWR P2 row z 24 P2 row z 25 USB2 GND P2 row z 26 P2 row z 27 USB2 P2 row z 28 Signal EE La ENIN TEM USBP0 Table 2 10 USB Port Connector Pin out Table 2 11 Rear USB ports 2 and 3 USB Port Connector Pin out on VMEbus P2 2 9 Installation and Setup COM 1 and COMA J4 Pin Definitions The XVME 689 VR7 has two serial ports out the front panel Com 1 and Com 4 these two com ports use the RJ 45 connector Two more com ports are out the VMEbus P2 connector See below for connector layout and pin descriptions Figure 2 11 RJ 45 Serial Port Connectors Com ports 1 and 4 Pin Definitions for front connectors Table 2 13 S
71. signs resources for the OS Disable this parameter when running non PnP OSes like DOS Enable this parameter when running PnP OSes like Windows95 Windows98 and WindowsNT IRQO Enable exclusive use of IRQO by PnP IRQI Enable exclusive use of IRQ1 by PnP IRQ2 Enable exclusive use of IRQ2 by PnP IRQ3 Enable exclusive use of IRQ3 by PnP IRQ4 Enable exclusive use of IRQ4 by PnP IRQ5 Enable exclusive use of IRQ5 by PnP IRQ6 Enable exclusive use of IRQ6 by PnP IRQ7 Enable exclusive use of IRQ7 by PnP IROS Enable exclusive use of IRQ8 by PnP IRQ9 Enable exclusive use of IRQ9 by PnP IRQ10 Enable exclusive use of IRQ10 by PnP IRQ11 Enable exclusive use of IRQ11 by PnP IRQ12 Enable exclusive use of IRQ12 by PnP IRQ13 Enable exclusive use of IRQ13 by PnP IRQ14 Enable exclusive use of IRQ14 by PnP IRQI5 Enable exclusive use of IRQ15 by PnP 3 14 BIOS Setup Menus 3 6 BIOS Super VO Configuration Menu The SIO menu is used to configure Super I O components on the XVME 689 VR7 689 These components commonly are serial and parallel port controllers to floppy disk and keyboard controllers The I O DMA and IRQ assignments of each peripheral are configurable so these values are also brought out to the SIO Setup menu Figure 3 6 shows the SIO Setup menu for the XVME 689 VR7 689 System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase BIOS Super I O Confi
72. st of drives that are scanned and assigned BIOS unit numbers for DOS 0 1 2 for floppy type devices and 80h 81h 83h and so on for hard drives If a drive on the list is not plugged in or working properly the BIOS moves on to the next drive skipping the inoperative device Second once the drives in the list have been verified POST attempts to boot from them in that order as well Drives without bootable partitions might be configured but skipped over in the boot phase so that other drives on the list become candidates for booting the OS BIOS Setup Menus This list can also contain other boot actions as boot from network ports When deciding what boot action to do first and then next in succession POST first scans all the drives in the list to verify they are present and operating properly as described earlier in this section and then goes down the list and tries to perform the actions in order During this boot phase if the list item is a drive an attempt is made to boot from the boot record of that drive If the list item is a device like a network PMC card an attempt is made to boot from that device If the list item is a non bootable device it moves on to the next item in the boot list The following table shows a list of boot devices and their configuration parameters BIOS Setup Menus Device Prioritization BBS Boot 0 Fixed USB 1 IDE 0 Pri 2 Floppy 0 3 None Floppy Drive Floppy 0 ID ID
73. system to move through POST and then reboot causing POST to be reexecuted over and over until Setup is reentered and this option is disabled When left unattended this is a straightforward way of having POST exercise system memory and peripherals without requiring a boot to a drive with an operating system installed The following table describes the settings associated with the POST setup menu s Device Initialization section POST Floppy Seek Enable head seek on each floppy drive configured in the system Used to recalibrate the drive in some systems with older DOS operating systems POST Hard Disk Seek Enable head seek on each hard drive configured in the system This is a way of extending the standard testing performed on each drive during POST by requesting that the drive actually move the head Not available with all drives 3 11 BIOS Setup Menus 3 5 Plug and Play Configuration Menu The PnP menu is used to configure Plug n Play a legacy BIOS initiative used to support operating systems such as Windows95 Windows98 and WindowsNT ACPI has largely replaced this feature however it is necessary for platforms to support older operating systems Figure 3 5 shows the PnP Setup menu 3 12 BIOS Setup Menus System Configuration Utility Main Exit Boot Post PnP SIO Features Firmbase Misc Plug n Play PnP Configuration Enable Plug n Play 1 0A specification Plug n Play Support Plug n Pla
74. the PS 2 port The keyboard and mouse are controlled in the SMC SCH3114 LPC Super I O PMC Expansion The XVME 689 VR7 provides an on board PMC site for use with standard 32 64 bit 33 66MHz PMC and PMC X modules The PMC site is serviced by the on board PCI X bus For electrical isolation the PMC front panel bezel is not connected to the main CPU ground PCI X or PCI extended is an enhanced version of PCI Peripheral Component Interconnect computer bus Although PCI X is backward compatible with traditional PCI devices and systems this specification implements additional features and performance improvements include 3 3V signaling increased speed grades and adaptation to other form factors PCI X effectively doubles the speed and amount of data exchanged between the computer processor and peripherals PCI X bus was designed for and is ideally suited for server cards such as FPGA DSP Fibre Channel RAID high speed networking and other demanding devices If a standard PCI PMC card is fitted on the XVME 689 VR7 PMC site the on board PCI X bus reverts to the PCI bus speed Additional PMC Expansion Options The XVME 689 VR7 supports optional PMC PCI Mezzanine Card expansion using XVME 976 209 expansion module The XVME 976 209 provides two PCI Mezzanine Card PMC sites The XVME 976 209 module is designed to plug directly into the XVME 689 VR7 using the 80 pin expansion board connector Another XVME 976 209 can be used to extend the XVME 689
75. us slave cycles must be allowed to be processed This becomes a problem when a Pentium cycle to the PCI slave image is in progress while a VMEbus slave cycle to the onboard DRAM is in progress The Pentium cycle will not give up the PCI bus and the VMEbus slave cycle will not give up the VMEbus thus the XVME 689 VR7 becomes deadlocked If the XVME 689 VR7 is to be used as a master and a slave at the same time the VMEbus master cycles must obtain the VMEbus prior to initiating VMEbus cycles All Slave interface cycles are byte swapped to maintain address coherency VMEbus Interrupt Handling The XVME 689 VR7 can service IRQ 7 1 A register in the Universe enables which interrupt levels will be serviced by the XVME 689 VR7 When a VMEbus IRQ is asserted the Universe requests the VMEbus and generates and IACK cycle Once the IACK cycle is complete a PCI bus interrupt is generated to allow the proper ISR Interrupt service routine to be executed The Universe connects to all 4 PCI bus interrupts These interrupts may be shared by other PCI bus devices The BIOS maps the PCI bus interrupts to the AT bus Interrupt controllers The AT bus interrupts must be uniquely mapped to each device Because the PCI devices share interrupt lines all ISR routines must be prepared to chain the interrupt vector to allow the other devices to be serviced 4 6 Rear Transition Module Note The 6300ESB allows multiple PCI bus Interrupts to be mapped to one AT bus inte
76. y SDRAM eee 1 9 P1 connector XVME 973 1 5 2 P3 connector XVME 973 1 5 6 P4 connector XVME 973 1 5 7 parallel port eee 1 5 POLO EE reete ie 1 5 PCI Ethernet controller enabling 2 20 pinouts CPU fan power eee 2 17 keyboard port 2 6 P1 connector XVME 973 1 5 2 P3 connector XVME 973 1 5 6 P4 connector XVME 973 1 5 7 PM EE EE eet Pe ELO SURE 2 16 Univeral Serial Bus USB 2 9 5 8 KA ditte ie ete EE INR 2 8 5 12 VMEbus DI 2 12 PMC ehm Ae e aTa 1 5 PMC connectors essen 2 16 ports keyboard em 1 5 parallel ze 1 5 EER NE EE HE edad 1 5 registers Abort Clear CMOS 2 3 Abort Clear CMOS register 2 3 Flash Paging and Byte Swap2 5 4 0 4 10 EBD BIOS nce netz 2 4 LED BIOS register 2 4 watchdog mer 2 4 reset options VMEbus 4 7 RJ 45 10 100 1000 Base T Connector 2 20 5 11 SDRAM inet eec ente 1 9 installation cem etm ee eite 1 Serial DOES alada diante 1 5 Software Support 1 6 specifications hardware metui 1 9 switch settings eee 2 3 system TesOurOeg eee eee eeeeeeeeeee 3 24 4 5 Universal Serial Bus USB port 2 9 5 8 Universe chip 4 5 4 7 4 8 4 9 4 10 Index VGA Connector iese esse sesse ee se
77. y OS ROs Reserved for Plug n Play RO RO RO RO RO RO RO RO RO RO RO 1 VO 0 H OU DU N HO A Channels Reserved for Plug n Play Jg D o H Disable A 1 Disable d d SARSA LSA RS Embedded BIOS 2000 v6 0 5 Copyright 2006 General Software Inc Figure 3 5 Plug n Play Configuration Menu 3 13 BIOS Setup Menus The PnP menu consists of two sections basic configuration that enables Plug n Play and identifies if a PnP should perform configuration or let the OS do it and then another section that defines which system IRQs should be reserved for PnP s use so that PCI doesn t use them The following table presents the fields in the PnP menu Plug n Play Enable PnP feature When disabled a PnP aware OS will not find any PnP services in the BIOS and all other configuration parameters in the menu will be greyed out Enable to support legacy OSes like DOS Windows95 Windows98 and WindowsNT Disable for operating systems like WindowsXP or Windows Vista or for Linux operating systems with ACPI support Plug n Play OS Enable delay of configuration of PnP hardware and option ROMs When enabled BIOS will NOT configure the devices and instead defer assignment of resources such as DMA I O memory and IRQs to the PnP OS When disabled the BIOS performs conflict detection and resolution and as

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