Getting Started Guide
Contents
1. vectors QeQO0U0000 WIDKINTIREA e EM AS DORZ SORAN ac OOOO OR INAN WIDIDOIDRER_ SA MEM DASTAG Py Add Seeticr Delete Section Data Sections Assign all Data Sectors to DORZ_SORAM_WIDIZH7ZABA SA MEM Section I Size bytes I Memory a DOR 2 2 SORAN WIDER St MEM BAS ton00000 reaeat QxOQ000000 ORZ IRAN WIDTEM7AROA SA MEM DAS 002 WONO ORE DRAN O00000 ANZ E SUNEN O00000000 AORZ SORAN WIOIIMTIREA_SA_MEM_BAS gt Reference Views read only Memories tee assess sce OPPFFORRO Gan ES DAW WIDOSaRDA SAMEM DASTADOR Ox00000000 2621440 Bout and Vector Sectors bostd Gar FFFFFOO beck OFFFFRFRC rate an Otga Urbar Script CrfDesagns PMC_V5 Programmable _FPGAPICSNEXTOT REONT PowerPC SEK SOK_WerkspxRFOOR_PowerPCjOOR Browse Compile your DDR2 main program DDR_PowerPC by selecting File gt Save in SDK The elf file generated must be converted to a binary file for download into DDR2 memory from the PCI bus or Flash memory Exit SDK by selecting File gt Exit Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 3 1 The following steps are needed to generate the binary file DDR Binary 1 Open a DOS command prompt dialog Start gt All Programs gt File Generation Accessories gt Command Prompt 2 Change directories to C Xilinx 11 1 EDK gnu powerpc eabi nt bin This is2. Code Sections Assign all Code Sections to X Section Size bytes Memory Reference Views read only text 0x000009C8 xps bram K cnti_t Memories Memory Address l Size xps_bram_if_entlr_1 OxFFFFOOOO 64K podsecioni i Peere acon DDR2_SDRAM_W1D32M72RBA_5A_MEM_BASEADDR 0x00000000 262144K Data Sections Assign all Data Sections to X Size bytes Memory 0x00000046 xos bram entk_1 bootO OxFFFFFFO0 xps_bram_if_cntlr_1 0x00000000 xos bram enti aboot OxFFFFFFFC xps_bram_if_cntlr_1 0x00000000 xos bram cntk_I OxO00000F8 xos bram A cn k_ I 0x00000000 xps bram K cntk_d 0x00000008 xos bram K enik i 0x00000000 xoz bram cntk_1 0x0000001C xps bram cntk_1 Boot and Vector Sections Select gt OK Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 O PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module Select File gt Save Saving the program compiles it and generates an elf file At this point you can test download the program to the board Setup Hyperterminal and connect the RS232 null modem cable from the EDK board to the RS232 of the Hyperterminal system From SDK Select Run gt Debug As gt Debug on Hardware If you receive the following Error message select OK and from SDK Select Run gt Debug As gt Debug on Hardware again aS Error amp Launch Failed Reason Error initializing XMD failed to c
3. gt Select XC5VFX70t_download bit Select gt Open Would you like to add another design file to Data Stream 0 Select gt No Select gt OK Select gt OK Double Select gt Generate File in the iMPACT Process section The file VFX70_revD mcs is generated and this new file can be downloaded over the PCI bus to configure the Virtex 5 device The Virtex 5 FPGA should be reconfigured with the new VFX70_revD mcs file As recommended earlier the Acromag software drivers should be used The Acromag software will simplify download of the mcs file and access of the system monitor registers for reading the temperature of the device The windows application PCIVFXDemo exe available with the PCISW API WIN software package can be used to download the new mcs file and test read of the board temperature Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 3 3 To build a program for download into DDR2 memory from the SDK the DDR Program following steps can be followed Creation Open Xilinx Platform Studio From the Xilinx Platform Studio select Project gt Export Hardware Design to SDK Set path to XC5VFX70T_RevD VFX70 PowerPC Select the Export amp Launch SDK Button Under File menu select New gt Managed Make C Application Project Enter DDR_PowerPC in the Project Name edit box Select Empty Application in the Sample Applica
4. 000000000 000000000 0xx00000000 000000000 9x00000000 OK Cancel Help Select gt OK In the MHS file the parameters C_SPLBO_RNG_MC_BASEADDR and C_SPLBO_RNG_MC_HIGHADDR have been set to the address range as set above Lines 72 and 73 of the mhs file should read as follow PARAMETER C_SPLBO_RNG_MC_BASEADDR 0x00000000 PARAMETER C_SPLBO_RNG_MC_HIGHADDR OxOFFFFFFF Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 2 1 The SPLBO still needs to be connected to the PLB bus In XPS with the Project tab selected and the Bus Interface tab selected select the circle next to the SPLBO to make the connection Xilinx Platform Studio C Designs PMC_V5 Programmable_FPGA XC5VFX70T_RevD WFX70 PowerPC PowerPC xmp System Assembly View DAR Edit Yiew Project Hardware Software Device Configuration Debug Simulation Window Help JA See xOOxX oo MH BABOR Olea S Bo AM wea iE k7 08x P a Bus Interfaces Ports Addresses Bus InterFace Filters L Name Bus Name IP Type TP Version IP Classifi By Connection es el Connected Project Files B ppc440_0 a tr ppc440_virt 1 01 a Processor Unconnected MHS ia PowerPC mhs MPLB plb_v46_0 v Standard M55 File PowerPC mss SPLBO No Connection PLBV46 UCF File data PowerPC ucf i DCR iMPACT Command File etc download cmd SPLB1 No Connection na Implementat
5. Status DDR SDRAM Address DDR SDRAM Read DDR SDRAM Write and DDR SDRAM Mask Registers These registers are implemented in the XC5VFX70T VHDL and are described in the PMC VFX User s Manual Also a user interface to the PLBV46 Slave Single core provides PowerPC read access of the Flash Program Code FIFO The XC5VFX70T VHDL code executes the move of the PowerPC program code data from flash memory starting at address sector 128 to the Flash Program Code FIFO The main functions coded in the PowerPC files include PowerPC Functions e 64Mx32 bit DDR2 Memory Controller The DDR2 SDRAM is directly accessible by the PowerPC A DDR2 Memory Controller for the PowerPC 440 Processor Xilinx core implements this interface between the PowerPC and the DDR memory The core is referenced as the PPC440MC core e 64K Byte Block RAM The bootloop program is executed out of this memory The bootloop program is preloaded in this Block RAM as part of the FPGA configuration file The bootloop program will automatically execute upon power up or reconfiguration e PLBV46 Master Single Core A user interface to the PLBV46 Master Single core provides a bi directional interface between the PCI bus and the DDR memory This core allows read and write of DDR SDRAM and Block RAM from the PCI bus The PCI bus is the master of this interface e PLBV46 Slave Single Core This core allows PowerPC read access of the Flash Program Code FIFO This core also handles PowerPC write a
6. Virtex 5 device Exit without saving E Close iMPACT cD Do you want to save configuration project file changes eg Select gt No To configure and run the Virtex 5 PMC VFX70 board it is recommended that the Acromag software drivers be used The Acromag software will simplify download of the mcs file and access of the system monitor registers for reading the temperature of the device This is a great way to verify initial functionality of the board For example the windows application PCIVFXDemo exe available with the PCISW API WIN software package can be used to download the new mcs file and test read of the board temperature The Xilinx JTAG cable will be used to download code to the PowerPC to test the PowerPC with the developed software Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 4 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module Open Xilinx Platform Studio Bootloop Program From the Xilinx Platform Studio select Generation Project gt Export Hardware Design to SDK Set path to XC5VFX70T_RevD VFX70 PowerPC Select the Export amp Launch SDK Button E Export to SDK Launch SDK 60x This dialog allows you to export hardware platform information to be used in Xilinx Software Development Kit Include bitstream and BMM file This project has been instantiated in Project Navigator Please copy the bitstream and lt design gt _bd bmm file Fr
7. follows Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 8 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module PCIVFX Main Menu 1 Example design demo instructions 2 Locate Choose board 3 Attach interrupt callback 4 Toggle PCI interrupts Disabled 5 Toggle FPGA interrupts Disabled 6 FPGA configuration 7 Copy PowerPC code file to flash 8 Flash commands 9 Dual Port SRAM menu 10 DMA transfers 11 Raw memory access 12 Display PCI configuration registers 13 View status information 14 Example design menu 99 Exit Enter selection 7 Select PowerPC code file 1 Example code file for VFX70 C Program Files Acromag PCISW_API_WIN config_files VWFX70_DDR bin 2 Other Enter selection 1 Writing file to flash This may take several minutes Complete 54192 code bytes written PCIVFX Main Menu Example design demo instructions Locate Choose board Attach interrupt callback Toggle PCI interrupts Disabled Toggle FPGA interrupts Disabled FPGA configuration Copy PowerPC code file to flash Flash commands Dual Port SRAM menu 10 DMA transfers 11 Raw memory access 12 Display PCI configuration registers 13 View status information 14 Example design menu 99 Exit Enter selection OMNOOARWD Now that the DDR2 program has been moved to flash the next power up cycle or reconfiguration will cause the program to be moved into DD
8. starting point 7 File gt New Project Project Name VFX70 Project Location Give path to VFX70 directory created C Designs PMC_V5 Programmable_FPGA XC5VFX70T_RevD Top Level source type HDL Select gt Next Enter the following Device Properties Product Category All Family Virtex5 Device XC5VFX70T Package FF1136 Speed Grade 1 Top Level Source Type HDL Synthesis Tool XST VHDL Verilog Simulator Modelsim XE VHDL Preferred Language VHDL Select gt Enable Enhanced Design Summary Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 0 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module Create New Source Dialog Opens Select gt Next no new source are needed Add Existing Sources Dialog Select Add Source button Browse to the directory location of the vhd and ucf files you moved in step 2 above gt Add Source gt XC5VFX70T vhd gt Open gt Add Source gt AXM_D vhd gt Open gt Add Source gt DIG_IO_8 vhd gt Open gt Add Source gt DP_SRAM vhd gt Open gt Add Source gt RearLVDS vhd gt Open gt Add Source gt v5_sysmon_v1_0 vhd gt Open gt Add Source gt XC5VFX70T Ucf gt Open They should not be copied to project since they already are stored in the project directory De Select the Copy to Project check box Select gt Next Select gt Finish gt Adding source files gt OK 8 In the Source in
9. 0000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt if readval amp 0x10000000 0x10000000 Almost Empty sprintf amp String 0 DDR Address x r n i iprint String DDRvalue readval amp OxFF lt lt 16 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt if readval amp 0x10000000 0x10000000 Almost Empty sprintf amp String 0 DDR Address x r n i print String DDRvalue readval amp OXxFF lt lt 8 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt if readval amp 0x10000000 0x10000000 Almost Empty sprintf amp String 0 DDR Address x r n i erint String 5 DDRvalue readval amp OxFF Write to DDR Memory pter unsigned int i pter DDRvalue The FIFO should not become full or empty sprintf amp String 0 Full Flag Count x r n FullCnt print String sprintf amp String 0 Empty Flag Count x r n EmptyCnt print String OXFFFFF038 is set with 0x33333333 if Flash code moved to DDR pter unsigned int OxFFFFF038 pter 0x33333333 sprintf amp String 0 Answer x r n CodeSize print String readval pter sprintf amp String 0 Answ
10. Acromag kd THE LEADER IN INDUSTRIAL I O Series PMC VFX70 Virtex 5 Based FPGA PMC Module Getting Started Guide Ni he he hi i EI XILINX n VIRTEX S f XC5VFX70T FF11361GU0813 DD1500903A ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice Tel 248 295 0310 Fax 248 624 9234 8500 827 D09F009 2 PMC VFX Getting Started Guide Virtex 5 Based FPGA PM TABLE OF CONTENTS The information of this manual may change without notice Acromag makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring C Module component sensor or software failure in the design of any type of control or monitoring system This is very important wher
11. PLB port where the PPC440 is the master is aware of the External Memory connections to DDR The SPLBO 1 ports require the MEMCON address ranges to be set to allow PLBV46 Master Single IP to have access to DDR Memory Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 20 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module In XPS with Project tab and the Bus Interface tab selected right mouse select on ppc440_0 and select Configure IP The ppc440_0 ppc440_virtex5_v1_01_a dialog opens Set the base address to 0x00000000 and High Addr to OFFFFFFF for the SPLBO MemCon Range gt ppc440_0 ppc440_virtex5_v1_01_a Addresses Cache BusFeatures DMA Reset APU Memory Controller Misc B gt HDL Toggle PowerpPt MemCon Base Address of Memory High Address of Memory DCR Internal DCR Register Base Address 0b0000000000 Internal DCR Register High Address 0b0011111111 SPLBO Allow SPLBO to Access MPLB Addr Oo Number of MPLB Addr Ranges 0 MemCon Range MPLB Rangel MPLB Rangel MPLB Range2 MPLB Range3 Base Addr 0x00000000 Oxffffffff Oxffffffff Oxffffffff Oxffffffff High Addr Ox0fffffff 0x00000000 0x00000000 0x00000000 0x00000000 SPLB1 a Allow SPLB1 to Access MPLB Addr o Number of MPLB Address Ranges 0 MemCon Range MPLB Rangel MPLB Rangel MPLB Range2 MPLB Range3 Base Addr oxffffffEE loxereecere loxerescere oxfffffffE loxereceeee High Addr
12. Project Dialog Window select XC5VFX70T XC5VFX70T_arch XC5VFX70T vhd so that it is hi lighted 9 Add the processor subsystem as a module in the ISE tool Select Project gt New Source and then Embedded Processor from the resulting list Enter the file name PowerPC 5 New Source Wizard Select Source Type Select source type file name and its location fq BMM File ChipScope Definition and Connection File Pr Implementation Constraints File JP CORE Generator amp Architecture Wizard Schematic File name User Document Verilog Module m Verilog Test Fixture Location la IEDU Mode VS Programmable_FPGA XCSVFX70T_RevD vFx70 A VHDL Library l P VHDL Package fa VHDL Test Bench W Embedded Processor PowerPc Add to project Select gt Next Select gt Finish Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 1 1 This will add an xmp file to the design and launch XPS In the future clicking on it will launch XPS Xilinx Platform Studio In XPS you can Xilinx Platform Studio build the processor system Exiting XPS leaves you back in ISE and you Base System Builder can add your other existing modules to the ISE project just as you would have previously when there was no embedded processor w Platform Studio 2 This project appears to be a blank project Do you want t
13. R2 memory and executed Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com
14. ache C Data Cache Data Cache Size 32 KB D32M72R8A_5A xps_bram_if_cntlr_1 xps_bram_if_cntlr_1 Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module The Application Configuration Dialog opens Keep all the setting shown Base System Builder System Processor Peripheral Application Configuration Configure the example applications Example Applications Application Option Value Standard IO R5232 Boot Memory xps_bram_if_cntlr_1 Memory Test TestApp_Memory_ppc440_0 Instructions xps_bram_if_cntlr_1 Data xps_bram_if_cnitlr_1 Interrupt Vector No Interrupt Peripheral Test TestApp_Peripheral_ppc440_0 Instructions DDR2_SDRAM_W1D32M72R84_54 Data DDR2_SDRAM_W1D32M72R84_54 Interrupt Vector No Interrupt Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module The Summary Dialog opens Review the summary of project setting shown in this dialog Notice the PowerPC base address assigned to the Block RAM UARTs and DDR2 memory and pcibusif Base System Builder Welcome Board System Processor Peripheral Cache Application Summary ee ee eee Summary Below is the summary of the system yo
15. ard System Processor Peripheral Cache Application eo System Configuration Configure your system Single Processor System Dual Processor System Select this option to create a design with a single processor This Select this option to create a design with two processors This Wizard Wizard will let you configure the processor the peripheral set and will let you configure the types of the processors the peripherals some major configuration parameters for the peripherals accessible to the two processors and the peripherals shared by the two processors Processor 1 Peripherals Shared Peripherals Mailbox Mutex Processor 2 Peripherals DDR EMAC Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual The Processor Configuration Dialog opens Keep all the setting shown Base System Builder Welcome Board System Processor Peripheral Cache Virtex 5 Based FPGA PMC Module 1 3 Application Processor Configuration Configure the processor s Reference Clock Frequency 200 00 Processor 1 Configuration Processor Type PowerPC Processor Clock Frequency 125 00 Bus Clock Frequency 125 00 Debug Interface C Enable Floating Point Unit FPGA JTAG Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 4 PMC VFX Getting St
16. arted Guide Virtex 5 Based FPGA PMC Module The Peripheral Configuration Dialog opens Change the Memory Size for the Block RAM to 64K as seen below Base System Builder Welcome Board System Processor Peripheral Cache Application Peripheral Configuration To add a peripheral drag it From the Available Peripherals to the processor peripheral list To change a core parameter expand the core Available Peripherals Processor 1 PowerPC 440 Peripherals Peripheral Names Core Parameter 10 Devices DDR2_SDRAM_W1D32M72R84_5A Internal Peripherals Core ppe440me_ddr2 xps_bram_if_cntlr R5232 xps_timebase_wdt Core xps_uartlite Baud Rate 9600 Data Bits 8 xps_timer RS232_1 Core xps_uartlite Baud Rate 9600 Data Bits 8 pcibusif_O Core pcibusif xps_bram_if_cntlr_ Add gt Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 1 5 The Cache Configuration Dialog opens Keep all the setting shown Base System Builder Welcome Board System Processor Peripheral Application Cache Configuration Select cache size and cache memory for processor s Processor 1 PowerPC 440 Cache The PowerPC embedded in the VirtexSFX series of FPGAs provides 32K of caches Caches are enabled in software and can be configured to cache multiple memory regions Instruction C
17. ccess to the PowerPC_Read_Reg The PowerPC_Read_Reg can be read by the PCI bus at PCI bus BAR2 address plus 0x8070 e UART1 This first UART is used to interface to a dumb terminal for program output display e UART2 This second UART is provided for additional program debug and development Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module Bootloop Overview The reprogrammable FPGA example design will run a bootloop out of the 64K Byte Block RAM after power up or direct reconfiguration The bootloop program will print Hello World From Block RAM and then reads DDR program code from the Flash Program Code FIFO read port and writes itto DDR memory The PowerPC reads the Flash Program Code FIFO read port via PowerPC address OxFFFE8000 After the data is moved into DDR memory the bootloop program will write the Block RAM address OxFFFFFO038 with value 0x33333333 This 0x33333333 value indicates that the DDR program code has been moved to DDR memory Next the bootloop program will set Block RAM address OxFFFFF030 to Ox33AA33AA to indicate that it has jumped to address 0x0 in DDR memory to start execution of the DDR resident program The DDR resident example program provided in file VFX70_DDR bin prints Hello World From DDR in a sine wave pattern After eight sine waves are printed the DDR program completes by writing 0x5A5A5A5A
18. e prope loss or human life is involved It is important that you perform rty satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Overview FPGA Fabric Functions 2 scccssseessseeesseereeees PowerPC Functions cc0 nennen eee cee cee eee eee eeeees Bootloop OVEIrVieW c cecceceeceeeeeeeeeeeeaeeeeeeneeeees DDR Program OVerview cccccceeesesteeeeeeeeeeeeeneees DDR Program Download cececseeeeeeeeeeeeeeeenees DDR Program Execution ccececseeeeeeeeeeeeeeeenes Development Hardware ccsceceeeeeeeeeeeeeeeeeees 2 0 Example Design Creation New Project Creation ccsccceceeeeeeeeeeeeeeeeneees Xilinx Platform Studio Base System Builder PowerPC MHS File 2 cesceceeeeeeeeeeeeeeeeeeeeeeeeees Compile Design In ISE cceeseeeeeeeeeeeeeeee eee Bootloop Program Generation 0 ceeeee Bootloop Program cecceceeeeeeeeeeeeeeeeeeeeeeeeeees Build Bootloop Program Into Configuration File DDR Program Creation 0ccscssesseeeeeeeseeeeeeees DDR PowerPC Program s s esceseeeeeeeeeeeeeensees DDR Binary File Generation 0 csseeeeeeeeees ONDODOOF PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 3 If you have problems you should visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date pr
19. er x r n readval print String Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 29 Set the pointer address to the Block RAM location used to check for 0x33AA33AA which indicates that DDR2 memory is loaded with program code and the bootloop program can now jump to execute DDR2 program code pter unsigned int OxFFFFF030 poter 0x33AA33AA print Exiting main r n dF print n Jump to DDR resident program in DDR memory at address 0x0 func_ptr 0x1d0 func_ptr return 0 Edit the Linker Script of the program to make sure it will run properly in hardware from block RAM Right select on BootloopPowerPC Select Generate Linker Script In the Linker Script Generator dialog Find Assign all Code section to and select xps_bram_if_cntlr_1 with the down arrow Find Assign all Data section to and select xps_bram_if_cntlr_1 with the down arrow Also assign the heap and stack sections to block RAM Select gt Generate Linker Script Generator Generate Linker Script Configure and generate linker script He id Stack Application project name BootloopPowerPC stall tess Section Size bytes Memory ELF file used to populate section info Heap 0x1000 xps bram ontk_i Stack 0x1000 xpz bram _ cntk_1 BootloopPowerPC Debug BootloopPowerPC elf
20. g BaatloopPowerPC elF The ELF file is assumed to be generated outside XPS Default ELF name is lt sw project name gt executable elf Select gt OK In XPS under the Applications Tab find the Project BootLoop Use the right mouse button to select BootLoop and then select Mark to initialize BRAM Exit from XPS This takes you back to ISE In ISE find the Processes Dialog Window and select Update Bitstream with Processor Data Run the Update Bitstream with Processor Data by selecting Process gt run This generates a new bit file called XC5VFX70T_download bit Use this new bit file to generate the PROM MSC file This process puts the BootloopPowerPC bootloop program in Block RAM In the Processes Dialog Window under Configure Target Device select Generate PROM ACE File so that it is highlighted Build Bootloop Into Configuration File Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 2 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module Process gt Rerun Select gt OK to warning Step 1 select Generic Parallel PROM Select the Green Arrow Parallel PROM Bytes Select 4M Select Add Storage Device button Select the next Green Arrow Step 3 File Name enter VFX70_revD Enter the File Location to your file Leave the other default settings Select gt OK Start adding device file to Data Stream 0 Select gt OK Add Device
21. hd file This was done as follows e Select PowerPC in the ISE source tab e Inthe processes tab double select View HDL Instantiation Template e Copy and paste the provided text into the xc5vfx70t vhd and connect the ports correctly The XPS will become a submodule in the ISE project The xc5vfx70t vhd file as provided in the EDK already contains the PowerPC component Declaration The component declaration can be found at lines 407 to 453 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 2 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module The PowerPC instantiation can be found in the xc5vfx70t vhd file at lines 873 to 917 In the Processes For Source Dialog Window select Synthesize XST so that it is highlighted Run the compiler by selecting Process gt run In the Processes For Source Dialog Window select Implement Design so that it is highlighted Run the compiler by selecting Process gt run In the Processes For Source Dialog Window select Generate Programming File so that it is highlighted Process gt Properties Then select Startup Options tab FPGA Start Up Clock CCLK Enable Internal Done Pipe Do not Check Done Output Events 6 Enable Outputs Output Events 5 Release Write Enable Release DLL Default Match Cycle Auto Drive Done Pin High Check gt OK Process gt Properties Then select Configurations Options tab Co
22. hile count gt 0 print 3 wy print Hello World From DDR2 r n Set Block RAM address OxFFFFF034 with Ox5A5A5A5A to indicate end of DDR memory program pter unsigned int OxFFFFF034 oter Ox5A5A5A5A print Exiting DDR main r n print An Jump back to bootloop program func_ptr OxFFFFOO0O0O func_ptr return 0 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 6 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module Edit the Linker Script of the program to make sure it will run properly in hardware from DDR memory Right select on DDR_PowerPC ppc440_0_software_platfrom Select Generate Linker Script In the Linker Script Generator dialog assign all Code section to Select DDR2_SDRAM_W1D32M72R8A_5A_C_MEM_BASEADDR assign all Data section to Select DDR2_SDRAM_W1D32M72R8A_5A_C_MEM_BASEADDR assign all Heap and Stack section to Select DDR2_SDRAM_W1D32M72R8A_5A_C_MEM_BASEADDR Select gt Generate T Linker Script Generator Generate Linker Script Configure and generate inher serge Agglcabon project name DOR PowerPc beanie ceel Heo Orso I Rok Orso Mimo ELF fle used to populate section fo CORZ_SORAM_WIDTENTEROA_SA_ MEM BASEACOR DORZ_SORAM_WIDTIMTIREA_SA_MEM_BASEAGOR Code Sections Asean al Code Sections to 0082 soram wioszmrzrna_sa mem w i sea ET Memory
23. ion Options File etc Fast_ru PPC440MC ppc440_0_PPC 4 Xilinx Point To Point Bitgen Options File etc bitgen ut MDCR No Connection _ face Type Project Options SDCR No Connection wv Slav ee Device xcSvFx7OtFF1136 1 MFCB No Connection Netlist SubModule MFCM DOC340_0_ MECM Implementation XPS xFlow JTAGPPC 440 0 jt ppc440_0_jta HDL vhdl ee Sim Model BEHAVIORAL RESETPPC ppc reset bus i Design Summary pib_v46_0 Yr plb_v46 PLBV46 DDOR2_SDRA ppc440mc_d Memor xps bram _ r xps_bram_if Memor xps_bram_i wir bram_block Memory Jtagopc_cnthe jtagppc_cntlr Periphe pcibusit_O r pcibusif Periphe KIK By Bi fe a Masters Master Slaves Monitors Targets Tnitiators EaIKSKSIKSKSIKS Fa KKK oe Select this SPLBO Circle SPLB plb_v46_0 v MPLB pib_v46_0 vi proc_sys_res proc_sys_re Periphe RS232 xps_uartlite Periphe RS252_4 xps_uartlite Periphe clock_genera clock_gener IP Legend O Master O Slave Master Slave Target lt Initiator O Connected Q Unconnected amp System Assembly View amp Block Diagram i Design Summary Project Applications IP Catalog Console Warnings Errors anal File gt Save Project File gt Exit Compile Design In The Xilinx Platform Studio XPS project has already been instantiated in the ISE xc5vfx70t v
24. le f RTEX a 5 In this section an overview of the PMC VFX is presented and the Acromag example design that the PMC VFX executes is also described The provided PMC VFX example design can serve as the launching point from which your custom design can be developed The first step is to become familiar with the provided example design af id of ht Hh he DDR2 DDR2 64Mx16 64Mx16 ee SS Fi UART Memory _ Rear I O 4 T mijan gt 256KR36 i PLB Ea Mast cro Sbar gy nove i SRAM 40V LAT PowerPC i a ed 64KByte Master gxue A reied ia gt 3 hz an SRAM 256Kx36 gt The PMC VFX comes preprogrammed with the example design This program is stored in a 32Mx8 Flash memory The 32Mx8 flash memory is a 256 sector memory with the first 128 sectors allocated for storage of the reprogrammable FPGA program code The second 128 sectors are allocated for storage of PowerPC code and data The PMC VFX comes preprogrammed with both FPGA program code and PowerPC program code The reprogrammable FPGA code is defined by both VHDL files and PowerPC files All VHDL and Xilinx PowerPC files used to define the example design are provided in the Engineering Design Kit EDK The main functions controlled by the VHDL include e Local Bus Interface This VHDL logic provides an interface to a second smaller Virtex 5 FPGA that handles the PCI X bus interface The local bus interface performs with the reprogrammable FPGA ac
25. linx PMC VFX project was performed using 2 0 Example Design the Xilinx ISE Design Suite 11 1 with no service pack A great deal can be c ti learned about how the Xilinx ISE XPS Xilinx Platform Studio and SDK reation tools are used to develop a custom application by performing the following project creation procedures The files provided in the EDK include the completed project executed in the example design The steps given in the following pages will allow one to incrementally develop the project 1 Make a new directory on your computer XC5VFX70T_RevD or copy N Project the directory structure provided on the EDK CD ew Fors C Designs PMC_V5 Programmable_FPGA XC5VFX70T_RevD Creation 2 Copy the following files AXM_D vhd DIG_IO_8 vhd DP_SRAM vhd RearLVDS vhd v5_sysmon_v1_0 vhd XC5VFX70T vhd and XC5VFX70T Ucf from the CD ROM to the new directory XC5VFX70T_RevD 3 Copy the PMC_VFX70_v2_2_0 xbd and ucf files from the EDK CD ROM board Acromag boards PMC_VFX70 data folder to xilinx 1 1 1 EDK board Acromag boards PMC_ VFX70 data folder 4 Copy the pcores folder provided in the EDK CD ROM edk_user_repository MyProcessorIPLib folder to Xilinx 11 1 edk_user_repository MyProcessorIPLib folder 5 Start the software by selecting Start gt Programs gt Xilinx ISE 11 1 gt ISE gt Project Navigator 6 Tocreate a new project the following steps can be taken Alternatively the project provided on the CD ROM can serve as a
26. mple design DDR resident program DDR_PowerPC prints Hello World From DDR in a sine wave pattern After eight sine wave cycles are printed the DDR program completes by writing OxSA5A5A5A to Block RAM address OxFFFFF034 Lastly the DDR program jumps back to the bootloop program The bootloop program checks Block RAM address OxFFFFFO34 for the value 0x5A5A5A5A and if found stays in an infinite while loop Exit of the while loop and re execution of the DDR program is possible by writing 0x0 to Block RAM address OxFFFFF034 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 3 5 Cut and paste the following DDR_PowerPC program into main c DDR PowerPC Program DDR_PowerPC Welcome to Xilinx Platform Studio SDK include xparameters h include stdio h include xutil h include xstatus h include xbasic_types h include xio h include xio_dcr h int main char String 80 unsigned int pter Xuint32 address_Main address_Main main extern double sin double temp int count int func_ptr sprintf amp String 0 Answer x r n address Main print String Set Block RAM address OxFFFFF034 with 0x0 to indicate started DDR memory program pter unsigned int OxFFFFF034 pter 0x0 for temp 0 0 temp lt 50 0 temp t 25 count int 30 28 sin temp w
27. nfiguration Rate 2 Configuration Pin MO Pull Down All other settings remain unchanged gt OK Run the Generate Programming File by selecting Process gt run After the design compiles without errors a new program file can be generated In the Processes For Source Dialog Window select Under Configure Target Device select Generate Target PROM ACE File so that it is highlighted Process gt Run In the ISE iMPACT dialog select PROM File Formatter from under the iMPACT Flows section Step 1 Select Generic Parallel PROM and then select the Green Arrow Parallel PROM Bytes set to 4M and then select Add Storage Device Then Select the second Green Arrow Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 23 Leave the Checksum Fill Value gt FF File Nave gt VFX70 File Location gt XC5VFX70T_RevD VFX70 File Format gt MCS Loading Direction gt UP Number of Data Streams gt 1 Data Stream 0 Start Address gt 0 Add Data Files gt No Select gt OK Start adding device file to Data Stream 0 Select gt OK Add Device gt Select XC5VFX70T bit Select gt Open Would you like to add another design file to Data Stream 0 Select gt No Select gt OK Select gt Operations gt Generate File The file VFX70 mcs is generated and this file will next be downloaded over the PCI bus to configure the
28. o create a Base System using the BSB Wizard Select gt Yes Welcome to the Base System Builder Dialog opens Select I would like to create a new design Select gt Next The Board Selection Dialog opens Select the down arrow of the Board Vendor and select Acromag Base System Builder System Processor Peripheral Cache Application Board Selection Select a target development board Board I would like to create a system for the Following development board Bard Vendor Board Name virtex 5 Acromag PMC FX70 Board Revision fa I would like to create a system for a custom board Board Information Architecture De Package E Speed Grade virtex5 xc5vfx70t ff1136 1 Use Stepping Reset Polarity Active Low Related Information Vendor s Website vendor s Contact Information Third Party Board Definition Files Download Website The Acromag Virtex 5 PMC VFX board uses the XCSYFX70T FF1136 device as a user programmable FPGA The board includes 256MB DDR2 SDRAM Memory 2MB SRAM 32MB of Commodity Flash front and rear I O ports and 2 R5232 serial ports Select gt Next Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 2 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module The System Configuration Dialog opens Select Single Processor System Base System Builder Welcome Bo
29. oduct and software information Choose the Support hyperlink in our website s top navigation row then select Embedded Board Products Support or go to http www acromag com subb_support cfm to access Application Notes Frequently Asked Questions FAQ s Knowledge Base Tutorials Software Updates Drivers An email question can be submitted from within the Knowledge Base or through the Contact Us hyperlink at the top of any web page Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed at the bottom of this page When needed complete repair services are also available The following manuals and part specifications provide the necessary information for in depth understanding of the board Virtex 5 Documentation http www xilinx com IDT70T3519S Spec http www idt com MT47H64M16HR Spec http Awww micron com CY23EP05 Specification http www cypress com WHERE TO GET HELP www acromag com CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS RELATED PUBLICATIONS Trademarks are the property of their respective owners Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module 1 0 GENERAL OVERVIEW Front AXM I O Connector FPGA Fabric Functions Slave 440 my Single FIFO BRAM Sing
30. of the PowerPC mhs file replace clk _200_O000MHz with dcm_clk_s The new line 218 should look like the following PORT mi_mcclk_200 dcm_clk_s Find the BEGIN clock_generator section and comment out lines250 to 253 and also line 263 A line is commented out by placing the sign at the beginning of the line Lines 250 to 253 and 263 should look like the following PARAMETER C_CLKOUT3_FREQ 200000000 PARAMETER C_CLKOUT3_BUF TRUE PARAMETER C_CLKOUT3_PHASE 0 PARAMETER C_CLKOUT3_GROUP PLLO_ADJUST PORT CLKOUTS3 clk_200_0000MHz Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 1 Q The PCIBUSIF needs to be added to the bus interface as seen in the Bus Interface tab Notice in the PLB bus interface view the box is not filled in This means that the pcibusif_0 has not yet been connected to the PLB bus Select the box next to MPLB and it will be connected to the PLB bus Xilinx Platform Studio C Designs PMC_V5 Programmable_FPGA XC5VFX70T_RevD WFX70 PowerPC PowerPC xmp System Assembly View amp File Edit view Project Hardware Software Device Configuration Debug Simulation Window Help De aea Be eo x e MAABARA n A Wie N K x Project 08x P a Bus Interfaces Ports Addresses Bus Interface Filters Platform L Name Bus Name IP Type IP Version IP Classifil By Connection Connected Project File
31. om Project Navigator directory to the location below Directory location For hardware description files Programmable_FPGA XCSVFX70T_RevD VFX70 PowerPC Export Only Export amp Launch SDK Next Steps i Now that you have a hardware design you can start creating software projects for it Before you can create C or C application projects you have to first create Software Platform projects To create a Software Platform project click on the New icon below the File menu and select Software Platform For tutorials on how to get started with Xilinx Software Development Kit select Help gt Cheat Sheets For SDK on line documentation select Help gt Help Contents or the SDK icon in the Welcome page I Do not show this message again Select gt OK Under the File menu Select gt Software Platform Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 2 5 T New Software Platform Project Create a Software Platform Project Create a Software Platform project Project name ppc 40_0_sw_platform Processor ppc440_0 ppc440_virtex5 Platform Type standalone Standalone is a simple low level software platform It provides access to basic processor Features such as caches interrupts and exceptions as well as the basic features of a hosted environment such as standard input and output profiling abor
32. onnect to remote target Error ERROR Unable to STOP PowerPC Processor Check 1 If the FPGA is Configured Correctly or 2 If Processor Reset and Clock Ports are Connected Correctly In the debug perspective click on the resume button or select run gt resume Terminate Exit SDK Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 3 1 You will need to add the BootloopPowerPC elf as a software application in XPS In XPS you must mark the Block RAM for initialization and in ISE you will be able to update the bitstream with this elf only application In XPS under the applications tab right click on the Add Software Application Project In the Add Software Application Project dialog that comes up enter the following Enter the Project Name as BootLoop Select box next to Project is an ELF only Project Then browse to the BootloopPowerPC elf file Choose Executable filename to save to A C Designs PMC_V5 Programmable_FPGA XCSYFX70T_RevD WFX70 PowerPC SDK SDK_Workspace BootloopPowerPC Debug BootloopPowerPC elF already exists Do you want to replace it Select gt Yes Add Software Application Project Project Name BootLoop Note Project Name cannot have spaces Processor ppc440_0 Project is an ELF only Project Choose an ELF file NFX70 PowerPC SDK SDK_Workspace BootloopPowerPC Debu
33. s ppc440_ 0 ppc440_virt 1 01 a Processor rl bat v Unconnected MHS mier PowerPC mhs pih_v46_0 ir plb_v46 1 04 4 PLBV46 By Bus Standard HR Aged DORZ_SDRA tir ppc440me_d 2 00 8 Memor PLBY46 UCF File data PowerPC ucf ri xr evi suas M Iv DCR iMPACT Command File etc download cmd MALONE iin nee FCB Implementation Options File etc fast_ru xoz bram K Ye bram_block 1 00 a Memory Xilinx Point To Point Jtagopc_cnth r itagppc_entlr 2 01 c Periphe Bitgen Options File etc bitgen ut ps Interface T Project Options pobusi 0 r pcibusif 1 00 a Periphe oo A ae Device xcSvFx7OtfF1136 1 SPLB plb_v46_0 v Macters Netlist SubModule MPLB No Connection Master Slaves Inelementation XPS xflow proc syz res pid proc_sys_re Periphe Monitors Sim Model BEHAVIORAL H R5232 xps_uartite Periphe rose Design Summary R5232_1 r xps_uartlite Periphe clock_genera clock_gener IP 1 3 Oe eae MPLB Box Legend O Master Slave Master Slave Target lt Initiator Connected Unconnected Project Applications IP Catalog A System Assembly View D Block Diagram 2 Design Summary Console Warnings Errors Sonnan A PLBV46 Master Single custom IP is used to implement an External Master of the PCI bus The use of the PLBV46 Master Single IP connects to the crossbar using a SPLBO 1 interface Currently only the M
34. t and exit Project Location MV Use default asses Under Project Name enter ppc440_0_sw_platform Keep the rest of the dialog defaults Select gt Finish Under File menu select New gt Managed Make C Application Project Enter BootloopPowerPC in the Project Name edit box Select Empty Application in the Sample Application section Select gt Finish With BootloopPowerPC ppc440_0_sw_platform highlighted selected Under File menu select New gt Source File In the Source File edit box enter main c Select gt Finish In the Editor view edit the default program main c and save it This creates a bootloop program in SDK as an elf application The program listed on the following pages can be cut and pasted into the new main c file Select File gt Save Saving the program compiles it and generates an elf file Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 26 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module In the Editor view edit the default program main c and save it This BootLoop creates a bootloop program in SDK as an elf application The program Program listed on the following pages can be cut and pasted into the new main c file Select File gt Save Saving the program compiles it and generates an elf file BootloopPowerPC bootloop program include xparameters h include stdio h include xutil h include xstatus h incl
35. ter3 DDRvalue readval amp OxFF lt lt 24 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt while readval amp 0x40000000 0x40000000 Empty FIFO readval pter3 DDRvalue readval amp OxFF lt lt 16 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt while readval amp 0x40000000 0x40000000 Empty FIFO readval pter3 DDRvalue readval amp OxFF lt lt 8 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt while readval amp 0x40000000 0x40000000 Empty FIFO readval pter3 DDRvalue readval amp OxFF CodeSize DDRvalue for i 0 i lt CodeSize i i 4 DDRvalue 0 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt if readval amp 0x10000000 0x10000000 Almost Empty sprintf amp String 0 DDR Address x r n i f erint String DDRvalue readval amp OxFF lt lt 24 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 8 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module readval pter3 if readval amp 0x8
36. the location of the Xilinx executable powerpc eabi objcopy You may also need to find and move cygwin1 dll to this directory 3 Copy the DDR_PowerPC elf file to C Xilinx 1 1 1 EDK gnu powerpc eabi nt bin The DDR_PowerPC elf can be found at XC5VFX70T_RevD VFX70 PowerPC SDK SDK_Workspace DDR _PowerPC Debug cx Command Prompt iC Rilinx 11 1 EDK gnu powerpce eabi nt bin gt powerpce eabi objcopy 0 binary j tex t j init j fini j rodata j data j got j goti j got2 j ctors j dtors j ieh_frame j gt j gcc_except_table j sdata j shss j tdata j thss DDR_PowerP jcr C elf UFKX76_DDR bin C 8ilinx 11 1 EDK gnu powerpce eabi nt bin gt 4 Type or cut and paste the following at the dos command line powerpc eabi objcopy O binary j text j init j fini j rodata j data j got j got1 j got2 j ctors j dtors j eh_frame j jcr j gcc_except_table j sdata j sbss j tdata j toss DDR_PowerPC elf VFX70_DDR bin 5 The VFX70_DDR bin file generated is used to download into DDR2 memory from either the PCI bus or flash memory 6 See your PMC VFX driver software requirements for the location to which the VFX70_DDR bin file must be moved For example the PC software requires this file to be stored at C Program Files Acromag PCISW_API_WIN config_files The PCIVFXDemo exe provided with PCISW_API_WIN can be used to download the VFX70_DDR bin file into flash starting at sector 128 as
37. ting as a slave and the PCI X bus FPGA acting as the master The local bus interface has a 32 bit data bus address lines 21 to 2 four byte strobe signals and five additional control signals Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 5 e Dual Port SRAM interface DP_SRAM Component A 256K x 64 bit synchronous dual port SRAM memory is provided One port interfaces to the PCI bus and the other port is directly connected to the reprogrammable FPGA This memory supports DMA transfers when requested by the system or the reprogrammable FPGA e Front I O Interface AXM_D Component An interface to front of panal I O mezzanine modules of various I O standards is provided by way of a 150 pin high speed connector The interface includes 31 differential signal pairs 29 control signals 2 clock signals and 53 power and ground signals e Rear I O Interface RearLVDS Component The reprogrammable FPGA is directly connected to 64 pins of the rear P4 connector The reprogrammable FPGA I O to these signals is powered by 2 5 volts and can perform any 2 5volt standard FPGA I O e PowerPC Interface PowerPC Component and XC5VFX70T VHDL Access to the DDR SDRAM and Block RAM address space from the PCI bus is performed by way of the PLBV46 Master Single core The PCI bus transfer of data is implemented using the following registers DDR SDRAM Control
38. tion section Select gt Finish With DDR_PowerPC ppc440_0_sw_platform highlighted selected Under File menu select New gt Source File In the Source File edit box enter main c Select gt Finish From SDK right mouse select the Project name DDR_PowerPC ppc440_0_sw_platform from the c c Project panel on the left Select properties Select C C Build in the left banner Select the Tool Settings tab Select Miscellaneous under the PowerPC C Compiler Enter nostartfiles in the Other Compiler Options to Append box as seen on the following page Select gt OK Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 4 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module T Properties for DDR_PowerPC type filter text v C C Build Info Builders Active Configuration C C Build Project Type C C Indexer Project References Configuration bebo o Manage Configuration Settings Tool Settings Build Settings Build Steps Error Parsers Binary Parser Environment Macros 2 8 PowerPC C Compiler Defined Symbols D 83 PowerPC Specific Options 3 Software Platform Option Include Paths Debug and Optimization 3 Miscellaneous B33 PowerPC C Linker Software Platform Option 3 Libraries amp Linker Script Other Compiler Options to Append nostartfiles 3 Miscellaneous Restore Defaults Apply The Acromag exa
39. to Block RAM address OxFFFFF034 Lastly the DDR program jumps back to the bootloop program The bootloop program checks Block RAM address OxFFFFFO34 for the value Ox5A5A5A5A and if found stays in an infinite while loop Exit of the while loop and re execution of the DDR program is possible by writing 0x0 to Block RAM address OxFFFFF034 DDR Program Overview The DDR2 example program can be downloaded directly into DDR DDR Program memory using the PCI bus The DDR memory example program has the Download file name VFX70_DDR bin This file can be found on the EDK CD ROM in the Designs PMC_V5 Programmable_FPGA XC5VFX70T_RevX VFX70 directory The Acromag software is not provided as part of the EDK It must be purchased separately The software available includes Windows DLL Drivers VxWorks QNX and Linux The Acromag software provides the code and drivers that allow exploring and testing the Acromag example design For example the Acromag software has a function that downloads the VFX70_DDR bin file into DDR memory The Acromag software function that moves the VFX70_DDR bin file into DDR memory executes the following 1 Writes the 32 bit data value that is to be written to the DDR memory to the DDR SDRAM Write registers at base address 8068H 2 Sets the DDR SDRAM Mask bits as desired at base address 806CH A value of OH would enable all bytes to be written 3 Sets the DDR SDRAM Address register at PCIBAR2 8060H with the DDR SDRAM
40. u are creating System Summary E Core Name Instance Name Base Address High Address pc440_0 ppc440me_ddr2 DDR2_SDRAM_W1D32M72R84_54 0x00000000 OxOFFFFFFF xps_uartlite R5232 0x84020000 0x8402FFFF xps_uartlite RS232_1 0x84000000 Ox8400FFFF pcibusif pcibusif_O OxFFFE8000 OxFFFESOFF xps_bram_if_cntlr xps_bram_if_cntlr_1 OxFFFFOOOO OxFFFFFFFF File Location f Overall C Designs PMC_ 5 Programmable_FPGA XCSVFX70T_RevDWFX70 PowerPC PowerPC xmp C Designs PMC_V5 Programmable_FPGA XCSVFX70T_RevD VFX70 PowerPC PowerPC mhs C Designs PMC_V5 Programmable_FPGA XCSVFX70T_RevD VFX70 PowerPC PowerPC mss C Designs PMC_V5 Programmable_FPGA XCSVFX70T_RevD VFX70 PowerPC datalPowerPC uct C Designs PMC_ 5 Programmable_FPGA XCSVFX70T_RevD WFX70 PowerPC etc Fast_runtime opt C Designs PMC_V5 Programmable_FPGA XCSVFX70T_RevD VFX70 PowerPC etc download cmd TestApp_Memory_ppc4 40_0 TestApp_Peripheral_ppc440_0 Save Base System Builder bsb Settings File c Designs PMC_VS Programmable_FPGA XCSYFX70T_RevD WFX70 PowerPC PawerPC bsb Select gt Finish Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 8 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module In Xilinx Platform Studio window XPS Make the following changes to the PowerPC mhs file PowerPC MHS Double select MHS File PowerPC mhs under the Projects Files to open it File At line 218
41. ude xbasic_types h include xio h include xio_dcr h int main print Hello World From Block RAM r n declare a function pointer int func_ptr char String 80 u32 i J u32 FullCnt EmptyCnt register unsigned int pter register unsigned int pter3 long readval long DDRvalue long flagvalue long CodeSize Initialize jump to DDR2 memory register value to zero pter unsigned int OxFFFFF030 pter 0x0 Check for Exit of DDR Program Identification value If Block RAM address OxFFFFF034 is set to Ox5A5A5A5A then the program in DDR Memory has completed execution pter unsigned int OxFFFFF034 if pter O0x5A5A5A5A print T r n while pter 0x5A5A5A5A Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 27 OxFFFFF038 is set with 0x33333333 if Flash code moved to DDR pter if pte unsigned int 0x33333333 E OxFFFFF038 Start move of Flash program data to DDR Memory pter3 unsigned int OxFFFE8000 FullCnt 0 EmptyCnt 0 DDRvalue 0 readval pter3 if readval amp 0x80000000 0x80000000 FullCnt if readval amp 0x40000000 0x40000000 EmptyCnt while readval amp 0x40000000 0x40000000 Empty FIFO readval p
42. write address location The DDR SDRAM memory starts at PowerPC base address 0x0 The DDR SDRAM high address is OXOFFFFFFF 4 Issues the Write Command Set bit 0 of the SDRAM Control Status Register at PCIBAR2 805CH to logic high Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module 1 After the DDR2 program code has been downloaded into DDR2 memory the PowerPC memory space address 0xFFFFF034 must be written with DDR Program data pattern 0x0 This will instruct the bootloop program to continue Execution execution of program code at the first memory location in DDR2 memory It does this by jumping to memory location 0x0 in DDR2 memory The following is the general procedure for setting memory space address OxFFFFF034 with the data value 0X0 Note the DDR SDRAM Read and Write registers are also used to access the Block RAM memory space in the PowerPC memory space 1 Write the 32 bit data value 0X0 to the DDR SDRAM Write registers at base address 8068H 2 Set the DDR SDRAM Mask bits to 0x0 at base address 806CH 3 Set the DDR SDRAM Address register at PCIBAR2 8060H with OxFFFFF034 the Block RAM write address location The Block RAM memory starts at PowerPC base address OXFFFFOOOO 4 Issue the Write Command Set bit 0 of the SDRAM Control Status Register at PCIBAR2 805CH to logic high After the PowerPC memory space address O
43. xFFFFF034 is written with data pattern 0x0 the DDR2 example program executes The DDR2 program prints the following to the terminal connected to UART port number one Answer address_Main Hello World From DDR2 About eight cycles of a sine wave are printed Exiting main Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 8 PMC VFX Getting Started Guide Virtex 5 Based FPGA PMC Module To develop and debug PowerPC programs you will need an RS232 Null Development Modem Cable and Xilinx JTAG program cable These cables are directly Hardware connected to the EDK board as shown in the following RS232 Null Modem Cable IMPORTANT Adequate air circulation or conduction cooling must be provided to prevent a temperature rise above the maximum operating temperature Connect your RS232 null modem cable from the top left connector of the EDK board to your hyper terminal com port Set the Bit Per Seconds to 9600 Data Bits to 8 Parity to None and one Stop Bit Xilinx JTAG Program Cable Install the JTAG program cable as recommended by Xilinx The flat 14 conductor ribbon cable must be connected to the JTAG port of the VFX EDK board as shown in the following figure RAB LADDA LLARA EE Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com PMC VFX User s Manual Virtex 5 Based FPGA PMC Module Q The development of the Xi
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