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CX29704

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2. Trib 1 Trib 2 Pos Pos SONET SONET SDH SDH SDH Ref Clock Ref Clock Ref Clock Loop Timing Loop Timing Loop Timing Off Off v Off 52 The All Tribs column in the Jump Start Screen can be used to set a parameter to the same value on all the channels of CX29704 The remaining columns configure an individual channel 2 1 1 Payload Contents The payload contents determine whether ATM cells or Packet over SONET is transported over the channels This setting affects all channels in the device therefore it can only be selected under the Tribs column 2 1 2 Framing Format The framing format for the optical signal can either be SONET STS 3c or SDH STM 1 2 1 3 Timing Source A channel s transmit data timing source can be set to either Ref Clock Timing based on an onboard clock source e Loop Timing Timing based on the clock recovered from the receive signal 29704 EVMD 001 C Mindspeed Technologies 13 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 1 4 Loopback There are five loopback options on the Jump Start Screen Off Disables loopback on the channel e Line Enables a remote line loopback within the CX29704 e Payload Enables a remote payload loopback within the C
3. 2 RS 232 29704 EVMD 001 C Mindspeed Technologies 24 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 4 1 1 CX29704 The 29704 is an integrated circuit that implements four channel mapping functions for SONET SDH processing and ATM HDLC at 155 52 Mbps The component contains both the PMD and the TC sublayers and provides an UTOPIA Level 2 interface for the ATM layer or a POS PHY Level 2 interface for the link layer Each port may be selected on a per port basis for either High Level Data Link Controller HDLC or ATM Cell Delineator protocol options The CX29704 line side interfaces support optical OCS STS 3c The system side interface may be chosen from the combination of UTOPIA Level 2 for ATM or POS PHY Level 2 for HDLC packets The dual mode Utopia Level 2 POS Level 2 interface is brought out to a Utopia 2 test connector and routed to the FPGA This FPGA provides POS Level 2 transparency to external POS Level 2 test equipment The feature set of this FPGA is described in Section 5 1 The SONET SDH Framer block provides access to the STS 3c transport DCC overhead both insertion and extraction The Overhead interfaces of the CX29704 are routed to the OH FPGA which allows access to overhead information on the STS 3c lines The feature set of this FPGA is described in Section 5 2 A full set of loopbacks is provided 4 1 2 Packet ATM F
4. 7 0003 0000 0000 0000 8421 007 0000 0000 FFFF 0000 0000 OFFF 0000 4001 0000 0000 0000 4101 0000 0000 0000 4201 0000 0000 0000 4301 0000 0000 0000 0050 0000 0000 0050 001 0000 0000 0050 001 0000 0000 0050 001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002 0000 0000 0000 2D 7 0000 0013 2pa7 0000 0013 2pa7 0000 0013 FFFF 0000 0013 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 0000 0000 0000 1 0000 0000 0000 01 0000 0000 0000 1 0000 0000 0000 0000 0000 2 2 1 Reading register Reading a register is a non invasive operation and will not influence the operation of the embedded driver To read a register follow these steps 1 Enter the register address to be read in the Register dialogue box 2 Click the Read command button 3 The register value will appear in the Value dialogue box A register can also be viewed via the Update command 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential 15 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 2 2 Writing a register
5. N List of Tables TEM TU dudes EORR OE 4 1 29704 EVM Memory 26 Om JTAG Signal 21 Table 5 1 POS PHY UTOPIA 2 Transmit CX29704 Side 30 Table 5 2 POS PHY UTOPIA 2 Receive 29704 Side Interface 31 Table 5 3 System Side POS PHY 2 UTOPIA Transmit interface 42 Table 5 4 System Side POS PHY2 UTOPIA Receive interface 33 Table 5 5 Interface Signal Description iussa oce REY ERR REAGOR 34 Table 5 6 Packet ATM FPGA 5 40 tabe oT TEs ROLOS 252252 5 44 29704 EVMD 001 C Mindspeed Technologies vii Mindspeed Proprietary and Confidential N 1 0 Getting Started 1 1 Introduction The CX29704 EVM is a fully integrated platform for evaluating the Mindspeed Technologies CX29704 device an OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer The CX29704 EVM includes the CX29704TAP software program a full featured driver available in C source code form under license from Mindspeed Technologies 1 1 1 System Overview The development system consists of the CX29704 EVM connected to
6. 12 Port DS3 E3 STS 1 Electrical Integrated Line Termination TAPDevice for Transport Networks MINDSPEED SOFTWARE LICENSE AGREEMENT THIS SOFTWARE LICENSE AGREEMENT is made between Mindspeed Technologies tm Inc CMINDSPEED and the person or company desiring to utilize the Licensed Program Licensee as ofthe date the Licensed Program is first received by Licensee Effective Date Licensee desires by this Agreement to obtain from MINDSPEED licenses to use the Licensed Program and related Documentation as defined below and establish the terms and conditions of all such transaction between them MINDSPEED is willing 10 license the Licensed Program to Licensee only if Licensee accepts ALL of he terms ofthis Agreement PLEASE READ THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE UTILIZING THE LICENSED PROGRAM BECAUSE BY UTILIZING THE LICENSED PROGRAM LICENSEE I8 AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF THIS AGREEMENT If Licensee does not agree to these terms and conditions MINDSPEED will not license the Licensed Program to Licensee and in that case Licensee should immediately cease utilizing in any fashion the Licensed Program and destroy all of Licensee s Copyright 2004 Mindspeed Technologies Inc 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential 17 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 5 2
7. Writing a register is an invasive operation and could influence the operation of the embedded driver It bypasses the normal driver execution This may lead to nondeterministic results in the execution of the driver To write a register follow these steps Enter the register address to be written in the Register dialogue box Enter the value to write to the specified register in the Value dialogue box Click the Write command button The new value will be written to the register This action can be confirmed by reading back the value via the read register process or clicking the Update command button and viewing the new value in the register display window gt N 2 2 8 Update command All of the register values since the last update are listed in the register display window To force a refresh of these values manually follow these steps 1 Click the Update command button The register display values will be refreshed Any register values that have changed since the last update will be highlighted in red 2 8 Packet ATM FPGA Registers Screen The Packet ATM FPGA Registers screen allows the user to read and write the various registers in the Packet ATM FPGA Reading and writing a register is done in the same manner as described in Section 2 2 2 4 FPGA Registers Screen The OH FPGA Registers screen allows the user to read and write the various registers in the OH FPGA Reading and writing a register is do
8. 0x80 Per port enables Port enable Port packet generator enable Port loopback enable Port packet generator mode 1 continous 0 5 packet burst reserved Port packet generator one shot burst mode trigger Rising edge sends burst Ox1C COR COR COR COR COR COR PM_stat_3 det_rx_pattern_err reserved PHY 5 Rx err PHY 4 Rx err PHY 3 Rx err PHY 2 Rx err PHY 1 Rx err PHY 0 Rx err 1 means Rx data does not compare equal to 5 1 means Rx data does not compare equal to 4 1 means Rx data does not compare equal to 3 1 means Rx data does not compare equal to 2 1 means Rx data does not compare equal to 1 1 means Rx data does not compare equal to 0 COR Rx data packet count Total number of packets received by device RW 1 0 Xmt packet length Packet Length bytes Valid values 1 0 RW 1 0 Xmt packet delay Delay between generated packtes Use this as a bandwidth control 29704 EVMD 001 C Mindspeed Technologies 41 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 2 FPGA Description Figure 5 5 OH FPGA 1 0 Signals lt gt uP Interface r SPSDISTSM m SW UP 50 P 2 mE gt MICTOR UP TP 15 0 UP 2 Clock Selects
9. U2 SY 4 C 0 RMOD indicates the number of valid bytes on the last word POS only 02 SY AB5 C 0 Indicates the validity of the POS PHY receive data signals POS only 29704 EVMD 001 C Mindspeed Technologies 33 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 1 1 2 3 HDLC Interface Table 5 5 HDLC Interface Signal Description Name Loc Type Dir Description Note the clock for this interface is provided to the 8260 via the PCB the 25MHz clock driven by the Packet ATM FPGA TXD 3 0 H18 C22 K18 C21 C 0 Serial data from the Packet ATM FPGA to the 8260 FCC RXD 3 0 F5 G5 H5 J5 C Serial data from the 8260 FCC to the Packet ATM FPGA RTS CTS K17 5 C 0 RTS indicates the beginning of a frame and can be used at the receiver for synchronization Note that RTS and CTS are used by a peripheral on the serial link by the corresponding peripherals transmitter CD is used by the receiver on the other end of the link A typical application would connect the RTS on peripheral A to CD on peripheral B via the serial bus Reference the Motorola MPC 8260 users manual chapters 28 and 32 for details of the timing There are several combinations of timing that depend on the nature of the data being moved These combinations must be set up in the 8260 register structure CTS in
10. eens 12 Figure 2 3 EVM GUI Application CX29704 xml 13 Figure 2 4 29704 Registers Screen 15 Figure 2 5 CX290704 GONG BUCO LansoaeecLiz tesscebb sbersbzbrreh thbsere redes 17 Figure 2 6 GA29709 FN SCICON a u u nA ed ORCI UR d dod DE RUD CORR 18 Figure 2 7 5 19 Figure 3 1 GX29704 EVM Software Block Diagram 20 Figure 4 1 CX29704 EVM Component Placement 23 Figure 4 2 CX29704 EVM Hardware Block Diagram 24 Fue ao JIANG e ONA 27 oA ee 4234 9rd OR Uh C dd REIR 29 Figure 5 2 FPGA Context Diagram 35 Figure 5 3 29704 EVM Packet ATM FPGA Block Diagram 36 Figure 5 4 CX29704 FPGA INTERFACES DATAFLOW and CLOCKING 37 Figure 5 5 OH FPGAI 0 510 42 Figure 5 6 Glock Selection Subsystem Block Diagram 43 29704 EVMD 001 C Mindspeed Technologies vi Mindspeed Proprietary and Confidential
11. 29704 FM This screen provides access to the failure monitoring parameters in the CX29704 TAP driver Figure 2 6 CX29704 FM Screen M29316 Failure Monitoring Reset DecayTime 10 0 Integration Time Reset mo ATM failure Ez e e P ER E e Fail Def Curr Hist eive Trib 0 UTOPIA error Def Curr Hist CHE NA UHE NA Q RCV CELL NA IDLE CELL NA SENT Fail Def Curr Hist XMT PARITY ERROR a at Fail Def Curr Hist NA NA NA DEVICE error LI LI LI EI LI I Fail Def Curr Hist DEVICE failure Fail Def Curr Hist Q OVERRUN Q OVERRUN Q XMT UNDERRUN TSOC ERROR Em End 18151 g 3 e Po ps s o en eka PKT XMT LOC PKT RCV LOC UTOPIA XMT LOC UTOPIA RCV LOC TDM XMT LOC LOC NA NA NA NA NA NA NA NA NA NA NA XMT LOS Q OPEN LIU OPEN LIU SHORT l Def Curr Hist LIU LCV CNTOF LIU AGCOF LIU PLL JAT OF JAT POS FD JAT NEG FD JAT FIFO UF JAT EQUALCO OF JAT EQUALCO UF PPM READY LIU ADPT START LIU ADPT FAIL 1083 Fail Def Curr Hist 1 9105 Q LOF Qas 1 jQ Q DLE sw fail
12. CX29704 Data Sheet 2 29704 SWG 002 X CX29704TAP Software Programming Guide 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 2 Unpacking The contents of the EVM shipping box should contain at a minimum the following items Table 1 1 Contents Qty Description 1 CX29704 EVM 1 120 Vac 5Vpc Power Converter 1 CX29704 EVM User Manual 2 SC SC Fiber Optic Patch Cable 1 10 100T Ethernet Cable straight through for connection to switch or hub 1 10 100T Ethernet Cross Over Cable cross over for direct connection to a PC 1 RS 232 Cable straight through for connection to PC serial port 1 DB9 RJ12 Adaptor 1 CD ROM containing device and software documentation hardware schematics and BOM 1 3 Requirements The following external peripherals are required to support the CX29704 system e System Requirements e Any of the following operating systems Windows 98 NT 2000 or XP e 40 MB available Hard drive space VT100 compatible monitor eg Windows Terminal HyperTerminal XTERM e 10 100T Ethernet card OC 3 Test Equipment e ESD safe workstation 1 4 Installation Procedures The CX29704 EVM is shipped in nearly plug and play condition The following setup procedures should take no longer than a few minutes 1 4 1 Hardware Assembly 1 4 1 1 Handling Normal ESD precauti
13. REOP U2 LE E7 C REOP marks the end of packet on the RDATA 15 0 bus POS amp UTOPIA 29704 EVMD 001 C Mindspeed Technologies 31 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 1 1 2 2 SYSTEM SIDE POS PHY 2 INTERFACE Table 5 3 System Side POS PHY 2 UTOPIA Transmit interface Name Loc Type Dir Description TXENB_U2_SY L20 C The TENB signal active low is used to initiate writes to selected ports POS amp UTOPIA TDAT U2 SY 15 0 G19 G20 G21 G22 C Transmit packet cell data bus 15 0 POS amp UTOPIA H19 H20 H21 H22 J19 J20 J21 J22 K19 K20 K21 K22 TPRTY U2 SY F18 C Calculated parity for the 2 LE bus POS 8 UTOPIA TSOP U2 SY F19 C TSOP a k a SOC indicates the first word of a packet POS amp UTOPIA TEOP U2 SY F20 C TEOP marks the end of a packet on the TDAT 15 0 bus POS only TERR U2 SY F21 C TERR is used to indicate that the current packet is aborted and should be discarded POS only TADR U2 SY 4 0 E18 E19 E20 E21 E C TADR is the mphy address of the channel POS amp UTOPIA 22 TMOD 02 SY F22 C indicates the size of the current word POS only TPA U2 SY 018 C 0 PTPA a k a TCLAV transitions high when a predefined minimum number of bytes is available in the polled transmit port s FIFO Once high PTPA indicates that the transmit port s FIFO is not full
14. kd eee wanwa sa NOR aD RC wb 43 s22 15 4 NERA TE DU aloe 44 BED SIMON 2cn1ks2595 2 49 992990812 929 248229 9922 910 94 9 9180 d452 83 46 61 EVM Environmental Conditions i EERReR EE CER tens 46 6 2 Power Requirements asked eek CARCER RR RE OE RD Race na 46 7 0 Physical Design Description 47 PA 0 TU UTERE rtr 47 F JE I RG LEETE 47 29704 EVMD 001 C Mindspeed Technologies v Mindspeed Proprietary and Confidential Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 List of Figures prp inu ru 1 CX29704 EVM Hardware Block 2 3 CX29704 EVM Software Block Diagram usas auk s Ear RERERPAXCTARSEZERPAE UO A RE ird 4 vrai glor lysssia uka sa 8 Figure T D New EVM Data NIS SOON pus 9 Figure EVM Data Filo SETON sss oo di doe ele OE EUR EUR ORI ORAE e ORC RE dA 10 Figure 2 1 29704 EVM Jump Start 11 Figure 2 2 Mode Switching Dialog tance cece ERER
15. 3 PHYMASTER_EN Set this bit to 1 to enable the external Phymaster interface 2 ADTECH_EN Set this bit to 1 to enable the external Adtech interface 1 POS_EN Set this bit to 1 to use an external POS interface 0 UTOPIA_EN Set this bit to 1 to use an external UTOPIA interface 0x3 REFCLK Control Register 7 3 Reserved RW 0x0 2 DISABLE REF This bit will disable the 19 44MHz oscillator when set to 1 Set this bit to 0 to enable the oscillator RW 0x0 1 0 REFCLK SEL 1 0 These bits select the source of the REFCLK signal 0x0 19 44MHz oscillator 0 1 REFCLK IN SMA connector 0x2 Reserved 0x3 Reserved 0x4 SMA OUT Control Register 7 4 Reserved RW 0x0 3 0 SMA OUT SEL 3 0 These bits select the source of the SMA OUT signal 0x0 Recovered line clock from channel 0 RECCLKO 0 1 Recovered line clock from channel 1 RECCLK1 0x2 Recovered line clock from channel 2 RECCLK2 0 3 Recovered line clock from channel 3 RECCLK3 0x4 microprocessor bus clock 0x5 ASSI interface clock 0x6 Reserved 0x7 Reserved 29704 EVMD 001 C Mindspeed Technologies 44 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Table 5 7 FPGA Registers Address R W Initial Bit Contents 0x5 CX29704 Reset Register 7 1 Reserved RW 0x0 0 SW DUT RESET set to 1 to reset the CX29704 Set to 0 to
16. CNTL TX DATA 8 16 TX CLK 25 50 MHz Optional ZBT SRAM Controller Optional ZBT SRAM transmit 29704 EVMD 001 C Mindspeed Technologies 36 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Figure 5 4 CX29704 FPGA INTERFACES DATAFLOW CLOCKING 100MHz TO 8260 HDLC 50MHz CX29704 Utopia 2 Packet Intf system side POS PHY CELL PACKET TO FROM V 25MHz clk TXD CPU Optional ZBT 34091 Data SRAM receive 50 MHz 25MHz 4 GENERATOR A U3 Tx and Rx CLK 25 50 MHz 100MHz Optional ZBT 100MHz SRAM transmit 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 1 3 Functional Blocks 5 1 8 1 29704 Interface The Packet ATM FPGA connects to CX29704 via standard POS PHY 2 and UTOPIA 2 interfaces The Packet ATM FPGA allows only one CX29704 interface active at a time SW control There are 31 POS UTOPIA 2 possible logical channels in which packet data may be transmitted or received the Packet ATM FPGA supports any six physical channels active at a time SW control Both packet interfaces are under the control of a single memory mapped bit that performs a r
17. IMPLIED RELATING TO SALE AND OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE CONSEQUENTIAL OR INCIDENTAL DAMAGES MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION TEXT GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL INDIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING WITHOUT LIMITATION LOST REVENUES OR LOST PROFITS WHICH MAY RESULT FROM THE USE OF THESE MATERIALS Mindspeed products are not intended for use in medical lifesaving or life sustaining applications Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale www mindspeed com General Information 949 579 3000 Headquarters Newport Beach 4000 MacArthur Blvd East Tower Newport Beach CA 92660 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential N Table of Contents Revision i PERTERRITI i QUE SUE D BL u uu dva 1 ET o EDO Luc eunt od ea E ds cca eie scs pos peciit a 1 114 System QVEIVIEW Ea RR nek cheba A
18. Parameter SUIDUIIB ERE R paco RR dE RR made 16 d rie entre PED Ed ok 17 IO HDI cei E cr Pr T PR 18 259 19 Pu Pras cssc Rese 19 3 0 Software Description quet raw tni ved eds 20 3 1 12 hc cae adt ker dE E dE EA ERE DERE ER db a EESE RR ee M dod 20 ar I D 14 REC RRO CR Do o e we ee 21 DPD 21 4 o kei espera 21 OP 21 3 24 FPGA Device Driver 32242504 cbe dick ie d oie acc asa 21 3 25 EVM Application Cade cn ck a asas RR RR Rm RR ACA ACE 21 HUS BODIE ret cnt kisu u uswa sia 22 23 1 Communications uana cs xix deck Xi OA ERO IE r RI 22 2o Deor UU usus seda dtecbcaweer dt daibecdedschiretitiescibcereNs 22 40 Hardware Description 23 4 1 Hardware Architecture 23 AA 1990 Lsiloshaadkatrnrrbe 25
19. high PTPA indicates that the transmit port s FIFO is not full When PTPA transitions low it optionally indicates that the transmit FIFO is full or near full normally user programmable PTPA allows to poll the port address selected by TADR 4 0 when TENB is asserted PTPA is driven by a port when its address is polled on TADR 4 0 POS amp UTOPIA TMOD U2 LE W20 CT OorZ TMOD indicates the size of the current word POS only TEOP U2 LE Y21 CT OorZ TEOP marks the end of a packet on the TDAT 15 0 bus POS only TERR U2 LE Y22 CT OorZ TERR is used to indicate that the current packet is aborted and should be discarded POS only STPA U2 LE P17 C STPA transitions high when a predefined minimum number of bytes is available in the selected transmit port s FIFO Once high STPA indicates that the transmit FIFO is not full When STPA transitions low it optionally indicates that the transmit FIFO is full or near full STPA always provide status indication for the selected port in order to avoid FIFO overflows while polling is performed POS only 29704 EVMD 001 C Mindspeed Technologies 30 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer The signals in Table 5 2 directly connect to the CX29704 device Table 5 2 08 PHY UTOPIA 2 Receive CX29704 Side Interface Name Loc Type Dir Description U2 LE CT
20. necessary to restore parameter settings Users can either create a new data file using the EVM template file CX29704EVM xml or alternatively open previously saved data file The first time the GUI is started the New option must be selected All EVM data files will have a ser extension 29704 EVMD 001 C Mindspeed Technologies 8 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 5 2 1 New EVM file Create a new EVM data file by following these steps 1 Select the New item under the File menu The following screen is displayed Figure 1 6 New EVM Data File Screen x Look In ce cca 8 Cf devices TextPreviewer CX29704EVM xml FileName Files of Type TAPDevice Profile Files xml 2 Select the CX29704ATMEVM xml file in the browser pane The file will be highlighted in the File Name text box 3 Click the Open command button 4 The Jump Start Screen is displayed See Section 2 1 29704 EVMD 001 C Mindspeed Technologies 9 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 5 2 2 Existing EVM File Load an existing data file by following these steps 1 Select the Open item under the File menu The following screen is displayed Figure 1 7 Open
21. reserved 5 reserved 4 reserved 3 reserved COR 2 reserved COR 1 POS_PHY parity error System Test Tx side POS2 COR 0 POS_PHY parity error Pele Rev side POS2 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential 40 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Table 5 6 FPGA Registers Continued Address R W Initial Bit s Contents OxD OxE COR COR RO RO RO RO RW RO RW 0x02 ODN DN Packet FPGA Performance Stat pm stat 2 reserved Pele side POS2 aborted packet detected DLL Locked up DLL Locked tx sy DLL Locked rx sy DLL Locked 50 2 for driving onto PCB using DDR registers DCM reset Reset far sytem side and clk 100 DCMs DLL locked Driven by External 100MHz produces internal 50 MHz CX29704 Rx FIFO Flush Flush reserved reserved reserved reserved Insert POS2 Tx eop errors continuous Insert POS2 Tx sop errors continuous reserved Flush Pele PO 52 Rx FIFO 1 flush OxF COR 0xC3 rS ODN Packet FPGA Performance Stat pm stat 3 Rx buffer 1 empty flag Rx buffer 0 empty flag Rx buffer 1 par full flag Rx buffer 0 par full flag Tx buffer 1 par full flag Tx buffer 0 par full flag Tx buffer 1 empty flag Tx buffer 0 empty flag 0x10 0x15 RW
22. 0 0 SAS mili 2 oll UAS nil 0 0 0 __ o ol ESCP 0 0 SESCP nil 0 011 0 UASCP ol 0 0 0 PathFarEnd 15 Min 24 FC 0 0 0 o E t es Elapsed Time 00 00 47 2 5 4 FPGA Config These screens provide access to the configuration and diagnostic parameters in the FPGA device drivers 29704 EVMD 001 C Mindspeed Technologies 19 Mindspeed Proprietary and Confidential N 3 0 Software Description 3 1 Software Architecture The software developed for the CX29704 EVM consists of code running on the EVM and code running on the Host PC Figure 3 1 illustrates the software components Figure 3 1 X29704 EVM Software Block Diagram Host PC EVM Graphical User Interface GUI Communications Communications EVM Application Software EVM CX29704TAP Driver FPGA Drivers VxWorks RTOS 29704 EVMD 001 C Mindspeed Technologies 20 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 3 2 EVM Software The software running on the EVM is composed of generic software RTOS Communications Protocol and EVM specific software EVM Application Software Device Drivers The following sections describe the software in more detail 3 2 1 RTOS At the lowest level the software consists of a VxWorks Real Time Operating System RTOS with a Board Support Pack
23. 1 13 2 Hardware Overvigw 2 TL EM SWE PERKINS 3 1 153 Rid phy pe 4 1 1 3 1 EVM Software Graphical User Interface 0 4 11 4 Reference DOCUMENTS 4 1 1 4 1 Mindspeed Technologies Documents RR 4 E EEO dnd LS A KH ICA 5 LS TG TOC nri OEE EAE Pr 5 uu See sue See PIDE d POT 5 dere UR sean Ue ed opea p dear did ye bib TO 5 TA LE ASSSITBI rid C ERGOK ER ERR RR ERO bd 5 oL PST SMS le RUE 5 14 2 Setting the IP Address 6 1 4 8 Installing the EVM GUI software 7 GNE OUI ci cence Rice Rr 8 15 1 the SONAE LIC 8 15 2 Startup Screen and loading data oc uu ia
24. CX29704 OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer EVM User Manual TM 29704 EVMD 001 C M N DS D June 2005 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Revision History Revision Level Date Description C Released June 2005 Updated document number B Advance November 2004 First revision for external use 2005 Mindspeed Technologies Inc All rights reserved Information in this document is provided in connection with Mindspeed Technologies products These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only Except as provided in Mindspeed s Terms and Conditions of Sale for such products or in any separate agreement related to this document Mindspeed assumes no liability whatsoever Mindspeed assumes no responsibility for errors or omissions in these materials Mindspeed may make changes to specifications and product descriptions at any time without notice Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document THESE MATERIALS ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESS OR
25. ETER ERREUR 28 hes ss RP 28 29704 EVMD 001 C Mindspeed Technologies iv Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer FPGA aue dE RR CERO apa RE aes 29 S1 POS IME D 29 Bd qd epa 29 Funcional Grouping db de CR Ql 29 ONS Pre Pup 30 5 1 2 Packet ATM FPGA Functional Description 35 Block DIUI O O u ep ep eee oR BOR 6 ORS PR RE er ERA ES 35 5 5 cuiu a ERA edat e ar wk Ra RR aa 38 ZJ WEEE aoatiad elses as bad ads shad eedesdaaause 38 5 1 3 2 CX29704 Side Loopback Mux s 38 Lo HDLC PERDUE REIN ELE VICES 39 5 1 4 Packet ATM FPGA Register Description 40 52 omi rei ede PS dee RE ma asas EAE 42 5 41 Clock Selection conc cares scr
26. EVM Data File Screen xj Files of Type EVM Serialization Files ser 2 Select EVM Serialization file in the browse pane The file will be highlighted in the File Name text box 3 Click the Open command button 4 The Jump Start Screen in displayed See Section 2 1 29704 EVMD 001 C Mindspeed Technologies 10 Mindspeed Proprietary and Confidential N 2 0 GUI Operation 2 1 Jump Start Screen The Jump Start Screen allows easy access to commonly used functions to provision all or any one of the four tributary channels on the CX29704 The default values for all of the parameters are shown in Figure 2 1 Figure 2 1 CX29704 EVM Jump Start CX29704 EVM Jump Start All Tribs Trib 0 Trib 1 Trib 2 Trib 3 5 Payload Contents Pos POS POS POS POS SONET SONET SONET SONET SONET Framing Format 2 SDH SDH 2 SDH 2 SDH 2 SDH IF T Ref Clock Ref Clock Ref Clock Ref Clock Ref Clock Timing Source Loop Timing Loop Timing Loop Timing Loop Timing Loop Timing Loopback off Packet ATM FPGA Mode Tri State 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential CX29704 EVM User Manua
27. O LOP3 Indicates LOP when illuminated AIS PO AIS P3 Indicates AIS P when illuminated L SDO L SD3 Indicates L SD when illuminated L SFO L SF3 Indicates L SF when illuminated AIS LO AIS L3 Indicates AIS L when illuminated LOFO LOFS Indicates LOF when illuminated LOSO 1063 Indicates LOS when illuminated 4 42 Jumpers There are no jumpers to set on the board 29704 EVMD 001 C Mindspeed Technologies 28 Mindspeed Proprietary and Confidential N 5 0 FPGA Description 5 1 Packet ATM FPGA 5 1 1 Interfaces 5 1 1 1 Functional Grouping Figure 5 1 Packet ATM FPGA 100M 50M 25M CX29704 CNTL ADDR DATA ADDR DATA ck clk ck SIDE AA A SRAM INTF Tx Transmit P0S PHY 2 lt gt UTOPIA2 Interface CONTROL SOP EOP ETC 50MHz 16 DAT POS PHY 2 iem UTOPIA 2 CONTROL Interface SOP EOP ETC 50MHz Receive TESTPOI amp LEDs 7 LEDs TSTPNTS CNTL ADDR DATA SYSTEM TESTER SIDE 1 CD RD 7 4 4 TxD RTS CTS gt 8 orl DAT Transmit POS PHY 2 CON foL UTOPIA 1 2 SOP EOP ETC Interface CLOCK L DAT Receive POS PHY 2 CONTROL UTOPIA 1 2 SOP EOP ETC Interface q CLOCK 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential 29 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 1 1 2 Signal Description I
28. OorZ The RENB signal is used to initiate reads from the receive FIFO s in CX29704 When RENB is asserted data is transferred from the selected PHY RADR 4 0 is used to select the PHY POS amp UTOPIA RADR U2 LE 4 0 K1 K2 K3 K4 CT OorZ The RADDR is used to select the PHY device or port number in which K6 the system FPGA wants to read data from this done by placing the appropriate address on RADDR one cycle before asserting RENB POS amp UTOPIA RDAT U2 LE 15 0 F1 F2 F3 F4 C The RDATA 15 0 bus carries the packet cell words that are read from the G1 G2 G3 G4 selected port POS amp UTOPIA H1 H2 H3 H4 J1 J2 J3 J4 RPRTY_U2_LE A6 C The receive parity RPRTY signal indicates the parity of the RDAT bus POS amp UTOPIA RSOP 02 LE B7 C RSOP marks the first word of a packet cell transfer POS amp UTOPIA PRPA U2 LE C7 C PRPA AKA RCALV indicates when data is available in the polled port When is high the port has at least one end of packet cell or a predefined number of bytes to be read POS amp UTOPIA RMOD U2 LE B6 C RMOD indicates the number of bytes carried by the RDATA 15 0 bus during the last word of a packet transfer POS only RVAL U2 LE 07 C RVAL indicates the validity of the receive data signals When RVAL is high the receive signals RDAT RSOP REOP RMOD RPRTY and RERR are valid POS only RERR U2 LE C6 C RERR is used to indicate that the current packet is aborted and should be discarded POS only
29. PGA The Packet ATM FPGA provides a number of functions e External UTOPIA L2 Tester access to CX29704 UTOPIA Level 2 Interface Per port active transmit UTOPIA interface selection System L2 interface Rx port loopback optional cell generator Per port Tx and Rx ATM cell counters External SPI 2 Tester access to CX29704 POS Level 2 Interface Full packetization of HDLC traffic Packet level loopback functionality CPU subsystem access serial HDLC stream to CX29704 POS Level 2 interface Packet and ATM cell generation and monitoring features tbd 4 1 3 Overhead FPGA The OH FPGA supports the ASSI alarm interface and contains miscellaneous glue logic for the EVM It also provides access to the SONET SDH Transport DCC Overhead for STS 3c interface 4 1 4 Control Subsystem The communications and control subsystem is implemented on a daughter board known as the Elgin Processor Board Elgin is comprised of an MPC8260 Microprocessor with SDRAM Flash EEPROM Ethernet USB and RS232 serial ports In customer applications of the EVM the Ethernet and USB interfaces will be used Refer to the Elgin Processor Hardware Description Document for more information 29704 EVMD 001 C Mindspeed Technologies 25 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 4 1 4 1 Internal Memory Map Table 4 1 summarizes the memory map for the CX29704 EVM The use of the other Chip Select
30. POS Framer 9 1 4 Packet ATM FPGA Register Description The FPGA registers are accessible using CS11 on the EVM Table 5 6 describes the general control registers for the CX29704 Packet ATM FPGA load Table 5 6 FPGA Registers Address R W Initial Bit s Contents 0x0 RW 0 70 Diagnostic Scratch Register scratch reg General purpose register for debug purposes 0 1 RO 5 T 0 FPGA Version ver Current FPGA version 0x2 RO 0xC2 70 FPGA ID id FPGA device ID 3 4 RW 0 thru 5 4 0 Receive Buffer Ingress Channel Assignments 7 8 Address of Channel to assign to Rx buffers 0 thru 5 0x18 0x19 5 6 RW 0 thru 5 40 Transmit Buffer Egress Channel Assignments 0x16 0x17 0x Address of Channel to assign to Tx buffers 0 thru 5 1A 0x1B 0X9 RO 0x09 BUILD NUMBER 0 06 TRANSMISSION CNTL 2 76 reserved 5 reserved 40 Number of addresses to poll RW OXOE TRANSMISSION CNTL REG xmit cntl reg 7 Test mode 1 single phy only no poling applies to Pele side only 6 Float POS PHY2 Pele side bus drivers 0 float 5 FPGA system side UTOPIA bus size 1 8 bit 0 16 bit 4 FPGA system side clock source 1 Adtech 0 PhyMaster 3 Run enable receive side POS PHY interface 1 run 2 Run enable transmit side POS PHY interface 1 run 1 reserved write to 0 0 FPGA interface mode 1 UTOPIA cells 0 POS packets OxC 0 Packet_FPGA_Performance_Stat pm_stat_1 7 reserved 6
31. REFCLK SEL 1 0 UP RESET CK SEL 1 0 PHYMASTER m I P0S_EN RECCLK 3 0 gt Recovered Enable Signals gt UTOPIA r 9 EN 100 EN REF So wee mom oum cus ASDO ASSI Interface LEDs h PSF 3 0 ASSTB gt gt LSD 3 0 Meera mee i ma LSF 3 0 gt LCD 3 0 x RSDCD 4 1 RSDCC 4 1 RLDCD 4 1 TXCP 3 0 RLDCC 4 1 83 I gt RLOS 3 0 TSDCC 4 1 9 TLDCC 41 CNN 0 ASENB DCC Interface m ISDCD 4 1 ra e E TLDCD 4 1 SMA IN SMA Interface we SMA OUT gt 1 Undefined FPGA CLK OUT CX29704EVM OH FPGA XC2S50E FT256 The OH FPGA supports the ASSI alarm interface and contains miscellaneous glue logic for the EVM It provides Software reset control of the CX29704 device as well as clock source control for REFCLK and the CX29704 Utopia interface The SONET SDH Transport DCC Overhead for STS 3c interface signals from the CX29704 have been routed to this FPGA to allow for future access to this interface Subsequent versions of this document will detail the available functionality 29704 EVMD 001 C Mindspeed Technologies 42 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 2 1 Clock Select
32. Signal Flow direction I Input O Output IO Bidirectional 43 2 JTAG Connector P1 is the JTAG connector on the EVM It is used to perform boundary scan test on the board using the standard Corelis pin out This JTAG connector connects to a single chain of all of the JTAG compliant devices on the board Any of these parts can be removed from the chain by removing the 33 ohm resistor at the device s output and installing the zero ohm resistor to bypass the part Figure 4 3 JTAG Test Chain not installed not installed not installed BDM c we 0 0 rd 7 W LH AW W Lay TDI 33 33 1 93 1 33 33 h We Packet TX imana RX TRST CX29704 FPGA ies OH FPGA mE AS RAM E TCK TK TCK TCK TDO lt P1 provides a 10 pin connector for use with standard JTAG controllers Table 4 2 JTAG Signal Description Name Loc Type Dir Description TRST P4 1 C JTAG Reset TDI P4 3 C JTAG Serial Data Input TDO P4 5 C 0 JTAG Serial Data Output TMS P4 7 C JTAG Mode Select TCK P4 9 C JTAG Clock 29704 EVMD 001 C Mindspeed Technologies 27 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 43 3 Test Points Connectors P2 and J8 are test points for FPGA development 4 3 4 UL2 Connectors Connectors J6 and J7 a
33. When PTPA transitions low it optionally indicates that the transmit FIFO is full or near full normally user programmable PTPA allows to poll the port address selected by TADR 4 0 when TENB is asserted POS only feature POS amp UTOPIA STPA U2 SY A19 C 0 STPA contains information about the availability of packets in the selected channel POS only 29704 EVMD 001 C Mindspeed Technologies 32 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Table 5 4 System Side POS PHY2 UTOPIA Receive interface Name Loc Type Dir Description RENB U2 5 5 C is used to control the flow of data from the receive FIFOs POS amp UTOPIA 02 SY 15 0 T1 T2 T3 14 C 0 Packet cell data POS amp UTOPIA T5 U1 U2 U3 U4 U5 V1 V2 V3 V4 V5 W1 RPRTY_U2_SY B5 C 0 RPRTY indicates the calculated Parity for the current octet POS amp UTOPIA RSOP U2 SY V6 C 0 RSOP indicates the first word of a packet cell POS amp UTOPIA REOP U2 SY W6 C 0 REOP indicates the first word of a packet POS only RERR 02 SY C5 C 0 RERR is used to indicate that the current packet is aborted and should be discarded POS only RADR U2 SY 4 0 Y7 R1 R2 R3 C RADR is the mphy address of the channel POS amp UTOPIA R4 RPA U2 SY 5 C 0 RPA a k a RCLAV indicates that the polled PHY has a packet or cell to transfer POS amp UTOPIA
34. X29704 The CX29704 datasheet refers to this loopback as a SONET loopback Terminal Enables a local ATM POS loopback within the CX29704 e FPGA Enables a remote loopback within the Packet ATM FPGA of data received over the UTOPIA POS PHY interface 2 1 5 Packet ATM FPGA Mode There are three modes of operation for the Packet ATM FPGA Disabled Disables the FPGA allowing test equipment to be attached to the UTOPIA POS PHY Level 2 connectors J9 J10 e Utopia Enables the Utopia interface on the Packet ATM FPGA e 92 Enables the POS PHY interface on the Packet ATM FPGA 2 1 6 Log Pane When parameters are changed in the Jump Start Screen a series of commands are sent to the EVM to configure the devices These commands will appear in the Log Pane at the bottom of the Jump Start screen 29704 EVMD 001 C Mindspeed Technologies 14 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 2 CX29704 Registers Screen The CX29704 Registers Screen allows the user to read and write any register in the CX29704 All register addresses and values are in hexadecimal format Figure 2 4 CX29704 Registers Screen CX29704 Registers Register Value Rem Save ToFile Registers 0 2 3 4 5 8 10 20 30 40 50 60 70 80 90 A0 0 Fo 100 1 6
35. X29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer www mindspeed com General Information 949 579 3000 Headquarters Newport Beach 4000 MacArthur Blvd East Tower Newport Beach CA 92660 MNDSPEED 29704 EVMD 001 C Mindspeed Technologies 48 Mindspeed Proprietary and Confidential
36. a power supply and a desktop PC or laptop which runs the EVM GUI This is shown in Figure 1 1 Figure 1 1 X29704 EVM System Power Supply 5V OptiPHY Optional Test Equipment 0C 3 CX29704 S 8 Utopia 12 Tester gt gt POS L2 Tester Communications CPU Subsystem USB or 10 100 T 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 1 2 Hardware Overview Figure 1 2 depicts the EVM hardware architecture Figure 1 2 X29704 EVM Hardware Block Diagram 19 44 MHz 19 44MHz Oscillator 0C 3 Reference Clock SONET SDH Recovered CLK 0 Framer l 4 CX29704 2 TxClockSelect Per Port Utopia L2 Utop POS POS L2 L2 Tester 0C 3 DCC ASSI Interface A xm SONET SDH Framer ester Recovered CLK 3 Microprocessor I F L2 Tester SODIMM USB EVM Control FPGA Ethernet 10 100 MPC8260 com Communications Processor RS 232 com2 RS 232 5 29704 EVMD 001 C Mindspeed Technologies 2 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 1 2 1 EVM Top View illustrates the component and connector placement
37. age BSP specific to the MPC8260 based CPU subsystem The RTOS and basic BSP are available from WindRiver as a licensed source code product The BSP is customized in small ways to account for the limited differences between the hardware components on the CPU subsystem and WindRiver s SBC8260 standard platform a Motorola reference design 3 2 2 Communications A communications driver protocol software layer is provided on the EVM to facilitate communications between the EVM and the host PC The communications function is provided in part by the RTOS in that it provides TCP IP and COM port support USB extensions are written to enhance the available BSP software Higher level protocol software is required for implementing a message set that relies on these lower layers 3 2 3 CX29704 The TAP Telecom Application Program is a full featured device driver for the CX29704 family that builds on existing line of software products and collateral for Mindspeed WAN Access devices The TAP software includes a comprehensive set of software parameters and functions that translate the device control registers and features into the software realm plus such value added features as standards compliant Failure Monitoring and Performance Monitoring 3 2 4 FPGA Device Driver For each FPGA device on the EVM a separate device driver will be included in the EVM software These drivers will control and monitor the loopback and other diagnostic featu
38. cket is present After a full packet is buffered the packet available signal on the system tester side is asserted The tester can now remove the packet in its entirety without any pauses on the packet bus The Xilinx Virtex 1 1000 has enough block RAM to implement six buffers each holding about 1 9K bytes If the incoming packet size is larger than the buffer then the packet will be accepted and truncated to fit in the buffer and that packet will be marked by the assertion of the err signal If a missing end condition is created by faulty transmission or a switch to loopback mid packet the current packet is also marked with an err UTOPIA cells are always internally stored 54 bytes in length This means that false data is inserted into the incoming stream when accepting 52 or 53 byte cells Also note that the extra bytes are removed from the outgoing stream when an outgoing interface is configured as 52 or 53 byte This is true in both the Tx and Rx directions Note that UTOPIA cells are marked with EOP internally using counters Therefore much of the control logic to operates as if HDLC packet are being processed This avoided a complete re design of the packet based design when UTOPIA features were added 5 1 3 2 2 Small Asynchronous FIFOs Small asynchronous FIFOs are used to decouple the internal and external clocks associated with the packet tester and the rest of the Packet ATM FPGA Data width conversion is done for the UTOPIA interface using c
39. d the CX29704 device itself plus adds macro functions to ease device setup and configuring of the test capabilities of the EVM Section 2 0 describes the GUI in more detail 29704 EVMD 001 C Mindspeed Technologies 22 Mindspeed Proprietary and Confidential N 4 0 Hardware Description 4 1 Hardware Architecture shows the component placement on the CX29704 EVM Figure 4 1 CX29704 EVM Component Placement CX29704 Status LEDs EXT CLK FPGA CLK In In MINDSPEED CX29704 EVM 29704 EVMD 001 C FPGA POS PHY L2 Elgin CPU Subsystem FPGA RX TX 5 23 29704 UTOPIA POS PHY 12 82 60 RX TX 100Mbit 131 Active Debug LEDO LEDI LED2 LED3 LED4 FPGA CLK LEDS Out au 1 8 LED7 Reg Mindspeed Technologies Mindspeed Proprietary and Confidential 23 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Figure 4 2 CX29704 EVM Hardware Block Diagram 19 44 MHz 19 44MHz Oscillator 0C 3 Reference Clock 29 XCVR 4 CX29704 2 Tx Clock Select e Utopia L2 Utop POS POS L2 L2 Tester 00 3 DCC ASSI Interface POS L2 Tester XCVR Recovered CLK 3 Microprocessor I F L2 Tester EVM pP Interface EVM SCC SDRAM SODIMM EVM Control Ethernet 10 100 MPC8260 T Communications Processor
40. dicates that the receiving end is able to accept data Note that RTS and CTS are used by a peripheral on the serial link by that peripherals transmitter CD is used by the receiver on the other end of the link CD E6 CD is used by a peripherals receiver to know when a start of frame is occurring Note that RTS and CTS are used by a peripheral on the serial link by that peripherals transmitter CD is used by the receiver on the other end of the link A typical application would connect the RTS on peripheral A to the CD on peripheral B 29704 EVMD 001 C Mindspeed Technologies 34 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 1 2 Packet ATM FPGA Functional Description 5 1 2 1 Block Diagram Figure 5 2 FPGA Context Diagram Utopia L2 Utopia POS L2 Tester CX29704 Utopia Tester FPGA uP Interface MPC8260 29704 EVMD 001 C Mindspeed Technologies 35 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Figure 5 3 CX29704 EVM Packet ATM FPGA Block Diagram TO FROM TO 8260 HDLC CPU A A Dat U2 Tx and Rx CLK dar S Optional ZBT 50 2 SRAM receive 29704 Utopia 2 POS2 system side INTERNAL CLOCKS CELL PACKET HDLC MONITOR SERDES and
41. ed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 Enter c and continue hitting return until the inet on ethernet field is displayed Enter the new IP address as show below Then continue to hit return until the boot prompt is redisplayed VxWorks Boot c clear field go to previous field D quit boot device flasho processor number 0 host name host file name aurora bin inet on ethernet e 10 1 158 112 10 1 158 123 inet on backplane b host inet h t T0 1 158 127 gateway inet 10 1 158 1 user u ftp password pw blank use rsh flags f 0x88 target name tn startup script s other o motfcc VxWorks Boot 3 Reboot the EVM by entering a When the board comes out of reset do not enter the debug menu After the debug menu prompt times out the board will load its application software and begin waiting for messages from the EVM GUI software VxWorks Boot 1 4 3 Installing the EVM GUI software Follow these steps to install the EVM GUI software 1 Place the EVM GUI software distribution CD into the CD drive 2 Runthe program installer exe on the CD A MS DOS window appears and installs the program files to the c cx29704evm directory This directory is fixed and can t be changed A list of the subdirectories and files installed is print
42. ed to the screen and then the following prompt To launch the application please do one of the following a Double click desktop icon labeled CX29704 EVM GUI b At the command prompt change to C cx29704evm directory and type go c Under window explorer go to C cx29704evm directory and double click go or go bat Do you want to launch the application now Y N 3 the necessary Java Virtual Machine is not already loaded on the PC the installer will issue a prompt to load the JVM 4 After pressing any key to continue a console window appears and the GUI application automatically launches displaying the Startup Screen illustrated in Figure 1 5 29704 EVMD 001 C Mindspeed Technologies 7 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 5 Quick Start Procedure 1 5 1 Running the software If the EVM GUI software has already been installed run the software by following these steps e Execute the go baf batch file in the c cx29704evm directory The EVM GUI software run screen will be displayed and the GUI application will launch displaying the Startup Screen illustrated in Figure 1 5 1 5 2 Startup Screen and loading a data file After the EVM GUI application is launched the following Startup Screen is displayed Figure 1 5 Startup Screen The EVM GUI application uses a data file containing all of the information
43. for the CX29704 EVM Figure 1 3 CX29704 EVM Top View FPGA POS PHY L2 Elgin CPU Subsystem FPGA RX TX 3232 CX29704 29704 UTOPIA POS PHY 1 2 M 82 6 0 Status LEDs TR Active Debug LEDO LEDI LED2 LED3 LED4 EXT CLK FPGA CLK FPGA CLK m In In Out 8V LED7 MINDSPEED CX29704 EVM 29704 EVMD 001 C Mindspeed Technologies 3 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 1 3 Software Architecture The CX29704 EVM software consists of code running on the EVM and code running on the Host PC Figure 1 4 illustrates the software components Figure 1 4 CX29704 EVM Software Block Diagram Host PC EVM Graphical User Interface GUI Communications Communications EVM Application Software EVM CX29704TAP Driver FPGA Drivers VxWorks RTOS 1 1 3 1 EVM Software Graphical User Interface GUI The EVM software package provides a Graphical User Interface GUI application to communicate with the EVM hardware module The GUI provides a means to configure the CX29704 and FPGA devices acquire status information collect performance monitoring data and directly read write device registers The GUI uses a TCP IP Sockets based connection to exchange messages with the embedded TAP drivers that reside on the EVM 1 1 4 Reference Documents 1 1 4 1 Mindspeed Technologies Documents 1 29704 DSH 001 X
44. ion Diagram A block diagram of the clock selection subsystem appears in Figure 5 1 Figure 5 8 Clock Selection Subsystem Block Diagram 19 44MHz 20ppm W Oscillator 100 21 1 2 74 153 O W REFCLK FPGA_CLK_OUT AW REFCLK_SELO SMA IN REFCLK_SEL1 SMA QUT AW CK SEL1 L CK SELO FPGA MC100EPT21 RXUTP_CLK_UP RXUTP_CLK_FPGA RXUTP_CLK_TEST TAUTE TXUTP_CLK_UP 1 2 P1383253Q TXUTP_CLK_FPGA TXUTP_CLK_TEST RXUTP CLK 1 2 832530 29704 EVMD 001 C Mindspeed Technologies 43 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 2 2 FPGA Registers The FPGA has 8 registers accessible using CS9 on the EVM Table 5 7 FPGA Registers Address R W Initial Bit Contents 0x0 Board ID Register R 0x2 7 5 Board ID code 0x3 CX29704 EVM 4 0 Reserved 0 1 Version Code Register R 0x1 7 0 Version Code 0x01 0 1 0x2 UTOPIA Control Register RW 0x0 7 DISABLE 100 This bit will disable the 100 MHz UTOPIA oscillator when set to 1 Set this bit to 0 to enable the oscillator 6 Reserved RW 0x0 5 4 CK SEL 1 0 These bits select the source of the UTOPIA clock 0x0 Utopia clock from microprocessor daughterboard 1 Utopia clock from FPGA 0x2 Utopia clock from external UTOPIA tester 0x3 Reserved
45. l OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer At this point the GUI is in offline mode Switch to online mode by following these steps 1 Select the Online item under the Edit menu The following screen is displayed Figure 2 2 Mode Switching Dialog Connection IP Addr 10 1 158 178 Port UTOPIA Clock Source OnBoard Connector Off Module 0 j Synchronization Reset EVM and local settings to default upload minimum recommended Retrieve EVM settings overwrite local copy slow O Overwrite EVM settings with local copy slow 2 Enter the IP address of the EVM 3 Selectthe desired UTOPIA bus clock source To use the timing source present on the EVM select Board To use a clock supplied via the UTOPIA connector select Connector 4 Selectthe desired software settings synchronization option The recommended option resets the EVM and GUI to default settings 5 Click the command button 6 Four screens as illustrated below in Figure 2 3 are displayed the Jump Start CX29704 Registers OH FPGA Registers and ATM FPGA Registers 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer Figure 2 3 EVM GUI Application 29704 File Edit Windows
46. lines are described in the Elgin Processor documentation Table 4 1 CX29704 EVM Memory Chip Select EVM Base Address Address Space Required Function CS8 0xB0000000 128 KByte CX29704 Device CS9 0xD0010000 64 KByte Packet ATM FPGA CS11 0xD0020000 64 KByte Overhead FPGA 4 1 5 Oscillators The CX29704 EVM employs the following oscillators e The CX29704 device uses a 19 44 MHz 20 ppm oscillator for its CLAD circuit e FPGA uses a 100 MHz 50 ppm oscillator to generate and receive POS ATM data 4 1 6 Power 4 1 6 1 External Power Power is provided from a 5V 5A regulated tabletop power supply Typical current draw for the board is 3 8A with all channels operational 4 1 6 2 EVM Regulators Four voltage regulators from 5V input supply are implemented on the EVM 3 3V Board supply 3 3V CX29704 supply 1 8V Overhead FPGA core voltage 1 5V FPGA core voltage Status LEDs for all supply voltages are provided If the voltages are below nominal the board will be held in reset The 3 3V regulators turn on first followed by the FPGA core voltage regulators Enable timing is adjustable by changing a voltage divider and capacitive loading on the regulator enable pin As a build option the board 3 3V and CX29704 3 3V supplies can be tied together by removing the CX29704 regulator and connecting the planes via a ferrite bead These options allow the verifica
47. n Table 5 1 Table 5 5 the following definitions are used Loc Physical Location of the 1 0 signal Classification of signal C 3 3V CMOS compatible input or output CT 3 3V CMOS Tristateable output P or VSS Type Dir Signal Flow direction l Input O Output IO Bidirectional Z high impedance signals are active high except for signal names ending in the symbol 5 1 1 2 1 CX29704 Interface The signals in Table 5 1 connect directly to the CX29704 device Table 5 1 POS PHY UTOPIA 2 Transmit CX29704 Side Interface Name Loc Type Dir Description TXENB_U2_LE P18 CT OorZ The TENB signal active low is used to initiate writes to selected ports POS amp UTOPIA TDAT_U2_LE 15 0 R18 R19 R20 R21 CT OorZ Transmit packet cell data bus 15 0 POS amp UTOPIA R22 T18 T19 T20 721 722 018 019 U20 U21 U22 V22 TPRTY U2 LE AA202 CT OorZ Calculated parity for the U2 LE bus POS amp UTOPIA TSOP U2 LE W22 CT OorZ TSOP SOC indicates the first word of a packet POS amp UTOPIA TADR U2 LE 4 0 AA18 V19 V20 V21 CT OorZ The TADR 4 0 bus is used to select the port that is written to using the W 1 TENB signal and the ports whose packet available signal is visible on the TPA output when polling POS amp UTOPIA PTPA U2 LE AB18 C PTPA TCLAV transitions high when a predefined minimum number of bytes is available in the polled transmit port s FIFO Once
48. ne in the same manner as described in Section 2 2 2 5 TAP Driver Parameter Screens Additional screens can be enabled via the Windows menu that provide more detailed access to the configuration and status of the CX29704 and FPGA devices These screens provide access to the TAP driver see section Section 3 2 3 and Section 3 2 4 parameters Refer to the CX29704 TAP Software Programming Guide see Section 1 1 4 for a description of the CX29704 parameters 29704 EVMD 001 C Mindspeed Technologies 16 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 5 1 CX29704 Config This screen provides access to the configuration and diagnostic parameters in the CX29704 TAP driver Figure 2 5 CX29704 Config Screen cx29704 POH P 29704 POH TRACE cx29704 TRCL P Diagnostic Dy 29704 DG Par 29704 DG Paramete 29704 POH DG Par 29704 DG Para General 29704 G FM 29704 G Parameter 29704 Para 29704 G Para 29704 6 PM Param 29704 G Para Overhead 628704 OH Par 29704 Para 29704 POH RD 3 29704 E Configuration 1628704 Para Change Logs 29704 Version 1 2 Date 07 22 2003
49. ons should be practiced when handling and operating the CX29704 EVM 1 4 1 2 Board Assembly The CX29704 EVM is a pre assembled two module set and no additional assembly is required 1 4 1 3 Flash Memory With the exception of occasional FlashROM upgrades to the EVM there should never be a need to remove or replace socketed components from the module 29704 EVMD 001 C Mindspeed Technologies 5 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 1 4 2 Setting the IP Address Before using the GUI software the IP address of the EVM should be changed to one that is appropriate for the Ethernet LAN to which it will be attached This is accomplished through the serial port of the EVM The serial port settings are 9600 baud 8 data bits no parity and 1 stop bit Follow these steps to change the default IP address to a local IP address 1 Connect to the EVM serial port connect and apply power Press and hold the CPU reset switch to reset the board Access the debug menu by pressing the return key when prompted and before the time out period expires The following text is displayed VxWorks System Boot Copyright 1984 1998 Wind River Systems Inc CPU MPC8260 CPLD N 04 Mindspeed Elgin Version 5 4 2 BSP version 2 0 00 Creation date Jan 29 2003 14 07 02 Press any key to stop auto boot 1 29704 EVMD 001 C Mindspeed Technologies 6 Mindspe
50. ontrol logic near these fifos and their flags 29704 EVMD 001 C Mindspeed Technologies 38 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 5 1 3 2 3 Master Design The POS UTOPIA 2 masters poll until a packet available is detected Next the transfer of a packet begins The master continues to poll while the packet is being transferred If another channel indicates packet available true then that channel number is stored so that the channel will be accessed when the current channel completes its transfer The number of channels to poll is programmable using the memory mapped interface 5 1 3 2 4 FPGA System Side Interface The system side interface to the external test set is configured as a POS PHY2 or UTOPIA 1 2 slave The POS 2 interface will delay assertion of the packet available signal until there is at least one EOP in the buffer 5 1 3 2 5 Packet Monitor Packet data is generated going toward the CX29704 system side datacom interfaces in the Tx direction on a per port basis The target interface is POS2 Packet length 1 255 byte and inter packet delay 16 8192 clocks is controllable in software The packet genrator operates in either a one shot mode sends 5 packets 1 time or a continuous run mode packets are streamed Packet data consists of fixed byte patterns with each PHY having a differnt pattern The pattern for a PHY is the PHY number PHY1 has pattern
51. re connectors for interfacing standard UTOPIA test equipment Adtech AX4000 Innocor Phymaster to the FPGA Connectors J9 and J10 are connectors for interfacing standard UTOPIA test equipment directly to the CX29704 UTOPIA bus 4 3 5 Power Interface The CX29704 EVM accepts 5V through J3 J4 4 4 Other Interfaces 4 4 1 LEDs The following LEDs are provided e RESET A Green LED indicates hardware reset when illuminated e DUT_RESET A Green LED indicates CX29704 only reset when illuminated e 5V 3 3V DUT 1 5V 1 8V A Green LED indicates that the indicated power supply voltage is above the minimum acceptable value LEDO LED3 Packet ATM FPGA LEDs for development PHYMASTER Indicates J9 and J10 are configured for use with Innocor Phymaster test pods ADTECH Indicates J9 and J10 are configured for use with Adtech AX4000 Utopia test pods UTOPIA Indicates J9 and J10 are configured for operation with ATM test pods POS Indicates J9 and J10 are configured for operation with POS test pods SDO SD3 A Yellow LED indicates receive signal detected at the optical interface The following LEDs are controlled by the CX29704 ASSI interface TXC PO TXC P3 Indicates transmitted cells or packets when illuminated RXC P3 Indicates received cells or packets when illuminated LCDO LCD3 Indicates LOCD when illuminated P SDO P SD3 Indicates P SD when illuminated P SFO Indicates P SF when illuminated LOP
52. remove the reset condition 0x6 ASSI Control Register RW 0x0 7 LED TEST set to 1 to activate all 48 ASSI LEDs Set to 0 for normal operation 6 1 Reserved RW 0x0 0 ASSI DISABLE set to 1 to disable CX29704 ASSI interface set to 0 to enable the ASSI interface 0 7 Diagnostic Data Register RW 0x0 7 0 Generic readable writeable register for diagnostic purposes 29704 EVMD 001 C Mindspeed Technologies 45 Mindspeed Proprietary and Confidential N 6 0 Specifications 6 1 Environmental Conditions Operating Temperature Oto 70 C Storage Temperature 40 to 125 C Relative Humidity 0109590 non condensing 6 2 Power Requirements Voltage 5V DC 5 e Note Additional voltages on EVM are supplied by the on board voltage regulators Current 4 5 Amps maximum 3 8 Amps typical 29704 EVMD 001 C Mindspeed Technologies Mindspeed Proprietary and Confidential 46 N 1 0 Physical Design Description 7 1 Schematics A PDF version of the schematics for the CX29704 EVM are included on the CD ROM They were created using the Innoveda toolset An electronic version of the design is available upon request 7 2 Bill of Materials The components used on the CX29704 EVM are also included in the Bill of Materials spreadsheet on the CD ROM An electronic version of this spreadsheet is available upon request 29704 EVMD 001 C Mindspeed Technologies 47 Mindspeed Proprietary and Confidential C
53. res of those devices 3 2 5 EVM Application Code In the category of miscellaneous additional application code and utilities will be provided on the EVM to integrate the various drivers and software layers Given the independence of the some of the functions on the module some of the high level features of the EVM will be implemented partly on the EVM and partly by software on the host PC 29704 EVMD 001 C Mindspeed Technologies 21 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 3 3 Host Software In addition to the standard Windows operating system running on the host PC a software program will be executed that is specific to the Mindspeed EVM product Similar to the EVM resident software the Host software will include EVM generic software and CX29704 EVM specific software 3 3 1 Communications Protocol A portion of the EVM Host Software is software for communicating with the EVM This software relies on Windows lower layer communications protocols and drivers for transport through the hardware connections to the EVM 3 3 2 Graphical User Interface GUI The user interface for the EVM is a Java based GUI running on a PC and has the following functionality Device configuration and diagnostics Failure monitoring Performance monitoring Low level register read write EVM Test Setup The GUI provides the user with a view into the CX29704TAP software parameters an
54. s si I RR RE E EE ERR RR 8 152 1 NOW EVO E ERA P ERE Ren PRR OX FEX RPG 9 lace EXSUnTEVIM FIR 10 20 Esso Do L IET 11 CREE 0 15 0600 eroa aeaieie er Ea 11 ZAM ERR Ag Sb RAO tA MERERETUR gU Rue 13 2 42 DIN PORTU LaaeeneerrbetbeetereECHEREHRER 13 21 VMI SONG soie aa ERR ERE Ped HU onda 13 214 qose ee RP ERE ED aedes 14 215 Packet ATM FPGA MORE 322222259952 eee Rees 14 DOP RR XE dete HR dede ob eer Op peo 14 22 X29704 Registers Screen 15 221 BS u u acted nace aquqa aqa dc Kh 15 222 NMutltingaregister iius uod dwn ua GRACE GR CR oe ed 16 225 pato u uu u d dics Ee RS upas Rel ARR OCC CA a a waqu 16 23 Packer AITNE FPGA Registers Screen 16 24 Registers sche mid REA Roc Rl 16 29704 EVMD 001 C Mindspeed Technologies ii Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 25 TAP Driver
55. tion of various power schemes that customers may wish to implement Dual regulators for the board 3 3V and CX29704 3 3V are provided to allow individual control of the supply voltages The regulators used are all the same adjustable regulator to minimize the number of different components used They are placed on generic dual TO 263 5 TO 220 5 footprints Removal of R250 allows for placing an ammeter across J1 and J2 to measure the current to the CX29704 device As an additional build option the CX29704 3 3V may be sourced from an external supply 29704 EVMD 001 C Mindspeed Technologies 26 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 4 2 Line Side Interface 4 2 1 Optical Front End The EVM line side interface consists of four Luminent 1310 nm single mode optical transceivers in an SC1x9 package Signal Detect signals from each of the four transceiver modules are indicated by individual LEDs All signals between the transceiver modules and the CX29704 device are LVPECL levels 4 3 Electrical Interfaces 4 3 1 X Signal Description In Table 4 2 the following definitions are used Loc Physical Location of the 1 0 signal Type Classification of signal C 3 3V CMOS compatible input or output CT 3 3V CMOS Tristateable output F DS3 E3 STS 1E facility RS232 compatible input or output E 10 100 BaseT input or output U USB P VDD or VSS Dir
56. un stop function default is run and individual channel enables Note that the POS PHY 2 interface outputs are tristatable to allow other masters on the PCB to communicate with the 29704 Data is continuously accepted by the Packet ATM FPGA POS2 UTOPIA 2 interface in the Rx direction subject to the run stop bit even if the FPGA s buffers are full No back pressure is applied to the POS2 UTOPIA 2 Rx interface One word packets are discarded in the Rx direction Two word or greater length packets are buffered and forwarded normally A limitation is imposed by the minimun packet size of the Innocor PHY Master 5 bytes Packets received with the err signal asserted are buffered and forwarded with the err signal asserted This is true in both Tx and Rx directions Parity is calculated at all the interfaces but NOT buffered Therefore parity errors do not loopback or pass thru the Packet ATM FPGA 5 1 3 2 29704 Side Loopback The Packet ATM FPGA provides POS PHY UTOPIA 2 channelized loopback under SW control Note that the loopbacks pass thru the packet buffers therefore the full packetization function is active while in loopback The loopback muxes also serves as the insertion point for the packet generator to drive packets toward the CX29704 5 1 3 2 1 Internal Block RAM Used as Packet Buffers The Packet ATM FPGA collects packet fragments from the packet interfaces and accumulates them in a buffer until an entire pa
57. ure Fail Def Curr Hist Q i Q LOOP ACT Sw error Fail Def Curr Hist 1 11 M Q FEAC TRANSITION error Fail Def Curr Hist PM Q SEF NA P PM NA FEBE Ex Est ESTE Elapsed Time 00 00 41 29704 EVMD 001 C Failure O Defect 9000000 OK Not Monitored Mindspeed Technologies Mindspeed Proprietary and Confidential 18 CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM POS Framer 2 5 3 X29704 This screen provides access to the performance monitoring parameters in the CX29704 TAP driver Figure 2 7 CX29704 PM Screen M29316 Performance Monitoring Reset Current Previous O O path OPat2 OPatha O path5 O aus 0 O au4 2 O AU4 93 Trib 0 ATM 053 CBIT TCV 45 Min TCV 24Hr 15 Min TCV 24 Hr UHE 0 0 ol 0 ev 0 0 0 CHE nil ol oll 0 ES 45 45 RCVCELLS oal 44 0 56 ol 45 CELLS 0 0 1055 0 0 0 0 LOCD 0 0 0 0 NON MATCHI all 0 9 a 15 TCV 24Hr p FC 0 0 0 0 RCV IU CELLS ol ol 0 0 0 0 XMT JU CELLS 0 0 0 0 0 SES ol 0
58. value 1 The Rx packet monitor detects errors based on packets generated by the FPGA and counts packets 5 1 3 2 6 SRAM Controller External SRAM The SRAM controller provides an interface to an optional external SRAM to allow the Packet ATM FPGA to accommodate more and larger packet buffers The SRAM technology used is ZBT to allow full bandwidth access to the device at 100Mhz The ZBT SRAM uses a single physical data bus so the bus traffic will be approximately 50MHz reads and 50 MHz writes Use of the external SRAM allows 12 32K byte storage buffers in each direction 5 1 3 2 7 Clock and DLL The Packet ATM FPGA uses a free running 100MHz clock provided from an external oscillator and derives a 50MHz clock from that using the Xilinx Virtex II DLLs The derived 50MHz clock is approximately skew free from the 100MHz reference The derived 50MHz clock is driven off the FPGA using a separate DLL The driving DLL assures a the clk data relationship on the PCB falls well within the POS2 spec 5 1 3 3 HDLC SERDES The main purpose of this block is serial to parallel and parallel to serial conversion of full duplex HDLC traffic The traffic path is to from the packet buffers in the Packet ATM FPGA to from the 8260 fast communications controller FCC3 located on the microprocessor plug in card 29704 EVMD 001 C Mindspeed Technologies 39 Mindspeed Proprietary and Confidential CX29704 EVM User Manual OptiPHY F155 STS 3 STM 1 SONET SDH ATM

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