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Datasheet - STMicroelectronics

1. Address Block Register label Register name D 0x005000 PAODR PorAdataoutputlatchregister 0x00 0x00 5001 PA IDR Port A input pin value register OxXX 0x00 5002 PortA PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register oxxx 0x00 5007 Port B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register OxXX 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register OxXX 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 Ky DoclD018576 Rev 7 31 103 Memory and register map STM8S003F3 STM8S003K3 Table 8 I O port hardware register map continued Address Block Register label Register name haaa 0x00 5014 PE ODR P
2. Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz User trimmed with the Accuracy of HSI oscillator GLK_HSITRIMR register 1 02 for given Vpp and Ta itions ACCus conditions oL Vpp 5 V Ta 25 90 l 5 Accuracy of HSI oscillator factory calibrated Vpp 5 V 5 5 40 C lt Tas 85 90 HSI oscillator wakeup p i 2 su HS time including calibration 1 0 la HSI oscillator power p I 3 IDD HSI consumption KO een p 1 See the application note 2 Guaranteed by design not tested in production 3 Data based on characterization results not tested in production Ly DoclD018576 Rev 7 63 103 Electrical characteristics STM8S003F3 STM8S003K3 64 103 Figure 19 Typical HSI frequency variation vs Vpp at 4 temperatures 1 0086 0 5086 0 00 1 5 e accuracy 100 1 5086 2 00 oa 4 45 5 5 5 vM Vect nm n eo Ko a Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 35 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fi si Frequency 128 kHz tsus LSI oscillator wakeup time E 7 Hs lopis LSI oscillator power consumption j 5 HA 1 Guaranteed by design not tested in production Figure 20 Typical LSI frequency variation vs Vpp 4 temperatures 5 07 4 00 3 00 2 0
3. Option bits Factor Option Option p y Addr name bute rio default 6 5 4 3 2 1 0 setting Read out 0x4800 protection OPTO ROP 7 0 0x00 ROP 0x4801 User boot code OPT UBC 7 0 0x00 ox4802 UBC NOPT1 NUBC 7 0 OxFF 0x4803 Alternate OPT2 AFR4 AFR3 AFR2 AFR1 AFRO 0x00 function 0x4804 AFR NOPT2 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO OxFF LSI IWDG WWDG WWDG 0x4805 OPT3 Reserved HSITRIM EN HW HW HALT 0x00 Misc option NHSI NLSI NIWDG NWWDG NWWDG 0x4806 NOPT3 Reserved TRIM EN HW HW HALT OxFF EXT CKAWU PRS PRS 0x4807 OPT4 Reserved CLK SEL C1 CO 0x00 Clock option NEXT NCKAW NPR NPR 0x4808 NOPT4 Reserved CLK USEL SC1 SCO OxFF 0x4809 HSE clock OPT5 HSECNT 7 0 0x00 Ox480A startup NOPT5 NHSECNT 7 0 OxFF Table 13 Option byte description Option byte no Description ROP 7 0 Memory readout protection ROP OPTO OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details 42 108 DoclD018576 Rev 7 STI STM8S003F3 STM8S003K3 Option bytes d Table 13 Option byte description continued Option byte no OPT1 Description UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 defined as UBC memory write protected 0x02 Pages 0 to 1 defined as UBC memory write protected Page 0 and page 1 contain the interrupt vectors Ox7F Pages 0
4. d DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics 3 Data based on characterization results not tested in production ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for IINJ PIN and Zlipu PIN in Section 9 3 6 does not affect the ADC accuracy Table 47 ADC accuracy with RAIN lt 10 ko Rains Vpo 3 3V Symbol Parameter Conditions Typ Max Unit fapc 2 MHz 1 6 3 5 IErl Total unadjusted error fADC 4 MHz 1 9 4 f 2 MHz 1 2 5 Eo Offset error fanc 4 MHz 1 5 2 5 f 2 MHz 1 3 3 Eg Gain error bh RR UN NUR i LSB fADC 4 MHz 2 3 f 2 MHz 0 7 1 0 Ep Differential linearity error S fanc 4 MHz 0 7 1 5 f 2 MHz 0 6 1 5 ELl Integral linearity error ADE TADO 4 MHz 0 8 2 Data based on characterization results not tested in production ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It
5. y life augmented STM8S003F3 STM8S003K3 Value line 16 MHz STM8S 8 bit MCU 8 Kbyte Flash 128 byte data EEPROM 10 bit ADC 3 timers UART SPI 12C Features Core e 16 MHz advanced STMS core with Harvard architecture and 3 stage pipeline e Extended instruction set Memories e Program memory 8 Kbyte Flash memory data retention 20 years at 55 C after 100 cycles e RAM 1 Kbyte e Data memory 128 bytes true data EEPROM endurance up to 100 k write erase cycles Clock reset and supply management e 2 95 V to 5 5 V operating voltage e Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC e Clock security system with clock monitor e Power management Low power modes wait active halt halt Switch off peripheral clocks individually Permanently active low consumption power on and power down reset Interrupt management e Nested interrupt controller with 32 interrupts e Up to 27 external interrupts on 6 vectors September 2015 Datasheet production data mu LQFP32 TSSOP20 UFQFPN20 7x7 mm 6 5x6 4 mm 3x3 mm Timers e Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization e 16 bit general purpose timers with 3 CAPCOM channels IC OC or PWM e 8 bit basic timer with 8 bi
6. eee eee 44 9 Electrical characteristics sss NGABA KABA AA 46 9 1 Parameter CONUMONS sseksseS et NAK psak R RO ela m bcn ded basi kesos 46 9 1 1 Minimum and maximum values 222 00ers 46 9 1 2 Typical values eh 46 9 1 3 Typical GUNES naaa ses sss ALAS sse kosa EEROR EEES ER ER 46 9 1 4 Loading capacitor en 46 9 1 5 Pin input voltage eh 46 9 2 Absolute maximum ratings 0 ee 47 9 3 Operating conditions kaa daa a KUR Re OD Re NA AE eke ob e BANA bu 49 9 3 1 VCAP external capacitor s esles lsesesssol 51 9 3 2 Supply current characteristics sssssss 51 9 3 3 External clock sources and timing characteristics 61 9 3 4 Internal clock sources and timing characteristics 63 9 3 5 Memory characteristics llli 65 9 3 6 I O port pin characteristics cee 66 9 3 7 Reset pin characteristics 00 cece eee eee 75 9 3 8 SPI serial peripheral interface llle 77 9 3 9 IC interface characteristios s ss sssss 80 9 3 10 10 bit ADC characteristics es slsssesssol 82 9 3 11 EMC characteristics l eee 85 10 Package information 4 4X4 aaa nna een dans on ce ea nee epee bode es 88 10 1 LQFP32 package information 0 000 cece ee 88 10 2 TSSOP20 package information 91 10 3 UFQF
7. i 1 8 V regulator capacitor 9 6 VDD S Digital power supply SPI master 7 PASTIM2_ CHS o x x x Hs los x x poraa mere slave select 10 SPI NSS channel 3 AFR1 Timer 1 ME IER vwlx x Ot T9 portE5 ll2Cdaa break input AFR4 ADC 9 PB4I C SCL vol x X lo1 19 PotB4 2c clock external 12 trigger AFR4 Top level interrupt PC3 TIM1_CH3 Timeri AFR3 13 10 TLI I O X X X HS OS X X Port C3 channel3 Timer 1 TIMI CHIN inverted channel 1 AFR7 Ly DoclD018576 Rev 7 27 108 Pinouts and pin descriptions STM8S003F3 STM8S003K3 Table 6 STM8S003F3 pin description continued Pin Input Output no Main Alternate Default ola Pin name Type E funelon ternate function Sez 9 v after after remap Ol amp S 2 F High 8 op pe reset function option bit oo S 3 sink o p ou x n F S Mi Configurable PC4 CLK CCO clock Timer 1 TIM1 output Timer inverted 14 CH4 AIN2 VOX Hs dE A f Fort G4 1 channel channel 2 TIM1_ CH2N 4 Analog AFR7 input 2 Timer 2 15 12 1 0 X X X HS O3 X X PortC5 SPI clock channel 1 i AFRO PC6 SPI MOSI SPI master Timer 1 13 mi VO X X X HS O3 X X Port C6 j channel 1 16 TIM1 CH1 out slave in AFRO PC7 SPI MISO SPI master fimer 1 14 m VO X X X HS O3 X X Port C7 channel 2 17 TIM1 CH2 in slave
8. 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data guaranteed by design not tested in production 3 Data based on characterization results not tested in production 66 103 DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 Electrical characteristics Figure 21 Typical Vj and Vj vs Vpp 4 temperatures Vi ViH V 45 5 5 5 6 Vco V Figure 22 Typical pull up resistance vs Vpp 4 temperatures Pull up resistance ka 25 3 3 5 4 45 5 5 5 6 Von V d DoclD018576 Rev 7 67 103 Electrical characteristics STM8S003F3 STM8S003K3 Figure 23 Typical pull up current vs Vpp 4 temperatures Pull up current HA Von V 1 The pull up is a pure resistor slope goes through 0 Table 39 Output driving current standard ports Symbol Parameter Conditions Min Max Unit VoL Output low level with 8 pins sunk lio 10 MA Vpp 5V 2 7 Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 100 Output high level with 8 pins sourced 1jo 10 mA Vpp 5 V 2 8 Gi Output high level with 4 pins sourced ljo 4 MA Vpp 3 3 V 240 i 1 Data based on characterization results not tested in production Table 40 Output driving current true open drain ports Symbol Parameter Conditions Max Unit lio 10 mA Vpp 5 V 1 VoL
9. Based on a simple application running on the product toggling two LEDs through the I O ports the product is monitored in terms of emission Emission tests conform to the IEC 61967 2 standard for test software board layout and pin loading Table 49 EMI data Conditions 1 Symbol Parameter Max fuse fcpu Unit General conditions Mohitored frequency band 16 MHz 16 MHz 8 MHz 16 MHz Vpp 5V 0 1 MHz to 30 MHz 5 5 Peak level Ta 25 C 30 MHz to 130 MHz 4 5 dBuV EMI LQFP32 package conforming to IEC 130 MHz to 1 GHz 5 5 EMI level 61967 2 2 5 2 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on three different tests ESD DLU and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges one positive then one negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin One model can be simulated the Human Body Model HBM This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 50 ESD absolute maximum r
10. Ly STM8S003F3 K3 value line features llis 10 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers 15 TIMtimerfeatures s sssssssssssreossesossrcosoos 18 Legend abbreviations for STM8S003F3 K3 pin description tables 21 STM8S003K3 descriplions tee 22 STM8S003F3 pindesocriplion ss sss lssssssssssessesse 27 Flash Data EEPROM and RAM boundary addresses sssssol 31 I O port hardware register map I n 31 General hardware register map eee 33 CPU SWIM debug module interrupt controller registers 39 Interrupt mapping 2 0 IRR I AR hh 41 Silio PPP 42 Option byte descriplion sssssssssssssssssssssesoss 42 STM8S003K3 alternate function remapping bits for 32 pin devices 44 STM8S003F3 alternate function remapping bits for 20 pin devices 45 Voltage characteristics l ss RR 47 Current characteristics 20 0 ccc teen eee 48 Thermal characteristics eects 48 General operating conditions llli 49 Operating conditions at power up power down sss s ss 50 Total current consumption with code execution in run mode at Vpp 25V 52 Total current consumption with code execution in run mode at Vpp 2 3 8 V 53 Total current
11. e 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 e 3 individually configurable capture compare channels e PWM mode e Interrupt sources 3 x input capture output compare 1 x overflow update DoclD018576 Rev 7 17 103 Product overview STM8S003F3 STM8S003K3 4 12 TIM4 8 bit basic timer e 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features Counter Timer Counting CAPCOM Complem Ext synchr Timer size Prescaler ne mode channels outputs trigger onization bits ign chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4 13 Analog to digital converter ADC1 STM8S003F3 K3 value line products contain a 10 bit successive approximation A D converter ADC1 with up to 5 external multiplexed input channels and the following main features e Input voltage range 0 to Vppa e Conversion time 14 clock cycles e Single and continuous buffered continuous conversion modes e Buffer size 10 x 10 bits e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Analog watchdog interrupt e External trigger input e Trigger from TIMI TRGO e End of conversion E
12. e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify the user STM8 microcontroller Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of user application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 One free version that outputs up to 16 Kbytes of code is available For more information see www cosmic software com e Haisonance C compiler for STM8 One free version that outputs up to 16 Kbytes of code For more information see www raisonance com e STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows users to assemble and link the user application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards w
13. tt uncuen option bit 2 mc ZO T IX Reset XIX x for x x Port a1 Resonator crystal in DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 Pinouts and pin descriptions d Table 5 STM8S003K3 descriptions continued Input Output c oc z Alternate e alis 58 Default i co o 5S eo f a unction Pin name a D alternate G esasla 3 alo 55 function _ after remap d 5 3 5c 2 or 5 option bit 9 EE 3 PAzOSCOUT V O X X x O1 X x Port a2 Resonator crystal out 4 Vss Digital ground VCAP 1 8 V regulator capacitor Vpo Digital power supply SPI master PA3 TIM2 CH T 2 7 STIMe GS lO X X X HS OS X X Port A3 E slave select SPI NSS channel 3 AFR1 8 PF4 VO X X O1 X Port F4 9 PB7 VOIX xX 101 X X Port B7 10 PB6 VO X X O1 X X Port B6 11 PB5 PC SDA VO X o1 T9 Port B5 I2C data 12 PB4 2C SCL VO X X 01 T X Port BA C clock Analog 13 PESAING VO X X X HS 03 X X Port B3 input 3 Timer 1 TIM1 ETR external trigger Analog PB2 AIN2 input 2 Timer 1 14 TIM1 CH3N VO X X X HS 03 X X Port B2 inverted channel 3 Analog PB1 AIN1 input 1 Timer 1 i 15 TIM1_CH2N VO X X X HS 03 X X Port
14. 32 pin 7 x 7 mm low profile quad flat recommended footprint 89 LQFP32 marking example package top view cece eee eee eee 90 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outline Rn 91 DoclD018576 Rev 7 7 103 List of figures STM8S003F3 STM8S003K3 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 8 103 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package footprint 00 eee ee TSSOP20 marking example package top view sl l UFQFPN20 20 lead 3 x 3 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline eee UFQFPNZO 20 lead 3 x 3 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint llli UFQFPN20 marking example packagetopvieW STM8S003F3 K3 value line ordering information scheme DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 Introduction 1 Introduction This datasheet contains the description of the STM8S003F3 K3 value line features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S and STM8A microcontroller families reference manual RM0016 e For information on programming erasing and protection of the
15. r MISO OUTPUT MSBOUT OUT BIT OUT BOTO f OUT tsu SI AG th Sl md MOSI INPUT MIN BITA IN LSN O ai14135b 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp d 78 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics Figure 40 SPI timing diagram master mode High NSS input tesch 3 CPHA O Y N 5 CPOL 0 i O 1 i 1 i i x CPHA 0 T i 1 n Oo 1 I wn 1 SCK Output OO 32 NA Os l tw SCKH Na pla SCK I 4 i tsu MI a so ret pm MISO sein INPUT i MSBIN IN BITE IN LBN IN me Mania BIT1 OUT Lsour OUT OUTPUT C MsBOUT QUT tv MO a io PNG ai14136c 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp Ly DoclD018576 Rev 7 79 103 Electrical characteristics STM8S003F3 STM8S003K3 9 3 9 I2C interface characteristics Table 44 I C characteristics Standard mode lC Fast mode 12C Symbol Parameter Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 E us tw SCLH SCL clock high time 4 0 0 6 tu spA SDA setup time 250 100 trspa SDA data hold time o9 o9 900G SDA SDA and SCL rise time i 1000 300 n lscL WSDA SDA and SCL fall time 300 300 tiscL thista START condition hold time 4 0 0 6 us tsusTAy Repeated START condition setup
16. z E PD1 HS SWIM PC7 HSySPI MISO TIM1 CH2 PCe HS SPI MOSI TIM1 CH1 PC5 HS SPI SCK TIM2 CH1 PCA HS TIM1 CH4 CLK CCO AINZ TIM1 CH2N MS36409V1 HS high sink capability T True open drain P buffer and protection diode to VDD not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Pinouts and pin descriptions Table 6 STM8S003F3 pin description en Input Output no I Main Alternate Default o9 T function function Qis Pin name Type o alternate A 2 e 2 o after B after remap s 2 High op PP reset THON roption bit o6 8 3 4 sik o P o LL x 0 F 5 Li Timer 2 PD4 BEEP channel 1 18 TIM2 CH1 VO X X X HS O3 X X Port D4 1 BEEP UART1 CK output UART1 clock Analog input 2 19 PDS AINS VO X X X HS O3 X X Port D5 5 UART1 UART1 TX data transmit Analog input PD6 AIN6 3 20 UART1 RX VO X X X HS OS X X Port D6 6 UART1 data receive 4 1 NRST VO X Reset 5 2 PA OSCINDO vo XI X X o1 x x portan Pesonator crystal in 6 3 Paz 0scout o X X x lot x x Portae Resonator crystal out 7 4 VSS S Digital ground 8 5 VCAP S
17. 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 ADC HTRH ADC high threshold register high 0x03 0x00 5409 ADC HTRL ADC high threshold register low OxFF 0x00 540A ADC LTRH ADC low threshold register high 0x00 0x00 540B ADC LTRL ADC low threshold register low 0x00 0x00 540C ADC AWSRH ADC analog watchdog status register high 0x00 0x00 540D ADC AWSRL ADC analog watchdog status register low 0x00 0x00 540E ADC AWCRH ADC analog watchdog control register high 0x00 0x00 540F ADC AWCRL ADC analog watchdog control register low 0x00 e Reserved area 1008 byte 1 Depends on the previous reset source 2 Write only register d 38 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Memory and register map 6 2 3 CPU SWIM debug module interrupt controller registers Table 10 CPU SWIM debug module interrupt controller registers Address Block Register Label Register Name indi 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F
18. 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles 0xD2 8 HSE cycles OxE1 0 5 HSE cycles DoclD018576 Rev 7 43 103 Option bytes STM8S003F3 STM8S003K3 8 1 Alternate function remapping bits Table 14 STM8S003K3 alternate function remapping bits for 32 pin devices Option byte number Description AFR7Alternate function remapping option 7 Reserved AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive default alternate function 1 Port D7 alternate function TIM1_CH4 AFR5 Alternate function remapping option 5 0 AFR5 remapping option inactive default alternate function 1 Port DO alternate function CLK_CCO AFR 4 2 Alternate function remapping option 4 2 Reserved AFR1 Alternate function remapping option 1 0 AFR1 remapping option inactive default alternate function 1 Port A3 alternate function SPI_NSS port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option 0 Reserved OPT2 1 Do not use more than one remapping option in the same port It is forbidden to enable both AFR1 and AFRO 2 Refer to the pinout description d 44 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Option bytes Table 15 STM8S003F3 alternate function remapping bits for 20 pin devices Option byte number Description AFR7 Altern
19. 20 Max number of GPIOs I O 28 16 External interrupt pins 27 16 Timer CAPCOM channels 7 7 Timer complementary outputs 3 2 A D converter channels 4 5 High sink I Os 21 12 program 8K 8K RAM byte 1K 1K True data EEPROM byte 1280 128 Peripheral set l Multi purpose timer TIM1 SPI 12C UART Window WDG independent WDG ADC PWM timer TIM2 8 bit timer TIM4 1 Without read while write capability 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Block diagram 3 d Block diagram Figure 1 STM8S003F3 K3 value line block diagram Reset block xaLitomz K gt Clock controller Reset Jun Reset 4 RC int 16 MHz Detector FORE BOR J RCint 128 kHz Clock to peripherals and core lt gt Window WDG STM8 core gt lt Independent WDG Single wire debug interfaci Debug SWIM 8 Kbyte program Flash 128 byte data EEPROM 3 400 Kbit s dum 12C Fi n g E 1 Kbyte RAM o o 5 Up to 8 Mbit s SPI 8 gt gt 16 bit advanced control 4 bakla 3 timer TIM1 3 complementary outputs LIN master Lt SPI emul vent 16 bit Up to bit general purpose timer TIM2 Ke Z GAFGOM channels up to 5 ADC1 lt channels lt 8 bit basic timer TIM4 1 2 4 kHz beep lt Bee
20. A 9 70 4 LJ An noco 7 30 0 80 Values in inches are converted from mm and rounded to 4 decimal digits Io NONG te 16 yo i p 7 30 00000004 UL DULTCULI 9 a 9 70 y 0 50 Figure 45 LQFP32 32 pin 7 x 7 mm low profile quad flat recommended footprint 5V_FP_V2 1 Dimensions are expressed in millimeters DoclD018576 Rev 7 89 103 Package information STM8S003F3 STM8S003K3 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 46 LQFP32 marking example package top view Product 4 identification S T M S 0 0 3 Date code Standard ST logo Revision code Pin 1 identifier MS37767V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 3 90 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Package information 10 2 3 TSSOP20 package information Figure 47 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outlin
21. AIN 10 bit A D AIN 1 conversion TI Capo d 84 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics 9 3 11 3 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimiza
22. Figure 27 Typ Vo Vpp 3 3 V true open drain ports lo mA Figure 28 Typ Vo E Vpp 5 V high sink ports d DoclD018576 Rev 7 71 103 Electrical characteristics STM8S003F3 STM8S003K3 Figure 29 Typ Vo E Vpp 3 3 V high sink ports lo nA Figure 30 Typ Vpp Von E Vpp 5 V standard ports d 72 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics Figure 31 Typ Vpp Von E Vpp 3 3 V standard ports Vov Vou V Vpp Vou V d DoclD018576 Rev 7 73 103 Electrical characteristics STM8S003F3 STM8S003K3 Figure 33 Typ Vpp Von E Vpp 3 3 V high sink ports Voo Vou V 74 103 DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Electrical characteristics 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 42 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VILQNAST NRST input low level voltage 1 0 3 V 0 3 x Vpp Vinwwrst NRST input high level voltage 07xVpp Vpp 0 3 V VOL NAST NRST output low level voltage 1 loi 2 2 mA 0 5 Reuwrst NRST pull up resistor 30 55 80 kQ tepwrsn NRST input filtered p
23. PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 ec PCKEN24 Reserved PCKEN20 Reserved DoclD018576 Rev 7 15 103 Product overview STM8S003F3 STM8S003K3 4 6 4 7 16 103 Power management For efficient power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between the lowest power consumption the fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU a
24. ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACKO is an ST trademark LQFP32 package information Figure 44 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE C E AA LLELELELBLELELET EV i 0 25 mm A Po C GAUGE PLANE Y v r K E E L1 A LLI v 5V ME V2 1 Drawing is not to scale a DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Package information d Table 52 LOFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 z 0 0394 k 0 3 5 Ze 0 3 5 7 ccc 0 100 0 0039 1
25. kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 24 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 1 fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply IpD WFi current in fcpu fMASTER 1 28 125 kHz HSI RC osc 1 6 MHz 0 7 0 88 mA Mall mode foru fuasrn 128 HSI RC osc 16 MHz 8 0 45 0 57 15 625 kHz l i cpu fMasteR 128 LSI RC osc 128 kHz 0 4 0 54 15 625 kHz 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 54 103 DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Electrical characteristics Total current consumption in active halt mode Table 25 Total current consumption in active halt mode at Vpp 5 V Conditions Symbol Parameter Main voltage Typ Basal Unit regulator Flash mode Clock source MVR HSE crystal oscillator 16 MHz 1080 i Operating mode ETE j oscillator 128 kHz 299 260 m HSE oscill Supply current in crystal oscillator 570 IDD H active halt mode 16 MHz pa Power down mode ENE i oscillator 128 kHz 130 209 Operating mode LSI RC oscillator 66 85 on 12
26. level Vss 0 3 x Vpp ILEAK HSE pun HUE Vss lt Vin lt Vpp 1 2 1 HA 1 Data based on characterization results not tested in production Figure 17 HSE external clock source External clock source JUUL MS36489V2 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy d DoclD018576 Rev 7 61 103 Electrical characteristics STM8S003F3 STM8S003K3 Table 33 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit in External high speed oscillator l 1 E 16 MHz frequency Rr Feedback resistor a 5 220 kQ Cc Recommended load capacitance 20 pF C 20 pF I 6 startup fosc 16 MHz 1 6 stabilized 9 Ipp HsE HSE oscillator power consumption mA C 10 pF i 1 6 startup fosc 16 MHz 1 2 stabilized 9 Om Oscillator transconductance 5 mA V tsuHse Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to
27. size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Product overview 4 2 4 3 4 4 3 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 byte ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller e Nested interrupts with three software priority levels e 32 interrupt vectors with hardware priority e Upto 27 external interrupts on six vectors includ
28. that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organization Option bytes Data EEPROM 128 bytes psh Programmable i area from 64 bytes UBC area 1 page up to Remains write protected during IAP 8 Kbytes Low density i OTEN Flash program memory 8 Kbytes Program memory area Write access possible for IAP MS36408V1 Read out protection ROP The read out protection blocks reading and writing from to the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller d 14 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Product overview 4 5 a Clock controller The clock controller distributes the system clock fyasrER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and
29. the device is described in Figure 8 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics Figure 8 Pin input voltage TJ STM8 pin S MN 9 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 16 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage 0 3 6 5 Input voltage on true open drain pins Vss 0 3 6 5 V Vin Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vppl Variations between different power pins 50 T Vssx Vss Variations between all the different ground pins 50 see Absolute maximum VEsD Electrostatic discharge voltage ratings electrical 5 sensitivity on page 86 1 All power Vpp and ground Vss pins must always be connected to the external power supply 2 lINJ PIN must never be exceeded This is implicitly insured if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the liy py value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive inj
30. to 126 defined as UBC memory write protected Other values Pages 0 to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR 7 0 Refer to the following section for alternate function remapping descriptions of bits 7 2 and 1 0 respectively OPT3 HSITRIM high speed internal clock trimming register size 0 3 bit trimming supported in CLK HSITRIMR register 1 4 bit trimming supported in CLK HSITRIMR register LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to
31. voltages are referred to Ves Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 2 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7 Figure 7 Pin loading conditions CT STM8 pin 50pF Pin input voltage The input voltage measurement on a pin of
32. z 0x00 8038 13 TIM2 TIM2 update overflow s 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 Reserved 0x00 8044 16 Reserved 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 EG C interrupt Yes Yes 0x00 8054 20 Reserved 0x00 8058 21 Reserved 0x00 805C 22 Apc ADOI kabi i anog 0x00 8060 23 TIM4 TIM4 update overflow 5 0x00 8064 24 Flash EOP WR PG DIS 0x00 8068 Reseed 0x00 806C to 0x00 807C 1 Except PA1 Ky DoclD018576 Rev 7 41 103 Option bytes STM8S003F3 STM8S003K3 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 12 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 12 Option bytes
33. 0 1 0066 0 00 accuracy 100 200 3 00 410056 500 DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Electrical characteristics 9 3 5 d Memory characteristics RAM and hardware registers Table 36 RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 20 on page 50 for the value of Vir may Flash program memory and data EEPROM General conditions T4 40 to 85 C Table 37 Flash program memory and data EEPROM Symbol Parameter Conditions Min Typ Max Unit Operating voltage all modes execution write erase fopu lt Io MP 2 95 um Li Vpp Standard programming time including erase for byte word block 6 0 6 6 ms 1 byte 4 bytes 64 bytes Fast programming time for 1 block 64 bytes tprog terase Erase time for 1 block 64 bytes 3 0 3 3 ms Erase write cycles 100 program memory Ta 85 C cycles 100k Erase write cycles data memory Data retention program memory after 100 erase write cycles at 20 Ta 85 C Tret 55 C tre Data retention data memory after 10k erase write cycles at Ta 85 C
34. 04 XH X index register high 0x00 0x00 7F05 CPUC XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7F0A CCR Condition code register 0x28 o Reserved area 85 byte 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 dis ITC SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt software priority register 8 OxFF EA Reserved area 2 byte 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 e Reserved area 15 byte Ky DoclD018576 Rev 7 39 103 Memory and register map STM8S003F3 STM8S003K3 Table 10 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name reo Ox007F90 DMBKIRE DMbreakpointiregisterextendedbyte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM
35. 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value Refer to crystal manufacturer for more details 3 Data based on characterization results not tested in production tsu usE is the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 18 HSE oscillator circuit diagram Rm i fuse to core AL HSE ins Re Cu pm I OSCIN 4 dm Resonator LI Consumption control Resonator C OSCOUT L2 STM8 MS36490V3 62 103 DocID018576 Rev 7 Ky STM8S003F3 STM8S003K3 Electrical characteristics HSE oscillator critical gm formula 9merit 2x TI x fuse x Rn 2C0 cy Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification C Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42C 5C Grounded external capacitance Om gt gt Omerit 9 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ty High speed internal RC oscillator HSI Table 34 HSI oscillator characteristics
36. 20 years Data retention data memory after 100 k erase write cycles at Ta 85 C Teer Le i Supply current Flash programming or 7 20 i mA DD erasing for 1 to 128 bytes 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte DoclD018576 Rev 7 65 103 Electrical characteristics STM8S003F3 STM8S003K3 9 3 6 O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 38 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level VIL voltage 0 3 0 3 x Vpp V Input high level Vpo 5V Vin voltage 0 7 x Vpp Vpp 0 3 V V Vhys Hysteresis 700 mV Rou Pull up resistor Vpp 5V Vin Vas 30 55 80 kQ Fast I Os 202 ns tet Rise and fall time Load 50 pF R F o o 10 90 Standard and high sink I Os I I 12502 Load 50 pF Input leakage likg current Vas S VS Vpp 1 HA analog and digital Analog input kg ana e Kia VssS VNS Vpp g 7 250 9 na likg inj an e N Injection current 4 mA 2 i19 uA
37. 3 EMS dalan a NG Tr PAGG a a NG ka KN GALA AOR gn KAN KA 85 DoclD018576 Rev 7 5 103 List of tables STM8S003F3 STM8S003K3 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 6 103 EMI data iln a diay a RN cla a Ped a o t ee Mee 4 86 ESD absolute maximum ratings ssssssssssssssscssvo 86 Electrical sensitivities eee 87 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data 89 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data 0 ete tees 91 UFQFPNZO 20 lead 3 x3 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 0 eect eee 95 Thermal characteristics eeror eria llle n 97 Document revision history 0 2 00 cee eae 102 DoclD018576 Rev 7 Ky STM8S003F3 STM8S003K3 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figu
38. 5 4 224 2 184 214 2 05 4 IDD run HSE MA Figure 12 Typ lpp RUN VS fcpu HSE user external clock Vpp 5 V 254 mA IDD run HSE 0 5 4 Fepu MHz 3 58 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics d run HS IDO I MA Figure 13 Typ lpp RUN VS Vpp HSI RC osc fopy 16 MHz T T T T T T 25 j 3 t 45 5 V ppl IDD WFI HSE mA Vi DoclD018576 Rev 7 59 103 Electrical characteristics STM8S003F3 STM8S003K3 Figure 15 Typ Ipp wri VS fcpu HSE user external clock Vpp 5 V 14 02 Oo 1 I 0 8 l a O 06 04 0 2 0 T T T T T T T 2 4 6 8 10 12 14 16 18 Fepu MHz Figure 16 Typ Ipp wri VS Vpp HSI RC osc fcpy 16 MHz 17 Es BB 5 8 5 6 8 8 8 a 2 1 5 LL e dp H 0 4 r 9 4 gt ia 13 12 14 1 25 3 3 5 4 45 5 5 5 6 d 60 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T Table 32 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit oe ead ian clock source 0 16 MHz Vage input pin high level i 0 7 x Vpp Vpp 0 3 V Vase t input pin low
39. 7 8 C 102 8 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Part numbering 11 Part numbering Figure 53 STM8S003F3 K3 value line ordering information scheme Example STM8 S 003 K 3 T 6 TR Product class STMS microcontroller Family type S standard Sub family type 00x Value line sub family 003 low density Pin count F 20 pins K 32 pins Program memory size 3 8 Kbyte Package type T LOFP P TSSOP U UFQFPN Temperature range 6 40 C to 85 C Package pitch No character 0 5 mm or 0 65 mm C 0 8 mm 9 Packing No character Tray or tube TR Tape and reel 1 Fora list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you Refer to Table 1 STM8S003F3 K3 value line features for detailed description TSSOP and UFQFPN packages LQFP package d DoclD018576 Rev 7 99 103 STMS development tools STM8S003F3 STM8S003K3 12 12 1 100 103 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool p
40. 7F 0x00 50D2 WWDG WR WWDR window register Ox7F e Reserved area 13 byte 0x00 50EO IWDG KR IWDG key register OxXX 2 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF peg Reserved area 13 byte 0x00 5OFO AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP_CSR BEEP control status register Ox1F Wara Reserved area 12 byte 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 pa SPI SR SPI status register 0x02 0x00 5204 SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF Ee rg Reserved area 8 byte 0x00 5210 l2C CR1 I2C control register 1 0x00 0x00 5211 I2C CR2 I2C control register 2 0x00 0x00 5212 o I2C FREQR I2C frequency register 0x00 0x00 5213 l2C OARL I2C own address register low 0x00 0x00 5214 l2C OARH I2C own address register high 0x00 0x00 5215 Reserved 34 103 DoclD018576 Rev 7 Ky STM8S003F3 STM8S003K3 Memory and register map Table 9 General hardware register map continued Addre
41. 8 kH Power down mode 128 kHz 10 20 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 26 Total current consumption in active halt mode at Vpp 3 3 V Conditions Max Symbol Parameter Main voltage Typ C Unit regulator Flash mode Clock source 1 MVR HSE crystal osc 16 MHz 550 Operating mode 6 LSI RC osc 128 kHz 200 260 n Supply current HSE crystal osc 16 MHz 970 Ipp aH lin active halt Power down mode HA mode LSI RC osc 128 kHz 150 200 Operating mode 66 80 Off k LSI RC osc 128 kHz Power down mode 10 18 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register d DoclD018576 Rev 7 55 103 Electrical characteristics STM8S003F3 STM8S003K3 Total current consumption in halt mode Table 27 Total current consumption in halt mode at Vpp 2 5 V Max at 85 C 1 Unit Symbol Parameter Conditions Typ Flash in operating mode HSI 63 75 i sigi F clock after wakeup upply current in halt mode u RDIM Flash in power down mode HSI 6 0 20 clock after wakeup 1 Data based on characterization results not tested in production Table 28 Total current consumption in
42. B1 ihv rt d channel 2 Analog PBO AINO input 0 Timer 1 16 TIM1 CHIN VO X X X HS 03 X X Port BO invaded channel 1 SPI 17 PE5 SPI NSS lO X X X HS OS X X Port E5 master slave select Timer 1 18 VO X X X HS 03 X X Port C1 channel 1 UART1 clock 19 PC2 TIML cH2 O X X X HS O8 X X Port c2 fimer t channel 2 20 PC3 TIMM cH3 O X X X HS O3 X X Portes TMe 1 channel 3 DoclD018576 Rev 7 23 103 Pinouts and pin descriptions STM8S003F3 STM8S003K3 24 103 Table 5 STM8S003K3 descriptions continued Input Output c o Alternate N E 50 Default o o o T Pin name a p e x se alternate function g Flz a g al lale Zg function after remap d 5 2 8 lt 2 or 5 option bit oe D IE Timer 1 PC4 TIM1_CH4 C channel 21 lik cco VO x x x Hs 03 X X Port c4 ie clock output 22 Pcs sPIsSck olx X X Hs 03 X X Port C5 SPI clock 23 pce sPLMosi O X X X HS O3 X X Port ce SP master out slave in SPI master in 24 PC7 SPI MISO O X X X IHS O3 X X Port C7 slave out Configurable 25 oe vol x x x HS O3 x x Port DO baka Kasa clock output eee p AFR5 26 PD1 SWIM vol x x X lus 04 x X Port p1 SWIM data interface PD2 Timer 2 DP ocu vo x x X Hs 03 X X Port D2 F channel 3 ME GHIS AFR1 Timer 2 og PDSITIM2 CH2 To x x x luslo3 X X Port
43. D3 channel2 ADC ADC ETA i external trigger Timer 2 29 CHE vo X x X Hs 03 X X Port D4 channel 1 BEEP output 30 PD5 UART1_TX l O X X X HS O8 X X Port ps VARTI data transmit 31 PD6 UART1_RX vo X X X HS O8 X X Port De VARTI data receive Timer 1 32 PD7 TLI vol x x X HS O8 X X Port p7 10 level channel 4 TIM1 CH4 interrupt AFR6 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings given in Section 9 Electrical characteristics When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented The PD1 pin is in input pull up during the reset phase and after the internal reset release DoclD018576 Rev 7 a STM8S003F3 STM8S003K3 Pinouts and pin descriptions 5 2 STM8S003F3 TSSOP20 UFQFPN20 pinout and pin description Figure 4 STM8S003F3 TSSOP20 pinout UART1_CK TIM2_CH1 BEEP HS PD4 UART1_TX AIN5 HS PD5 UART1 RX AIN6
44. Drawing is not to scale 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Package information Table 54 UFQFPN20 20 lead 3 x3 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 Al 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 060 D 3 000 0 1181 3 000 3 0 1181 3 L1 0 500 0 550 0 600 0 0197 0 0217 0 0236 L2 0 300 0 350 0 400 0 0118 0 0138 0 0157 L3 0 375 0 0148 L4 0 200 0 0079 L5 0 150 0 0059 b 0 180 0 250 0 300 0 0071 0 0098 0 0118 e 0 500 0 0197 ddd 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 51 UFQFPN20 20 lead 3 x 3 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 4 ost er 0 50 0 50 A0A5 FP V2 1 3 Dimensions are expressed in millimeters DoclD018576 Rev 7 95 103 Package information STM8S003F3 STM8S003K3 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 52 UFQFPN20 marking example packag
45. Figure 48 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package footprint 7 10 4 40 E JUL 0 25 kaa ar 1 0 25 1 d 1 35 E DOO 0 40 0 65 poong YA FP V1 1 Dimensions are expressed in millimeters DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 49 TSSOP20 marking example package top view Standard ST logo Product identification Pin 1 identifier Revision code MS37768V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 3 DoclD018576 Rev 7 93 103 Package information STM8S003F3 STM8S003K3 10 3 94 103 UFQFPN20 package information Figure 50 UFQFPN20 20 lead 3 x 3 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline D Pin 1 E TOP VIEW C ddd A3 A1 BOTTOM VIEW A SIDE VIEW A0A5_ME_V3 1
46. HS PD6 NRST OSCIN PA1 OSCOUTIPA2 Vss VCAP VDD SPI NSS TIM2 CH3 HS PA3 O o N O O AR Oo N a o 20 19 18 17 16 15 14 13 12 11 DUIUDUDUDUU UO PD3 HSYAIN4 TIM2 CH2 ADC ETR PD2 HS AIN3 TIM2_CH3 PD1 HS SWIM PC7 HS SPI_MISO TIM1 CH2 PC6 HS SPI_MOSI TIM1 CH1 PC5 HS SPI_SCK TIM2 CH1 PC4 HS TIM1 CH4 CLK CCO AIN2 TIM1 CH2N PC3 HS TIM1 CH3 TLI TIM1 CH1N PB4 T I2C SCL ADC ETR PB5 T I2C SDA TIM1 BKIN MS37741V1 d HS high sink capability T True open drain P buffer and protection diode to VDD not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function DoclD018576 Rev 7 25 103 Pinouts and pin descriptions STM8S003F3 STM8S003K3 26 103 Figure 5 STM8S003F3 UFQFPN20 pinout NRST OSCIN PA1 OSCOUT PA2 Vss VCAP Ng koli o B x x5 NN e ne HL I IT Jal o O E EZ aa Y LE 32 5 2a k E o 4 uo X S 2 zu Z z z KO L gx op 00 O0 t rli L o D x o N 8 O a Q Q n LA n nu n 1 4 ot 1 1 pth g td 20 19 18 17 16 1 157 MET 14 7 3 137 4 1207 45 no 6 7 8 9 10 Na NG YT Kk VI a e LO b e a a SE E E m o LLO Loa 3 i o Q o L e vi I O o O O N a q Ji 2 sre E x LLI o m II 4 8 E xa E Z w I 9
47. MHz 0 81 code CPU 7 IMASTER Z executed HSI RC osc 16 MHz 0 7 0 87 from RAM fcpu fuasTER 128 15 625 kHz HSI RC osc 16MHz 8 0 46 0 58 fopy fuasrER 128 kHz LSI RC osc 128 kHz 0 41 0 55 HSE crystal osc 16 MHz 4 fopu fMASTER 16 MHz HSE user ext clock 16 MHz 3 9 4 7 Supply HSI RC osc 16 MHz 3 7 4 5 current in run mode fcpy fmasTER 2 MHz HSI RC osc 16 MHz 8 0 84 1 05 code executed fopu fuasTER 128 125 kHz HSI RC osc 16 MHz 0 72 0 9 from Flash fopy fuAsTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fopu fmasTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 Unit mA 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off a DoclD018576 Rev 7 53 103 Electrical characteristics STM8S003F3 STM8S003K3 Total current consumption in wait mode Table 23 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 6 fopy fmasTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 Supply HSI RC osc 16 MHz 0 89 1 1 Ipp wri currentin fopy fmastep 128 125 kHz HSI RC osc 16 MHz 0 7 088 MA wait mode fopu fuasTER 128 2 15 625 kHz HSI RC osc 16 MHz 8 0 45 0 57 cPU TMASTER 128 kHz LSI RC osc 128
48. Min Typ Max Unit VDDA 3to 5 5 V 1 4 fanc ADC clock frequency MHz VDDA 4 5to5 5V 1 6 Vain Conversion voltage range Vss Vpp V Internal sample and hold ADO capacitor 3 pF fapc 4 MHz 0 75 tg Sampling time us fADC 6 MHZ n 0 5 tsrag Wakeup time from standby 7 us fapc 4 MHz 3 5 US Total conversion time including T conv sampling time 10 bit resolution fanc 6 MHz Laki 14 1 fapc 1 During the sample time the input capacitance C ay 3 pF max can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tg After the end of the sample time tg changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming Table 46 ADC accuracy with Ramn lt 10 KQ Vpp 5 V Symbol Parameter Conditions Typ Max Unit fapc 2 MHz 1 6 3 5 Ez Total unadjusted error fapo 4 MHz 2 2 4 fapo 6 MHz 2 4 4 5 fapo 2 MHz 14 2 5 Eo Offset error fapo 4 MHz 1 5 3 fapo 6 MHz 1 8 3 fapc 2 MHz 1 5 3 Eg Gain error 9 fano 4 MHz 2 1 3 LSB fApc 6 MHz 2 2 4 fapo 2 MHz 0 7 1 5 Ep Differential linearity error fapo 4 MHz 0 7 1 5 fapo 6 MHz 0 7 1 5 fapc 2 MHz 0 6 1 5 ELI Integral linearity error 2 fapc 4 MHz 0 8 2 fapo 6 MHz 0 8 2
49. OC interrupt Note Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC_DRH ADC_DRL registers 4 14 Communication interfaces The following communication interfaces are implemented e UART1 full feature UART synchronous mode SPI master mode SmartCard mode IrDA mode LIN2 1 master capability e SPI full and half duplex 8 Mbit s e 2C up to 400 Kbit s 18 103 DoclD018576 Rev 7 Ly STM8S003F3 STM8S003K3 Product overview 4 14 1 4 14 2 d UART1 Main features e 1 Mbit s full duplex SCI e SPI emulation e High precision baud rate generator e Smartcard emulation e IrDA SIR encoder decoder e LIN master mode e Single wire half duplex mode Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fepy 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Two receiver wakeup modes A Address bit MSB Idle line interrupt e Transmission error detection with interrupt generation e Parity control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Maximum speed 1 Mbit s at 16 MHz fcpu 16 LIN master mode e Emission generates 13 bit synch break f
50. Output low level with 2 pins sunk lio 10 mA Vpp 3 3 V 1 5 0 V lio 20 mA Vpp 5 V 20 1 Data based on characterization results not tested in production 68 103 DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Electrical characteristics Table 41 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lo 10 mA Vpp 5V 0 8 Vo Output low level with 4 pins sunk lio 10 MA Vpp 3 3 V 1 0 Output low level with 4 pins sunk lio 20 mA Vpp 5 V 150 Output high level with 8 pins sourced lo 10 mA Vpp2 5 V 4 0 E Von Output high level with 4 pins sourced lo 10mA Vpp2 333 V 2140 Output high level with 4 pins sourced lio 20 mA Vpp 5 V 3 3 1 Data based on characterization results not tested in production Typical output level curves Figure 25 to Figure 32 show typical output level curves measured with output on a single pin Figure 24 Typ Vo Vpp 5 V standard ports Vor V lo mA d DoclD018576 Rev 7 69 103 Electrical characteristics STM8S003F3 STM8S003K3 Figure 25 Typ Vo Vpp 3 3 V standard ports lol mA Figure 26 Typ Vo Vpp 5 V true open drain ports Vor V lo mA 70 103 DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Electrical characteristics
51. PN20 package information 94 104 Thermal characteristics sssssssss 97 10 4 14 Reference document 000 cece eee eee 97 10 4 2 Selecting the product temperature range 98 Ky DoclD018576 Rev 7 3 103 Contents STM8S003F3 STM8S003K3 11 Part numbering 1a AA KA KAG 0 eid Cc ca C ORC suk daa 99 12 STM8 development tools 4 cece eee eee eee 100 121 Emulation and in circuit debugging tools 100 12 2 Software NDIS seis screed eeebaeikiseskeksevipesos ee heed bees 101 122 1 STMONOOISOE 1 owe an dod aces Da Eg ON e LA 101 12 2 2 Candassemblytoolchains s 101 12 3 Programming tools 4 42 4454 xor uer ydo Rar io sis sian ue 101 13 Revision history css kun ena oa d Ede se nee RE CUORE I a 102 4 103 DoclD018576 Rev 7 KYI STM8S003F3 STM8S003K3 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48
52. Slave mode after enable edge 27 G Data output hold time th MO Master mode after enable edge 11 1 Values based on design simulation and or characterization results and not tested in production 2 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data Ly DoclD018576 Rev 7 77 103 Electrical characteristics STM8S003F3 STM8S003K3 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z Figure 38 SPI timing diagram slave mode and CPHA 0 NSS input I tSU NSS J4 H te sck th Nss I 1 1 m 1 Ng S CPHA O 5 f N c CPOL 0 1 T I m D tw SCKH 14 i Pa I 1 5 CPHA 0 1 tw SCKL 1 T T o CPOL 1 i i i ta tv so lt gt t80 lg ali tr SCK tdis SO taso B ti SCK l MISO MSB OUT BITO OUT BOT OUT OUTPUT tsu S re MOSI n A PUT a MSB IN BIT IN X ism Y l re this ai14134c Figure 39 SPI timing diagram slave mode and CPHA 1 NSS input Y m I tSU NSS lt gt r te SCK th Nss 4 1 z i 1 3 cPHA 1 J I I J CPOL 0 ec i n i n i S 44 O CPHA 1 twsck hi T 9 CPOL 1 1 E i 1 1 i 1 i H T 60 Pre th SO bag pa SCK ig tdis SO lt lt ta SO
53. Ta 85 C for suffix 6 UFQFPN20 220 mw LQFP32 330 Ta Ambient temperature tor Maximum power dissipation 40 85 suffix version Junction temperature range Ty for 6 suffix version 40 105 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter maximum values must be respected for the full application range 2 This frequency of 1 MHz as a condition for VcAp parameters is given by the design of the internal regulator To calculate Ppmax Ta use the formula Ppmax Tymax TA Oya see Section 10 4 Thermal characteristics on page 97 with the value for T Jmax given in Table 19 above and the value for O j4 given in Table 55 Thermal characteristics Figure 9 fcpumax Versus Vpp fcPu MHz Functionality not guaranteed 16 in this area 1 1 1 1 1 1 ai 12 Supply voltage MS36411V1 DoclD018576 Rev 7 49 103 Electrical characteristics STM8S003F3 STM8S003K3 50 103 Table 20 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 2 oo tvpp us V 1 I Vpp fall time ratel 2 oo Reset release trEMP delay Vpp rising a 1 7 ms Power on reset Vir threshold 2 6 2 7 2 85 V Brown out reset Vir threshold 2 5 2 65 2 8 V Brown out reset VHYS BOR hyst
54. a EEPROM unprotection register 0x00 oer Reserved area 59 byte 0x00 50A0 EXTI CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EE Reserved area 17 byte 0x00 50B3 RST RST SR Reset status register OxXX E Reserved area 12 byte 0x00 50C0 CLK ICKR Internal clock control register 0x01 0x00 50C1 iiaj CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 ed CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte Ky DoclD018576 Rev 7 33 103 Memory and register map STM8S003F3 STM8S003K3 Table 9 General hardware register map continued Address Block Register label Register name aries 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD CLK GLK SWIMCCR SWIM clock control register o E Eee Reserved area 3 byte 0x00 50D1 WWDG CR WWDG control register Ox
55. ackage including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers STice key features e Occurrence and time profiling and code coverage new features e Advanced breakpoints with up to 4
56. ate function remapping option 7 0 AFR7 remapping option inactive default alternate function 1 Port C3 alternate function TIM1 CHIN port C4 alternate function TIM1 CH2N AFR6 Alternate function remapping option 6 Reserved AFR5 Alternate function remapping option 5 Reserved AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive default alternate function 1 Port B4 alternate function ADC ETR port B5 alternate function TIM1_BKIN OPT2 AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive default alternate function 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 Reserved AFR1 Alternate function remapping option 1 2 0 AFR1 remapping option inactive default alternate function 1 Port A3 alternate function SPI_NSS port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option o9 0 AFRO remapping option inactive Default alternate functions 1 Port C5 alternate function TIM2 CH1 port C6 alternate function TIM1 CH1 port C7 alternate function TIM1 CH2 1 Refer to the pinout description 2 Do not use more than one remapping option in the same port It is forbidden to enable both AFR1 and AFRO d DoclD018576 Rev 7 45 103 Electrical characteristics STM8S003F3 STM8S003K3 9 9 1 46 103 Electrical characteristics Parameter conditions Unless otherwise specified all
57. atings Symbol Ratings Conditions Class Maximum Unit value Electrostatic discharge voltage Ta 25 C conforming to VESD HBM Human body model JESD22 A114 A A009 ed Electrostatic discharge voltage Ta 25 C conforming to VESD CDM Charge device model JESD22 C101 i 1099 ki 1 Data based on characterization results not tested in production 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics d Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e Asupply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable I O pin is performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 51 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class TA 85 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard DoclD018576 Rev 7 87 103 Package information STM8S003F3 STM8S003K3 10 10 1 88 103 Package information To meet environmental requirements
58. ays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate function remap option bit AFR7 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time e Encoder mode e interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM2 16 bit general purpose timer e 16 bit autoreload AR up counter
59. breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF Reserved area 5 byte 1 Accessible by debug module only d 40 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Interrupt vector mapping 7 Interrupt vector mapping Table 11 Interrupt mapping lees Description atau om Wakeup om Vector address RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTIS Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 Reserved 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 41 TIM1 Ai A 0x00 8034 12 TIM1 TIM1 capture compare
60. consumption in wait mode at Vpp 5V 54 Total current consumption in wait mode at Vpp 3 8 V a 54 Total current consumption in active halt mode at Vpp 2 5 V eee eee eee eee 55 Total current consumption in active halt mode at Vpp 3 3V a 55 Total current consumption in halt mode at Vpp 25 V eee 56 Total current consumption in halt mode at Vpp 2 3 3V a 56 Wakeup times aa 56 Total current consumption and timing in forced reset state 57 Peripheral current consumption e 57 HSE user external clock characteristics llle 61 HSE oscillator characteristics iliis 62 HSI oscillator characteristics illis 63 LSI oscillator characteristics lille 64 RAM and hardware registers n 65 Flash program memory and data EEPROM 2 2 2222 65 I O static characteristics rh 66 Output driving current standard ports llle 68 Output driving current true open drain poris ssssssssos 68 Output driving current high sink ports liliis 69 NRST pin characteristics lille 75 SPI characteristics stre ced nere eU E Rada t qoi ee ee ee 77 IC characteristics TTT TTTTTTTTTTTTTTTTTTTTTEETTTE 80 ADC characteristics ses mma a aen e nd e ESA ase deed QU RT REL DASS 82 ADC accuracy with RA lt 10kQ Vpp HSV ssslss sss sss sees 82 ADC accuracy with Ran lt 10 KQ Rain Vpp 3 3 V ww ee seso 8
61. counter 2 00 cee eee 17 4 9 BEEDET 3 2aba pamana det baews bass uas ROSS SS KN Sa AKEN TI Qesos 17 410 TIM1 16 bit advanced control timer 17 4 11 TIM2 16 bitgeneralpurposetimer 17 4 12 TIMA 8 bit basic timer csse se o Rm kes onmes 18 4 13 Analog to digital converter ADC1 a 18 4 14 Communication interfaces 0 00 ee 18 4441 UABTI 1c set bo kel sen atte Mink Re Rede Pe eed Re REA Ree 19 434 2 SPI i ies uiis ac nace no Mea eode a Col ica UE a ana Rao aa 19 rk e 20 5 Pinouts and pin descriptions s 21 5 1 STM8S003K3 LQFP32 pinout and pin description 22 5 2 STM8S003F3 TSSOP20 UFQFPN20 pinout and pin description 25 5 3 Alternate function remapping cee eee eee 29 6 Memory and register map 2222 eee eee eee 30 6 1 MEMOMMAD ey srastsn ests seperas cas EO tet 268 bod segas 30 6 2 Register map skasus cot ks ge kas ds ves DE skao sla kas utate 31 2 103 DoclD018576 Rev 7 Ly STM8S003F3 STM8S003K3 Contents 6 2 1 I O port hardware register map 4 31 6 2 2 General hardware register map ss 32 6 2 3 CPU SWIM debug module interrupt controller registers 39 7 Interrupt vector mapping eee iih 41 8 Option DyieS s euintisugaszkdza kU au urta sais NADA katkekkusa 42 8 1 Alternate function remapping bits
62. e SEATING PLANE C GAGE PLANE PIN 1 IDENTIFICATION 1 Drawing is not to scale YA ME V3 Table 53 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 200 0 0472 Al 0 050 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 0 300 0 0075 0 0118 C 0 090 0 200 0 0035 0 0079 plo 6 400 6 500 6 600 0 2520 0 2559 0 2598 E 6 200 6 400 6 600 0 2441 0 2520 0 2598 E16 4 300 4 400 4 500 0 1693 0 1732 0 1772 e 0 650 0 0256 0 450 0 600 0 750 0 0177 0 0236 0 0295 Li E 1 000 s 0 0394 DoclD018576 Rev 7 91 103 Package information STM8S003F3 STM8S003K3 92 103 Table 53 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max k 0 8 0 8 aaa 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal digits 2 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15mm per side 3 Dimension E1 does not include interlead flash or protrusions Interlead flash or protrusions shall not exceed 0 25mm per side
63. e aries 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1 SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1 ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIMI SRI TIM1 status register 1 0x00 0x00 5256 TIM1 SR2 TIM1 status register 2 0x00 0x00 5257 TIM1 EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture compare mode register 3 0x00 0x00 525B TIM1 CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1 CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1 CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIM1 CNTRH TIM1 counter high 0x00 0x00 525F TIM1 CNTRL TIM1 counter low 0x00 0x00 5260 Lu TIM1 PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1 ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1 CCR3H TIM1 capture compare register 3 h
64. e top view Product identification Date code Ha Revision code Dot pin 1 MS37769V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 3 96 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Package information 10 4 10 4 1 d Thermal characteristics The maximum chip junction temperature T max must never exceed the values given in Table 19 General operating conditions The maximum chip junction temperature Timax in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X Oga Where e Tamax is the maximum ambient temperature in C e jpis the package junction to ambient thermal resistance in C W e Ppmax is the sum of Pintmax and P yomax PDmax PINTmax Piomax e PiINTmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power e Pyomax represents the maximum power dissipation on output pins where PyOmax Vor lov Z Vpp Voy loH and taking account of the actual Vo lo and VowlloH of the I Os at low and high level in the ap
65. ection current and the corresponding Viy maximum must always be respected d DoclD018576 Rev 7 47 103 Electrical characteristics STM8S003F3 STM8S003K3 48 103 Table 17 Current characteristics Symbol Ratings Max Unit lvpp Total current into Vpp power lines source 2 100 lyss Total current out of Vss ground lines sink 80 i Output current sunk by any I O and control pin 20 Output current source by any I Os and control pin 20 Injected current on NRST pin 4 lue DO Injected current on OSCIN pin 4 Injected current on any other pin 4 Elingpiny o Total injected current sum of all I O and control pins 9 t20 mA Data based on characterization results not tested in production All power Vpp and ground Vss pins must always be connected to the external supply IiNj piN must never be exceeded This is implicitly insured if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the lyy pin value A positive injection is induced by Viy Vpp while a negative injection is induced by VjysVgs For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another ana
66. eresis g 7 a 7 my 1 Reset is always generated after a temp delay The application must ensure that Vpp is still above the minimum operating voltage Vpp min when the trepp delay has elapsed DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 Electrical characteristics 9 3 1 9 3 2 d VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cex to the Vcap pin Cgxr is specified in Table 19 Care should be taken to limit the series inductance to less than 15 nH Figure 10 External capacitor C xr FS STA aet DOO Pen TOMBAKO seas 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as described in Section 9 1 5 Pin input voltage Total current consumption in run mode The MCU is placed under the following conditions e All I O pins in input mode with a static value at Vpp or Vas no load e All peripherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and Ta DoclD018576 Rev 7 51 103 Electrical characteristics STM8S003F3 STM8S003K3 Table 21 Total current consumption with code execution in run mode at Vpp 5 V S
67. forced reset state Table 30 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state Loj ras HA Vpp 3 3 V 300 tREsETBL Reset pin release to vector fetch 150 us 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vgs Current consumption of on chip peripherals Subject to general operating conditions for Vpp and Ta HSI internal RC fopu fMASTER 16 MHz VDD 5 V Table 31 Peripheral current consumption Symbol Parameter Typ Unit Ibom TIM1 supply current 210 lpo riw TIM2 supply current 130 Ipp rima TIM4 timer supply current 50 Ipp uanri UARTI supply current 120 Ipp sPI SPI supply current 45 uA Ipp i2C I2C supply current 65 Ippapct ADC1 supply current when converting 1000 d 16 MHz No IC OC programmed no I O pads toggling Not tested in production DoclD018576 Rev 7 Data based on a differential lh measurement between reset configuration and timer counter running at 57 103 Electrical characteristics STM8S003F3 STM8S003K3 Current consumption curves The following figures show the typical current consumption measured with code executing in RAM Figure 11 Typ lpp RUN VS Vpp HSE user external clock fcpy 16 MHz 25 C 23 85 C 45 C 2 2
68. halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Unit Flash in operating mode HSI clock 60 75 Sini after wakeup A DD H upply current in halt mode u qe Flash in power down mode HSI 45 17 clock after wakeup i 1 Data based on characterization results not tested in production Low power mode wakeup times Table 29 Wakeup times Symbol Parameter Conditions Typ Max Unit 2 t Wakeup time from wait 0 to 16 MHz 2 a WU WFI 3 WF mode to run mode 15 fasten 16 MHz 0 56 Flash in operating 1 6 7 6 mode MVR voltage 4 regulator on Flash in power down 3 6 5 2 i Wakeup time active halt mode HSI after iis WU AH 3 U AH mode to run mode Flash in operating Wakeup 4g 5 2 MVR voltage mode At regulator off Flashin power down 50 6 i model Wakeup time from halt Flash in operating mode 52 WU H 3 um mode to run mode Flash in power down mode 54 1 Data guaranteed by design not tested in production 2 twu wri 2 X 1 fmaster 7 X 1 fcpu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization d 56 103 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics Total current consumption and timing in
69. hich provide dedicated programming platforms with sockets for programming the user STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STMB8 family DoclD018576 Rev 7 101 103 Revision history STM8S003F3 STM8S003K3 13 102 103 Revision history Table 56 Document revision history Date 12 Jul 2011 Revision 1 Changes Initial release 09 Jan 2012 Added Npy and tper for data EEPROM in Table Flash program memory and data EEPROM Updated Rpy in Table NAST pin characteristics and Table I O static characteristics Updated notes related to VcAp in Table General operating conditions 12 Jun 2012 Updated temperature condition for factory calibrated ACCyg in Table HSI oscillator characteristics Changed SCK input to SCK output in Figure SPI timing diagram master mode Modified Figure 20 lead ultra thin fine pitch quad flat no lead package outline 3 x 3 to add the package top view 18 Dec 2014 Updated the package information for the 20 pin TSSOP and the 20 pin UFQFPN 21 Apr 2015 Added package marking examples in Section Package information Figure LQFP32 marking example package top view Figure TSSOP20 marking example package top view Figure UFQFPN20 marking example package top view 26 Jun 2015 Addit
70. ical characteristics Figure 37 Recommended reset pin protection ox konono eon m e Poo teo sxem I Mp HOT Mp RHO xonexpmmsseo ore 4 2065 D gt fe Sesay 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 43 are derived from tests performed under ambient temperature fyaster frequency and Vpp supply voltage conditions tMASTER 1 MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 43 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 8 SCK SPI clock frequency MHz Vie scK Slave mode 0 7 SCK SPI clock rise and fall time Capacitive load C 30 pF 25 lsck tsunss NSS setup time Slave mode 4 X MASTER tss NSS hold time Slave mode 70 1 pisc SCK high and low time Master mode tsck 2 15 tgck 2 4 15 w SCKL t 1 Master mode 5 su MI 4 Data input setup time tsuSl Slave mode 5 1 Master mode 7 ns thm Data input hold time this Slave mode 10 teo Data output access time Slave mode 3 x IVASTER taisoy 9 Data output disable time Slave mode 25 tuso 1 Data output valid time Slave mode after enable edge 65 tumo Data output valid time Master mode after enable edge 30 tnso
71. igh 0x00 0x00 526A TIM1 CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1 CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1 CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1 BKR TIM1 break register 0x00 0x00 526E TIM1 DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state register 0x00 a E Reserved area 147 byte 36 103 DoclD018576 Rev 7 Ky STM8S003F3 STM8S003K3 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ue 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 Reserved 0x00 5302 Reserved 0x00 5303 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5304 TIM2 SR1 TIM2 status register 1 0x00 0x00 5305 TIM2 SR2 TIM2 status register 2 0x00 0x00 5306 TIM2 EGR TIM2 event generation register 0x00 0x00 5307 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5308 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5309 TIM2 CCMR3 TIM2 capture compare mode register 3 0x00 0x00 530A TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 530B TIM2 TIM2 CCER2 TIM2 capture compare enable register 2 0x00 0x00 530C TIM2 CNTRH TIM2 counter high 0x00 0x00 530D TIM2 CNTRL TIM2 coun
72. ing TLI e Trap and reset interrupts Flash program memory and data EEPROM e 8Kbyte of Flash program single voltage Flash memory e 128 byte true data EEPROM e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to modify the content of main program memory and data EEPROM or to reprogram the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 DoclD018576 Rev 7 13 103 Product overview STM8S003F3 STM8S003K3 The size of the UBC is programmable through the UBC option byte Table 13 in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory 8 Kbyte minus UBC e User specific boot code UBC Configurable up to 8 Kbyte The UBC area remains write protected during in application programming This means
73. internal Flash memory please refer to the PM0051 How to program STM8S and STM8A Flash program memory and data EEPROM e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STMB core please refer to the STM8 CPU programming manual PM0044 3 DoclD018576 Rev 7 9 103 Description STM8S003F3 STM8S003K3 2 10 103 Description The STM8S003F3 K3 value line 8 bit microcontrollers offer 8 Kbytes of Flash program memory plus integrated true data EEPROM They are referred to as low density devices in the STM8S microcontroller family reference manual RM0016 TheSTM8S003F3 K3 value line devices provide the following benefits performance robustness and reduced system cost Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write erase cycles advanced core and peripherals made in a state of the art technology at 16 MHz clock frequency robust I Os independent watchdogs with separate clock source and a clock security system The system cost is reduced thanks to a high system integration level with internal clock oscillators watchdog and brown out reset Full documentation is offered as well as a wide choice of development tools Table 1 STM8S003F3 K3 value line features Features STM8S003K3 STM8S003F3 Pin count 32
74. ion of the footnotes about D and E1 dimensions to Table 53 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data Update of the standard for EMI characteristics in Section Electromagnetic interference EMI 23 Sep 2015 Correction of UART peripheral in Figure 1 STM8S003F3 K3 value line block diagram DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes a
75. is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lijy pin and Zliny Pin in Section 9 3 6 does not affect the ADC accuracy DoclD018576 Rev 7 83 103 Electrical characteristics STM8S003F3 STM8S003K3 Figure 42 ADC accuracy characteristics A i EG i Pai ud im PA 1LSB iei E e 7 t 1021 IDEAL 1024 E A Bf e i E ke 7 pt 14 3 i TI 1 A 1 LI 64 E NN ES LA B Eo d Pa E l 4 1 AZ 1 1 1 4 ez i 1 1 LA 1 34 L Ep 25 lt gt 1d z ing 1 LSBipEAL l l l l I l 0 1 2 3 4 5 6 7 1021102210231024 Vssa VDDA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Ey Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 43 Typical application with ADC Vpp STM8 R v qe
76. levels of conditions e Data breakpoints e Program and data trace recording up to 128 KB records e HRead write on the fly of memory during emulation e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer e 1 input and 2 output triggers e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 STMS development tools 12 2 12 2 1 12 2 2 12 3 d Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 A free version that outputs up to 16 Kbytes of code is available STMS toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST Visual Develop Full featured integrated development environment from ST featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management
77. log input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for linJ pin and XliNj piN in the I O port pin characteristics section does not affect the ADC accuracy When several inputs are submitted to a current injection the maximum 2liy pi is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with ZligycPIN maximum current injection on four I O port pins of the device Table 18 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 de Tj Maximum junction temperature 150 d DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electrical characteristics 9 3 a Operating conditions The device must be used in operating conditions that respect the parameters in Table 19 In addition full account must be taken of all physical capacitor characteristics and tolerances Table 19 General operating conditions Symbol Parameter Conditions Min Max Unit fcpu Internal CPU clock frequency 5 0 16 MHz Vpp Standard operating voltage 2 95 5 5 V CEXT capacitance of external l 470 3300 nF capacitor 1 VCAP ESR of external capacitor E 0 3 ohm At 1 MHz ESL of external capacitor 15 nH TSSOP20 238 3 Power dissipation at Pp
78. nd peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout at 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window the down counter is refreshed before its value is lower than the one stored in the window register d DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Product overview 4 8 4 9 4 10 4 11 3 independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus st
79. nd replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 3 DoclD018576 Rev 7 103 103
80. o longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 DoclD018576 Rev 7 29 103 Memory and register map STM8S003F3 STM8S003K3 6 Memory and register map 6 1 Memory map Figure 6 Memory map 0x00 0000 RAM 1 Kbyte 513 byte stack 0x00 03FF 0x00 0800 0x00 4000 Data EEPROM omar Reseved 0x00 47FF aos Option bytes 0x00 480A 0x00 480B 0x00 4FFF NEA 0x00 5000 GPIO and periph reg 0x00 57FF 0x00 5800 0x00 7EFF EP KABABA CPU SWIM debug ITC registers 0x00 7FFF 0x00 6000 32 interrupt vectors 0x00 807F 0x00 8080 Flash program memory 0x00 9FFF 8 Kbyte 0x00 A000 0x02 7FFF MS36410V1 30 103 DocID018576 Rev 7 Ly STM8S003F3 STM8S003K3 Memory and register map Table 7 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case Table 7 Flash Data EEPROM and RAM boundary addresses Memory area Size byte Start address End address Flash program memory 8K 0x00 8000 0x00 9FFF RAM 1K 0x00 0000 0x00 O3FF Data EEPROM 128 0x00 4000 0x00 407F 6 2 Register map 6 2 1 O port hardware register map Table 8 I O port hardware register map
81. ort E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register oxxx 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register OxXX 1 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 1 Depends on the external circuitry 6 2 2 General hardware register map 32 103 DoclD018576 Rev 7 Ky STM8S003F3 STM8S003K3 Memory and register map Table 9 General hardware register map Address Block Register label Register name a Es Reserved area 60 byte 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash in application programming status 0x00 register ys er Reserved area 2 byte 0x00 5062 Flash FLASH PUKR Flash ER Unprotection 0x00 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Dat
82. out AFRO 15 PD1 sw Md vo xl X X Hs O4 X X Potpi SWIM data 48 interface Timer 2 ig 16 Ta vo x X x Hs OS x X Port D2 input Channel 3 AFR1 Analog input PD3 AIN4 d ai 20 17 TIM2 CH2 1 0 X X X HS O3 X X Port D3 2 ADC ADC ETR external trigger I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings When the MCU is in halt active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended d to use PA1 only in input mode if halt active halt is used in the application In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to VDD are not implemented The PD1 pin is in input pull up during the reset phase and after internal reset release 28 103 DoclD018576 Rev 7 d STM8S003F3 STM8S003K3 Pinouts and pin descriptions 5 3 3 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes When the remapping option is active the default alternate function is n
83. per AWU timer DoclD018576 Rev 7 11 103 Product overview STM8S003F3 STM8S003K3 4 4 1 12 103 Product overview The following section intends to give an overview of the basic features of the STM8S003F3 K3 value line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains six internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching for most instructions e XandY 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 K level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20 addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80instructions with 2 byte average instruction
84. peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Upto 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock
85. plication Table 55 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient LQFP 32 7 x 7 mm Qe Thermal resistance junction ambient OJA TSSOP20 4 4 mm 84 C W Thermal resistance junction ambient 90 UFQFPN20 3 x 3 mm 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org DoclD018576 Rev 7 97 103 Package information STM8S003F3 STM8S003K3 10 4 2 98 103 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 53 STM8S003F3 K3 value line ordering information scheme 1 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tamax 75 C measured according to JESD5 1 2 e IDDmax 8 mA Vpp 5 0V e Maximum 20 I Os used at the same time in output at low level with lot 8 mA VoL 0 4 V Pintmax 8 MA x 5 0 V 400 mW Ppmax 400 mW 64 mW Thus Ppmax 464 mW Using the values obtained in Section Table 55 Thermal characteristics T jmay is calculated as follows for LQFP32 7 x 7 mm 60 C W Timax 75 C 60 C W x 464 mW 75 C 2
86. rame e Reception detects 11 bit break frame SPI e Maximum speed 8 Mbit s fuasrEp 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e CRC calculation e 1 byte Tx and Rx buffer e Slave master selection input pin DoclD018576 Rev 7 19 103 Product overview STM8S003F3 STM8S003K3 4 14 3 20 103 IC I2C master features Clock generation Start and stop generation IC slave features Programmable I2C address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds A Standard speed up to 100 kHz Fast speed up to 400 kHz 3 DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Pinouts and pin descriptions 5 Pinouts and pin descriptions Table 4 Legend abbreviations for STM8S003F3 K3 pin description tables Type input O output S power supply Input CM CMOS Level Output HS high sink O1 slow up to 2 MHz O2 fast up to 10 MHz Output d pe O3 fast slow programmability with slow as default state after reset O4 fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configuration Output T true open drain OD open drain PP push p
87. re 46 Figure 47 Ly STM8S003F3 K3 value line block diagram sss sss ise 11 Flash memory organization l sss rn 14 STM8S003K3 LQFP32 pinout sss sse e 22 STM8S003F3 TSSOP20 pinout n 25 STM8S003F3 UFQFPN20 pinout e eee 26 Memory Map EE 30 Pin loading conditions seai e 46 PIN input voltage ase ee LUS KG Ru ae RR RU Rab d t UR e RAT RR ee 47 cp max VENSUS VHD se kazaka EN knee deor BA AL DN ee NG Rope ads 49 External capacitor CE r sss sss e raa dinan Rara 51 Typ Ipp RuN VS Vpp HSE user external clock fepy 16 MHz eee eee 58 Typ Ipp Ruw VS fepu HSE user external clock Vpp DV 58 Typ IDD RUN VS Vpp HSI RC OSC fopu 216 MHZ sa GNG RR mem ees 59 Typ Ipp wri VS Vpp HSE user external clock fopy 16MHz a 59 Typ Ipp wri VS fopu HSE user external clock Vpp S V 1 ee eee eee eee 60 Typ IDD WFI VS Vpp HSI RC OSC fcpu 216 MHz ssssssssressesasvas 60 HSE external clock source sss teens 61 HSE oscillatorcircuitdiagram ssi Lssissssssssssissssol 62 Typical HSI frequency variation vs Vpnpatdtemperatures 64 Typical LSI frequency variation vs Vpp 4 temperatures 64 Typical Vj and Vip vs Vpp 4 temperatures esos 67 Typical pull up resistance vs Vpp 4 temperatures s ss ss iss ee 67 Typical pull up current v
88. s Vpp 4 temperatures s ssssss esos 68 Typ Vor 9 Vpp 5 V standard ports 6 0 eee 69 Typ Voi Vpp 3 3 V standard ports 0 eA 70 Typ Voi Vpp 5 V true open drain ports 0 ss ssso 70 Typ Voi Vpp 3 3 V true open drain ports sene 71 Typ VoL Vpp 5 V high sink ports BRI 71 Typ VoL Vpn 3 3 V high Sink ports i eco abe eR RENE y Ead 72 Typ Vpp Vou Vpp 5 V standard ports 2 2 eese 72 Typ Vpp Vou E Vpp 3 3 V standard ports sees 73 Typ Vpp Vou E Vpp 5 V high sink ports 0 ns 73 Typ Vpp Vou Vpp 3 3 V high sink ports lle 74 Typical NRST Vj and Vj vs Vpp 4 temperatures s s ss sse 75 Typical NRST pull up resistance vs Vpp 9 4 temperatures 76 Typical NRST pull up current vs Vpp 4 temperatures s 76 Recommended reset pin protection eae 77 SPI timing diagram slave mode and CPHA 0 0 eens 78 SPI timing diagram slave mode and CPHA TU GANG ska ea pha dae ede en 78 SPI timing diagram master mode METTRE 79 Typical application with I2C bus and timing diagram sss 81 ADC accuracy characteristics sss ssssss es 84 Typical application with ADC i s Ll IIR 84 LQFP32 32 pin 7 x 7 mm low profile quad flatpackage outline 88 LQFP32
89. ss Block Register label Register name ue 0x00 5216 l2C DR IC data register 0x00 0x00 5217 I2C SR1 IC status register 1 0x00 0x00 5218 l2C SR2 I2C status register 2 0x00 0x00 5219 I2C SR3 IC status register 3 0x00 0x00 521A ec l2C ITR oj interrupt control register 0x00 0x00 521B l2C CCRL I2C clock control register low 0x00 0x00 521C l2C CCRH I2C clock control register high 0x00 0x00 521D l2C TRISER IC TRISE register 0x02 0x00 521E l2C PECR ec packet error checking register 0x00 e e Reserved area 17 byte 0x00 5230 UART1 SR UART1 status register OxCO 0x00 5231 UART1 DR UART1 data register OxXX 0x00 5232 UART1 BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1 BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1 CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1 CR2 UART1 control register 2 0x00 0x00 5236 UART1 CR3 UART1 control register 3 0x00 0x00 5237 UART1 CR4 UART1 control register 4 0x00 0x00 5238 UART1 CR5 UART1 control register 5 0x00 0x00 5239 UART1 GTR UART1 guard time register 0x00 0x00 523A UART1 PSCR UART1 prescaler register 0x00 oe ig Reserved area 21 byte Ky DoclD018576 Rev 7 35 103 Memory and register map STM8S003F3 STM8S003K3 Table 9 General hardware register map continued Address Block Register label Register nam
90. t prescaler e Auto wakeup timer e Window and independent watchdog timers Communications interfaces e UART with clock output for synchronous operation SmartCard IrDA LIN master mode e SPlinterface up to 8 Mbit s e IC interface up to 400 Kbit s Analog to digital converter ADC e 10 bit ADC 1 LSB ADC with up to 5 multiplexed channels scan mode and analog watchdog Os e Upto 28 I Os on a 32 pin package including 21 high sink outputs e Highly robust I O design immune against current injection Development support e Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging DoclD018576 Rev 7 1 103 This is information on a product in full production www st com Contents STM8S003F3 STM8S003K3 Contents 1 IMOLUCNON hip Si a AA 9 2 Description sas sen au e ca ti ai ei ica Re REC a E ae 10 3 Block diagram ss sx e xh acu uam OES c acu Rod Ro PA keno 11 4 Product overview c senate aon Qr on OR CR n D t i RC a kak 12 4 1 Central processing unit STM8 ee 12 4 2 Single wire interface module SWIM and debug module DM 13 4 3 Interrupt controller s iab tree l acm ce RR qua LAN NBA 13 4 4 Flash program memory and data EEPROM 13 4 5 Clock controller P CP LITT 15 4 6 Power management s ssssssssssss 16 4 7 Watchdog timers aaa kpa sss eask zazszsjasiu risaisate aso i 16 4 88 Auto wakeup
91. ter low 0x00 0x00 530E TIM2 PSCR TIM2 prescaler register 0x00 0x00 530F TIM2 ARRH TIM2 auto reload register high OxFF 0x00 5310 TIM2 ARRL TIM2 auto reload register low OxFF 0x00 5311 TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5312 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5313 TIM2 CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5314 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5315 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 0x00 5316 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 ue Reserved area 43 byte 0x00 5340 TIM4 CR1 TIM4 control register 1 0x00 0x00 5341 Reserved 0x00 5342 Reserved 0x00 5343 TIM4 IER TIM4 interrupt enable register 0x00 0x00 5344 TIM4 TIM4 SR TIM4 status register 0x00 0x00 5345 TIM4 EGR TIM4 event generation register 0x00 0x00 5346 TIM4 CNTR TIM4 counter 0x00 0x00 5347 TIM4 PSCR TIM4 prescaler register 0x00 0x00 5348 TIM4 ARR TIM4 auto reload register OxFF Ky DoclD018576 Rev 7 37 103 Memory and register map STM8S003F3 STM8S003K3 Table 9 General hardware register map continued Address Block Register label Register name a DE Reserved area 153 byte pores ADC1 ADC DBxR ADC data buffer registers 0x00 e pelt Reserved area 12 byte 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00
92. time 4 7 0 6 lsusro STOP condition setup time 4 0 0 6 Hs STOP to START condition time tw STO STA bus free 4 7 1 3 us Cp Capacitive load for each bus line 400 400 pF faster must be at least 8 MHz to achieve max fast IC speed 400kHz Data based on standard IC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 80 103 DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 Electrical characteristics d Figure 41 Typical application with I C bus and timing diagram VDD VDD START REPEATED I tsu STA pr le NGAY 1 PAG SDA OAK LI tf SDA He Le fr SDA png tsu SDA f i stop m ME STO H 9 h STAJM P lw SCHL gt lt th SDA SCL LT VATA IT 1 1 I tw SCLH i t SCL He T t SCL tsu STO ai17490V2 1 Measurement points are made at CMOS levels 0 3 x Vpp and 0 7 x Vpp DoclD018576 Rev 7 81 103 Electrical characteristics STM8S003F3 STM8S003K3 9 3 10 82 103 10 bit ADC characteristics Subject to general operating conditions for Vppa MASTER and Ta unless otherwise specified Table 45 ADC characteristics Symbol Parameter Conditions
93. tion and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 48 EMS data Symbol Parameter Conditions Level class Voltage limits to be applied on any I O pin to LESS tee VFESD fVASTER 16 MHz 2B induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 3 3 V Ta 25 90 Verte applied through 100pF on Vpp and Ves pins fmaster 16 MHz 4A to induce a functional disturbance conforming to IEC 61000 4 4 1 Data obtained with HSI clock configuration after applying HW recommendations described in AN2860 EMC guidelines for STM8Smicrocontrollers DoclD018576 Rev 7 85 103 Electrical characteristics STM8S003F3 STM8S003K3 Electromagnetic interference EMI
94. ull Bold x pin state after internal reset release Reset state Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release d DoclD018576 Rev 7 21 103 Pinouts and pin descriptions STM8S003F3 STM8S003K3 5 1 22 103 STM8S003K3 LQFP32 pinout and pin description Figure 3 STM8S003K3 LQFP32 pinout NRST OSCIN PA1 OSCOUT PA2 VSS VCAP VDD SPI NSS TIM2 CH3 HS PA3 PF4 E o T s 58 O O alg z S LSF z JJEOO m EBRE ENNS nk t N 3222322 took Ea k NNONDDHD DAD LILILLLIILI oO O t 2 N O O 0 0 0 DD OO A O O O O O na na CE C10 0 0 32 31 30 29 28 27 26 25 10 24 2 23 C13 22 4 21 5 20 6 19 7 18 I8 17 9 1011 12 13 14 15 16 LILILI LT MOL t ON xx o mm mm mmm Logo OO o OD REG D DD ziz OSS oo2222 oi ox NNe 222 DTT a 9 ss x FS p2 23 2 FEFF LT ET ET ET E GJ CHI PC7 HSySPI MISO PC6 HS SPI MOSI PC5 HS SPI_SCK PC4 HS TIM1 CH4 CLK CCO PC3 HS TIM1 CH3 PC2 HS TIM1_CH2 PC1 HSyTIM1 CH1 UART1 CK PE5 HS SPI NSS MS37740V1 Table 5 STM8S003K3 descriptions N o o a Pin name 2 e e 1 INRST VO 2 PA1 OSCINO VO Input Output c oc Ble 33 Defaut Alternate o 2 co function 23 5 8 B pla 25 alternate after remap so 2 3 9 i 3 SE c g Oo
95. ulse 9 75 ns tINFPONAST NRST Input not filtered pulse 500 A ns toewasr NRST output pulse 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 34 Typical NRST Vj and Vj vs Vpp 4 temperatures 40 C 64 m 25 C 85 C 4 3 2 fu mi ne n 1 0 ki T T T T T 25 3 35 4 4 5 5 55 6 Voo v Ly DoclD018576 Rev 7 75 103 Electrical characteristics STM8S003F3 STM8S003K3 76 103 Figure 35 Typical NRST pull up resistance vs Vpp 4 temperatures NRESET pulkup resistor ka NRESET Pul Up current Voo V The reset network shown in Figure 37 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vj max level specified in Table 38 Otherwise the reset is not taken into account internally For power consumption sensitive applications the capacity of the external reset capacitor can be reduced to limit charge discharge current If the NRST signal is used to reset the external circuitry care must be taken of the charge discharge time of the external capacitor to fulfill the external device s reset timing conditions The minimum recommended capacity is 10 nF d DoclD018576 Rev 7 STM8S003F3 STM8S003K3 Electr
96. ymbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 3 fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 2 2 35 pp HSI RC osc 16 MHz 17 2 current in run mode a HSE user ext clock 16 MHz 0 86 PU IMASTER z aa g 5 HSI RC osc 16 MHz 0 7 0 87 from RAM fopy fmasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fopy MASTER 128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN mA HSE crystal osc 16 MHz 4 5 fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 4 3 4 75 APRO HSI RC osc 16 MHz 37 45 current in run mode fopy fMASTER 2 MHz HSI RC osc 16 MHz 8 0 84 1 05 code executed fopy fMmasTER 128 125 kHz HSI RC osc 16 MHz 0 72 0 9 from Flash fopy fuAsTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fopy fMasrER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 52 103 DoclD018576 Rev 7 3 STM8S003F3 STM8S003K3 Electrical characteristics Table 22 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol IDD RUN Parameter Conditions Typ Max HSE crystal osc 16 MHz 1 8 fopu fuasrER 16 MHz HSE user ext clock 16 MHz 2 2 3 Supply HSI RC osc 16 MHz 1 5 2 current in run mode HSE user ext clock 16

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