MICRONAS
Contents
1. 00 I2CWS10 I2CWS00 Micronas June 30 2003 6251 609 2 29 3231G C ADVANCE INFORMATION Table 9 5 Base address 0x00F90400 Offs Byte Address Remarks 3 2 1 0 Module OxOFC HxPIN H Port7 H Ports OxOF8 HxLVL HxNS Ox0F4 reserved for OxOFO H Port6 OxOEC H Port5 0x0E8 HxLVL HxNS 0x0E4 ui FNS esse reserved for 0x0C4 H Port0 FNS 2 P Porti P Port 0 reserved U Ports 0 084 UxSLOW UxDPM UxD UXMODE UxSLOW UxDPM UxD UxMODE UxSLOW Ox060 UxDPM UxNS 0x054 UxMODE UxPIN UxSLOW UxDPM UxD UxMODE UxSLOW UxDPM UxD UxMODE UxSLOW 0x030 UxDPM UxNS 0x024 UxMODE UxPIN UxLVL UxSLOW UxDPM UxD UxMODE UxSLOW UxDPM UxD UxMODE UxSLOW 30 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C Table 9 6 Base address 0x00F90500 Offs Byte Address Remarks 3 1 0 Module OxOFC 128 Bytes reserved 0x080 0x07C SMX Power Saving 0x078 POL Polling ATCC RTC Wake Ports mode Wake up source 0x03C 0x030 0x01C 0 014 ULCDLD reserved Clock PLL ERM reserved GBus LCD Patch Micronas June 30 2003 6251 609 2 31 3231G C ADVANCE INFORMATION 9 2 32 Bit VO Region Table 9 7 Base ad2. Table 3 2 All voltages listed are referenced to ground UVss HVssn AVss 0V except where noted All grounds except VSS must be connected externally lovv ohmic Symbol Parameter Pin Name Min Typ Max Unit Vsup Main Supply Voltage UVDD AVDD 3 5 Analog Supply Voltage SM Supply Voltage HVDDn 4 75 5 5 V 5 25 V 200 mV Ripple Peak to Peak dVpp dt Supply Voltage Up Down Ramping Rate 20 V us XTAL Clock Frequency MHz fxTAL CPU Clock Frequency PLL on For a list of available settings see Tables 4 1 and 4 2 fgus Program Storage Clock Fre quency PLL on Vi Automotive Low Input Voltage see Table 2 2 for a list of input types and their supply volt CMOS Low Input Voltage U Ports TEST ages TEST2 H Ports P Ports 0 5 xVpp V 0 3 xVpp V Vin Automotive High Input Voltage U Ports 0 86 xVpp see Table 2 2 H Ports for a list of input P Ports types and their supply volt CMOS High Input Voltage U Ports TEST ages TEST2 H Ports P Ports Reset Active Input Voltage RESETQ 0 75 V WRV Reset Active Input Voltage during RESETQ Power Saving Modes and Wake Reset 0 4 V RVim Reset Inactive and Alarm Active RESETQ Input Voltage 2 3 V Reset Inactive and Alarm Inactive RESETQ Input Voltage Reset Inactive Input Voltage dur RESETQ ing Povver Saving Modes and VVake Reset lt lt lt 12 30 2003 6251 609 2 Microna
3. oo Ox00C ESM REC OCR 0x008 ICR BT3 BT2 BT1 0x004 IDM 0x000 IDX ESTR STR CTR Micronas June 30 2003 6251 609 2 27 3231G C ADVANCE INFORMATION Table 9 3 Base address 0x00F90000 formerly 1200 Offs Byte Address Remarks 3 2 1 0 Module OxOFC TST2 TST1 TST3 TST4 Test 0x0F8 TST5 __ TSTAD3 TSTAD2 0x0F4 reserved for DIGITBus ADC UARTO UAOBR1 UAOBRO 0 07 CCCOH CCCOL CAPCOMO Ox068 8 byte 0 064 CSWI Core Logic SMVMUX SMVCMP SMVCOS Stepper Motor SMVSIN Module VDO TIM4 TIM2 TIM1 Timer 0x050 Ki 04040 TIMOR TIMOL 0x048 reserved for 0x040 CAPCOM1 0x03C 16 byte 0x030 Audio Module Port Interrupt 0x01C reserved for QUE x COOSEL Core Logic SPIOD SPI Core Logic 0x004 prr 0x000 p 28 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION 3231G C Table 9 4 Base address 0x00F90100 formerly 1200 Offs Byte Address Remarks 3 2 1 0 Module OxOFC 16 byte HW Options OxOFO PSP P5C PIC POP 0x0C0 T3C T2C T1C TOC reserved for PFM 0 04 PWMC V z PWM 32 byte 0x01C reserved for 12 1 12C 12C0 0 004 I2CRSO I2CRDO I2CWP10 2 Ox000 I2CWD10 12
4. C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD TEST2 System Ground no internal pull down For normal operation vvith internal code connect TEST2 to June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 2 4 External Components 5V Supply 100n to 150n 2 System DE Ground 5V Supply 4 7k Resetq 5V HVDDO to 1 1 T Supply 2 x 100n to 150n Hvsso to 1 Bd 100n to 150n VREFINT 10n Ceramic Analog 6753 Ground 150n Ceramic BVDD 7 Fig 2 2 CDC3231G C Recommended external supply and quartz connection To provide effective decoupling and to improve EMC behav iour the small decoupling capacitors must be located as close to the supply pins as possible The self inductance of these capacitors and the parasitic inductance and capaci tance of the interconnecting traces determine the self reso nant frequency of the decoupling network Too low fre quency will reduce decoupling effectiveness will increase RF emissions and may adversely affect device operation XTAL1 and XTAL2 quartz connections are especially sensi tive to capacitive coupling from other pc board signals It is strongly recommended to place quartz and oscillation capac itors as close to the pins as possible and to shield the XTAL 1 and XTAL2 traces from other signals by embedding them i
5. be used and may result in undefined behaviour It is required not to operate VO faster than ROM Suppression Strength SUP and Clock Tolerance TOL may be varied between zero and the values for strong settings according to the rules in Section 4 4 2 of the document CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD The given limits must not be exceeded Table 4 1 PLL and ERM Modes Recommended Settings and Resulting Operating Frequencies MHz CPU ROM VO ERMC EOM 1 ERMC EOM 2 or 3 Weak Weak Normal Strong fsys PLLC fgus fio 100 5 E E Sia PMF fo F G F 4 8 1 8 0 00 8 0 oj 4 0 0 414 2 7 4 11 6 emt e pops of ppm of spp 157 24 5 8 0x22 8 2 0 12 oj 15 0 15 12 6 21 11 31 12 12 0x11 0 10 01 10 01 10 12 2 21 2 33 2 32 7 8 0 33 8 oj 12 oj 12 12 31 12 10 67 0x22 oj 12 12 oj 12 16 8 19 9j 19 9 23 7 23 7 28 6 37 6 40 9 10 0 33 8 4 e ej e 8121 6 35 6 37 6 48 11 12 0 33 8 5 0 1 0 1 0 1 25 1 42 1 42 1 5 10 1 10 0 00 10 0 oj 5 0 8 14 5 3 8 4 14 7 20 3 10 Ox11 10 oj 10 5 17 8 28 8 30 5 10 0 22 10 Oj 14 0 i 8 24 12 28 10 26 11 30 9 35 8 40 7 10 0 33 10 e ej ol e 8121 6 35 6 37 6 50 9 12 5 0 33 10 4 set 0 set 0 Ta
6. 0 LA no Output Activity all SM Module off HVDDn inputs Input Leakage TEST2 1 1 LA 0 lt V lt UVpp 1 Typical values describe typical behaviour at room temperature 25C unless otherwise noted with typical Recommended Operating Conditions applied and are not 100 tested 2 Value may be exceeded with unusual Hardware Option setting 3 Measured with external clock Add typically 120uA for operation on quartz with SR0 XTAL 0 Oscillator RUN mode LA 900 800 700 Ulpps SLOW mode 600 Ulpp 500 400 Ulppa DEEP SLOW mode 300 200 100 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 C Fig 3 1 Typical Ulpp characteristics over temperature fra 4MHz 5V 14 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION 3231G C 3 4 Recommended Quartz Crystal Characteristics See Chapter 3 4 of document CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD Micronas June 30 2003 6251 609 2 15 3231G C ADVANCE INFORMATION 16 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 4 CPU and Clock System 4 1 Recommended Register Settings Other settings for PMF IOP and WSR than those given in Tables 4 1 and 4 2 shall not
7. 007 001 02 Fig 2 1 PMQFP128 2 Plastic Metric Quad Flat Package 128 leads 14 x 20 x 2 7 mm Ordering code QK Weight approximately 1 81 g Micronas June 30 2003 6251 609 2 7 GDC 3231 G C ADVANCE INFORMATION 2 2 Pin Assignment Basic Function Pin 8 ccon CC1 IN TMS U3 1 2 IN 7 TD U3 0 2 a A dol UVDD oj coj 2 2 5 1 00 UVSS UARTO RX U2 5 N Apo NJ UARTO TX CC1 IN U2 4 toj tej tj CC2 OUT NI AN E O0 U2 3 2 IN U2 2 U7 7 Dv old ES CO1 U7 6 7 03 07 m mi 0 0 Aoi N 07 5 to tej tj co Nj N NC NC 5 05 1 05 0 SDAO ANO TX N m mi 0 0 7 N N WP6 SDA0 CAN0 RX U2 1 WPO PINTO 01 7 RH INTRES COO PINT1 U1 6 CO1 CO0Q PINT2 U1 5 N XTAL2 XTAL1 V VDD SEG1 4 ITSTOUT AM OUT SEG1 3 MTO AM PWM 1 NTR OU 1 1 1 0U mj moj i 9 sl lt gt sl n NJ T2 OUT mj T3 OUT OU O 3 0U o m mi 0 2 N N ES toj toj CO1 tj PWMO no m mi 0 0 S S S S coj I mi EE PWM3 PWM4 PWM PWMS coj c
8. 3 3 0 V PLL Supply Voltage BVDD IsuP Core Current VDD VSS 100 100 mA Main Supply Current UVDD UVSS Analog Supply Current AVDD AVSS 20 20 mA SM Supply Current HVDDn 250 250 mA Tcase 105C Duty Factor 0 71 1 HVSSn PLL Supply Current BVDD 20 20 mA Input Voltage Input Current U Ports XTAL RESETQ TEST TEST2 P Ports VREF all Inputs Output Current Duration of Short Circuit to UVSS or UVDD Port SLOW Mode enabled Junction Temperature under Bias Storage Temperature U Ports WAITH H Ports U Ports except in DP Mode 45 115 indefinite Maximum Power Dissipation 45 125 0 8 5 This condition represents the worst case load with regard to the intended application Micronas June 30 2003 6251 609 2 11 3231G C ADVANCE INFORMATION 3 2 Recommended Operating Conditions Do not insert the device into live socket Instead apply power by switching on the external power supply Keep UVppzAVpp during all power up and power down sequences Failure to comply vvith the above recommendations vvill result in unpredictable behavior of the device and may result in device destruction Functional operation of the device beyond those indicated in the Recommended Operating Conditions of this specification is not implied may result in unpredictable behaviour of the device and may reliability and lifetime
9. ADVANCE INFORMATION mm MICRONAS CDC 3231G C mmm Automotive Controller Edition June 30 2003 2 MI C RO NAS 6251 609 2Al 3231G C ADVANCE INFORMATION Contents Page Section Title 3 1 Introduction 3 1 1 Features 5 1 2 Abbreviations 6 1 3 Block Diagram 7 2 Packages and Pins 7 2 1 Package Dimensions 8 2 2 Pin Assignment 8 2 3 Pin Function Description differing from document CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD 9 2 4 External Components 11 3 Electrical Data 11 3 1 Absolute Maximum Ratings 12 3 2 Recommended Operating Conditions 13 3 3 Characteristics 15 3 4 Recommended Quartz Crystal Characteristics 17 4 CPU and Clock System 19 5 Memory and Special Function ROM SFR System 21 6 Core Logic 21 6 1 Control VVord CVV 23 7 IRQ Interrupt Controller Unit ICU 25 8 Hardware Options 25 8 1 Functional Description 27 9 Register Cross Reference Table 27 9 1 8 Bit VO Region 32 9 2 32 Bit VO Region 33 9 3 Modified Registers 35 10 Differences 36 11 Data Sheet History 2 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 1 Introduction Release Note Revision bars indicate significant interfaces and PWM outputs and a crystal clock multiplying changes to the previous edition PLL The device is a microcontroller for
10. Reg AVSS Bye JTAG Test and Debug 5 Interface E ROM 8 e 16 32 32k x 32 8 ON N i ontroller 5 5 VVait SFR 4kx 16 P06 Comp 8 Patch 10 Locations 3 5 Bandgap Ref T 7 10Bit ADC Bridge R E y Stepper Motor 16Bit Timer 0 16Bit CCC 0 8 4 UART 0 LCD Control Control 8Bit Timer 1 Audio Module 8Bit PWM 0 CAPCOM O 3 8 168 PWM 1 8Bit 2 1 SPIO Clock Out 0 CAPCOM 2 7 z 8Bit 2 CAPCOM 3 lock Out 1 SPI 1 SABB ENNS 8Bit Timer 4 3 8Bit PWM 4 2 8 16 PWM 5 8Bit 6 8 16B PWM 7 8Bit PWM 8 8 16B PWM 9 000 HPort7 HVSS1 lc o UPort8 UPort7 UPort6 UPort5 UPort4 UPort3 UPort2 UPort1 UPort0 Fig 1 1 231 block diagram 6 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION 3231G C 2 Packages and Pins 2 1 Package Outline Dimensions PIN 1 INDEX DETAIL X SEATING PLANE il does not include dambar protrusion of 0 08 max per side JEDEC STANDARD ISSUE DATE YY MM DD DRAVVING NO SPZG NO ITEM NO MS 022 03 04 16 06607 0001 4 5 20001
11. VDD PLL Mode Supply UVDD 50 mA fgyg 24MHz Current Ulpp UVDD FAST Mode UVDD 22 mA all Modules off 2 Current UVDD SLOW Mode Supply UVDD see 1 4 mA all Modules off Current Fig 3 1 1 Ulppa UVDD DEEP SLOW Mode UVDD See 0 9 mA all Modules off Supply Current Fig 3 UVDD Ulppw UVDD WAKE Mode Supply Current UVDD STANDBY Mode Supply Current UVDD UVDD Ulppst 1 Typical values describe typical behaviour at room temperature 25C unless otherwise noted with typical Recommended Operating Conditions applied and are not 100 tested RC and XTAL oscillators off RC oscillator on XTAL off XTAL oscillator on RC off 3 Micronas June 30 2003 6251 609 2 13 3231G C ADVANCE INFORMATION Table 3 3 UVss HVssn AVss 0V 3 5V lt AVpp UVpp lt 5 5V 4 75V lt HVppn lt 5 25V Tcase 40 to 1 05 25 components according to Fig 2 3 unless otherwise noted Symbol Parameter Pin Na Min Typ Max Unit Test Conditions Ulppi UVDD IDLE Mode Supply UVDD 50 TBD oscillator on XTAL Current off 75 TBD uA XTAL oscillator on RC off 3 AVDD Active Supply AVDD 0 35 0 6 mA ADC on PLL off rent I 1 2 mA ADC and PLLon fsys 24MHz I Quiescent Supply Current AVDD 0 1 10 LA SLOW DEEP SLOW and power saving l modes ADC and PLL off Sum of 0 1 4
12. Wake Up Inputs including Slope Level 10 inputs Selection Patch Module Boot System 10 ROM locations allows in system downloading of 5 external code to Flash memory via JTAG Micronas June 30 2003 6251 609 2 3 3231G C ADVANCE INFORMATION Table 1 1 CDC32xxG C Family Feature List continued This Device CDC3205G C CDC3207G C CDC3272G C EMU MCM Flash Mask ROM Mask ROM Device Lock Module Inhibits Access to internal Firm ware Lock settable by Customer Analog Reset Alarm Combined Input for Regulator Input Supervision Clock and Supply Supervision v 10 bit ADC charge balance type 16 channels each selectable as digital input ADC Reference VREF Pin P1 0 Pin P1 1 Pin or VREFINT Internal Bandgap selectable Comparators PO6COMP with 1 2 AVDD reference WAITCOMP with Internal Bandgap reference LCD Internal processing of all analog voltages for the LCD driver Communication DMA 3 DMA Channels one each for serving the Graphics Bus interface SPIO and SPI1 UART 2 UARTO and UART1 UARTO Synchronous Serial Peripheral Interfaces 2 SPIO and SPI1 DMA supported Full CAN modules V2 0B 4 CANO CAN1 CAN2 and CAN3 2 CANO and 1 CANO with 512 byte object RAM each CANI LCANOOOE DIGITbus 1 master module 2 master modules 12 0 and 12 1 12 0 Graphics Bus Interface 8 bit data bus DMA supported e g for connection of EPSON SED 1560 LCD co
13. al cel toj ro BLQ v S e PWM9 MD1 MD COMP3 AY si ca col ol i S oof Sj SMD1 SMD COMP2 EN coj MD2 MD COMP1 EN ES SMD2 SMD COMPO 5 1 5 2 gt gt ADA 54 SL di SMA COMP0 ai NC not connected leave vacant future usage Pin Functions Basic Function Port Special Out U3 2 U3 4 CC0 OUT 112 U3 5 SPI0 D IN 111 110 109 U3 6 U3 7 04 0 p KIN PTT D IN 108 04 1 CC0 IN D OUT BP1 107 106 105 U4 2 U4 3 U8 0 BP2 8 0 104 08 1 SEG8 1 103 102 101 U8 2 08 3 08 4 SEG8 2 K OU 8 3 8 4 LCD CLK IN U8 5 PINT3 WP8 LCD SYNC OUT SEG8 5 NC 06 1 06 2 BEGET P2 0 P2 1 0 0 PO 1 P0 2 P0 3 PO 4 5 Po 6 7 9 DS P0 6 Comp VREFO WP1 VREF1 WP2 PINTO PINTI PINT2 PINT3 PWM7 PWM5 PWM37PO MC COMPO SMC COMP1 MC COMP2 SMC COMP3 SMB COMPO MB COMP SMB COMP3 Fig 2 1 Pin Assignment Please note that in contrast to CDC3205G C CDC3207G C and CDC3272G C the function CC3 OUT is not present on pin 1041 2 3 Pin Function Description differing from document CDC32xxG
14. ble 4 2 PLL2 and Modes Settings Sacrificing Unlimited Operation of Peripheral Modules and Resulting Operating Frequencies MHz 1 CPU VO ERMC EOM 1 ERMC EOM 2 3 Normal PLLC WSR PMF 4 12 2 6 0 11 12 0 00 20 4 10 0 11 5 15 2 7 5 0 11 Micronas June 30 2003 6251 609 2 17 3231G C ADVANCE INFORMATION 18 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION 3231G C 5 Memory and Special Function ROM SFR System address range RESETQ 1 RESETQ 0 16M CR MAP 00 CR MAP 01 CR MAP 1x TEST2 Pin 0 TEST2 Pin 1 rsvd debug I 00FF FFFF F8 0000 F0 0000 E0 0000 C0 1800 C0 0000 RAM RAM RAM 6KB 6KB 6KB 0 0000 8M 22 0000 ROM ROM 128KB 128KB 20 0000 2 0000 2M 1800 ROM ROM RAM 128KB 128KB 6KB Fig 5 1 Address Map Most Common Settings Micronas June 30 2003 6251 609 2 19 3231G C ADVANCE INFORMATION 20 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 6 Core Logic 6 1 Control Word CW A number of important system configuration properties are selectable during device start up by means of a unique Con trol Word CW 6 1 1 Reset Active At the end of the reset period the device fetches this CW from address locations 0x20 to 0x23 of a source that is d
15. dress OXOOFFFDOO Byte Address Remarks Module 252 bytes Core Logic reserved Control Register Table 9 8 Base address 0x00FFFE00 Offs Byte Address Remarks 3 2 1 0 Module OxOFC reserved for 0 000 Table 9 9 Base address 0x00FFFF00 Offs Byte Address Remarks 3 2 1 0 Module OxOFC 12 bytes reserved IRQ and Interrupt Control CRE PRE FIQ registers s 40 bytes reserved IRQ registers PEPRIO 128 bytes reserved Interrupt source nodes 0x004 ISN7 ISN6 0x000 ISN3 ISN2 32 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 9 3 Modified Registers Listed are only those registers that are differing from Docu ment CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD 9 3 1 Standby Registers cf chapter 6 3 in CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD SR0 Standby Register 0 7 6 5 4 3 2 1 0 rw x 12 0 x x x 3 rw x TIM2 TIM3 TIM4 EN ico rem fom c s SM x x x 5 10 0 00000100 Res 9 3 2 UVDD Analog Registers cf chapter 6 4 9 in CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD ANAU Anal
16. ent CDC32xxG C Automotive Controller Family User Manual CDC3205G C Automotive Controller 6251 579 1PD Hardware Option setting requires two steps 1 selection is done by programming dedicated address loca tions in the HW Options field with the desired options code 2 activation is done by copying the HW Options field to the corresponding HW Options registers at least once after each reset In this device as in EMU and MCM devices all HW Options are SW progammable In future mask ROM derivatives the clock options and the Watchdog Clock and Supply Monitors may be hard wired according to the HW Options field of the ROM code hex file Those options can only be altered by changing a production mask To ensure compatible option settings in this IC and future mask ROM derivatives when run with the same ROM code it is mandatory to always write the HW Options field to the HW option registers directly after reset Micronas June 30 2003 6251 609 2 25 3231G C ADVANCE INFORMATION 26 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION 3231G C 9 Register Cross Reference Table 9 1 8 Bit Region Table 9 1 Base address 0 00 80000 Byte Address Remarks 3 Module 7 CAN reserved CAN RAM Table 9 2 Base address 0x00F81000 Offs Byte Address Remarks 3 2 o o o Module Ox1FC 7 GAN reserved CAN register 0 040 0x03C CANO Ox014
17. etermined by the state of pins TEST and TEST2 and flag MFPLR MFPL see Table 6 1 parts Table 6 2 for ROM parts Table 6 1 CW fetch in MCM parts QFP128 Control Word Fetch desired from Necessary Reset con figuration TEST2 TEST MFPL Int Flash 0 0 x Int Flash Ext via Multi Function port Int Special Function ROM 1 Only available after a non Power On RESET with MFPL 0 set before As can be seen from Table 6 1 the device disables external access through the Multi Function port to internal code as long as MFPLR MFPL is 1 state after UVDD power up Setting it to 0 requires internal SW By this means an effec tive device lock mechanism is implemented that prevents unauthorized access to internal SW In ROM parts flag MFPLR MFPL is available but does not lock the Multi Function port Thus Table 6 1 reduces to Table 6 2 Table 6 2 CW fetch in ROM parts QFP128 Control Word Fetch desired from Necessary Reset config of pins TEST2 TEST Internal ROM External via Multi Function port Int Special Function ROM 1 x 6 1 2 Reset Inactive When exiting Reset the CW is read and stored in the Control Register CR and the system will start up according to the configuration defined therein Normally the CW is fetched from the same memory that the system will start executing code from Table 6 3 gives fix CWs for a list of the most common
18. ly used configurations Table 6 3 Some common system configurations and the corresponding CW setting Part Program Start desired from Additional desired properties Necessary CW MS 31 16 15 0 int 16 Bit Flash Am29LV400BT i Don t care 0x7F5F ROM int 32 Bit ROM 16 Bit mode Don t care Ox7F5F ROM int 32 Bit ROM 32 Bit mode OxFFBA 0 775 Micronas June 30 2003 6251 609 2AI 21 3231G C ADVANCE INFORMATION 22 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION 3231G C 7 IRQ Interrupt Controller Unit ICU Table 7 1 ICU Input Availability Table 7 1 ICU Input Availability Interrupt Source ISN Interrupt Source Timer 4 0 Default vector not connected Not connected Timer 1 Timer 0 Po6 COMP RESET ALARM WAIT COMP UARTO 2 COMMRX TX PINT5 PINT3 Not connected Not connected Not connected 28 Not connected 29 Not connected Micronas June 30 2003 6251 609 2 23 3231G C ADVANCE INFORMATION 24 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 8 Hardware Options 8 1 Functional Description Hardware Options are available in several areas to adapt the IC function to the host system requirements For details see the docum
19. n a VSS trace The RESETQ pin adjacent to XTAL2 should be supplied with a 47nF capacitor to prevent fast RESETQ transients from being coupled into XTAL2 to prevent XTAL2 from coupling into RESETQ and to guarantee a time constant of 220045 sufficient for proper Wake Reset functionality Micronas June 30 2003 6251 609 2 3231G C ADVANCE INFORMATION 10 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 3 Electrical Data 3 1 Absolute Maximum Ratings Stresses beyond those listed in the Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only Functional operation of the device at these conditions is not implied Exposure to absolute maximum ratings condi tions for extended periods will affect device reliability This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields how ever it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum rated volt ages to this high impedance circuit Table 3 1 All voltages listed are referenced to ground UVss HVssn AVss 0V except where noted All grounds except VSS must be connected externally low ohmic Symbol Parameter Pin Name Min Max Unit Vsup Main Supply Voltage UVDD 0 3 6 0 V Analog Supply Voltage AVDD SM Supply Voltage HVDDn VREG Core Supply Voltage VDD 0
20. ndomly selectable HW options JTAG test interface v allows Flash v programming On Chip Debug Aids Set by copy from user program storage during system start up Embedded Trace Module JTAG JTAG Core Bond Out v Supply Voltage 3 5 to 5 5V limited VO performance below 4 5V Case Temperature Range 0 to 70 40 to 105 Package Type Ceramic Plastic 128QFP 257PGA 0 5mm pitch Bonded Pins 256 128 126 111 and Thumb are the registered trademarks of ARM Limited ARM7TDMIM is the trademark of ARM Limited 1 2 Abbreviations ADC Analog to Digital Converter LCD Liquid Crystal Display Module AM Audio Module PO6COMP P0 6 Alarm Comparator CAN Controller Area Network Module PINT Port Interrupt Module CAPCOM Capture Compare Module PWM Pulse Width Modulator Module CCC Capture Compare Counter SM Stepper Motor Control Module CPU Central Processing Unit SPI Serial Synchronous Peripheral Interface DMA Direct Memory Access Module T Timer ERM EMI Reduction Mode UART Universal Asynchronous Receiver Transmitter ETM Embedded Trace Module WAITCOMP Wait Comparator ICU Interrupt Controller 12 Interface Module Micronas June 30 2003 6251 609 2AI 5 3231G C ADVANCE INFORMATION 1 3 Block Diagram Reset Alarm RESETQ Watchdog TEST2 Clock XTAL1 PLL ERM XTAL2 RC Oscillator WAIT WAITH 26 Input RTC Interrupt VREFINT ARM7TDMI Controller Power VREF CPU Saving AVDD 2 5V
21. ntroller Input 8 Output Universal Ports selectable as 4 1 mux LCD up to 52 I O or 48 LCD segment lines 2192 segments up to 50 I O or Segment Backplane lines or Digital I O Ports individually configurable as or LCD 46LCD seg ment lines 2184 seg ments Universal Port Slew Rate SW selectable Stepper Motor Control Modules with High 7 Modules 4 Modules Current Ports 32 dl dt controlled ports 23 dl dt con trolled ports PWM Modules each configurable as two 8 6 Modules PWMO 1 PWM2 3 PWM4 5 PWM6 7 5 Modules bit PWMSs or one 16 bit PWM PWM8 9 and PWM 1 0 11 PWMO 1 PWM2 3 PWM4 5 6 7 8 9 Phase Frequency Modulator 2 PFMO and PFM1 Audio Module with auto decay v 4 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C Table 1 1 CDC32xxG C Family Feature List continued This Device CDC3205G C CDC3207G C CDC3272G C CDC3231G C EMU MCM Flash Mask ROM Mask ROM SW selectable Clock outputs 2 Polling Flash Timer Output Timers amp Counters 1 High Current Port output operable in Power Saving Modes 16 bit free running counters with Capture CCC0 with 4 CAPCOM CCC0 with 4 Compare modules CCC1 with 2 CAPCOM CAPCOM 16 bit timers 1 TO 8 bit timers 4 T1 T2 T3 and T4 Real Time Clock Delivering Hours Minutes and Seconds Miscellaneous Scalable layout in CAN RAM and ROM v v Various ra
22. og UVDD Register 7 6 5 4 3 2 1 0 I ee 0 0 0 0 0 Micronas June 30 2003 6251 609 2 33 3231G C ADVANCE INFORMATION 34 June 30 2003 6251 609 2 Micronas ADVANCE INFORMATION CDC 3231G C 10 Differences This chapter describes differences of this document to pre decessor document CDC3231G C V1 0 Automotive Con troller Specifictaion 6251 609 1Al Section Description 1 Introduction Editorial corrections 2 Pins and Packages 3 Electrical Data TEST2 pin without internal pull down Pin 104 U8 1 without the Special Out function CC3 OUT Figure 2 1 changed Figure 2 3 corrected Absolute Maximum Ratings Revised introduction Recommended Operating Conditions Revised introduction Characteristics Editorial corrections Changed definition Table 3 3 footnote 3 Added parameters li Changed value Ulpps Ulppg Ulppw Ulppst Ulppi Values added Alppg Added conditions Rihja Figure 3 1 added 10 Differences Added Micronas June 30 2003 6251 609 2 35 3231G C ADVANCE INFORMATION 11 Data Sheet History 1 Advance Information CDC3231G C V1 0 Automo tive Controller Specification 13 JAN 03 6251 609 1 First release of the advance information Originally created for HW version CDC3231G C1 2 Advance Information CDC3231G C Automotive C
23. ontroller June 30 2003 6251 609 24Al Second release of the advance information Originally created for HW version CDC3231G C2 Micronas GmbH Hans Bunte Strasse 19 D 79108 Freiburg Germany P O Box 840 D 79008 Freiburg Germany Tel 49 761 517 0 Fax 49 761 517 2174 E mail docservice Omicronas com Internet www micronas com Printed in Germany Order 6251 609 2 information and data contained in this data sheet vvithout any commitment are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability new issue of this data sheet invalidates previous issues Product availability and delivery are exclusively subject to our respective order confirmation form the same applies to orders based on development samples deliv ered By this publication Micronas GmbH does not assume responsibil ity for patent infringements or other rights of third parties which may result from its use Further Micronas GmbH reserves the right to revise this publication and to make changes to its content at any time without obligation to notify any person or entity of such revisions or changes No part of this publication may be reproduced photocopied stored on a retrieval system or transmitted without the express written consent of Micronas GmbH 36 June 30 2003 6251 609 2 Micronas
24. s ADVANCE INFORMATION CDC 3231G C Table 3 2 All voltages listed are referenced to ground UVss HVssn AVss 0V except where noted All grounds except VSS must be connected externally low ohmic Symbol Parameter Pin Name Min Typ Max Unit VREFI Ext ADC Reference Input Voltage VREF 2 56 AVpp V ADC Port Input Voltage referenced P Ports 0 Vnrri V to int VREF Reference ADC Port Input Voltage referenced 0 VREFINT to ext VREFINT Reference 3 3 Characteristics ily User Manual CDC3205G C Automotive Controller 6251 579 1PD All not differing characteristics that are not listed here Listed are only those characteristics that are differing from Chapter 3 3 of Document CDC32xxG C Automotive Controller Fam apply but in a Tcase temperature range extended to 40 to 105C Table 3 3 UVss HVssn AVss OV 3 5V lt AVpp UVpp lt 5 5V 4 75V lt HVppn lt 5 25V Tcase 40 to 1 05 fytaL oMHz external components according to Fig 2 3 unless otherwise noted Package Rinje Thermal Resistance from C W Junction to Case Thermal Resistance from Junction to Ambient Supply Currents CMOS levels on all inputs i e Vi xVss 0 3V and Vih XVppt0 3V no loads on outputs measured on Micronas typical 2 layer board 1s1p described in docu menit Integrated Circuits Thermal Characteriza tion of Packages 6200 266 1E modified JESD 51 3 Ulppp U
25. use in automotive applica This document provides ROM hardware specific information tions The on chip CPU is an ARM processor ARM7TDMI General information on operating the IC can be found in the with 32 bit data and address bus which supports Thumb document CDC32xxG C Automotive Controller Family format instructions User Manual CDC3205G C Automotive Controller 6251 579 1PD The chip contains timer counters interrupt controller multi channel AD converter stepper motor and LCD driver CAN 1 1 Features Table 1 1 CDC32xxG C Family Feature List This Device CDC3205G C CDC3207G C CDC3272G C CDC3231G C EMU MCM Flash Mask ROM Mask ROM Core CPU 32 bit ARM7TDMI CPU Active Operation Modes DEEP SLOW SLOW FAST and PLL Power Saving Modes CPU Inactive IDLE WAKE and STANDBY CPU clock multiplication EMI Reduction Mode PLL delivering up to 50MHz selectable in PLL mode Oscillators 4 to 5MHz Quartz and 20 to 50kHz Internal RC RAM zero wait state 32 bit wide 32kByte 16kByte 6kByte ROMIess ext 512 kByte Flash 384kByte 128kByte up to 256K x 16 top 96K x 32 32K x 32 4 32 boot conf 192 16 64K x 16 8M x 16 int 8 KByte int 8 KByte Boot ROM Boot ROM Digital Watchdog v Central Clock Divider v Interrupt Controller expanding IRQ 40 inputs 16 priority levels 26 inputs 16 priority levels Port Interrupts including Slope Selection 6 inputs 5 inputs Port
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