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DSP Selection Guide

1. s smart multiprocessor MP debug support provides a seamless interface to multiple DSPs on the same physical hardware Users are able to issue parallel step run and halt commands to all of the applicable DSPs RAPT dep bP AEP Pee TEGE El Multiproces E3 Tapi Hare Teed noes Pape Lim aa VisualDSP s multiprocessor dialog box and tollbar DSP Selection Guide 9 VisualDSP The developer can pick and choose individual DSP register or memory sets of interest by pinning those that should be updated between runs halts and steps This feature also eliminates screen clutter in multiprocessor debugging Statistical Profiling Statistical profiling allows for a more generalized form of profiling that JTAG emulator debug targets can take advantage of The debugger has the ability to unintrusively randomly sample the target processors PC and then present the user with a graphical display of the resultant samples This allows the user to easily see where their application is spending most of its time VisualDSP s statistical profiling window Graphical Profiling The plot window supports exporting images to both bitmap and JPEG format files and has highly configurable formatting options such as title subtitle font size font face font color and element colors Code Generation Tools DSP code generation tools allow development of applications that take full advantage of the DSPs arc
2. 1998 ANALOG DEVICES 218X D M Series Up to 2MBit SRAM 0 5 mA MIP 2 5V 1999 http www analog com dsp Code Compatible GES 150 320 MIPS Up to 2 5MBit SRAM 218X N Series 80 MIPS Up to 2MBit SRAM 0 3 mA MIP 1 8V 75 MIPS 2000 DSP Selection Guide 23 ADSP 218x N Series Low Power ADSP 218x Family The new ADSP 218x N series is a low power Benefits 1 8V 16 Bit DSP family that is pin compati ble with all the ADSP 218xM products and code compatible with all ADSP 21xx DSPs e Simple algebraic assembly language reduces development time and time to market e Pin compatible packages mitigates product Features development risks 0 3 mA MIP 1 8 volt core supply e 16 Bit DMA port makes bus interfacing easier e Code compatible with all 21xx derivatives ensures re use of legacy code e Large on chip memory eliminates the e 12 5 ns instruction cycle time 80 MIPS e Up to 48K words of on chip program RAM e Up to 56K words of on chip data memory RAM need for expensive SRAM e I O voltage support to 3 3 volts e 144 Ball mini BGA package provides for e 16 Bit Internal DMA Port maximum space savings 10 mm x 10 mm e 8 Bit Byte Memory DMA Applications e Two Double Buffered Serial Ports 1 with TDM mode e Consumer Telephony l e JJO Memory Interface w 2048 Locations j Embedded Speech Processing e ADSP 2100 Family code amp function POS Terminals compatible PBX e 100 Lead LQFP 144 Lead
3. ADI leads the industry in DSP SRAM inte gration ADI processors have on chip memo ries which often eliminate the need for exter nal memory in a system Furthermore the memory is configurable for data word size code word size and storage size This allows designers to tailor the memory to meet the algorithm requirements ANALOG DEVICES http www analog com dsp TDM Mode TDM Time Division Multiplexed mode refers to time division multiplexing which is a com mon mode for transferring serial data In telecommunications applications T1 and E1 lines use TDM TDM allows multiple serial devices to send and receive information using the same physical connection TDM also allows communication between multiple DSPs All ADI DSPs support TDM mode in the seri al ports Zero Overhead Looping The code for most DSP routines falls naturally into a set of nested loops Without the support for zero overhead looping the DSP core must spend cycles calculating the loop termination values in addition to the cycles used to process the algorithm s computations Without zero overhead looping performance degrades ADI offers 16 bit fixed point and 32 bit fixed floating point DSPs with zero over head nestable looping to save instruction cycles DSP Selection Guide 17 18 ADSP 2100 Family Benchmarks 16 Bit DSPs The flexibility and power of the ADSP 2100 Family provides users with e Best price performance over a wide
4. Internal voltage reference e Three phase 16 bit PWM generation unit e Two 8 bit auxiliary PWM outputs e 25 MIPS fixed point DSP core 4K x 24 bit program memory RAM 2K x 24 bit program memory ROM 1K x 16 bit data memory RAM e Incremental encoder interface e Programmable digital I O Benefits e High performance DSP integrated with high resolution 12 bit ADC provides true single chip solution e Flexible encoder interface unit for position feedback e Fully code compatible with all ADSP 21xx and ADMCxx family products e Algebraic assembly language for easy pro gramming ADSP 21xx Base Architecture Data Address Generators Program Memory Block 24 Program RAM 4K x 24 Applications e Motor types AC Induction Motors ACIM Permanent Magnet Synchronous Motors PMSM Brushless DC Motors BDCM e Industrial variable speed and servo drives e Uninterruptable power supplies e Electric vehicles e Smart sensors data acquisition systems Price 100 499 Pin PKG Instr Rate Temp Model Range ADMC300BST Industrial 25 MHz 80Pin 19 95 40 C LQFP to 85 C Development Tools Price ADMC300 ADEVALKIT 395 00 ADMC300 evaluation board and motor control development tools assembler linker debugger http www analog com motorcontrol Motor Control Peripherals Program Event S Data RAM Inter
5. out standardization can significantly simplify the design in process Compare Advertised Pricing 1Ku ADI Competitor 9 50 18 00 17 00 30 00 25 00 34 00 A N a 32K Words 64K Words gt 100K Words 15 Advertised Price Suggested Resale in 1K quantity A a The ADSP 2188N for example is packaged in a tiny 10mm x 10mm Ball Grid Array mini BGA In a one centimeter square package the design engineer has 80 MIPS 2 Mbits of SRAM and two serial ports Likewise Analog Devices pin for pin compati ble packaging strategy saves designers time With little or no change to the hardware designers can migrate to higher speeds lower voltages and larger memory sizes Program Memory 16 Bit Fixed Point SRAM DSP Core Byte DMA Internal Controller DMA Port Powerdown Control 16 Bit Timer with Reload Register High Speed High Speed Serial Port Serial Port 1 2 Data Memory SRAM I O Port and Control ANALOG DEVICES ADSP 2188 gt EEn DEVICES ADSP 218 93 Pin compatibility mitigates design risks and minimizes development cycles 64K Words 100K Words On Chip Memory Integration n o r ANALOG DEVICES ADSP 218x Family Code and Pin Compatible Family of 16 Bit Fixed Point DSPs Features e Easy to use algebraic like assembly language syntax All instructions execute in a single cycle Over 100 pin and code compatible devices Fast interrupt res
6. 160 MIPS ADSP 219x 1 8V Low Power 0 1 mW MIPS 26 DSP Selection Guide http www analog com dsp gt ANALOG DEVICES Compiler Friendly Many of the enhancements in the ADSP 219x architecture are designed to improve compiler efficiency A global register allocator and sup port for register file like computations reduce spills and reduce reliance on the local stack The compiler features DSP intrinsic support including fractional and complex math Some of the enhancements to the ADSP 219x core to improve C compiler efficiency are more flexible addressing modes in DAG regis ters register file capable instructions added depth to stacks added secondary DAG registers and extended address reach to 16 Mwords Extended Address Reach The address reach has been extended to 24 bits This supports 64 Kword direct memory addressing or 16 Mword paged memory addressing All existing addressing modes are supported and five new DAG addressing modes have been added ADSP 219x Family The addressing modes include e Direct immediate address to from a register in groups 0 3 e Indirect post modify to from a DREG e Indirect post modify write with immediate data e Two indirect post modify reads to AX AY MX MY only e Modify address register without a transfer e Indirect post modify to from any register in banks 0 3 e Indirect post modify with immediate 8 bit offset e Indirect with immediate 8 bit offse
7. Addr Bus Program Memory Address Data Memory Address Program Memory Data External Data Bus Data Memory Data Arithmetic Units ADSP 218X DSP ANALOG DEVICES http www analog com dspconverter Byte DMA Controller Serial Ports SPORT 0 SPORT 1 Seri rts ial Po Analog Front End Section DSP Selection Guide 43 AD73422 Dual Low Power Analog Front End with DSP Features AFE PERFORMANCE e 16 Bit A D converter e 16 Bit D A converter e Programmable input output sample rates 76 dB ADC SNR e 77 dB DAC SNR e 64 kS s maximum sample rate e 90 dB crosstalk e Low group delay 25 us typ per ADC channel 50 us typ per DAC channel e Programmable input output gain e On chip reference DSP PERFORMANCE e 19 ns instruction cycle time 3 3 Volts 52 MIPS performance e Single cycle instruction execution e Single cycle context switch e 3 Bus architecture allows dual operand fetches in every instruction cycle e Multifunction instructions e Power down mode featuring low CMOS standby e Power dissipation with 400 cycle recovery from power down condition e Low power dissipation in idle mode ea DSN laet Benefits e Extensive analog front ends include A Ds D A PGAs reference and input conditioning circuitry e Reduced design risk all the interface design work is done e Pro
8. Interrupt Latency Interrupt latency is a measure of how quickly a DSP responds to an interrupt Quick response is important especially in real time processing For example an interrupt might indicate the availability of data which is only available for a finite amount of time Therefore fast response is critical or the data will be lost ADI DSPs feature fast interrupt response time for quick execution of interrupt service routines gt ANALOG DEVICES Benchmarks Multiprocessing Support Even with the powerful DSPs available today there are times when the DSP task for a given system does not fit into a single DSP Examples of such applications include sonar radar med ical imaging audio mixers etc In these cases the ability to connect multiple DSPs in a sys tem without any glue logic greatly simplifies the implementation ADI offers SHARC DSPs with specialized hardware for glueless multiprocessing On Chip Memory On Chip SRAM Size The amount of on chip memory available can greatly impact system performance cost size power consumption and complexity Any time the DSP core accesses external memory the performance can suffer Off chip memory often requires the core to wait additional cycles In contrast the DSP core can access on chip memory at the same rate as its instruction rate The addition of external memory adds extra components to the system which increases cost power consumption and complexity
9. Register File 16 x 40 Bit Barrel Shifter ANALOG DEVICES http www analog com dsp Memory Mapped Control Status and Data Buffers I O Processor DSP Selection Guide 33 ADMC Motor Control Family Embedded DSP Based Moto r Controllers The ADMC family of embedded DSP based Motor Controllers integrate 16 bit fixed point DSPs with software and analog circuitry opti mized for motor control applications All processors are fully code compatible allowing for additional features and enhanced perfor mance while protecting the software develop ment investment Development Tools Generic specific evaluation and development tools are available for each ADMCxxx device Development tool kits include everything required to quickly and easily develop user spe cific applications including Embedded DSP Motor C Memor Program Program Program Device MIPS RAM FLASH ROM ADMC401 26 2K x 24 bits 2K x 24 bits DashDSP 20 512 x 24 bits 4K x 24 bits 4K x 24 bits ADMCF326 F32x 32 ADMC326 ADMCF327 ADMC327 ADMCF328 ADMC326 ADMC331 26 2K x 24 bits 2K x 24 bits ADMC300 25 4K x 24 bits 2K x 24 bits 34 DSP Selection Guide http www analog com motorcontrol e VisualDSP based motion control debugger e Connector board e Compiler linker assembler e Serial cable e Example software e User documentation and reference guides e Modular processor board Motor
10. 219x DSPs VisualDSP enables design engineers to easily develop debug and deploy code throughout the research design development and test stages of any project VisualDSP integrates all of the code generation tools below e Assembler e PROM splitter e Linker e Math DSP and e Simulator C runtime library e C Compiler e Integrated development e Debugger environment e Librarian EZ KIT Lite Evaluation Kit The EZ KIT Lite provides an easy way to evaluate the power of ADI s DSPs and begin to develop applications These systems consist of a stand alone evaluation board and fundamental debugging software to facilitate architecture evaluations via a PC hosted tool set With the EZ Kit Lite users can e Evaluate ADI s DSPs e Learn about DSP applications e Simulate amp debug applications e Prototype applications I ee Emulators Emulators provide non intrusive target based debugging of DSP systems Compact and easy to use these in circuit emu lators perform a wide range of emulation func tions including single step and full speed exe cution with pre defined breakpoints viewing and or altering of register and memory con tents ADDS 2181 EZLITE ADSP 2100 Family ADSP 2181 ADSP 218XM N Family ADSP 218XM N Family ADSP 2192 Complete Package ADSP 218x 219x IDE Debugger Compiler Assembler Linker with Emulation and Simulation Support Code Gen Package ADSP 218x 219x Compiler Assembler Linker Assembler P
11. 2K 2 5K 8 9K 3K 75 508 lt 1K 1312 8 2K 7 2K 9 6K 7 5K 10 2K lt 2K 10 5K 14K lt 2K 1 5K Speech Algorithm O P Rate IE 133 lt 200 ANALOG DEVICES ADSP 21000 SHARC Family Benchmarks 32 Bit DSPs Just looking at the cycle time clock speed SHARC DSPs are the highest performance MIPS or MFLOPS of a DSP cannot give an 32 bit DSPs available These processors excel accurate indication of the true performance of at IEEE floating point math 32 bit fixed point the processor Benchmarks are important in that math and extended precision 40 bit floating they show how a particular DSP performs in point the context of an application The smaller the benchmark number the quicker the algorithm The ADSP 21000 Family offers a maximum execution If a DSP can perform the task quick performance for minimum system cost while er the processor can perform more tasks in a dramatically shortening product development given amount of time time and critical time to market Clock Speed 66 MHz 100 MHz Instruction Cycle Time 15 ns 10 ns MFLOPS Sustained Peak 132 198 MFLOPS 400 600 MFLOPS MOPS 32 bit Fixed Point 132 198 MFLOPS 400 600 MFLOPS Sustained Peak 1024 Point Complex FFT 0 27 ms SISD 0 09 ms SIMD Radix 4 with Digit Reverse FIR Filter per Tap 15 ns 10 ns IIR Filter per Biquad 60 ns 10 ns Matrix Multiply 3x3 x 3x1 135 ns 56 25 ns 4x4 x 4x1 240 ns 80 ns Divide y x 90 ns 30 ns Inverse Square Root
12. 5V 2K 1K 2 21 70 Package B Plastic Ball Grid Array PBGA G Ceramic Pin Grid Array PGA Contact factory for pricing P Plastic Leaded Chip Carrier PLCC S Plastic Quad Flat Pack PQFP US Dollars Lowest grade suggested resale price per unit in 100 unit quantities ANALOG DEVICES ee ST Thin Quad Flat Pack LQFP CA Mini Ball Grid Array DSP Selection Guide 21 22 DSP Selection Guide M and N Series Pin Compatibility Mitigates Design Risks Analog Devices industry leading DSP and SRAM integration capability is evident in the ADSP 218x family Well known for the 32 bit DSP and SRAM integration pioneered in the SHARC family Analog Devices provides the 16 bit complement in the ADSP 218x family With up to 2 Mbits of on chip SRAM many functions run without the need for external memory vastly simplifying the board design algorithm development and debug process In addition to minimizing memory I O bottle necks executing algorithms using on chip memory reduces chip count system cost board space and power consumption Large amounts of SRAM coupled with the ADSP 2100 fami ly s sophisticated DMA and programming fea tures make the ADSP 218x processors the best choice to make your design challenge easier Packaging technology also plays an important role in how easily designers can incorporate these processors into their applications Advanced miniaturization techniques and pin
13. A converter e Programmable input output sample rates e 76 dB ADC SNR e 77 dB DAC SNR e 64 kS s maximum sample rate e 90 dB crosstalk e Low group delay 25 us typ per ADC channel 50 us typ per DAC channel e Programmable input output gain e On chip reference DSP PERFORMANCE e 19 ns instruction cycle time 3 3 Volts 52 MIPS performance e Single cycle instruction execution e Single cycle context switch e 3 Bus architecture allows dual operand fetches in every instruction cycle e Multifunction instructions e Power down mode featuring low CMOS standby e Power dissipation with 400 cycle recovery from power down condition e Low power dissipation in idle mode Data Address Generators Benefits e Extensive analog front ends include A Ds D A PGAs reference and input conditioning circuitry e Reduced design risk all the interface design work is done e Programmable high speed DSP based on ADSP 218x Family Applications e General Purpose Analog I O e Speech Processing e Cordless and Personal Communications e Telephony e Wireless Local Loop e Active Control of Sound and Vibration e Data Communications Prog AFE Model CHNS AD73411 40 1 AD73411 80 1 Data Memory 8 8K 16 16K Pin PKG 119 PBGA 119 PBGA Powerdown Control Memory 16K PM Optional 16K DM Optional Program Data Program Programmable Full Memory Sequencer 1 0 and Mode Flags Eoee External
14. C to 70 C 128 LQFP 9 00 ADSP 2186MBST 266 8K 8K 66 40 C to 85 C 128 LQFP 9 00 ADSP 2186MKCA 300 8K 8K 75 0 C to 70 C 144 MBGA 11 00 ADSP 2186MBCA 266 8K 8K 66 40 C to 85 C 144 MBGA 11 00 ADSP 2185MKST 300 16K 16K__75 0 C to 70 C 128 LQFP 11 50 ADSP 2185MBST 266 16K 16K 66 40 C to 85 C 128 LQFP 11 50 ADSP 2185MKCA 300 16K 16K 75 0 C to 70 C 144 MBGA 13 50 ADSP 2185MBCA 266 16K 16K 66 40 C to 85 C 144 MBGA 13 50 ADSP 2189MKST 300 32K 48K 75 0 C to 70 C 128 LQFP 26 50 ADSP 2189MBST 266 32K 48K 66 40 C to 85 C 128 LQFP 26 50 ADSP 2189MKCA 300 32K 48K 75 0 C to 70 C 144 MBGA 28 50 ADSP 2189MBCA 266 32K 48K 66 40 C to 85 C 144 MBGA 28 50 ADSP 2188MKST 300 48K 56K 75 0 C to 70 C 128 LQFP 32 00 ADSP 2188MBST 266 48K 56K 66 40 C to 85 C 128 LQFP 32 00 ADSP 2188MKCA 300 48K 56K 75 0 C to 70 C 144 MBGA 34 00 ADSP 2188MBCA 266 48K 56K 66 40 C to 85 C 144 MBGA 34 00 M indicates 2 5V operation ANALOG DEVICES http www analog com dsp DSP Selection Guide 25 ADSP 219x Family Code Compatible Low Cost Low Power The ADSP 219x family maintains code com patibility with the ADSP 218x while extending architectural performance to beyond 300 MIPS Streamlined for faster processing and improved C compiler efficiency with power consumption better than 0 4mA MIP the ADSP 219x family will include multiple DSPs for applications such as telephony industrial equipment auto motive and co
15. Control applications support can be obtained at mcapps analog com Users can also obtain additional support free software upgrades and sample code by visiting the Motor Control Web site at www analog com motorcontrol ontrol Selector Guide Data Control Package RAM ADC Peripherals Options 1kx 8 Channel e 3 Phase 16 bit 144 Pin 16 bits 12 bit PWM LQFP Simultaneous Aux PWM Sampling e Encoder Interface 12 PlOs e 2 Serial Ports e Power On Reset 2k x 6 Channel e 3 Phase 16 bit 28 Pin 16 bits 10 bit PWM SOIC or F326 326 PWM SR Mode PDIP F327 327 F327 327 e 5 Channel e Aux PWM 10 bit 9 PlOs Isense Power On Reset F328 328 1kx 7 Channel e 3 Phase 16 bit 80 Pin 16 bits 10 bit PWM TQFP e Aux PWM 24 PlOs 1kx 5Channel 3 Phase 16 bit 80 Pin 16 bits 16 bit Sigma PWM TQFP Delta 76 dB Aux PWM SNR Typical Encoder Interface Converters e 12 PlOs e 2 Serial Ports ANALOG gt DEVICES ADMCF32x ADMC32x 28 Pin DSP Based Motor Controllers with Flash Memory Features Temp Instr Pin Price e Integrated ADC subsystem Model Jy ii Nge i att a cae ADMCF328 ADMC328 Five e 10 bit analog inputs plus one dedicated analog current sense ADMCF326BR Industrial 20 MHz 28Pin 15 95 5X amplifier plus PWM trip 40 C SOIC ADMCF326 7 ADMC326 7 Six 10 bit analog inputs ADMCF327BN Industrial 20 MHz 28Pin 15 95 Internal voltage reference 40 C PDIP e Three phase 16 bit PWM generation unit A
16. Lit Center ADSP 2186M REV 0 Lit Center ADSP 2187L REV 0 Lit Center ADSP 2188M REV 0 Lit Center ADSP 2189M REV A Lit Center ADSP 2188N REV Pr A Lit Center ADSP 2192 REV Pr A Lit Center NC No charge Data Sheets and Manuals Can Also Be Downloaded From the ADI DSP Website DSP Selection Guide C1891b 10 2 96 C2145 16 7 96 C1984A 6 11 95 C351 1 3 10 99 C2041c 3 3 98 C3025c 2 5 2 00 C3418 2 5 99 C3419 2 5 99 C2993 10 3 97 C3189a 3 10 98 C02047 3 5 10 00 C2999a 2 12 99 C00191a 2 5 8 00 C02048 3 5 10 00 C3174 3 7 98 C01629 2 5 9 00 C3605a 2 3 00 Preliminary Preliminary NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC gt ANALOG DEVICES DSP Literature Selection Guide Where to Order Publication or Download Number ADSP 21000 SHARC Family Publications ADSP 2106x SHARC Family User s Manual 2nd Edition Lit Center E2003a 16 5 97 NC ADSP 21065L User s Manual amp Technical Reference Lit Center 82 001833 01 NC ADSP 21160 SHARC Hardware Reference Lit Center 82 001966 01 NC ADSP 21160 SHARC Instruction Set Reference Lit Center 82 001967 01 NC ADSP 21000 Family Applications Handbook Lit Center 82 000757 01 NC A Guide To Multiprocessing Solutions from the DSP Collaborative Lit Center G3632 10 7 00 Rev A NC ADSP 21000 Family Assembler Simulator Manual From Dist through SAP ADSP 21XX DSW MAN 20 00 ADSP 21000 Family C Tools User Guide From Dist through SAP ADSP 21XX CTOOLML
17. Multiple Data SIMD SHARC The ADSP 21161N is the newest member of the high performing SIMD SHARC DSP fami ly This device offers the industry s highest 32 bit DSP performance at a price that will support consumer applications Features e 3 3 Volt external 1 8 Volt Internal e Mbit on chip SRAM e 14 Zero Overhead DMA Channels e SPI compatible port for serial host and peripheral control e 4 SPORTs supporting 128 Channel TDM and PS e 12 General Purpose I O lines 4 IRQ lines 1 Timer e Code compatible to all other SHARC Family DSPs e Single Instruction Multiple Data SIMD computational architecture two 32 bit IEEE floating point computation units each with a multiplier ALU shifter and register file e 100 MHz 10 ns core instruction rate 600 MFLOPS peak and 400 MFLOPs sus tained performance e Dual Data Address Generators DAGs with modulo and bit reverse addressing e Zero overhead looping with single cycle loop setup providing efficient program sequencing e IEEE 1149 1 JTAG standard test access port and on chip emulation e 225 ball 17x17 mm PBGA package Price eke f MHZ Pin Pkg 100 499 ADSP 21161NKB 100x 100 225 PBGA 39 00 X indicates pre release silicon N indicates 1 8 volt operation Budgetary pricing subject to change ADDS 2116X WKSHP DSP Workshop ADDS 21161N EZLITE Evaluation Kit VDSP SHARC PC FULL Complete Software Pkg ADDS MTN ICE ISA Based Emulator ADDS SUMMIT ICE PCl Based Emul
18. PS mode supports up to 16 channels e 2 timers with event capture and PWM options e 12 programmable I O pins e 10 DMA channels e Glueless multiprocessing with 2 ADSP 21065Ls e Code compatible with all SHARC family members e 3 3 volt 208 pin MQFP 196 MBGA Core Processor Instruction Cache 32 x 48 Bit Program Sequencer 24 Za PM Address Bus Processor Port Applications e Digital Audio e Keyless Entry Using Voice Analysis recognition e Bar Code Scanners e Imaging e Ultrasound Epuipment e Digital Oscilloscopes e Fingerprint Recognition Price MHz Pin Pkg 100 499 208 MQFP_ 34 50 208 MQFP 43 00 196 MBGA 42 50 Model ADSP 21065LKS 240 60 ADSP 21065LKS 264 66 ADSP 21065LKCA 240 60 ADSP 21065LKCA 264 66 196 MBGA 44 20 ADSP 21065LCS 240 60 208 MQFP 43 00 C Industrial 40 C to 100 C K Commercial 0 C to 85 C L Indicates 3 3 Volt Operation Development Tools ADDS 2106X WKSHP DSP Workshop ADDS 21065L EZLITE Evaluation Kit VDSP SHARC PC FULL Complete Software Pkg ADDS MTN ICE ADDS SUMMIT ICE ADDS APEX ICE ADDS TREK ICE ISA Based Emulator PCl Based Emulator USB Based Emulator Ethernet Based Emulator JTAG 7 Test and Emulation External Port 1 0 Po Data ddr Data J SDRAM Interface Multiprocessor Interface Host Port Dual Ported SRAM Two Independent Dual Ported Blocks DM Address Bus PM Data Bus DM Data Bus Data
19. and I O Integration simplify real time system development e Up to 14 channels of non intrusive Direct Memory Access DMA allow data movement without interrupting math processing Large On Chip Memory e Provides ample on chip storage for most common DSP tasks such as digi tal filtering and FFTs eliminating the need for off chip memory Efficient Program e Minimizes off chip memory access wait states Sequencing and e On chip hardware manages looping and provides the most efficient code Zero Overhead Looping execution with no extra programming for repetitive DSP code e No need to control looping with complex software Pin for Pin Compatible e Increase speed or memory integration within a common pin out Family Members e Adds flexibility without requiring board redesign 6 DSP Selection Guide DEVICES ADI DSP Common Features All Family Members Share These Common Features e Single cycle instruction execution e Separate program and data buses on chip e Dual purpose program memory for both instruction and data storage Three independent computation units ALU multiplier accumulator and barrel shifter e Two independent data address generators e Powerful program sequencer provides Zero overhead looping Conditional arithmetic instruction execution e Programmable wait state generation e Automatic booting of internal program mem ory from low cost byte wide external memory or other sources e g EPROM or host inter face port
20. e Single cycle context switch e Multifunction instructions ANALOG DEVICES http www analog com dsp e Edge or level sensitive external interrupts e Rich instruction set conditional execution e Nestable interruptible hardware circular buffers e Shadowing of most arithmetic registers with single level single cycle register set context switch e Support for operand unrelated parallel moves including register to register moves e Barrel shifter supports shifting by 0 32 bits e Large number of address registers e Support for modulo and bit reversed addressing DSP Selection Guide 7 VisualDSP Integrated Development Environment Features Integrated Development Environment e Define all project and tool configurations through property page dialog boxes e Set project wide or individual file settings for debug or release mode project builds e Create source files using an integrated full featured editor with syntax highlighting OLE drag and drop and bookmarks Debugger e View source files in C C assembly or mixed C and assembly e Profile and trace instruction execution of C C and assembly programs simulation only e Set watch points conditional breakpoints on processor registers and stacks as well as pro gram and data memory including Inclusive or exclusive memory range Read or write of any value or a specific value Stack overflows and underflows e Create custom register windo
21. integration of DSPs into a wide range of applications is simplified by the availability of runtime libraries included with the C compiler ADIs Applications Engineering group and our third party solutions providers have prepared code for many key algorithms Audio Signal Processing DSP Function e Reverb e Tone Control Echo e Filterin e Audio Compression e Frequency Equalization e Pitch Shifting e Spatial Effects e Surround Sound Speech Processing DSP Function Speech Synthesis Speech Recognition Speech Compression e Text to Speech e Pitch Shifting Filtering Speech Record amp Playback Communications DSP Function Modulation amp Transmission Demodulation amp Reception Speech Compression e T1 Switching DTMF e Data Encryption Signal Recovery e Echo Cancellation e Voice Over Data ANALOG DEVICES Application Musical Instruments amp Amplifiers e Audio Mixing Consoles e Recording Equipment e Disc Jockey Mixing Consoles Broadcast Equipment Cable TV Equipment Audio Equipment amp Boards for PCs e Toys amp Games e Automotive Sound Systems Digital Audio Tape Players Compact Disk Players HDTV Equipment Digital TV Recommended DSPs e ADSP 21065L ADSP 21160M e ADSP 21161N Application Digital Tapeless Recorders e Voice Store Equipment e Phone Mail e Voice Secure Entry Systems e Intercom Systems e Personal ID
22. range of applications due to flexible architecture and high level of memory and peripheral integration e Fastest interrupt response time due to alternate register set e High dynamic range offered by 40 bit accu mulator e Easy to use assembly language syntax DSP Selection Guide V 34 Annex 12 V 34 V 32bis V 22bis V 42 V 42bis MNP2 5 V 17 Fax Group3 T 30 T 4 Fax Protocol G 729 Annex A G 711 G 721 G 726 G 722 G 723 G 728 G 729A G 729A G 729 GSM FR GSM EFR GSM HR M GSM CELP Single Sample FIR Filter Complex Block FIR Filter IIR Biquad Filter Section Lattice Filter Section 256 Point Complex FFT 1024 Point Complex FFT 4096 Point Complex FFT 256 Tap LMS Adaptive Filter Coefficient Update 10th Order LPC Analysis 240 Point Rectangular Window ADPCM Full Transcode CCITT G 721 ANSI TI 301 1987 16K ai 16K 11 5 7 5K 3 4 5 2K 0 5 5 3K 4 5 1K SS 4 3K 6 5 7 7K 2 5 7 6K 10 7K 64 Kbps 32 Kbps 16 40 Kbps 64 Kbps 5 3 6 3 Kbps 16 Kbps 8 Kbps 8 Kbps 8 Kbps 13 Kbps 12 2 Kbps 5 6 Kbps 5 0 and 6 5 Kbps 4 3 and 7 5 Kbps cea 16K 16K 7K 1 1K ADSP 218x Family 31 Inst Clock 2941 Inst Clocks 7 Inst Clocks 5 Inst Clocks 7372 Inst Clocks 34K Inst Clocks 149K Inst Clocks 516 Inst Clocks 4666 Inst Clocks 893 Inst Clocks Benchmarks for ADSP 218X DSPs Modem Algorithm Me 33 6 Kbps 3 8K 28 8 Kbps 3 7K 28 8 Kbps 512 entries
23. the ADSP 218x and ADSP 219x DSPs the Suey newest processors in the ADSP 2100 family Code Compatible 16 BIT RAM ROM RAM Serial Generic ee E Words Words Words _ Price ADSP 2192 32K 100K 60 00 ADSP 2188M sia on 5 a 48K 56K 5 32 00 ADSP 2188N ST CA m 1 8V 48K 56K 2 30 00 ADSP 2189M ST CA 75 2 5V 32K 48K 2 26 50 ADSP 2189N ST CA 80 1 8V 32K 48K 2 25 00 ADSP 2187L ST 52 3 3V 32K 32K 2 37 17 ADSP 2187N ST CA 80 1 8V 32K 32K 2 20 00 ADSP 2185 ST 33 5V 16K 16K 2 23 05 ADSP 2185L ST CA 52 3 3V 16K 16K 2 21 95 ADSP 2185M ST CA 75 2 5V 16K 16K 2 11 50 ADSP 2185N ST CA 80 1 8V 16K 16K 2 11 25 ADSP 2186 ST CA 40 5V 8K 8K 2 17 28 ADSP 2186L ST CA 40 3 3V 8K 8K 2 17 28 ADSP 2186M ST CA 75 2 5V 8K 8K 2 9 00 ADSP 2186N ST CA 80 1 8V 8K 8K 2 8 50 ADSP 2184 ST 40 5V 4K 4K 2 10 00 ADSP 2184L ST 40 3 3V 4K 4K 2 10 00 ADSP 2184N ST CA 80 1 8V 4K 4K 2 7 00 ADSP 2183 S CA 52 3 3V 16K 16K 2 21 95 ADSP 2181 SSi 40 5V 16K 16K 2 20 95 ADSP 2173 STSI 20 3 3V 2K 2K 2 45 13 ADSP 2171 S ST 33 5V 2K 2K 2 37 41 ADSP 2166 BS 16 7 3 3V 1K 12K 4K 2 CF ADSP 2165 BS 20 5V 1K 12K 4K 2 CF ADSP 2164 PES 10 2 3 3V 4K 0 5K 2 CF ADSP 2163 BS 16 7 5V 4K 0 5K 2 CF ADSP 2162 RS 10 2 3 3V 8K 0 5K 2 CF ADSP 2161 BS 16 7 5V 8K 0 5K 2 CF ADSP 2115 PESASI 25 5V 1K 0 5K 2 14 11 ADSP 2111 G S 20 5V 2K 1K 2 114 06 ADSP 2105 P 20 5V 1K 0 5K 1 11 90 ADSP 2104 P 20 5V 0 5K 0 25K 1 7 32 ADSP 2103 BS 10 3 3V 2K 1K 2 26 02 ADSP 2101 GIRIS 25
24. 0 Mbit s independent serial ports one from each SHARC One 40 Mbit s common serial port Ceramic quad flat pack with enhanced I O Low profile 2 05 308 lead ceramic quad flat pack package AD14160 Sixteen 40 Mbyte s link ports per SHARC accessible to from the outside world Eight link ports connected internally in ring configuration Eight 40 Mbit s independent serial ports two from each SHARC available from outside Ceramic ball grid array QUAD SHARC with enhanced I O Low profile 1 85 ceramic ball grid array package For any further inquiries please contact MCP Marketing in Greensboro NC 336 668 9511 Le DSP Selection Guide 41 dspConverter Integrated DSP and Data Converter for Voice Processing ADI s dspConverters feature our industry lead ing data converters 16 bit fixed point DSPs and flash memory all packed into one small 14 mm x 22 mm BGA package The analog front ends are based on our AD733xx family which include 16 bit linear codecs input output conditioning circuitry and a flexible serial interface The DSPs are based on the ADSP 218x family Analog Front Ends AFEs The analog front ends are much more than codecs Each channel includes e Sigma delta DAC e Sigma delta ADC e PGA for each encoder and decoder e Input conditioning circuitry e Reference SPORT No Digital Feedthrough Problems One of the critical aspects of mixed signal desi
25. 00 C case Speed Grade 1 MIPS or MHz e g 100 100 MIPS 100 MHz ADSP 219X Part Numbering x Device Type y Peripherals Multi Channel A Set 1 1 65K B Set 2 2 128K C A p v Voltage M 2 5 Single Channel F Flash 5 bg aS N 1 8 P 1 5 6 16K 7 R 1 2 8 S 1 0 A D s P 2 i elxly v t piplalajal A 2 B N BCA 3 C P Y 4 D R S 3 Pack p Package SF ST LQFP 7 CA MiniBGA 8 t Temp ADIS P Analog Devices DSP K 0 70 16 Bit fixed point code compatible DSPs A Integrates 9x core S 55 125 20 DSP Selection Guide gt hea Processor Selection Guide ADSP 2100 16 Bit DSP Family The ADSP 2100 family is built around a com mon instruction set architecture ISA which is 16 Bit DSP Family Tree A History of Improvements in Packaging Power Performance optimized for signal processing Within the ADSP 2100 family all processors are code Extend 21xx ISA enna 7 esc e Continually Improve 0 4 mA MIPs compatible allowing additional features and Tools LaFP gt D performance while protecting software develop oats ann ment investment Each family member differs ein h poe bee na PLCC of in circuitry added to the base architecture such D 400 oa i e aD BE as memory processor speed serial ports and AR CD D other peripherals The following pages detail o ina por
26. 135 ns 45 ns 1024 Point Complex FFT in place 32 BIT Floating Point DSPs DSP Instruction Instruction Number Total FFT Processor Rate Cycle Time of Cycles Time TMS320C6701 167 MHz 6 ns 19 875 0 12 ms TMS320C6711 150 MHz 6 7 ns 19 875 0 13 ms TMS320C6712 100 MHz 10 ns 19 875 0 19 ms ADSP 21065L 66 MHz 15 ns 18 221 0 27 ms ADSP 21160N 90 MHz 11 ns 9 111 0 10 ms ADSP 21161N 100 MHz 10 ns 9 111 0 09 ms Specification Source TI website www ti com DEVICES DSP Selection Guide 19 Part Numbering System DSP Part Numbering Packaging Code S Plastic Quad Flat Pack MQFP ST Thin LQFP B Plastic Ball Grid Array PBGA Power Code Z Ceramic QFP Heat slug up L Low Power 3 3V W Ceramic QFP Heat slug down X Grade M 2 5V internal 3 3V I O P PLCC X X Grade Analog Devices No Suffix 5V G PGA No Suffix Production Digital Signal Processing Exception ADSP 2183 3 3V CA mini BGA Released ADSP 21xx x X X XX HEH XR or REEL Product Number Temperature Codes Speed Grade Code Tape and Reel 21XX 16 Bit K Commercial Speed Grade 4 MIPS or MHz 21XXX 32 Bit 0 C to 70 C ambient 16 Bit e g 133 33 MIPS 40 MHz 0 C to 85 C case 32 Bit 160 40 MIPS 40 MHz T Extended temperature grades 200 50 MIPS 50 MHz A Industrial 40 C to 85 C case 300 75 MIPS 75 MHz B Industrial 40 C to 85 C ambient Exception ADSP 2116x products C Industrial 40 C to 1
27. 14060 AD14160 or 3 3V AD14060L AD14160L versions Competition With 480 MFLOPS of throughput the AD14060 AD14160 have no close competitors TI s Dual C40 MCM provides a similar func tion but delivers only 80 MFLOPS in a signifi cantly larger package and roughly equivalent cost The Quad SHARC AD14060 AD 14160 is targeted to be priced such that users can take advantage of system cost advantages of using MCMs ideal for applications requiring higher i i t t t t oO J O A levels of performance and or function TERE EEE ality per unit area a CPA LINK 0 E LINK 0 CPA Be SHARC A ule gic SHARCIB jal ID20 1 5 TDO gt TDI Do2 The AD14060 AD14160 take advan g E g 4 tage of the built in multiprocessing Be F 5 gg Bb Ei z TP features of the ADSP 21060 to F Iri e ae achieve 480 peak MFLOPS witha sin k lg y gle chip type in a single package The F f H 7 on chip SRAM of the DSPs provides AD14060 ADDR31 9 DATAy 9 MS3 o RD WR PAGE ADRCLK SW ACK 16 Mbi f d l h d SRAM AD14060L SHARC BUS SBTS HBR HBG REDY BR6 1 RPBA DMAR4 2 DMAG4 2 its of on module share f I A The complete shared bus 48 bit data l 7 32 address is also brought off module yy try A A AAAA E22 zj pag E22 zii er ggo for interfacing with expansion memory gle ESI BES 3 gla 3 ig p
28. 188N 2 200 200 1 8V 3 3V 144BGA TMS320VC5421 ADSP 2192 2 200 256 1 8V 3 3V 144BGA TMS320VC5441 ADSP 2192 4 532 640 1 5V 3 3V 179BGA TMS320VC5510 ADSP 219x 1 400 160 1 6V 3 3V 240BGA TMS3206201 ADSP 2192 1 400 80 1 8V 3 3V 352BGA TMS3206202 ADSP 2192 1 500 128 1 8V 3 3V 352BGA TMS3206203 ADSP 2192 1 600 608 1 5V 3 3V 352BGA TMS3206204 ADSP 2192 1 400 80 1 5V 3 3V 288BGA TMS3206205 ADSP 2192 1 400 80 1 5V 3 3V 288BGA TMS3206211 ADSP 2192 1 334 72 1 8V 3 3V 256BGA Note Analog Devices BGA package is 10 mm x 10 mm TI BGA package is 12 mm x 12 mm DEVICES DSP Selection Guide 15 Benchmarks Comparing DSPs To truly assess a processor s performance you have to look beyond MHz MIPS or MFLOPS There are many attributes which may be more accurate predictors of a DSP s real time embed ded processing performance Circular Buffers Circular buffers allow a region of memory to be continually accessed without explicit program interaction The buffer uses a pointer that auto matically resets to the beginning of the buffer wrap around if the pointer is advanced beyond the last location in the buffer Circular buffers are a key feature of DSP routines Multiple buffers are used in the same routine to store filter coefficients and implement a delay line of input samples Performance suffers if the DSP core has to perform pointer calcula tions along with the calculations for the rou tine Performance also suffers if t
29. 25 00 ADSP 21000 Family C Runtime Library Reference From Dist through SAP ADSP 21XX CRTL ML 10 00 ADSP 21060 ADSP 21060L Rev D Lit Center C3165d 2 5 12 99 NC ADSP 21061 ADSP 21061L Rev B Lit Center C3244a 2 5 6 99 NC ADSP 21062 ADSP 21062L Rev C Lit Center C3078c 2 5 12 99 NC ADSP 21065L Rev B Lit Center C3533b 3 5 00 NC ADSP 21060C ADSP 21060LC Rev B Lit Center C00168a 0 1 01 NC ADSP 21160M REV Pr E Lit Center Preliminary ADSP 21161N REV Pr A Lit Center Preliminary ADSP 21065L EZ LAB System Development Manual www analog com dsp 82 001916 01 ADSP 2106x EZ KIT Lite Manual www analog com dsp 82 001916 02 NE Apex ICE USB Emulator Hardware Installation Guide www analog com dsp MANAPEXICE NC Trek ICE Universal Emulator Hardware and Software Installation Guide www analog com dsp MANTREKICE NC Mountain ICE Emulator Hardware User s Guide www analog com dsp MANMTNICE NC Summit ICE Emulator Hardware User s Guide www analog com dsp MANSUMICE na VisualDSP Emulation Tools Installation Guide for Windows 95 98 NT 2000 www analog com dsp MANVDSPMU Complete Set of ADSP 21xx VDSP Manuals includes the following From Dist Ta SAP VDSP SHARC MAN FULL 100 00 VisualDSP Getting Started Guide VisualDSP User s Guide for the ADSP 21xxx Family DSPs Assembler Manual for the ADSP 21xxx Family DSPs C C Compiler amp Library Manual for the ADSP 21xxx Family DSPs Linker amp Utilities for the ADSP 21xxx Family DSPs Product Bul
30. 3 e CD Ripping audio standard e Home Theatre e Supports half sampling frequencies of 16 e Internet Audio 22 05 and 24 kHz and full sampling frequen e Internet Distribution of Original Music cies of 32 44 1 and 48 kHz per channel e Previewing Favorite Artists eSupports 8 kbps to 160 kbps bit rates for half sampling frequencies 32 kbps to 320 kbps for full sampling frequencies ADSST DAP EVALO1 75 Reference e Compact single chip chipset or 85 mm x Beige 60 mm x 30 mm board its e Supports multiple storage types e Operates in real time e Directly encodes MP3 onto the device e Requires no external SRAM or SDRAM e Supports watermarking technology and DRM e Includes bass boost and equalize DC IN 5V Samsung oo ia 46MB 8MB x 2 yte gt lt q ma ADSST 1885 p AKM SPO MIC IN amp Audio IN ote gt g ADSST 2185M DAP 1 0 Block Diagram Recorder 46 DSP Selection Guide http i www analog com solutions Cacevices ADSST PEGASUS SDK Melody Floating Point Audio Encoders Decoders Features e Decodes DTS Discrete 6 1 DTS ES Matrix 6 1 DTS Neo 6 Dolby Digital Dolby Pro Logic Dolby Pro Logic II Dolby Headphone HDCD MPEG Audio Layer 3 MP3 MPEG Audio Layers 1 and 2 AAC PCM MLP SRS 3D Wave Surround Stereo e Post Processes THX Surround EX THX Select THX Ultra e Encodes Dolby Digital Consumer Encoding DDCE and MPEG1 Audio Layers 1 2 and 3 MP3 e Autodetects and displays bitstream info
31. ADSP 21061 L S 50 3 3 5V 1 Mbit 2 58 00 ADSP 21060 L B S 40 3 3 5V 4 Mbits 2 245 00 Package B Plastic Ball Grid Array PBGA G Ceramic Pin Grid Array PGA S Plastic Quad Flat Pack PQFP CA Mini Ball Grid Array MBGA US Dollars Lowest grade suggested resale price per unit in 100 unit quantities DEVICES DSP Selection Guide 29 30 ADSP 21160 Single Instruction Multiple Data SHARC Features e 540 MFLOPS 32 bit floating point peak operation e 540 MOPS 32 bit fixed point peak operation e 90 MHz core operation 11 ns cycle time e 92 us 1024 point comlex FFT benchmark with bit reversal e Code compatible with first generation SHARC e SIMD core includes 2 multipliers 2 ALUs 2 shifters and 2 register files e 4 Mbits on chip dual ported SRAM e Division of SRAM between program and data memory is selectable e Core can fetch four 32 bit words from mem ory in a single processor cycle using two 64 bit wide buses e Dual data address generators with modulo and bit reverse addressing e Efficient program sequencing with zero over head looping single cycle loop setup e IEEE JTAG standard 1149 1 test access port and on chip emulation e 32 bit single precision IEEE floating point data type and 40 bit extended precision floating point data type support e 32 bit fixed point formats integer and frac tional with 80 bit accumulators in both pro cessing elements e 14 channels of zero overhead DMA e Gluel
32. APEX ICE 4995 VDSP SHARC PC FULL 2995 Available 2Q01 ADDS TREK ICE 5995 ADDS SUMMIT ICE 3995 DEVICES DSP Selection Guide 3 Analog Devices is the world s fastest growing DSP supplier Our portfolio includes mixed signal DSPs general purpose DSPs such as the SHARC family and embedded DSP solutions that serve secure data ADSL modems GSM handsets internet access speech processing and motor control applications ADI leverages 30 years of high performance analog expertise to develop DSPs that make the design challenge easier ADI s DSP architectures feature simple yet powerful programming models and are supported by the White Mountain brand of high quality development tools More than 30 000 software developers have invested in our 16 bit and 32 bit fixed point and floating point DSP architectures The ADSP 2100 family has inspired thousands of high performance applications at the forefront of DSP integration All DSPs in the ADSP 2100 family share the same base architecture and algebraic assembly language The trademark simplicity of the assembly programming language makes learning code reading code and using code very easy More memory faster processing and lower power consumption have made these workhorses the right choices in more than 10 000 designs Our commitment to meeting our customers production needs will keep applications of 16 bit DSPs growing strong First to market with industry standard MACs in CMOS First programmable
33. Customer Support 52 2 16 Bit DSP Key Products Recommended for New Designs 150 50 Code Compatible Code Compatible and gt J 218X D Pin Compatible N Series v 80 MIPS Up to 2MBit SRAM 0 3 mA MIP 1 8V 218X D M Series 75 MIPS Up to 2MBit SRAM 218X D L Series 33 52 MIPS 0 5 mA MIP 2 5V Up to 1 2MBit SRAM D MIPS Up to 2 5MBit SRAM 0 8 mA MIP 3 3V 1998 1999 2000 Program 16 Bit RAM Generic Package Max MIPS Words Status Price Samples Mar 01 ADSP 2192 ST 320 2 5V 32K 100K Release 3Q01 53 20 ADSP 2188M ST CA 75 2 5V 48K 56K Released 28 00 Samples Now ADSP 2188N ST CA 80 1 8V 48K 56K Release 2Q01 26 00 ADSP 2189M_ ST CA 75 2 5V 32K 48K Released 23 00 Samples Now ADSP 2189N ST CA 80 1 8V 32K 48K Release 2Q01 21 00 Samples Now ADSP 2187N ST CA 80 1 8V 32K 32K Release 2Q01 17 00 ADSP 2185M ST CA 75 2 5V 16K 16K Released 10 00 Samples Now ADSP 2185N ST CA 80 1 8V 16K 16K Release 2Q01 9 50 ADSP 2186M ST CA 75 2 5V 8K 8K Released 7 50 Samples Now ADSP 2186N ST CA 80 1 8V 8K 8K Release 2Q01 7 25 Samples Now ADSP 2184N ST CA 80 1 8V 4K 4K Release 2Q01 5 75 Packages ST Thin Quad Flat Pack TQFP CA Mini Ball Grid Array 10 x 10 mm US Dollars Lowest grade suggested resale price per unit in 1000 unit quantities Budgetary pricing subject to change Development Software Evaluation Processor Development Platform Emulator AD
34. DMCF327BR Industrial 20 MHz 28Pin 15 95 40 C SOIC Switched reluctance specific PWM generation unit ADMCF327 ADMC327 only ADMCF328BN Industrial 20 MHz 28Pin 15 95 oa 40 C PDIP e Two 8 bit auxiliary PWM outputs 20 MIPS fixed point DSP core ADMCF328BR Industrial 20MHz 28Pin 15 95 4K x 24 bit program flash 40 C SOIC memory ADMCF32x only Three independently written A unique model Industrial 20MHz 28Pin 15 95 sectors number is assigned 40 C PDIP to each ROM order to 85 C Non volatile security lock bits received Automotive 28 Pin 10K erase program cycles 40 C SOIC to 85 C 4K x 24 bit program memory ROM ADMC32x only Development Tools 512 x 24 bit program memory ADMCF326 EVALKIT ADMCF326 evaluation board 395 00 RAM and motor control develop ment tools assembler linker 512 x 16 bit data memory RAM debugger e 9 Bits of programmable digital I O ADMCF327 EVALKIT ADMCF327 evaluation board 395 00 e Integrated power on reset function and motor control develop e Pin f tible ROM options ment tools assembler linker a P AOIL Gr EDU package ADMCF328 EVALKIT ADMCF328 evaluation board 395 00 options and motor control develop ment tools assembler linker debugger ANALOG DEVICES http www analog com motorcontrol DSP Selection Guide 35 ADMCF32x ADMC32x Benefits e ADC subsystems and peripherals tailored for specific motor types to simplify development e 28 pin
35. DSP Selection Guide 2001 Edition N iE i Reps 30 35 5 0 9 30 35 02 30 35 0130 35 23 00 35 19 30 5 19 30 35 18 30 35 eas ANALOG Z DEVICES Table of Contents Introduction to ADI DSPs 16 Bit DSP Key Products 2 32 Bit DSP Key Products 3 ADI DSP Overview 4 Markets amp Applications 5 Key Benefits 6 Common Features T Processor Selection Guides ADSP 2100 Family 16 Bit Processor Selection Guide 21 ADSP 21000 Family 32 Bit SHARC Processor Selection Guide 29 ADMC DSP Based Motor Controllers 34 AD73xxx dspConverters 42 DSP Development Tools VisualDSP Development Tools 8 _16 Bit Tools o y Oa _32 Bit Tools o OB Third Party Program The DSP Collaborative 14 Competitor Cross Reference 15 Benchmarks Comparing DSPs 16 ADSP 2100 Family 16 Bit DSPs 18 ADSP 21000 Family 32 Bit DSPs 19 DSP Part Numbering System 20 Product Specifications ADSP 2100 16 Bit Famil 21 ADSP 218xN Famil 24 ADSP 218xM Famil 25 ADSP 219x Overview 26 ADSP 2192 27 ADSP 21000 32 Bit SHARC Family 29 ADSP 21160M N 30 TADSP 2HGIN OOOOOYO Z O _ADSP 21065L_ 88 DSP Based Motor Controllers 34 ADMCF32x ADMC32x 35 _ADMC40 8 _ADMC33 S OB _ADMC300 8 Quad SHARCs 40 AD14060 AD14160 40 dspConverters 42 ADBA S B AD73422 44 Software amp Systems Technologies SST 45 ADSST MPEG EVALO1 45 ADSST DAP EVALO1 46 ADSST PEGASUS SDK 47 Technical Training Workshops 48 University Program 49 Literature Selection Guide 50 DSP
36. DSP development via common development environment across all ADI hardware and DSPs The debugger has many features that greatly reduce debugging time C C source can be viewed interspersed with the resulting assembly code Users can profile execution of a range of instructions in a program set watch points on hardware and software registers program and data memory and trace instruction execution and memory accesses These features enable ANALOG DEVICES ee users to correct coding errors identify bottlenecks and examine DSP performance The custom register option allows developers to select any combination of registers to view in a single window The debugger when used with the simulator can also generate inputs outputs and interrupts to simulate real world application conditions With C developers can realize a significant increase in time to market with the ability to efficiently work with complex signal processing data types and take advantage of specialized DSP operations without having to understand the underlying DSP architecture VisualDSP simplifies DSP development via common development environment across all Analog Devices hardware and DSPs TCL Command Line interface Tool command line Tcl scripting language facilitates executing repeated sequences of debugger commands This powerful C like interface allows developing complete test applications of DSP systems Multiprocessing Support VisualDSP
37. Rate PKG 100 499 ADMC401BST Industrial 26 MHz 144 Pin 24 95 40 C LQFP to 85 C Development Tools Price ADMC401 ADEVALKIT 395 00 ADMC401 evaluation board and motor control development tools assembler linker debugger Motor Control 4 Peripherals Memory Block Program Event Interrupt Capture Controller Timers remove system cost Program Memory Address Data Memory Address Program Memory Data Data Memory Data Arithmetic Units ANALOG DEVICES Serial Ports http www analog com motorcontrol Precision Voltage Reference DSP Selection Guide 37 ADMC331 Single Chip DSP Based Motor Controller Features e Seven channel 10 bit analog to digital converter e Three Phase 16 bit PWM generation unit e Two 8 bit auxiliary PWM outputs e 26 MIPS fixed point DSP core 2K x 24 bit program memory RAM 2K x 24 bit program memory ROM 1K x 16 bit data memory RAM e 24 Bits of programmable digital I O e Preprogrammed mathematical functions e Preprogrammed motor control functions Vector Transformations e 16 bit watchdog timer e Two double buffered synchronous serial ports Benefits e Single chip solution with integrated motor control peripherals simplifies hardware devel opment and reduces system cost e Preprogrammed mathematical and motor con trol functions simpli
38. SP 2187L 1 52 64 3 3V 144BGA ADSP 2185M 1 75 32 2 5V 2 5V 3 3V 144BGA ADSP 2186M 1 75 16 2 5V 2 5V 3 3V 144BGA ADSP 2188M 1 75 104 2 5V 2 5V 3 3V 144BGA ADSP 2189M 1 75 80 2 5V 2 5V 3 3V 144BGA ADSP 2184N 1 80 8 1 8V 3 3V 144BGA ADSP 2185N 1 80 32 1 8V 3 3V 144BGA ADSP 2186N 1 80 16 1 8V 3 3V 144BGA ADSP 2187N 1 80 64 1 8V 3 3V 144BGA ADSP 2188N 1 80 104 1 8V 3 3V 144BGA ADSP 2189N 1 80 80 1 8V 3 3V 144BGA ADSP 2192 2 320 132 2 5V 3 3V 144LQFP TMS320C541 ADSP 2181 2185 1 40 5 5V 100TQFP TMS320C542 ADSP 2181 2185 1 40 10 5V 128TQFP TMS320LC541 ADSP 2185L 2186L 1 66 5 3 3V 100TQFP TMS320LC542 ADSP 2185L 2186L 1 50 10 3 3V 128TQFP TMS320LC543 ADSP 2185L 2186L 1 50 10 3 3V 100TQFP TMS320LC545A ADSP 2185L 2186L 1 66 6 3 3V 128TQFP TMS320LC546A ADSP 2185L 2186L 1 66 6 3 3V 100TQFP TMS320LC548 ADSP 2185L 2187L 1 66 32 3 3V 144BGA TMS320LC549 ADSP 2185L 2187L 1 80 32 3 3V 144BGA TMS320UC5402 ADSP 2186N 1 80 16 1 8V 1 8V 3 3V 144BGA TMS320UC5409 ADSP 2185N 1 80 32 1 8V 1 8V 3 3V 144BGA TMS320UVC5401 ADSP 2184N 1 50 8 1 8V 3 3V 144BGA TMS320UVC5402 ADSP 2186N 1 30 16 1 2V 1 2V 2 75V 144BGA TMS320UVC5409 ADSP 2185N 1 30 32 1 2V 1 2V 2 75V 144BGA TMS320VC549 ADSP 2185N 1 120 32 2 5V 3 3V 144BGA TMS320VC5402 ADSP 2186N 1 100 16 1 8V 3 3V 144BGA TMS320VC5409A ADSP 2185N 1 160 32 1 8V 3 3V 144BGA TMS320VC5410A ADSP 2187N 1 160 64 2 5V 3 3V 176BGA TMS320VC5416 ADSP 2188N 1 160 128 1 5V 3 3V 144BGA TMS320VC5420 ADSP 2
39. SP 218xM ADDS 2189M EZLITE 295 ADSP 218xN ADDS 2189M EZLITE 295 ADSP 2192 ADDS 2192 12EZLITE 295 DSP Selection Guide ADDS 218X ICE 1 8V 1995 ADDS 218X ICE 1 8V 1995 ADDS APEX ICE 4995 ADDS TREK ICE 5995 ADDS SUMMIT ICE 3995 http www analog com dsp VDSP 21XX PC FULL 2995 VDSP 21XX PC FULL 2995 VDSP 21XX PC FULL 2995 O ANALOG DEVICES 32 Bit SHARC DSP Key Products Recommended for New Designs 10 000 2 400 4 1 200 4 wo 750 7 a SIMD SHARC Ta aD 100 MHz SHARC Core 600 SIMD Doubles Cycles Performance 198 gt C 210651 3 SISD SHARC 60 MHz SHARC Core 120 rT Time 32 Bit Max On Chip Generic Package MFLOPS Vcc SRAM Status Price ADSP 21160N B 540 1 9 3 3V 4 Mbits Samples 4Q01 145 00 ADSP 21160M B 480 2 5 3 3V 4 Mbits Released 145 00 ADSP 21065L S B 198 3 3V 544 Kbits Released 30 00 Samples 2Q01 ADSP 21161N B 600 1 8 3 3V 1 Mbits Released 1Q02 34 32 Packages B Plastic Ball Grid Array PBGA S Plastic Quad Flat Pack PQFP US Dollars Lowest grade suggested resale price per unit in 1000 unit quantities Evaluation Development Processor Development Platform Emulator Software ADSP 21065L ADDS 21065L EZLITE 299 ADDS APEX ICE 4995 VDSP SHARC PC FULL 2995 ADDS TREK ICE 5995 ADDS SUMMIT ICE 3995 ADSP 21160M ADDS 21160M EZLITE 595 ADDS APEX ICE 4995 VDSP SHARC PC FULL 2995 ADDS TREK ICE 5995 ADDS SUMMIT ICE 3995 ADSP 21161N ADDS 21161N EZLITE TBD ADDS
40. Systems Audio Equipment amp Boards for PCs Toys amp Games Recommended DSPs ADSP 218XM N ADSP 21065L e ADSP 21161N Application Modems e Fax Machines e PBX Systems e Phone Mail Systems Private Data Communications Systems e Automatic Teller Machines Broadcast Equipment e Mobile Phones Digital Pagers Global Positioning Systems Secure Speaker amp Video Telephones Digital Answering Machines Satellite Phones e Wireless Local Loop Telecom Infrastructure Recommended DSPs e ADSP 218XM N ADSP 21065L http www analog com dsp DSP Function e Fast Fourier Transform FFT e Waveform Synthesis Adaptive Filtering e High Speed Numeric e Echo Cancellation e Fast Fourier Transform FFT Beam Forming e Pattern Recognition e Image Smoothing e Fast Fourier Transform Control Loops e Noise Cancellation Instrumentation and Measurement Application Test amp Measurement Equipment e Vibration Analysis Equipment I O Cards for PCs e Automotive Engine Analyzers e Automotive Wheel Balancers e Industrial Scales amp Measurement e Active Mufflers Oil Drilling Equipment e Seismic Instruments e Power Meters e Exercise Machines e Signal Analyzers e Function Signal Generators Recommended DSPs ADSP 218XM N ADSP 21065L ADSP 21161N Medical Electronics DSP Function Application e Respiration Monitoring Equipment e Heart Rate Cardi
41. X ICE ADDS TREK ICE ADDS SUMMIT ICE ADDS MTN ICE ADSP 2106X Family ADSP 21160M N ADSP 21161N ADSP 21065L Complete Package IDE Debugger Compiler Assembler Linker with Emulation and Simulation Support Code Gen Package Compiler Assembler Linker Assembler Package Assembler Linker IDE Debugger Package IDE Debugger with Emulation and Simulation Support Floating VisualDSP VisualDSP Test Drive 30 Day Free Trial Apex ICE USB Based Emulator Trek ICE Ethernet Based Emulator Summit ICE PCI Based Emulator Mountain ICE ISA Based Emulator E a http www analog com dsp tools DSP Selection Guide 13 14 DSP Selection Guide The DSP Collaborative ADI s Third Party Partner Program ANALOG DEVICES The DSP Collaborative partners Analog Devices Third Party Program offer tools ser vices and solutions for a wide range of applica tions markets Communications Audio Medical Imaging Radar Sonar Motion Control Motor Control Industrial Automation Signal Intelligence When you select Analog Devices as your DSP vendor you re broadening your design team to include the industry leading resources of the DSP Collaborative The DSP Collaborative is comprised of over 80 partners who offer more than 400 commercial products in addition to hundreds of custom solutions that build on more than 30 years of signal processing experi ence found in every one of our DSPs These partners offer
42. ac Monitoring e Ultra Sound Equipment e Medical Imaging Equipment Blood Analyzers e Fetal Infant Monitors e Patient Monitors e Blood Flow Monitors e CAT Scanners e Hearing Aides Recommended DSPs ADSP 218XM N e ADSP 2116X e ADSP 2106X Optical and Image Processing DSP Function 2 Dimensional Filtering e Fast Fourier Transform FFT Application e Bar Code Scanners e Underwater Object Finders e Automatic Inspection Systems Fingerprint Recognition e Digital Televisions e Sonar Radar Systems e Robotic Vision e Vision Systems Recommended DSPs ADSP 2106X ADSP 2116X Industrial Motor Control DSP Function Application e Motors in Appliances Robotics or Office Automation e Power Management Equipment e Generators e Elevators e Air Conditioners e Traffic Control Systems e Navigation e Disk Drives e High Speed Controls e Vibration Analyzers Recommended DSPs ADSP 2106X ADSP 21160M ADMCXXX e ADSP 218XM N DSP Selection Guide 5 ADI DSP Key Benefits Selecting a DSP processor can be a difficult task language support To understand the benefits of Design engineers are concerned with time to mar ADTs families of 16 and 32 bit DSPs and how ket for which ease of use quality development ADIs architectures are optimized for digital sig tools extensive application engineering support nal processing keep in mind three basic features and the availability of algor
43. ackage ADSP 218x 219x Assembler Linker IDE Debugger Package ADSP 218x 219x IDE Debugger with Emulation and Simulation Support Floating VisualDSP ADSP 218x 219x VisualDSP Test Drive ADSP 218x 219x 30 Day Free Trial JTAG Emulators for the ADSP 219x DSP Family ADDS 218X ICE 1 8V ADDS 2189M EZLITE ADDS 2192 12EZLITE VDSP 21 XX PC FULL VDSP 21 XX PC CAL VDSP 21 XX PC AL VDSP 21 XX PC DIS VDSP 21XX PCFLOAT VDSP 21XX PC TEST ADDS APEX ICE ADSP 219x ADDS SUMMIT ICE ADSP 219x ADDS TREK ICE ADSP 219x ADDS MTN ICE ADSP 219x ANALOG DEVICES Development Tools SHARC DSPs are the highest performance 32 bit DSPs available These single chip sys tem solutions optimize memory I O and core speed ADI offers over 50 32 bit processors for computing communications audio industrial mil aero and consumer applications Within the ADSP 21000 SHARC Family all processors are code compatible allowing addi tional features and performance while protect ing software development investment The SHARC family is unique among 32 bit DSPs in that it processes fixed point data at the same speed as it processes floating point data Designers may use both math types depending on their application needs Development Software VisualDSP is a comprehensive toolset for SHARC DSPs VisualDSP enables design engineers to easily develop debug and deploy code throughout the research design develop ment and test sta
44. atible with all ADSP 21xx DSPs Features e 13 ns instruction cycle time 75 MIPS e Up to 48K words of on chip program RAM e Up to 56K words of on chip data memory RAM e 2 5 volt core supply with up to 3 3 volt I O e 16 Bit Internal DMA Port e 8 Bit Byte Memory DMA e Two Double Buffered Serial Ports 1 with TDM mode e JJO Memory Interface w 2048 Locations e ADSP 2100 Family code amp function compatible e 0 5 mA MIP power consumption e 100 Lead LQFP 144 Lead miniBGA Development Tools Benefits e Algebraic assembly language for easy pro gramming e On chip RAM and 6 DMA channels e 16 Bit DMA port makes bus interfacing easier e 5 sleep and powerdown modes maximize bat tery life e 144 Ball mini BGA package provides for maximum space savings 10 mm x 10 mm Applications e Consumer Telephony e Speaker Phones e Embedded Speech e Digital Speech Processing Interpolation e POS Terminals e Data Encryption e PBX e ISDN Modems e Smartcard Readers e VOIP Phone e Multi channel Voice e Pattern Matching Processing e Satellite Telephone e Industrial Measurement and Control e Zero Install Full Duplex e Global Positioning e Navigation e Network Access Servers ADDS 218x WKSHP DSP Workshop ADDS 218x ICE 1 8V In circuit Emulator Hands Free Car Kit ADDS 2189M EZ LITE Evaluation Kit VDSP 21xx PC FULL Complete Software Pkg Model PM DM MHz Temperature Pin Pkg Price 100 499 ADSP 2186MKST 300 8K 8K 75 0
45. ator ADDS APEX ICE USB Based Emulator ADDS TREK ICE Ethernet Based Emulator Benefits e Two 100 Mbyte S link ports simplify connec tion and communication in multiprocessing systems e 14 zero overhead DMA channels mean no cycles stolen from the core to move data on and off chip e Cluster multiprocessing enables universally addressable memory system e SDRAM controller for controlling large banks of DRAM e 4 serial ports allow for 16 channels of data to be transferred in out of the DSP Applications e Video Phones e Power Line Modems e Finger Print Recognition e Medical Equipment e Multi Access Motor Control e Automatic Car Systems e Professional Audio e Voice Recognition e MP3 Encoder e ADSL Cable Test Equipment e Global Positioning e Telephony e High End Consumer Audio e Digital Broadcast Radio HO Processor ca ANALOG DEVICES ADSP 21065L Low Cost Entry Point to the SHARC DSP Family Features e 16K 32 bit dual ported on chip memory 544 KBits configurable e 64M x 32 bit word external address space e 198 MFLOPS 32 bit floating point e 198 MOPS 32 bit fixed point e Glueless SDRAM interface e 2 serial transmit receive ports support 32 channel TDM e
46. ce e On chip Boot ROM e 8 Dedicated General Purpose I O Pins e 14 DMA Channels e Supported by ADI s VisualDSP Integrated Development Environment e Supported by an Optimizing C Compiler e 2 5 volt supply with 3 3 volt I O e 144 Lead LQFP Applications e Voice Fax Over IP e Voice Over ATM e Voice Mail Systems e PBX Extenders e Echo Cancellation e Integrated Access Devices IAD e SOHO Telephony e Data Acquisition e Multi mode Modems Benefits e Dual core device provides more flexibility and higher sustained performance e Large on chip memory reduces off chip mem ory access bottlenecks and overall system cost e Unified memory space allows more efficient use of memory e Efficient C Compiler for ease of programming Price Model MHZ Pin Pkg 100 499 ADSP219212MKST160x 320 144 LQFP 60 00 Commercial Temp 0 C to 70 C M Indicates 2 5 Volt Operation Budgetary pricing subject to change ADDS 219X WKSHP DSP Workshop ADDS 219X EZ ICE In circuit Emulator ADDS 2192 12EZLITE Evaluation Kit VDSP 21 XX PC FULL Complete SW Pkg ADSP 2192 Assembly Benchmarks Average Cycle Time Algorithm Description us 1024 Point Complex 1024 point Decimation in Time FFT on a complex normally 151 Complex FFT ordered input The original complex input is destroyed in the process Radix 2 with The complex result is stored in an output buffer in normal order The twid reversal dle factors are contained in se
47. consulting services as well as a wide range of commercial off the shelf COTS products Their development tools are specifi cally designed to work with Analog Devices DSP based systems dee Tap Into the Experience and Global Reach of the DSP Collaborative Working together to extend your design team With the DSP Collaborative you are supported by highly reputable brands patented technolo gies and the pioneers in real time system design and debug The DSP Collaborative part ners offer products and services that provide both system and application level expertise Speed up your design process by leveraging the solutions our partners have to offer Debuggers Real Time Operating Systems Development and Evaluation Boards MATLAB DSP Support Algorithms and Libraries Emulators DSP Systems COTS Hardware Boards Design with Analog Devices DSP Collaborative team approach with a proven strategy for maximizing your resources be te Se party ANALOG DEVICES DSP Competitor Cross Reference Guide Operating Device ADI Suggested Functional Number RAM Voltage Smallest Part Number Replacement Device of Cores Kwords Core 1 0 Package Analog Devices 218x Family ADSP 2181 1 40 32 5V 128TQFP ADSP 2183 1 52 32 3 3V 128TQFP ADSP 2184 1 40 8 5V 100TQFP ADSP 2185 1 33 32 5V 100TQFP ADSP 2186 1 40 16 5V 144BGA ADSP 2184L 1 40 8 3 3V 144BGA ADSP 2185L 1 52 32 3 3V 144BGA ADSP 2186L 1 40 16 3 3V 144BGA AD
48. enar wh S s wh g g and or other peripherals 3 a a z O oO Bele a SHARC D ee ES SHARC C crea a TDO ID2 0 4 LINK 5 gt LINK 5 ID2 0 3 TDI e TDO Bova Boescg Ee EEE DSP Selection Guide AD14060 Functional Block Diagram http www analog com milsystems ANALOG DEVICES Quad SHARCs AD14060 AD14160 Development Tools The AD14060 AD14160 is supported with a complete set of software and hardware develop ment tools including an EZ LAB in circuit emulator and development software Features e ADSP 21060 core processor x4 e 480 MFLOPS Peak 320 MFLOPS sustained e 25 ns instruction rate single cycle instruction execution each of 4 processors e 16 Mbit shared SRAM internal to SHARC s e 4 gigawords addressable off module memory e 48 bit shared memory bus 48 bit data bus e Full 32 bit address bus e Interrupts flag pins and timers are also avail able as I O e 32 Bit single precision and 40 Bit extended precision IEEE floating point data formats or 32 Bit fixed point data format e User configurable boot modes bus priority and other features with control lines e IEEE JTAG standard 1149 1 test access port and on chip emulation ANALOG DEVICES http www analog com milsystems AD14060 Twelve 40 Mbyte s link ports 3per SHARC accessible to from the outside world Four link ports connected internally in a ring configuration Four 4
49. ess connection for scaleable DSP multiprocessing architectures e Distributed on chip bus arbitration for parallel bus connect of up to six ADSP 21160s plus host e Six 100 Mbytes sec link ports for point to point connectivity and array multi processing e 2 5 volt core 3 3 volt I O 80 MHz 21160M e 1 9 volt core 3 3 volt I O 90 MHz 21160N DSP Selection Guide Applications e Cellular Base Stations e Call Processing e Speech Recognition e Instrumentation e 3D Graphics Acceleration for Workstations and Arcade Video Games e Imaging e High End Audio e Radar and Sonar Model MHZ Pin Pkg ADSP 21160MKB 80 80 ADSP 21160NKB 90 90 M indicates 2 5V operation N indicates 1 9V operation K Commercial Temp 0 C to 85 C ADDS 2116X WKSHP DSP Workshop ADDS 21160M EZLITE Evaluation Kit VDSP SHARC PC FULL Complete Software Pkg ADDS MTN ICE ISA Based Emulator ADDS SUMMIT ICE PCI Based Emulator ADDS APEX ICE USB Based Emulator Ethernet Based Emulator Price 400 PBGA 179 00 400 PBGA 179 00 ADDS TREK ICE ia Core Processor Dual Ported SRAM Two Independent A Dual Ported Blocks Processor Port voPot Data Data Addr Data DAG1 DAG2 8x4x32 8x4x32 Connect t aa Ros 32 40 64 E llO Processor ANALOG DEVICES ADSP 21160 vs TMS320C6x Compar
50. fy code development e Auxiliary PWM outputs enable power factor correction for energy efficient motor systems e Fully code compatible with all ADSP 21xx and ADMCxx family products e Algebraic assembly language for easy pro Applications e Motor Types AC Induction Motors ACIM Permanent Magnet Synchronous Motors PMSM Brushless DC Motors BDCM Switched Reluctance Motors SRM e Consumer Applications washing machines HVAC refrigerator compressors e Industrial variable speed drives pumps electric vehicles Temp Instr Pin Price Model Range Rate PKG 100 499 ADMC331BST Industrial 26 MHz 80 Pin 14 95 40 C LQFP to 85 C Development Tools Price ADMC331 ADEVALKIT 395 00 ADMC331 evaluation board and motor control development tools assembler linker debugger Note The ADMC331 is recommended for future designs based on the obsoleted ADMC330 gramming ADSP 21xx Base Memory Architecture Program ROM Block 2K x 24 Data Address Generators Program Program RAM Data Memo oo 2K aiai Program Memory Address Data Memory Address Program Memory Data Data Memory Data Serial Ports SPORT 1 H ANALOG 38 DSP Selection Guide http www analog com motorcontrol DEVICES High Performance ADMC300 DSP Based Motor Controller Features e High Resolution 16 bit sigma delta analog input system 76 dB SNR Five independent ADC channels
51. ges of any project VisualDSP integrates all of the code generation tools below e PROM Splitter e Math DSP and C Runtime Library e Integrated Develop ment Environment e Assembler e Linker e Simulator e C Compiler e Librarian EZ KIT Lite Evaluation Kit The EZ KIT Lite provides an easy way to evaluate the power of ADI s DSPs and begin to develop applications These systems consist of a stand alone evaluation board and fundamental debug ging software to facilitate architecture evalua tions via a PC hosted tool set With the EZ Kit Lite users can e Evaluate ADI s DSPs e Learn about DSP applications e Simulate amp debug applications e Prototype applications ANALOG DEVICES ADSP 21000 SHARC Family Emulators Emulators provide non intrusive target based debugging of DSP systems Com pact and easy to use these in circuit emulators perform a wide range of emulation functions including single step and full speed execution with pre defined breakpoints viewing and or altering of register and memory contents DSP emulators are available for PC AT PCI and USB host platforms Remote emulation and debug is made possible over a local area net work with Ethernet based products Model Supported DSP ADDS 21061 EZLITE ADDS 21160M EZLITE ADDS 21161N EZLITE ADDS 21065L EZLITE VDSP SHARC PC FULL VDSP SHARC PC CAL VDSP SHARC PC AL VDSP SHARC PC DIS VDSP SHARC PCFLOAT VDSP SHARC PC TEST ADDS APE
52. gn is digital feedthrough from high speed processors to high resolution analog circuitry This is fully addressed in our dspConverters with careful circuit layout and synchronization of clocks Test results have verified that clock noise is absent from the digitized analog spec trum even when the DSP is running at full speed Converter Performance and Group Delay The converters are fully specified with SNR THD figures of 78 dB for the encoders and 77 dB for the decoders A notable feature of the performance specification is it s clarity Group delay can be critical in noise cancella tion applications It s important to cancel the noise as close to the source as possible Delays increase modeling errors require larger filters and inhibit random noise cancellation systems All analog front ends in the family offer group delays which are 25 us for the encoder and 50 us for the decoder dspConverter Selection Table AFE Program Data Generic abl DSP ees sees Price AD73411 40 AD7341 1 80 AD73422 40 AD73422 80 AD73460 80 52 MIPS 52 MIPS z 52 MIPS 2 52 MIPS 6 Ch ADC 52 MIPS 17 64 IK TK 21 17 8K 8K 20 41 16K 16K 23 47 16K 16K 23 47 US Dollars Lowest grade suggested resale price per unit in 100 unit quantities 42 DSP Selection Guide ANALOG http www analog com dspconverter DEVICES AD73411 Low Power Analog Front End with DSP Features AFE PERFORMANCE e 16 Bit A D converter e 16 Bit D
53. grammable high speed DSP based on ADSP 218x Family Applications e General Purpose Analog I O e Speech Processing e Cordless and Personal Communications e Telephony e Wireless Local Loop e Active Control of Sound and Vibration e Data Communications Prog AFE Data Model CHNS Memory Pin PKG AD73422 40 2 8 8K 119 PBGA AD73422 80 2 16 16K 119 PBGA Control Full Memory Modei Memory Programmable External Program Data Yo and Addr Bus 4 Memory Memory Flags External Program Sequencer A Program Memory Address Data Bus Data Memory Address Byte DMA Controller 1 Program Memory Data Y LW E Data Memory Data 44 DSP Selection Guide A Arithmetic Units Serial Ports Timer ADSP 218X DSP Serial Ports Analog Front End Section DEVICES http www analog com dspconverter ANALOG Software and Systems Technologies SST Marketplace pressures of the newest technolo gies faster time to market and ever lower sys tems costs drive leading OEMs to look for the newest fastest ways to introduce their products to their customers To meet this need Analog Devices Inc offers numerous chipset and algorithm solutions with reference designs and third party support in emerging and high growth market segments such as e Audio Solutions e Video Communications Solutions e Energy Meter Solutions e Com
54. he DSP core only supports one circular buffer and must save and restore address registers to implement mul tiple buffers ADIs DSPs have hardware support for mul tiple circular buffers eliminating processor overhead for address calculations Data Registers The number of general purpose data registers available can impact the code performance Fewer registers require intermediate results to be stored in memory decreasing performance and increasing the load on the memory bus ADI DSPs feature a secondary register set which allows for quick context saves when interrupts occur rather than delaying responses to the interrupt while all register values are saved to memory DSP Selection Guide http www analog com dsp DMA Channels Non Intrusive DMA The DMA Direct Memory Access channels transfer data between an external source and the DSP s on chip memory With DMA chan nels data transfers occur without the core processor having to execute data movement instructions For example the overhead clock cycles used to move data for an FFT can add a significant amount of time to overall algorithm execution With multiple DMA channels avail able all data transfers happen without core involvement eliminating any overhead clock cycles One of the strengths of Analog Devices DSP architecture is that these DMAs do not inter fere with the core operation This capability is referred to as non intrusive or zero overhead DMA
55. hitecture including multiprocessing shared memory and memory overlays Code generation tools include the C C compiler C C runtime library DSP and math libraries DSP Selection Guide I ee VisualDSP s plot window assembler linker loader and splitter Code generation tools work seamlessly within the VisualDSP environment C C Compiler and Assembler The C C compiler generates efficient code that is optimized for both code density and execution time The C C compiler can be easily interfaced with assembly code modules Thus users can program in C C and still use assembly for time critical loops The math DSP and C C runtime library routines help shorten time to market The SHARC DSP ADSP 218x ADSP 218x does not have C and ADSP 219x DSP family assembly language is based on an algebraic syntax that is easy to learn program and debug The add instruction for example is written in the same manner as the actual equation the algebraic statement r x y is coded in assembly language as f0 f1 f2 SHARC DSPs example Linker amp Loader The linker provides flexible system definition through linker description files ldf In a single ldf file users are able to define different types of executables for a single or multiprocessor system The linker resolves symbols over multiple executables maximizes memory use and allows common code to be ANALOG DEVICES VisualDSP shared amo
56. ison VEEE C TEE 21160 SHARC IEEE 32 bit floating point support Native 32 bit fixed point support a si Dual ported internal memory No No Yes Built in multiprocessing support No No Cluster and link Number of DMA channels 4 4 14 Zero overhead DMA support No No Yes Number of registers 32 32 128 Accumulator size 40 bits 40 bits 80 bits 64 bit product support No Yes Yes Memory bandwidth 64 bits cycle 128 bits cycle 128 bits cycle Software loop support No interrupts for No interrupts for Interrupts allowed compact loops compact loops in compact loops Assembly complexity Highly complex Highly complex Algerbraic assembly language Number of circular buffers supported 8 8 32 Conditional execution support Requires extra Requires extra Dedicated conditional register register logic FIR filter code size 100 instructions 100 instructions 25 instructions Package size 35mm 352 ball 35mm 352 ball 27mm 400 ball 1 The TMS320C6x does DMA by stealing cycles from the core 2 Memory bandwidth refers to the data path widths between the register file and memory 3 Hand optimized TMS320C6x assembly language must be written in a highly complex non single assignment form 4 The TMS320C6x only allows two different lengths of circular buffers and the lengths must be power of two 5 TMS32062xx Programmer s Guide page 4 112 DEVICES DSP Selection Guide 31 32 DSP Selection Guide ADSP 21161N Low Cost Single Instruction
57. ithm code are critical of DSP DSPs must have the ability to Of course designers are also concerned with low 1 Perform fast arithmetic production cost low power consumption system 2 Fetch data at a fast rate integration and other criteria such as clock fre 3 Sequence efficiently through repetitive quency size of on chip memory and high level operations Key Feature Benefit Single Cycle Instruction e One cycle per instruction execution Execution e ADSP 218x requires no extra latency cycles for decision branches condition code checking or subroutine calls e Delayed branches increase efficiency on pipelined architectures such as SHARC and ADSP 219x e Deterministic operations make it easy to develop profile and benchmark code Code Compatible Family All ADSP 2100 Family members share the same base architecture and Members assembly language All ADSP 21000 SHARC Family members share the same base architec ture and assembly language e No need to learn or invest in new development tools when moving from one family member to another e Software investment is preserved Simple Programming e Algebraic syntax assembly language makes code easy to use easy to Language learn and easy to read e Unlike competitors who use mnemonics like SPAC and XORX ADI assembly language syntax makes programming in highly efficient assem bly language easy Balanced Core Memory e Fast core processing large on chip memories and high bandwidth I O
58. lephone 800 ANALOGD North America Email dsptools support analog com Europe Email dsp europe analog com Web http www analog com dsp tools Worldwide Headquarters P O Box 9106 Norwood MA 02062 9106 U S A Telephone 1 781 329 4700 1 800 262 5643 USA only Fax 1 781 326 8703 Europe Headquarters Am Westpark 1 3 81373 Munchen Germany Telephone 879 76903 0 Fax 879 76903 157 Japan Headquarters New Pier Takeshiba South Tower Building 1 16 1 Kaigan Minato Ku Tokyo 105 6891 Japan Telephone 3 5402 8200 Fax 3 5402 1063 Southeast Asia Headquarters 4501 Nat West Tower Times Square Causeway Bay Hong Kong Telephone 2 506 9336 Fax 2 506 4755 52 DSP Selection Guide Batters Remember Analog Devices Offers Products and Solutions for the Entire Signal Chain O Y N N gp Ss oo pC Si uy XP pv we or tes a r d multiplexer PWer Managemen t and much much more 23 00 35 19 30 35 18 30 35 2 30 35 1 30 35 09 30 35 02 30 35 0130 35 DSP SUPPORT Email In the U S A dsp support analog com In Europe dsp europe analog com Fax Inthe U S A 1 781 461 3010 In Europe 49 89 76903 557 World Wide Web Site ei http www analog com dsp t WORLD HEADQUARTERS One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 1781 329 4700 1 800 262 5643 U S A only Fax 1781 326 8703 World Wide Web Site http www analog co
59. letin for VisualDSP and the ADSP 21xxx Family DSPs ME SE a SSE Anai ge DSP Selection Guide 51 DSP Customer Support Web You can visit Analog Devices World Wide Web home page Browse through a wide assortment of information about the company and products You can also get detailed techni cal information as well as cross reference infor mation A search engine and site map will help you find what you are looking for You can reach Analog Devices over the internet at www analog com dsp Here you ll find e Applications and Solutions e Development Tools e Data Sheets amp Manuals e DSP Collaborative e Technical Support e University Program e Training and Education Faxback System You can get 24 hour access to data sheets for Analog Devices products by using the Analog Devices FAXback automated literature delivery system Simply call 1 800 446 6212 and follow the recorded instructions By providing a FAX code and your FAX number you can receive a copy of a data sheet in a matter of minutes An index of products and FAX codes can be faxed to you upon demand DSP Customer Support Literature North America Telephone 800 ANALOGD Faxback 800 446 6212 Europe Telephone 49 89 76903 312 Faxback 49 87 6593 00 Technical Assistance North America Email dsp support analog com Fax 781 461 3010 Europe Telephone 49 89 76903 333 Email dsp europe analog com Fax 49 89 76903 307 DSP Tools Support Te
60. m EUROPE HEADQUARTERS Am Westpark 1 3 D 81373 Munchen Germany Tel 49 89 76903 0 Fax 49 89 76903 157 JAPAN HEADQUARTERS New Pier Takeshiba South Tower Building 1 16 1 K aigan Minato ku Tokyo 105 Japan Tel 81 3 5402 8210 Fax 81 3 5402 1063 SOUTHEAST ASIA HEADQUARTERS 4501 Nat West Tower Times Square One Matheson Street Causeway Bay Hong Kong Tel 85 2 2506 9336 Fax 85 2 2506 4755 G02458 25 3 01 G 23 00 3
61. mini BGA epee Meadors e Multi channel Voice Processing e Satellite Telephone e Industrial Measurement amp Control e Data Encryption Pee A a ain ADDS 218x WKSHP DSP Workshop ADDS 218x ICE 1 8V In circuit Emulator VOIP Phone ADDS 2189M EZ LITE Evaluation Kit e Global Positioning VDSP 21xx PC FULL Complete Software Pkg e Internet Gateway Model PM DM MHz Temperature Pin Pkg Price 100 499 ADSP 2184NBST 320 4K 4K 80 40 C to 85 C 128 LQFP 7 00 ADSP 2184NBCA 320 4K 4K 80 40 C to 85 C 144 MBGA 9 00 ADSP 2186NBST 320 8K 8K 80 40 C to 85 C 128 LQFP 8 50 ADSP 2186NBCA 320 8K 8K 80 40 C to 85 C 144 MBGA 10 50 ADSP 2185NBST 320 16K 16K 80 40 C to 85 C 128 LQFP 11 25 ADSP 2185NBCA 320 16K 16K 80 40 C to 85 C 144 MBGA 13 50 ADSP 2187NBST 320 32K 32K 80 40 C to 85 C 128 LQFP 20 00 ADSP 2187NBCA 320 32K 32K 80 40 C to 85 C 144 MBGA 22 00 ADSP 2189NBST 320 32K 48K 80 40 C to 85 C 128 LQFP 25 00 ADSP 2189NBCA 320 32K 48K 80 40 C to 85 C 144 MBGA 27 00 ADSP 2188NBST 320 48K 56K 80 40 C to 85 C 128 LQFP 30 00 ADSP 2188NBCA 320 48K 56K 80 40 C to 85 C 144 MBGA 32 00 N indicates 1 8V core supply Budgetary pricing subject to change 24 DSP Selection Guide DEVICES ADSP 218x M Series The Compatible DSP Family The ADSP 218x M Series expands the code compatible pin compatible portfolio offers the highest performance and memory integration at 2 5V and is code comp
62. mpiler Throughout the workshop attendees learn how easy it is to use Analog Devices DSPs from lecture sessions and hands on exercises Locations and Schedules The workshops are offered monthly in North America Workshop schedules and more details on DSP workshops are also available on the web site DSP Selection Guide http www analog com dsp training How to Register To enroll customers should register online at the Analog Devices web site at http www analog com dsp training You will be notified when your seat is confirmed ADSP 218x Workshop This is a 3 day workshop which covers the ADSP 218x family of DSPs and development tools For registration and price contact Momentum Data Systems via e mail at sales mds com or by phone at 714 378 5805 Part Number ADDS 218x WKSP Price Contact Momentum This is a 3 5 day workshop which covers all the ADSP 2106x DSPs including the ADSP 21065L and development tools For registration and price contact Melinda Rosauro at BBD Electronics at MRosauro bbd ca or 905 821 7800 X110 Part Number ADDS 2106x WKSP__ Price Contact BBD ADSP 2116x Workshop This is a 3 5 day workshop which covers ADSP 21160 and development tools Part Number ADDS 2116x WKSP Price 1375 00 ADSP 219x Workshop This is a 3 5 day workshop which covers the ADSP 219x family of DSPs and development tools Part Number ADDS 219x WKSP ERS Price 1375 00 ANALOG DEVICES ADI Sup
63. munications amp Telephony Solutions e Global Positioning Solutions e Embedded Modems e Standalone Embedded Modems e Internet Modems e Wireless Local Loop ADSST MPEG EVALO1 Single Chip MP3 Encoder Decoder Features e Decodes MPEG1 Audio Layer 3 MP3 e Encodes MPEGI Audio Layer 3 MP3 e Fully complies with the ISO IEC 11172 3 audio standard e Supports half sampling frequencies of 16 22 05 and 24 kHz and full sampling frequen cies of 32 44 1 and 48 kHz per channel e Supports 8 kbps to 160 kbps bit rates for half sampling frequencies 32 kbps to 320 kbps for full sampling frequencies e Compact single chip chipset or 85 mm x 60 mm x 30 mm board ANALOG DEVICES http www analog com solutions Benefits e Operates in real time and processes all combi nations of the algorithms e Directly encodes MP3 onto the device flash memory e Requires no external SRAM or SDRAM e Includes bass boost and equalizer Applications e Digital Audio e Portable Handheld and Automotive Audio e CD Ripping e Home Theatre e Internet Audio e Internet Distribution of Original Music e Previewing Favorite Artists Model MHz Pin Pkg ADSST MPEG EVALO1 75 Reference Design DSP Selection Guide 45 ADSST DAP EVAL01 Single Chip MP3 Encoder Decoder S e Decodes MPEG1 Audio Layer 3 e Digital Audio e Encodes MPEGI Audio Layer 3 e Portable Handheld and Automotive Audio e Fully complies with the ISO IEC 11172
64. ng multiple processors The loader programming interfaces API s The DSP supports creation of host link port and PROM Collaborative is a comprehensive collection of boot images Along with the linker the loader DSP development support companies The DSP allows multiprocessor system configuration Collaborative product offerings real time with smaller code and faster boot time operating systems emulators high level The DSP Collaborative nea compilers and multiprocessor ardware can interface seamlessly with The VisualDSP environment enables VisualDSP thereby simplifying development independent third party companies to add value across all platforms and targets using ADI s published set of application VisualDSP Bundles Emulation and Simulation Bundle Suffix IDE aeee et ae i Support Complete Package X Code Gen Package he Assembler Package AL X 7 IDE Debugger Package DIS X X X Floating License FLOAT X X X X x x auian DSP Selection Guide 11 12 DSP Selection Guide Development Tools ADSP 2100 Family Development tools from Analog Devices are one of the industry s most complete lines from the economical EZ KIT Lite evaluation kits to multiprocessor debuggers These tools are easy to learn and easy to use and allow designers to bring DSP based products to market quickly and efficiently VisualDSP Integrated Development Environment VisualDSP is a comprehensive toolset for ADSP 218x and ADSP
65. nsumer electronics JTAG sup port is also included to provide a more robust software emulation and test capability Processor Core Based on the industry proven ADSP 21xx architecture the ADSP 219x core architecture consists of three computational units data reg isters program sequencer and two data address generators Computational capabilities include an Arithmetic Logic Unit ALU a Multiply Accumulator MAC with 40 bit precision and a general purpose 32 bit wide barrel shifter Any data register in the 32 register register file can be used as an input to any computational unit This mathematical capability is fed by two powerful data address generators that can oper ate simultaneously enabling dual data operands in a single cycle Data can be accessed any where in a 16 Mword space through the address generators 16 bit base register set and 8 bit page registers A flexible set of addressing modes allows for efficient data transfers and stack manipulation Instruction flow is handled through an efficient Program Sequencer that ensures single cycle operation for all mathematical operations A selective instruction provides high speed opera tion and power efficiency without sacrificing intuitive operation and easy programmability 218x to 219x 15 Years of Code Compatible Architectures ADSP 218x 80 MIPS MIPS Highest Performance 4X Higher Performance 1200 MIPS ADSP 2192 320 MIPS ADSP 2191
66. og com dsp ADSP 2189M EZ KIT Lite Evaluation System Manual www analog com dsp ADSP 218x Family EZ ICE Hardware Installation Guide www analog com dsp Release Notes for ADSP 21xx Family of DSPs www analog com dsp VisualDSP amp ADSP 21xx DSP Tools Release 7 0 Publication Number SE_Guide_to DSP DSP Solutions 2001 82 000780 03 VDSP DUG 82 000806 02 82 000390 087 ADSP 21XX DSW ML ADSP 21XX EZ MAN 82 000779 01 82 000333 01 82 000332 01 83 000853 06 40 00 NC NC 25 00 NC NC 20 00 ADSP 21XX CTOOL ML 25 00 10 00 NC NC NC NC Complete Set of ADSP 21xx VDSP Manuals includes the following From Dist through SAP VDSP 21XX MAN FULL 100 00 VisualDSP User s Guide for the ADSP 21xx Family DSPs Assembler Manual for the ADSP 218x Family DSPs Assembler Manual for the ADSP 219x Family DSPs C Compiler amp Library Manual for the ADSP 218x Family DSPs C Compiler amp Library Manual for the ADSP 219x Family DSPs Linker amp Utilities Manual for the ADSP 21xx Family DSPs ADSP 2100 Family Data Sheets ADSP 21xx Family REV B Lit Center ADSP 2104 ADSP 2109 REV 0 Lit Center ADSP 2171 2172 2173 REV A Lit Center ADSP 216x REV 0 Lit Center ADSP 2181 REV D Lit Center ADSP 2183 REV C Lit Center ADSP 2184 REV 0 Lit Center ADSP 2184L REV 0 Lit Center ADSP 2185 REV 0 Lit Center ADSP 2185L REV A Lit Center ADSP 2185M REV 0 Lit Center ADSP 2186 REV A Lit Center ADSP 2186L REV A
67. oject Management The IDE provides flexible project management for the development of DSP applications The IDE includes access to all the activities necessary to create and debug DSP projects The IDE editor allows the creation or modification of source files or viewing of listing or map files This powerful editor is part DSP Selection Guide auarog VisualDSP of the IDE and includes multiple language syntax highlighting OLE drag and drop bookmarks and standard editing operations such as undo redo find replace copy paste cut and go to The IDE allows access to the DSP C C compiler C C runtime library assembler linker loader and splitter Specification of options for these tools is made possible through the property page dialogs Property page dialogs are easy to use and simplify configuring changing and managing projects These options may be defined once and then modified to meet changing development needs The DSP code generation tools can be accessed from the operating system command line Greatly Reduced Debugging Time The VisualDSP debugger has an easy to use common interface to all DSP simulators and emulators available through Analog Devices Inc ADJ and many from participating parties VisualDSP Development Environment Emulator Hardware EZ KIT Lite Hardware Software Simulator Third Party Hardware ADSP 2106x ADSP 2116x ADSP 218x ADSP 219x VisualDSP simplifies
68. or sustained high speed compu 3D Graphics e Audio Equipment tations just as it should be for real time embed Arcade Games e Call Processing ded DSP development e Imaging e Speech Recognition e Video Conferencing Cellular Basestations Code compatibility helps to keep development e Medical Imaging e Instrumentation time at a minimum and maximize our cus tomers software investments SHARC Roadmap Commitment to Code Compatibility into Tomorrow The original Single Instruction Single Data 40 MrLoPs A SISD SHARC DSPs feature a broad range of integrated Ke E gt memory sizes and price points For very high oe D 10 GFLOPs performance applications ADI has extended K 64 Mbits Speer the architecture to a code compatible Single yw Instruction Multiple Data SIMD platform Low Cost gt SS 120 198 MFLOPs gt SHARC era 0 5 4 Mbits lt L 1200 MFLOPs 5 SHARC The popularity of SHARC DSPs is evident in Gr Coen a Rae r ADSP 21061 ADSP 21065 our leadership in multiprocessing applications Patented link port technology has helped estab 32 BIT On Chip Serial Generic Package Max MIPS Vcc SRAM Ports Price B 600 MFLOPs Price performance Low Cost ADSP 21160N 90 1 9 3 3V 4 Mbits 2 179 00 ADSP 21160M B 80 2 5 3 3V 4 Mbits 2 179 00 ADSP 21161N B 100 1 8 3 3V 1 Mbit 2 39 00 ADSP 21065L S CA 66 3 3V 544 Kbits 2 34 50 ADSP 21062 L B S 40 3 3 5V 2 Mbits 2 98 00
69. parate files that are in bit reversed order The core benchmark is given for 1024 samples FIR Filter Real direct form FIR filter It can be used for sample by sample filtering 0 003125 per tap The core benchmark is given per sample IIR Filter Each biquad section is implemented using Direct form II The core 0 0125 per biquad benchmark is given per sample Viterbi Based on 189 point block length 1 2 rate soft decision decoder 96 Decoder 1 Core clock frequency is 160 MHz resulting in an instruction cycle time of 6 25 ns 2 These benchmarks represent the execution time of two algorithms executing simultaneously when both DSP cores are used DSP Selection Guide Aa eal ater ADSP 21000 SHARC DSP Family Real Time Multiprocessing Leader The Analog Devices SHARC DSP family fea lish SHARC as a de facto standard Future gen tures a super Harvard architecture optimized erations of this high performance solution will to enable a variety of real time embedded continue to deliver the horsepower required for applications These 32 bit DSPs allow users to the most demanding multiprocessing applica program with equal efficiency in both fixed tions those that require clusters of versatile point and floating point arithmetic The unique memory architecture two large on chip dual ported SRAM blocks coupled with the sophisti SL cated I O processor gives the SHARC DSPs e Prosumer Audio e Radar and Sonar Guidance the bandwidth f
70. ponse e 160 Kbits to 2 Mbits of on chip SRAM e DSP balanced for data processing and data VO Multifunction instructions allow simultan eous operations of Computational units 2 data address generators Powerful program sequencer Byte DMA transfers up to 4Mbytes of stored code or data 2 Serial ports including multi channel ser ial port for direct interfacing to T1 E1 lines 16 Bit wide internal DMA port e As low as 3 mA MIP at 80 MHz e 28 to 80 MHz e 5V 3 3V 2 5V 1 8V Supply Voltages Benefits e Greater flexibility in system design because of performance and memory options in the same package type e Large amounts of on chip SRAM eliminate the need for external memory thus simplify ing algorithm development and reducing chip count board space and power consumption e Several types of peripheral DMA support allow for modular system designs with a min imum of external circuitry e Multi function instructions and zero overhead nested looping capabilities combine to pro duce efficient algorithm execution Applications e Consumer Telephony e Cellular Accessories e Embedded Speech Processing e POS Terminals e Smartcard Readers e PBX e Portable Text Scanners e Audio Equipment e Multi channel Voice e Data Encryption e ISDN Modems e Global Positioning e Navigation 150 Code Compatible and Pin Compatible 218X p L Series 33 52 MIPS Up to 1 2MBit SRAM 0 8 mA MIP 3 3V 50
71. port for Universities The ADI DSP University Program provides the next generation of engineers with DSP knowledge to help them compete in the industry of tomorrow The ADI DSP University Program offers e Complete DSP Software and Hardware Tools to set up a DSP LAB e Teaching material to help design experiments e Priority technical support to professors Analog Devices DSP Technology is easy to teach e DSP architectures that are the simplest to program in the industry e Simple instruction sets e High levels of SRAM integration Hundreds of universities in 37 countries use ADI DSPs for teaching and research To request a University donation or learn more go to alieke http www analog com industry dsp university html DSP Selection Guide 49 50 DSP Literature Selection Guide Where to Order or Download ADSP 2100 Family Publications Scientist and Engineer s Guide to DSP From Dist through SAP DSP Designer s Reference Lit Center ADSP 2100 Family User s Manual Lit Center ADSP 2100 Family 16 Bit Tools Publications VisualDSP Debugger Guide amp Reference From Dist through SAP Debugger Tutorial for the ADSP 21 xx www analog com dsp ADSP 219x DSP Instruction Set Reference Lit Center ADSP 2100 Family Assembler Simulator Manual From Dist through SAP ADSP 2100 Family C Tools User Guide From Dist through SAP ADSP 2100 Family C Runtime Library Reference From Dist through SAP ADSP 2181 EZ KIT Lite Reference www anal
72. processor with algebraic assembly syntax First to market with sub 10 DSP ADSP 2105 First to integrate 32Kw SRAM on a DSP World s smallest DSP ADSP 2183 Highest memory density in industry ADSP 2188M 1984 1986 1988 1990 1992 1994 1996 1998 2000 300 MIPS ADSP 219x 200 MIPS Family Over 300 MIPS 100 MIPS ADSP 218x Family Pin for Pin Compatible 33 80 MIPS Up to 2Mbits SRAM On Chip ADSP 2101 217x Family 20 33 MIPS The SHARC family of fixed and floating point 32 bit processors has successfully defined a new standard in overall DSP integration By placing an emphasis on balance between computational core performance memory bandwidth and I O throughput SHARC DSP performance is predictably high and sustained First DSP to integrate 30 million transistors ADSP 21060 First 32 bit DSP to 120 MFLOPS First 32 bit DSP to 1 GigaFLOPS First DSP to 2 Billion MACS 1994 1995 1996 1997 1998 1999 2000 2001 2002 2700 MFLOPS 2100 MFLOPS TigerSHARC 5 Billion Operations per Second 8 Bit 16 Bit 32 Bit DSP 1500 MFLOPS STATIC SUPERSCALAR SHARC 900 MFLOPS 1200 2400 MFLOPS 300 MFLOPS SIMD SHARC 1200 MFLOPS SISD SHARC Up to 198 MFLOPS and as Low as 10 per Unit Next Generation 5 SHARC gt ANALOG X DEVICES Multiprocessing Leader DSP Markets and Applications As the processing capabilities of DSPs have increased they are being used in more and more applications The
73. rma tion Automatically applies appropriate or selected decoder e Supports sampling frequencies of 16 22 1 24 32 44 1 48 88 2 96 KHz e Supports 32 kbps to 4 096 kbps bit rates e 32 bit floating point programmable imple mentation facilitates software upgrades Benefits e Decodes latest 6 1 channel algorithms from DTS Dolby e Supports multiple audio formats Applications e Digital Audio e Portable Handheld and Automotive Audio e Set Top Boxes e Home Theatre e Internet Audio e Audio DVDs e DVD CD MLP Players Model MHz Pin Pkg ADSST 21065LKST 264 66 PQFP ADSST 21061L 44 PQFP ADSST PEGASUS SDK 66 Reference Design Aa ae a SE SPDIF Out P CH4 L R CS8404A DAC AD1854 R DAC A O L DAC EOZ L ADSST 21065L PEEN EPROM 1IMx8 SDRAM 1MB UART 8 Bit Parallel Key Pad Serial I F lt gt A Micro 80C31 LCD Dispaly Aout PEGASUS II Audio Reference ANALOG DEVICES http www analog com solutions DSP Selection Guide 47 DSP Technical Training Workshops Description The DSP System Development and Programming workshops are comprehensive hands on workshops The workshops are geared towards people who have a working knowledge of microprocessors and want to learn how to use Analog Devices DSPs These courses cover the DSP architecture assembly language syntax IO interface hardware and software development tools and C co
74. rupt Capture bcs 1K x 16 Controller Timers A A Program Memory Address Data Memory Address y A Program Memory Data y Data Memory Data Serial Ports SPORT 0 SPORT 1 Arithmetic Units ANALOG DEVICES http www X Interval Timer analog com motorcontrol DSP Selection Guide 39 Quad SHARCs AD14060 AD14160 480 MFLOP Single Package Multiprocessor The AD14060 Quad SHARC is a first genera tion CQFP DSP multiprocessor Using high density packaging techniques the module fits four SHARCs in approximately 30 of the space required using discrete packages The AD14160 Quad SHARC Ceramic Ball Grid Array CBGA puts the power of the first generation AD14060 CQFP DSP multiproces sor into a very high density ball grid array package the module fits four SHARCs in approximately 30 of the space required using discrete packages now with additional link and serial I O pinned out beyond that from the CQFP package The core of the multiprocessors is the ADSP 21060 DSP Microcomputer The AD14X60 modules have the highest performance density and lowest cost performance ratios of any mul tiprocessors in their class They are Applications Multi SHARC designs with tight area volume constraints such as large array and image processors smart missiles avionics and others will benefit The AD14060 AD14160 are avail able as both industrial and MIL SMD grade parts in 5V AD
75. standard package options simplify sys tem design e 3 Sector on chip Flash memory allows for in circuit programming for software upgrade ability and rapid code development e Integrated Power On Reset and precision voltage reference reduce system costs e Pin for pin compatible ROM device provide low cost high volume option e Fully Code Compatible with all ADSP 21xx and ADMCxx family products e Algebraic assembly language for easy pro gramming e Industrial and Automotive temperature grades Memory Block Prog Flash 4K x 24 ADMCF32x ADSP 21xx Base Architecture Program Sequencer Program Memory Address Program ROM 2K x 24 Data Address Generators Program RAM 512 x 24 512 x 16 Data Memory Applications e Motor types AC Induction Motors ACIM Permanent Magnet Synchronous Motors PMSM Brushless DC Motors BDCM Switched Reluctance Motors SRM e Industrial variable speed and servo drives e Uninterruptable power supplies e Electric vehicles e Smart sensors data acquisition systems Motor Control Peripherals Inputs and Trip 328 Only Data Memory Address Program Memory Data Data Memory Data Arithmetic Units 36 DSP Selection Guide http www analog com motorcontrol ANALOG DEVICES ADMC401 Single Chip High Performance DSP Based Motor Controller Features e High resolution in
76. t to from any DREG e Indirect with M register offset to from any register e Modify address register immediate 2 s com plement modifier The development tools are VisualDSP com patible supporting a unified ADSP 2100 and SHARC DSP development environment Designers work with the same tool chain across all Analog Devices DSPs DSP Processor Core PM Address DM Address PM Data DM Data Data Registers l E l asr l er Sequencer Sequencer sequencer l Ea Ea Ea A Industry Standard System and DMA Interface e Compiler efficient data register design e Program sequencer for fast code execution e Fully transparent instruction cache for dual operand fetches ADSP 219x Core Block Diagram ANALOG DEVICES http www analog com dsp DSP Selection Guide 27 28 ADSP 2192 First ADSP 219x Family Member The ADSP 2192 is a dual core 16 bit fixed point DSP code compatible with the popular ADSP 218x family and the first member of the ADSP 219x DSP Family available now The ADSP 2192 combines two ADSP 219x cores with industry standard PCI USB and AC 97 glueless system interfaces This reduces overall system cost and OEM development time Features e 160 MHz 320 MIPs High performance Dual Core 16 bit Device e 2 4 Mbits On chip SRAM e PCI 2 2 33MHz 32 bit Compliant e Integrated USB 1 1 Compliant Interface e AC 97 Rev 2 1 Compliant Interfa
77. tegrated 12 bit multi chan nel ADC gt 70 dB SNR 8 channel simultaneous sampling 8 chan nels converted in lt 2u sec Integrated precision voltage reference e Three phase 16 bit PWM generation unit e Two 8 bit auxiliary PWM outputs e 26 MIPS fixed point DSP core 2K x 24 bit program memory RAM 2K x 24 bit program memory ROM 1K x 16 bit data memory RAM 14 bit adress bus and 24 bit data bus for external memory expansion e Incremental encoder interface e Programmable digital I O e Integrated power on reset Benefits e High performance DSP integrated with fast 12 bit ADC provides for true single chip solution e Fully code compatible with all ADSP 21xx and ADMCxx family products e Algebraic assembly language for easy pro gramming e External address and data bus allows exter nal memory to be added as needed e Flexible encoder interface unit for position feedback e Integrated power on reset function and voltage reference ADSP 21xx Base Architecture Program Sequencer Data Address Generators Program ROM 2K x 24 Program RAM Data RAM 2K x 24 1K x 16 4 A Applications e Motor types AC Induction Motors ACIM Permanent Magnet Synchronous Motors PMSM Brushless DC Motors BDCM Switched Reluctance Motors SRM e Industrial variable speed and servo drives e Uninterruptable power supplies e Numerical control machines e Robotics Temp Instr Pin Price Model Range
78. ws e Simulate standard I O interrupts and streams simulator only e Statistical profiling e MP multiprocessing e Graphical plotting Code Generation Key Features e Program with an easy to use algebraic syntax assembly language e Develop applications using an optimizing C C compiler e Intersperse inline assembly statements within C C source code e Create executables using a linker that sup ports multiprocessing shared memory and code overlays e Access numerous math DSP and C C runtime library routines e Create host link port and PROM boot images e Initialize all data and code memory locations using modifiable loader e Concantenate multiple executables within single PROM image Overview VisualDSP is an easy to use project management environment comprised of an integrated development environment IDE and debugger VisualDSP enables management of projects from start to finish from within a single interface The project development and debug environments are integrated allowing movement easily between editing building and debugging activities a rrr ee ba ee ee zF hm 8 ie aie are nik 68 Boke tlre soem eo ENET I VisualDSP debugger interface Platform and Processor Support VisualDSP supports the SHARC DSP family on Windows 9x Windows NT and Windows 2000 ADSP 218x ADSP 218x does not have C and ADSP 219x families will be available soon Flexible Pr

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