User`s Guide
Contents
1. 73 7 ULP COM 5 874150 iaa 74 741 411 74 7 2 Linux EZ Software Development Kit 74 7 3 ULP COM sA3874i Linux Modifications 74 7 4 Kontron BSP Board Support 74 8 ULP COM 8538741 Boot Brief rin AM 75 8 1 ULP COM sA3874i Boot Up Sequence 75 WEE Ipae t 76 9 ULP COM SA38741 Programming 77 9 1 External SD Card Programming scosse aaae 77 9 2 SPIPrOGrammitgi uya do ee eee Ne een eaa ey e pev ee des are esed 77 9 3 Programming EI E OO 77 10 Appendix A Major Components ina taa 78 11 Appendix B Document REVISION 81 www kontron com Table of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figu2. VOUTO CLK T WV 55 LVDS CK exa LVDS CK D1 gt 5135 Figure 2 Sitara Module LVDS LCD Implementation www kontron com The following table details exactly how the Sitara ARM CPU parallel LCD pins are mapped to the on Module Texas Instruments SN65LVDS93AZ LVDS transmitter For 18 bit displays LVDS channels 0 1 and 2 are used For 24 bit displays that accept 18 bit color packing channels 0 1 2 and 3 are used i F8 A9 8 3 VOUTO_R 7 D7 VOUTO G 2 04 D3 D2 D1 D18 D15 D14 D13 VOUTO G 6 1 4 D12 D26 D25 024 022 021 20 1 AD14 VOUT O G Y YC 7 vour o G Y YC 6 VOUTO_G 5 VOUTO_G 4 VOUTO_G 3 VOUTO_AVID J J J E F G G J K5 4 K3 3 K2 K1 2 D5 5 6 6 5 6 K6 AB12 VOUT O G Y YC 5 VOUT 0 AVID VOUT 0 FLD AA10 B4 A4 A6 B5 D www kontron com T VOUTO B 4 2 MI VOUTO B 1 Not Used VOUTO B 0 Not Used VOUT 0 C 6 E mm per uei _ pes uere t ed 9 LM S Not Used C6 A5 H4 K4 2 www kontron com 3 2 8 Parallel LCD Display Interface The Sitara ARM CPU parallel 24 bit LCD interface is brought to the Module edge connector The interface runs at the 1 8V Module I O voltage This voltage swing may be used directly with 1 8V
3. 5100000 m c e ooo ooo E DDR3 REGULATOR DQ 23 16 DQ 7 0 DQ 23 16 DDR RANKO DDR RANK1 3V3_SO REGULATOR 100000001 2 015 2 100000002 RU 014 gt U17 I 15 55 REGULATOR CLOCK GENERATOR mm 021 CPLD gm 8 8 1 EEPROM 023 P 019 000000077 svs i LVDS TRANSMITTER ood REGULATOR EDGE FINGER SECONDARY SIDE J3 158 S76 575 Figure 9 ULP COM sA3874i Bottom Side Components 000000000000 8 8 LI 022 GBE CONTROLLER www kontron com sA3874i height information is shown in Figure 10 ULP COM sA3874i Edge View below 2 5x3mm STANDOF SOC HEIGHT I 3 00mm 2 95 mm d w 2 95mm i t 1 42mm 4 Figure 10 ULP COM sA3874i Edge View The SOC height above the PCB based on measurements performed on a number of assembled units is 2 7mm 0 1mm 3 4 5 Module Assembly Hardware The ULP COM sA3874i module is attached to the carrier with four M2 5 screws A 4mm length screw is usually used The attachment holes are located on the corners of the module Attachment holes have a 6mm diameter pad 2 7 mm dia drill hole as shown Figure 7 ULP COM 55438741 Top Side Components 3 4 6 Module Cooling Solution Attachment Two Penn Engineering and Manufacturing PEM SMTSO surface mount standoffs with M2 5 internal threads and 3mm stand o
4. 2 Introduction The ULP COM Ultra Low Power Computer on Module sA3874i is a versatile small form factor Computer On Module that requires low power and provides high performance at low cost The module connector has 314 edge fingers that mate with a low profile 314 pin 0 5mm pitch right angle connector this connector is sometimes identified as an 321 pin connector but 7 pins are lost to the key Featuring Texas Instruments ARM Cortex A8 microprocessor Kontron s ULP COM sA3874i offers LVDS Parallel LCD HDMI Display Gigabit Ethernet PCIe SATA USB USB OTG Camera support and graphics functions in a cost effective low power miniature package Kontron s ULP COM sA3874i thin and robust design makes it an ideal building block for reliable system design Caution The ULP COM sA3874i module is ESD sensitive equipment Users must observe precautions for handling electrostatic discharge sensitive devices 2 1 Feature Set Overview ULP COM compliant in an 82mm x 50mm form factor Y Texas Instrument single core 1 0 GHz ARM Cortex A8 SoC Up to 2GB of DDR3 SDRAM support On board NAND flash eMMC support up to 32GB On board Atheros AR8031 GbE PHY Single channel 18bit 24bit 18 bit compatible LVDS display panel support HDMI output GPIO support SDIO support Y Y Y Y Y Y Y Y 125 support Y I2C support One Parallel Camera interface Y 2 One PCIe port Y USB Host and
5. ww emm PY mur pape mus Tl me eem m T mex o emm Y P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 1 92 P94 P95 P97 98 P www kontron com ULP COM sA3874i Edge finger lote mm SLE sss ss ss ss sss s s ws 2 P117 GPIO9 CAN1_ERR wmm p LA e p me p eem 52 e CT www kontron com ULP COM sA3874i Edge finger TI Cortex A8 CPU _ Pp E E ppp gt pp T mE G E T E mp CT T T www kontron com ULP COM sA3874i Edge finger TI Cortex A8 CPU P153 VDD 1 7 E P154 VDD IN8 2 NR mw d macro 4 el _ id cal a wan wma AA wp 7007 e AA CT L A www kontron com ULP COM sA3874i Edge finger TI Cortex A8 CPU 525 GND17 ma ma 528 SDMMC D2 S29 SDMMC D3 SDMMC 04 i E pem 7 E JE EI SDMMC D5 SDMMC D6 500 CMD SD1 CMD GPO 2 NENNEN NE 546 1261 CK MCA 3 _ACLKX GPO 16 Through a 22 ohm resistor 547 GND19 SDMMC CK SDMMC CMD
6. ULP COM sA3874i 1 0 EN V 3V3 SO GPIO6 The ULP COM sA3874i module provides multiple I O lines for various functions 12 I Os lines are used as interrupt capable GPIOs which follow ULP COM hardware specification GPIO5 PWM output and GPIO6 Tachometer input support is also provided as per the ULP COM hardware specification Caution These details are provided for reference Generally access to the I O is abstracted in the Kontron BSP packages GPIO functionality and 1 0 mapping to the ULP COM sA3874i connector are shown in the following table Default Function Boot code should set this MCA 2 ACLKX GP GPIOO to output high GPIOO CAMO 0 10 sid Alternate Function CAMO active low camera power enable www kontron com MCA 2 _AFSX GPO GPIO1 11 CAM1_PWR VIN OJA_FLD CAM GPIO2 _D 5 GP0 20 CAMO_RSTH pp 08103 GPIO1 CAM1 PWRi GPIO2 CAMO_RSTH UART2_TXD GPIO3 CAM1_RST 6 0 27 GPIO4 HDA_RSTH GPIO4 GP1 8 HDA_RSTH GPMC_A 20 SPI 2 SCS 1 4 P113 GPIO5 PWM OUT GPIO5 PWM OUT GP1 15 GPIOG TACHIN GPIO6 TACHIN GPMC_CS 0 GP1 23 UART5 RXD I2C GPIO7 PCAM_FLD 2 _SCL GP2 1 _ GPIO7 PCAM Default Function Boot code should set this to output high Alternate Function 1 active low camera power enable Default Function Boot code should set this to output high Alternate Func
7. 4 6 2 6 S37 SDMMC_RST 1 Y Y N L 5 3 4 V T N V 6 1 H 3 www kontron com ULP COM sA3874i Edge finger Notes po L e 557 ON 5104 Connected to ground S58 PCAM ON 511 Connected to ground S60 SPDIF IN Connected through SPDIF S61 GND20 562 AFB_DIFFO 563 AFB DIFFO 64 565 AFB_DIFF1 receiver S67 568 AFB DIFF24 569 AFB DIFF2 570 571 AFB DIFF34 572 AFB DIFF3 573 GND24 www kontron com EH p ss ss www kontron com Y un 7 B8 8 D9 B9 9 F8 F6 E8 120 LCD_DE 122 LCD_HS AC11 VOUT O _HSYNC _ un un 123 LCD_PCK www kontron com ULP COM sA3874i Edge finger pa ww a _ apo p apo p mer p 1 40 EM un un un wx mm AA od 11 wem G 5151 CHARGING www kontron com 5152 CHARGER 5 S153 CARRIER STBYH S154 CARRIER ON MAX V CPLD MAX V CPLD MAX V CPLD 5156 BATLOW 5157 TEST 5158 VDD_IO_SEL V CPLD MAX V CPLD Tied to GND to indicate 1 8V I O www kontron com 4 2 JTAG Figure 13 shows the ULP COM sA3874i JTA
8. Document Revision History Revision Date Edited by Changes 1 0 Initial Public Release www kontron com Corporate Offices Europe Middle East amp Africa Oskar von Miller Str 1 85386 Eching Munich Germany Tel 49 0 8165 77 777 Fax 49 0 8165 77 219 info kontron com North America 14118 Stowe Drive Poway CA 92064 7147 USA Tel 1 888 294 4558 Fax 1 858 677 0898 info us kontron com Asia Pacific 17 Building Block 1 ABP 188 Southern West 4th Ring Beijing 100070 P R China Tel 86 10 63751188 Fax 86 10 83682438 info kontron cn www kontron com
9. HPD signals as well as ESD protection on all the HDMI signals The Carrier board ESD protection is important as HDMI is a hot pluggable interface A device such as the Texas Instruments TPD12S016 is recommended The Kontron ULP COM Evaluation Board schematic KAI 501 146 is useful as an implementation example www kontron com 3 2 11 Parallel Camera Interface The ULP COM sA3874i module supports one parallel camera interface The parallel camera interface signals are exposed on the ULP COM sA3874i edge connector as shown below ULP COM sA3874I Edge finger TI Cortex A8 CPU PCAM SIGNALS Net Name P13 D6 CSI1 02 VIN 0 A D 6 PCAM_D 6 P14 PCAM_D7 CSI1_D2_N VIN 0 A D 7 D 7 PCAM 08 511 D3 P VIN 0 A D 8 BD 0 PCAM 09 511 03 AGO VIN 0 A D 9 BD 1 D10 CSIO CK P 9 VIN 0 A D 10 BD 2 PCAM D11 CSIO CK N AH17 VIN O A D 11 BD 3 PCAM 012 510 00 P 617 VIN O A D 12 4 D13 CSIO DO N AF17 VIN 0 A D 13 BD 5 D14 CSIO 01 P 12 VIN 0 A D 14 BD 6 015 510 D1 VIN 0 A D 15 BD 7 Parallel camera input www kontron com ULP COM sA3874I Edge finger TI Cortex A8 CPU Net Name VIN 0 A CLK PXL CK Parallel camera primary pixel clock input 17 VIN O B Parallel camera Master Clock output S2 PCAM HSYNC AC20 VIN OJA_HSYNC PCAM_H
10. 5 kontron ULP COM sA38741 User Guide Document revision 1 0 Draft 07 www kontron com Table of Contents 1 1 8 AAA A 6 1 1 About This DOCUMENT D 6 1 2 Copyright eo rre erus os ever t Eee 6 1 3 MS 6 1 4 Quality Standards acosta rd en ve Hee xe A aa da a 6 1 57 RI 6 1 6 Technical SUpDOFES 3 u u ds ai 7 2 8 NEM C cEMU TAS 8 2 2 Software Support Hardware Abstraction 9 2 3 Document and Standards References 9 2 3 1 External Industry Standard Documents 9 2 3 2 kontron scietis L IN 10 2 3 3 A e Ree vet eek e EET 10 2 3 4 Texas Instruments Hardware Documents 10 2 3 5 Texas Instruments Software Documents 10 2 3 6 Kontron Software 5 Ey EE v
11. Client Support Watch Dog Timer WDT support UART support 2 Y Y CAN support SATA support Y 8 www kontron com 2 2 Software Support Hardware Abstraction The Kontron sA3874i Module is supported by Kontron BSPs Board Support Package The first sA3874i BSP targets Linux support and is available under Kontron part number xxx xxx 00 BSPs for other operating systems are planned Check with your Kontron contact for the latest BSPs This manual goes into a lot of detail on 1 0 particulars information is provided on exactly how the various ULP COM edge fingers tie into the Texas Instruments ARM SoC and to other Module hardware This is provided for reference and context Most of the I O particulars are covered and abstracted in the BSP and it should generally not be necessary for sA3874i users to deal with 1 0 at the register level 2 3 Document and Standards References 2 3 1 External Industry Standard Documents Y eMMC Embedded Multi Media Card the eMMC electrical standard is defined by JEDEC JESD84 B45 and the mechanical standard by JESD84 C44 www jedec org GbE MDI Gigabit Ethernet Medium Dependent Interface defined by IEEE 802 3 The 1000Base T operation over copper twisted pair cabling is defined by IEEE 802 3ab www ieee org HDMI Specification Version 1 3a November 10 2006 9 2006 Hitachi and other companies www hdmi org Y Y 2 The I2C Specification Version 2 1 January 2000 Philip
12. SDIO CK SDIO Clock signal signal SDIO 08 5010 08 5010 card detect SDIO PWR EN 4 501 POW 5010 PWR EN SD card power enable The SDIO card power should be switched on the Carrier board and the SDIO lines should be ESD protected The ULP COM Evaluation Carrier schematic KAI 501 146 is useful as an implementation reference www kontron com 3 2 17 SDMMC Interface for Carrier The ULP COM sA3874i module supports an 8bit SDMMC interface that may be used with a Carrier based eMMC device The ULP COM specification provides for an SDMMC data path that may be up to 8 bits wide The signaling level is at the Module I O voltage level of 1 8V SDMMC interface signals are exposed on the ULP COM sA3874i edge connector as shown below P Phe RR Data REI peer m Fm CK 500 CLK GPO 1 SDMMC CK SDMMC Clock SDMMC CMD 200 SDMMC CMD SDMMC Command GPO 2 Reset signal to www kontron com 3 2 18 SPI Interfaces The ULP COM sA3874i module supports two external SPI interfaces that are available off Module for general purpose use SPI interface signals are exposed on the ULP COM 55 38741 edge connector as shown below ULP COM sA3874i Edge finger TI Cortex A8 CPU Net Name SPI 0 Master Chip Select 0 SPI 3 _SCS O n SPI3_CSO output SPI 0 Master Chip Select 1 SPIO 51 SPI 3 SCS 1 n 5 518
13. Save option does save power and the response to events such as keyboard and mouse activity can be sluggish Evaluation units are available from Kontron to allow users to check out some of these tradeoffs www kontron com 3 6 Environmental Specification 3 6 1 Operating Temperature The ULP COM sA3874i module operates from 0 to 60 C air temperature with a passive heat sink arrangement Higher ambient temperature performance may be achieved with a passive or active cooling solution and will depend on system level thermal properties 3 6 2 Humidity Operating 1090 to 9090 RH non condensing Non operating 5 to 95 RH non condensing 3 6 3 RoHS Compliance The ULP COM sA3874i module is compliant to the 2002 95 EC RoHS directive www kontron com 4 Connectors 4 1 ULP COM sA3874i Edge Connector Pin Mapping e 00 0 O Figure 11 ULP COM sA3874i edge finger primary pins 200000000 gt 83 EDGE FINGER SECONDARY SIDE J3 St Figure 12 ULP COM sA3874i edge finger secondary pins www kontron com Pin mapping between the ULP COM sA3874i module edge connector and TI Cortex A8 SoC is shown in the table below Connections between the edge connector and other devices on the module are not shown ULP COM sA3874i Edge finger TI Cortex A8 CPU ESA meum Ee 3 DONSTL VIN 0 A 0101 VIN 0 A 0141 F P Aco 0
14. activity indicator www kontron com 5 4 Temperature Sensor This section to be updated in a future revision of this User s Guide There is no temperature sensor on Kontron sA3874i Sitara Rev A Modules An I2C interfaced NC72 sensor is available on the Rev B and later Modules 5 5 ULP COM sA3874i Power Management The ULP COM sA3874i module supports the following system and power management modes Deep Sleep Mode Standby mode Active Mode Low Power mode support and supported resume events are software dependant Please consult the software release notes available with the ULP COM sA3874i board support package at http emdcustomersection kontron com 5 6 Board ID EEPROM The ULP COM sA3874i module includes an I2C serial EEPROM available on the I2C PM bus An Atmel 24C32 or equivalent EEPROM is used in the module The device operates at 1 8V The Module serial EEPROM is placed at I2C slave addresses A2 AO set to 0 I2C slave address 50 hex 7 bit address format or AO hex 8 bit format for I2C EEPROMs address bits A6 A5 A4 A3 are set to binary 0101 convention The module serial EEPROM is intended to retain module parameter information including serial number The module serial EEPROM data structure conforms to the PICMG EEEP Embedded EEPROM Specification www kontron com 6 Thermal Design Considerations 6 1 Thermal Management A heat spreader plate assembly is available from Kont
15. derived from the Linux EZ Software Development Kit release provided by Texas Instruments version 5 05 04 01 Without changing any core functionality the software has been customized to enable native peripherals on the ULP COM sA3874i module and also to support additional features provided on the development carrier board 7 2 Linux EZ Software Development Kit The initial customer release for the ULP COM sA3874i software package is based in Linux EZ Software based on Linux kernel version 2 6 35 Texas Instrument Linux EZ Software resources for Cortex A8 SoC can be downloaded at http www ti com tool linuxezsdk sitara The ULP COM sA3874i bootloader is based in U Boot http www denx de wiki U Boot 7 3 ULP COM sA3874i Linux Modifications Texas Instruments has made available a Linux development kit LINUXEZSDK AM389X AM387X for support of the Cortex A3874 A8 SoC Kontron has performed a few modifications as follows Y Updated U Boot bootloader and configured the pin multiplexing Updated Kernel configuration file to support I2C I2S and all embedded interfaces available in the ULP COM 53874 and development carrier board Y 2 Added support for a set of programmable GPIO s Y Added support for Intel miniPCIe WiFi devices 2 Various I2C address changes Enabled SATA and PCIe Added support for WM8903 Audio codec Y Y Kontron s ULP COM sA3874i software documentation and release notes are available for
16. options from 4 GB up to 32 GB The standard SKUs support 4 GB eMMC flash 3 2 6 Clocks A 32 768 KHz clock is required for the Sitara ARM Cortex CPU RTC Real Time Clock and PMC Power Management Controller This clock is provided by Power Management Unit PMU www kontron com 3 2 7 LVDS Serialized LCD Display Interface The LVDS color packing used on the Module is in the 18 bit color compatible mode more details on this can be found later in this section and in the Ultra Low Power Computer Module Hardware Specification The display connection may be 18 bit or 24 bit but if a 24 bit connection is used then the display must be capable of accepting an 18 bit color packing This is sometimes alternatively referred to as 6 bit pack it s 6 bits per color or 18 bits total For single channel LVDS a display resolution up to approximately 1280 x 1024 may be supported approximate because factors such as Carrier Board trace lengths routing quality cable length and quality Carrier EMI and ESD suppression device selections and display timing particulars can affect the maximum resolution achieved For high resolution displays 1280 x 1024 and higher a Carrier Board based dual channel LVDS transmitter operating from the Module parallel data path should be used instead For flat panel use parallel LCD data and control information Red Green and Blue color data Display Enable Vertical Synch and Horizontal Synch are ser
17. rece cete See tear ehe eio ee o ener ts eee nes aet eeu ee pao esee cet ases e eon 64 TI COrt ex A8 CPU JTAG 64 ITA Gusana 65 5 E 72 Boot Selection Strap Implementation 76 1 User Information 1 1 About This Document This document provides information about products from Kontron and or its subsidiaries No warranty of suitability purpose or fitness is implied While every attempt has been made to ensure that the information in this document is accurate the information contained within is supplied as is and it is subject to change without notice For the circuits descriptions and tables indicated Kontron assumes no responsibility as far as patents or other rights of third parties are concerned 1 2 Copyright Notice Copyright 2012 Kontron America Inc All rights reserved No part of this document may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means electronic mechanical photocopying recording or otherwise without the express written permission from Kontron 1 3 Trademarks Sitara ARM and all other products and trademarks mentioned in this manual are trademarks of their respective owners 1 4 Quality Standards Kontron i
18. sA3874i Special Features 5 1 Watchdog Timer The ULP COM sA3874i module implements a Watchdog Timer WDT based on the TI Cortex A8 implementation with a 32b counter The WDT is made available through the standard Linux Watchdog API A description of the API is available following the link below http www kernel org doc Documentation watchdog watchdog api txt 5 2 PMU GPIO The PMU on the ULP COM sA3874i contains a few GPIOs These GPIOs are used for power management functionality but can also be used for general purpose 1 0 These GPIOs are different from ULP COM 5 38741 module hardware specification GPIOs The table below shows the PMU GPIO usage information details indication f SLEEP SLEEP SLEEP PMU_SLEEP Sleep indication from carrier board PMU_INT1 PMU Interrupt signal PWRDN High Temp warning signal P i f PWRON P128 POWER POWER BTN ower button input from carrier board NRESPWRON PMU NRESPWRON PMU reset out signal GPIOO V 1V5 DDR3 Power regulator EN V 1V5 DDR3 enable signal RESET_IN Reset input to the PMU SYS_RESET_IN through level translator www kontron com EN V 540 SYS V_5V0_SYS Power regulator enable signal V_3V3_SO Power regulator enable signal EN_V_3V3_S0_GPIO2 j VENE Was PGD V 3V3 SO V 3 3 50 Power good signal mm PGD V 1V5 DDR3 15 DURS Power good signal V 3 3 50 Power regulator enable optional signal 12 Te __ 5 3
19. sA3874i module complies with the default 1 0 voltage 1 8V level defined by ULP COM Hardware specification Module pin 5158 VDD_IO_SEL is tied low on the Module per the ULP COM specification indicating a 1 8V I O voltage level www kontron com 3 5 5 Power Consumption Power figures are given in the table below for the Module power consumption in various situations These are Module power figures Off Module power consumption e g display backlight display power Carrier board devices is not included here What is included in these power figures everything on the Module the TI Cortex A8 SoC the DDR3 DRAM the Module power supplies the Module LVDS transmitter the GBE controller and miscellaneous Module circuits Power measurement is done with MO 300 SATA Module mini PCIe Wi Fi Module HDMI Display 4 Ethernet cable is present in the Evaluation carrier wherever it is not mentioned Power figures are less for LVDS display and it is not shown in the below table The power figures below given below are subject to change Active state 1 0 GHz um umum 2D Graphics demonstration loop Active state 1 0 GHz 3D Graphics demonstration loop state 1 0 m m Stress test 859 CPU Load banal state 1 0 0 300 SATA miniPCIe Module not present amp Etherent cable is not plugged in oe state Hs EE ba state There are many options configurable in software And there are trade offs for example the Power
20. support 2 No 0 Parallel Camera support 2 Yes 1 USB Interface 3 Yes 2 PCIe Interface 3 Yes 1 SATA Interface 1 Yes 1 GbE Interface 1 Yes 1 SDIO Interface 1 Yes 1 SDMMC Interface 1 Yes 1 SPI Interface 2 Yes 2 I2S Interface 3 Yes 3 I2C Interface 5 Yes 5 CAN 2 Yes 2 AFB 1 No 0 1 0 Voltage 1 8V level Yes 1 0 Voltage 3 3V level No www kontron com 3 2 2 Form Factor The ULP COM sA3874i module complies with the ULP COM General Specification module size requirements in an 82mm x 50mm form factor 3 2 3 CPU The ULP COM sA3874i module implements Texas Instruments Sitara ARM Cortex A8 microprocessor Y 45nm AM3874 Cortex A8 1 0 GHz Single core 32 KB Instruction cache and 32 KB Data cache 512 KB L2 cache Y 2 Y 128 KB on chip memory controller 23 0 x 23 0 mm 684 pin FCBGA package 2 Y Allowable CPU junction temperature range 40 C to 90 C 3 2 4 Module Memory The ULP COM sA3874i module supports 1GB and 2GB total DDR3L memory through two separate orderable SKU s 51002 1000 08 1 ULP COM sA3874i 800 MHz 168 memory 51002 2000 08 1 ULP COM sA3874i 800 MHz 208 memory Additional SKUs may become available SKU variations would include alternative eMMC options including possibly no on Module eMMC Check with your Kontron contact or on the Kontron web site for updated information 3 2 5 On board Storage The ULP COM sA3874i module supports SPI flash memory devices with build
21. wutput SPIO CK SPI 3 SCLK SPI3 CK SPI O Master Clock output SPI 0 Master Data input SPIO DIN AC16 SPI 3 D 1 SPI3 DIN input to CPU output from SPI device SPI 0 Master Data output SPIO DO 21 SPI 3 D 0 SPI3 DO output from CPU input to SPI device SPI 1 Master Chip Select 0 5 11_ 50 SPI 1 _SCS 0 SPILCSO ee SPI 1 Master Chip Select 1 SPI1 51 SPI 1 SCS 1 n SPI1 518 aster Chip Selec output SPI SPI 1 SCLK SPI1 CK SPI 1 Master Clock output SPI 1 Master Data input SPI1 DIN SPI 1 0101 SPI DIN input to CPU output from SPI device SPI 1 Master Data output SPI1 DO SPI 1 D 1 SPI1 DO output from CPU input to SPI device www kontron com 5 3 2 19 125 Interfaces The ULP COM sA3874i module supports three off Module 125 DAP interfaces The default ULP COM audio interface 15 1250 and the Kontron 5 38741 bootloader implements this The other 125 ports may be used for audio if the bootloader is re configured for this or may be used for other devices that accept an I2S interface I2S interface signals are exposed on the ULP COM sA3874i edge connector as shown below 1250 539 1250 LRCK 13 MCA 0 AFSX 1250 LRCK Left amp Right audio synchronization clock S40 1250 SDOUT J1 MCA 0 AXR 1 I2C 3 SCL 1250 SDOUT Digital audio Output S41 1250 SDIN J2 MCA O _AXR 0 VCX_VIC 1 I2
22. 3 PCIe Interface The ULP COM sA3874i module supports one PCIe GEN2 interface PCIe interface signals are exposed on the ULP COM sA8374 edge connector as shown below PCIE A TX P PCIE TXPO PCIE A Differential PCIe Link A transmit data pair 0 Series decoupling PCIE TXNO PCIE 0 caps are provided in the Module ras EE PCIE RXNO uk mee Differential PCIe Link A receive peo pair 0 Series decoupling PCIE RXPO PCIE A RXO saps aie mot provided imithe Module PCIE REFCK P 2 7 PCIE REFCKO Differential PCIe Link reference clock output PCIE PCIE PCIe Port A clock request input P74 PCIE 5 16 TIM7 IO GPO 28 PCIE_A_PRSNT PC PCIe Port A present input IE A PRSNT 1 81 P75 PCIE A PCIE A PCIe Port A reset output active low is generated from CPLD www kontron com 3 2 14 SATA Interface The ULP COM sA3874i module supports one SATA port SATA interface signals are exposed on the ULP COM sA3874i edge connector as shown below SATA TX P SATA TXPO TX Differential SATA 0 data Pair SATA TX N SATA TXNO TX Series decoupling caps are provided in the Module SATA RXPO posue Differential SATA 0 poe dE data Pair bi SATA RXNO SATAO_RX Series decoupling caps are provided in the Module
23. 50511 01 N VIN O A_D 5 D7NCSI1 D2 N VIN OJA_D 7 PCAM_D8 CSI1_D3_P VIN 0 A D 8 BD O PCAM_D9 CSI1_D3_N D 9 BD 1 em LN GbE MDI2 N P1 P2 P P4 P5 P7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 PCAM_D6 CSI1_D2_P AH16 D 6 www kontron com ULP COM sA3874i Edge finger TI Cortex A8 CPU P24 GbE MDI2 P E OS 4 7 2 ll AAA pu mee 44 1440 _ qe UN ss ss SSS F SDIO_D3 SD1 DAT 3 P2 P3 B8 P1 P5 P4 25 26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 49 P www kontron com p50 GNDo il P 1 2 03 6 A6 A3 Li mem pa j USB1_N 581 DM CPLD mam AP I AA AA mum A mum AA P51 P52 P53 P54 P55 P56 P57 P58 P59 P61 P62 P63 P64 P65 P67 P68 70 71 72 73 74 75 www kontron com pasa mum E e mum LL LL E
24. G connectors location and pin out 0149 Figure 13 ULP COM sA3874i JTAG Connectors 4 2 1 Connector J2 CPU JTAG Figure 14 shows the TI Cortex A8 SoC JTAG connector 1 amp location detail Looooooon PIN 1 00000000 VIP nao zr o o o o o 0000 OO OO OO 000000 00 00 00 OO 00 000000 0000000000000000000000000000 Figure 14 TI Cortex A8 CPU JTAG www kontron com CPU JTAG Connector JST SM10B SRSS TB 1mm pitch R A SMD Header E es T L pom eo p eS 68 E p MFG MODE Caution The JTAG port is for internal use only Do not connect any devices 4 2 2 Connector J1 CPLD JTAG Figure 15 shows the CPLD JTAG connector pin1 amp location detail is shown in the figure below o B PIN 1 OO 0000000000 or 43 PH 156 Figure 15 CPLD JTAG www kontron com CPLD JTAG Connector JST SMO8B SRSS TB 1mm pitch SMD Header CPLD JTAG TDI CPLD JTAG TCK Connected to Ground through resistor EM Caution The JTAG port is internal use only Do not connect any devices 1 AA A www kontron com 5 ULP COM
25. Implementation USB port power enable and over current logic implementation between the TI AM3874CPU and CPLD is shown in the table below USBO DRVVBUS USB PortO power enable EN USB1 VBUS 1V8 2 z B Port1 10 1 EN USB1 VBUS 313 USB Port1 power enable USBO_OC USB PortO over current indication AE27 MI_AD 10 USB1_0CH USB Porti over current indication AF28 GMI CS1 IO L5 USB port power enable and over current logic implementation between the CPLD and ULP COM sA3874i edge connector is shown in the table below BP F3 10 F3 P62 USBO EN USBO EN HS i pone enable over current OCH indication signal 61 10 61 P67 USB1_EN_ USB1 EN ponei enable over current OCH indication signal www kontron com Power distribution for external USB plug in peripherals USB memory sticks cameras keyboards mice etc is typically handled by USB power switches such as the Texas Instruments TPS2052B Micrel MIC2026 1 or similar devices on the Carrier board The Enable pin on the Carrier board USB power switch must be active high and the Over Current pin OC must be open drain active low these are commonly available No pull up is required on the USB power switch Enable or line they are tied together on the Carrier and fed to the Module USBx EN OCit pin The pull up is on the Module 5V USBx_EN_OC Figure 5 USB Power Distribution Implementation on Carrier www kontron com 3 2 1
26. MI_CTRL_DAT AG24 HDMI SDA HDMI_CTRL_DAT Data 41 www kontron com User s Guide All five I2C busses originate in the multi master capable I2C controllers within the TI Cortex A8 SoC The only I2C devices on the sA3874i Module are on the I2C PM bus Those devices and their address details are listed in the following table 2 PM Bus Ox2D 0 58 General purpose usage address 1 TITPS65911C PMU U15 Voltage scaling address 2 On Semi NCT72 Thermal Sensor U26 0x4C 0x99 0x98 2 temperatures can be read CPU Thermal diode board ambient 3 Atmel AT24C02 U24 0x50 OxA1 OxAO General purpose parameter EEPROM Serial number etc in PICMG EEEP format 4 Altera CPLD U20 General purpose logic 5M240ZM100C5N As the name implies PM Power Management this 12 bus 15 used by low level software for system power management PMU regulator is attached to this bus and various voltage levels and options are continuously modified over this interface So use care if accessing this interface www kontron com 3 3 ULP COM sA3874i Debug 3 3 1 Serial Port for Linux Debug ULP COM module has 4 serial output ports SERO SER1 SER2 and SER3 Out of these 4 serial ports SER1 is set as the serial debug port use with Linux SER1 is exposed along with all other serial ports available on the module in the ULP COM Evaluation Carrier SER1 pin out of the ULP COM sA3874i is shown below Asynchronous serial port data o
27. S0 SDIN Digital audio Input S42 1250 CK R4 MCA O _ACLKX 1250 Digital audio clock 1251 543 1251 LRCK H4 MCA 3 _AFSX GPO 17 12S1_LRCK Left amp Right audio synchronization clock S44 1251_SDOUT G2 MCA 3 AXR 1 TIM5 IO GPO 19 1251_SDOUT Digital audio Output S45 1251 SDIN G1 31 AXR O TIM4 IO GPO 18 1251 SDIN Digital audio Input S46 1251 CK G6 MCA 3 ACLKX GPO 16 1251 CK Digital audio clock 1252 550 1252 LRCK H3 MCA 4 _AFSX GPO 22 1252 1 Left amp Right audio synchronization clock 551 1252 50001 34 MCA 4 AXR 1 TIM6 IO GPO 24 1252 SDOUT Digital audio Output 52 1252 SDIN H6 MCA 4 _AXR 0 GPO 23 1252 501 Digital audio Input 53 1252 CK K7 MCA 4 ACLKX GPO 21 1252 CK Digital audio clock Audio Master clock S38 AUDIO H1 AUD_CLKIN2 AUDIO_MCK Master clock output to Audio codec www kontron com 3 2 20 SPDIF Interface The ULP COM sA3874i module supports one SPDIF interface SPDIF interface signals are exposed on the ULP COM sA3874i edge connector as shown below SPDIF OUT MCA 1 AXR 2 MCB FSR SPDIF OUT Digital Audio Output SPDIF IN DEBER SPDIF IN Digital Audio Input 3 2 21 Asynchronous Serial Ports The ULP COM sA3874i module supports four UARTs SERO 3 UARTs SERO and SER2 supports flow control signals RTS CTS UARTs SER1 and SER3 do not support flow control The 5 38741 asynchronous serial port signals have a 1 8V level signal swing They can be converted to RS232 level an
28. S54 SATA_ACTH AE24 VIN 1 A_HSYNC GP2 28 SATA_ACTH SATA activity indication www kontron com User s Guide 3 2 15 Gigabit Ethernet Controller GbE Interface The ULP COM sA3874i module supports one GbE interface This is accomplished by using TI Cortex A8 50 5 internal MAC in conjunction with Atheros PHY AR8031 This is diagrammed below O M G27 ES 11 gt 37 12 GBE MDIO P29 RGMIIO TXDI 2 F28 RGMIIO TXD 3 14 GBE MDII 557 RGMIIO TXCTL GBE MDI1 P2 J26 34 12 4 gt P26 H27 15 MDI24 I GBE MDI2 4 _ m RGMIIO RXD O GBE PHY 31 SITARA 723 ATHEROS 20 MPIS peo xm U7 R23 AR8031 21 QGBE 3 y pig RGMIIO RXDI2 28 es 3 MEA 5 32 BE LINK100 p RXC a3 26 _SBE_LINK100 _ p21 127 INT ETH 5 24 GBE_LINK1000 P22 GBE_LINK_ACT T MDCLK 23 A P25 A MDIO Figure 6 GbE Controller Implementation www kontron com The following table details the TI AM3874 to Atheros GBE Phy AR8031 connection details TI Cortex A8 CPU GBE controller RGMIT transmit data GBE controller RGMII receive data RGMIIO_RXD2 RGMIIO_RXD 2 RGMIIO RXD3 RGMIIO RXD 3 RGMIIO RXCTL RGMIIO RXCTL RGMII receive data valid signal EMAC RMREFCLK TI 2 I0 GP1 10 H28 MDCLK MDC Management data clock re
29. SYNC Parallel camera Horizontal Sync input S1 PCAM_VSYNC AD20 VIN OJA_VSYNC PCAM_VSYNC Parallel camera Vertical Sync input P5 PCAM_DE AE21 VIN OJA_DE PCAM_DE Parallel camera Data Enable input GPIO7 PCAM_FLD AA20 VIN OJA_FLD VIN O GPIO7 PCAM_FLD Parallel camera Field B VSYNC UART5 R input XD I2C 2 SCL GP2 1 PCAM Support signals 55 I2C CAM AH26 12C 3 _SCL I2C CAM CK I2C3 Parallel camera support S7 I2C CAM DAT AA24 12C 3 _SDA I2C DAT I2C Parallel camera support GPIOO PWR MCA 2 ACLKX GPO GPIOO CAMO_PWR Camera 0 Power Enable 10 active low output D 5 GPo 20 low output 557 5104 Camera type selection signal S58 PCAM ON 5114 MID Camera type selection GPIO2 CAMO_RST VIN OJA_FLD CAM_ GPIO2 CAMO_RST Camera 0 Reset active signal www kontron com User s Guide 3 2 12 USB Interfaces The Kontron sA3874i module supports two USB ports USB 0 1 Per the ULP COM specification the Kontron sA3874i 0580 port is capable of functioning either as a client or host device The sA3874i module also supports one additional USB2 0 host port on ULP COM USB1 This product does not implement the optional third USB interface defined in the ULP COM spec USB interface signals are exposed on the ULP COM sA3874i edge connector as shown below USBO Port USBO P USBO DP USBO P61 USBO USBO DM USBO pair USB host power detection when this port is us
30. ana ue Ree erbe ovv as pear e Yin 10 o 11 3 1 Functional eie oon e EE eene Eb 11 3 2 SA3874i General F HCtioris teeth etti tene ee nacidos 12 3 2 1 UEP COM SA38741 Feature Seb rene eet peer ne o eoe EYE ear Ud eee seo darias 12 3 2 090 E 13 3 2 3 044 13 3 2 4 Mod le MEM iii 13 3 2 5 On board Storage eicere tere eee rere eo Cen ag ae eeu eve diia 13 3 2 6 13 3 2 7 LVDS Serialized LCD Display Interface 14 3 2 8 Parallel LCD Display Iriterface doe ae dere gus 17 3 2 0 Carrier Based 24 bit Color Depth LVDS 20 3 2 10 High Definition Multimedia Interface HDMI Interface 23 2 www kontron com 3 2 11 Parallel Camera Interfaces U l ua n EEE O REE EEE 24 3 2 12 USB Interfaces ON 26 3 2 13 PCIe Inti 29 3 2 14 SATA E 30 3 2 15 Gigabit Ethernet Contr
31. ath may be used to implement single or dual channel Carrier Board LVDS transmitter s The color packing may be 24 bit or 18 bit Since 18 bit single channel color packing is already available from the Module LVDS only 24 bit color packing is described in this section A single channel implementation uses one SN75LVDS83B or equivalent LVDS transmitter and a dual channel implementation uses one Thine THC63LVD827 or equivalent LVDS transmitter The same dual channel LVDS transmitter can be used for single channel LVDS implementation if the feature is available on the transmitter The following table shows how the sA3874i LCD pins should be mapped to TI SN75LVDS83B for standard single channel LVDS 24 bit color packing The chart shows pin numbers for the BGA version of the part The TSSOP version can be used as well although the pin numbering is different The pin names remain the same Transmitters from other vendors may be used as well D7 04 D3 D2 01 018 015 014 013 012 026 025 www kontron com COC mx M _ _ v T LAN NL 5 The following table shows how the 5 38741 LCD pins should be mapped to Thine THC63LVD82 for standard dual channel LVDS 24 bit color packing Other LVDS 24 bit mapping can be used with this transmitter Transmitters from other vendors may be used as well www kontron com Pixel clock very good lower cost alternative to
32. capable Carrier Board LVDS transmitters such as the TI SN75LVDS83B The 1 8V signaling may not be suitable for direct connection to a parallel flat panel Generally speaking only small panels with screen diagonals of 5 or less are available with a 1 8V interface Larger parallel LCD panels are likely to use 3 3V signaling and a set of voltage translators buffers would be needed on the Carrier RED VOUTO R 0 7 GREEN VOUTO G 0 7 BLUE VOUTO 0 7 m SITARA CPU 07 VOUTO HSYNC 3 VOUTO VSYNC Dee 5 13 SCIO CE S121 n AD12 S123 LCD DE EM CPLD 020 49 LCD_DUAL_PCK 10 Figure 3 Sitara Module Parallel LCD Implementation The mapping of the Sitara CPU parallel LCD balls to the ULP COM edge connector is shown in the table below For 24 bit implementations all bits are used For 18 bit implementations in ULP COM the least significant bits Red D17 16 Green D9 8 Blue D1 0 are dropped www kontron com F E A B A A A A A 8 6 8 9 B9 D9 8 8 H AA B 11 VOUT O B CB C 4 595 10 02 VOUTO B 2 15 VOUT O _B_CB_C 3 594 01 VOUTO B 1 AG7 00101 B CB C 2 LCD DO VOUTO B O www kontron com qe ax www kontron com 3 2 9 Carrier Based 24 bit Color Depth LVDS The Module parallel LCD p
33. cification CANO amp CAN1 The sA3874i supports both CAN buses The CAN bus interface signals on the ULP COM sA3874i edge connector are shown below P t P143 TX DCANO TX 2 PM CK I2CO Owen Managemen 12 bus clock CAN1_TX m I2 TX I2C GP CK I2C2 Genera pipes 6 bus clock I2 DCAN1 I2C GP DAT I2C2 DAT General purpose I2C bus data www kontron com 3 2 23 I2C Interface There are five I2C buses defined in the ULP COM specification PM Power Management LCD Liquid Crystal Display GP General Purpose CAM Camera and HDMI The sA3874i supports multiple masters and slaves in fast mode 400 KHz operation The I2C interface signals on the ULP COM sA3874i edge connector are shown below ULP COM sA3874i Edge finger 12 P P121 12 PM CK ACA 12C 0 _SCL 12C_PM_CK T2C0_CK ower management 12 bus clock P P122 I2C PM DAT 6 _ I2C 0 SDA 120 PM 2 DAT Power management I2C bus data GP 120 12 AF27 12C 2 _SCL 12C GP CK I2C2 bus clock 12 2 GP DAT I2C 2 SDA I2C GP DAT I2C2 DAT 7 C CAM I2C LCD I2C LCD display I2C b 5139 I2C LCD CK AH26 I2C 3 SCL I2C LCD CK I2C3 CK e uS LCD display I2 S140 I2C LCD DAT AA24 I2C 3 SDA I2C LCD DAT I2C3 DAT 2 HDMI I2C 12C 1 _SCL HDMI dedicated I2C P105 HDMI CTRL CK AF24 HDMI CTRL CK 12C 1 _SDA HDMI dedicated I2C P106 HD
34. d polarity signals by using a suitable RS232 transceiver There are transceivers available that accept a 1 8V signal level some examples include the Texas Instruments 53253 the Maxim MAX3218 and the Linear Technology LTC2801 Note that RS232 transceivers invert the signal a logic 1 is a negative voltage 3 0V to 15V and a logic 0 a positive voltage 3 0V to 15V on the RS232 line www kontron com Asynchronous serial ports interface signals are exposed on the ULP COM sA3874i edge connector as shown below SERO TX TXD SERO TX Asynchronous serial port data out SERO UART4 SERO Asynchronous serial port data in SERO UART4_RTSn SERO RTSH Request to Send handshake line for SERO SERO 154 UART4_CTSN SERO_CTS Clear to Send handshake line for SERO SER1 SER1 TX UARTO SER1 TX Asynchronous serial port data out SER1 RX UARTO SER1 RX Asynchronous serial port data in SER SER2 TX UART3 TXD SER2 TX Asynchronous serial port data out SER2 RX UART3 RXD SER2 RX Asynchronous serial port data in handshake line f P138 5 2 RTS AC24 UART3_RTS SER2_RTS handshake line fi P139 SER2 CTSH AA23 UART3 CTS SER2_CTS Une for SER3 SER3_TX UART2_TXD SER3_TX Asynchronous serial port data out SER3_RX UART2_RXD SER3_RX Asynchronous serial port data in www kontron com 3 2 22 CAN Interface There are two CAN buses defined in the ULP COM spe
35. download at the EMD Customer Section http emdcustomersection kontron com 7 4 Kontron BSP Board Support Package The Kontron sA3874i Module is supported by Kontron BSPs Board Support Package The first 5 38741 BSP targets Linux support available under Kontron part number XXX XXX 00 BSPs for other operating systems are planned Check with your Kontron contact for the latest BSPs www kontron com 8 8 1 ULP COM sA3874i Boot Brief ULP COM sA3874i Boot Up Sequence The following steps define the ULP COM sA3874i boot process at a high level 1 10 11 The power supplies on the module will be up and stable at the required voltage level after powering on the system System level hardware executes the power up sequence This sequence ends when system level hardware releases SYS RESET N The boot ROM on the TI Cortex A8 SoC begins executing and programs the on chip I O controllers to access the secondary boot device Secondary boot device will be selected based on the external boot device selection jumpers which are provided on the ULP COM carrier board Details are provided in the section 8 2 BOOT Selection The boot ROM on the TI Cortex A8 device fetches the Boot Configuration Table BCT and boot loader from the secondary boot device If the BCT and boot loader are fetched successfully boot ROM on the TI Cortex A8 device yields to the boot loader Otherwise boot ROM on the TI Cortex A8 device enters USB r
36. ecovery mode Note The ULP COM sA3874i uses U Boot boot loader The boot loader configures processor memories and essential peripherals into known and usable state The boot loader then loads the kernel image and jump to kernel The kernel sets up the processor and all peripherals as per configuration Kernel starts various kernel daemons and processes Finally kernel loads the file system and OS desktop Kontron has described the ULP COM sA3874i boot sequence in the Booting ULP COM white paper available in the EMD Section http emdcustomersection kontron com This is an interesting and insightful read Kontron encourages users to read this document and learn how to enable the power of this architecture www kontron com 8 2 BOOT Selection ULP COM sA3874i module can be booted from various devices or modules The boot selection is done in the carrier board by either floating the ULP COM BOOT_SELx pins or tying them to GND per the table below Currently only Carrier SD Card boot is supported FLOAT Serial Port 1 FLOAT FLOAT FLOAT Module SPI GND GND FLOAT Carrier SD Card FLOAT GND GND Module eMMC Caution A BOOT_SELx combination not contained in the table above is not valid The ULP COM sA3874i module will default to boot from the Module eMMC Flash if an invalid combination is selected The ULP COM sA3874i boot selection is provided from the module CPLD as a 4bit selection to the TI Cortex A8 SoC The CPLD provide
37. ed as a device P63 USB0_VBUS_DET AG12 USBO VBUSIN 0580 VBUS DET USB OTG ID P64 USBO_OTG_ID AG10 USBO_ID USBO_OTG_ID input active high USB1 Port P65 USB1_P USB1_DP USB1 USB1 port data USB1 N USB1_DM USB1 pn The ULP COM Hardware specification defines USBx where x 15 0 and 1 for use with USBO and USB1 pins as multifunction pins to use for power enable of USBx ports as well as for over current indication The ULP COM sA3874i complies with this definition These nets are provided with pull up resistors on the Module The Module CPLD contains the glue logic required for this implementation The sA3874i Module USB power enable and over current indication logic implementation is shown in the following block diagram There are 10K pull up resistors on the Module on the ULP COM USBx EN 0 8 lines The CPLD outputs driving the USBx lines are open drain The Carrier board USB power switch if present is enabled by virtue of the 10K Module pull up to 3 3V www kontron com 0880 EN OC PU EN USBO VBUS 1V8 EN USBO VBUS 3V3 K10 AF11 1v8 to 3v3 C1 Ls LEN_USB1_VBUS_1V8 Translator 0581 VBUS 3V3 m EI 4880 EN OC SITARA F P62 CPLD clu CPU U20 51 07 Ago USB0_OC_SV3 E USB1 EN OC PU 3v3 to 1v8 1 AF28 USB1 Translator USB1 15 lt USBILEN OC T Figure 4 External USB Port Power Distribution Logic
38. ference Management data 8 7 8 26 6 27 3 3 5 3 3 4 G2 G2 F2 H J2 H P2 R2 R2 T2 L2 L2 J www kontron com The following table details the Atheros GBE Phy AR8031 to ULP COM connections P30 GbE MDIO P 11 TRXPO GBEO Bi directional transmit receive pair 0 to magnetics GbE N TRXNO MDIO P 1 GbE MDI14 Bi directional transmit receive pair 1 to magnetics GbE MDI1 TRXN1 GbE_MDI1 GbE_MDI2_P TRXP2 GbE_MDI2 Bi directional transmit receive pair 2 to magnetics GbE_MDI2_N TRXN2 GbE MDI2 GbE MDI3 P TRXP3 GbE_MDI3 Bi directional transmit receive pair 3 to magnetics MDI3 N a TRXN3 EE MDI3 EM LINK100 LED_LINK10_100 LINK100 Link speed indication LED for 100Mbps open drain GbE_LINK1000 LED_LINK1000 GBEO_LINK1000 Link speed indication LED for 1000Mbps open drain GbE_LINK_ACT LED_ACT GBEO_LINK_ACT Link activity LED open drain www kontron com User s Guide 3 2 16 SDIO Interface The ULP COM sA3874i module supports a 4bit SDIO interface per the ULP COM specification The SDIO interface uses 3 3V signaling per the ULP COM spec and for compatibility with commonly available SDIO cards SDIO interface signals are exposed on the ULP COM sA3874i edge connector as shown below ma o mem 07 SDIO CMD 501 CMD GPO 0 SDIO CMD SDIO Command signal SDIO CK 5 1
39. ff height are soldered into the Module top side adjacent to the TI Cortex A8 SoC They are provided for the attachment of a heat spreader or heat sink independent of the corner mounting holes The PEM SMTSO parts have excellent pull strength and the Module PCB will deform before the standoffs can be pulled out The heat sink heat spreader mounting holes are shown in Figure 7 ULP COM sSA3874I Top Side Components The Heat Spreader is secured to the Module with two 6mm flathead M2 5 screws For a large area heat spreader or heat sink the corner holes should be used as well with suitable standoffs www kontron com 3 5 Electrical Specification 3 5 1 Supply Voltage The ULP COM sA3874i module operates over an input voltage range of 3 1V to 5 25V Power is provided from the carrier through 10 power pins as defined by the ULP COM specification Caution The ULP COM specification states that the input voltage range should extend down to 3 0V The 5 38741 lower limit is determined by a non volatile register setting in the TI PMU used 3 5 2 RTC Backup Voltage 3 0V RTC backup power is provided through the VDD_RTC pin from the carrier board This connection provides back up power to the module PMU 3 5 3 No Separate Standby Voltage The ULP COM sA3874i does not have a standby power rail Standby operation is powered through the main supply voltage rail as defined in the ULP COM specification 3 5 4 Module 1 0 Voltage The ULP COM
40. ialized onto a set of LVDS differential pairs The information is packed into frames that are 7 bits long For 18 bit color depths the data and control information utilize three LVDS channels 18 data bits 3 control bits 21 bits hence 3 channels with 7 bit frames plus a clock pair For 24 bit color depths four LVDS channels are used 24 data bits 3 control bits 1 unused bit 28 bits or 4 x 7 plus a clock pair The LVDS clock is transmitted on a separate LVDS pair The LVDS clock period is 7 times longer than the pixel clock period The LVDS clock edges are off from the 7 bit frame boundaries by 2 pixel periods Unfortunately there are two different 24 bit color mappings in use The more common one sometimes referred to as 24 bit standard color mapping is not compatible with 18 bit panels as it places the most significant RGB color data on the 4 LVDS data pair the pair that is not used on 18 bit panels There is a less common 24 bit 18 bit compatible mapping that puts the least significant color bits of the 24 bit set onto the 47 LVDS pair and allows 24 bit color depths VOUTO B 0 7 pe Beste H1 5126 VOUTO_G 0 7 LVDS1 VOUTO R 0 7 ERIDS G1 gt 5129 LVDS m XMITTER LVDS2 SITARA CPU U19 2 5131 2 SN65LVDS93AZ VOUT0_HSYN AC11 APPS 0_ 4 S 2 02255 8137 VOUTO VSYN 13 B4 LVpS3
41. it n n DDR A DDR3 DQ7 DQ0 T 256M x 8 AR DDRB CAN 2 instances DDR3 DQ31 DQ24 ARM Cortex A8 256M x 8 Sinale C Interfaces shown in gray ingle Core SPI Flash and with designation DDRB 800MHz 1 GHz 8MB are not used on this DDR3 0923 0016 S N etc module but may be used 256 8 P on other modules Industrial DDRB Temp DDR3 DQ15 DQ8 256M x 8 125 DAP 4 instances DDRB DDR3 007 000 SPDIF Out gt 256 8 SDDIF M 3PDFIn Receiver DIR9001 Micron SATA Industrial cule nic 0582 y Flash Memory 8 bit USB Host USB1 lt q v h Build options 058 OTG Client 380 y 4GB up to PCle C amp Options shown in this 32GB diagram are in the design N C 4 PCle B but may not be available in the standard product offerings Figure 1 ULP COM sA3874i Block Diagram www kontron com 3 2 ULP COM sA3874i General Functions This section lists the feature set supported by the ULP COM sA3874i module 3 2 1 ULP COM sA3874i Feature Set The following table summarizes the ULP COM features implemented on the sA3874i vs the maximum possible allowed in the ULP COM specification All mandatory features required by the ULP COM specification are implemented in the sA3874i Module LVDS Display support 1 Yes 1 Parallel LCD support 1 Yes 1 HDMI Display support 1 Yes 1 CSI Camera
42. oller GbE 31 3 2 16 SDIO Interface RETE 34 3 2 17 SDMMC Interface for Carrier eMMC nean to 35 3 2 18 5 HDIES C 36 3 2 19 TAS gt 37 3 2 20 SPDIF iP M 38 3 2 21 Asynchronous senal POMS uu uuu inte eterne 38 3 2 22 Brice 40 3 2 23 120 A 41 3 3 EA DE 43 3 3 1 SerialPort for Linux Debug cioe eee 43 3 3 2 EE VELOCI 43 3 4 Mechanical Specificatioris citando ERR SIR ORE Eo Seo Ae ER Ee RUE ee PE Ege gea 44 3 4 1 Module Dimensions sissies Eee eere deo ERO ii 44 3 4 2 t ER 44 3 4 3 Height on Bottom 44 3 4 4 Layout Diagralils eoe eere eror e re e Ea aii 44 3 4 5 Module Assembly eiie ere recette Speer eere 46 3 4 6 Module Cooling Solution Attachment 46 3 5 Electrical Specificato Ne epo 47 3 5 1 Supply A 47 3 5 2 Voltage eee eee tie asirio 47 3 5 3 Separate Standby Voltage
43. pp 47 3 5 4 T O Voltage u EI OOo 47 3 25 57 Power CONSUMPUION een 48 3 6 Environmental SpecifiCatlOR aiii iia 49 3 61 Operating Temperature 49 49 3 6 3 ROHS Compliance ninia rr 49 BGS UNS 50 4 1 ULP COM sA3874i Edge Connector Pin Mapping 50 3 www kontron com 4 0 ic cots 64 4 21 Connector J2 CPU JTAG e ao een 64 4 2 2 Connector JTAG 65 MEPSCOM SA39721 Special a na 67 nd 67 5 2 67 5 3 5 87 1 0 68 5 4 Temp rature Sensor sii aieo eei d 71 5 5 ULP COM sA3874i Power Management 71 5 6 Board ID EEPROM ie ener a 71 6 Thermal Design Considerations sin 72 6 1 Thermal Management 72 6 2 Heat Spreader DIMENSIONS ulaqa 72 6 3 Thermal P rdmetets s 73 6 4 Operation without Heat Spreader Heat Sink
44. re 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 5 www kontron com sA38741 Block A ei dete eye eue 11 Sitara Module LVDS LCD Implementation 14 Sitara Module Parallel LCD Implementation 17 External USB Port Power Distribution Logic Implementation 27 USB Power Distribution Implementation Carrler 28 GbE Controller Implementation pp 31 ULP COM 55438741 Side Components pp 44 ULP COM sA3874i Top Side Components Labeled 45 ULP COM sA3874i Bottom Side Components 45 2 5 38741 Edge c de 52551545 eroe tree va nero ea e ere po eu cod pede eve e eae e Ue or er Svp ee PP RENE QUON 46 ULP COM sA3874i edge finger primary pins 50 sA3874i edge finger secondary pins 50 5 38741 2 6 05 5
45. ron for the ULP COM sA3874i module The heat spreader plate on top of this assembly is NOT a heat sink It works as a ULP COM standard thermal interface to be used with a heat sink or other cooling device External cooling must be provided to maintain the heat spreader plate at proper operating temperatures Under worst case conditions the cooling mechanism must maintain an ambient air and heat spreader plate temperature of 60 C or less The aluminum slugs and thermal pads on the underside of the heat spreader assembly implement thermal interfaces between the heat spreader plate and the major heat generating components on the sA3874i Module About 80 of the power dissipated within the module is conducted to the heatspreader plate and can be removed by the cooling solution You can use passive thermal management solutions with the heatspreader plates The optimum cooling solution varies depending on the ULP COM application and environmental conditions 6 2 Heat Spreader Dimensions The ULP COM sA3874i module includes two mounting holes for mounting the passive heat sink located to the left and right of the TI Cortex A8 SoC Heat spreader dimensions are shown in the diagram below TIM stands for Thermal Interface Material Module ___ for Side Figure 16 Heat Spreader www kontron com The table below describes the function and assembly hardware required by each of the heatspreader holes 3mm standoffs Clearance hole
46. rt number xxx xxx 00 www kontron com 3 Specifications 34 Functional Block Diagram Power In 3 0 5 25V DC Y JTAG TI AM3874 UARTs 2x 2 Wire and 2x 4 Wire 274 GB DDR3 Memory 5010 4 Build option Sitara Boot Straps Boot Device Select 999 GPIO 12 Bit PWM Tach dco M SDIO eMMC 8 Bit PCle x1 Gen2 Root or End Point PCle A ee gem 227 MDI 4 pairs for GBE 82mm x 50mm Form Factor 8031 plus support signals LEDs etc N C lt A gt User s Guide 314 Pin 0 5mm pitch 1 edge finger pattern for Noise Power use with style Supplies M 2 carrier board connector CPLD JTAG d s aka the ULP COM Carrier Connector Actual pin order on the Misc i tor will differ Misc Ctrl Out b Misc Ctrl Out Reset etc connecto 1 GB DDR3 800 Logic from what is implied Memory Misc Ctrl In Misc Ctrl In Pwr Btn etc here DDRA DDR3 DQ31 DQ24 256M x 8 i LVDS 18 24 24 LVDS requires Xmiter LVDS display to be DDR3 Dass Hate 18 bit compatible PXL Clock Dual Pixel CI 256 8 Divider ES HDMI DDRA lt gt DDR3 DQ15 DQ8 No CSI Functions on this Module REA Parallel Camera Interface up to 16 b
47. s M2 5 Threaded Standoffs Clearance for M2 5 3mm captive standoff Cl for M2 5 earance M2 5 thread N A M3 thread N A 6 3 Thermal Parameters The TI Cortex A8 SoC thermal parameters are shown in the table below Junction Temperature Tj 40 C to 90 C Industrial temp grade Thermal Resistance CPU Junction to ambient 0 11 67 C W Thermal Resistance CPU Junction to case 0 39 C W Thermal Resistance CPU case to heat spreader far surface 0cs Less than 1 C W heat spreader is available now from Kontron for the sA3874i Module A passive heat sink solution is also available 6 4 Operation without a Heat Spreader Heat Sink The ULP COM sA3874i Module is sometimes used in a room temperature environment without any heat sink at all While it is easy and convenient it is not generally recommended as it can put the CPU die at or above the 90 C limit depending on what you are running and how system performance parameters CPU speed etc At the Linux desktop without any heat sinking at all assuming a typical SOC power consumption of 5W and an ambient room temperature of 23 C with all SOC features enabled the CPU die would be at about 81 5 5W 11 7 C W 23 C This is OK but there is not much margin A higher CPU load can push the temperature over the 90 C limit www kontron com 7 ULP COM sA3874i Software 7 1 Introduction Software in the ULP COM sA3874i is
48. s Semiconductor now www nxp com 125 Bus Specification Feb 1986 and Revised June 5 1996 Philips Semiconductor now NXP www nxp com JTAG Joint Test Action Group defined by IEEE 1149 1 2001 IEEE Standard Test Access Port and Boundary Scan Architecture www ieee org Y Y Y MXM3 Graphics Module Mobile PCI Express Module Electromechanical Specification Version 3 0 Revision 1 1 O 2009 NVIDIA Corporation www mxm sig org PICMG Embedded EEPROM Specification Rev 1 0 August 2010 www picmg org PCI Express Specifications www pci sig org 2 Y Y Serial ATA Revision 3 1 July 18 2011 Gold Revision 9 Serial ATA International Organization www sata io org 50 Specifications Part 1 Physical Layer Simplified Specification Version 3 01 May 18 2010 9 2010 SD Group and SD Card Association Secure Digital www sdcard org SPDIF aka S PDIF Sony Philips Digital Interface IEC 60958 3 Y Y Y SPI Bus Serial Peripheral Interface de facto serial interface standard defined by Motorola A good description may be found on Wikipedia http en wikipedia org wiki Serial Peripheral Interface Bus 2 USB Specifications www usb org 9 www kontron com 2 3 2 2 3 3 Documents Ultra Low Power Computer On Module Hardware Specification version 1 2 September 19 2012 9 Kontron 2012 Ultra Low Power Computer Module E
49. s a 3bit selection from the carrier as shown in the table above BOOT_SELO m MENISSSUME Ku po SITARA CPU Y28 C7 CPLD 010 e BIVODEP 020 1 BOOT_SEL1 e 5 V26 _ J11 BOOT_SEL2 P125 Figure 17 Boot Selection Strap Implementation www kontron com 9 sA3874i Programming Methods 9 1 External SD Card Programming The ULP COM sA3874i module supports external SD card boot and this card need to programmed through external Linux PC The following procedure need to be followed for programming the external SD card TBD 9 2 SPI Programming TBD This feature is not yet supported 9 3 eMMC Programming TBD This feature is not yet supported www kontron com 10 Appendix A Major Components IC CPU TI Cortex A8 AM3874 U7 IC PMU TPS6591104E 98 IC LVDS TRANSMITTER SN65LVDS93A BGA56 IC SPI FLASH 64 Megabit W25064DW WSON8 IC eMMC FLASH 1608 MTFC16GJVEC WFBGA169 IC GBE PHY ATHEROS AR8031 QFN40 IC TEMP SENSOR NCT72CMT WDFN8 IC EEPROM 2Kbits AT24CO2C VFBGA8 IC CPLD 5M240Z MBGA100 ALTERA ui TEXAS INSTRUMENTS AM3874 TEXAS INSTRUMENTS TPS6591104EA2ZRC R TEXAS INSTRUMENTS SN6SLVDS93AZQLR WINBOND W25064DWZP 1 optional MTFC16GIVEC 4MIT 024 AT24CO2C CUM T ON SEMICONDUCTOR 5M240ZM100C5N www kontron com 11 Appendix B
50. s certified to ISO 9000 Quality Standards 1 5 Warranty This Kontron product is warranted against defects in material and workmanship for the warranty period from the date of shipment During the warranty period Kontron will at its discretion decide to repair or replace defective products Within the warranty period the repair of products is free of charge as long as warranty conditions are observed The warranty does not apply to defects resulting from improper or inadequate maintenance or handling by the buyer unauthorized modification or misuse operation outside of the product s environmental specifications or improper installation or maintenance Kontron will not be responsible for any defects or damages to other products not supplied by Kontron that are caused by a faulty Kontron product 6 www kontron com 1 6 Technical Support Technicians and engineers from Kontron and or its subsidiaries are available for technical support We are committed to making our product easy to use and will help you use our products in your systems Please consult our website at http www kontron com support for the latest product documentation utilities drivers and support contacts Consult our customer section http emdcustomersection kontron com for the latest software downloads Product Change Notifications and additional tools and software In any case you can always contact your board supplier for technical support 7 www kontron com
51. the Thine THC63LVD82 dual channel LVDS transmitter is the TI DS90C187 dual channel LVDS transmitter A future version of this manual will replace the Thine references with a TI DS90C187 reference The module Design Guide is being written up with the TI DS90C187 as the example www kontron com 3 2 10 High Definition Multimedia Interface HDMI Interface The ULP COM sA3874i module supports a single HDMI interface with a resolution up to 1920x1080 pixels HDMI signals are exposed on the ULP COM sA3874i edge connector as shown below ULP COM sA3874i Edge finger TI Cortex A8 CPU Net Name HDMI Differential Signals P98 HDMI DO P AG19 HDMI DPO HDMI 00 HDMI Differential Data pai HDMI DO N AH19 HDMI DNO HDMI DO 0 output P95 HDMI D1 P AG20 HDMI DP1 HDMI 01 HDMI Differential D ir1 HDMI AH20 HDMI DN1 HDMI D1 par output P92 HDMI D2 P AG21 HDMI DP2 HDMI 02 HDMI Differential Data pair 2 P93 HDMI D2 N 21 HDMI DN2 HDMI D2 output P101 HDMI CK P HDMI CLKP HDMI HDMI Differential P102 HDMI CK N HDMI CLKN HDMI CK clock output HDMI Support signals HDMI Hot Plug P104 HDMI HPD AA26 HDMI HPDET HDMI Detect input HDMI dedi P105 HDMI CTRL CK AF24 HDMI SCL HDMI DDC SCL 1V8 12 Clock HDMI dedi P106 HDMI CTRL DAT HDMI CNTL DAT HDMI DDC SDA 1V8 ie 2 P107 HDMI HDMI HDMI The Carrier board must provide voltage translation the DDC
52. tion CAMO active low reset Default Function Boot code should set this to output high Alternate Function CAM1 active low reset Default Function Boot code should set this to output high Alternate Function HD Audio reset active low Default Function Boot code should set this to output high Alternate Function PWM output Default Function Boot code should set this to input Alternate Function Tachometer input Default Function Boot code should set this to input Alternate Function Parallel camera field input signal www kontron com CANO pii GPIO9 CAN1_ERR C A 24 GP1 25 TIM4 I0 GP1 27 GPMC ADV GPMC_CS 6 TIM 5 I0 GP1 28 GPIO11 VOUT 0 AVID V P118 GPIO10 01101 FLD TCLKIN GPO 30 GPIO9 CAN1_ERR GPIO10 GPIO11 VOUT AVID PCIE GPIO1 IO L8 DEV OE PCIE A PCIE A 4 L9 1019 SATA SATA User s Guide to input Alternate Function CANO bus error signal Default Function Boot code should set this to input Alternate Function 1 bus error signal Default Function Boot code should set this to input Alternate Function General purpose IO Default Function Boot code should set this to input Alternate Function General purpose IO LCD data enable option signal PCIe wake interrupt signal through MAX V CPLD PCIe A optional active low reset SATA
53. ut Name OTe 1 UARTO_TXD SER1_TX SER1_TX UARTO_RXD SER1_RX SER1_RX Asynchronous serial port data in 3 3 2 AM3874 CPU JTAG A JTAG connector is provided on board for the debugging purpose Connector Reference Designator J2 is used for this purpose Pin out details are provided in section 4 2 1 Connector J2 CPU JTAG www kontron com 3 4 Mechanical Specifications 3 4 1 Module Dimensions The ULP COM sA3874i complies with ULP COM Hardware Specification in an 82mm x 50 mm form factor 3 4 2 Height on Top Caution 3 0 mm maximum the ULP COM specification defines as 3 0 mm as the maximum 3 4 3 Height on Bottom Caution 1 45 mm maximum whereas the ULP COM specification defines as 1 3mm as the maximum 3 4 4 Layout Diagrams Top side major component IC and Connector information is shown in Figure 7 ULP COM 55 38741 Top Side Components NL 4x62 7mm B6mm PAD M2 5X4mm SCREW DAD 2 4 2 6 2 PAD HEAT SPREADER MOUNTING Figure 7 ULP COM 55 38741 Top Side Components www kontron com O D J PIN 1 mm 0160 DO JL lo 05 SPDIF RECEIVER SD TRANSCEIVER PIN 1 NS 90 O L U7 SITARA CPU Figure 8 ULP COM sA3874i Top Side Components Labeled Bottom side major component IC amp Connector information is shown in Figure 9 User s Guide 011 221 es 012 555 880
54. valuation Carrier User Manual Version 1 0 September 10 2012 9 Kontron 2012 Ultra Low Power Computer On Module Evaluation Carrier Quick Start Manual Version 1 0 September 10 2012 9 Kontron 2012 Kontron Schematics The following schematic numbers are listed for reference The Module schematic is not usually available outside of Kontron without special permission The other schematics may be available under NDA or otherwise Contact your Kontron representative for more information The ULP COM Evaluation Carrier schematic is particularly useful as an example of the implementation of various interfaces on a Carrier board Y Y 2 3 4 Y Y 2 3 5 2 2 3 6 5438747 Module 501 149 latest revision ULP COM Evaluation Carrier KARMA Eval Carrier Board Schematic 501 146 latest revision eMMC Mezzanine Schematic KAI 501 151 latest revision KLAS Schematic Hyundai 1366 x 768 Single Ch LVDS KAI 501 162 latest revision KLAS Schematic NEC 1280 x 768 Single Ch LVDS KAI 501 163 latest revision Texas Instruments Hardware Documents AM387x Sitara ARM Processors Datasheet SPRS695B Rev B Sept 14 2012 AM387x Sitara Technical Reference Manual 5 PRUGZ7B Rev B July 24 2012 Texas Instruments Software Documents Linux EZ Software Development Kit for Sitara ARM Microprocessors LINUXEZSDK Sitara July 27 2012 Kontron Software BSP Kontron BSP for ULP COM sA3874i Module Kontron pa
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