Home

DE1-SoC User Manual 1 www.terasic.com April 2, 2015

1. where szData is an array of six bytes B Demonstration Source Code e Build tool Altera SoC EDS v13 1 e Project directory Demonstration SoC hps_gsensor e Binary file gsensor e Build command make make clean to remove all temporal files e Execute command gsensor loop count B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEI SoC board and the host PC DE1 SoC User Manual 95 www terasic com TijasiC April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM e Copy the executable file esensor into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEI SoC board e Power on the DEI SoC board e Launch PuTTY to establish connection to the UART port of DEI SoC board Type root to login Yocto Linux e Execute gsensor in the UART terminal of PuTTY to start the G sensor polling e The demo program will show the X Y and Z values in the PuTTY as shown in Figure 6 8 Figure 6 8 Terminal output of the G sensor demonstration e Press CTRL C to terminate the program 6 4 12C MUX Test The I2C bus on DEI SoC is originally accessed by FPGA only This demonstration shows how to switch the I2C multiplexer for HPS to access the I2C bus B Function Block Diagram Figure 6 9 shows the function block diagram of this demonstration The I2C bus from both FPGA and HPS are connected to an DC multiplexer It is control
2. DE1 506 USER MANUAL NNNM MANA N y AN Y t M UT AN Hn m MI K Rtg fis ter PET Ea e UNIVERSITY PROGRAM www terasic com Copyright 2003 2014 Terasic Technologies Inc All Rights Reserved CONTENIS DECEM CHAPTER1 DE7 SOC DEVELOPMENT KIT ee esen naaa anna nana nnn nnn nnn nnn nnne 4 I ee EE BN EQ A Pi 4 IBS DEIR OC System Como Ec 5 IB reru das aon ence sea AA basi ve nageccsavarsecsasatensaamyssnaceosgooasatarsentareeensantiaere 5 CHAPTER2 NTRODUCTION OF THE DE1 SOC BOARD cessere nnne 6 2 T Layout and BMC SN ORT 6 2 2 Block Diagram of the DEI SoC Board ooooW Wanna 9 CHAPTERS USING THE DET SOC BOARD wesbite 12 3 1 Settings of FPGA Configuration Mode nenda ae aa nennen nnne nennen nennen 12 3 2 Configuration of Cyclone V SoC FPGA on DE1 S0C mn 13 2 9 Board Status Elements ssns esta sentana sana nda asetat sca oU Ios na nan ga son on na P IARE 19 14 Board Reset Blei sma ngan Ban UE 20 3 iles d ici TU T I Tm 21 3 0 Peripherals Connected to the BP GA vosicins cvs esicepvansissaranssaietauciuasvessbanvlensiauscasssdielatcineavassbensiosalascs 23 3 6 1 User Push buttons Switches and LEDS oo oooo ooWooo om oo Wo Wo ener rennen tentent een 23 31012 Iesooment IDISP AY nn tk am eh setan AA ea 26 20 9 20 GAG Pepsodent nana an tan sen as 28 3104 24 Dit Audio CODEC nama 30
3. ADCDAT AUD_ADCLRCK ADCLRCK Figure 3 20 Connections between the FPGA and audio CODEC Table 3 12 Pin Assignment of Audio CODEC 3 6 5 12C Multiplexer Signal Name FPGA Pin No Description AUD ADCLRCK X PIN K8 Audio CODEC ADC LR Clock AUD ADCDAT PIN K7 Audio CODEC ADC Data AUD DACLRCK PIN H8 Audio CODEC DAC LR Clock AUD DACDAT PIN J7 Audio CODEC DAC Data AUD XCK PIN G7 Audio CODEC Chip Clock AUD BCLK PIN H7 Audio CODEC Bit stream Clock I2C SCLK PIN J12 or PIN E23 I2C Clock I2C SDAT PIN K12 or PIN C24 I2C Data Mic In Line In D J2 Line Out 4 J3 I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V The DEI SoC board implements an I2C multiplexer for HPS to access the I2C bus originally owned by FPGA Figure 3 21 shows the connection of I2C multiplexer to the FPGA and HPS HPS can access Audio CODEC and TV Decoder if and only if the HPS_I2C_CONTROL signal is set to high The pin assignment of I2C bus is listed in Table 3 13 Tasic DE1 SoC User Manual www terasic com 31 www terasic com April 2 2015 I2C Bus FPGA Qsys Figure 3 21 Control mechanism for the I2C multiplexer MEM Table 3 13 Pin Assignment of I2C Bus MEM SignalName FPGAPinNo Description VO Standard FPGA I2C SCLK PIN J12 FPGA I2C Clock 3 FPGA I2C SDAT PIN K12 FPGA I2C Data HPS I2C1 SCLK PIN E23 RC Clock of the first HPS I2C
4. 6 2 Users LED and KEY This demonstration shows how to control the users LED and KEY by accessing the register of GPIO controller through the memory mapped device driver The memory mapped device driver allows developer to access the system physical memory B Function Block Diagram Figure 6 1 shows the function block diagram of this demonstration The users LED and KEY are connected to the GPIOI controller in HPS The behavior of GPIO controller is controlled by the register in GPIO controller The registers can be accessed by application software through the memory mapped device driver which is built into Altera SoC Linux DE1 SoC User Manual 87 www terasic com asic April 2 2015 www terasic com FPGA SoC DDR3 ARM Program HPS Linux User Mode LED Linux Kernel Mode KEY Figure 6 1 Block diagram of GPIO demonstration B Block Diagram of GPIO Interface The HPS provides three general purpose I O GPIO interface modules Figure 6 2 shows the block diagram of GPIO Interface GPIO 28 0 is controlled by the GPIOO controller and GPIO 57 29 is controlled by the GPIOI controller GPIO 70 58 and input only GPI 13 0 are controlled by the GPIO2 controller GPI 13 0 GPIO Interface Reset gpio rst n n Interrupt amp NE Control Register Manager j GPIO 28 0 Slave GPIO 57 29 Interface Ike TN lt y L4 Peripheral Bus GPIO 70 58 Figure 6 2 Block diagram of
5. www terasic com mg E Line In Baie Push Button 3d bb Figure 5 4 Block diagram of the Karaoke machine demonstration B Demonstration Setup File Locations and Instructions e Project directory DEI SOC i2sound e Bitstream used DEI SOC 12sound sof e Connect a microphone to the microphone in port pink color e Connect the audio output of a music player such as a MP3 player or computer to the line in port blue color e Connect a headset speaker to the line out port green color e Load the bitstream into the FPGA by executing the batch file DEI SOC i2sound in the directory DEI SOC i2s5ound Memo batch e Users should be able to hear a mixture of microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume level 0 to 9 Figure 5 5 illustrates the setup for this demonstration DE1 SoC User Manual 65 WWW terasic com Tijasic April 2 2015 www terasic com MP3 Any Audio Output Microphone A ty Wa Cw 1 E 3 E at Pm i i f PEU nnne Hz H paa D 1 oft i3 i H g H H 2 gt Ld LI LI LI LI Le H EE IP BADAN a RD bool bel bret bel beet vet Deol feel bet Clock Data Frequency Generator Figure 5 5 Setup for the Karaoke machine 5 4 SDRAM Test in Nios II There are many applications use SDRAM as a temporary storage Both hardware and software designs are provided to illustrate how
6. ANU S RYA PIN w17 ED4 LEDS E Si HE LEDS Cyclonet V E ce LED6 20M Lv LED 2 LEDe LED p ES epe LED9 Figure 3 17 Connections between the LEDs and the Cyclone V SoC FPGA Table 3 6 Pin Assignment of Slide Switches Signal Name FPGA Pin No Description O Standard SW 0 PIN AB12 Slide Switch 0 3 3V SW 1 PIN AC12 Slide Switch 1 3 3V SW 2 PIN_AF9 Slide Switch 2 3 3V SWI3I PIN AF10 Slide Switch 3 3 3V SW A PIN AD11 Slide Switch 4 3 3V SW 5 PIN AD12 Slide Switch 5 3 3V SW 6 PIN_AE11 Slide Switch 6 3 3V SWI 7 PIN AC9 Slide Switch 7 3 3V SW 8 PIN_AD10 Slide Switch 8 3 3V SW 9 PIN_AE12 Slide Switch 9 3 3V Table 3 7 Pin Assignment of Push buttons Signal Name FPGA Pin No Description VO Standard KEY 0 PIN AA14 Push button 0 3 3V KEY 1 PIN AA15 Push button 1 3 3V KEY 2 PIN W15 Push button 2 3 3V KEY 3 PIN Y16 Push button 3 3 3V DE1 SoC User Manual 25 www terasic com asic April 2 2015 www terasic com Table 3 8 Pin Assignment of LEDs Signal Name FPGA Pin No Description VO Standard LEDR 0 PIN V16 LED 0 3 3V LEDR 1 PIN W16 LED 1 3 3V LEDR 2 PIN_V17 LED 2 3 3V LEDR 3 PIN_V18 LED 3 3 3V LEDR 4 PIN_W17 LED 4 3 3V LEDR 5 PIN_W19 LED 5 3 3V LEDR 6 PIN_Y19 LED 6 3 3V LEDR 7 PIN_W20 LED 7 3 3V LEDR 8 PIN_W21 LED 8 3 3V LEDR 9 PIN Y21 LED 9 3 3V 3 6 2 7 segment Displays The DEI SoC board has six 7 segment displays These displays are paired to display numbers i
7. Figure 3 23 VGA horizontal timing specification Table 3 14 VGA Horizontal Timing Specification VGA mode Horizontal Timing Spec Configuration Resolution HxV a us b us c us d us Pixel clock MHz VGA 60Hz 640x480 3 8 1 9 25 4 0 6 25 VGA 85Hz 640x480 1 6 2 2 17 8 1 6 36 SVGA 60Hz 800x600 3 2 2 2 20 1 40 SVGA 75Hz 800x600 1 6 3 2 16 2 0 3 49 SVGA 85Hz 800x600 1 1 2 7 14 2 0 6 56 XGA 60Hz 1024x768 2 1 2 5 15 8 0 4 65 XGA 70Hz 1024x768 1 8 1 9 13 7 0 3 75 XGA 85Hz 1024x768 1 0 2 2 10 8 0 5 95 1280x1024 60Hz 1280x1024 1 0 2 3 11 9 0 4 108 Table 3 15 VGA Vertical Timing Specification VGA mode Vertical Timing Spec Configuration Resolution HxV a lines b lines c lines d lines Pixel clock MHz VGA 60Hz 640x480 2 33 480 10 25 VGA 85Hz 640x480 3 25 480 1 36 SVGA 60Hz 800x600 4 23 600 1 40 SVGA 75Hz 800x600 3 21 600 1 49 SVGA 85Hz 800x600 3 27 600 1 56 XGA 60Hz 1024x768 6 29 768 3 65 XGA 70Hz 1024x768 6 29 768 3 75 XGA 85Hz 1024x768 3 36 768 1 95 1280x1024 60Hz 1280x1024 3 38 1024 1 108 DE1 SoC User Manual 34 www terasic com asic April 2 2015 www terasic com Table 3 16 Pin Assignment of VGA Signal Name FPGA Pin No Description VO Standard VGA RIO PIN A13 VGA Red 0 3 3V VGA R 1 PIN C13 VGA Red 1 3 3V VGA R 2 PIN E13 VGA Red 2 3 3V VGA RI3I PIN B12 VGA Red 3 3 3V VGA R 4 PIN C12 VGA Red 4 3 3V VGA R 5 PIN D12 VGA Red 5 3 3V VGA R 6 PIN E12 VGA Red 6 3 3V VGA R T7 PIN F13 VGA Req 7 3 3V VGA G 0 PIN
8. PIN W25 PIN V25 PIN AA28 PIN Y27 PIN AB27 PIN AB26 PIN AA26 PIN AA25 DE1 SoC User Manual Kadasic www terasic com Description Seven Segment Digit O 0 Seven Segment Digit 0 1 Seven Segment Digit O 2 Seven Segment Digit 0 3 Seven Segment Digit O 4 Seven Segment Digit 0 5 Seven Segment Digit O 6 Seven Segment Digit 1 0 Seven Segment Digit 1 1 Seven Segment Digit 1 2 Seven Segment Digit 1 3 Seven Segment Digit 1 4 Seven Segment Digit 1 5 Seven Segment Digit 1 6 Seven Segment Digit 2 0 Seven Segment Digit 2 1 Seven Segment Digit 2 2 Seven Segment Digit 2 3 Seven Segment Digit 2 4 Seven Segment Digit 2 5 Seven Segment Digit 2 6 Seven Segment Digit 3 0 Seven Segment Digit 3 1 Seven Segment Digit 3 2 Seven Segment Digit 3 3 Seven Segment Digit 3 4 Seven Segment Digit 3 5 Seven Segment Digit 3 6 Seven Segment Digit 4 0 Seven Segment Digit 4 1 Seven Segment Digit 4 2 Seven Segment Digit 4 3 Seven Segment Digit 4 4 Seven Segment Digit 4 5 Seven Segment Digit 4 6 Seven Segment Digit 5 0 Seven Segment Digit 5 1 Seven Segment Digit 5 2 Seven Segment Digit 5 3 Seven Segment Digit 5 4 Seven Segment Digit 5 5 Seven Segment Digit 5 6 27 I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3
9. TARGET TARGET main o ILDFLAGS o 8 s due CFLAGS c o clean rm f TARGET a f o B Compile Please launch Altera SoC EDS Command Shell to compile a project by executing C Naltera13 NNembeddedEmbedded Command Shell bat The cd command can change the current directory to where the Hello World project is located DE1 SoC User Manual 86 www terasic com TijasiC April 2 2015 www terasic com UNIVERSITY PROGRAM The make command will build the project The executable file my first hps will be generated after the compiling process is successful The clean all command removes all temporary files B Demonstration Source Code e Build tool Altera SoC EDS v13 1 e Project directory Demonstration SoC my_first_hps e Binary file my first hps e Build command make make clean to remove all temporary files e Execute command my first hps B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEI SoC board and the host PC e Copy the demo file my first hps into a microSD card under the home root folder in Linux e Insert the booting microSD card into the DEI SoC board e Power on the DEI SoC board e Launch PuTTY and establish connection to the UART port of Putty Type root to login Altera Yocto Linux e Type my first hps in the UART terminal of PuTTY to start the program and the Hello World message will be displayed in the terminal
10. and other interfaces connected exclusively Users can control these interfaces to monitor the status of HPS Table 3 23 gives the pin assignment of all the LEDs switches and push buttons DE1 SoC User Manual 43 www terasic com Cijasic April 2 2015 www terasic com Table 3 23 Pin Assignment of LEDs Switches and Push buttons Signal Name HPSGPIO Register bit Function HPS KEY GPIO54 GPIO1 25 VO HPS LED GPIO53 GPIO1 24 VO 3 7 2 Gigabit Ethernet The board supports Gigabit Ethernet transfer by an external Micrel KSZ9021 RN PHY chip and HPS Ethernet MAC function The KSZ9021RN chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver also supports RGMII MAC interface Figure 3 32 shows the connections between the HPS Gigabit Ethernet PHY and RJ 45 connector The pin assignment associated to Gigabit Ethernet interface is listed in Table 3 24 More information about the KSZ9021 RN PHY chip and its datasheet as well as the application notes which are available on the manufacturer s website HPS ENET TX DATA 3 0 TXD 3 0 HPS ENET GTX CLK GTX CLK HPS ENET TX EN x EN MDI HPS N HPS ENET RX DATAQ 3 0 RXDI3 0 L HPS MDI HPS P JNO S RYAN HPS ENET RX CLK py ci Tx HPS i HPS ENET RX DV py Cyclone a e HPS ENET MDC jc HPS HPS ENET MDIO LED2 DUAL 1 3 4 LED2 DUAL 2 HPS ENET INT N INT N HPS ENET RESET N E mam RESET N ENET CL
11. which provides non volatile storage for the bit stream The information is retained within EPCS 128 DE1 SoC User Manual 13 www terasic com asic April 2 2015 www terasic com UNIVERSITY PROGRAM even if the DEI SoC board is turned off When the board is powered on the configuration data in the EPCS128 device is automatically loaded into the Cyclone V SoC FPGA B JTAG Chain on DE1 SoC Board The FPGA device can be configured through JTAG interface on DEI SoC board but the JTAG chain must form a closed loop which allows Quartus II programmer to the detect FPGA device Figure 3 2 illustrates the JTAG chain on DE1 SoC board Extemal JTAG Header Em Installed FPGA TA TDI HPS TDI lt gt lt Cyclone V USB ES ll JY FPGA TDO Connector Figure 3 2 Path of the JTAG chain B Configure the FPGA in JTAG Mode There are two devices FPGA and HPS on the JTAG chain The following shows how the FPGA is programmed in JTAG mode step by step 1 Open the Quartus II programmer and click Auto Detect as circled in Figure 3 3 DE1 SoC User Manual 14 www terasic com Tijasic April 2 2015 www terasic com ANU S RYAN UNIVERSITY PROGRAM Window Help 57 esce JCJ Enable real time ISP to allow background programming for MAX II and MAX V devices Checksum Usercode Program Verify Configure ET Start B Stop Fi Auto Detect x Delete 3 Add File Lab Save F
12. 2409 5 a P OR PER sae case nde re on an mane tata mantel Kes na anna ab anta A A PA 31 SO E e E akan Uno meta 32 SEO IN D O e UU D MT 35 OR E E T 37 Sr Menard Bab N A 37 DE1 SoC User Manual 1 www terasic com TijasiC April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM 3 6 FO IBS nun kans ma me ea 38 SEEN Pe aio AE TTE 40 30 12 A D Converter and 2x5 LIe SIE ceteros aereo espana ee enamel emng 42 3 7 Peripherals Connected to Hard Processor System HPS an 43 5 7 1 User Push buttons and LEDS 5 at mmm 43 De Ga bi ANIC MNCL TTE anal inna E 44 SNR BR THO nana 45 ADDR NIGRO aeos se02 000080909925 p1029995 3502862086000040089595 01919555 1206 0 20000 09 A 100000 0000000090697 46 Iha NITO SD Card SOCKEL mC 48 3 102 port Bo mio EE aka bana 49 Na ea M RE UU Tm 50 SMA MA COCCO e DETULIT 51 CHAPTER 4 DET SOC SYSTEM BUILDER nana cessisse eene eene nennen nnne nnne nnn nnn nnns 53 dE Intodu eos RUE 53 a NU Desi OV NT ea ea an AB 53 4 3 Using DE1 SoC System Builder ierit poppe E cH Io coe vos ua I km nm ana 54 CHAPTER5 EXAMPLES FOR EF OI em nana aran anna nan n anna nana 60 SJ DEI S0C Factory ContigOtatIOh oo oo o ommoooimwlamast anita 60 5 2 Audio Recording and PIAYIng woo oo mo meanaste 940 952850 05699800099 22 959 5 0868 05051
13. 3 HPS DDR3 DQ O HPS DDR3 DQ 1 HPS DDR3 DQ 2 HPS DDR3 DQ 3 HPS DDR3 DQIA HPS DDR3 DQ 5 HPS DDR3 DQ 6 HPS DDR3 DQ 7 HPS DDR3 DQ HPS DDR3 DQ 9 HPS DDR3 DQ 10 HPS DDR3 DOQ 11 HPS DDR3 DQ 12 HPS DDR3 DQ 13 HPS DDR3 DOQ 14 HPS DDR3 DQ 15 HPS DDR3 DOQ 16 HPS DDR3 DQ 17 HPS DDR3 DO 18 HPS DDR3 DQ 19 HPS DDR3 DQ 20 HPS DDR3 DQ 21 HPS DDR3 DQ 22 PIN F29 PIN E28 PIN H27 PIN G26 PIN D29 PIN C30 PIN B30 PIN C29 PIN H25 PIN E29 PIN J24 PIN J23 PIN E27 PIN L29 PIN L23 PIN M23 PIN H24 PIN K28 PIN M28 PIN R28 PIN W30 PIN K23 PIN K22 PIN H30 PIN G28 PIN L25 PIN L24 PIN J30 PIN J29 PIN K26 PIN L26 PIN K29 PIN K27 PIN M26 PIN M27 PIN L28 PIN M30 PIN U26 PIN T26 PIN N29 PIN N28 PIN P26 PIN P27 PIN N27 DE1 SoC User Manual Kadasic www terasic com HPS DDR3 Address 6 HPS DDR3 Address 7 HPS DDR3 Address 8 HPS DDR3 Address 9 HPS DDR3 Address 10 HPS DDR3 Address 11 HPS DDR3 Address 12 HPS DDR3 Address 13 HPS DDR3 Address 14 HPS DDR3 Bank Address 0 HPS DDR3 Bank Address 1 HPS DDR3 Bank Address 2 DDR3 Column Address Strobe HPS DDR3 Clock Enable HPS DDR3 Clock HPS DDR3 Clock p HPS DDR3 Chip Select HPS DDR3 Data Mask 0 HPS DDR3 Data Mask 1 HPS DDR3 Data Mask 2 HPS DDR3 Data Mask 3 HPS DDR3 Data 0 HPS DDR3 Data 1 HPS DDR3 Data 2 HPS DDR3 Data 3 HPS DDR3 Data 4 HPS DDR3 Data 5 HPS DDR3 Data 6 HPS DDR3 Data 7 HPS DDR3 Data 8 HP
14. 3 34 shows signals connected between the HPS and Micro SD card socket Table 3 28 lists the pin assignment of Micro SD card socket to the HPS DE1 SoC User Manual Kadasic www terasic com 48 www terasic com April 2 2015 SD CLK 5 SD CMD 3 e 7 Micro SD Card Cvclone CV Lo ul Sod yc One SoC TN Li lll bd Figure 3 34 Connections between the FPGA and SD card socket Table 3 28 Pin Assignment of Micro SD Card Socket Signal Name FPGA Pin No Description O Standard HPS SD CLK PIN A16 HPS SD Clock 3 3V HPS SD CMD PIN F18 HPS SD Command Line 3 3V HPS SD DATAIOJ PIN G18 HPS SD Data 0 3 3V HPS SD DATAT 1 PIN C17 HPS SD Data 1 3 3V HPS SD DATA 2 PIN D17 HPS SD Data 2 3 3V HPS SD DATA 3 PIN B16 HPS SD Data 3 3 3V 3 7 6 2 port USB Host The board has two USB 2 0 type A ports with a SMSC USB3300 controller and a 2 port hub controller The SMSC USB3300 device in 32 pin OFN package interfaces with the SMSC USB2512B hub controller This device supports UTMI Low Pin Interface ULPI which communicates with the USB 2 0 controller in HPS The PHY operates in Host mode by connecting the ID pin of USB3300 to ground When operating in Host mode the device is powered by the two USB type A ports Figure 3 35 shows the connections of USB PTG PHY to the HPS Table 3 29 lists the pin assignment of USBOTG PHY to the HPS DE1 SoC User Manual 49 WWW terasic com TijasiC April 2 2015 www terasic com HPS USB
15. DATA 0 HPS USB CLKOUT JAN DTE RYA HPS USB NXT Cyclone y HPS USB DIR ag HPS USB STP HPS Signal Name HPS USB CLKOUT HPS USB DATAIOJ HPS USB DATA 1 HPS USB DATA 2 HPS USB DATA 3 HPS USB DATA 4 HPS USB DATA 5 HPS USB DATA 6 HPS USB DATA T HPS USB DIR HPS USB NXT HPS USB RESET HPS USB STP 3 7 7 G sensor U30 RSTnMRn USBPHY CLK 24 ADM812 PIN N16 PIN E16 PIN G16 PIN D16 PIN D14 PIN A15 PIN C14 PIN D15 PIN M17 PIN E14 PIN A14 PIN G17 PIN C15 N Q HPS RESET n U9 USB CPEN DATA 7 0 CPEN EN OUT USB_EXTVBUS CLKOUT EXTVBUS USB_VBUS USBUP_DM USBUP DP tb FAULT N TPS2553DRVR U2 NXT VBUS DIR DM USBUP_DM USBUP_DP USBDN1_DP USBDN1_DM USBDN2 DP USBDN2 DM USB3300 USBHUB CLK 24 XTALIN CLKIN USB2512 Table 3 29 Pin Assignment of USB OTG PHY FPGA Pin No Description 60MHz Reference Clock Output HPS USB DATA 0 HPS USB DATA 1 HPS USB DATA 2 HPS USB DATA 3 HPS USB DATA 4 HPS USB DATA HPS USB DATA 6 HPS USB DATA 7 Direction of the Data Bus Throttle the Data HPS USB PHY Reset Stop Data Stream on the Bus USB VCC5 Figure 3 35 Connections between the HPS and USB OTG PHY I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V The board comes with a digital accelerometer sensor module ADXL345 commonly known as G sensor This G sensor is a small thin ultralow power assumpti
16. E ioc Hoo 5 35 7 Segment Display x6 Figure 2 3 Block diagram of DE1 SoC Detailed information about Figure 2 3 are listed below DE1 SoC User Manual 9 www terasic com Tijasic April 2 2015 www terasic com FPGA Device e Cyclone V SoC 5CSEMASF31 Device e Dual core ARM Cortex A9 HPS e 85K programmable logic elements e 4 450 Kbits embedded memory e 6 fractional PLLs e 2 hard memory controllers Configuration and Debug e Quad serial configuration device EPCS128 on FPGA e Onboard USB Blaster II normal type B USB connector Memory Device e 64MB 32Mx16 SDRAM on FPGA e 1GB 2x256Mx16 DDR3 SDRAM on HPS e Micro SD card socket on HPS Communication e Two port USB 2 0 Host ULPI interface with USB type A connector e UART to USB USB Mini B connector e 10 100 1000 Ethernet e PS 2 mouse keyboard e IR emitter receiver e 2C multiplexer Connectors e Two 40 pin expansion headers e One 10 pin ADC input header e One LTC connector one Serial Peripheral Interface SPI Master one I2C and one GPIO interface DE1 SoC User Manual 10 www terasic com asic April 2 2015 www terasic com Display e 24 bit VGA DAC Audio e 24 bit CODEC Line in Line out and microphone in jacks Video Input e TV decoder NTSC PAL SECAM and TV in connector ADC e Fast throughput rate 1 MSPS e Channel number 8 e Resolution 12 bit e Analog input range 0 2 5 V or 0 5V as selected via the RANGE bit in
17. Hard Processor System e 800MHz Dual core ARM Cortex A9 MPCore processor e 1GB DDR3 SDRAM 32 bit data bus e Gigabit Ethernet PHY with RJ45 connector e 2 port USB Host normal Type A USB connector e Micro SD card socket e Accelerometer I2C interface interrupt e UART to USB USB Mini B connector e Warm reset button and cold reset button e One user button and one user LED e TC 2x7 expansion header DE1 SoC User Manual 8 www terasic com TijasiC April 2 2015 www terasic com 2 2 Block Diagram of the DE1 SoC Board Figure 2 3 is the block diagram of the board All the connections are established through the Cyclone V SoC FPGA device to provide maximum flexibility for users Users can configure the FPGA to implement any system design 25MHz Clock Input P Clock Generator x1 x4 PS 2 SDRAM x16 64 MB Micro mim SD Card REMI e5 vu Ethernet USB Host Normal Type A DDR3 x72 SDRAM x32 1 GB USB Mini B x Co D 40 pin GPIO x C e 40 pin GPIO Cyclo ety oC SCSEMASF31C6N Video DAC x N e VGA 8 bit Video In ti a ua di x6 Line Out FPGA HPS I2C I2C x2 From HPS Switch Control Line In IR RX x1 x1 Clock Clock Generator 2x7 LTC Header x1 x1 x1 x1 ieee Ie HPS HPS HPS WAR User LED RST User RST Button aaaaaaagada LED x10 Push Button x4 BEBRRRERRE Slide Switch x10
18. J9 VGA Green 0 3 3V VGA G 1 PIN J10 VGA Green 1 3 3V VGA G 2 PIN H12 VGA Green 2 3 3V VGA G 3 PIN G10 VGA Green 3 3 3V VGA G 4 PIN G11 VGA Green 4 3 3V VGA G 5 PIN G12 VGA Green 5 3 3V VGA G 6 PIN F11 VGA Green 6 3 3V VGA G T7 PIN E11 VGA Green 7 3 3V VGA BIO PIN B13 VGA Blue 0 3 3V VGA B 1 PIN G13 VGA Blue 1 3 3V VGA B 2 PIN H13 VGA Blue 2 3 3V VGA BI3I PIN F14 VGA Blue 3 3 3V VGA B 4 PIN H14 VGA Blue 4 3 3V VGA B 5 PIN F15 VGA Blue 5 3 3V VGA B 6 PIN G15 VGA Blue 6 3 3V VGA BIT PIN J14 VGA Blue 7 3 3V VGA CLK PIN A11 VGA Clock 3 3V VGA BLANK N PIN F10 VGA BLANK 3 3V VGA HS PIN B11 VGAH SYNC 3 3V VGA VS PIN D11 VGA V SYNC 3 3V VGA SYNC N PIN C10 VGA SYNC 3 3V 3 6 7 TV Decoder The DEI SoC board is equipped with an Analog Device ADV7180 TV decoder chip The ADV7180 is an integrated video decoder which automatically detects and converts a standard analog baseband television signals NTSC PAL and SECAM into 4 2 2 component video data which is compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 is compatible with wide range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras www terasic com DE1 SoC User Manual 35 TijasiC April 2 2015 www terasic com UNIVERSITY PROGRAM The registers in the TV decoder can be accessed and set through serial I2C bus by the Cyclone V SoC FPGA or HPS Note that the I2C address W R of the
19. SoC User Manual 69 www terasic com Tijasic April 2 2015 www terasic com RW test module writes the entire memory with a test seguence first before comparing the data read back with the regenerated test seguence which is same as the data written to the memory KEYO triggers test control signals for the SDRAM and the LEDs will indicate the test result according to Table 5 3 Design Tools Quartus II v13 1 Demonstration Source Code Project directory DEI SoC SDRAM RTL Test Bitstream used DEI SoC SDRAM RTL Test sof Demonstration Batch File Demo batch file folder DEI SoC SDRAM RIL Testidemo batch The directory includes the following files Batch file DE SoC SDRAM RTL Test bat FPGA configuration file DEI SoC SDRAM RTL Test sof Demonstration Setup Quartus II v13 1 must be pre installed to the host PC Connect the DEI SoC board J13 to the host PC with a USB cable and install the USB Blaster II driver if necessary Power on the DEI SoC board Execute the demo batch file DEI SoC SDRAM RTL Test bat from the directoy DE1 SoC SDRAM RTL Test Memo batch Press KEYO on the DEI SoC board to start the verification process When KEYO is pressed the LEDR 2 0 should turn on When KEYO is then released LEDRI and LEDR2 should start blinking After approximately 8 seconds LEDRI should stop blinking and stay ON to indicate the test 1s PASS Table 5 3 lists the status of LED indicators If LEDR2 is not blinking it means 50M
20. User Manual 98 www terasic com asic April 2 2015 www terasic com Chapter 7 Examples for using both HPS SoC and FGPA Although HPS and FPGA can operate independently they are tightly coupled via a high bandwidth system interconnect built from high performance ARM AMBA AXITM bus bridges Both FPGA fabric and HPS can access to each other via these interconnect bridges This chapter provides demonstrations on how to achieve superior performance and lower latency through these interconnect bridges when comparing to solutions containing a separate FPGA and discrete processor 7 1 HPS Control LED and HEX This demonstration shows how HPS controls the FPGA LED and HEX through Lightweight HPS to FPGA Bridge The FPGA is configured by HPS through FPGA manager in HPS B A brief view on FPGA manager The FPGA manager in HPS configures the FPGA fabric from HPS It also monitors the state of FPGA and drives or samples signals to or from the FPGA fabric The application software is provided to configure FPGA through the FPGA manager The FPGA configuration data is stored in the file with rbf extension The MSEL 4 0 must be set to 01010 or 01110 before executing the application software on HPS B Function Block Diagram Figure 7 1 shows the block diagram of this demonstration The HPS uses Lightweight HPS to FPGA AXI Bridge to communicate with FPGA The hardware in FPGA part is built into DE1 SoC User Manual 99 www terasic com asic April 2 2
21. and so on The pin direction of HPS LED and HPS KEY are controlled by the bit 24 and bit 25 in the gpio swporta ddr register of the GPIOI controller respectively Similarly the output status of HPS LED is controlled by the bit 24 in the gpio swporta dr register of the GPIOI controller The status of KEY can be queried by reading the value of the bit 24 in the gpio ext porta register of the GPIOI controller DE1 SoC User Manual 9 www terasic com asic April 2 2015 www terasic com UNIVERSITY PROGRAM GPIO1 Controller gpio swporta ddr register Controls the Direction of HPS GPIO29 Controls the Direction of HPS GPIO30 Controls the Direction of HPS GPIO31 Controls the Direction of HPS GPIOS3 HPS LED Controls the Direction of HPS GPIO54 HPS KEY Controls the Direction of HPS GPIO55 Controls the Direction of HPS GPIO56 Controls the Direction of HPS GPIO57 Figure 6 5 gpio swporta ddr register in the GPIO1 controller The following mask is defined in the demo code to control LED and KEY direction and LED s output value define USER IO DIR 0x01000000 define BIT LED 0x01000000 define BUTTON MASK 0x02000000 The following statement is used to configure the LED associated pins as output pins alt setbits word virtual base Cuint32 t C ALT GPIO SWPORTA DDR ADDR amp uint32 t HW REGS MASK USER IO DIR The following statement 1s used to turn on the LED alt setbits word virtual base Cuint
22. board configuration in cfg file as shown in Figure 4 6 DE1 SoC User Manual 58 www terasic com Tijasic April 2 2015 www terasic com UNIVERSITY PROGRAM DE1 SoC V1 0 0 System Configuration UNIVERSITY Wwww Lterasic com Project Name PROGRAM DEI SOC DE1 SoC FPGA Board MI CLOCK Mi Seqment x 6 MW LED x 10 MI Switch x 10 4 Button x 4 M IR TX RX VIVGA Mi Video In Wi Audio v ADC SDRAM 32MB Wi PS2 FE HPS GPIO 0 Header None S Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 6 Project Settings B Project Generation When users press the Generate button the DEI SoC System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 Table 4 1 Files generated by the DE1 SoC System Builder No m Project name gpf Quartus II Project File Wi Project name gsf Quartus II Setting File ui Project name sdc Synopsis Design Constraints file for Quartus II LN Project name htm Pin Assignment Document Users can add custom logic into the project in Quartus II and compile the project to generate the SRAM Object File sof DE1 SoC User Manual 59 www terasic com Tijasic April 2 2015 www terasic com Chapter 5 Examples For FPGA This chapter provides examples of advanced designs implemented by RTL or Qsys on the DEI SoC board These reference designs cover the features
23. concontroller HPS I2C1 SDAT PIN C24 I2C Data of the first HPS I2C concontroller HPS I2C2 SCLK PIN H23 JI2C Clock of the second HPS I2C concontroller _ HPS I2C2 SDAT PIN A25 I2C Data of the second HPS I2C concontroller 3 3V 3 6 6 VGA The DEI SoC board has a 15 pin D SUB connector populated for VGA output The VGA synchronization signals are generated directly from the Cyclone V SoC FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC only the higher 8 bits are used transforms signals from digital to analog to represent three fundamental colors red green and blue It can support up to SXGA standard 1280 1024 with signals transmitted at 100MHz Figure 3 22 shows the signals connected between the FPGA and VGA asic DE1 SoC User Manual 32 www terasic com kidd 25 C Apr i 2 2015 VGA RI 7 0 VGA G 7 0 is ia PN OTS 2YA VGA BI7 0 VGA_CLK PAD Cyclone y ADV7123 soc VGA_SYNC_N VGA_BLANK_N VGA_VS VGA_HS Figure 3 22 Connections between the FPGA and VGA The timing specification for VGA synchronization and RGB red green blue data can be easily found on website nowadays Figure 3 22 illustrates the basic timing requirements for each row horizontal displayed on a VGA moni
24. e If the VGA D SUB connector is connected to a VGA display it would show a color picture e If the stereo line out jack is connected to a speaker and KEY 1 is pressed a 1 kHz humming sound will come out of the line out port e For the ease of execution a demo batch folder is provided in the project It is able to not only load the bit stream into the FPGA in command line but also program or erase jic file to the EPCO by executing the test bat file shown in Figure 5 1 If users want to program a new design into the EPCQ device the easiest method is to copy the new sof file into the demo_batch folder and execute the test bat Option 2 will convert the sof to jic and option 3 will program jic file into the EPCQ device Plesase choise your operation a for programming sof to FPGA 2 For converting sof to jic US for programming jic to EPCQ 4 for erasing jic From EPC nE hE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE Please enter your choise 11 2 3 41 Figure 5 1 Command line of the batch file to program the FPGA and EPCQ device 5 2 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player on DEI SoC board with the built in audio CODEC chip It is developed based on Qsys and Eclipse Figure 5 2 shows the buttons and slide switches used to interact this demonstration onboard Users can configure this audio sys
25. n HPS DDR3 WE n HPS DDR3 RZQ PIN R29 PIN P24 PIN P25 PIN T29 PIN T28 PIN R27 PIN R26 PIN V30 PIN W29 PIN M19 PIN N24 PIN R18 PIN R21 PIN N18 PIN N25 PIN R19 PIN R22 PIN H28 PIN D30 PIN P30 PIN C28 PIN D27 HPS DDR3 Data 23 HPS DDR3 Data 24 HPS DDR3 Data 25 HPS DDR3 Data 26 HPS DDR3 Data 27 HPS DDR3 Data 28 HPS DDR3 Data 29 HPS DDR3 Data 30 HPS DDR3 Data 31 HPS DDR3 Data Strobe n 0 HPS DDR3 Data Strobe n 1 HPS DDR3 Data Strobe n 2 HPS DDR3 Data Strobe n 3 HPS DDR3 Data Strobe p 0 HPS DDR3 Data Strobe p 1 HPS DDR3 Data Strobe p 2 HPS DDR3 Data Strobe p 3 HPS DDR3 On die Termination DDR3 Row Address Strobe HPS DDR3 Reset HPS DDR3 Write Enable External reference ball for output drive calibration 3 7 5 Micro SD Card Socket SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class I SSTL 15 Class I SSTL 15 Class SSTL 15 Class SSTL 15 Class l SSTL 15 Class I Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class l Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class I SSTL 15 Class SSTL 15 Class 1 5 V The board supports Micro SD card interface with x4 data lines It serves not only an external storage for the HPS but also an alternative boot option for DEI SoC board Figure
26. of peripherals connected to the FPGA such as audio SDRAM and IR receiver All the associated files can be found in the directory Demonstrations FPGA of DEI SoC System CD B Installation of Demonstrations To install the demonstrations on your computer Copy the folder Demonstrations to a local directory of your choice It is important to make sure the path to your local directory contains NO space Otherwise it will lead to error in Nios II Note Quartus II v13 0 or later is required for all DEI SoC demonstrations to support Cyclone V SoC device 5 1 DE1 SoC Factory Configuration The DEI SoC board has a default configuration bit stream pre programmed which demonstrates some of the basic features onboard The setup required for this demonstration and the location of its files are shown below B Demonstration Setup File Locations and Instructions e Project directory DEI SoC Default e Bitstream used DEI SoC Default sof or DEI SoC Default jic e Power on the DEI SoC board with the USB cable connected to the USB Blaster II port If necessary that is if the default factory configuration is not currently stored in the EPCQ device download the bit stream to the board via JTAG interface e You should now be able to observe the 7 segment displays are showing a sequence of characters and the red LEDs are blinking DE1 SoC User Manual 60 www terasic com asic April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM
27. user space alt read word read a value from a specified register alt write word write a value into a specified register munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt setbits word set specified bit value to one for a specified register alt clrbits word set specified bit value to zero for a specified register The program must include the following header files to use the above API to access the registers of GPIO controller include stdio h include unistd h include fcntl h DE1 SoC User Manual 90 www terasic com Tijasic April 2 2015 www terasic com include sys mman h include hwlib h include socal socal h include socal hps h include socal alt gpio h B LED and KEY Control Figure 6 4 shows the HPS users LED and KEY pin assignment for the DEI SoC board The LED is connected to HPS GPIOS53 and the KEY is connected to HPS GPIO54 They are controlled by the GPIOI controller which also controls HPS GPIO29 HPS GPIOS57 HPS GPIos4 L G21 HPS KEY HPS GPIO53 424 HPS LED Figure 6 4 Pin assignment of LED and KEY Figure 6 5 shows the gpio swporta ddr register of the GPIOI controller The bit O controls the pin direction of HPS GPIO29 The bit 24 controls the pin direction of HPS GPIOS53 which connects to HPS LED the bit 25 controls the pin direction of HPS GPIOS54 which connects to HPS KEY
28. with SFL solution 3 3 Board Status Elements In addition to the 10 LEDs that FPGA device can control there are 5 indicators which can indicate the board status See Figure 3 10 please refer the details in Table 3 3 UART JTAG TXD RXD TX RX 12 V Power re d Figure 3 10 LED Indicators on DE1 SoC asic DE1 SoC User Manual 19 www terasic com bad 25 C Apr i 2s 2015 UNIVERSITY PROGRAM Table 3 3 LED Indicators Board Reference LED Name Di4 mv Power Illuminate when 12V power is active TXD UART TXD Illuminate when data is transferred from FT232R to USB Host RD U ART RXD Illuminate when data is transferred from NIEVE ARCH NONA MAN RON EP Host to FT232R JTAG RX Reserved 3 4 Board Reset Elements There are two HPS reset buttons on DEI SoC HPS cold reset and HPS warm reset as shown in Figure 3 11 Table 3 4 describes the purpose of these two HPS reset buttons Figure 3 12 is the reset tree for DE1 SoC HPS WARM RSTn Beeston boys bowel el roel bol beet Pool Kl Kl Kel HPS RESET n Figure 3 11 HPS cold reset and warm reset buttons on DE1 SoC DE1 SoC User Manual 20 www terasic com Tijasic April 2 2015 www terasic com Table 3 4 Description of Two HPS Reset Buttons on DE1 SoC Board Reference Signal Name KEY5 HPS RESET N cold reset io the bs Ethernet PHY and zan host device Active low input which resets all HPS logics that can be reset KEY7 HPS WARM RST N Warm reset to the HS bl
29. 015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM Qsys The data transferred through Lightweight HPS to FPGA Bridge is converted into Avalon MM master interface Both PIO Controller and HEX Controller work as Avalon MM slave in the system They control the associated pins to change the state of LED and HEX This is similar to a system using Nios II processor to control LED and HEX HPS FPGA Qsys LWAXI LED 9 0 LWAXI HEX 5 0 Figure 7 1 FPGA LED and HEX are controlled by HPS B LED and HEX control The Lightweight HPS to FPGA Bridge is a peripheral of HPS The software running on Linux cannot access the physical address of the HPS peripheral The physical address must be mapped to the user space before the peripheral can be accessed Alternatively a customized device driver module can be added to the kernel The entire CSR span of HPS is mapped to access various registers within that span The mapping function and the macro defined below can be reused if any other peripherals whose physical address 1s also in this span define HW REGS BASE ALT STM OFST define HW REGS SPAN 0x04000000 define HW REGS MASK HW REGS SPAN i The start address of Lightweight HPS to FPGA Bridge after mapping can be retrieved by ALT LWFPGASLVS OFST which is defined in altera hps hardware library The slave IP connected to the bridge can then be accessed through the base address and the register offset in th
30. 0904 61 20 Karaoke Venna oa E 64 S ORA Tes OS Ih kaka am nana 66 5 0 DRAM Ter cule Mena ea Na PE 69 245 T3 Box DeHmoBSIOHOE Aa AAN 0000005500 E EEEE 71 23 7 PS2 Mouse Demonstran amat maa ELE sei 13 5 8 IR Emitter LED and Receiver Demonstration XX 16 SA OS Ea da Os ea matan Tc 82 CHAPTERS EXAMPLES FOR HPS SOC siaran MAN AE 85 DE1 SoC User Manual 2 www terasic com TijasiC April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM Oo SIS leute ur INTE 85 MA Users BS BENIN hU mE 87 0 3 12C NAN an EE EEE 93 OA MUKA T a AA NA OR 96 CHAPTER7 EXAMPLES FOR USING BOTH HPS SOC AND FGPA eere 99 TA Cool LED Jud FUE osea aee UIS UE Ubri N 99 2DEI SOoC Control Panel RR uu 103 73 DEA SoC Linux Frame Butter Proje 0 cute ann nana na Ka um una 103 CHAPTER8 PROGRAMMING THE EPCS DEVICE nana anna aan 105 a Betore Programming Berinti nn nnti a an A A AN naaa 105 S Omer SOFA PIS nan AA AAA a AAA Aa 105 5 9 Write JIC File into the EPCS Device an nina un se te a A A A A ian 110 5d Frase the PERDA 61 aa ai asa MAA AA AAA 112 8 5 Nios II Boot from EPCQ Device in Quartus II v13 1 oooooooooooooo Wah 113 CHAPTERS APP EN Naaah 114 ENSURE ai Ns naat 114 02 Copa Aa eee ee E en NEM MEME MUI EE 114 DE1 SoC User Manual 3 www terasic com TijasiC April 2 2015 www terasic com Chapter 1 DE1 SoC Development Kit The DE1 SoC Development Kit presents a robust hardware design platf
31. 2 25us 1 le 562 25us vi P 562 25us pi 2 25ms 1 125ms Figure 5 13 Duration of logical 1 and logical 0 Figure 5 14 shows a frame of the protocol Protocol sends a lead code first which is a 9ms leading pulse burst followed by a 4 5ms window The second inversed data is sent to verify the accuracy of the information received A final 562 5us pulse burst is sent to signify the end of message transmission Because the data is sent in pair original and inverted according to the protocol the overall transmission time is constant 000000001 1 1 1 1 1 1 1 O1 1 01 0 1 O 1 00 1 O 1 0 LSB LSB LSB LSB 9ms 4 5ms Address Address Logical Inverse Command Command Logical Inverse qe ss E gt 27ms did 27ms 67 5ms Figure 5 14 Typical frame of NEC protocol Note The signal received by IR Receiver is inverted For instance if IR TX Controller sends a lead code 9 ms high and then 4 5 ms low IR Receiver will receive a 9 ms low and then 4 5 ms high lead code asic DE1 SoC User Manual 78 www terasic com kidd asic Apr i 2 2015 JA DTE RYA UNIVERSITY PROGRA M B IR Remote When a key on the remote controller show in Figure 5 15 is pressed the remote controller will emit a standard frame as shown in Table 5 5 The beginning of the frame is the lead code which represents the start bit followed by the key related information The last bit end code represents the end of
32. 32 t C ALT GPIO SWPORTA DR ADDR amp uint32 t HW REGS MASK BIT LED The following statement is used to read the content of gpio ext porta register The bit mask is used to check the status of the key alt read word virtual base Cuint32 t ALT GPIOI EXT PORTA ADDR amp uint32 t HW REGS MASK asic DE1 SoC User Manual 92 www terasic com kidd 25 C Apr i 2s 2015 UNIVERSITY PROGRAM B Demonstration Source Code e Build tool Altera SoC EDS V 13 1 e Project directory Demonstration SoC hps_gpio e Binary file hps gpio e Build command make make clean to remove all temporal files e Execute command hps gpio B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEI SoC board and the host PC e Copy the executable file hps gpio into the microSD card under the home root folder in Linux e Insert the booting micro SD card into the DEI SoC board e Power on the DEI SoC board e Launch PuTTY and establish connection to the UART port of Putty Type root to login Altera Yocto Linux e Type hps gpio in the UART terminal of PuTTY to start the program e HPS LED will flash twice and users can control the user LED with push button e Press HPS KEY to light up HPS LED e Press CTRL C to terminate the application 6 3 I2C Interfaced G sensor This demonstration shows how to control the G sensor by accessing its registers through the bui
33. 4 GPIO Connection 0 25 GPIO Connection 0 26 GPIO Connection 0 27 GPIO Connection 0 28 GPIO Connection 0 29 GPIO Connection 0 30 GPIO Connection 0 31 GPIO Connection 0 32 GPIO Connection 0 33 GPIO Connection 0 34 GPIO Connection 0 35 GPIO Connection 1 0 GPIO Connection 1 1 GPIO Connection 1 2 GPIO Connection 1 3 GPIO Connection 1 4 GPIO Connection 1 5 GPIO Connection 1 6 GPIO Connection 1 7 GPIO Connection 1 8 GPIO Connection 1 9 GPIO Connection 1 10 GPIO Connection 1 11 20 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com April 2 2015 JAN DTE RYA UNIVERSITY PROGRAM GPIO 1 12 PIN AH27 GPIO Connection 1 12 3 3V GPIO 1 13 PIN AJ27 GPIO Connection 1 13 3 3V GPIO 1 14 PIN AK29 GPIO Connection 1 14 3 3V GPIO 1 15 PIN AK28 GPIO Connection 1 15 3 3V GPIO 1 16 PIN AK27 GPIO Connection 1 16 3 3V GPIO 1 17 PIN AJ26 GPIO Connection 1 17 3 3V GPIO 1 18 PIN AK26 GPIO Connection 1 18 3 3V GPIO 1 19 PIN AH25 GPIO Connection 1 19 3 3V GPIO 1 20 PIN AJ25 GPIO Connection 1 20 3 3V GPIO 1 21 PIN AJ24 GPIO Connection 1 21 3 3V GPIO 1 22 PIN AK24 GPIO Connection 1 22 3 3V GPIO 1 23 PIN AG23 GPIO Connection 1 23 3 3V GPIO 1 24 PIN AK23 GPIO Connection 1 2
34. 4 3 3V GPIO 1 25 PIN AH23 GPIO Connection 1 25 3 3V GPIO 1 26 PIN AK22 GPIO Connection 1 26 3 3V GPIO 1 27 PIN AJ22 GPIO Connection 1 27 3 3V GPIO 1 28 PIN AH22 GPIO Connection 1 28 3 3V GPIO 1 29 PIN AG22 GPIO Connection 1 29 3 3V GPIO 1 30 PIN AF24 GPIO Connection 1 30 3 3V GPIO 1 31 PIN AF23 GPIO Connection 1 31 3 3V GPIO 1 32 PIN AE22 GPIO Connection 1 32 3 3V GPIO 1 33 PIN AD21 GPIO Connection 1 33 3 3V GPIO 1 34 PIN AA20 GPIO Connection 1 34 3 3V GPIO 1 35 PIN AC22 GPIO Connection 1 35 3 3V 3 6 4 24 bit Audio CODEC The DEI SoC board offers high quality 24 bit audio via the Wolfson WM 8731 audio CODEC Encoder Decoder This chip supports microphone in line in and line out ports with adjustable sample rate from 8 kHz to 96 kHz The WMS731 is controlled via serial I2C bus which is connected to HPS or Cyclone V SoC FPGA through an I2C multiplexer The connection of the audio circuitry to the FPGA is shown in Figure 3 20 and the associated pin assignment to the FPGA is listed in Table 3 12 More information about the WMS731 codec is available in its datasheet which can be found on the manufacturer s website or in the directory IDEI1 SOC datasheetsAudio CODEC of DEI SoC System CD www terasic com DE1 SoC User Manual 30 TijasiC April 2 2015 www terasic com JA DTE SAN Cyclone vV Soc WM8731 iacens Se XTI MCLK AUD_BCLK BCLK AUD_DACDAT DACDAT AUD DACLRCK DACLRCK AUD_ADCDAT
35. C Linux Console with framebuffer Please refer to DEI SoC Getting Started Guide about how to get the SD images and create a boot SD card DE1 SoC User Manual 104 www terasic com asic April 2 2015 www terasic com Chapter 8 Programming the EPCS Device This chapter describes how to program the guad serial configuration EPCS device with Serial Flash Loader SFL function via the JTAG interface Users can program EPCS devices with a JTAG indirect configuration jic file which is converted from a user specified SRAM object file sof in Quartus The sof file is generated after the project compilation is successful The steps of converting sof to jic 1n Quartus II are listed below 8 1 Before Programming Begins The FPGA should be set to AS x1 mode i e MSEL 4 0 10010 to use the quad Flash as a FPGA configuration device 8 2 Convert SOF File to JIC File 1 Choose Convert Programming Files from the File menu of Quartus II as shown in Figure 8 1 DE1 SoC User Manual 105 www terasic com asic April 2 2015 www terasic com UNIVERSITY PROG M Edit View Project Assignments Process L New Ctrl4N EE Open Ctrl Close Ctrl F4 id New Project Wizard BS Open Project Ctrl Save Project Close Project al Save Ctrl 5 Save As g Save Al Ctrl Shift s File Properties Create Update k Convert Programming Files Figure 8 1 File menu of Quartus II 2 Selec
36. C of the DEI SoC System CD Please refer to Chapter 5 Running Linux on the DE1 SoC board from the DEI SoC Getting Started Guide pdf to run Linux on DEI SoC board B Installation of the Demonstrations To install the demonstrations on the host computer Copy the directory Demonstrations into a local directory of your choice Altera SoC EDS v13 1 is required for users to compile the c code project 6 1 Hello Program This demonstration shows how to develop first HPS program with Altera SoC EDS tool Please refer to My First HPS pdf from the system CD for more details The major procedures to develop and build HPS project are Install Altera SoC EDS on the host PC Create program c h files with a generic text editor Create a Makefile with a generic text editor Build the project under Altera SoC EDS DE1 SoC User Manual 85 www terasic com Sasic April 2 2015 www terasic com JA DTE RYN UNIVERSITY PROGRAM B Program File The main program for the Hello World demonstration is include lt stdio h gt int mainfint argc char targyi d printf Hello World rYn returni B 17 B Makefile A Makefile is required to compile a project The Makefile used for this demo 1s TARGET my first hps CROSS COMPILE arm linux gnueabihf CFLAGS g Wall I SOCEDS DEST ROOT ip altera hps altera hps hwlib include LDFLAGS g Wa ll CC CROSS COMPILE ace ARCH arm build
37. DR 12 PIN AJ14 SDRAM Address 12 43 3V DRAM DOQ 0 PIN AK6 SDRAM Data 0 33V DRAM DOQ 1 PIN AJ7 SDRAM Data 1 3 39V DRAM DOQ 2 PIN AK7 SDRAM Data 2 43 3V DRAM DQ 3 PIN AK8 SDRAM Data 3 33V DRAM DQ 4 PIN AK9 SDRAM Data 4 43 3V DRAM DQ 5 PIN AG10 SDRAM Data 5 3 3V www terasic com DE1 SoC User Manual 39 TijasiC April 2 2015 www terasic com UNIVERSITY PROGRAM DRAM DQ 6 PIN AK11 SDRAM Data 6 3 3V DRAM DQ 7 PIN AJ11 SDRAM Data 7 3 3V DRAM DQ 8 PIN AH10 SDRAM Data 8 3 3V DRAM DQ 9 PIN AJ10 SDRAM Data 9 3 3V DRAM DQ 10 PIN AJ9 SDRAM Data 10 3 3V DRAM DQ 11 PIN AH9 SDRAM Data 11 3 3V DRAM DQ 12 PIN AH8 SDRAM Data 12 3 3V DRAM DQ 13 PIN AH7 SDRAM Data 13 3 3V DRAM_DQ 14 PIN AJ6 SDRAM Data 14 3 3V DRAM DQ 15 PIN AJ5 SDRAM Data 15 3 3V DRAM BA 0 PIN AF13 SDRAM Bank Address 0 3 3V DRAM BAH PIN AJ12 SDRAM Bank Address 1 3 3V DRAM LDOM PIN AB13 SDRAM byte Data Mask 0 3 3V DRAM UDOM PIN AK12 SDRAM byte Data Mask 1 3 3V DRAM RAS N PIN AE13 SDRAM Row Address Strobe 3 3V DRAM CAS N PIN AF11 SDRAM Column Address Strobe 3 3V DRAM CKE PIN AK13 SDRAM Clock Enable 3 3V DRAM CLK PIN AH12 SDRAM Clock 3 3V DRAM WE N PIN AA13 SDRAM Write Enable 3 3V DRAM CS N PIN AG11 SDRAM Chip Select 3 3V 3 6 11 PS 2 Serial Port The DEI SoC board comes with a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 28 shows the connection of PS 2 circuit to the FPGA Users can use the PS 2 ke
38. GPIO Interface Cortex A9 Subsystem Core Generic Interrupt Controller gpioO Intr In asic DE1 SoC User Manual 88 www terasic com kidd asic Apr i 2 2015 JAN DTE RYA UNIVERSITY PROGRAM B GPIO Register Block The behavior of I O pin 1s controlled by the registers 1n the register block There are three 32 bit registers in the GPIO controller used in this demonstration The registers are pio swporta dr write output data to output I O pin pio swporta ddr configure the direction of I O pin pio ext porta read input data of I O input pin The gpio swporta ddr configures the LED pin as output pin and drives it high or low by writing data to the gpio swporta dr register The first bit least significant bit of gpio swporta dr controls the direction of first IO pin in the associated GPIO controller and the second bit controls the direction of second IO pin in the associated GPIO controller and so on The value 1 in the register bit indicates the I O direction is output and the value 0 in the register bit indicates the I O direction is input The first bit of gpio swporta dr register controls the output value of first I O pin in the associated GPIO controller and the second bit controls the output value of second I O pin in the associated GPIO controller and so on The value 1 in the register bit indicates the output value is high and the value 0 indicates the output value is low The st
39. HPS GPIO 0 Header MI 7 Segment x 6 t Iv iv Switch x 10 IR TXJRX Video In VI ADC VI PS2 C Prefix Name GPIO 1 Header Prefix Name Load Setting Exit Figure 4 4 System configuration group B GPIO Expansion If users connect any Terasic GPIO based daughter card to the GPIO connector s on DEI SoC the DEI SoC System Builder can generate a project that include the corresponding module as shown in Figure 4 5 It will also generate the associated pin assignment automatically including pin name pin location pin direction and I O standard Tasic DE1 SoC User Manual 57 www terasic com www terasic com April 2 2015 UNIVERSITY PROGRAM DE1 SoC V1 0 0 SNB S RYA Hasic System Configuratio Project Name DEI SOC UNIVERSITY PROGRAM www terasic com DE1 SoC FPGA Board MI CLOCK Mi 7 Seqment x 6 iV LEDx 10 MI Switch x 10 4 Button x 4 v IR TXIRX iV VGA Mi Video In Wi Audio v ADC 4 SDRAM 32MB VI PS2 7 HPS GPIO 0 Header D5M 5M Pixel Camera Prefix Name GPIO 1 Header Save Setting None Prefix Name Load Setting Figure 4 5 GPIO expansion group The Prefix Name is an optional feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank B Project Setting Management The DEI SoC System Builder also provides the option to load a setting or save users current
40. Hz Controller Figure 3 13 Block diagram of the clock distribution on DE1 SoC Table 3 5 Pin Assignment of Clock Inputs PIN_AF14 50 MHz clock input PIN_AA16 50 MHz clock input 3 PINY26 50 MHz clock input PIN K19 50 MHz clock input CLOCKA 50 HPS CLOCKi 25 PIN D25 25 MHz clock input HPS CLOCK2 25 PIN F25 25 MHz clock input 3 www terasic com DE1 SoC User Manual 22 TadasiC April 2 2015 www terasic com 3 6 Peripherals Connected to the FPGA This section describes the interfaces connected to the FPGA Users can control or monitor different interfaces with user logic from the FPGA 3 6 1 User Push buttons Switches and LEDs The board has four push buttons connected to the FPGA as shown in Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA Schmitt trigger circuit is implemented and act as switch debounce in Figure 3 15 for the push buttons connected The four push buttons named KEYO KEY1 KEY2 and KEY3 coming out of the Schmitt trigger device are connected directly to the Cyclone V SoC FPGA The push button generates a low logic level or high logic level when it is pressed or not respectively Since the push buttons are debounced they can be used as clock or reset inputs in a circuit VCC3P3 KEYO KEY1 E ms VAN D E RYAN KEY2 e W15 oneS V SoC Y16 Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA DE1 SoC User Manual 23
41. Hz clock source is not working If LEDRI failed to remain ON after approximately 8 seconds the SDRAM test is NG Press KEYO again to repeat the SDRAM test DE1 SoC User Manual 70 www terasic com Kadasic TIE T www terasic com April 2 2015 Table 5 3 Status of LED Indicators Name Description LEDRO Reset LEDR1 ON if the test is PASS after releasing KEYO LEDR2 Blinks 5 6 TV Box Demonstration This demonstration turns DEI SoC board into a TV box by playing video and audio from a DVD player using the VGA output audio CODEC and the TV decoder on the DE1 SoC board Figure 5 9 shows the block diagram of the design There are two major blocks in the system called PC AV Config and TV to VGA The TV to VGA block consists of the ITU R 656 Decoder SDRAM Frame Buffer YUVA22 to YUV444 YCbCr to RGB and VGA Controller The figure also shows the TV decoder ADV7180 and the VGA DAC ADV7123 chip used The register values of the TV decoder are used to configure the TV decoder via the DC AV Config block which uses the I2C protocol to communicate with the TV decoder The TV decoder will be unstable for a time period upon power up and the Lock Detector block is responsible for detecting this instability The ITU R 656 Decoder block extracts YcrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV decoder It also generates a data valid control signal which indicates the valid period of data output De interlacing
42. IO 0 5 GPIO 0 6 GPIO 0 7 GPIO 0 8 GPIO 0 9 GPIO 0 10 GPIO 0 11 GPIO 0 12 GPIO 0 13 GPIO 0 14 GPIO 0 15 GPIO 0 16 GPIO 0 17 GPIO 0 18 GPIO 0 19 GPIO 0 20 GPIO 0 21 GPIO 0 22 GPIO 0 23 GPIO 0 24 GPIO 0 25 GPIO 0 26 GPIO 0 27 GPIO 0 28 GPIO 0 29 GPIO 0 30 GPIO 0 31 GPIO 0 32 GPIO 0 33 GPIO 0 34 GPIO 0 35 GPIO 1 0 GPIO 1 1 GPIO 1 2 GPIO 1 3 GPIO 1 4 GPIO 1 5 GPIO 1 6 GPIO 1 7 GPIO 1 8 GPIO 1 9 GPIO 1 10 GPIO 1 11 www terasic com PIN AK16 PIN AK18 PIN AK19 PIN AJ19 PIN AJ17 PIN AJ16 PIN AH18 PIN AH17 PIN AG16 PIN AE16 PIN AF16 PIN AG17 PIN AA18 PIN AA19 PIN AE17 PIN AC20 PIN AH19 PIN AJ20 PIN AH20 PIN AK21 PIN AD19 PIN AD20 PIN AE18 PIN AE19 PIN AF20 PIN AF21 PIN AF19 PIN AG21 PIN AF18 PIN AG20 PIN AG18 PIN AJ21 PIN AB17 PIN AA21 PIN AB21 PIN AC23 PIN AD24 PIN AE23 PIN AE24 PIN AF25 PIN AF26 PIN AG25 PIN AG26 PIN AH24 DE1 SoC User Manual GPIO Connection 0 41 GPIO Connection O 5 GPIO Connection O 6 GPIO Connection 0 7 GPIO Connection O 8 GPIO Connection O 9 GPIO Connection O 10 GPIO Connection 0 11 GPIO Connection 0 12 GPIO Connection 0 13 GPIO Connection 0 14 GPIO Connection 0 15 GPIO Connection 0 16 GPIO Connection 0 17 GPIO Connection 0 18 GPIO Connection O 19 GPIO Connection 0 20 GPIO Connection 0 21 GPIO Connection 0 22 GPIO Connection 0 23 GPIO Connection 0 2
43. K 25 XI KSZ9021RN RJ45 Figure 3 32 Connections between the HPS and Gigabit Ethernet DE1 SoC User Manual 44 www terasic com TijasiC April 2 2015 www terasic com Table 3 24 Pin Assignment of Gigabit Ethernet PHY Signal Name FPGA Pin No Description VO Standard HPS ENET TX EN PIN A20 GMII and MII transmit enable 3 3V HPS ENET TX DATA 0 PIN F20 MII transmit data 0 3 3V HPS ENET TX DATA 1 PIN J19 MII transmit data 1 3 3V HPS ENET TX DATA 2 PIN F21 MII transmit data 2 3 3V HPS ENET TX DATA 3 PIN F19 MII transmit data 3 3 3V HPS ENET RX DV PIN K17 GMII and MII receive data valid 3 3V HPS ENET RX DATAIOJ PIN A21 GMII and MII receive data 0 3 3V HPS ENET RX DATA 1 PIN B20 GMII and MII receive data 1 3 3V HPS ENET RX DATA 2 PIN B18 GMII and MII receive data 2 3 3V HPS ENET RX DATA 3 PIN D21 GMII and MII receive data 3 3 3V HPS ENET RX CLK PIN G20 GMII and MII receive clock 3 3V HPS ENET RESET N PIN E18 Hardware Reset Signal 3 3V HPS ENET MDIO PIN E21 Management Data 3 3V HPS ENET MDC PIN B 1 Management Data Clock Reference 3 3V HPS ENET INT N PIN C19 Interrupt Open Drain Output 3 3V HPS ENET GTX CLK PIN H19 GMII Transmit Clock 3 3V There are two LEDs green LED LEDG and yellow LED LEDY which represent the status of Ethernet PHY KSZ9021RNI The LED control signals are connected to the LEDs on the RJ45 connector The state and definition of LEDG and LEDY are listed in Table 3 25 For instance the co
44. N OFF O 9 ir ase 64MB SDRAM Accelerometer ADC ADC Header 2x7 LTC 7 Segment Display Expansion Header LED x10 HPS User LED IR out IR in Switch x10 Button x4 WARM RST HPS User Button HPS RST Figure 2 1 DE1 SoC development board top view PO14080081 1422F 2 Am nana nooo FPGA Configuration Mode Switch EPCS 128MB m E a a E LEE E EE E LEE STELE TEET LIII NM Daaa Figure 2 2 De1 SoC development board bottom view Tasic DE1 SoC User Manual www terasic com 7 www terasic com April 2 2015 UNIVERSITY PROGRAM The DEI SoC board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board B FPGA e Altera Cyclone V SE 5CSEMASE31CON device e Altera serial configuration device EPCS 128 e USB Blaster II onboard for programming JTAG Mode e 64MB SDRAM 16 bit data bus e 4 push buttons e 10 slide switches e 10 red user LEDs e Six 7 segment displays e Four SOMHz clock sources from the clock generator e 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 8 bit high speed triple DACs with VGA out connector e TV decoder NTSC PAL SECAM and TV in connector e PS 2 mouse keyboard connector e R receiver and IR emitter e Two 40 pin expansion header with diode protection e A D converter 4 pin SPI interface with FPGA B HPS
45. PS RC CONTROL DE1 SoC User Manual 97 www terasic com asic April 2 2015 www terasic com UNIVERSITY PROGRAM B 2C Driver The procedures to read register value from TV Decoder by the existing I2C bus driver in the system are Set HPS DC CONTROL high for HPS to access I2C bus Open the I2C bus driver dev i2c 0 file open dev i2c 0 O_RDWR Specify the I2C address 0x20 of ADV7180 10ctl file RC SLAVE 0x20 Read or write registers set HPS I2C CONTROL low to release the I2C bus B Demonstration Source Code e Build tool Altera SoC EDS v13 1 e Project directory Demonstration SoC hps 12c switch e Binary file i2c switch e Build command make make clean to remove all temporal files e Execute command 12c switch B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Copy the executable file i2c switch into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEI SoC board e Power on the DEI SoC board e Launch PuTTY to establish connection to the UART port of DEI SoC borad Type root to login Yocto Linux e Execute i2c switch in the UART terminal of PuTTY to start the I2C MUX test e The demo program will show the result in the Putty as shown in Figure 6 10 Figure 6 10 Terminal output of the I2C MUX Test Demonstration e Press CTRL C to terminate the program DE1 SoC
46. S DDR3 Data 9 HPS DDR3 Data 10 HPS DDR3 Data 11 HPS DDR3 Data 12 HPS DDR3 Data 13 HPS DDR3 Data 14 HPS DDR3 Data 15 HPS DDR3 Data 16 HPS DDR3 Data 17 HPS DDR3 Data 18 HPS DDR3 Data 19 HPS DDR3 Data 20 HPS DDR3 Data 21 HPS DDR3 Data 22 41 SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class I SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class l SSTL 15 Class I SSTL 15 Class SSTL 15 Class SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I www terasic com April 2 2015 JAN DTE RYA UNIVERSITY PROGRAM HPS DDR3 DQ 23 HPS DDR3 DQ 24 HPS DDR3 DQ 25 HPS DDR3 DQ 26 HPS DDR3 DQ 27 HPS DDR3 Daj28 HPS DDR3 DQ 29 HPS DDR3 DQ 30 HPS DDR3 DQ 31 HPS DDR3 DOS n 0 HPS DDR3 DOS n 1 HPS DDR3 DOS n 2 HPS DDR3 DOS n 3 HPS DDR3 DOS p 0 HPS DDR3 DOS p 1 HPS DDR3 DOS p 2 HPS DDR3 DOS p 3 HPS DDR3 ODT HPS DDR3 RAS n HPS DDR3 RESET
47. Select the correct jic file 5 Erase the EPCS device by clicking the corresponding Erase box A factory default SFL image will be loaded as shown in Figure 8 8 DE1 SoC User Manual 112 WWW terasic com LijasiC April 2 2015 www terasic com Usercode 00000000 lt none gt Factory default enhanced SCSEMAS DO C7SAEC DOC 79AEC iD output file jic i EPCS128 98823544 b ES Al Save File Figure 8 8 Erase the EPCS device in Quartus II Programmer 6 Click Start to erase the EPCS device 8 5 Nios ll Boot from EPCQ Device in Quartus II v13 1 There is a known problem in Quartus II software that the Quartus Programmer must be used to program the EPCO device on DEI SoC board Please refer to Altera s website here with details step by step DE1 SoC User Manual 113 www terasic com Cijasic April 2 2015 www terasic com Chapter 9 Appendix 9 1 Revision History Change Log Initial Version Preliminary Add Chapter 5 and Chapter 6 Modify Chapter 3 Add Chapter 3 HPS Modify Chapter 3 Modify Chapter 8 Modify section 3 3 1 Add Sectiom 7 3 2 Modify Figure 3 2 Modify Figure 3 2 Modify Figure 5 5 descriptions of remote controller Copyright O 2015 Terasic Technologies All rights reserved DE1 SoC User Manual 114 www terasic com asic April 2 2015 www terasic com
48. TV decoder U4 is 0x40 0x41 The pin assignment of TV decoder is listed in Table 3 17 More information about the ADV7180 is available on the manufacturer s website or in the directory NDE1 SOC datasheets Video Decoder of DEI SoC System CD ADV7180 TD DATA 7 0 TD VS TD HS J6 e AIN1 PP C J ey TD RESET N Z 4 Soc I2C SCLK I2C SDAT OSC 28MHz Y1 Figure 3 24 Connections between the FPGA and TV Decoder Table 3 17 Pin Assignment of TV Decoder Signal Name FPGA Pin No Description O Standard TD DATA 0 PIN D2 TV Decoder Data 0 3 3V TD DATA 1 PIN B1 TV Decoder JData 1 3 3V TD DATA 2 PIN E2 TV Decoder Data 2 3 3V TD DATA 3 PIN B2 TV Decoder BData 3 3 3V TD DATA 4 PIN D1 TV Decoder Data 4 3 3V TD DATA 5 PIN E1 TV Decoder Data 5 3 3V TD DATA 6 PIN C2 TV Decoder Data 6 3 3V TD DATA 7 PIN B3 TV Decoder Data 7 3 3V TD HS PIN A5 TV Decoder H SYNC 3 3V TD VS PIN A3 TV Decoder V SYNC 3 3V TD CLK27 PIN H15 TV Decoder Clock Input 3 3V TD RESET N PIN F6 TV Decoder Reset 3 3V l2C SCLK PIN J12 or PIN E23 I2C Clock 3 3V I2C SDAT PIN K12 or PIN_C24 I2C Data 3 3V www terasic com DE1 SoC User Manual 36 TijasiC April 2 2015 www terasic com 3 6 8 IR Receiver The board comes with an infrared remote control receiver module model IRM V538 TR1 whose datasheet is provided in the directory Datasheets IR Receiver and Emitter of DEI SoC system CD The remote controller included in the kit has an encoding chip
49. The program will display the test progress and result as shown in Figure 5 7 DE1 SoC User Manual 68 www terasic com asic April 2 2015 www terasic com UNIVERSITY PROGRAM ES Alters NiosI EDS 13 0 gced ella esa Using cable DE Sot USB 1 device 1 instance HxBHH Resetting and pausing target processor OK Initializing CPU cache if present OK Downloaded 61KB in A is Verified OK Starting processor at address Hx2BHH2H1EB4 nios2 terminal connected to hardware target using JIAG UART on cable niosZ terminal DE SoC I USB 1 1 device 1 instance H nios2 terminal Use the IDE stop button or Ctrl C to terminate SDRAM Test Size 64MB CPU Clock 1B8BHBBHBBBHBBH Press any KEY to start test IKEYB for continued test gt SDRAM Testing Iteration 1 urite 1H 26 30 46 Sk bak Yz Bak Hz 106z read uerifu lak 26 38 48 5Hz Figure 5 7 Display of progress and result for the SDRAM test in Nios II 5 5 SDRAM Test in Verilog DEI SoC system CD offers another SDRAM test with its test code written in Verilog HDL The memory size of the SDRAM bank tested 1s still 64MB B Function Block Diagram Figure 5 8 shows the function block diagram of this demonstration The SDRAM controller uses 50 MHz as a reference clock and generates 100 MHz as the memory clock RW Test Test Sdram Es Conrtoller Test 4 Control po KEYO Logic Process Gin Figure 5 8 Block diagram of the SDRAM test in Verilog DE1
50. V 3 3V 3 3V www terasic com April 2 2015 3 6 3 2x20 GPIO Expansion Headers The board has two 40 pin expansion headers Each header has 36 user pins connected directly to the Cyclone V SoC FPGA It also comes with DC 45V VCC5 DC 3 3V VCC3P3 and two GND pins The maximum power consumption allowed for a daughter card connected to one or two GPIO ports is shown in Table 3 10 Table 3 10 Voltage and Max Current Limit of Expansion Header s Supplied Voltage Max Current Limit 5V 1A 3 3V 1 5A Each pin on the expansion headers is connected to two diodes and a resistor for protection against high or low voltage level Figure 3 19 shows the protection circuitry applied to all 2x36 data pins Table 3 11 shows the pin assignment of two GPIO headers VCC3P3 JP1 ANU S RYAN Cyclone v Soc GPIO_0 35 0 db 0 0 0 0000000000000000 db NN M MN NE NEN E NM E NE MN EM NE E E EM M NE EZ Figure 3 19 Connections between the GPIO header and Cyclone V SoC FPGA Table 3 11 Pin Assignment of Expansion Headers Signal Name FPGA Pin No Description YO Standard GPIO O 0 PIN AC18 GPIO Connection O 0 3 3V GPIO 0 1 PIN Y17 GPIO Connection O 1 3 3V GPIO 0 2 PIN AD17 GPIO Connection 0 2 3 3V GPIO 0 3 PIN_Y18 GPIO Connection 0 3 3 3V Tasic DE1 SoC User Manual 28 www terasic com April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM GPIO 0 4 GP
51. X Controller When KEYO is pressed data test pattern generator will generate data to the IR TX Controller continuously When IR TX Controller is active it will format the data to be compatible with NEC IR transmission protocol and send it out through the IR emitter LED The IR receiver will decode the received data and display it on the six HEXs Users can also use a remote to send data to the IR Receiver The main function of IR TX RX controller and IR remote in this demonstration is described in the following sections B IR TX Controller Users can input 8 bit address and 8 bit command into the IR TX Controller The IR TX Controller will encode the address and command first before sending it out according to NEC IR transmission protocol through the IR emitter LED The input clock of IR TX Controller should be 50MHz The NEC IR transmission protocol uses pulse distance to encode the message bits Each pulse burst is 562 5us in length with a carrier frequency of 38kHz 26 3us Figure 5 13 shows the duration of logical 1 and 0 Logical bits are transmitted as follows e Logical 0 a 562 5us pulse burst followed by a 562 5us space with a total transmit time of 1 125ms DE1 SoC User Manual 71 www terasic com Tijasic April 2 2015 www terasic com UNIVERSITY PROGRAM e Logical 1 a 562 5us pulse burst followed by a 1 6875ms space with a total transmit time of 2 25ms Logical 1 Logical 0 y AA e os P 56
52. X1 High byte of DATA Key Code HEXO Low byte of DATA Key Code 5 9 ADC Reading This demonstration illustrates steps to evaluate the performance of the 8 channel 12 bit A D Converter ADC7928 The DC 5 0V on the 2x5 header is used to drive the analog signals by a trimmer potentiometer The voltage can be adjusted within the range between 0 and 5 0V The 12 bit voltage measurement is displayed on the NIOS II console Figure 5 19 shows the block diagram of this demonstration If the input voltage is 2 5V 2 5V a pre scale circuit can be used to adjust it to 0 5 V DE1 SoC User Manual 82 www terasic com asic April 2 2015 www terasic com FPGA A QSYS 50 MHz H 3 f oqe 1 euuooJe ju WajasAS 1 ER dab ADC Controller Mp 20 convener 2x5 Header Figure 5 19 Block diagram of ADC reading Figure 5 20 depicts the pin arrangement of the 2x5 header This header is the input source of ADC convertor in this demonstration Users can connect a trimmer to the specified ADC channel ADC INO ADC INY7 that provides voltage to the ADC convert The FPGA will read the associated register in the convertor via serial interface and translates it to voltage value to be displayed on the Nios II console J15 ADC INO ADC IN2 VCC5 Q ADC IN1 ADC IN3 ADC IN4 ADC IN6 ADC IN5 ADC IN7 2x5 Box Header Figure 5 20 Pin distribution of the 2x5 Header for
53. ate Machine block The input clock should be 50MHz IR Signal Code s Code Detector Shift Register State Machine Figure 5 17 Modules in the IR Receiver controller DE1 SoC User Manual 80 www terasic com Cijasic April 2 2015 www terasic com End Code Lead Code Custom Code Figure 5 18 State shift diagram of State Machine block Demonstration Source Code e Project directory DEI SoC IR e Bitstream used DEI SOC IR sof Demonstration Batch File Demo batch file directory DEI SoC IR Memo batch The folder includes the following files e Batch file DEI SoC IR bat e FPGA configuration file DEI SOC IR sof Demonstration Setup File Locations and Instructions e Load the bitstream into the FPGA by executing DEI SoC IR demo batch DEI SoC IR bat e Keep pressing KEY 0 to enable the pattern to be sent out continuously by the IR TX Controller e Observe the six HEXs according to Table 5 6 e Release KEY 0 to stop the IR TX e Point the IR receiver with the remote and press any button DE1 SoC User Manual 81 www terasic com Cijasic April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM e Observe the six HEXs according to Table 5 6 Table 5 6 Detailed Information of the Indicators Indicator Name Description HEX5 Inversed high byte of DATA Key Code HEX4 Inversed low byte of DATA Key Code HEX3 High byte of ADDRESS Custom Code HEX2 Low byte of ADDRESS Custom Code HE
54. atus of KEY can be queried by reading the value of gpio ext porta register The first bit represents the input status of first IO pin in the associated GPIO controller and the second bit represents the input status of second IO pin in the associated GPIO controller and so on The value 1 in the register bit indicates the input state is high and the value 0 indicates the input state is low B GPIO Register Address Mapping The registers of HPS peripherals are mapped to HPS base address space OXFC000000 with 64K B size The registers of the GPIOI controller are mapped to the base address OXFF708000 with 4KB size and the registers of the GPIO2 controller are mapped to the base address OXFF70A000 with 4KB size as shown in Figure 6 3 DE1 SoC User Manual 80 www terasic com asic April 2 2015 www terasic com HPS Identifier HPS Access R W Description Address map for the HHP HPS system domain Reserved o 0 O oo QSPI Flash Controller Module QSPIREGS OxFF705000 OxFF705100 IR et AC P IL anper K AC PI Reserved OxFF708080 Reserved 3 1 OxFF709080 O Reserved F XFF7UAURO Ox FFSSOOQQ AXI Slave EMAC Module EMACI OxFF702000 Figure 6 3 GPIO address map B Software API Developers can use the following software API to access the register of GPIO controller open open memory mapped device driver mmap map physical memory to
55. board via JTAG interface Launch SOC Kit System Builder Launch Quartus II and Open Project Create New SOC Kit System Builder Add User Design Logic Project Generate Quartus II Project and Document Compile to generate SOF Configure FPGA Figure 4 1 Design flow of building a project from the beginning to the end 4 3 Using DE1 SoC System Builder This section provides the procedures in details on how to use the DEI SoC System Builder DE1 SoC User Manual 54 WWW terasic com TijasiC April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM B Install and Launch the DE1 SoC System Builder The DEI SoC System Builder is located in the directory Tools SystemBuilder of the DEI SoC System CD Users can copy the entire folder to a host computer without installing the utility A window will pop up as shown in Figure 4 2 after executing the DE1 SoC SystemBuilder exe on the host computer DE1 SoC V1 0 0 System Configuration Zjas c ATERA Project Name PROGRAM DEI SOC DE1 SoC FPGA Board VI CLOCK 4 7 Segment x 6 MV LEDx 10 4 Switch x 10 MI Button x 4 WI IR TXIRX VIVGA Mi Video In Wi Audio v ADC 4 SDRAM 32MB Wi PS2 PF HPS GPIO 0 Header None Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 2 The GUI of DE1 SoC System Builder B Enter Project Name Enter the project name in the circled area as shown i
56. erasic com kidd asic April 2 2015 AN S RYAN UNIVERSITY PROGRAM ti Convert Programming File S Conversion setup files Save Gmn Seng Output programming file Programming fle type Eo File name D foutput file jic Advanced Remote Local update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd File Data area Start Address Add Hex Data 4 SOF Data Add Device DE1 5oC Default sof Remove Up Down Properties Figure 8 5 Convert Programming Files page after selecting the device 8 3 Write JIC File into the EPCS Device When the conversion of SOF to JIC file is complete please follow the steps below to program the EPCS device with the jic file created in Quartus II Programmer 1 Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select the correct device Both FPGA device and HPS should be detected as shown in Figure 8 6 DE1 SoC User Manual 110 www terasic com Cijasic April 2 2015 www terasic com PANO TS RYN UNIVERSITY PROGRAM 4 Double click the green rectangle region shown in Figure 8 6 and the Select New Programming File page will appear Select the jic file to be programmed 5 Program the EPCS device by clicking the correspondin
57. ercode Program Verify Blank Examine ipii Start Configure alli Stop lt none gt SOCVHPS 00000000 lt none gt cee Lanononor M F H NH F ME Select All Ctrl A X Delete B eree 70 I Change File ix Save File gt Gal Save File Add IPS File 39 Add D Change IPS File i Delete IPS File ADER PPP 7 i TDI PR Programming File Yu Down P Change PR Programming File Delete PR Programming File SOCVHPS TDO Attach Flash Device S Change Flash Device Delete Flash Device Z Add Device f up a a Kia Figure 3 6 Open the sof file to be programmed into the FPGA device 5 Select the sof file to be programmed as shown in Figure 3 7 ip Select New Programming File RT A demo batch hc output kv y VGA DATA Tan DEL soc Defeultsof Files of type Programming Files sof pof jam jbc ekp jic Figure 3 7 Select the sof file to be programmed into the FPGA device DE1 SoC User Manual 17 www terasic com Tijasic April 2 2015 www terasic com UNIVERSITY PROGRAM 6 Click Program Configure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 8 x Programmer Chain1 cdf File Edit View Processing Tools Window Help 57 2 Hardware Setup DE SoC USB 1 Mode JTAG Enable real time ISP to allow background programming for MAX II and MAX V devices m File Device Chec
58. ese IPs For instance the base address of the PIO slave IP in this system is 0x0001 0040 the direction control register offset is 0x01 and the data register offset is 0x00 The following statement is used to retrieve the base address of PIO slave IP h2p Iw led addr virtual base unsigned long ALT LWFPGASILVS OFST LED PIO BASE amp unsigned long HW REGS MASK DE1 SoC User Manual 100 www terasic com asic April 2 2015 www terasic com Considering this demonstration only needs to set the direction of PIO as output which is the default direction of the PIO IP the step above can be skipped The following statement is used to set the output state of the PIO alt write word h2p Iw led addr Mask The Mask in the statement decides which bit 1n the data register of the PIO IP is high or low The bits in data register decide the output state of the pins connected to the LEDs The HEX controlling part is similar to the LED Since Linux supports multi thread software the software for this system creates two threads One controls the LED and the other one controls the HEX The system calls pthread create which is called 1n the main function to create a sub thread to complete the job The program running in the sub thread controls the LED flashing in a loop The main thread in the main function controls the digital shown on the HEX that keeps changing in a loop The state of LED and HEX state change simultaneously when
59. g Program Configure box A factory default SFL image will be loaded as shown in Figure 8 7 6 Click Start to program the EPCS device Wp Programmer Chain3 cdf File Edit View Processing Tools Window Help 5 E Vode CJ Enable real time ISP to allow background programming for MAX II and MAX V devices Checksum Usercode cu Start 00000000 lt none gt 00000000 lt none gt giu Stop Delete Mic e File Ma Change File LA Save File 23 Add Device Tu Up Down Figure 8 6 Two devices are detected in the Guartus II Programmer DE1 SoC User Manual 111 www terasic com Cijasic April 2 2015 www terasic com Device Checksum Usercode Program Verify Blank Configure Check WES lt none gt SOCVHPS 00000000 lt none gt a Stop Factory default enhanced SCSEMAS OOCTSAEC OQOCTSAEC ET m ID foutput file jic EPCS128 988235A4 E J amp Delete ue Change File AD Save File Figure 8 7 Quartus II programmer window with one jic file 8 4 Erase the EPCS Device The steps to erase the existing file in the EPCS device are 1 Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 4 Double click the green rectangle region shown in Figure 8 6 and the Select New Programming File page will appear
60. ide e NTSC output e 60Hz refresh rate e 4 3 aspect ratio e Non progressive video DE1 SoC User Manual T2 www terasic com Sadasic s www terasic com April 2 2015 UNIVERSITY PROGRAM e Connect the VGA output of the DEI SoC board to a VGA monitor e Connect the audio output of the DVD player to the line in port of the DEI SoC board and connect a speaker to the line out port If the audio output jacks from the DVD player are RCA type an adaptor is needed to convert to the mini stereo plug supported on the DEI SoC board e Load the bitstream into the FPGA by executing the batch file DEI SoC TV bat from the directory DEI SoC TV Memo batchX Press KEYO on the DEI SoC board to reset the demonstration VGA LCD CRT Monitor diri Video In VGA Out CVBS Output Cc mma ter L EJ CELLS E 3 miam ie amp X k iA ema 8888 gal HEEE i Ari E i ure cc Uo ME CS NET ALIS I II EI EE m ded bl bol Pot ed bal ed E Ke De Interlace Figure 5 10 Setup for the TV box demonstration ITU R 656 YUV 422 Decoder 5 7 PS 2 Mouse Demonstration A simply PS 2 controller coded in Verilog HDL is provided to demonstrate bi directional communication with a PS 2 mouse A comprehensive PS 2 controller can be developed based on it and more sophisticated functions can be implemented such as setting the sampling rate or resolution which needs to transfer two data bytes at once More informati
61. ile amp Add Device fiw Piom Figure 3 3 Detect FPGA device in JTAG mode 2 Select detected device associated with the board as circled in Figure 3 4 Figure 3 4 Select 5CSEMA5 device 3 Both FPGA and HPS are detected as shown in Figure 3 5 DE1 SoC User Manual 15 www terasic com Tijasic April 2 2015 www terasic com JA DTE RYA UNIVERSITY PROGRAM ip Programmer Chain cdf E Hardware Setup EU Vode E Enable real time ISP to allow background programming for MAX II and MAX V devices Checksum Usercode bli Start wW stp 5 00000000 meum 00000000 none 3 Auto Detect X Delete au Add File Big gt Change File Ab Save File qu Up Jl Down Figure 3 5 FPGA and HPS detected in Quartus programmer 4 Right click on the FPGA device and open the sof file to be programmed as highlighted in Figure 3 6 DE1 SoC User Manual 16 www terasic com Tijasic April 2 2015 www terasic com ANU S RYAN UNIVERSITY PROGRAM ER x Programmer Chain1 cdf T aa Smm c File Edit View Processing Tools Window Help 5 Search altera com aturan ai Mode Em 4 CJ Enable real time ISP to allow background programming for MAX II and MAX V devices File Device Checksum Us
62. is design constraints file sdc e Pin assignment document htm The above files generated by the DEI SoC System Builder can also prevent occurrence of situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are e Board is damaged due to incorrect bank voltage setting or pin assignment e Board is malfunctioned because of wrong device chosen declaration of pin location or direction 1s incorrect or forgotten e Performance degradation due to improper pin assignment 4 2 Design Flow This section provides an introduction to the design flow of building a Quartus II project for DEI SoC under the DEI SoC System Builder The design flow is illustrated in Figure 4 1 DE1 SoC User Manual 53 www terasic com TijasiC April 2 2015 www terasic com UNIVERSITY PROGRAM The DEI SoC System Builder will generate two major files a top level design file v and a Quartus II setting file qsf after users launch the DEI SoC System Builder and create a new project according to their design requirements The top level design file contains a top level Verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer is used to download sof file to the development
63. ksum Usercode Program Verify Blank wis onfigur Check lla Stop lt none gt SOCVHPS 00000000 lt none gt D dei soc trunk cd CD SCSEMASF31 03888274 03888274 dij Auto Detect By Add File SOCVHPS SCSEMA5F31 TDI a a TDO Figure 3 8 Program sof file into the FPGA device B Configure the FPGA in AS Mode e The DEI SoC board uses a quad serial configuration device EPCS 128 to store configuration data for the Cyclone V SoC FPGA This configuration data is automatically loaded from the quad serial configuration device chip into the FPGA when the board is powered up e Users need to use Serial Flash Loader SFL to program the quad serial configuration device via JTAG interface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridge the JTAG and Flash interfaces The SFL Megafunction is available in Quartus II Figure 3 9 shows the programming method when adopting SFL solution e Please refer to Chapter 9 Steps of Programming the Quad Serial Configuration Device for the basic programming instruction on the serial configuration device asic DE1 SoC User Manual 18 www terasic com bbdd 25 C Apr i 2 2015 Cyclone V SoC Quartus Il SFL Image Programmer e Quad Serial USB Blaster II to Bridge AS x4 Circuit The JTAG ASMI gt and ASMI evice Figure 3 9 Programming a quad serial configuration device
64. lash Loader and click Add Device as shown in Figure 8 3 11 Click OK and the Select Devices page will appear DE1 SoC User Manual 107 www terasic com Cijasic April 2 2015 www terasic com ANU S RYAN UNIVERSITY PROGRAM CC INNEREN Zn C Search altera com altera com Output programming file Programming file type File name D foutput_file jic Remote Local update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd File Data area Properties Start Address Flash Loader 4 SOF Data Page D lt auto gt DE1 SoC Default sof SCSEMASF31 Remove Properties Figure 8 3 Click on the Flash Loader 12 Select the targeted FPGA to be programed into the EPCS as shown in Figure 8 4 13 Click OK and the Convert Programming Files page will appear as shown in Figure 8 5 14 Click Generate DE1 SoC User Manual 108 www terasic com Tijasic April 2 2015 www terasic com Import Export Remove Uncheck All Cvdone IVE Cydone IV GX M Cydone V HardCopy II HardCopy III LI HardCopy IV MAX 10 FPGA MAX II C scsxrcace Figure 8 4 Select Devices page asic DE1 SoC User Manual 109 www t
65. led by HPS I2C CONTROL which is connected to the GPIOI controller in HPS The HPS DC is connected to the I2C0 controller in HPS as well as the G sensor asic DE1 SoC User Manual 96 www terasic com bad 257 Apr i 2s 2015 UNIVERSITY PROGRAM FPGA SoC DDR3 ARM Program FPGA I2C HPS Linux User Mode HPS I2C Linux Kernel Mode Figure 6 9 Block diagram of the I2C MUX test demonstration Audi Decoder HPS I2C CONTROL B HPS 2C CONTROL Control HPS RC CONTROL is connected to HPS GPIO48 which is bit 19 of the GPIOI controller Once HPS gets access to the I2C bus it can then access Audio CODEC and TV Decoder when the HPS RC CONTROL signal is set to high The following mask in the demo code is defined to control the direction and output value of HPS DC CONTROL define HPS RC CONTROL 0x00080000 The following statement is used to configure the HPS I2C CONTROL associated pins as output pin alt setbits word virtual base Cuint32 t ALT GPIOI SWPORTA DDR ADDR amp uint32_t HW REGS MASK HPS RC CONTROL The following statement is used to set HPS RC CONTROL high alt setbits word virtual base Cuint32 t ALT GPIO SWPORTA DR ADDR amp uint32 t HW REGS MASK HPS RC CONTROL The following statement is used to set HPS RC CONTROL low alt cirbits word virtual base Cuint32 t ALT GPIO1 SWPORTA DR ADDR amp uint32_t HW REGS MASK H
66. lt in I2C kernel driver in Altera Soc Yocto Powered Embedded Linux B Function Block Diagram Figure 6 6 shows the function block diagram of this demonstration The G sensor on the DEI SoC board is connected to the I2C0 controller in HPS The G Sensor I2C 7 bit device address is 0x53 The system I2C bus driver is used to access the register files in the G sensor The G sensor interrupt DE1 SoC User Manual 93 www terasic com asic April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM signal is connected to the PIO controller This demonstration uses polling method to read the register data FPGA SoC DDR3 ARM Program HPS Linux User Mode G Sensor E 200 E I2C address 0x53 Linux Kernel Mode Interrupt Figure 6 6 Block diagram of the G sensor demonstration B 2C Driver The procedures to read a register value from G sensor register files by the existing I2C bus driver in the system are 1 Open I2C bus driver dev 12c 0 file open dev 12c 0 O_RDWR 2 Specify G sensor s I2C address 0x53 ioctl file 2C SLAVE 0x53 3 Specify desired register index in g sensor write file amp Addrs sizeof unsigned char 4 Read one byte register value read file amp Data8 sizeof unsigned char The G sensor I2C bus is connected to the I2CO controller as shown in the Figure 6 7 The driver name given is dev 12c 0 E23 HPS I2C1 SCLK C24 HPS I2C1 SDAT I2C0 SCL I2C0 SDA Figure 6 7 Connectio
67. n various sizes Figure 3 18 shows the connection of seven segments common anode to pins on Cyclone V SoC FPGA The segment can be turned on or off by applying a low logic level or high logic level from the FPGA respectively Each segment in a display is indexed from 0 to 6 with corresponding positions given in Figure 3 18 Table 3 9 shows the pin assignment of FPGA to the 7 segment displays HEXO 0 HEXO 1 ia ATERA HEXO 3 p E Cyclone V HEXO 5 Soc A HEXO 6 Figure 3 18 Connections between the 7 segment display HEXO and the Cyclone V SoC FPGA www terasic com DE1 SoC User Manual 26 TijasiC April 2 2015 www terasic com Signal Name HEXO 0 HEXO 1 HEXO 2 HEXO 3 HEXO 4 HEXO 5 HEXO 6 HEX1 0 HEX1 1 HEX1 2 HEX1 3 HEX1 4 HEX1 5 HEX1 6 HEX2 0 HEX2 1 HEX2 2 HEX2 3 HEX2 4 HEX2 5 HEX2 6 HEX3 0 HEX3 1 HEX3 2 HEX3 3 HEX3 4 HEX3 5 HEX3 6 HEXA 0 HEX4A 1 HEX4 2 HEX4 3 HEX4 4 HEX4 5 HEXA 6 HEX5 0 HEX5 1 HEX5 2 HEX5 3 HEX5 4 HEX5 5 HEX5 6 Table 3 9 Pin Assignment of 7 segment Displays FPGA Pin No PIN AE26 PIN AE27 PIN AE28 PIN AG27 PIN AF28 PIN AG28 PIN AH28 PIN AJ29 PIN AH29 PIN AH30 PIN AG30 PIN AF29 PIN AF30 PIN AD27 PIN AB23 PIN AE29 PIN AD29 PIN AC28 PIN AD30 PIN AC29 PIN AC30 PIN AD26 PIN AC27 PIN AD25 PIN AC25 PIN AB28 PIN AB25 PIN AB22 PIN AA24 PIN Y23 PIN Y24 PIN W22 PIN W24 PIN V23
68. n Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design entity DE1 SoC User Manual 55 www terasic com Tijasic April 2 2015 www terasic com UNIVERSITY PROGRAM DE1 SoC V1 0 0 AN OTS 84 AN asic System Configuration UNIVERSITY Mild Proje P R o G R A M www terasic com k UT DEI SOC DE1 SoC FPGA Board MI CLOCK lv T Seqment x 6 VI LED x 10 VI Switch x 10 IR TXIRX VI NGA video in MI Audio VI ADC VI SDRAM 32MB VI PS2 HPS GPIO 0 Header C Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 3 Enter the project name B System Configuration Users are given the flexibility in the System Configuration to include their choice of components in the project as shown in Figure 4 4 Each component onboard is listed and users can enable or disable one or more components at will If a component is enabled the DEI SoC System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard DE1 SoC User Manual 56 www terasic com Tijasic April 2 2015 www terasic com UNIVERSITY PROGRAM DE1 SoC V1 0 0 js System Configuratio ADE RYA UNIVERSITY PROGRAM WWw terasic com DE1 SoC FPGA Board Project Name DEI SOC W CLOCK WM LED x 10 4 Button x 4 VIVGA MI Audio 4 SDRAM 32MB
69. n of HPS I2C signals The step 4 above can be changed to the following to write a value into a register write file amp Data8 sizeof unsigned char The step 4 above can also be changed to the following to read multiple byte values DE1 SoC User Manual 94 www terasic com TijasiC April 2 2015 www terasic com read file amp szData8 sizeof szData8 where szData is an array of bytes The step 4 above can be changed to the following to write multiple byte values write file amp szData8 sizeof szData8 where szData is an array of bytes B G sensor Control The ADI ADXL345 provides I2C and SPI interfaces I2C interface is selected by setting the CS pin to high on the DEI SoC board The ADI ADXL345 G sensor provides user selectable resolution up to 13 bit 16g The resolution can be configured through the DATA FORAMT 0x31 register The data format in this demonstration is configured as Full resolution mode 16g range mode Left justified mode The X Y Z data value can be derived from the DATAX0 0x32 DATAX1 0x33 DATAYO 0x34 DATAY 1 0x35 DATAZO 0x36 and DATAX1 0x37 registers The DATA XO represents the least significant byte and the DATAXI represents the most significant byte It is recommended to perform multiple byte read of all registers to prevent change in data between sequential registers read The following statement reads 6 bytes of X Y or Z value read file szData8 sizeof szDatas
70. ne This is called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequence in less than 10ms time The transmit data consists of 12bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit always zero After sending out the parity check bit the controller should release the data line and the device will detect any state change on the data line in the next clock cycle If there s no change on the data line for one clock cycle the device will pull low the data line again as an acknowledgement which means that the data is correctly received After the power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 5 11 shows the waveform while communication happening on two lines DE1 SoC User Manual 74 www terasic com TijasiC April 2 2015 www terasic com Sending command CLK Inhibit 4st 2nd gth 10th 41th CLK CLK CLK e cek DATA IET UG koi Start bit Bit0 Bit7 Parity bit Stop Line bit control bit Receiving data 1 st 2nd 1 Om 1 1 th CLK CLK CLK CLK CLK ecce i Start bit BitO Bit7 Parity bit Stop bit Figure 5 11 Waveform of clock and data signals during data t
71. needs to be performed on the data source because the video signal for the TV decoder is interlaced The SDRAM Frame Buffer and a field selection multiplexer MUX which is controlled by the VGA Controller are used to perform the de interlacing operation The VGA Controller also generates data request and odd even selection signals to the SDRAM Frame Buffer and filed selection multiplexer MUX The YUV422 to YUVAAA block converts the selected YcrCb 4 2 2 YUV 4 2 2 video data to the YcrCb 4 4 4 YUV 4 4 4 video data format Finally the YcrCb to RGB block converts the YcrCb data into RGB data output The VGA Controller block generates standard VGA synchronous signals VGA HS and VGA VS to enable the display on a VGA monitor DE1 SoC User Manual 71 www terasic com asic April 2 2015 www terasic com YUV 4 2 2 Data Valid I2C SCLK I2C SDAT Figure 5 9 Block diagram of the TV box demonstration Demonstration Source Code e Project directory DEI SoC TV e Bitstream used DEI SoC TV sof Demonstration Batch File Demo batch directory NDE1 SoC TV Memo batch The folder includes the following files e Batch file DEI SoC TV bat e FPGA configuration file DEI SoC TV sof Demonstration Setup File Locations and Instructions e Connect a DVD player s composite video output yellow plug to the Video in RCA jack J6 on the DE1 SoC board as shown in Figure 5 10 The DVD player has to be configured to prov
72. nnection from board to Gigabit Ethernet 1s established once the LEDG lights on Table 3 25 State and Definition of LED Mode Pins LED State LED Definition Link Activity LEDG LEDY LEDG LEDY H H OFF OFF Link off L H ON OFF 1000 Link No Activity Toggle H Blinking OFF 1000 Link Activity RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking 10 Link Activity RX TX 3 7 3 UART The board has one UART interface connected for communication with the HPS This interface doesn t support HW flow control signals The physical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector More information about the chip is available on the manufacturer s website or in the directory Datasheets UART TO www terasic com DE1 SoC User Manual 45 TijasiC April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM USB of DE1 SoC system CD Figure 3 33 shows the connections between the HPS FT232R chip and the USB Mini B connector Table 3 26 lists the pin assignment of UART interface connected to the HPS ND S RYA Cyclone v HPS Signal Name HPS UART RX HPS UART TX HPS CONV USB N HPS RESET n o MB FT232R FT232 DP FT232 DM USB Mini B Connector Figure 3 33 Connections between the HPS and FT232R Chip Table 3 26 Pin Assignment of UART I
73. ns all the documents and supporting materials associated with DEI SoC including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http cd del soc terasic com 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems e Altera Corporation e 101 Innovation Drive San Jose California 95134 USA Email university altera com e Terasic Technologies e 9E No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 575 0880 Website del soc terasic com DE1 SoC User Manual 5 WWW terasic com TijasiC April 2 2015 www terasic com Chapter 2 Introduction of the DE 1 SoC Board This chapter provides an introduction to the features and design characteristics of the board 2 1 Layout and Components Figure 2 1 shows a photograph of the board It depicts the layout of the board and indicates the location of the connectors and key components DE1 SoC User Manual 6 www terasic com TijasiC April 2 2015 www terasic com c i VGA Out Mic Line Line VGA HPS Gigabit HPS In In Out Video In 24 bit DAC Ethernet USB Host UART to USB AAA USB HUB JTAG Header e a B T EM roller Audio Codec os Video Decoder unie Micro SD Card PS2 USB PHY Ethernet PHY USB Blaster II OD mete Power DC Jack n i 1GB DDR3 SDRAM ae i Altera 28 nm Power O
74. nterface FPGA Pin No Description PIN B25 HPS UART Receiver PIN C25 HPS UART Transmitter PIN B15 Reserve 3 7 4 DDR3 Memory I O Standard 3 3V 3 3V 3 3V The DDR3 devices connected to the HPS are the exact same model as the ones connected to the FPGA The capacity is 1GB and the data bandwidth is in 32 bit comprised of two x16 devices with a single address command bus The signals are connected to the dedicated Hard Memory Controller for HPS I O banks and the target speed is 400 MHz Table 3 27 lists the pin assignment of DDR3 and its description with I O standard Signal Name HPS DDR3 A 0 HPS DDR3 A 1 HPS DDR3 A 2 HPS DDR3 A 3 HPS DDR3 A 4 HPS DDR3 A 5 Table 3 27 Pin Assignment of DDR3 Memory FPGA Pin No Description PIN F26 HPS DDR3 Address 0 PIN G30 HPS DDR3 Address 1 PIN F28 HPS DDR3 Address 2 PIN F30 HPS DDR3 Address 3 PIN J25 HPS DDR3 Address 4 PIN J27 HPS DDR3 Address 5 Tasic DE1 SoC User Manual 46 www terasic com I O Standard SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I www terasic com April 2 2015 UNIVERSITY PROGRAM HPS DDR3 A 6 HPS DDR3 A 7 HPS DDR3_A 8 HPS DDR3 A 9 HPS DDR3 A 10 HPS DDR3 Af11 HPS DDR3 A 12 HPS DDR3 A 13 HPS DDR3 A 14 HPS DDR3 BA 0 HPS DDR3 BA 1 HPS DDR3 BA 2 HPS DDR3 CAS n HPS DDR3 CKE HPS DDR3 CK n HPS DDR3 CK p HPS DDR3 CS n HPS DDR3 DM 0 HPS DDR3 DM 1 HPS DDR3 DM 2 HPS DDR3 DM
75. o chip The audio chip is programmed through I2C protocol which is implemented in C code The I2C pins from the audio chip are connected to Qsys system interconnect fabric through PIO controllers The audio chip is configured in master mode in this demonstration The audio interface is configured as 16 bit I28 mode 18 432MHz clock generated by the PLL is connected to the MCLK XTI pin of the audio chip through the audio controller asic DE1 SoC User Manual 62 www terasic com kidd 25 C Apr i 2 2015 aiiis SDRAM Store Audio Data Nios II Program ouqe J OUUODIAJU ure s S P cc LO ir 4 Figure 5 3 Block diagram of the audio recorder and player LED KEY ISW I2C E Demonstration Setup File Locations and Instructions e Hardware project directory DE1 SoC Audio e Bitstream used DE SoC Audio sof e Software project directory DE1_SoC _Audio software e Connect an audio source to the Line in port e Connect a Microphone to the MIC in port e Connect a speaker or headset to the Line out port e Load the bitstream into the FPGA note 1 e Load the software execution file into the FPGA note 1 e Configure the audio with SWO as shown in Table 5 1 e Press KEY3 to start stop audio recording note 2 e Press KEY2 to start stop audio playing note 3 Table 5 1 Slide switches usage for audio source Slide Switches 0 DOWN Position 1 UP Position swo Audiois from MIC in Audio is fr
76. oard Type root to login Altera Yocto Linux e Execute hps config fpga soc system dc rbf in the UART terminal of PuTTY to configure the FPGA through the FPGA manager After the configuration is successful the message shown in Figure 7 2Figure72 will be displayed in the terminal ce e Execute HPS LED HEX in the UART terminal of PuTTY to start the program e The message shown in Figure 7 3OLE LINKA will be displayed in the terminal The LED 9 0 will be flashing and the number on the HEX 5 0 will keep changing simultaneously Lo iu g Taj W i co uj I e Press CTRL C to terminate the program DE1 SoC User Manual 102 www terasic com TijasiC April 2 2015 www terasic com 7 2 DE1 SoC Control Panel The DEI SoC Control Panel is a more comprehensive example It demonstrates Control HPS LED and FPGA LED HEX Query the status of buttons connected to HPS and FPGA Configure and query G sensor connected to HPS Control Video in and VGA out connected to FPGA Control IR receiver connected to FPGA This example not only controls the peripherals of HPS and FPGA but also shows how to implement a GUI program on Linux Figure 7 4OLE LINKA is the screenshot of DEI SOC Control Panel Figure 7 4 Screenshot of DE1 SoC Control Panel Please refer to DE1 SoC Control Panel pdf which is included in the DE1 SOC System CD for more information on how to build a GUI program step by step 7 3 DE1 SoC Lin
77. ock Active low input affects the system reset domain for debug purpose USB Blaster II JTAG Connector PIN 6 VCC3P3 Cyclone V SoC KEY 7 HPS FPGA HE B HPS WARM RST n AP PGA WARM RST VCC3P3 HPS RESET n KEY 5 a S HPS RESET n HPS ENET RESET n 10 100 1000 Base T Ethernet PHY KSZ9021RN RESET N USB 2 0 OTG PHY USB3300 RESET HPS RESET PHY Inverter Figure 3 12 HPS reset tree on DE1 SoC board 3 5 Clock Circuitry Figure 3 13 shows the default frequency of all external clocks to the Cyclone V SoC FPGA A clock generator is used to distribute clock signals with low jitter The four 50MHz clock signals connected to the FPGA are used as clock sources for user logic One 25MHz clock signal is connected to two HPS clock inputs and the other one is connected to the clock input of Gigabit DE1 SoC User Manual 21 www terasic com Tijasic April 2 2015 www terasic com JA DTE RYA UNIVERSITY PROGRAM Ethernet Transceiver Two 24MHz clock signals are connected to the clock inputs of USB Host OTG PHY and USB hub controller The associated pin assignment for clock inputs to FPGA I O pins is listed in Table 3 5 Si5350C JN DTE RYAN Cyclone v CLOCK 50 50MHz kp Sel CLOCK2 50 50MHz CLOCK4_50 50MHz CLOCK3 50 50MHz bna HPS CLK 25 25MHz na mid HPS CLK2 Gigabit Ethernet ENET CLK 25 25MHz Transceiver USB Host PHY USBPHY CLK 24 24MHz 2 port Hub USBHUB CLK 24 24M
78. ode which is also the default setting on DEI SoC When the board is powered on the FPGA is configured from EPCS which is pre programmed with the default code If developers wish to reconfigure FPGA from an application software running on Linux the MSEL 4 0 needs to be set to 01010 before the programming process begins If developers using the Linux Console with frame buffer or Linux LXDE Desktop SD Card image the MSEL 4 0 needs to be set to 00000 before the board is powered on Table 3 2 MSEL Pin Settings for FPGA Configure of DE1 SoC MSEL 4 0 X Configure Scheme Description 10010 AS FPGA configured from EPCS default 01010 FPPx32 FPGA configured from HPS software Linux FPGA configured from HPS software U Boot with 00000 FPPx16 image stored on the SD card like LXDE Desktop or console Linux with frame buffer edition 3 2 Configuration of Cyclone V SoC FPGA on DE1 SoC There are two types of programming method supported by DEI SoC 1 JTAG programming It is named after the IEEE standards Joint Test Action Group The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA The FPGA will retain its current status as long as the power keeps applying to the board the configuration information will be lost when the power is off 2 AS programming The other programming method is Active Serial configuration The configuration bit stream is downloaded into the quad serial configuration device EPCS 12
79. om Line in DE1 SoC User Manual 63 WWW terasic com Tijasic April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM Table 5 2 Settings of switches for the sample rate of audio recorder and player SW5 SW4 SW3 0 DOWN 0 DOWN 0 DOWN Sample Rate 1 UP 1 UP 1 UP 0 0 0 96K 0 0 1 48K 0 1 0 44 1K 0 1 1 32K 1 0 0 8K Unlisted combination 96K Q Note 1 Execute DE7 SoC Audio demo batch DE1 SoC Audio bat to download sof and elf files 2 Recording process will stop if the audio buffer is full 3 Playing process will stop if the audio data is played completely 5 3 Karaoke Machine This demonstration uses the microphone in line in and line out ports on DEI SoC to create a Karaoke machine The WM8731 CODEC is configured in master mode The audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically The DC interface is used to configure the audio CODEC as shown in Figure 5 4 The sample rate and gain of the CODEC are set in a similar manner and the data input from the line in port is then mixed with the microphone in port The result is sent out to the line out port The sample rate is set to 48 kHz in this demonstration The gain of the audio CODEC is reconfigured via I2C bus by pressing the pushbutton KEYO cycling within ten predefined gain values volume levels provided by the device DE1 SoC User Manual 64 www terasic com asic April 2 2015
80. on 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit in two s complement and can be accessed through RC interface The I2C address of G sensor is OxA6 OxA7 More information about this chip can be found in its datasheet which is available on manufacturer s website or in the directory Datasheet folder of DEI SoC system CD Figure 3 36 shows the connections between the HPS and G sensor Table 3 30 lists the pin assignment of G senor to the HPS Tasic DE1 SoC User Manual www terasic com 50 www terasic com April 2 2015 U28 re HPS I2C1 SCLK arsa SCLK Cyclone V ES eee ls ens SDL SDIO SoC HPS GSENSOR INT INIT HPS ADXL345 Figure 3 36 Connections between Cyclone V SoC FPGA and G Sensor Table 3 30 Pin Assignment of G senor Signal Name FPGA Pin No Description O Standard HPS GSENSOR INT PIN B22 HPS GSENSOR Interrupt Output 3 3V HPS I2C1 SCLK PIN E23 HPS I2C Clock share bus with LTC 3 3V HPS I2C1 SDAT PIN C24 HPS I2C Data share bus 3 3V 3 7 8 LTC Connector The board has a 14 pin header which 1s originally used to communicate with various daughter cards from Linear Technology It is connected to the SPI Master and I2C ports of HPS The communication with these two protocols is bi directional The 14 pin header can also be used for GPIO SPI or I2C based communication with the HPS Connections between the HPS and LTC connector are shown in Figure 3 37 and the pin as
81. on about the PS 2 protocol can be found on various websites DE1 SoC User Manual 73 www terasic com Tijasic April 2 2015 www terasic com B Introduction PS 2 protocol uses two wires for bi directional communication One is the clock line and the other one is the data line The PS 2 controller always has total control over the transmission line but it is the PS 2 device which generates the clock signal during data transmission B Data Transmission from Device to the Controller After the PS 2 mouse receives an enabling signal at stream mode it will start sending out displacement data which consists of 33 bits The frame data 1s cut into three sections and each of them contains a start bit always zero eight data bits with LSB first one parity check bit odd check and one stop bit always one The PS 2 controller samples the data line at the falling edge of the PS 2 clock signal This is implemented by a shift register which consists of 33 bits easily be implemented using a shift register of 33 bits but be cautious with the clock domain crossing problem B Data Transmission from the Controller to Device When the PS 2 controller wants to transmit data to device it first pulls the clock line low for more than one clock cycle to inhibit the current transmission process or to indicate the start of a new transmission process which is usually called as inhibit state It then pulls low the data line before releasing the clock li
82. orm built around the Altera System on Chip SoC FPGA which combines the latest dual core Cortex A9 embedded cores with industry leading programmable logic for ultimate design flexibility Users can now leverage the power of tremendous re configurability paired with a high performance low power processor system Altera s SoC integrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The DEI SoC development board is equipped with high speed DDR3 memory video and audio capabilities Ethernet networking and much more that promise many exciting applications The DEI SoC Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a photograph of the DE1 SoC package DE1 SoC Board DE1 SoC Quick Start Guide Type A to B USB Cable Type A to Mini B USB Cable Power DC Adapter 12V Figure 1 1 The DE1 SoC package contents DE1 SoC User Manual 4 www terasic com TijasiC April 2 2015 www terasic com The DEI SoC package includes e The DEI SoC development board e DEI SoC Quick Start Guide e USB cable Type A to B for FPGA programming and control e USB cable Type A to Mini B for UART control e 12V DC power adapter 1 2 DE1 SoC System CD The DEI SoC System CD contai
83. ransmission Demonstration Source Code e Project directory DEI SoC PS2 DEMO e Bitstream used DE SoC PS2 DEMO sof Demonstration Batch File Demo batch file directoy NDE1 SoC PS2 DEMO demo batch The folder includes the following files e Batch file DEI SoC PS2 DEMO bat e FPGA configuration file DEI SoC PS2 DEMO sof asic DE1 SoC User Manual 75 www terasic com Migjas e April 2 2015 Demonstration Setup File Locations and Instructions e Load the bitstream into the FPGA by executing DEI SoC PS2 DEMO Memo batch DEI SoC PS2 DEMO bat e Plug in the PS 2 mouse Press KEY O to enable data transfer Press KEY 1 to clear the display data cache e The 7 segment display should change when the PS 2 mouse moves The LEDR 2 0 will blink according to Table 5 4 when the left button right button and or middle button is pressed Table 5 4 Description of 7 segment Display and LED Indicators r r r 5 8 IR Emitter LED and Receiver Demonstration DEI SoC system CD has an example of using the IR Emitter LED and IR receiver This demonstration is coded in Verilog HDL DE1 SoC User Manual 76 www terasic com Tiasic April 2 2015 www terasic com FPGA KEY 0 E gt DATA test pattern IR RX IR T Controller dum Receiver 4 4 Remote Figure 5 12 Block diagram of the IR emitter LED and receiver demonstration Figure 5 12 shows the block diagram of the design It implements a IR TX Controller and a IR R
84. red to accept eight input signals at inputs ADC INO through ADC INT7 These eight input signals are connected to a 2x5 header as shown in Figure 3 30 More information about the A D converter chip 1s available in its datasheet It can be found on manufacturer s website or in the directory Matasheet of Del SoC system CD VCC5 ADC INO ADC IN1 ADC IN2 ADC IN3 ADC IN4 ADC IN5 ADC IN6 ADC IN7 GND Figure 3 30 Signals of the 2x5 Header Figure 3 31 shows the connections between the FPGA 2x5 header and the A D converter DE1 SoC User Manual 42 www terasic com asic April 2 2015 www terasic com UNIVERSITY PROGRAM AD7928BRUZ ADC INO ADC INT ADC SCLK ADC IN2 y ADC_DIN qe ADC_DOUT 2x5 ADC_IN3 SE Header ADC IN4 ADC_CS_N ey ADC IN5 Cyclone ADC IN6 So ADC IN7 Figure 3 31 Connections between the FPGA 2x5 header and the A D converter Table 3 22 Pin oe of ADC Signal Name FPGA Pin No Besorioen _10 Standard _ Standard ADC CS N PIN AJ4 Chip select 33V ADC DOUT PIN AK3 Digital data input ADC DIN PIN_AK4 Digital data output ADC SCLK PIN AK2 Digital clock input 3 7 Peripherals Connected to Hard Processor System HPS This section introduces the interfaces connected to the HPS section of the Cyclone V SoC FPGA Users can access these interfaces via the HPS processor 3 7 1 User Push buttons and LEDs Similar to the FPGA the HPS also has its set of switches buttons LEDs
85. signment of LTC connector is listed in Table 3 31 DE1 SoC User Manual 51 www terasic com asic April 2 2015 www terasic com HPS SPIM CLK HPS SPIM SS ANU S RAN D22 PPS SPIM MOSI c ey b HPS_SPIM_MISO yclone s SoC AE HPS I2C2 SDAT Connector HPS I2C2 SCLK H23 HPS HPS LTC GPIO H17 U41 HPS SPIM MOSI F we HPS I2C2 SDAT MOSI SDA HPS SPIM CLK HPS I2C2 SCLK HPS LTC GPIO TS3A5018 Figure 3 37 Connections between the HPS and LTC connector Table 3 31 Pin Assignment of LTC Connector FPGA Pin No VO Standard PIN H17 HPS LTC GPIO 3V HPS I2C2 Clock share bus with 3 3V G Sensor HPS 1I2C2 Data share bus with 3 G Sensor HPS SPIM MISO PIN E24 SPI Master Input Slave Output 33V HPS SPIM MOSI PIN D22 SPI Master Output Slave Input 33V HPS SPIM SS fPIND24 SPI Slave Select 1 33V O DE1 SoC User Manual 52 www terasic com Tijasic April 2 2015 www terasic com Chapter 4 DE 1 SoC System Builder This chapter describes how users can create a custom design project with the tool named DEI SoC System Builder 4 1 Introduction The DEI SoC System Builder is a Windows based utility It is designed to help users create a Quartus II project for DEI SoC within minutes The generated Quartus II project files include e Quartus II project file qpf e Quartus II setting file qsf e Top level design file v e Synops
86. ss reaches 100 the result will be displayed in nios terminal B Design Tools e Quartus II v13 1 e Nios II Eclipse v13 1 B Demonstration Source Code e Quartus project directory DEI SoC SDRAM Nios Test e Nios II Eclipse directory DEI SoC SDRAM Nios Test Software DE1 SoC User Manual 67 www terasic com Cijasic April 2 2015 www terasic com B Nios II Project Compilation e Click Clean from the Project menu of Nios II Eclipse before compiling the reference design in Nios II Eclipse B Demonstration Batch File The files are located in the directory DEI SoC SDRAM Nios Test demo batch The folder includes the following files e Batch file for USB Blaster IIT DEI SoC SDRAM Nios Test bat and DEI SoC SDRAM Nios Test bashrc e FPGA configuration file DEI SoC SDRAM Nios Test sof e Nios II program DEI SoC SDRAM Nios Test elf B Demonstration Setup e Quartus II v13 1 and Nios II v13 1 must be pre installed on the host PC e Power on the DEI SoC board e Connect the DE1 SoC board J13 to the host PC with a USB cable and install the USB Blaster driver if necessary e Execute the demo batch file DEI SoC SDRAM Nios Test bat from the directory DEI SoC SDRAM Nios Testidemo batch e After the program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Press any button KEY3 KEYO to start the SDRAM verification process Press KEYO to run the test continuously e
87. t JTAG Indirect Configuration File jic from the Programming file type field in the dialog of Convert Programming Files 3 Choose EPCS128 from the Configuration device field 4 Choose Active Serial from the Mode filed 5 Browse to the target directory from the File name field and specify the name of output file 6 Click on the SOF data in the section of Input files to convert as shown in Figure 2 asic DE1 SoC User Manual 106 www terasic com kidd asic Apr i 2 2015 fu Convert Programming File File Tools Window Spedfy the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type JTAG Indirect Configuration File jic Qe Conran deve Mode File name D foutput file jic Remote Local update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd File Data area Start Address Flash Loader SOF Data lt auto gt of Page Figure 8 2 Dialog of Convert Programming Files 7 Click Add File 8 Select the sof to be converted to a jic file from the Open File dialog 9 Click Open 10 Click on the F
88. t data line control line and address line connected to the FPGA This chip uses the 3 3V LVCMOS signaling standard Connections between the FPGA and SDRAM are shown in Figure 3 27 and the pin assignment is listed in Table 3 20 DE1 SoC User Manual 38 www terasic com TijasiC April 2 2015 www terasic com 32Mx16 SDRAM DRAM DQ 5 0 PS 2s DRAM ADDR 12 0 an n DRAM BA 1 0 BAI1 0 DRAM CLK CLK ANU amp B4AN DRAM CKE CKE i DRAM_LDQM LDQM Cyclone V SRAM we N Ma e DRAM WE N AWE Soc DRAM_CAS_N ACAS DRAM_RAS_N nRAS DRAM CS N nCS R Figure 3 27 Connections between the FPGA and SDRAM Table 3 20 Pin Assignment of SDRAM Signal Name FPGA Pin No Description O Standard DRAM ADDRIOJ PIN AK14 SDRAM Address 0 33V DRAM_ADDR 1 PIN_AH14 SDRAM Address 1 43 39V DRAM_ADDR 2 PIN AG15 SDRAM Address 2 43 39V DRAM ADDR 3 PIN AE14 SDRAM Address 3 q3 39V DRAM ADDR 4 PIN AB15 SDRAM Address 4 43 39V DRAM ADDR 5 PIN AC14 SDRAM Address 5 33V DRAM ADDR 6 PIN AD14 SDRAM Address 6 33V DRAM ADDR 7 PIN AF15 SDRAM Address 7 3 3V DRAM ADDRI8I PIN AH15 SDRAM Address 8 3 3V DRAM ADDR 9 PIN AG13 SDRAM Address 9 33V DRAM ADDR 10 PIN AG12 SDRAM Address 10 33V DRAM ADDR 11 PIN AH13 SDRAM Address 11 43 39V DRAM AD
89. tem through two push buttons and four slide switches e SWO is used to specify the recording source to be Line in or MIC In e SWI SW2 and SW3 are used to specify the recording sample rate such as 96K 48K 44 1K 32K or 8K e Table 5 1 and Table 5 2 summarize the usage of slide switches for configuring the audio recorder and player DE1 SoC User Manual 61 www terasic com asic April 2 2015 www terasic com ett Ari AIT ITE mE i fs Pe Here z t ar a 1 n Comal Hala on miza 1125 d WOC1PS ODORS Cita mba m Cita r 3 ae E E ity as l T aA D EE a 5 ea H it D 3 F Br 4 um nd D I ua 3182 2 eo Ha s JTD li L TEU IE de 1 Hi HTC cia ni La ri n Powe peo ee emo Ce Doel Bol beet ls Dect fet Dood Hl Audio Source Play MIC or LINE IN Sample Rate Record Figure 5 2 Buttons and switches for the audio recorder and player Figure 5 3 shows the block diagram of audio recorder and player design There are hardware and software parts in the block diagram The software part stores the Nios II program in the on chip memory The software part is built under Eclipse in C programming language The hardware part is built under Qsys in Quartus II The hardware part includes all the other blocks such as the AUDIO Controller which is a user defined Qsys component and it is designed to send audio data to the audio chip or receive audio data from the audi
90. the ADC B System Requirements The following items are required for this demonstration DE1 SoC User Manual 83 www terasic com Tijasic April 2 2015 www terasic com JA DTE RYA UNIVERSITY PROGRAM e DEI SoC board xl e Trimmer Potentiometer x1 e Wire Strip x3 B Demonstration File Locations e Hardware project directory DEI SoC ADC e Bitstream used DEI SoC ADC sof e Software project directory DEl SoC ADC software e Demo batch file DEI SoC ADCMemo batch DEI SoC ADC bat B Demonstration Setup and Instructions e Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in Figure 5 21 as well as the 5V and GND signals The setup shown above is connected to ADC channel 0 e Execute the demo batch file DEI SoC ADC bat to load the bitstream and software execution file to the FPGA e The Nios II console will display the voltage of the specified channel voltage result information EL EE a Figure 5 21 Hardware setup for the ADC reading demonstration DE1 SoC User Manual 84 www terasic com Tijasic April 2 2015 www terasic com Chapter 6 Examples for HPS SoC This chapter provides several C code examples based on the Altera SoC Linux built by Yocto project These examples demonstrates major features connected to HPS interface on DEI SoC board such as users LED KEY I2C interfaced G sensor and I2C MUX AII the associated files can be found in the directory Demonstrations SO
91. the FPGA is configured and the software is running on HPS B Demonstration Source Code e Build tool Altera SoC EDS V13 1 e Project directory Demonstration SoC FPGANAPS LED HEX e Quick file directory Demonstration SoC FPGAMIPS LED HEX quickfile e FPGA configuration file soc system dc rbf e Binary file HPS LED HEX and hps config fpga e Build app command make make clean to remove all temporal files e Execute app command hps config fpga soc system dc rbf and HPS LED HEX B Demonstration Setup e Quartus II and Nios II must be installed on the host PC e The MSEL 4 0 is set to 01010 or 01110 e Connect a USB cable to the USB Blaster II connector J13 on the DE1 SoC board and the host PC Install the USB Blaster II driver if necessary e Connect a USB cable to the USB to UART connector J4 on the DEI SoC board and the host PC e Copy the executable files hps config fpga and HPS LED HEX and the FPGA configuration file soc system dc rbf into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEI SoC board Please refer to the chapter 5 DE1 SoC User Manual 101 www terasic com TijasiC April 2 2015 www terasic com UNIVERSITY PROGRAM Running Linux on the DEI SoC board on DEI SoC Getting Started Guide pdf on how to build a booting microSD card image e Power on the DEI SoC board e Launch PuTTY to establish connection to the UART port of the DEI SoC b
92. the control register Switches Buttons and Indicators e 5user Keys FPGA x4 HPS x1 e 10 user switches FPGA x10 e Il user LEDs FPGA x10 HPS x 1 e 2 HPS reset buttons HPS RESET n and HPS WARM RST n e Six 7 segment displays Sensors e G Sensor on HPS Power e 2V DC input DE1 SoC User Manual 11 www terasic com asic April 2 2015 www terasic com Chapter 3 Using the DE1 SoC Board This chapter provides an instruction to use the board and describes the peripherals 3 1 Settings of FPGA Configuration Mode When the DEI SoC board is powered on the FPGA can be configured from EPCS or HPS The MSEL 4 0 pins are used to select the configuration scheme It is implemented as a 6 pin DIP switch SW10 on the DEI SoC board as shown in Figure 3 1 T y Bo BEE NEL MH lt TEE NEL Hi EN _ gt Tom Bi Q SW10 1 Figure 3 1 DIP switch SW10 setting of Active Serial AS mode at the back of DE1 SoC board Table 3 1 shows the relation between MSEL 4 0 and DIP switch SW10 DE1 SoC User Manual 12 WWW terasic com Sasic April 2 2015 www terasic com Table 3 1 FPGA Configuration Mode Switch SW10 Board Reference Signal Name Description Default SW10 1 MSELO ON 0 SW10 2 MSEL1 Use th T tthe FPGA OFF 1 SW10 3 MSEL2 aa aa ON 0 Configuration scheme SW10 4 MSEL3 ON 0 SW10 5 MSEL4 OFF 1 SW10 6 N A N A N A Figure 3 1 shows MSEL 4 0 setting of AS m
93. the frame The value of this frame 1s completely inverted at the receiving end www terasic com Figure 5 15 The remote controller used in this demonstration Table 5 5 Key Code Information for Each Key on the Remote Key Code Key Code Key Code Key Code DE1 SoC User Manual POWER R 600 000k CHANNEL o 0 OW o O O MENU RETURN SEDES G 0 op PLAY ADJUST MUTE e DOW INTERAN te TO N W A L N f 0x17 Y j 79 e LN www terasic com April 2 2015 End Inv Key Code Lead Code 1bit Custom Code 16bits Key Code 8bits 8bits Figure 5 16 The transmitting frame of the IR remote controller B IR RX Controller The following demonstration shows how to implement the IP of IR receiver controller in the FPGA Figure 5 17 shows the modules used in this demo including Code Detector State Machine and Shift Register At the beginning the IR receiver demodulates the signal inputs to the Code Detector The Code Detector will check the Lead Code and feedback the examination result to the State Machine The State Machine block will change the state from IDLE to GUIDANCE once the Lead Code is detected If the Code Detector detects the Custom Code status the current state will change from GUIDANCE to DATAREAD state The Code Detector will also save the receiving data and output to the Shift Register and display on the 7 segment Figure 5 18 shows the state shift diagram of St
94. to perform memory access in Qsys in this demonstration It also shows how Altera s SDRAM controller IP accesses SDRAM and how the Nios II processor reads and writes the SDRAM for hardware verification The SDRAM controller handles complex aspects of accessing SDRAM such as initializing the memory device managing SDRAM banks and keeping the devices refreshed at certain interval B System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz clock input from the board The SDRAM controller is configured as a 64MB controller The working frequency of the SDRAM controller is 100MHz and the Nios II program is running on the on chip memory DE1 SoC User Manual 66 www terasic com Tijasic April 2 2015 www terasic com FPGA QSYS au e po w JTAG ce lt gt Controller B A IM baki o Figure 5 6 Block diagram of the SDRAM test in Nios II 50 MHz On Chip lt gt Memory System Intercoment Fabric The system flow is controlled by a program running in Nios II The Nios II program writes test patterns into the entire 64MB of SDRAM first before calling the Nios II system function alt_dcache_flush_all to make sure all the data are written to the SDRAM It then reads data from the SDRAM for data verification The program will show the progress in nios terminal when writing reading data to from the SDRAM When the verification proce
95. tor An active low pulse of specific duration is applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB output to the monitor must be off driven to O V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of vertical synchronization vsync is similar to the one shown in Figure 3 23 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 14 and Table 3 15 show different resolutions and durations of time period a b c and d for both horizontal and vertical timing More information about the ADV7123 video DAC 1s available in its datasheet which can be found on the manufacturer s website or in the directory Datasheets WIDEO DAC of DEI SoC System CD The pin assignment between the Cyclone V SoC FPGA and the ADV7123 is listed in Table 3 16 DE1 SoC User Manual 33 www terasic com TijasiC April 2 2015 www terasic com Back porch b Front porch d Display interval c mU MNM RGB DATA HSYNC Sync a
96. uPD6121G built in for generating infrared signals Figure 3 25 shows the connection of IR receiver to the FPGA Table 3 18 shows the pin assignment of IR receiver to the FPGA VCC3P3 IRDA_RXD JA DTE RA i ai y dx GND CHASSIS Figure 3 25 Connection between the FPGA and IR Receiver EM Table 3 18 Pin Assignment of IR Receiver Signal Name FPGA Pin No Description vO Standard IRDA_RXD PIN AA30 IR Receiver 3 3V 3 6 9 IR Emitter LED The board has an IR emitter LED for IR communication which is widely used for operating television device wirelessly from a short line of sight distance It can also be used to communicate with other systems by matching this IR emitter LED with another IR receiver on the other side Figure 3 26 shows the connection of IR emitter LED to the FPGA Table 3 19 shows the pin assignment of IR emitter LED to the FPGA DE1 SoC User Manual 37 www terasic com asic April 2 2015 www terasic com PROG M VCC3P3 IR Emitter LED IRDA TXD N VAN S B4AN HE8050G Cyclone v Soc Figure 3 26 Connection between the FPGA and IR emitter LED Table 3 19 Pin Assignment of IR Emitter LED E Signal Name FPGA Pin No Description vO Standard IRDA TXD PIN AB30 IR Emitter 133V 3 6 10 SDRAM Memory The board features 64MB of SDRAM with a single 64MB 32Mx16 SDRAM chip The chip consists of 16 bi
97. ux Frame Buffer Project The DEI SoC Linux Frame Buffer Project is a example that a VGA monitor is utilized as a standard output interface for the linux operate system The Quartus II project is located at this path Demonstrations SOC FPGA DEI1 SOC Linux FB The soc system rbf file in the project is used for configuring FPGA through HPS The rbf file is converted form DEI SOC Linux FB sof by clicking the sof to rbf bat The project is adopted for the following demonstrations DE1 SoC User Manual 103 www terasic com Tijasic April 2 2015 www terasic com UNIVERSITY PROGRAM e DEI SoC Linux Console with framebuffer e DEI SoCLXDE with Desktop e DEI SoC Ubuntu Desktop The SD image file for the demonstrations above can be downloaded in the design resources for DEI SoC at Terasic website These examples provide a GUI environment for further developing for the users For example a QT application can run on the system AI InunumHnmH nian HHH titt HHHHHHH nununudud HHH uu HH tt tt tt III i HHHH un H nun HHHH Hth HHH HHHH H nuum LIII III tt tt tt HHH HHHH HHHHH n uu nana tt tt tt i HHH H HHHH HHHH HHRHHHHHH HH HH ekk da ah Ih th H1 OR AP H3 unuk HHHH HHHHHH n bite HHHH RHR H Iititititititititi titi tt ting tt n IE LE LE LI LN LE REAL AR AL AT nti HH HH AT LP LL IG AK AE IP HEH HE HEHEHHELHEHEHEHEHEHE LE HP SE Ah hh HA IA YA HEHEHEHHEHHHHHELHHHELHEEHEHELHEHEHEHEHELHELHEUA ot Figure 7 5 Screenshot of DE1 So
98. www terasic com Tiasic April 2 2015 www terasic com pou depressed pou released Before pes TPT EBENEN Schmitt Trigger Debounced Figure 3 15 Switch debouncing There are ten slide switches connected to the FPGA as shown in Figure 3 16 These switches are not debounced and to be used as level sensitive data inputs to a circuit Each switch is connected directly and individually to the FPGA When the switch is set to the DOWN position towards the edge of the board it generates a low logic level to the FPGA When the switch is set to the UP position a high logic level is generated to the FPGA JA DTE RYAN Cyclone V SoC fasal ato AC9 Ie 1 AD11 TIT AC12 AB 12 Logic 1 1311111 SW9 SW8 SW SW6 SW5 SW4 SW3 SW2 SW1 i Logic 0 Figure 3 16 Connections between the slide switches and the Cyclone V SoC FPGA There are also ten user controllable LEDs connected to the FPGA Each LED is driven directly and individually by the Cyclone V SoC FPGA driving its associated pin to a high logic level or low asic DE1 SoC User Manual 24 WWW terasic com kidd asic Apr i 2 2015 JAN DTE RYA UNIVERSITY PROGRAM level to turn the LED on or off respectively Figure 3 17 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 6 Table 3 7 and Table 3 8 list the pin assignment of user push buttons switches and LEDs LEDO LEDO PIN V16 gt EE icr LEDI M LED LED2 SNO LLEDS LED3
99. yboard and mouse on the DEI SoC board simultaneously by a PS 2 Y Cable as shown in Figure 3 29 Instructions on how to use PS 2 mouse and or keyboard can be found on various educational websites The pin assignment associated to this interface 1s shown in Table 3 21 Q Note If users connect only one PS 2 equipment the PS 2 signals connected to the FPGA I O should be PS2 CLK and PS2 DAT www terasic com DE1 SoC User Manual 40 TijasiC April 2 2015 www terasic com ADT PS2 CLK Apo 4 92 CL2 JA D S RYAN e Cyclone v Soc AES PS2 DAT2 ABEL PS2 DAT Figure 3 28 Connections between the FPGA and PS 2 C Figure 3 29 Y Cable for using keyboard and mouse simultaneously Table 3 21 Pin Assignment of PS 2 Signal Name FPGA Pin No Description VO Standard PS2 CLK PIN AD7 PS 2 Clock 3 3V PS2 DAT PIN AE7 PS 2 Data PS2 CLK2 PIN AD9 PS 2 Clock reserved for second PS 2 device 3 3V PS2 DAT2 PIN AE PS 2 Data reserved for second PS 2 device DE1 SoC User Manual 4 www terasic com Cijasic April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM 3 6 12 A D Converter and 2x5 Header The DEI SoC has an analog to digital converter AD7928 which features lower power eight channel CMOS 12 bit This ADC offers conversion throughput rate up to IMSPS The analog input range for all input channels can be 0 V to 2 5 V or 0 V to 5V depending on the RANGE bit in the control register It can be configu

DE1-SoC User Manual 1 www.terasic.com April 2, 2015

Contents

Download Pdf Manuals

Related Search

Related Contents