Mixed-Language Simulation with Lattice IP Designs Using Active
Contents
1. Target HDL lt lt OK C EDIF A C Verilog Cancel VHDL Caution Changing the target HDL language will result with an unrecoverable loss of some data specific for the current output format Click on OK to complete the change Generate the VHDL Wrapper by clicking on the Generate HDL Code icon blue logic symbol blue lines and black connector in the BDE Edit toolbar Click on the View HDL Code icon black glasses and blue lines to view the generated VHDL wrapper The Text Edit screen appears with the VHDL wrapper containing the Entity Architecture pair component declara tion and component instantiation as shown in Figure 29 19 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 29 Design Environment with VHDL Wrapper Displayed in Text Edit Window File Edt Search Wew Workenece Deap Simulation Took Window Heip ate me x je e Rl eum es POR Sar On oO Fees lem eo bana Ble asses ie o MAE Een m e mle EOE EE ie Workspace ddr _sdram_best 1 designis Design wnat h sada F ddr sdram_eval ia library IEEE Hae iadd Mew Eila 22 use IEEE std logic 1164 allj HE ddr adam evada 23 Brea T ddr adam eval bde Kgl add Mew Library SY ddr_sdrarn_eval library gt Pope rat z6 entity ddr sdram eval is hh All Werilg 2a port E foot 30 burst term in STD LOGIC hal grad dd adam 3i clk in in STD LOGIC 0 dr2. Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Ensure Automatically add new files to design is selected Click on Save to save the file The new VHDL wrapper ddr_sdram_eval vhd now appears in the Files tab of the Design Browser as shown in Figure 31 Figure 31 Design Browser Window Displaying VHDL Wrapper Pee cae CRETE x 7 ae Ar da I f z i ee S Sees n ad la anaa Bett eceben i ENERE HITI a ete one ORAS sie SOP eee Gjtest_mem_ctrl X ol Unsorted En Workspace ddr_sdram_test 1 design s Hyj ddr_sdram_eval fey ddr_sdram_eval do 4 ddr_sdram_eval bde E9 ddr_sdram_eval vhd gS Add New Library i ddr_sdram_eval library Multiple Linit All Verilag froot oq d_ddr_sdram ddr 1 bidi _dgs anl ib_ddr_sdram bidi_ cell data_valid_macrol cal_dvgen_ddr_sdram data valid _macro2 ddr_sdram ddr_dm_io ddr_data_io ddr_dgs_io ddr_sdram_mem_top ddr_sdram_mem_io_top af E Structure amp y Resources Compile the new VHDL Wrapper by left clicking on ddr_sdram_eval vhd to select it Right click on ddr_sdram_eval vhd Left click on Compile to run the compiler Active HDL compiles the VHDL wrapper and adds the Entity Architecture pair to the ddr_sdram_eval library for use by the simulator The Design Browser s Files tab now appears as shown in Figure 32 21 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs
3. attice Mixed Language Simulation with sraa aa semiconductor Lattice IP Designs Using Active HDL u a u u Corporation February 2007 Technical Note TN1146 Introduction Lattice provides pre tested reusable functions that can be easily integrated into designs thereby allowing the designer to focus on their unique system architecture These Intellectual Property IP cores eliminate the need to recreate many industry standard functions These IP Cores are optimized for Lattice Field Programmable Gate Array FPGA architectures which results in fast compact cores that utilize the latest Lattice architectures to their fullest The IPexpress design flow enables users to fully parameterize IP in real time IPexpress generates the IP in the Verilog hardware description language HDL The designer can then instantiate the user configured IP and com plete the design process including simulation and bitstream generation For those designers who prefer a VHDL environment for simulation the use of a single kernel mixed language simulator with Lattice FPGA device library support is required EDA tools such as ModelSim from Mentor Graphics and Active HDL from Aldec provide this feature Verilog Simulation Flow Lattice IP cores are distributed using an obfuscated Verilog RTL simulation model and an encrypted Verilog gate level model In Verilog based designs the IP cores are directly instantiated in the top level of the design as mod
4. Listings Verilog Core Top Level Module module ddr _ sdram mem top Clock and reset clk_in rst_n Mixed Language Simulation with Lattice IP Designs Using Active HDL System Clock System reset Inputs signals from the User Interface cmd addr cmd valid init start write data data mask Command for controller Address for Rd Wr Command Valid Starts the Iitialization Data to be written Data Mask User Interface Output signals cmd rdy init done data_rdy read data read data valid k clk Ready for the new Command Initialization is done Ready for more Write data Read data to the User Read Data Valid Bi directional databus to external memory em ddr data em ddr dqs Data to the memory Data_ Strobes Output to External memory SDRAM Address controls em ddr clk 14 em ddr clk_n em ddr cke em ddr ras n em ddr _cas_n em ddr we_n em ddr cs_ n burst term em ddr dm em ddr ba em ddr addr User Inputs 3 0 ADDR _WIDTH 1 0 and clock DDR1 DDR2 clock Inverted DDR1 DDR2 clock Clock Enable Row address strobe Column Address Strobe Write Enable Chip select Burst Termination Data mask Bank Address Row or Collumn Address clk_ in rst n cmd addr cmd valid init start 23 input input output output output output output output
5. Macro File File Name ddr _ sdram eval do compile vlog libext v y S DSN models mem incdir SDSN testbench tests ecp incdir SDSN src params incdirt DSN models mem SDSN src params ddr_ sdram mem params v fa SDSN models ecp pio dvalid gen v SDSN models ecp ddr data_io v SDSN models ecp ddr dm _io v SDSN models ecp ddr dqs io v SDSN models ecp kbar clk pll v SDSN models ecp pmi_ distributed dpram v SDSN ddr_sdram beh v SDSN models ecp ddr_ sdram mem io top v SDSN srce rtl1 top ecp ddr_sdram mem top v SDSN testbench top ecp odt watchdog v SDSN testbench top ecp monitor v his N SDSN testbench top ecp test mem ctrl v define NO DEBUG ECP vcom src rtl top ecp ddr_sdram_mem core top vhd run the simulation vsim L ovi_ecp ddr sdram eval test mem ctrl 1 ddr_sdram eval log view wave onerror resume 12 Lattice Semiconductor Mixed Language Simulation with Lattice IP Designs Using Active HDL quiet WaveActivateNextPane 0 add wave divider Global Signals noupdate format Logic test mem ctrl Ul_ ddr sdram mem top clk in noupdate format Logic test mem ctr1 Ul1 ddr sdram mem top rst n divider Memory Inte
6. Using Active HDL Figure 32 Design Browser s Files Tab with VHDL AARRE and Entity Architecture Pair Added miaa Sot a st an Brows ce a g EF eee Ree Tat Eo ES eae ies Sea RS ae eed ea 2 E See E T t reo Deena ao N atest_mem_ctr O Unsorted FSi Workspace ddr_sdram_test 1 design s l ddr_sdram_eval a Add New File 33 ddr_sdram_eval do Eh ddr_sdram_eval vhd as Add New Library ddr_sdram_eval library i Multiple Linit ddr_sdram_eval ddr_sdrarm_eval i All Verilag G root Q 2a462e0_ddr_sdram G ddri Gy bidi_dqs Q ani881b_ddr_sdram Q bidi_cell Q data_valid_macrot G cal_dvgen_ddr_sdram M data_valid_macroz Gy ddr_sdram M ddr_dm_io Cy ddr_data io Gy ddr_das_io Gy ddr_sdram_mem_io_top A structure iy Resources Summary The previous steps have verified the integrity of the Lattice Pexpress DDR SDRAM Controller 6 2 core and created VHDL top level wrappers for instantiation of the core into the user s design As Lattice does not package a VHDL test bench with the IP core the user must create a VHDL testbench for simulation of the core using the new wrap pers Optionally the user may instantiate the core into their VHDL design and simulate the core as part of the over all design References Refer to the ModelSim SE User s Manual Chapter 9 Mixed Language Simulation and Chapter 18 Signal Spy for fur ther information 22 Lattice Semiconductor HDL Source
7. out STD LOGIC VECTOR 0 downto 0 em ddr dm out STD LOGIC VECTOR 3 downto 0 em ddr ras n out STD LOGIC em ddr wen out STD LOGIC init done out STD LOGIC k clk out STD LOGIC read data out STD LOGIC VECTOR 63 downto 0 read data valid out STD LOGIC em ddr data inout STD LOGIC VECTOR 31 downto 0 em ddr_dqs inout STD LOGIC VECTOR 3 downto 0 7 end component 25 Lattice Semiconductor begin Ul 7 end ddr_sdram eval Component instantiations ddr sdram mem top port map addr burst _term clk _in cmd cmd rdy cmd valid data_mask data rdy em ddr addr em ddr ba em ddr cas n em ddr _ cke em ddr clk em ddr clk n em ddr_cs n em ddr data em ddr dm em ddr dqs em ddr ras n em ddr we n init done init start k clk read data read data valid rst_n write data addr burst term clk_ in cmd cmd rdy cmd valid data _ mask data rdy em ddr addr em ddr ba em ddr _cas_n em ddr _ cke em ddr clk em ddr _clk_n em ddr_cs n em ddr data em ddr dm em ddr dqs em ddr ras n em ddr wen init done init start k clk read data read data valid rst_n write data Technical Support Assistance 1 800 LATTICE North America 1 503 268 8001 Outside North America techsupport latticesemi com Hotline e mail Internet www latticesemi com Revision History Version Mixed Language Simulation with Lattice IP Designs Using Active
8. select it 16 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL The Symbols Toolbox now appears as shown in Figure 23 Figure 23 Symbols Toolbox window with ddr_sdram_mem_top Selected eatizel ddr _sdram i nsasssas Settee ee tier eteret er i AA Taasan Fe Hod Bad A TETEE od el SI n Settee rie tert ie gq48d_ddr sdram i icfafSf_ddr_sdram aa jr13d50_ddr_sdram kbar_clk_pll aan i enea Left click on the ddr_sdram_mem_top symbol icon Drag and drop it into the BDE Edit window The Design Environment Screen now appears as shown in Figure 24 Figure 24 Design Environment Screen with ddr_sdram_mem_top Symbol Added to the BDE Edit Window ex alae SIE mbols Toolbox F dd _scrom_mem_j_too G orio dt sdam G okadi GI mm d miha 0 ri3d50_dd_scramn G xfs dh soon k s kpl G tas dd shan 0 pri dattod dran reg Q pri datrited_ dram 1 KERNEL test nem ctri 243162 000 ns INFO Selecting BANK 2 KERNEL test mem ctrl 244026 000 ns INFO Selecting BANK J KERNEL test_memictri 244602 000 na INFO Bank Nanagewent Section is DONE RUNTIME RUNTINE_OO7O testcase v 462 stop called KERNEL Tipe 245803 ns Iteration O TOP instance Process AINITIAL 44_29 gt s KEPNEL stopped at delta O at time 245808 ns gt Cr i Use the tools provided on the BDE
9. 7 2 3cript etartup do Warning Your license vill expire on Sun dul 01i 07 53 59 2007 a ao i ao gt Console x Emors p Warnings M Find Click on Create New Workspace if not already selected Click on OK to continue The New Workspace screen appears as shown in Figure 4 Figure 4 New Workspace Screen New Workspace Zz S ee Tee ee Specify basic information about the new workspace Type the workspace name Select the location of the workspace folder c Stools active hdl 7 2 my_designs M Add New Design to Workspace Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Enter ddr_sdram_test in the workspace name text entry box Use the Browse button to select the location of the workspace folder Click on Browse The Browse for Folder screen appears as shown in Figure 5 Figure 5 Browse for Folder Screen ax Select new workspace s parent directory amp _ Dat C denali Drivers 7 ete a Evita H O Flows H IP CORE C License pi H O MINGW H E My_Designs __ Samples _72 _ tutorials xi IA MetSetun OK Cancel Navigate to the directory C DDR_ML_Example ddr_p_eval ddr_sdram sim aldec The Browse for Folder screen is now as shown in Figure 6 Figure 6 Browse for Folder Screen with Workspace Directory Selected Browse for Folder a x Select new workspace s parent directory J C
10. Edit toolbar to add signals buses ports and names to the Block Diagram 17 Lattice Semiconductor Mixed Language Simulation with Lattice IP Designs Using Active HDL After additions the Block Diagram Editor sheet now appears as shown in Figure 25 Figure 25 Block Diagram Editor Widow with Symbol and Ports Connected and Named Bo 15 iE ml A addii 0E a burst termi i ES Eon emd dit pe cmd vali ci R data_mask 0 i imt starti i raton i write data53 MNE a La i 2 ot a i Fi H 1 Ti 4s 40 55 W addr d i Horst herm cola RY Sa F data mly ok in Pea mei REA a de LD EE 4 gs EAS nae han se SAL o wdd Ba D pai ena eee sian ik E A oD iman nemi dola masi i UA aa EAn Eaa in abari F rat_ ni wee dalsie ao timid iagi eae Pht Weve wa am ted on OT a 7 ime of ee der sdram mem top C ALDEC Inc 2260 Corporate Circle Bs Crm _ nti datr mip am dee akini 20 em dar batini am Gor Ces em ddr cero em ddr crit em dur cle ni0 am ddir cs nii 0j am ddr dabii ti am dee dma g am oor daaa 0 za gar racer Win E e nit_done tiu mai diota 0 mad dasta walid al Henderson NV 89074 BD BS 5 S EE leon E gt cmd_rdy data ray A Den ddr add ia iii Derdo ba tuj Bem dd casn Derm _ddr_cke 0 0 Dem di ean gt wem ddr cik nit 0 Dem ddr cs nill Sem_ddr_data 31 0 Dern_der_den 3 0 Serem_ddr_des 30 Wen _d
11. HDL Change Summary February 2007 Initial release 26
12. _SPI_Slave H cyalNs 5 C cygwin A C DDR_ML_Example N BA ddr_p_eval a ddr_sdram 2 impl B sim J aldec C modelsim AHS sre w models E 9 testhench OK Cancel Click on OK to continue Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL The New Workspace screen is now show as shown in Figure 7 Figure 7 New Workspace Screen with Required Information Entered New Specify basic information about the new workspace Type the workspace name ddr_sdram_test Select the location of the workspace folder LNDDR_ML_Example lt ddrp_eval ddr_sdrarm sin ald Browse IM Add New Design to Workspace OK Cancel Click OK to continue The New Design Wizard screen appears as shown in Figure 8 Figure 8 New Design Wizard Screen New Design Wizard E x How would you like to create Design Resources Create an Empty Design C Create an Empty Design with Design Flow S C Add existing Resource Files E m C Import a Design from Active CAD C Greate New Workspace P Add Design to Curent Workspace lt Back Next gt Cancel Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Click on Next to continue creating an Empty Design The Property Page screen appears as shown in Figure 9 Figure 9 Property Page Screen Property Page x Specily additional information about the new desi
13. ame later on Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Enter ddr_sdram_eval in the design name text entry box Note that ddr_sdram_eval is also automatically entered into the default working library text box The New Design Wizard screen is now as shown in Figure 12 Figure 12 New Design Wizard Screen with Information Entered New Design Wizard x Specify basic information about the new design Type the design name ddr_sdram_eval Select the location of the design folder C DDR_ML_Example ddr_p_evalddr_sdram eim valdec ddr_sdram_test Browse The name of the default working library of the design ddr _sdram_eval The name specified here will be used as the file name for the library files and as the logical name of the ibrar rou can change the logical name later on Click on Next to continue The New Design Wizard screen is now as shown in Figure 13 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 13 New Design Wizard Screen with Information Entry Completed New Design Wizard The new design will have the following specifications Design name ddr_sdram_eval C ddt_p_eval ddr_sdram sim aldec ddr_sdram_test Compile source files after creation Click on Finish to create the new design The Active HDL Design Environment screen now appears as shown in Figure 14 Figure 14 Act
14. dr_ras_n Hem ddr ween init dons k clk Dresd data30 read date valid The Design Verification Company Save the Block Diagram by clicking on File gt Save A Save As screen now appears Enter ddr_sdram_ eval as the new file name The Save As screen will appear as shown in Figure 26 Figure 26 Save As Screen with File Name Entered 2x Save in Sy sic e ce ea amp ddr_sdram_eval do History i Desktop T Z i hy Computer a E i F My Network P File name Save as type IV Automatically add new files to design ddr_sdram_eval ta Block Diagram File The next step changes the HDL language selection from Verilog to VHDL 18 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Left click on Design gt Change Target HDL The Change Target HDL for Block Diagrams screen appears as shown in Figure 27 Figure 27 Change Target HDL for Block Diagram Screen Change Target HDL for Bla cl 21 x Target HDL OK C EDIF Verilog o Cancel C VHDL Caution Changing the target HDL language will result with an unrecoverable loss of some data specific for the current output format Click on the radio button new to VHDL to change the Target HDL The Change Target HDL for Block Diagrams screen appears as shown in Figure 28 Figure 28 Change Target HDL Screen Modified to VHDL
15. ductor with Lattice IP Designs Using Active HDL em ddr ras n out STD LOGIC em ddr wen out STD LOGIC init done out STD LOGIC k clk out STD LOGIC read data valid out STD LOGIC em ddr addr out STD LOGIC VECTOR 12 downto 0 em ddr ba out STD LOGIC VECTOR 1 downto 0 em ddr cke out STD LOGIC VECTOR 0 downto 0 em ddr clk out STD LOGIC VECTOR 0 downto 0 em ddr clk n out STD LOGIC VECTOR 0 downto 0 em ddr_cs n out STD LOGIC VECTOR 0 downto 0 em ddr dm out STD LOGIC VECTOR 3 downto 0 read data out STD LOGIC VECTOR 63 downto 0 em ddr data inout STD LOGIC VECTOR 31 downto 0 em ddr_dqs inout STD LOGIC VECTOR 3 downto 0 end ddr_sdram eval architecture ddr _ sdram eval of ddr sdram eval is Component declarations component ddr sdram mem top port addr in STD LOGIC VECTOR 24 downto 0 burst term in STD LOGIC clk_ in in STD LOGIC cmd in STD LOGIC VECTOR 3 downto 0 cmd valid data_ mask init start in STD LOGIC in STD _ LOGIC _VECTOR 7 downto 0 in STD LOGIC rst i in STD_LOGIC write data in STD LOGIC VECTOR 63 downto 0 cmd rdy out STD LOGIC data rdy out STD LOGIC em ddr addr out STD LOGIC VECTOR 12 downto 0 em ddr ba out STD LOGIC VECTOR 1 downto 0 em ddr cas _ n out STD LOGIC em ddr cke out STD LOGIC VECTOR 0 downto 0 em ddr clk out STD LOGIC VECTOR 0 downto 0 em ddr clk n out STD LOGIC VECTOR 0 downto 0 em ddr_cs n
16. eo fe Jesigi Booo EE EA LCE WMA EAN Aa a Se a ea at oes lalllll Gishal Signali p i e a best 1 Goateatsd bin i T der siram _eval aR Abd Mews Fila GD dd siam avada maii Add New Library Ee am dd ck nn 1 Ei hirsdan eva library Ee em dicke z H endd ede oo N E l Ee em dd ba 0 CX EEE EEEE EELEE EEC HEN He em dd dia EOE et E ee a ee z H pm odd dar a Bi em dd dn C 0 a em ddan ee 1 D mika i am ae gi j am di can m o om dh wen Ee am dd cin 4 H FERNEL tear men ctrl 243162 000 na INFO Selecting BANK 238 RERMEL test Mam trl t 244026 000 na INFO Selecting DANE 3 z KERNEL teat_mem erri 244602 000 na INFO Bank Management Section is DONE 7 E BUNTIBE RUNTIBE 0070 testcase Y 462 stop called KERNEL Time 245803 na Iteration D TOP instance Procesa NINITIAL 44_29 s KERNEL stopped at delta O ar time 245508 ns E gt E Console _ C es 4 The user can now verify the functionality of the IP core Click on the sign next to the ddr_sdram_eval library entry in the Design Browser window The Active HDL Design Environment screen now appears as shown in Figure 18 Figure 18 Design Browser Screen with ddr_sdram_eval Library Expanded Ggtest_mem_ctrl Fi Workspace ddr_sdram_test 1 design s Hgs ddr_sdram_eval ax Add New File 3 ddr_sdram_eval do gX Add New Lib
17. express tool to install the DDR SDRAM Controller v 6 2 in the direc tory C DDR_ML_Example e The targeted file name is ddr_sdram e The targeted device is the LFECP33E 4F484C e The user has already installed Aldec Active HDL 7 2 PE in the directory C Active HDL 7 2 Create the directory C DDR_ML_Example ddr_p_eval ddr_sdram sim aldec using Windows Explorer Launch Active HDL Click on Start gt Programs gt Active HDL 7 2 The Active HDL License Configuration screen appears as shown in Figure 2 Figure 2 Active HDL License Configuration Screen License Configuration Select one of the Active HDL product configurations and click Next gt Reserve simulation features at startup Simulation features For more details click license information License information l Do not display this dialog again Cancel Click on Next to launch Active HDL The Active HDL Getting Started screen appears as shown in Figure 3 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 3 Active HDL Getting Started Screen gt Active HDL 7 2 design not loaded Ele Edt Search Yew Workspace Design Simulation Tools Widow Hels Se G H cs a ESF sok ear OR e 2 2 2 we woe Bem 4 Getting Started a C Open ering korip e E a Create new workipace I Akey open last workspace I Welcome to Actave HDL of This message wast printed from macro file C Tools Active HDL
18. gn Design Language lt lt Block Diagram Configuration Default HDL Language Default HDL Language VHDL Target Technology Vendor Notdefned Technology Not defined lt Back Next gt Cancel Using the drop down list for the Default HDL Language select VERILOG Using the drop down list for the Vendor select Lattice Using the drop down list for the Technology select ECP The Property Page screen is now as shown in Figure 10 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 10 Property Page with Information Entered Specify additional information about the new design Design Language Block Diagram Configuration Defaut HDL Language Default HDL Language VERILOG Target Technology Vendor Lattice st Technology ECP it lt Back Next gt Cancel Click on Next to continue The New Design Wizard screen is now as shown in Figure 11 Figure 11 New Design Wizard Screen with Design Folder Location Selected xj Specify basic information about the new design Type the design name er o o o Select the locaton of the design tolder CAQDDR_ML_Example ddr_p eval ddr_sdram simsaldec ddr_sdram_test The name of the default working library of the design The name specified here will be used as the file name for the library files and as the logical name of the library You can change the logical n
19. i 32 em valid in STD LOGIC G bidi dgs 33 init start in STD LOGIC G anil der_sdram 34 zat n in STD LOGIC 0 bidel Tps addr in STD LOGIC VECTOR 2 downto C 0J data vaid macrol 36 cmd in STD LOGIC VECTOR dounto LE cal_dvgen_ddr_scham a7 data mask in STD LOGIC VECTOR downto 0 E data valid maroz ae VELte date in STD LOGIC VECTOR S Gevnto oO E dk sdram 39 emi rdy our STD Logie Th dd dm io 40 data_cdy out STD_LOGIC ether libraries declarations LLPESEy DDR _SDRAH_EVAL 0 ddr data io m ddr cas n i out STD LORIC E dr dy io m adr Tas m i out STD Lost 0 dir sdram mam _bop en dic we nm i out STR LOGIC I 4 init_done out STD _LoGIc Fram mem Jo top 5 x cle oun STD LOGIC la erzel de ic sdram ceod data valid out STD LOGIC Save the file to the Lattice IP core source directory Click on File gt Save As and navigate to the directory C DDR_ML_Example ddr_p_eval ddr_sdram src rtl top ecp The Save As screen will appear as shown in Figure 30 Figure 30 File Save As Screen with Source Directory Selected IE Save in ecp E ddr_sdram_ mer top jhd ddr_sdram_mem_top nar History ddr_sdram_mem_ top sym E ddr_sdram_mem_top y Desktop w My Computer ee B tiy Network F File name ddt_sdram_ eval yhd Save Save as type VHBL Source Code File T Cancel V Automatically add new files to design f 20
20. in Figure 21 Figure 21 Design Environment Screen with Symbols Toolbox Window Open Acbive HDL 72 ddr_sdram_test ddr_sdram_eval BlockDiagrami aloj xj ES ae ee ae ee ee o e Hea og EENEN ool e eme im Ens 245800 F o ETETE e eee ar F E ddr_sdram_mem_jo_boo W ertze dd aka E odt_yanchdog W em db width a 0 1250 ddr sdam a rars dr sdram E kear ekpl i iseia dir adam E montor E ntas _do_sdram E pri ritud pran reg Eam I we Gre a neg eS a a E a Ea om AE Gwen R E ol C E o dvald gen D iF Structure iy Resources KERNEL teart mem Ctrl egoibe 000 na INFO Selecting BANK z ii A RERWEL teart mem Ceri 44020 0000 ne INFO Selecting BANK 3 i o E FEPWEL teart mem ctrl 996802 000 ne INFO Bank Keanagement Section is DONE off RUNTIHE RUNTIME 0070 testcase v 462 fstop called off KERNEL Time 245806 na Iteration 0 TOP instance Process AINITIAL 44 29 off KERNEL Stopped at delta O art time 245808 ne H gt B Console 4 Enors p Wamings on fo BRST g In the Symbols Toolbox window left click on the sign next to the Units without symbols label to expand it The Symbols Toolbox now appears as shown in Figure 22 Figure 22 Symbols Toolbox with Units without symbols Label Expanded Scroll down to ddr _sdram mem top and double click to
21. ined In the Design Browser left click on ddr_sdram_eval to select Right click and hover on Add Files to Design Left click to select The Add Files screen appears as shown in Figure 16 Figure 16 Add Files Screen Add Files C DDR_ML_Example ddr_p_eval ddr_sd ram sim aldec ddr_sdram_test dd ajxj History i Desktop hy Computer as ei My Network F oo M Files of type AI Fies 4 x Cancel Open as Auto x F Make local copy Navigate to the CADDR_ML_Example ddr_p_eval ddr_sdram sim modelsim directory Left click on ddr_sdram_eval do to select it 11 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Make sure the Make Local Copy radio button is selected Click on Add to copy the macro file into the ddr_sdram_eval directory Double click on ddr_sdram_eval do in the Design Browser to open it for editing Delete the following lines 1 2 3 and 4 Append DSN to the relative paths defined on lines 8 through 23 Delete the following lines 24 25 26 and 27 Add the following text on lines 24 25 and 26 vsim L ovi_ecp ddr sdram eval test mem ctrl l ddr_sdram_eval log Change quietly to quiet on line 30 Delete noupdate in lines 31 47 and 59 Comment out the following lines 60 through 75 Click on File gt Save The following table details the contents of the ddr_srdam_eval do macro file Table 1 Modified ddr_sdram_eval do
22. ive HDL Design Environment Screen with Workspace Active Gi DR Seah Yen makoen Goo amkan loos won b OOOO a E EAE E E A Ro eo gt m e os a a at il aesan ense a eee ffl dir dram ewal Ghrary i of Desige Design ddr_sdran eval already active 1 Detault Design Language VERTLOG J H DISI Detsule EDIE Language VERILOG i e i DESIG Flow Pamager Mot Defined E Click on the Blue Logic Gate icon on the Standard toolbar to create a new Block Diagram A new Block Diagram Entry sheet appears in the Active HDL Design Environment screen as shown in Figure 15 10 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 15 Active HDL Design Environment Screen with New BDE Sheet Active 1E hed ddr_sdram_best sdr_scdr am_eval Dlockiungearmt j o PArEJ fie Ek Seach yew Workspace peig gmulton Deyan Joe Window bep oo x PSR HO SF SORSSavOW S So Se hm ee Ee wa ee fe rruatin 7 Design Browser nn HB oa QOmAQRQgraa seit s S OR OL La a ia e a e aSo e aoo e aj 45 ap a op of 7p wah i T Workspace ddr_sdram_test 1 design s f ddr_sdeom_eval mv hgh Add Mew Fie i Pgs Add New Library i ddr_sdram_eval library 1 aft F ri x z i _ S b S blockdteg i Denign ddr sdram eval alceady active GH Default Design Language VERILOG a PESTS Default BRE Language VERTLOG DESIGN Flow Manager Mot Def
23. j h A tel et SS ik OS O La HOW 35 40 4 09 55 oo 05 7p 75 BO 6 DA 2H Ow o QHQgaaa D 14 29 25 ap test mem etri G distan 5 nas ROET E event 0 dk da o er gt gt a dd daai s ddr dgs jo O dhsan mem top j RERNE BETE FAG enh kala SOVET irah D dd_scram_mem_jo_top a ee ER Sad Ree slats G ext62e0_de_sdram 0 ok watchdog 0 mem_db_width_32 Q p13450_ddr sdam a D kfefst ddk sdram kdar ck p W netecte ddir siram monitor 0 mas dd _sdram ke pied vies ptavels G pri dstriuted_dpram reg v avs ate AS one ty re O pr detrteted_dpran a at E pio draid oen w ea U a Je DEVS 12 ie j Structure lt gt Resources amp biockdia idr sdram 2waveform e gt KERNEL test mem ctrl 243162 000 ns INFO Selecting BANK 2 KERNEL test mem trl 244026 000 na INFO Selecting BANK 3 s KERNEL test mem ctri 244602 000 ns INFO Bank Management Section is DONE RUNTIME RUNTIME 0070 testcase v 462 fstop called KERNEL Time 245608 na Iteration 0 TOP instance Process INITIAL 44_ 29 KERNEL stopped at deita O at time 245808 no J gt B Console X Eror 7 WS Left click on the yellow logic gate of the BDE Edit toolbar to open the Symbols Toolbox 15 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL The Design Environment will appear as shown
24. mat format format format format format format format format format format Logic test_ mem ctrl Ul_ddr sdram mem top init start Logic test mem ctrl Ul_ddr sdram mem top init done Logic test_mem ctrl Ul_ddr sdram mem top cmd_rdy Logic test mem ctrl Ul_ddr sdram mem top cmd valid Literal test_ mem ctrl Ul_ddr sdram mem top cmd Literal radix hexadecimal test_ mem ctr1 U1 ddr sdram mem top addr Logic test mem ctrl Ul_ ddr sdram mem top data_rdy Literal radix hexadecimal test mem ctr1 U1 ddr sdram mem top write data Literal test_mem ctrl Ul_ddr_sdram mem top data mask Literal radix hexadecimal test_ mem ctrl Ul_ ddr sdram mem top read data Logic test mem ctrl Ul_ddr sdram mem top read data valid divider End of the Core Browser left click on ddr_sdram_eval do to select it Right click and hover over Execute to select Left click to Execute macro The design will now compile elaborate and simulate Left click on the Design Browsers Files tab to select it The Active HDL Design Environment screen now appears as shown in Figure 17 13 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 17 Active HDL Design Environment Screen Actie HOL ft ddr sdram test ide sdram _oval Woveloem Editor L 7 r lgj xd Ela C amp R Sesh yam Wokpan Deson gimen Waton Tose waew HW 2 20 ALEA R EA EA aleme on Bee a Sia asas
25. output output output output Lattice Semiconductor DSIZE 1 0 USER _DM 1 0 User Outputs DSIZE 1 0 DATA WIDTH 1 0 DQS WIDTH 1 0 DDR Outputs DATA WIDTH 8 1 0 CLKO WIDTH 1 0 CLKO WIDTH 1 0 CKE WIDTH 1 0 DDR Bi Directionals Mixed Language Simulation with Lattice IP Designs Using Active HDL write data data _ mask cmd rdy init done data rdy read data read data valid k clk em ddr data em ddr dqs em ddr dm em ddr clk em ddr _clk_n em ddr _cke output output output output CS WIDTH 1 0 em ddr ras _n em ddr cas _n em ddr we n em ddr_cs n DDR Inputs input burst term DDR Output Buses output ROW WIDTH 1 0 output BNK WDTH 1 0 em ddr addr em ddr_ ba VHDL Wrapper Listing Design unit header library IEEE use IEEE std logic 1164 all other libraries declarations library DDR SDRAM EVAL entity ddr _sdram eval is port burst term clk _in cmd valid init start rst_n addr cmd data mask write data cmd rdy data rdy em ddr cas n in STD LOGIC in STD LOGIC in STD LOGIC in STD LOGIC in STD LOGIC in STD LOGIC VECTOR in STD LOGIC VECTOR in STD LOGIC VECTOR in STD LOGIC VECTOR out STD LOGIC out STD LOGIC out STD LOGIC 24 downto 0 3 downto 0 7 downto 0 63 downto 0 Fe ee A I 24 Mixed Language Simulation Lattice Semicon
26. rary ddr_sdram_eval library Multiple Unit All Verilog troot qq4 8d_ddr_sdram ddr 1 bidi_dqs ani881b_ddr_sdram bidi_cell data_valid_macrol cal_dvgen_ddr_sdrarm data_valid_macro2 ddr sdram M al al Gl al a Gl fal al al M Structure Resources Scroll down and left click to select the ddr_sdram_mem_top Verilog module 14 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL The Active HDL Design Environment screen now appears as shown in Figure 19 Figure 19 Design Browser Screen with ddr_sdram_mem_top Verilog Module Selected Design Browser Etest _mem_ctrl ol Unsorted ddr_sdram ddr_drm_io ddr_data_io ddr_dqs_io ddr_sdram_mem_top ddr sdrarm_mem_ io top eat62e0_ddr_sdram odt_watchdog mem_db_width_32 jr13d50_ddr_sdram icFafSF ddr scram kbar _clk_pll nr6ee6e_ddr_sdram oe monitor Eg ntas7f7_ddr_sdram E pmi_distributed_dpram_reg pmi distributed _dpram EJ pio dvalid gen P b l Files Structure cy Resources Click on the Block Diagram Editor tab to expose the Block Diagram sheet The Design Environment will appear as shown in Figure 20 Figure 20 Design Environment Screen with BDE Sheet Exposed Active MDL 7 2 ddr sdram test wide sdram eval BlockDiagramt ajoj x Fle Edt Search yew Workspace Design Simulation Diagram Took Window Help gt P Sa KUM CY POGGEMTOR OS F 9 SS lene oHa m a ae asos i o
27. rface Signals add add add add add add add add add add add add add add add add add add add add add add add add add add add add run wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave wave all In Design noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate format format format format format format format format format format format format Logic test_ mem ctrl Ul_ ddr sdram mem top em ddr clk Logic test_ mem ctrl Ul_ddr_ sdram mem top em ddr clk_n Logic test_ mem ctrl Ul_ddr sdram mem top em ddr cke Literal radix hexadecimal test mem ctrl Ul_ ddr sdram mem top em ddr addr Literal test_mem ctrl Ul_ddr_sdram mem top em ddr ba Literal radix hexadecimal test mem ctrl Ul_ ddr sdram mem top em ddr data Logic test_ mem ctrl Ul_ ddr sdram mem top em ddr dqs Logic test mem ctrl Ul_ddr sdram mem top em ddr dm Logic test mem ctrl Ul_ddr sdram mem top em ddr ras_n Logic test_ mem ctrl Ul_ddr_ sdram mem top em ddr cas_n Logic test_ mem ctrl Ul_ ddr sdram mem top em ddr we n Logic test_ mem ctrl Ul_ ddr sdram mem top em ddr cs_n divider Local Interface Signals noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate noupdate for
28. tered trademarks of their respective holders The specifications and information herein are subject to change without notice www latticesemi com 1 tn1146_01 0 Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Figure 1 Mixed Mode Simulation Flow for IP Express Generated IP Cores Verilog ictal 7 wn Verilog Top Level VHDL Testbench VHDL Top Level VHDL Wrapper Verilog IP Core Verilog IP Core Obfuscated RTL Obfuscated RTL or or Encrypted NL Encrypted NL Verilog Checker VHDL Checker IP Core Correct No No Yes Yes No Examples The example below illustrates a VHDL instantiation of a Lattice DDR Verilog core generated by IPexpress The IP core can be created and simulated in the Active HDL environment The following examples assume that the user is experienced in using the isoLEVER IPexpress and Active HDL tool flows to implement a Lattice Semiconductor IP It also assumes that the user has used Pexpress to download and install the Lattice Semiconductor DDR SDRAM Controller v6 2 in the directory C DDR_ML_Example Mixed Language Simulation Lattice Semiconductor with Lattice IP Designs Using Active HDL Using Active HDL to Instantiate a Verilog RTL Design Into a VHDL Project This example assumes the following e The user has installed Lattice isoLEVER 6 1 SP1 in the directory C ispTOOLS6_1 e The user has already utilized the Lattice P
29. ules A Verilog testbench is provided for all Lattice IPs The testbench is used to verify the correct operation of the IP prior to use in a design Mixed Language Simulation Flow lf the FPGA application is being developed in VHDL the IP must be instantiated as a component The entire FPGA application can then be simulated as though the IP were a VDHL design This process is shown in Figure 1 Once the core has been generated by IPexpress a VHDL wrapper must be created for instantiating the obfuscated Verilog RTL simulation model In Active HDL a designer creates a Entity Architecture pair complete with the com ponent declaration and component instantiation using the Block Diagram Editor Tool This tool reads in the Verilog top level module port list and creates a symbol The designer then connects I O ports and signals to the symbol After selecting VHDL as the target language the Entity Architecture pair is push button generated Entity Architec ture pair and instantiates the component within to create the VHDL wrapper The newly created VHDL wrapper can then be instantiated in a VHDL testbench or in a top level VHDL design The design may now be compiled for sim ulation using vcom for the VHDL design units and vlog for the Verilog modules 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or regis
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