User`s Manual - Avago Technologies
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1. ACPL 337 LVAGO Isolated IGBT Gate Driver Evaluation board TECHNOLOGIES User s Manual Quick Start Visual inspection is needed to ensure that the evaluation board is received in good condition Default connections of the evaluation board are as shown see Figure 1 1 UVLO Fault e Q1 Bipolar Buffer Driver Q2 Miller Clamp Bipolar and Q3 IGBT are not mounted An actual IGBT should be mounted at Q3 for TO 247 package or connected to the driver board through short wire connections from the holes provided at Q3 CON3 is provided to allow for positive supply Vcc2 and negative supply Vee2 with respect to Ve marked as E which is connected to emitter pin of the IGBT J1 jumper is shorted by default to connect the output to the Gate pin of the IGBT through gate resistors R6 10 Q amp R7 0 Q R9 R10 and Q1 provisions for buffer driver are not mounted by default These components will be needed if more than 4 A of gate drive current is required J1 must be removed while R7 must then be shorted to accommodate this Similarly Q2 is not mounted by default This component should be mounted however if Miller Clamp current of more than 2 A is required CON2 and J2 are shorted by default to allow for a single input PWM signal at Vin pin 2 of CON1 to drive the LED of ACPL 337J If a separate LED drive signal across R3 and R4 is required then CON2 and J2 if R4 cannot be grounded to Gnd m2. LUATION BOARD ucc2 E UVEE2 REV 1 0 OLJUNE12 D j CON1 RS 2431d GIGHHOAT Q9 Figure 5 Top and bottom views of ACPL 337J evaluation board DEFOSX ID Using the Board The evaluation board is easily prepared for use Only minor preparations just by soldering cables for DC supplies input PWM amp Fault UVLO feedback signals proper cables for HV HV high voltage bus and load connections are re quired The evaluation board is having a default connection as shown in Table1 when shipped to customer Customer is free to select a different LED driving schemes and whether negative supply is used as shown in the Table Table 1 LED is Vec2 VEE2 No driven by CON2 Kca 30 V maximum Ve J1 J2 Remarks 1 VLEDDRV S c 5V 15V 30V OV 15V OV s c s c Default External External External 3 external supplies needed for Vcca1 Vcc2 and VEE2 2 VLEDDRV S C 5 V 15V 30V s c s c 1 Simplest External External OV 2 external supplies needed for Vcc amp Vcc2 3 Micro open 5V 15V 30V OV 15V OV s c s c LED s driven externally controller External External External 3 external supplies needed for Vcc1 external Vcc2a amp VcC2b 4 Micro open 5V 15V 30V s c sc 1 LED s driven externally controller External External OV 2 external supplies needed for Vcc amp external Vcc2 Notes 1 Whether J2 can be shorted depends on the drive signals for connection to LED and LED from the Microcontroller 2 Since Miller Clamp
3. T 330pF 330pF P nH 7 ANODE eo Figure 3 Schematics of the ACPL 337 evaluation board Via Vout Vctamp Vee2 nm Not Mounted Practical Connections of the Evaluation board Using Power MOSFET for Actual Inverter Test 1 2 5 Microcontroller Solder an actual IGBT at Q3 by following the pins marked as G gate C collector and E emitter Connect a 5V DC supply DC supply 1 across Vcc and GND terminals of CON1 Connect another DC supply DC Supply 2 of 15V across Vcc2 Vcc2 pin and Ve E pin terminals of CON3 Connect a third DC supply DC Supply 3 of 5V typical or 15V max across Vge2 Vee2 pin and Ve E pin terminals of CON3 Maximum voltage across Vcc2 and Veg is 30 V These two DC power supplies must be isolated from DC Supply 1 Connect the PWM output signals meant to drive the IGBT from microcontroller to input signals at IN and Gnd pins of CON1 Connect also the UVLO and Fault from CON1 to the same microcontroller at designated feedback pins Use a multi channel Digital Oscilloscope to capture the waveforms at the following points a Input PWM signal at IN pin CON1 with reference to w r t Gnd b Vg representing the gate drive voltage of ACPL 337J U1 at G gate pin of Q3 w r t E emitter pin Monitoring of this signal must be done through a HV differential probe c Desat signal at pin 14 of U1 represents the Desat voltage of IGBT s C collector pin during turn on Monitoring
4. age has no chance of going above the turn on threshold level again Figure 8 shows the actual Desat 7 V threshold detection that triggers the Vg output soft shutdown as well as Fault feed back pin voltage is pulled low to inform microcontroller that a fault has been detected 1 5 00 V a 2 p 100v 3 g 50v 2 a p 50v oy OO E ie reece 7 en i VINE e be sa i ce ou S i oS Of 2 Shy i w oy sN bs valez 7 T T e ems x H 1 00 5 a a ll 3 3455400 18 0 thov r Figure 8 Desat Protection amp Fault Feedback Figure 9 shows that the Vcc2 voltage sag below UVLO level between 11 12 V triggers the UVLO and shutdown the output Vg level and recovers after normal Vcc2 voltage recovers above UVLO level between 12 13 V The UVLO pin voltage is also pulled low throughout the same duration to inform the microcontroller that severe Vcc2 level drop has happened EOV SCE 5 00 v Ea 4 p 10 0v Ea E ae ey Vine Vg output atected anvoltage detected Vccz Normal t e feais x H 500 ms n ni 3 3455400 ps of Tf10 13V Figure 9 UVLO Feedback In conclusion with these sophisticated IGBT gate driving and driver protection schemes built in ACPL 337J is well suited for modern IGBT applications such as Motor Control and Voltage inverters For product information and a complete list of distributors please go to o
5. ard is enough to drive an Inverter arm This allows the designer to easily test the performance of gate driver in an actual application solution Operation of the evaluation board requires just the inclusion of acommon 5V DC isolated Supply1 on the input side and two isolated DC supplies on the output side together with a PWM drive signal from the microcontroller Provision is done on the board to allow for the LED to be driven either directly by external 5V PWM 10 kHz signals or the generated LED signal by disconnecting or connecting the shunt post at CON2 respectively By default the LED is driven by the internally generated LED drive signal LEDDRV pin 4 at U1 Once the shunt post at CON2 is removed external PWM signals at 5Vpp 10 kHz can be connected directly to LED and LED pins at CON1 to drive the LED of the optocoupler through the onboard current limiting resistors This provision is to provide the designer flexibility Once the LED is driven by a signal current typically 11 5 mA output at pin 11 is activated with a positive pulse volt age and ready to drive the IGBT s gate through a gate resistor R6 10 Q Assuming that the voltage supply at Vcc2 and Vee w r t Ve or E are 15V and 5V respectively the maximum drive current is limited to 2 A peak Vcc2 VeE Rea If needed Rg can be reduced to accommodate up to 4 A of peak output drive current allowable by the specification But care must be taken to ensure that junction te
6. cross IN and Gnd pins of CON1 to simulate microcontroller output to drive the IGBT 6 Use a multichannel digital oscilloscope to capture the waveforms at the following points a Input PWM signal at IN pin CON1 with reference to w r t Gnd LED signal at LED pin w r t Gnd or LED Note this is a generated LED drive signal from the device ACPL 337J VG representing the gate drive voltage of ACPL 337J U1 at G gate pin of Q3 w r t E emitter pin Desat signal at pin 14 of U1 which represents the Desat voltage of IGBT s C collector pin during turn on Confirm that LED signal is almost identical to IN signal and then switch this channel to monitor the simulated Miller Clamp voltage of IGBT at pin 10 of U1 7 Provision is done on the board to allow for the LED to be driven directly by 5V PWM 10 kHz signals instead of the IN signal by disconnecting the shunt post at CON2 Once the shunt post at CON2 is removed the external PWM signals at 10 kHz 5Vpp can be connected directly to LED and LED pins at CON1 Note Before you proceed to the next tests make sure you remove the jumper wire that was connected in Step 2 Dano DCSupply 2 DC Supply 3 gt Q a pO z ACPL 337J EVALUATION BOARD ucc REV 1 0 OLJUNEI2 E R5 in Figure 2 Simple Simulation Test Setup of Evaluation board Schematics Figure 3 shows the schematics of the evaluation board CON1 O a C3 r Pr i UVLO I he fa 6 FAUL
7. ction For other design criteria for Desat protection refer to the application notes Preventing false turn on by Miller effect Every IGBT used will have a junction capacitance between collector and gate or Miller capacitance Ideally this capaci tance has to be as small as possible but it can never be eliminated This Miller capacitance might allow transient current to flow from collector to gate and causes the gate voltage to rise during gate turn off duration If this sudden surge of gate voltage is higher than the gate threshold voltage usually 2 5V a false IGBT turn on might happen To prevent this the IGBT gate voltage is monitored by connecting it to the Clamp pin 10 of U1 during the turn off dura tion During turn off the gate voltage as monitored is pulled low and it will drop from Vcc2 level to Vgeg2 level As soon as this gate voltage level drops below 2 V w r t Veg2 an internal clamp is activated to shunt the Clamp pin 10 to pin 9 which is at Veg2 level By doing so it ensures that the gate voltage has no chance of getting over 2 V again during the entire IGBT off duration Monitoring of this pin 10 will notice a sudden dip in voltage from 2 V typically to 0 V immedi ately to confirm that the active Miller Clamp is working properly Note As an active Miller clamp is built in to this ACPL 337J device negative supply is not needed and Ve and Vez can be shorted 5 Preventing premature output turn on through the
8. function is built in ve supply for VEE2 can be omitted so VEE2 can be shorted to VE externally Note As the Desat diode s breakdown voltage is rated at 1k V IGBT must be selected with Vces lt 1 kV and maximum HV voltage plus flyback voltage of load inductor must be lt 1 kV Output Measurement A sample of Input signal and various output waveforms are captured and shown in Figure 6 during IGBT gate turn off and turn on instants Default setup connection is used but with Q3 IGBT mounted The IGBT used has a gate capaci tance equivalent to 10 nF It is noticed that during normal working condition the Desat pin voltage is much less than 7 V and no Fault occurs 1 p 50 v Yt 2 10 0 v 3 pf 100v 4 p 20v Dy T ee VIN 41 For the exploded view see Figure 7 T fe eals x H 100ps 9 all 3 2455400 us Tiz4v am Figure 6 ACPL 337J Input and output plus protection signal waveforms On On On O On NF 2 3 p 100 V ar aw i i i i t t t oas x H 20re7 i 38 5000 re aof p ar Figure 7 Exploded view of Active Miller Clamp pin waveform at turn off Figure 7 is the exploded view of the Miller Clamp pin 10 waveform during turn off duration it shows clearly that once the detected Gate voltage drops below 2 V typically the Gate voltage is shunt and clamped to 0 V w r t Vee2 level dur ing the entire turn off duration to ensure that the Gate volt
9. mperature of the device is always below 125 C ACPL 337J is a smart gate driver with many integrated protection features such as a IGBT collector desaturation fault protection against overload as well as short circuit b Preventing false turn on due to Miller current effect and c UVLO to prevent premature output turn on due to insufficient supply voltage Desat Protection For normal loading during IGBT turn on the collector saturation voltage should fall below 5V Vdesat Iconstant Rdesat VF where Vdesat 7V typical protection threshold of Desat voltage lconstant 1 MA of internal constant current source Rdesat 1 kQ of R5 Ve 1V typical of D1 for BYV26E at 1 mA During overload or short circuit the collector saturation voltage is higher than 5 V and the detected voltage at the Desat pin 14 of U1 will be higher than 7 V This will trigger output shutdown output soft shutdown will be initiated and at the same time the Fault feedback pin 6 will be pulled low to inform external microcontroller that there is a Fault happening at the IGBT power switch to turn off the IGBT to protect it from damage So the IGBT should be selected such that its collector saturation voltage during turn on under full load condition is less than 5 V If the collector saturation voltage during full load is too low e g lt 3 V then adding a 2 V Zener between R5 and diode D1 would definitely help to provide proper overload or short circuit prote
10. of this signal must be done through a HV differential probe d Miller Clamp voltage of IGBT at pin 10 of U1 Monitoring of this signal must be done through a HV differential probe Connect C collector pin of the IGBT to HV High Voltage DC Bus through a properly selected Inductive Load Connect E emitter pin of the IGBT to HV High Voltage DC Bus Note It is advised to enable the current limiting function of the HV Power Source supplying the High Voltage DC Bus voltage during this test to protect the Inverter and its drive circuits Maximum voltage allowed across HV and HV is 1 kV for the board DCSupply 3 DCSupply 2 15 5 ACPL 337J z 3 EVALUATION BOARD ucc2 z REU 1 0 GIJUNEI2 H j Gnd g ROn 1e TT f N a Figure 4 Connection of evaluation board in actual applications Application Circuit Description The ACPL 337J is an isolated gate driver that provides gt 4 A output current The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving of IGBT with ratings up to 1000 V 100 W It is also designed to drive different sizes of buffer stage that will make the class of IGBT scalable ACPL 337J provides a single isolation solution suitable for both low power and high power ratings of motor control and inverter applications Each of the ACPL 337J evaluation boards as shown in Figure 5 accommodates an ACPL 337J IC The bo
11. ur web site wWww avagotech com Avago Avago Technologies and the A logo are trademarks of Avago Technologies in the United States and other countries Data subject to change Copyright 2005 2014 Avago Technologies All rights reserved LVe 5 O AV02 4404EN February 6 2014 TECHNOLOGIES
12. use of UVLO When IGBT is allowed to turn on immediately after gate voltage crosses the threshold voltage typically 2 5V the collector emitter junction is operating at the linear region This will cause high voltage built up across the very same junction especially when the load is high The conduction power dissipation load current junction voltage of the device will be very high and it will be damaged if this power is higher than the allowable limit To prevent high power dissipation the designer has to ensure that the turn on of the IGBT is prohibited until the gate voltage has reached a certain level where collector saturation can be reached and usually this calls for a gate voltage to be gt 12 V This is achieved by including a UVLO circuit inside the ACPL 337J device This UVLO circuit monitors the supply voltage at Vcc2 w rt Ve and it will not allow output to be turn on until Vcc2 voltage crosses the UVLO threshold typically 12 3 V The UVLO protection circuit can be checked by varying Vcc2 supply voltage higher than or lower than the UVLO or UVLO threshold voltage respectively When Vcc2 supply voltage is lower than the UVLO threshold the UVLO at pin 6 of U1 should send out a low level w r t Gnd Note As can be seen on the board the isolation circuitry at the far left is easily contained within a small area while adequate spacing is maintained for good voltage isolation and easy assembly ACPL 337J m j conz EVA
13. ust be opened CON1 is provided to allow for the power supply 5V to be connected across Vcc and Gnd TTL signal drive at Vin direct driving of LED plus UVLO and Fault feedback Component Side Solder Side ACPL 337u CON3 cnc ioriod Teee MT Ee on REY 1 0 Cl E gja SBD CON4 ee Te TECH P OLOGIES Gnd E Vin Vcc1 LED LED J2 shorted CON2 shorted J1 shorted Figure 1 Actual ACPL 337J evaluation board showing default connections Once inspection is done the evaluation board can be powered up in seven simple steps as shown in Figure 2 in simula tion mode without the need of actual IGBT Testing IGBT Gate Driver in Simulation Mode 1 Solder a 10 nF capacitor across the Gate and Emitter terminals of Q3 to simulate actual gate capacitance of an IGBT 2 Solder a jumper wire across the Collector and Emitter terminals of Q3 to simulate a turn on saturated Collector voltage of IGBT 3 Connect a 5V DC supply DC supply 1 across Vcc and GND terminals of CON1 4 Connect another DC supply DC Supply 2 of 15 V typical or 30 V maximum across Vcc2 Vcc2 pin and Ve E pin terminals of CON3 Connect a third DC supply DC Supply 3 of 5V typical or 15 V maximum across Veg Vee2 pin and Ve E pin terminals of CON3 Maximum voltage across Vcc and V_eg is 30 V For testing these power supplies can be non isolated 5 Connect a 10 kHz 5 V DC pulse at about 50 duty from a dual output signal generator a
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